mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 G_GNUC_UNUSED static void
 113 break_count (void)
 114 {
 115 }
 116
 117 G_GNUC_UNUSED static gboolean
 118 debug_count (void)
 119 {
 120         static int count = 0;
 121         count ++;
 122
 123         if (count == atoi (getenv ("COUNT"))) {
 124                 break_count ();
 125         }
 126
 127         if (count > atoi (getenv ("COUNT"))) {
 128                 return FALSE;
 129         }
 130
 131         return TRUE;
 132 }
 133
 134 static gboolean
 135 debug_ins_sched (void)
 136 {
 137 #if 0
 138         return debug_count ();
 139 #else
 140         return TRUE;
 141 #endif
 142 }
 143
 144 static gboolean
 145 debug_omit_fp (void)
 146 {
 147 #if 0
 148         return debug_count ();
 149 #else
 150         return TRUE;
 151 #endif
 152 }
 153
 154 static void
 155 ia64_patch (unsigned char* code, gpointer target);
 156
 157 typedef enum {
 158         ArgInIReg,
 159         ArgInFloatReg,
 160         ArgInFloatRegR4,
 161         ArgOnStack,
 162         ArgValuetypeAddrInIReg,
 163         ArgAggregate,
 164         ArgSingleHFA,
 165         ArgDoubleHFA,
 166         ArgNone
 167 } ArgStorage;
 168
 169 typedef enum {
 170         AggregateNormal,
 171         AggregateSingleHFA,
 172         AggregateDoubleHFA
 173 } AggregateType;
 174
 175 typedef struct {
 176         gint16 offset;
 177         gint8  reg;
 178         ArgStorage storage;
 179
 180         /* Only if storage == ArgAggregate */
 181         int nregs, nslots;
 182         AggregateType atype;
 183 } ArgInfo;
 184
 185 typedef struct {
 186         int nargs;
 187         guint32 stack_usage;
 188         guint32 reg_usage;
 189         guint32 freg_usage;
 190         gboolean need_stack_align;
 191         ArgInfo ret;
 192         ArgInfo sig_cookie;
 193         ArgInfo args [1];
 194 } CallInfo;
 195
 196 #define DEBUG(a) if (cfg->verbose_level > 1) a
 197
 198 #define PARAM_REGS 8
 199
 200 static void inline
 201 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = ArgInIReg;
 211                 ainfo->reg = *gr;
 212                 *(gr) += 1;
 213     }
 214 }
 215
 216 #define FLOAT_PARAM_REGS 8
 217
 218 static void inline
 219 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 (*stack_size) += sizeof (gpointer);
 226     }
 227     else {
 228                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 229                 ainfo->reg = 8 + *fr;
 230                 (*fr) += 1;
 231                 (*gr) += 1;
 232     }
 233 }
 234
 235 static void
 236 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 237                gboolean is_return,
 238                guint32 *gr, guint32 *fr, guint32 *stack_size)
 239 {
 240         guint32 size, i;
 241         MonoClass *klass;
 242         MonoMarshalType *info;
 243         gboolean is_hfa = TRUE;
 244         guint32 hfa_type = 0;
 245
 246         klass = mono_class_from_mono_type (type);
 247         if (type->type == MONO_TYPE_TYPEDBYREF)
 248                 size = 3 * sizeof (gpointer);
 249         else if (sig->pinvoke)
 250                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 251         else
 252                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 253
 254         if (!sig->pinvoke || (size == 0)) {
 255                 /* Allways pass in memory */
 256                 ainfo->offset = *stack_size;
 257                 *stack_size += ALIGN_TO (size, 8);
 258                 ainfo->storage = ArgOnStack;
 259
 260                 return;
 261         }
 262
 263         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 264         info = mono_marshal_load_type_info (klass);
 265         g_assert (info);
 266         for (i = 0; i < info->num_fields; ++i) {
 267                 guint32 ftype = info->fields [i].field->type->type;
 268                 if (!(info->fields [i].field->type->byref) &&
 269                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 270                         if (hfa_type == 0)
 271                                 hfa_type = ftype;
 272                         else if (hfa_type != ftype)
 273                                 is_hfa = FALSE;
 274                 }
 275                 else
 276                         is_hfa = FALSE;
 277         }
 278         if (hfa_type == 0)
 279                 is_hfa = FALSE;
 280
 281         ainfo->storage = ArgAggregate;
 282         ainfo->atype = AggregateNormal;
 283
 284         if (is_hfa) {
 285                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 286                 if (is_return) {
 287                         if (info->num_fields <= 8) {
 288                                 ainfo->reg = 8;
 289                                 ainfo->nregs = info->num_fields;
 290                                 ainfo->nslots = ainfo->nregs;
 291                                 return;
 292                         }
 293                         /* Fall through */
 294                 }
 295                 else {
 296                         if ((*fr) + info->num_fields > 8)
 297                                 NOT_IMPLEMENTED;
 298
 299                         ainfo->reg = 8 + (*fr);
 300                         ainfo->nregs = info->num_fields;
 301                         ainfo->nslots = ainfo->nregs;
 302                         (*fr) += info->num_fields;
 303                         if (ainfo->atype == AggregateSingleHFA) {
 304                                 /*
 305                                  * FIXME: Have to keep track of the parameter slot number, which is
 306                                  * not the same as *gr.
 307                                  */
 308                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 309                         } else {
 310                                 (*gr) += info->num_fields;
 311                         }
 312                         return;
 313                 }
 314         }
 315
 316         /* This also handles returning of TypedByRef used by some icalls */
 317         if (is_return) {
 318                 if (size <= 32) {
 319                         ainfo->reg = IA64_R8;
 320                         ainfo->nregs = (size + 7) / 8;
 321                         ainfo->nslots = ainfo->nregs;
 322                         return;
 323                 }
 324                 NOT_IMPLEMENTED;
 325         }
 326
 327         ainfo->reg = (*gr);
 328         ainfo->offset = *stack_size;
 329         ainfo->nslots = (size + 7) / 8;
 330
 331         if (((*gr) + ainfo->nslots) <= 8) {
 332                 /* Fits entirely in registers */
 333                 ainfo->nregs = ainfo->nslots;
 334                 (*gr) += ainfo->nregs;
 335                 return;
 336         }
 337
 338         ainfo->nregs = 8 - (*gr);
 339         (*gr) = 8;
 340         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 341 }
 342
 343 /*
 344  * get_call_info:
 345  *
 346  *  Obtain information about a call according to the calling convention.
 347  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 348  * Gude" document for more information.
 349  */
 350 static CallInfo*
 351 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 352 {
 353         guint32 i, gr, fr;
 354         MonoType *ret_type;
 355         int n = sig->hasthis + sig->param_count;
 356         guint32 stack_size = 0;
 357         CallInfo *cinfo;
 358         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 359
 360         if (mp)
 361                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 362         else
 363                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 364
 365         gr = 0;
 366         fr = 0;
 367
 368         /* return value */
 369         {
 370                 ret_type = mono_type_get_underlying_type (sig->ret);
 371                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 372                 switch (ret_type->type) {
 373                 case MONO_TYPE_BOOLEAN:
 374                 case MONO_TYPE_I1:
 375                 case MONO_TYPE_U1:
 376                 case MONO_TYPE_I2:
 377                 case MONO_TYPE_U2:
 378                 case MONO_TYPE_CHAR:
 379                 case MONO_TYPE_I4:
 380                 case MONO_TYPE_U4:
 381                 case MONO_TYPE_I:
 382                 case MONO_TYPE_U:
 383                 case MONO_TYPE_PTR:
 384                 case MONO_TYPE_FNPTR:
 385                 case MONO_TYPE_CLASS:
 386                 case MONO_TYPE_OBJECT:
 387                 case MONO_TYPE_SZARRAY:
 388                 case MONO_TYPE_ARRAY:
 389                 case MONO_TYPE_STRING:
 390                         cinfo->ret.storage = ArgInIReg;
 391                         cinfo->ret.reg = IA64_R8;
 392                         break;
 393                 case MONO_TYPE_U8:
 394                 case MONO_TYPE_I8:
 395                         cinfo->ret.storage = ArgInIReg;
 396                         cinfo->ret.reg = IA64_R8;
 397                         break;
 398                 case MONO_TYPE_R4:
 399                 case MONO_TYPE_R8:
 400                         cinfo->ret.storage = ArgInFloatReg;
 401                         cinfo->ret.reg = 8;
 402                         break;
 403                 case MONO_TYPE_GENERICINST:
 404                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 405                                 cinfo->ret.storage = ArgInIReg;
 406                                 cinfo->ret.reg = IA64_R8;
 407                                 break;
 408                         }
 409                         /* Fall through */
 410                 case MONO_TYPE_VALUETYPE:
 411                 case MONO_TYPE_TYPEDBYREF: {
 412                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 413
 414                         if (sig->ret->byref) {
 415                                 /* This seems to happen with ldfld wrappers */
 416                                 cinfo->ret.storage = ArgInIReg;
 417                         } else {
 418                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 419                                 if (cinfo->ret.storage == ArgOnStack)
 420                                         /* The caller passes the address where the value is stored */
 421                                         add_general (&gr, &stack_size, &cinfo->ret);
 422                                 if (cinfo->ret.storage == ArgInIReg)
 423                                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 424                         }
 425                         break;
 426                 }
 427                 case MONO_TYPE_VOID:
 428                         cinfo->ret.storage = ArgNone;
 429                         break;
 430                 default:
 431                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 432                 }
 433         }
 434
 435         /*
 436          * IA64 has MONO_ARCH_THIS_AS_FIRST_ARG defined, but we don't need to really pass
 437          * this as first, because this is stored in a non-stacked register by the calling
 438          * sequence.
 439          * FIXME: mono_arch_get_unbox_trampoline () depends on this.
 440          */
 441
 442         /* this */
 443         if (sig->hasthis)
 444                 add_general (&gr, &stack_size, cinfo->args + 0);
 445
 446         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 447                 gr = PARAM_REGS;
 448                 fr = FLOAT_PARAM_REGS;
 449
 450                 /* Emit the signature cookie just before the implicit arguments */
 451                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 452         }
 453
 454         for (i = 0; i < sig->param_count; ++i) {
 455                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 456                 MonoType *ptype;
 457
 458                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 459                         /* We allways pass the sig cookie on the stack for simplicity */
 460                         /*
 461                          * Prevent implicit arguments + the sig cookie from being passed
 462                          * in registers.
 463                          */
 464                         gr = PARAM_REGS;
 465                         fr = FLOAT_PARAM_REGS;
 466
 467                         /* Emit the signature cookie just before the implicit arguments */
 468                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 469                 }
 470
 471                 if (sig->params [i]->byref) {
 472                         add_general (&gr, &stack_size, ainfo);
 473                         continue;
 474                 }
 475                 ptype = mono_type_get_underlying_type (sig->params [i]);
 476                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 477                 switch (ptype->type) {
 478                 case MONO_TYPE_BOOLEAN:
 479                 case MONO_TYPE_I1:
 480                 case MONO_TYPE_U1:
 481                         add_general (&gr, &stack_size, ainfo);
 482                         break;
 483                 case MONO_TYPE_I2:
 484                 case MONO_TYPE_U2:
 485                 case MONO_TYPE_CHAR:
 486                         add_general (&gr, &stack_size, ainfo);
 487                         break;
 488                 case MONO_TYPE_I4:
 489                 case MONO_TYPE_U4:
 490                         add_general (&gr, &stack_size, ainfo);
 491                         break;
 492                 case MONO_TYPE_I:
 493                 case MONO_TYPE_U:
 494                 case MONO_TYPE_PTR:
 495                 case MONO_TYPE_FNPTR:
 496                 case MONO_TYPE_CLASS:
 497                 case MONO_TYPE_OBJECT:
 498                 case MONO_TYPE_STRING:
 499                 case MONO_TYPE_SZARRAY:
 500                 case MONO_TYPE_ARRAY:
 501                         add_general (&gr, &stack_size, ainfo);
 502                         break;
 503                 case MONO_TYPE_GENERICINST:
 504                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 505                                 add_general (&gr, &stack_size, ainfo);
 506                                 break;
 507                         }
 508                         /* Fall through */
 509                 case MONO_TYPE_VALUETYPE:
 510                 case MONO_TYPE_TYPEDBYREF:
 511                         /* FIXME: */
 512                         /* We allways pass valuetypes on the stack */
 513                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 514                         break;
 515                 case MONO_TYPE_U8:
 516                 case MONO_TYPE_I8:
 517                         add_general (&gr, &stack_size, ainfo);
 518                         break;
 519                 case MONO_TYPE_R4:
 520                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 521                         break;
 522                 case MONO_TYPE_R8:
 523                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 524                         break;
 525                 default:
 526                         g_assert_not_reached ();
 527                 }
 528         }
 529
 530         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 531                 gr = PARAM_REGS;
 532                 fr = FLOAT_PARAM_REGS;
 533
 534                 /* Emit the signature cookie just before the implicit arguments */
 535                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 536         }
 537
 538         cinfo->stack_usage = stack_size;
 539         cinfo->reg_usage = gr;
 540         cinfo->freg_usage = fr;
 541         return cinfo;
 542 }
 543
 544 /*
 545  * mono_arch_get_argument_info:
 546  * @csig:  a method signature
 547  * @param_count: the number of parameters to consider
 548  * @arg_info: an array to store the result infos
 549  *
 550  * Gathers information on parameters such as size, alignment and
 551  * padding. arg_info should be large enought to hold param_count + 1 entries.
 552  *
 553  * Returns the size of the argument area on the stack.
 554  */
 555 int
 556 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 557 {
 558         int k;
 559         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 560         guint32 args_size = cinfo->stack_usage;
 561
 562         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 563         if (csig->hasthis) {
 564                 arg_info [0].offset = 0;
 565         }
 566
 567         for (k = 0; k < param_count; k++) {
 568                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 569                 /* FIXME: */
 570                 arg_info [k + 1].size = 0;
 571         }
 572
 573         g_free (cinfo);
 574
 575         return args_size;
 576 }
 577
 578 /*
 579  * Initialize the cpu to execute managed code.
 580  */
 581 void
 582 mono_arch_cpu_init (void)
 583 {
 584 }
 585
 586 /*
 587  * Initialize architecture specific code.
 588  */
 589 void
 590 mono_arch_init (void)
 591 {
 592 }
 593
 594 /*
 595  * Cleanup architecture specific code.
 596  */
 597 void
 598 mono_arch_cleanup (void)
 599 {
 600 }
 601
 602 /*
 603  * This function returns the optimizations supported on this cpu.
 604  */
 605 guint32
 606 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 607 {
 608         *exclude_mask = 0;
 609
 610         return 0;
 611 }
 612
 613 GList *
 614 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 615 {
 616         GList *vars = NULL;
 617         int i;
 618         MonoMethodSignature *sig;
 619         MonoMethodHeader *header;
 620         CallInfo *cinfo;
 621
 622         header = cfg->header;
 623
 624         sig = mono_method_signature (cfg->method);
 625
 626         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 627
 628         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 629                 MonoInst *ins = cfg->args [i];
 630
 631                 ArgInfo *ainfo = &cinfo->args [i];
 632
 633                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 634                         continue;
 635
 636                 if (ainfo->storage == ArgInIReg) {
 637                         /* The input registers are non-volatile */
 638                         ins->opcode = OP_REGVAR;
 639                         ins->dreg = 32 + ainfo->reg;
 640                 }
 641         }
 642
 643         for (i = 0; i < cfg->num_varinfo; i++) {
 644                 MonoInst *ins = cfg->varinfo [i];
 645                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 646
 647                 /* unused vars */
 648                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 649                         continue;
 650
 651                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 652                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 653                         continue;
 654
 655                 if (mono_is_regsize_var (ins->inst_vtype)) {
 656                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 657                         g_assert (i == vmv->idx);
 658                         vars = g_list_prepend (vars, vmv);
 659                 }
 660         }
 661
 662         vars = mono_varlist_sort (cfg, vars, 0);
 663
 664         return vars;
 665 }
 666
 667 static void
 668 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 669 {
 670         CallInfo *cinfo;
 671         guint32 reserved_regs;
 672         MonoMethodHeader *header;
 673
 674         if (cfg->arch.reg_local0 > 0)
 675                 /* Already done */
 676                 return;
 677
 678         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 679
 680         header = cfg->header;
 681
 682         /* Some registers are reserved for use by the prolog/epilog */
 683         reserved_regs = header->num_clauses ? 4 : 3;
 684
 685         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 686                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 687                 /* One registers is needed by instrument_epilog to save the return value */
 688                 reserved_regs ++;
 689                 if (cinfo->reg_usage < 2)
 690                         /* Number of arguments passed to function call in instrument_prolog */
 691                         cinfo->reg_usage = 2;
 692         }
 693
 694         cfg->arch.reg_in0 = 32;
 695         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 696         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 697
 698         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 699         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 700         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 701
 702         /*
 703          * Frames without handlers save sp to fp, frames with handlers save it into
 704          * a dedicated register.
 705          */
 706         if (header->num_clauses)
 707                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 708         else
 709                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 710
 711         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 712                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 713                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 714         }
 715
 716         /*
 717          * Need to allocate at least 2 out register for use by OP_THROW / the system
 718          * exception throwing code.
 719          */
 720         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 721 }
 722
 723 GList *
 724 mono_arch_get_global_int_regs (MonoCompile *cfg)
 725 {
 726         GList *regs = NULL;
 727         int i;
 728
 729         mono_ia64_alloc_stacked_registers (cfg);
 730
 731         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 732                 /* FIXME: regmask */
 733                 g_assert (i < 64);
 734                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 735         }
 736
 737         return regs;
 738 }
 739
 740 /*
 741  * mono_arch_regalloc_cost:
 742  *
 743  *  Return the cost, in number of memory references, of the action of
 744  * allocating the variable VMV into a register during global register
 745  * allocation.
 746  */
 747 guint32
 748 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 749 {
 750         /* FIXME: Increase costs linearly to avoid using all local registers */
 751
 752         return 0;
 753 }
 754
 755 void
 756 mono_arch_allocate_vars (MonoCompile *cfg)
 757 {
 758         MonoMethodSignature *sig;
 759         MonoMethodHeader *header;
 760         MonoInst *inst;
 761         int i, offset;
 762         guint32 locals_stack_size, locals_stack_align;
 763         gint32 *offsets;
 764         CallInfo *cinfo;
 765
 766         header = cfg->header;
 767
 768         sig = mono_method_signature (cfg->method);
 769
 770         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 771
 772         /*
 773          * Determine whenever the frame pointer can be eliminated.
 774          * FIXME: Remove some of the restrictions.
 775          */
 776         cfg->arch.omit_fp = TRUE;
 777
 778         if (!debug_omit_fp ())
 779                 cfg->arch.omit_fp = FALSE;
 780
 781         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 782                 cfg->arch.omit_fp = FALSE;
 783         if (header->num_clauses)
 784                 cfg->arch.omit_fp = FALSE;
 785         if (cfg->param_area)
 786                 cfg->arch.omit_fp = FALSE;
 787         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 788                 cfg->arch.omit_fp = FALSE;
 789         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 790                 cfg->arch.omit_fp = FALSE;
 791         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 792                 ArgInfo *ainfo = &cinfo->args [i];
 793
 794                 if (ainfo->storage == ArgOnStack) {
 795                         /*
 796                          * The stack offset can only be determined when the frame
 797                          * size is known.
 798                          */
 799                         cfg->arch.omit_fp = FALSE;
 800                 }
 801         }
 802
 803         mono_ia64_alloc_stacked_registers (cfg);
 804
 805         /*
 806          * We use the ABI calling conventions for managed code as well.
 807          * Exception: valuetypes are never passed or returned in registers.
 808          */
 809
 810         if (cfg->arch.omit_fp) {
 811                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 812                 cfg->frame_reg = IA64_SP;
 813                 offset = ARGS_OFFSET;
 814         }
 815         else {
 816                 /* Locals are allocated backwards from %fp */
 817                 cfg->frame_reg = cfg->arch.reg_fp;
 818                 offset = 0;
 819         }
 820
 821         if (cfg->method->save_lmf) {
 822                 /* No LMF on IA64 */
 823         }
 824
 825         if (sig->ret->type != MONO_TYPE_VOID) {
 826                 switch (cinfo->ret.storage) {
 827                 case ArgInIReg:
 828                         cfg->ret->opcode = OP_REGVAR;
 829                         cfg->ret->inst_c0 = cinfo->ret.reg;
 830                         break;
 831                 case ArgInFloatReg:
 832                         cfg->ret->opcode = OP_REGVAR;
 833                         cfg->ret->inst_c0 = cinfo->ret.reg;
 834                         break;
 835                 case ArgValuetypeAddrInIReg:
 836                         cfg->vret_addr->opcode = OP_REGVAR;
 837                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 838                         break;
 839                 case ArgAggregate:
 840                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 841                         if (cfg->arch.omit_fp)
 842                                 g_assert_not_reached ();
 843                         offset = ALIGN_TO (offset, 8);
 844                         offset += cinfo->ret.nslots * 8;
 845                         cfg->ret->opcode = OP_REGOFFSET;
 846                         cfg->ret->inst_basereg = cfg->frame_reg;
 847                         cfg->ret->inst_offset = - offset;
 848                         break;
 849                 default:
 850                         g_assert_not_reached ();
 851                 }
 852                 cfg->ret->dreg = cfg->ret->inst_c0;
 853         }
 854
 855         /* Allocate locals */
 856         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 857         if (locals_stack_align) {
 858                 offset = ALIGN_TO (offset, locals_stack_align);
 859         }
 860         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 861                 if (offsets [i] != -1) {
 862                         MonoInst *inst = cfg->varinfo [i];
 863                         inst->opcode = OP_REGOFFSET;
 864                         inst->inst_basereg = cfg->frame_reg;
 865                         if (cfg->arch.omit_fp)
 866                                 inst->inst_offset = (offset + offsets [i]);
 867                         else
 868                                 inst->inst_offset = - (offset + offsets [i]);
 869                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 870                 }
 871         }
 872         offset += locals_stack_size;
 873
 874         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 875                 if (cfg->arch.omit_fp)
 876                         g_assert_not_reached ();
 877                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 878                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 879         }
 880
 881         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 882                 inst = cfg->args [i];
 883                 if (inst->opcode != OP_REGVAR) {
 884                         ArgInfo *ainfo = &cinfo->args [i];
 885                         gboolean inreg = TRUE;
 886                         MonoType *arg_type;
 887
 888                         if (sig->hasthis && (i == 0))
 889                                 arg_type = &mono_defaults.object_class->byval_arg;
 890                         else
 891                                 arg_type = sig->params [i - sig->hasthis];
 892
 893                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 894                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 895                                 inreg = FALSE;
 896
 897                         inst->opcode = OP_REGOFFSET;
 898
 899                         switch (ainfo->storage) {
 900                         case ArgInIReg:
 901                                 inst->opcode = OP_REGVAR;
 902                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 903                                 break;
 904                         case ArgInFloatReg:
 905                         case ArgInFloatRegR4:
 906                                 /*
 907                                  * Since float regs are volatile, we save the arguments to
 908                                  * the stack in the prolog.
 909                                  */
 910                                 inreg = FALSE;
 911                                 break;
 912                         case ArgOnStack:
 913                                 if (cfg->arch.omit_fp)
 914                                         g_assert_not_reached ();
 915                                 inst->opcode = OP_REGOFFSET;
 916                                 inst->inst_basereg = cfg->frame_reg;
 917                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 918                                 break;
 919                         case ArgAggregate:
 920                                 inreg = FALSE;
 921                                 break;
 922                         default:
 923                                 NOT_IMPLEMENTED;
 924                         }
 925
 926                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 927                                 guint32 size = 0;
 928
 929                                 inst->opcode = OP_REGOFFSET;
 930                                 inst->inst_basereg = cfg->frame_reg;
 931                                 /* These arguments are saved to the stack in the prolog */
 932                                 switch (ainfo->storage) {
 933                                 case ArgAggregate:
 934                                         if (ainfo->atype == AggregateSingleHFA)
 935                                                 size = ainfo->nslots * 4;
 936                                         else
 937                                                 size = ainfo->nslots * 8;
 938                                         break;
 939                                 default:
 940                                         size = sizeof (gpointer);
 941                                         break;
 942                                 }
 943
 944                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 945
 946                                 if (cfg->arch.omit_fp) {
 947                                         inst->inst_offset = offset;
 948                                         offset += size;
 949                                 } else {
 950                                         offset += size;
 951                                         inst->inst_offset = - offset;
 952                                 }
 953                         }
 954                 }
 955         }
 956
 957         /*
 958          * FIXME: This doesn't work because some variables are allocated during local
 959          * regalloc.
 960          */
 961         /*
 962         if (cfg->arch.omit_fp && offset == 16)
 963                 offset = 0;
 964         */
 965
 966         cfg->stack_offset = offset;
 967 }
 968
 969 void
 970 mono_arch_create_vars (MonoCompile *cfg)
 971 {
 972         MonoMethodSignature *sig;
 973         CallInfo *cinfo;
 974
 975         sig = mono_method_signature (cfg->method);
 976
 977         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 978
 979         if (cinfo->ret.storage == ArgAggregate)
 980                 cfg->ret_var_is_local = TRUE;
 981         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 982                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 983                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 984                         printf ("vret_addr = ");
 985                         mono_print_ins (cfg->vret_addr);
 986                 }
 987         }
 988 }
 989
 990 static void
 991 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
 992 {
 993         MonoInst *arg;
 994
 995         MONO_INST_NEW (cfg, arg, OP_NOP);
 996         arg->sreg1 = tree->dreg;
 997
 998         switch (storage) {
 999         case ArgInIReg:
1000                 arg->opcode = OP_MOVE;
1001                 arg->dreg = mono_alloc_ireg (cfg);
1002
1003                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1004                 break;
1005         case ArgInFloatReg:
1006                 arg->opcode = OP_FMOVE;
1007                 arg->dreg = mono_alloc_freg (cfg);
1008
1009                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1010                 break;
1011         case ArgInFloatRegR4:
1012                 arg->opcode = OP_FCONV_TO_R4;
1013                 arg->dreg = mono_alloc_freg (cfg);
1014
1015                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1016                 break;
1017         default:
1018                 g_assert_not_reached ();
1019         }
1020
1021         MONO_ADD_INS (cfg->cbb, arg);
1022 }
1023
1024 static void
1025 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1026 {
1027         MonoMethodSignature *tmp_sig;
1028
1029         /* Emit the signature cookie just before the implicit arguments */
1030         MonoInst *sig_arg;
1031         /* FIXME: Add support for signature tokens to AOT */
1032         cfg->disable_aot = TRUE;
1033
1034         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1035
1036         /*
1037          * mono_ArgIterator_Setup assumes the signature cookie is
1038          * passed first and all the arguments which were before it are
1039          * passed on the stack after the signature. So compensate by
1040          * passing a different signature.
1041          */
1042         tmp_sig = mono_metadata_signature_dup (call->signature);
1043         tmp_sig->param_count -= call->signature->sentinelpos;
1044         tmp_sig->sentinelpos = 0;
1045         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1046
1047         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1048         sig_arg->dreg = mono_alloc_ireg (cfg);
1049         sig_arg->inst_p0 = tmp_sig;
1050         MONO_ADD_INS (cfg->cbb, sig_arg);
1051
1052         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1053 }
1054
1055 void
1056 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1057 {
1058         MonoInst *in;
1059         MonoMethodSignature *sig;
1060         int i, n, stack_size;
1061         CallInfo *cinfo;
1062         ArgInfo *ainfo;
1063
1064         stack_size = 0;
1065
1066         mono_ia64_alloc_stacked_registers (cfg);
1067
1068         sig = call->signature;
1069         n = sig->param_count + sig->hasthis;
1070
1071         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1072
1073         if (cinfo->ret.storage == ArgAggregate) {
1074                 MonoInst *vtarg;
1075                 MonoInst *local;
1076
1077                 /*
1078                  * The valuetype is in registers after the call, need to be copied
1079                  * to the stack. Save the address to a local here, so the call
1080                  * instruction can access it.
1081                  */
1082                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1083                 local->flags |= MONO_INST_VOLATILE;
1084                 cfg->arch.ret_var_addr_local = local;
1085
1086                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1087                 vtarg->sreg1 = call->vret_var->dreg;
1088                 vtarg->dreg = local->dreg;
1089                 MONO_ADD_INS (cfg->cbb, vtarg);
1090         }
1091
1092         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1093                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1094         }
1095
1096         for (i = 0; i < n; ++i) {
1097                 MonoType *arg_type;
1098
1099                 ainfo = cinfo->args + i;
1100
1101                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1102                         /* Emit the signature cookie just before the implicit arguments */
1103                         emit_sig_cookie (cfg, call, cinfo);
1104                 }
1105
1106                 in = call->args [i];
1107
1108                 if (sig->hasthis && (i == 0))
1109                         arg_type = &mono_defaults.object_class->byval_arg;
1110                 else
1111                         arg_type = sig->params [i - sig->hasthis];
1112
1113                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1114                         guint32 align;
1115                         guint32 size;
1116
1117                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1118                                 size = sizeof (MonoTypedRef);
1119                                 align = sizeof (gpointer);
1120                         }
1121                         else if (sig->pinvoke)
1122                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1123                         else {
1124                                 /*
1125                                  * Other backends use mono_type_stack_size (), but that
1126                                  * aligns the size to 8, which is larger than the size of
1127                                  * the source, leading to reads of invalid memory if the
1128                                  * source is at the end of address space.
1129                                  */
1130                                 size = mono_class_value_size (in->klass, &align);
1131                         }
1132
1133                         if (size > 0) {
1134                                 MonoInst *arg;
1135
1136                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1137                                 arg->sreg1 = in->dreg;
1138                                 arg->klass = in->klass;
1139                                 arg->backend.size = size;
1140                                 arg->inst_p0 = call;
1141                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1142                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1143
1144                                 MONO_ADD_INS (cfg->cbb, arg);
1145                         }
1146                 }
1147                 else {
1148                         switch (ainfo->storage) {
1149                         case ArgInIReg:
1150                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1151                                 break;
1152                         case ArgInFloatReg:
1153                         case ArgInFloatRegR4:
1154                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1155                                 break;
1156                         case ArgOnStack:
1157                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1158                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1159                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1160                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1161                                 else
1162                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1163                                 break;
1164                         default:
1165                                 g_assert_not_reached ();
1166                         }
1167                 }
1168         }
1169
1170         /* Handle the case where there are no implicit arguments */
1171         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1172                 emit_sig_cookie (cfg, call, cinfo);
1173         }
1174
1175         call->stack_usage = cinfo->stack_usage;
1176         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1177 }
1178
1179 void
1180 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1181 {
1182         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1183         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1184         int size = ins->backend.size;
1185
1186         if (ainfo->storage == ArgAggregate) {
1187                 MonoInst *load, *store;
1188                 int i, slot;
1189
1190                 /*
1191                  * Part of the structure is passed in registers.
1192                  */
1193                 for (i = 0; i < ainfo->nregs; ++i) {
1194                         slot = ainfo->reg + i;
1195
1196                         if (ainfo->atype == AggregateSingleHFA) {
1197                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1198                                 load->inst_basereg = src->dreg;
1199                                 load->inst_offset = i * 4;
1200                                 load->dreg = mono_alloc_freg (cfg);
1201
1202                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1203                         } else if (ainfo->atype == AggregateDoubleHFA) {
1204                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1205                                 load->inst_basereg = src->dreg;
1206                                 load->inst_offset = i * 8;
1207                                 load->dreg = mono_alloc_freg (cfg);
1208
1209                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1210                         } else {
1211                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1212                                 load->inst_basereg = src->dreg;
1213                                 load->inst_offset = i * 8;
1214                                 load->dreg = mono_alloc_ireg (cfg);
1215
1216                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1217                         }
1218                         MONO_ADD_INS (cfg->cbb, load);
1219                 }
1220
1221                 /*
1222                  * Part of the structure is passed on the stack.
1223                  */
1224                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1225                         slot = ainfo->reg + i;
1226
1227                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1228                         load->inst_basereg = src->dreg;
1229                         load->inst_offset = i * sizeof (gpointer);
1230                         load->dreg = mono_alloc_preg (cfg);
1231                         MONO_ADD_INS (cfg->cbb, load);
1232
1233                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1234                         store->sreg1 = load->dreg;
1235                         store->inst_destbasereg = IA64_SP;
1236                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1237                         MONO_ADD_INS (cfg->cbb, store);
1238                 }
1239         } else {
1240                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1241         }
1242 }
1243
1244 void
1245 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1246 {
1247         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1248
1249         switch (cinfo->ret.storage) {
1250         case ArgInIReg:
1251                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1252                 break;
1253         case ArgInFloatReg:
1254                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1255                 break;
1256         default:
1257                 g_assert_not_reached ();
1258         }
1259 }
1260
1261 void
1262 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1263 {
1264 }
1265
1266 void
1267 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1268 {
1269         MonoInst *ins, *n, *last_ins = NULL;
1270         ins = bb->code;
1271
1272         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1273                 switch (ins->opcode) {
1274                 case OP_MOVE:
1275                 case OP_FMOVE:
1276                         /*
1277                          * Removes:
1278                          *
1279                          * OP_MOVE reg, reg
1280                          */
1281                         if (ins->dreg == ins->sreg1) {
1282                                 MONO_DELETE_INS (bb, ins);
1283                                 continue;
1284                         }
1285                         /*
1286                          * Removes:
1287                          *
1288                          * OP_MOVE sreg, dreg
1289                          * OP_MOVE dreg, sreg
1290                          */
1291                         if (last_ins && last_ins->opcode == OP_MOVE &&
1292                             ins->sreg1 == last_ins->dreg &&
1293                             ins->dreg == last_ins->sreg1) {
1294                                 MONO_DELETE_INS (bb, ins);
1295                                 continue;
1296                         }
1297                         break;
1298                 case OP_MUL_IMM:
1299                 case OP_IMUL_IMM:
1300                         /* remove unnecessary multiplication with 1 */
1301                         if (ins->inst_imm == 1) {
1302                                 if (ins->dreg != ins->sreg1) {
1303                                         ins->opcode = OP_MOVE;
1304                                 } else {
1305                                         MONO_DELETE_INS (bb, ins);
1306                                         continue;
1307                                 }
1308                         }
1309                         break;
1310                 }
1311
1312                 last_ins = ins;
1313                 ins = ins->next;
1314         }
1315         bb->last_ins = last_ins;
1316 }
1317
1318 int cond_to_ia64_cmp [][3] = {
1319         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1320         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1321         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1322         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1323         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1324         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1325         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1326         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1327         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1328         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1329 };
1330
1331 static int
1332 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1333 {
1334         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1335 }
1336
1337 int cond_to_ia64_cmp_imm [][3] = {
1338         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1339         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1340         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1341         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1342         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1343         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1344         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1345         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1346         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1347         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1348 };
1349
1350 static int
1351 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1352 {
1353         /* The condition needs to be reversed */
1354         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1355 }
1356
1357 #define NEW_INS(cfg,dest,op) do {       \
1358                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1359                 (dest)->opcode = (op);  \
1360         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1361         last_ins = (dest); \
1362         } while (0)
1363
1364 /*
1365  * mono_arch_lowering_pass:
1366  *
1367  *  Converts complex opcodes into simpler ones so that each IR instruction
1368  * corresponds to one machine instruction.
1369  */
1370 void
1371 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1372 {
1373         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1374         ins = bb->code;
1375
1376         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1377                 switch (ins->opcode) {
1378                 case OP_STOREI1_MEMBASE_IMM:
1379                 case OP_STOREI2_MEMBASE_IMM:
1380                 case OP_STOREI4_MEMBASE_IMM:
1381                 case OP_STOREI8_MEMBASE_IMM:
1382                 case OP_STORE_MEMBASE_IMM:
1383                         /* There are no store_membase instructions on ia64 */
1384                         if (ins->inst_offset == 0) {
1385                                 temp2 = NULL;
1386                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1387                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1388                                 temp2->sreg1 = ins->inst_destbasereg;
1389                                 temp2->inst_imm = ins->inst_offset;
1390                                 temp2->dreg = mono_alloc_ireg (cfg);
1391                         }
1392                         else {
1393                                 NEW_INS (cfg, temp, OP_I8CONST);
1394                                 temp->inst_c0 = ins->inst_offset;
1395                                 temp->dreg = mono_alloc_ireg (cfg);
1396
1397                                 NEW_INS (cfg, temp2, OP_LADD);
1398                                 temp2->sreg1 = ins->inst_destbasereg;
1399                                 temp2->sreg2 = temp->dreg;
1400                                 temp2->dreg = mono_alloc_ireg (cfg);
1401                         }
1402
1403                         switch (ins->opcode) {
1404                         case OP_STOREI1_MEMBASE_IMM:
1405                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1406                                 break;
1407                         case OP_STOREI2_MEMBASE_IMM:
1408                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1409                                 break;
1410                         case OP_STOREI4_MEMBASE_IMM:
1411                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1412                                 break;
1413                         case OP_STOREI8_MEMBASE_IMM:
1414                         case OP_STORE_MEMBASE_IMM:
1415                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1416                                 break;
1417                         default:
1418                                 g_assert_not_reached ();
1419                         }
1420
1421                         if (ins->inst_imm == 0)
1422                                 ins->sreg1 = IA64_R0;
1423                         else {
1424                                 NEW_INS (cfg, temp3, OP_I8CONST);
1425                                 temp3->inst_c0 = ins->inst_imm;
1426                                 temp3->dreg = mono_alloc_ireg (cfg);
1427                                 ins->sreg1 = temp3->dreg;
1428                         }
1429
1430                         ins->inst_offset = 0;
1431                         if (temp2)
1432                                 ins->inst_destbasereg = temp2->dreg;
1433                         break;
1434                 case OP_STOREI1_MEMBASE_REG:
1435                 case OP_STOREI2_MEMBASE_REG:
1436                 case OP_STOREI4_MEMBASE_REG:
1437                 case OP_STOREI8_MEMBASE_REG:
1438                 case OP_STORER4_MEMBASE_REG:
1439                 case OP_STORER8_MEMBASE_REG:
1440                 case OP_STORE_MEMBASE_REG:
1441                         /* There are no store_membase instructions on ia64 */
1442                         if (ins->inst_offset == 0) {
1443                                 break;
1444                         }
1445                         else if (ia64_is_imm14 (ins->inst_offset)) {
1446                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1447                                 temp2->sreg1 = ins->inst_destbasereg;
1448                                 temp2->inst_imm = ins->inst_offset;
1449                                 temp2->dreg = mono_alloc_ireg (cfg);
1450                         }
1451                         else {
1452                                 NEW_INS (cfg, temp, OP_I8CONST);
1453                                 temp->inst_c0 = ins->inst_offset;
1454                                 temp->dreg = mono_alloc_ireg (cfg);
1455                                 NEW_INS (cfg, temp2, OP_LADD);
1456                                 temp2->sreg1 = ins->inst_destbasereg;
1457                                 temp2->sreg2 = temp->dreg;
1458                                 temp2->dreg = mono_alloc_ireg (cfg);
1459                         }
1460
1461                         ins->inst_offset = 0;
1462                         ins->inst_destbasereg = temp2->dreg;
1463                         break;
1464                 case OP_LOADI1_MEMBASE:
1465                 case OP_LOADU1_MEMBASE:
1466                 case OP_LOADI2_MEMBASE:
1467                 case OP_LOADU2_MEMBASE:
1468                 case OP_LOADI4_MEMBASE:
1469                 case OP_LOADU4_MEMBASE:
1470                 case OP_LOADI8_MEMBASE:
1471                 case OP_LOAD_MEMBASE:
1472                 case OP_LOADR4_MEMBASE:
1473                 case OP_LOADR8_MEMBASE:
1474                 case OP_ATOMIC_EXCHANGE_I4:
1475                 case OP_ATOMIC_EXCHANGE_I8:
1476                 case OP_ATOMIC_ADD_NEW_I4:
1477                 case OP_ATOMIC_ADD_NEW_I8:
1478                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1479                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1480                         /* There are no membase instructions on ia64 */
1481                         if (ins->inst_offset == 0) {
1482                                 break;
1483                         }
1484                         else if (ia64_is_imm14 (ins->inst_offset)) {
1485                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1486                                 temp2->sreg1 = ins->inst_basereg;
1487                                 temp2->inst_imm = ins->inst_offset;
1488                                 temp2->dreg = mono_alloc_ireg (cfg);
1489                         }
1490                         else {
1491                                 NEW_INS (cfg, temp, OP_I8CONST);
1492                                 temp->inst_c0 = ins->inst_offset;
1493                                 temp->dreg = mono_alloc_ireg (cfg);
1494                                 NEW_INS (cfg, temp2, OP_LADD);
1495                                 temp2->sreg1 = ins->inst_basereg;
1496                                 temp2->sreg2 = temp->dreg;
1497                                 temp2->dreg = mono_alloc_ireg (cfg);
1498                         }
1499
1500                         ins->inst_offset = 0;
1501                         ins->inst_basereg = temp2->dreg;
1502                         break;
1503                 case OP_ADD_IMM:
1504                 case OP_IADD_IMM:
1505                 case OP_LADD_IMM:
1506                 case OP_ISUB_IMM:
1507                 case OP_LSUB_IMM:
1508                 case OP_AND_IMM:
1509                 case OP_IAND_IMM:
1510                 case OP_LAND_IMM:
1511                 case OP_IOR_IMM:
1512                 case OP_LOR_IMM:
1513                 case OP_IXOR_IMM:
1514                 case OP_LXOR_IMM:
1515                 case OP_SHL_IMM:
1516                 case OP_SHR_IMM:
1517                 case OP_ISHL_IMM:
1518                 case OP_LSHL_IMM:
1519                 case OP_ISHR_IMM:
1520                 case OP_LSHR_IMM:
1521                 case OP_ISHR_UN_IMM:
1522                 case OP_LSHR_UN_IMM: {
1523                         gboolean is_imm = FALSE;
1524                         gboolean switched = FALSE;
1525
1526                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1527                                 ins->opcode = OP_ZEXT_I1;
1528                                 break;
1529                         }
1530
1531                         switch (ins->opcode) {
1532                         case OP_ADD_IMM:
1533                         case OP_IADD_IMM:
1534                         case OP_LADD_IMM:
1535                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1536                                 switched = TRUE;
1537                                 break;
1538                         case OP_ISUB_IMM:
1539                         case OP_LSUB_IMM:
1540                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1541                                 if (is_imm) {
1542                                         /* A = B - IMM -> A = B + (-IMM) */
1543                                         ins->inst_imm = - ins->inst_imm;
1544                                         ins->opcode = OP_IADD_IMM;
1545                                 }
1546                                 switched = TRUE;
1547                                 break;
1548                         case OP_IAND_IMM:
1549                         case OP_IOR_IMM:
1550                         case OP_IXOR_IMM:
1551                         case OP_AND_IMM:
1552                         case OP_LAND_IMM:
1553                         case OP_LOR_IMM:
1554                         case OP_LXOR_IMM:
1555                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1556                                 switched = TRUE;
1557                                 break;
1558                         case OP_SHL_IMM:
1559                         case OP_SHR_IMM:
1560                         case OP_ISHL_IMM:
1561                         case OP_LSHL_IMM:
1562                         case OP_ISHR_IMM:
1563                         case OP_LSHR_IMM:
1564                         case OP_ISHR_UN_IMM:
1565                         case OP_LSHR_UN_IMM:
1566                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1567                                 break;
1568                         default:
1569                                 break;
1570                         }
1571
1572                         if (is_imm) {
1573                                 if (switched)
1574                                         ins->sreg2 = ins->sreg1;
1575                                 break;
1576                         }
1577
1578                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1579
1580                         if (ins->inst_imm == 0)
1581                                 ins->sreg2 = IA64_R0;
1582                         else {
1583                                 NEW_INS (cfg, temp, OP_I8CONST);
1584                                 temp->inst_c0 = ins->inst_imm;
1585                                 temp->dreg = mono_alloc_ireg (cfg);
1586                                 ins->sreg2 = temp->dreg;
1587                         }
1588                         break;
1589                 }
1590                 case OP_COMPARE_IMM:
1591                 case OP_ICOMPARE_IMM:
1592                 case OP_LCOMPARE_IMM: {
1593                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1594                         gboolean imm;
1595                         CompRelation cond;
1596
1597                         next = ins->next;
1598
1599                         /* Branch opts can eliminate the branch */
1600                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1601                                 NULLIFY_INS (ins);
1602                                 break;
1603                         }
1604
1605                         /*
1606                          * The compare_imm instructions have switched up arguments, and
1607                          * some of them take an imm between -127 and 128.
1608                          */
1609                         next = ins->next;
1610                         cond = mono_opcode_to_cond (next->opcode);
1611                         if ((cond == CMP_LT) || (cond == CMP_GE))
1612                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1613                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1614                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1615                         else
1616                                 imm = ia64_is_imm8 (ins->inst_imm);
1617
1618                         if (imm) {
1619                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1620                                 ins->sreg2 = ins->sreg1;
1621                         }
1622                         else {
1623                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1624
1625                                 if (ins->inst_imm == 0)
1626                                         ins->sreg2 = IA64_R0;
1627                                 else {
1628                                         NEW_INS (cfg, temp, OP_I8CONST);
1629                                         temp->inst_c0 = ins->inst_imm;
1630                                         temp->dreg = mono_alloc_ireg (cfg);
1631                                         ins->sreg2 = temp->dreg;
1632                                 }
1633                         }
1634
1635                         if (MONO_IS_COND_BRANCH_OP (next)) {
1636                                 next->opcode = OP_IA64_BR_COND;
1637                                 next->inst_target_bb = next->inst_true_bb;
1638                         } else if (MONO_IS_COND_EXC (next)) {
1639                                 next->opcode = OP_IA64_COND_EXC;
1640                         } else if (MONO_IS_SETCC (next)) {
1641                                 next->opcode = OP_IA64_CSET;
1642                         } else {
1643                                 printf ("%s\n", mono_inst_name (next->opcode));
1644                                 NOT_IMPLEMENTED;
1645                         }
1646
1647                         break;
1648                 }
1649                 case OP_COMPARE:
1650                 case OP_ICOMPARE:
1651                 case OP_LCOMPARE:
1652                 case OP_FCOMPARE: {
1653                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1654
1655                         next = ins->next;
1656
1657                         /* Branch opts can eliminate the branch */
1658                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1659                                 NULLIFY_INS (ins);
1660                                 break;
1661                         }
1662
1663                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1664
1665                         if (MONO_IS_COND_BRANCH_OP (next)) {
1666                                 next->opcode = OP_IA64_BR_COND;
1667                                 next->inst_target_bb = next->inst_true_bb;
1668                         } else if (MONO_IS_COND_EXC (next)) {
1669                                 next->opcode = OP_IA64_COND_EXC;
1670                         } else if (MONO_IS_SETCC (next)) {
1671                                 next->opcode = OP_IA64_CSET;
1672                         } else {
1673                                 printf ("%s\n", mono_inst_name (next->opcode));
1674                                 NOT_IMPLEMENTED;
1675                         }
1676
1677                         break;
1678                 }
1679                 case OP_FCEQ:
1680                 case OP_FCGT:
1681                 case OP_FCGT_UN:
1682                 case OP_FCLT:
1683                 case OP_FCLT_UN:
1684                         /* The front end removes the fcompare, so introduce it again */
1685                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1686                         temp->sreg1 = ins->sreg1;
1687                         temp->sreg2 = ins->sreg2;
1688
1689                         ins->opcode = OP_IA64_CSET;
1690                         MONO_INST_NULLIFY_SREGS (ins);
1691                         break;
1692                 case OP_MUL_IMM:
1693                 case OP_LMUL_IMM:
1694                 case OP_IMUL_IMM: {
1695                         int i, sum_reg;
1696                         gboolean found = FALSE;
1697                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1698
1699                         /* First the easy cases */
1700                         if (ins->inst_imm == 1) {
1701                                 ins->opcode = OP_MOVE;
1702                                 break;
1703                         }
1704                         for (i = 1; i < 64; ++i)
1705                                 if (ins->inst_imm == (((gint64)1) << i)) {
1706                                         ins->opcode = shl_op;
1707                                         ins->inst_imm = i;
1708                                         found = TRUE;
1709                                         break;
1710                                 }
1711
1712                         /* This could be optimized */
1713                         if (!found) {
1714                                 sum_reg = 0;
1715                                 for (i = 0; i < 64; ++i) {
1716                                         if (ins->inst_imm & (((gint64)1) << i)) {
1717                                                 NEW_INS (cfg, temp, shl_op);
1718                                                 temp->dreg = mono_alloc_ireg (cfg);
1719                                                 temp->sreg1 = ins->sreg1;
1720                                                 temp->inst_imm = i;
1721
1722                                                 if (sum_reg == 0)
1723                                                         sum_reg = temp->dreg;
1724                                                 else {
1725                                                         NEW_INS (cfg, temp2, OP_LADD);
1726                                                         temp2->dreg = mono_alloc_ireg (cfg);
1727                                                         temp2->sreg1 = sum_reg;
1728                                                         temp2->sreg2 = temp->dreg;
1729                                                         sum_reg = temp2->dreg;
1730                                                 }
1731                                         }
1732                                 }
1733                                 ins->opcode = OP_MOVE;
1734                                 ins->sreg1 = sum_reg;
1735                         }
1736                         break;
1737                 }
1738                 case OP_LCONV_TO_OVF_U4:
1739                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1740                         temp->sreg1 = ins->sreg1;
1741                         temp->sreg2 = IA64_R0;
1742
1743                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1744                         temp->inst_p1 = (char*)"OverflowException";
1745
1746                         ins->opcode = OP_MOVE;
1747                         break;
1748                 case OP_LCONV_TO_OVF_I4_UN:
1749                         NEW_INS (cfg, temp, OP_ICONST);
1750                         temp->inst_c0 = 0x7fffffff;
1751                         temp->dreg = mono_alloc_ireg (cfg);
1752
1753                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1754                         temp2->sreg1 = ins->sreg1;
1755                         temp2->sreg2 = temp->dreg;
1756
1757                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1758                         temp->inst_p1 = (char*)"OverflowException";
1759
1760                         ins->opcode = OP_MOVE;
1761                         break;
1762                 case OP_FCONV_TO_I4:
1763                 case OP_FCONV_TO_I2:
1764                 case OP_FCONV_TO_U2:
1765                 case OP_FCONV_TO_I1:
1766                 case OP_FCONV_TO_U1:
1767                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1768                         temp->sreg1 = ins->sreg1;
1769                         temp->dreg = ins->dreg;
1770
1771                         switch (ins->opcode) {
1772                         case OP_FCONV_TO_I4:
1773                                 ins->opcode = OP_SEXT_I4;
1774                                 break;
1775                         case OP_FCONV_TO_I2:
1776                                 ins->opcode = OP_SEXT_I2;
1777                                 break;
1778                         case OP_FCONV_TO_U2:
1779                                 ins->opcode = OP_ZEXT_I4;
1780                                 break;
1781                         case OP_FCONV_TO_I1:
1782                                 ins->opcode = OP_SEXT_I1;
1783                                 break;
1784                         case OP_FCONV_TO_U1:
1785                                 ins->opcode = OP_ZEXT_I1;
1786                                 break;
1787                         default:
1788                                 g_assert_not_reached ();
1789                         }
1790                         ins->sreg1 = ins->dreg;
1791                         break;
1792                 default:
1793                         break;
1794                 }
1795                 last_ins = ins;
1796                 ins = ins->next;
1797         }
1798         bb->last_ins = last_ins;
1799
1800         bb->max_vreg = cfg->next_vreg;
1801 }
1802
1803 /*
1804  * emit_load_volatile_arguments:
1805  *
1806  *  Load volatile arguments from the stack to the original input registers.
1807  * Required before a tail call.
1808  */
1809 static Ia64CodegenState
1810 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1811 {
1812         MonoMethod *method = cfg->method;
1813         MonoMethodSignature *sig;
1814         MonoInst *ins;
1815         CallInfo *cinfo;
1816         guint32 i;
1817
1818         /* FIXME: Generate intermediate code instead */
1819
1820         sig = mono_method_signature (method);
1821
1822         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1823
1824         /* This is the opposite of the code in emit_prolog */
1825         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1826                 ArgInfo *ainfo = cinfo->args + i;
1827                 gint32 stack_offset;
1828                 MonoType *arg_type;
1829
1830                 ins = cfg->args [i];
1831
1832                 if (sig->hasthis && (i == 0))
1833                         arg_type = &mono_defaults.object_class->byval_arg;
1834                 else
1835                         arg_type = sig->params [i - sig->hasthis];
1836
1837                 arg_type = mono_type_get_underlying_type (arg_type);
1838
1839                 stack_offset = ainfo->offset + ARGS_OFFSET;
1840
1841                 /* Save volatile arguments to the stack */
1842                 if (ins->opcode != OP_REGVAR) {
1843                         switch (ainfo->storage) {
1844                         case ArgInIReg:
1845                         case ArgInFloatReg:
1846                                 /* FIXME: big offsets */
1847                                 g_assert (ins->opcode == OP_REGOFFSET);
1848                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1849                                 if (arg_type->byref)
1850                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1851                                 else {
1852                                         switch (arg_type->type) {
1853                                         case MONO_TYPE_R4:
1854                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1855                                                 break;
1856                                         case MONO_TYPE_R8:
1857                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1858                                                 break;
1859                                         default:
1860                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1861                                                 break;
1862                                         }
1863                                 }
1864                                 break;
1865                         case ArgOnStack:
1866                                 break;
1867                         default:
1868                                 NOT_IMPLEMENTED;
1869                         }
1870                 }
1871
1872                 if (ins->opcode == OP_REGVAR) {
1873                         /* Argument allocated to (non-volatile) register */
1874                         switch (ainfo->storage) {
1875                         case ArgInIReg:
1876                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1877                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1878                                 break;
1879                         case ArgOnStack:
1880                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1881                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1882                                 break;
1883                         default:
1884                                 NOT_IMPLEMENTED;
1885                         }
1886                 }
1887         }
1888
1889         return code;
1890 }
1891
1892 static Ia64CodegenState
1893 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1894 {
1895         CallInfo *cinfo;
1896         int i;
1897
1898         /* Move return value to the target register */
1899         switch (ins->opcode) {
1900         case OP_VOIDCALL:
1901         case OP_VOIDCALL_REG:
1902         case OP_VOIDCALL_MEMBASE:
1903                 break;
1904         case OP_CALL:
1905         case OP_CALL_REG:
1906         case OP_CALL_MEMBASE:
1907         case OP_LCALL:
1908         case OP_LCALL_REG:
1909         case OP_LCALL_MEMBASE:
1910                 g_assert (ins->dreg == IA64_R8);
1911                 break;
1912         case OP_FCALL:
1913         case OP_FCALL_REG:
1914         case OP_FCALL_MEMBASE:
1915                 g_assert (ins->dreg == 8);
1916                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1917                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1918                 break;
1919         case OP_VCALL:
1920         case OP_VCALL_REG:
1921         case OP_VCALL_MEMBASE:
1922         case OP_VCALL2:
1923         case OP_VCALL2_REG:
1924         case OP_VCALL2_MEMBASE: {
1925                 ArgStorage storage;
1926
1927                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1928                 storage = cinfo->ret.storage;
1929
1930                 if (storage == ArgAggregate) {
1931                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1932
1933                         /* Load address of stack space allocated for the return value */
1934                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1935                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1936                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1937
1938                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1939                                 switch (cinfo->ret.atype) {
1940                                 case AggregateNormal:
1941                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1942                                         break;
1943                                 case AggregateSingleHFA:
1944                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1945                                         break;
1946                                 case AggregateDoubleHFA:
1947                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1948                                         break;
1949                                 default:
1950                                         g_assert_not_reached ();
1951                                 }
1952                         }
1953                 }
1954                 break;
1955         }
1956         default:
1957                 g_assert_not_reached ();
1958         }
1959
1960         return code;
1961 }
1962
1963 #define add_patch_info(cfg,code,patch_type,data) do { \
1964         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1965 } while (0)
1966
1967 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1968         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1969     if (tins == NULL) \
1970         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1971     else \
1972                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1973         ia64_br_cond_pred (code, (predicate), 0); \
1974 } while (0)
1975
1976 static Ia64CodegenState
1977 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1978 {
1979         add_patch_info (cfg, code, patch_type, data);
1980
1981         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1982                 /* Indirect call */
1983                 /* mono_arch_patch_callsite will patch this */
1984                 /* mono_arch_nullify_class_init_trampoline will patch this */
1985                 ia64_movl (code, GP_SCRATCH_REG, 0);
1986                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1987                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1988                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1989                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1990         }
1991         else {
1992                 /* Can't use a direct call since the displacement might be too small */
1993                 /* mono_arch_patch_callsite will patch this */
1994                 ia64_movl (code, GP_SCRATCH_REG, 0);
1995                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
1996                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1997         }
1998
1999         return code;
2000 }
2001
2002 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2003
2004 void
2005 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2006 {
2007         MonoInst *ins;
2008         MonoCallInst *call;
2009         guint offset;
2010         Ia64CodegenState code;
2011         guint8 *code_start = cfg->native_code + cfg->code_len;
2012         MonoInst *last_ins = NULL;
2013         guint last_offset = 0;
2014         int max_len, cpos;
2015
2016         if (cfg->opt & MONO_OPT_LOOP) {
2017                 /* FIXME: */
2018         }
2019
2020         if (cfg->verbose_level > 2)
2021                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2022
2023         cpos = bb->max_offset;
2024
2025         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2026                 NOT_IMPLEMENTED;
2027         }
2028
2029         offset = code_start - cfg->native_code;
2030
2031         ia64_codegen_init (code, code_start);
2032
2033 #if 0
2034         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2035                 break_count ();
2036 #endif
2037
2038         MONO_BB_FOR_EACH_INS (bb, ins) {
2039                 offset = code.buf - cfg->native_code;
2040
2041                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2042
2043                 while (offset + max_len + 16 > cfg->code_size) {
2044                         ia64_codegen_close (code);
2045
2046                         offset = code.buf - cfg->native_code;
2047
2048                         cfg->code_size *= 2;
2049                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2050                         code_start = cfg->native_code + offset;
2051                         mono_jit_stats.code_reallocs++;
2052
2053                         ia64_codegen_init (code, code_start);
2054                 }
2055
2056                 mono_debug_record_line_number (cfg, ins, offset);
2057
2058                 switch (ins->opcode) {
2059                 case OP_ICONST:
2060                 case OP_I8CONST:
2061                         if (ia64_is_imm14 (ins->inst_c0))
2062                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2063                         else
2064                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2065                         break;
2066                 case OP_JUMP_TABLE:
2067                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2068                         ia64_movl (code, ins->dreg, 0);
2069                         break;
2070                 case OP_MOVE:
2071                         ia64_mov (code, ins->dreg, ins->sreg1);
2072                         break;
2073                 case OP_BR:
2074                 case OP_IA64_BR_COND: {
2075                         int pred = 0;
2076                         if (ins->opcode == OP_IA64_BR_COND)
2077                                 pred = 6;
2078                         if (ins->inst_target_bb->native_offset) {
2079                                 guint8 *pos = code.buf + code.nins;
2080
2081                                 ia64_br_cond_pred (code, pred, 0);
2082                                 ia64_begin_bundle (code);
2083                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2084                         } else {
2085                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2086                                 ia64_br_cond_pred (code, pred, 0);
2087                         }
2088                         break;
2089                 }
2090                 case OP_LABEL:
2091                         ia64_begin_bundle (code);
2092                         ins->inst_c0 = code.buf - cfg->native_code;
2093                         break;
2094                 case OP_NOP:
2095                 case OP_RELAXED_NOP:
2096                 case OP_DUMMY_USE:
2097                 case OP_DUMMY_STORE:
2098                 case OP_NOT_REACHED:
2099                 case OP_NOT_NULL:
2100                         break;
2101                 case OP_BR_REG:
2102                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2103                         ia64_br_cond_reg (code, IA64_B6);
2104                         break;
2105                 case OP_IADD:
2106                 case OP_LADD:
2107                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2108                         break;
2109                 case OP_ISUB:
2110                 case OP_LSUB:
2111                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2112                         break;
2113                 case OP_IAND:
2114                 case OP_LAND:
2115                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2116                         break;
2117                 case OP_IOR:
2118                 case OP_LOR:
2119                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2120                         break;
2121                 case OP_IXOR:
2122                 case OP_LXOR:
2123                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2124                         break;
2125                 case OP_INEG:
2126                 case OP_LNEG:
2127                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2128                         break;
2129                 case OP_INOT:
2130                 case OP_LNOT:
2131                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2132                         break;
2133                 case OP_ISHL:
2134                 case OP_LSHL:
2135                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2136                         break;
2137                 case OP_ISHR:
2138                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2139                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2140                         break;
2141                 case OP_LSHR:
2142                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2143                         break;
2144                 case OP_ISHR_UN:
2145                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2146                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2147                         break;
2148                 case OP_LSHR_UN:
2149                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2150                         break;
2151                 case OP_IADDCC:
2152                         /* p6 and p7 is set if there is signed/unsigned overflow */
2153
2154                         /* Set p8-p9 == (sreg2 > 0) */
2155                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2156
2157                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2158
2159                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2160                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2161                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2162                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2163
2164                         /* res <u sreg1 => unsigned overflow */
2165                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2166
2167                         /* FIXME: Predicate this since this is a side effect */
2168                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2169                         break;
2170                 case OP_ISUBCC:
2171                         /* p6 and p7 is set if there is signed/unsigned overflow */
2172
2173                         /* Set p8-p9 == (sreg2 > 0) */
2174                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2175
2176                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2177
2178                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2179                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2180                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2181                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2182
2183                         /* sreg1 <u sreg2 => unsigned overflow */
2184                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2185
2186                         /* FIXME: Predicate this since this is a side effect */
2187                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2188                         break;
2189                 case OP_ADDCC:
2190                         /* Same as OP_IADDCC */
2191                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2192
2193                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2194
2195                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2196                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2197
2198                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2199
2200                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2201                         break;
2202                 case OP_SUBCC:
2203                         /* Same as OP_ISUBCC */
2204
2205                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2206
2207                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2208
2209                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2210                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2211
2212                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2213
2214                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2215                         break;
2216                 case OP_ADD_IMM:
2217                 case OP_IADD_IMM:
2218                 case OP_LADD_IMM:
2219                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2220                         break;
2221                 case OP_IAND_IMM:
2222                 case OP_AND_IMM:
2223                 case OP_LAND_IMM:
2224                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2225                         break;
2226                 case OP_IOR_IMM:
2227                 case OP_LOR_IMM:
2228                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2229                         break;
2230                 case OP_IXOR_IMM:
2231                 case OP_LXOR_IMM:
2232                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2233                         break;
2234                 case OP_SHL_IMM:
2235                 case OP_ISHL_IMM:
2236                 case OP_LSHL_IMM:
2237                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2238                         break;
2239                 case OP_SHR_IMM:
2240                 case OP_LSHR_IMM:
2241                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2242                         break;
2243                 case OP_ISHR_IMM:
2244                         g_assert (ins->inst_imm <= 64);
2245                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2246                         break;
2247                 case OP_ISHR_UN_IMM:
2248                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2249                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2250                         break;
2251                 case OP_LSHR_UN_IMM:
2252                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2253                         break;
2254                 case OP_LMUL:
2255                         /* Based on gcc code */
2256                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2257                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2258                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2259                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2260                         break;
2261
2262                 case OP_STOREI1_MEMBASE_REG:
2263                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2264                         break;
2265                 case OP_STOREI2_MEMBASE_REG:
2266                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2267                         break;
2268                 case OP_STOREI4_MEMBASE_REG:
2269                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2270                         break;
2271                 case OP_STOREI8_MEMBASE_REG:
2272                 case OP_STORE_MEMBASE_REG:
2273                         if (ins->inst_offset != 0) {
2274                                 /* This is generated by local regalloc */
2275                                 if (ia64_is_imm14 (ins->inst_offset)) {
2276                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2277                                 } else {
2278                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2279                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2280                                 }
2281                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2282                         }
2283                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2284                         break;
2285
2286                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2287                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2288                         break;
2289                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2290                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2291                         break;
2292                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2293                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2294                         break;
2295                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2296                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2297                         break;
2298
2299                 case OP_LOADU1_MEMBASE:
2300                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2301                         break;
2302                 case OP_LOADU2_MEMBASE:
2303                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2304                         break;
2305                 case OP_LOADU4_MEMBASE:
2306                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2307                         break;
2308                 case OP_LOADI1_MEMBASE:
2309                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2310                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2311                         break;
2312                 case OP_LOADI2_MEMBASE:
2313                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2314                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2315                         break;
2316                 case OP_LOADI4_MEMBASE:
2317                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2318                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2319                         break;
2320                 case OP_LOAD_MEMBASE:
2321                 case OP_LOADI8_MEMBASE:
2322                         if (ins->inst_offset != 0) {
2323                                 /* This is generated by local regalloc */
2324                                 if (ia64_is_imm14 (ins->inst_offset)) {
2325                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2326                                 } else {
2327                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2328                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2329                                 }
2330                                 ins->inst_basereg = GP_SCRATCH_REG;
2331                         }
2332                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2333                         break;
2334
2335                 case OP_IA64_LOADU1_MEMBASE_INC:
2336                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2337                         break;
2338                 case OP_IA64_LOADU2_MEMBASE_INC:
2339                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2340                         break;
2341                 case OP_IA64_LOADU4_MEMBASE_INC:
2342                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2343                         break;
2344                 case OP_IA64_LOADI8_MEMBASE_INC:
2345                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2346                         break;
2347
2348                 case OP_SEXT_I1:
2349                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2350                         break;
2351                 case OP_SEXT_I2:
2352                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2353                         break;
2354                 case OP_SEXT_I4:
2355                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2356                         break;
2357                 case OP_ZEXT_I1:
2358                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2359                         break;
2360                 case OP_ZEXT_I2:
2361                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2362                         break;
2363                 case OP_ZEXT_I4:
2364                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2365                         break;
2366
2367                         /* Compare opcodes */
2368                 case OP_IA64_CMP4_EQ:
2369                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2370                         break;
2371                 case OP_IA64_CMP4_NE:
2372                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2373                         break;
2374                 case OP_IA64_CMP4_LE:
2375                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2376                         break;
2377                 case OP_IA64_CMP4_LT:
2378                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2379                         break;
2380                 case OP_IA64_CMP4_GE:
2381                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2382                         break;
2383                 case OP_IA64_CMP4_GT:
2384                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2385                         break;
2386                 case OP_IA64_CMP4_LT_UN:
2387                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2388                         break;
2389                 case OP_IA64_CMP4_LE_UN:
2390                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2391                         break;
2392                 case OP_IA64_CMP4_GT_UN:
2393                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2394                         break;
2395                 case OP_IA64_CMP4_GE_UN:
2396                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2397                         break;
2398                 case OP_IA64_CMP_EQ:
2399                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2400                         break;
2401                 case OP_IA64_CMP_NE:
2402                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2403                         break;
2404                 case OP_IA64_CMP_LE:
2405                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2406                         break;
2407                 case OP_IA64_CMP_LT:
2408                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2409                         break;
2410                 case OP_IA64_CMP_GE:
2411                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2412                         break;
2413                 case OP_IA64_CMP_GT:
2414                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2415                         break;
2416                 case OP_IA64_CMP_GT_UN:
2417                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2418                         break;
2419                 case OP_IA64_CMP_LT_UN:
2420                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2421                         break;
2422                 case OP_IA64_CMP_GE_UN:
2423                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2424                         break;
2425                 case OP_IA64_CMP_LE_UN:
2426                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2427                         break;
2428                 case OP_IA64_CMP4_EQ_IMM:
2429                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2430                         break;
2431                 case OP_IA64_CMP4_NE_IMM:
2432                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2433                         break;
2434                 case OP_IA64_CMP4_LE_IMM:
2435                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2436                         break;
2437                 case OP_IA64_CMP4_LT_IMM:
2438                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2439                         break;
2440                 case OP_IA64_CMP4_GE_IMM:
2441                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2442                         break;
2443                 case OP_IA64_CMP4_GT_IMM:
2444                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2445                         break;
2446                 case OP_IA64_CMP4_LT_UN_IMM:
2447                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2448                         break;
2449                 case OP_IA64_CMP4_LE_UN_IMM:
2450                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2451                         break;
2452                 case OP_IA64_CMP4_GT_UN_IMM:
2453                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2454                         break;
2455                 case OP_IA64_CMP4_GE_UN_IMM:
2456                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2457                         break;
2458                 case OP_IA64_CMP_EQ_IMM:
2459                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2460                         break;
2461                 case OP_IA64_CMP_NE_IMM:
2462                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2463                         break;
2464                 case OP_IA64_CMP_LE_IMM:
2465                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2466                         break;
2467                 case OP_IA64_CMP_LT_IMM:
2468                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2469                         break;
2470                 case OP_IA64_CMP_GE_IMM:
2471                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2472                         break;
2473                 case OP_IA64_CMP_GT_IMM:
2474                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2475                         break;
2476                 case OP_IA64_CMP_GT_UN_IMM:
2477                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2478                         break;
2479                 case OP_IA64_CMP_LT_UN_IMM:
2480                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2481                         break;
2482                 case OP_IA64_CMP_GE_UN_IMM:
2483                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2484                         break;
2485                 case OP_IA64_CMP_LE_UN_IMM:
2486                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2487                         break;
2488                 case OP_IA64_FCMP_EQ:
2489                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2490                         break;
2491                 case OP_IA64_FCMP_NE:
2492                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2493                         break;
2494                 case OP_IA64_FCMP_LT:
2495                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2496                         break;
2497                 case OP_IA64_FCMP_GT:
2498                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2499                         break;
2500                 case OP_IA64_FCMP_LE:
2501                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2502                         break;
2503                 case OP_IA64_FCMP_GE:
2504                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2505                         break;
2506                 case OP_IA64_FCMP_GT_UN:
2507                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2508                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2509                         break;
2510                 case OP_IA64_FCMP_LT_UN:
2511                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2512                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2513                         break;
2514                 case OP_IA64_FCMP_GE_UN:
2515                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2516                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2517                         break;
2518                 case OP_IA64_FCMP_LE_UN:
2519                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2520                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2521                         break;
2522
2523                 case OP_COND_EXC_IOV:
2524                 case OP_COND_EXC_OV:
2525                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2526                         break;
2527                 case OP_COND_EXC_IC:
2528                 case OP_COND_EXC_C:
2529                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2530                         break;
2531                 case OP_IA64_COND_EXC:
2532                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2533                         break;
2534                 case OP_IA64_CSET:
2535                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2536                         ia64_no_stop (code);
2537                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2538                         break;
2539                 case OP_ICONV_TO_I1:
2540                 case OP_LCONV_TO_I1:
2541                         /* FIXME: Is this needed ? */
2542                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2543                         break;
2544                 case OP_ICONV_TO_I2:
2545                 case OP_LCONV_TO_I2:
2546                         /* FIXME: Is this needed ? */
2547                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2548                         break;
2549                 case OP_LCONV_TO_I4:
2550                         /* FIXME: Is this needed ? */
2551                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2552                         break;
2553                 case OP_ICONV_TO_U1:
2554                 case OP_LCONV_TO_U1:
2555                         /* FIXME: Is this needed */
2556                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2557                         break;
2558                 case OP_ICONV_TO_U2:
2559                 case OP_LCONV_TO_U2:
2560                         /* FIXME: Is this needed */
2561                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2562                         break;
2563                 case OP_LCONV_TO_U4:
2564                         /* FIXME: Is this needed */
2565                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2566                         break;
2567                 case OP_ICONV_TO_I8:
2568                 case OP_ICONV_TO_I:
2569                 case OP_LCONV_TO_I8:
2570                 case OP_LCONV_TO_I:
2571                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2572                         break;
2573                 case OP_LCONV_TO_U8:
2574                 case OP_LCONV_TO_U:
2575                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2576                         break;
2577
2578                         /*
2579                          * FLOAT OPCODES
2580                          */
2581                 case OP_R8CONST: {
2582                         double d = *(double *)ins->inst_p0;
2583
2584                         if ((d == 0.0) && (mono_signbit (d) == 0))
2585                                 ia64_fmov (code, ins->dreg, 0);
2586                         else if (d == 1.0)
2587                                 ia64_fmov (code, ins->dreg, 1);
2588                         else {
2589                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2590                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2591                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2592                         }
2593                         break;
2594                 }
2595                 case OP_R4CONST: {
2596                         float f = *(float *)ins->inst_p0;
2597
2598                         if ((f == 0.0) && (mono_signbit (f) == 0))
2599                                 ia64_fmov (code, ins->dreg, 0);
2600                         else if (f == 1.0)
2601                                 ia64_fmov (code, ins->dreg, 1);
2602                         else {
2603                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2604                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2605                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2606                         }
2607                         break;
2608                 }
2609                 case OP_FMOVE:
2610                         ia64_fmov (code, ins->dreg, ins->sreg1);
2611                         break;
2612                 case OP_STORER8_MEMBASE_REG:
2613                         if (ins->inst_offset != 0) {
2614                                 /* This is generated by local regalloc */
2615                                 if (ia64_is_imm14 (ins->inst_offset)) {
2616                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2617                                 } else {
2618                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2619                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2620                                 }
2621                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2622                         }
2623                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2624                         break;
2625                 case OP_STORER4_MEMBASE_REG:
2626                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2627                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2628                         break;
2629                 case OP_LOADR8_MEMBASE:
2630                         if (ins->inst_offset != 0) {
2631                                 /* This is generated by local regalloc */
2632                                 if (ia64_is_imm14 (ins->inst_offset)) {
2633                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2634                                 } else {
2635                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2636                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2637                                 }
2638                                 ins->inst_basereg = GP_SCRATCH_REG;
2639                         }
2640                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2641                         break;
2642                 case OP_LOADR4_MEMBASE:
2643                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2644                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2645                         break;
2646                 case OP_ICONV_TO_R4:
2647                 case OP_LCONV_TO_R4:
2648                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2649                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2650                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2651                         break;
2652                 case OP_ICONV_TO_R8:
2653                 case OP_LCONV_TO_R8:
2654                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2655                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2656                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2657                         break;
2658                 case OP_FCONV_TO_R4:
2659                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2660                         break;
2661                 case OP_FCONV_TO_I8:
2662                 case OP_FCONV_TO_I:
2663                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2664                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2665                         break;
2666                 case OP_FADD:
2667                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2668                         break;
2669                 case OP_FSUB:
2670                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2671                         break;
2672                 case OP_FMUL:
2673                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2674                         break;
2675                 case OP_FNEG:
2676                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2677                         break;
2678                 case OP_CKFINITE:
2679                         /* Quiet NaN */
2680                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2681                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2682                         /* Signaling NaN */
2683                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2684                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2685                         /* Positive infinity */
2686                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2687                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2688                         /* Negative infinity */
2689                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2690                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2691                         break;
2692
2693                 /* Calls */
2694                 case OP_CHECK_THIS:
2695                         /* ensure ins->sreg1 is not NULL */
2696                         /* Can't use ld8 as this could be a vtype address */
2697                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2698                         break;
2699                 case OP_ARGLIST:
2700                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2701                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2702                         break;
2703                 case OP_FCALL:
2704                 case OP_LCALL:
2705                 case OP_VCALL:
2706                 case OP_VCALL2:
2707                 case OP_VOIDCALL:
2708                 case OP_CALL:
2709                         call = (MonoCallInst*)ins;
2710
2711                         if (ins->flags & MONO_INST_HAS_METHOD)
2712                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2713                         else
2714                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2715
2716                         code = emit_move_return_value (cfg, ins, code);
2717                         break;
2718
2719                 case OP_CALL_REG:
2720                 case OP_FCALL_REG:
2721                 case OP_LCALL_REG:
2722                 case OP_VCALL_REG:
2723                 case OP_VCALL2_REG:
2724                 case OP_VOIDCALL_REG: {
2725                         MonoCallInst *call = (MonoCallInst*)ins;
2726                         CallInfo *cinfo;
2727                         int out_reg;
2728
2729                         /*
2730                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2731                          * register.
2732                          */
2733                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2734                         out_reg = cfg->arch.reg_out0;
2735                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2736                                 out_reg ++;
2737                         ia64_mov (code, IA64_R10, out_reg);
2738
2739                         /* Indirect call */
2740                         ia64_mov (code, IA64_R8, ins->sreg1);
2741                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2742                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2743                         ia64_ld8 (code, IA64_GP, IA64_R8);
2744                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2745
2746                         code = emit_move_return_value (cfg, ins, code);
2747                         break;
2748                 }
2749                 case OP_FCALL_MEMBASE:
2750                 case OP_LCALL_MEMBASE:
2751                 case OP_VCALL_MEMBASE:
2752                 case OP_VCALL2_MEMBASE:
2753                 case OP_VOIDCALL_MEMBASE:
2754                 case OP_CALL_MEMBASE: {
2755                         MonoCallInst *call = (MonoCallInst*)ins;
2756                         CallInfo *cinfo;
2757                         int out_reg;
2758
2759                         ia64_mov (code, IA64_R11, ins->sreg1);
2760                         if (ia64_is_imm14 (ins->inst_offset))
2761                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2762                         else {
2763                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2764                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2765                         }
2766
2767                         if (call->method && ins->inst_offset < 0) {
2768                                 /*
2769                                  * This is a possible IMT call so save the IMT method in a global
2770                                  * register where mono_arch_find_imt_method () and its friends can
2771                                  * access it.
2772                                  */
2773                                 ia64_movl (code, IA64_R9, call->method);
2774                         }
2775
2776                         /*
2777                          * mono_arch_find_this_arg () needs to find the this argument in a global
2778                          * register.
2779                          */
2780                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2781                         out_reg = cfg->arch.reg_out0;
2782                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2783                                 out_reg ++;
2784                         ia64_mov (code, IA64_R10, out_reg);
2785
2786                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2787
2788                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2789
2790                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2791
2792                         code = emit_move_return_value (cfg, ins, code);
2793                         break;
2794                 }
2795                 case OP_JMP: {
2796                         /*
2797                          * Keep in sync with the code in emit_epilog.
2798                          */
2799
2800                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2801                                 NOT_IMPLEMENTED;
2802
2803                         g_assert (!cfg->method->save_lmf);
2804
2805                         /* Load arguments into their original registers */
2806                         code = emit_load_volatile_arguments (cfg, code);
2807
2808                         if (cfg->arch.stack_alloc_size) {
2809                                 if (cfg->arch.omit_fp) {
2810                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2811                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2812                                         else {
2813                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2814                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2815                                         }
2816                                 }
2817                                 else
2818                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2819                         }
2820                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2821                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2822
2823                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2824                         ia64_movl (code, GP_SCRATCH_REG, 0);
2825                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2826                         ia64_br_cond_reg (code, IA64_B6);
2827
2828                         break;
2829                 }
2830                 case OP_BREAK:
2831                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2832                         break;
2833
2834                 case OP_LOCALLOC: {
2835                         gint32 abi_offset;
2836
2837                         /* FIXME: Sigaltstack support */
2838
2839                         /* keep alignment */
2840                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2841                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2842                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2843
2844                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2845
2846                         ia64_mov (code, ins->dreg, IA64_SP);
2847
2848                         /* An area at sp is reserved by the ABI for parameter passing */
2849                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2850                         if (ia64_is_adds_imm (abi_offset))
2851                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2852                         else {
2853                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2854                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2855                         }
2856
2857                         if (ins->flags & MONO_INST_INIT) {
2858                                 /* Upper limit */
2859                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2860
2861                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2862
2863                                 /* Init loop */
2864                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2865                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2866                                 ia64_br_cond_pred (code, 8, -2);
2867
2868                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2869
2870                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2871                         }
2872
2873                         break;
2874                 }
2875                 case OP_LOCALLOC_IMM: {
2876                         gint32 abi_offset;
2877
2878                         /* FIXME: Sigaltstack support */
2879
2880                         gssize size = ins->inst_imm;
2881                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2882
2883                         if (ia64_is_adds_imm (size))
2884                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2885                         else
2886                                 ia64_movl (code, GP_SCRATCH_REG, size);
2887
2888                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2889                         ia64_mov (code, ins->dreg, IA64_SP);
2890
2891                         /* An area at sp is reserved by the ABI for parameter passing */
2892                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2893                         if (ia64_is_adds_imm (abi_offset))
2894                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2895                         else {
2896                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2897                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2898                         }
2899
2900                         if (ins->flags & MONO_INST_INIT) {
2901                                 /* Upper limit */
2902                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2903
2904                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2905
2906                                 /* Init loop */
2907                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2908                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2909                                 ia64_br_cond_pred (code, 8, -2);
2910
2911                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2912
2913                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2914                         }
2915
2916                         break;
2917                 }
2918                 case OP_TLS_GET:
2919                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2920                         ia64_ld8 (code, ins->dreg, ins->dreg);
2921                         break;
2922
2923                         /* Synchronization */
2924                 case OP_MEMORY_BARRIER:
2925                         ia64_mf (code);
2926                         break;
2927                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2928                         g_assert (ins->inst_offset == 0);
2929                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2930                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2931                         break;
2932                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2933                         g_assert (ins->inst_offset == 0);
2934                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2935                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2936                         break;
2937                 case OP_ATOMIC_EXCHANGE_I4:
2938                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2939                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2940                         break;
2941                 case OP_ATOMIC_EXCHANGE_I8:
2942                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2943                         break;
2944                 case OP_ATOMIC_ADD_NEW_I4: {
2945                         guint8 *label, *buf;
2946
2947                         /* From libatomic_ops */
2948                         ia64_mf (code);
2949
2950                         ia64_begin_bundle (code);
2951                         label = code.buf + code.nins;
2952                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2953                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2954                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2955                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2956                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2957                         buf = code.buf + code.nins;
2958                         ia64_br_cond_pred (code, 7, 0);
2959                         ia64_begin_bundle (code);
2960                         ia64_patch (buf, label);
2961                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2962                         break;
2963                 }
2964                 case OP_ATOMIC_ADD_NEW_I8: {
2965                         guint8 *label, *buf;
2966
2967                         /* From libatomic_ops */
2968                         ia64_mf (code);
2969
2970                         ia64_begin_bundle (code);
2971                         label = code.buf + code.nins;
2972                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2973                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2974                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2975                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2976                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2977                         buf = code.buf + code.nins;
2978                         ia64_br_cond_pred (code, 7, 0);
2979                         ia64_begin_bundle (code);
2980                         ia64_patch (buf, label);
2981                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2982                         break;
2983                 }
2984
2985                         /* Exception handling */
2986                 case OP_CALL_HANDLER:
2987                         /*
2988                          * Using a call instruction would mess up the register stack, so
2989                          * save the return address to a register and use a
2990                          * branch.
2991                          */
2992                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2993                         ia64_mov (code, IA64_R15, IA64_R0);
2994                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
2995                         /* Add the length of OP_CALL_HANDLER */
2996                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
2997                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2998                         ia64_movl (code, GP_SCRATCH_REG2, 0);
2999                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3000                         ia64_br_cond_reg (code, IA64_B6);
3001                         // FIXME:
3002                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3003                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3004                         break;
3005                 case OP_START_HANDLER: {
3006                         /*
3007                          * We receive the return address in GP_SCRATCH_REG.
3008                          */
3009                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3010
3011                         /*
3012                          * R15 determines our caller. It is used since it is writable using
3013                          * libunwind.
3014                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3015                          * R15 != 0 means we are called by call_filter ().
3016                          */
3017                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3018                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3019
3020                         ia64_br_cond_pred (code, 6, 6);
3021
3022                         /*
3023                          * Called by call_filter:
3024                          * Allocate a new stack frame, and set the fp register from the
3025                          * value passed in by the caller.
3026                          * We allocate a similar frame as is done by the prolog, so
3027                          * if an exception is thrown while executing the filter, the
3028                          * unwinder can unwind through the filter frame using the unwind
3029                          * info for the prolog.
3030                          */
3031                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3032                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3033                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3034                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3035                         /* Signal to endfilter that we are called by call_filter */
3036                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3037
3038                         /* Branch target: */
3039                         if (ia64_is_imm14 (spvar->inst_offset))
3040                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3041                         else {
3042                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3043                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3044                         }
3045
3046                         /* Save the return address */
3047                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3048                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3049
3050                         break;
3051                 }
3052                 case OP_ENDFINALLY:
3053                 case OP_ENDFILTER: {
3054                         /* FIXME: Return the value in ENDFILTER */
3055                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3056
3057                         /* Load the return address */
3058                         if (ia64_is_imm14 (spvar->inst_offset)) {
3059                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3060                         } else {
3061                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3062                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3063                         }
3064                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3065
3066                         /* Test caller */
3067                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3068                         ia64_br_cond_pred (code, 7, 4);
3069
3070                         /* Called by call_filter */
3071                         /* Pop frame */
3072                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3073                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3074                         ia64_br_ret_reg (code, IA64_B0);
3075
3076                         /* Called by CALL_HANDLER */
3077                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3078                         ia64_br_cond_reg (code, IA64_B6);
3079                         break;
3080                 }
3081                 case OP_THROW:
3082                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3083                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3084                                                           (gpointer)"mono_arch_throw_exception");
3085
3086                         /*
3087                          * This might be the last instruction in the method, so add a dummy
3088                          * instruction so the unwinder will work.
3089                          */
3090                         ia64_break_i (code, 0);
3091                         break;
3092                 case OP_RETHROW:
3093                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3094                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3095                                                           (gpointer)"mono_arch_rethrow_exception");
3096
3097                         ia64_break_i (code, 0);
3098                         break;
3099
3100                 default:
3101                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3102                         g_assert_not_reached ();
3103                 }
3104
3105                 if ((code.buf - cfg->native_code - offset) > max_len) {
3106                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3107                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3108                         g_assert_not_reached ();
3109                 }
3110
3111                 cpos += max_len;
3112
3113                 last_ins = ins;
3114                 last_offset = offset;
3115         }
3116
3117         ia64_codegen_close (code);
3118
3119         cfg->code_len = code.buf - cfg->native_code;
3120 }
3121
3122 void
3123 mono_arch_register_lowlevel_calls (void)
3124 {
3125 }
3126
3127 static Ia64InsType ins_types_in_template [32][3] = {
3128         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3129         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3130         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3131         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3132         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3133         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3134         {0, 0, 0},
3135         {0, 0, 0},
3136         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3137         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3138         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3145         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3148         {0, 0, 0},
3149         {0, 0, 0},
3150         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3151         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3154         {0, 0, 0},
3155         {0, 0, 0},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3158         {0, 0, 0},
3159         {0, 0, 0}
3160 };
3161
3162 static gboolean stops_in_template [32][3] = {
3163         { FALSE, FALSE, FALSE },
3164         { FALSE, FALSE, TRUE },
3165         { FALSE, TRUE, FALSE },
3166         { FALSE, TRUE, TRUE },
3167         { FALSE, FALSE, FALSE },
3168         { FALSE, FALSE, TRUE },
3169         { FALSE, FALSE, FALSE },
3170         { FALSE, FALSE, FALSE },
3171
3172         { FALSE, FALSE, FALSE },
3173         { FALSE, FALSE, TRUE },
3174         { TRUE, FALSE, FALSE },
3175         { TRUE, FALSE, TRUE },
3176         { FALSE, FALSE, FALSE },
3177         { FALSE, FALSE, TRUE },
3178         { FALSE, FALSE, FALSE },
3179         { FALSE, FALSE, TRUE },
3180
3181         { FALSE, FALSE, FALSE },
3182         { FALSE, FALSE, TRUE },
3183         { FALSE, FALSE, FALSE },
3184         { FALSE, FALSE, TRUE },
3185         { FALSE, FALSE, FALSE },
3186         { FALSE, FALSE, FALSE },
3187         { FALSE, FALSE, FALSE },
3188         { FALSE, FALSE, TRUE },
3189
3190         { FALSE, FALSE, FALSE },
3191         { FALSE, FALSE, TRUE },
3192         { FALSE, FALSE, FALSE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, FALSE },
3195         { FALSE, FALSE, TRUE },
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, FALSE }
3198 };
3199
3200 static int last_stop_in_template [32] = {
3201         -1, 2, 1, 2, -1, 2, -1, -1,
3202         -1, 2, 0, 2, -1, 2, -1, 2,
3203         -1, 2, -1, 2, -1, -1, -1, 2,
3204         -1, 2, -1, -1, -1, 2, -1, -1
3205 };
3206
3207 static guint64 nops_for_ins_types [6] = {
3208         IA64_NOP_I,
3209         IA64_NOP_I,
3210         IA64_NOP_M,
3211         IA64_NOP_F,
3212         IA64_NOP_B,
3213         IA64_NOP_X
3214 };
3215
3216 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3217
3218 /*
3219  * Debugging support
3220  */
3221
3222 #if 0
3223 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3224 #else
3225 #define DEBUG_INS_SCHED(a)
3226 #endif
3227
3228 static void
3229 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3230 {
3231         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3232         guint8 *deps = code->dep_info;
3233         gboolean need_stop, no_stop;
3234
3235         for (i = 0; i < code->nins; ++i)
3236                 stops [i] = FALSE;
3237
3238         ins_index = 0;
3239         current_deps_start = 0;
3240         current_ins_start = 0;
3241         deps_start [ins_index] = current_ins_start;
3242         pos = 0;
3243         no_stop = FALSE;
3244         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3245         while (pos < code->dep_info_pos) {
3246                 need_stop = FALSE;
3247                 switch (deps [pos]) {
3248                 case IA64_END_OF_INS:
3249                         ins_index ++;
3250                         current_ins_start = pos + 2;
3251                         deps_start [ins_index] = current_ins_start;
3252                         no_stop = FALSE;
3253                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3254                         break;
3255                 case IA64_NONE:
3256                         break;
3257                 case IA64_READ_GR:
3258                         reg = deps [pos + 1];
3259
3260                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3261                         for (i = current_deps_start; i < current_ins_start; i += 2)
3262                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3263                                         need_stop = TRUE;
3264                         break;
3265                 case IA64_WRITE_GR:
3266                         reg = code->dep_info [pos + 1];
3267
3268                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3269                         for (i = current_deps_start; i < current_ins_start; i += 2)
3270                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3271                                         need_stop = TRUE;
3272                         break;
3273                 case IA64_READ_PR:
3274                         reg = deps [pos + 1];
3275
3276                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3277                         for (i = current_deps_start; i < current_ins_start; i += 2)
3278                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3279                                         need_stop = TRUE;
3280                         break;
3281                 case IA64_READ_PR_BRANCH:
3282                         reg = deps [pos + 1];
3283
3284                         /* Writes to prs by non-float instructions are visible to branches */
3285                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3286                         for (i = current_deps_start; i < current_ins_start; i += 2)
3287                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3288                                         need_stop = TRUE;
3289                         break;
3290                 case IA64_WRITE_PR:
3291                         reg = code->dep_info [pos + 1];
3292
3293                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3294                         for (i = current_deps_start; i < current_ins_start; i += 2)
3295                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3296                                         need_stop = TRUE;
3297                         break;
3298                 case IA64_WRITE_PR_FLOAT:
3299                         reg = code->dep_info [pos + 1];
3300
3301                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3302                         for (i = current_deps_start; i < current_ins_start; i += 2)
3303                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3304                                         need_stop = TRUE;
3305                         break;
3306                 case IA64_READ_BR:
3307                         reg = deps [pos + 1];
3308
3309                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3310                         for (i = current_deps_start; i < current_ins_start; i += 2)
3311                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3312                                         need_stop = TRUE;
3313                         break;
3314                 case IA64_WRITE_BR:
3315                         reg = code->dep_info [pos + 1];
3316
3317                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3318                         for (i = current_deps_start; i < current_ins_start; i += 2)
3319                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3320                                         need_stop = TRUE;
3321                         break;
3322                 case IA64_READ_BR_BRANCH:
3323                         reg = deps [pos + 1];
3324
3325                         /* Writes to brs are visible to branches */
3326                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3327                         break;
3328                 case IA64_READ_FR:
3329                         reg = deps [pos + 1];
3330
3331                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3332                         for (i = current_deps_start; i < current_ins_start; i += 2)
3333                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3334                                         need_stop = TRUE;
3335                         break;
3336                 case IA64_WRITE_FR:
3337                         reg = code->dep_info [pos + 1];
3338
3339                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3340                         for (i = current_deps_start; i < current_ins_start; i += 2)
3341                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3342                                         need_stop = TRUE;
3343                         break;
3344                 case IA64_READ_AR:
3345                         reg = deps [pos + 1];
3346
3347                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3348                         for (i = current_deps_start; i < current_ins_start; i += 2)
3349                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3350                                         need_stop = TRUE;
3351                         break;
3352                 case IA64_WRITE_AR:
3353                         reg = code->dep_info [pos + 1];
3354
3355                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3356                         for (i = current_deps_start; i < current_ins_start; i += 2)
3357                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3358                                         need_stop = TRUE;
3359                         break;
3360                 case IA64_NO_STOP:
3361                         /*
3362                          * Explicitly indicate that a stop is not required. Useful for
3363                          * example when two predicated instructions with negated predicates
3364                          * write the same registers.
3365                          */
3366                         no_stop = TRUE;
3367                         break;
3368                 default:
3369                         g_assert_not_reached ();
3370                 }
3371                 pos += 2;
3372
3373                 if (need_stop && !no_stop) {
3374                         g_assert (ins_index > 0);
3375                         stops [ins_index - 1] = 1;
3376
3377                         DEBUG_INS_SCHED (printf ("STOP\n"));
3378                         current_deps_start = current_ins_start;
3379
3380                         /* Skip remaining deps for this instruction */
3381                         while (deps [pos] != IA64_END_OF_INS)
3382                                 pos += 2;
3383                 }
3384         }
3385
3386         if (code->nins > 0) {
3387                 /* No dependency info for the last instruction */
3388                 stops [code->nins - 1] = 1;
3389         }
3390
3391         deps_start [code->nins] = code->dep_info_pos;
3392 }
3393
3394 static void
3395 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3396 {
3397         int stop_pos, i, deps_to_shift, dep_shift;
3398
3399         g_assert (n <= code->nins);
3400
3401         // if (n > 1) printf ("FOUND: %ld.\n", template);
3402
3403         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3404
3405         stop_pos = last_stop_in_template [template] + 1;
3406         if (stop_pos > n)
3407                 stop_pos = n;
3408
3409         /* Compute the number of 'real' instructions before the stop */
3410         deps_to_shift = stop_pos;
3411         if (stop_pos >= 3 && (nops & (1 << 2)))
3412                 deps_to_shift --;
3413         if (stop_pos >= 2 && (nops & (1 << 1)))
3414                 deps_to_shift --;
3415         if (stop_pos >= 1 && (nops & (1 << 0)))
3416                 deps_to_shift --;
3417
3418         /*
3419          * We have to keep some dependencies whose instructions have been shifted
3420          * out of the buffer. So nullify the end_of_ins markers in the dependency
3421          * array.
3422          */
3423         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3424                 if (code->dep_info [i] == IA64_END_OF_INS)
3425                         code->dep_info [i] = IA64_NONE;
3426
3427         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3428         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3429         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3430
3431         dep_shift = deps_start [deps_to_shift];
3432         for (i = 0; i < code->nins + 1 - n; ++i)
3433                 deps_start [i] = deps_start [n + i] - dep_shift;
3434
3435         /* Determine the exact positions of instructions with unwind ops */
3436         if (code->unw_op_count) {
3437                 int ins_pos [16];
3438                 int curr_ins, curr_ins_pos;
3439
3440                 curr_ins = 0;
3441                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3442                 for (i = 0; i < 3; ++i) {
3443                         if (! (nops & (1 << i))) {
3444                                 ins_pos [curr_ins] = curr_ins_pos + i;
3445                                 curr_ins ++;
3446                         }
3447                 }
3448
3449                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3450                         if (code->unw_ops_pos [i] < n) {
3451                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3452                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3453                         }
3454                 }
3455                 if (code->unw_op_pos < code->unw_op_count)
3456                         code->unw_op_pos += n;
3457         }
3458
3459         if (n == code->nins) {
3460                 code->template = 0;
3461                 code->nins = 0;
3462         }
3463         else {
3464                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3465                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3466                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3467                 code->nins -= n;
3468         }
3469 }
3470
3471 void
3472 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3473 {
3474         int i, ins_type, template, nins_to_emit;
3475         int deps_start [16];
3476         int stops [16];
3477         gboolean found;
3478
3479         /*
3480          * We implement a simple scheduler which tries to put three instructions
3481          * per bundle, then two, then one.
3482          */
3483         ia64_analyze_deps (code, deps_start, stops);
3484
3485         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3486                 /* Find a suitable template */
3487                 for (template = 0; template < 32; ++template) {
3488                         if (stops_in_template [template][0] != stops [0] ||
3489                                 stops_in_template [template][1] != stops [1] ||
3490                                 stops_in_template [template][2] != stops [2])
3491                                 continue;
3492
3493                         found = TRUE;
3494                         for (i = 0; i < 3; ++i) {
3495                                 ins_type = ins_types_in_template [template][i];
3496                                 switch (code->itypes [i]) {
3497                                 case IA64_INS_TYPE_A:
3498                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3499                                         break;
3500                                 default:
3501                                         found &= (ins_type == code->itypes [i]);
3502                                         break;
3503                                 }
3504                         }
3505
3506                         if (found)
3507                                 found = debug_ins_sched ();
3508
3509                         if (found) {
3510                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3511                                 break;
3512                         }
3513                 }
3514         }
3515
3516         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3517                 /* Wait for more instructions */
3518                 return;
3519
3520         /* If it didn't work out, try putting two instructions into one bundle */
3521         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3522                 /* Try a nop at the end */
3523                 for (template = 0; template < 32; ++template) {
3524                         if (stops_in_template [template][0] != stops [0] ||
3525                                 ((stops_in_template [template][1] != stops [1]) &&
3526                                  (stops_in_template [template][2] != stops [1])))
3527
3528                                 continue;
3529
3530                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3531                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3532                                 continue;
3533
3534                         if (!debug_ins_sched ())
3535                                 continue;
3536
3537                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3538                         break;
3539                 }
3540         }
3541
3542         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3543                 /* Wait for more instructions */
3544                 return;
3545
3546         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3547                 /* Try a nop in the middle */
3548                 for (template = 0; template < 32; ++template) {
3549                         if (((stops_in_template [template][0] != stops [0]) &&
3550                                  (stops_in_template [template][1] != stops [0])) ||
3551                                 stops_in_template [template][2] != stops [1])
3552                                 continue;
3553
3554                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3555                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3556                                 continue;
3557
3558                         if (!debug_ins_sched ())
3559                                 continue;
3560
3561                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3562                         break;
3563                 }
3564         }
3565
3566         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3567                 /* Try a nop at the beginning */
3568                 for (template = 0; template < 32; ++template) {
3569                         if ((stops_in_template [template][1] != stops [0]) ||
3570                                 (stops_in_template [template][2] != stops [1]))
3571                                 continue;
3572
3573                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3574                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3575                                 continue;
3576
3577                         if (!debug_ins_sched ())
3578                                 continue;
3579
3580                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3581                         break;
3582                 }
3583         }
3584
3585         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3586                 /* Wait for more instructions */
3587                 return;
3588
3589         if (flush)
3590                 nins_to_emit = code->nins;
3591         else
3592                 nins_to_emit = 1;
3593
3594         while (nins_to_emit > 0) {
3595                 if (!debug_ins_sched ())
3596                         stops [0] = 1;
3597                 switch (code->itypes [0]) {
3598                 case IA64_INS_TYPE_A:
3599                         if (stops [0])
3600                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3601                         else
3602                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3603                         break;
3604                 case IA64_INS_TYPE_I:
3605                         if (stops [0])
3606                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3607                         else
3608                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3609                         break;
3610                 case IA64_INS_TYPE_M:
3611                         if (stops [0])
3612                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3613                         else
3614                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3615                         break;
3616                 case IA64_INS_TYPE_B:
3617                         if (stops [0])
3618                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3619                         else
3620                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3621                         break;
3622                 case IA64_INS_TYPE_F:
3623                         if (stops [0])
3624                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3625                         else
3626                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3627                         break;
3628                 case IA64_INS_TYPE_LX:
3629                         if (stops [0] || stops [1])
3630                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3631                         else
3632                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3633                         nins_to_emit --;
3634                         break;
3635                 default:
3636                         g_assert_not_reached ();
3637                 }
3638                 nins_to_emit --;
3639         }
3640 }
3641
3642 unw_dyn_region_info_t*
3643 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3644 {
3645         unw_dyn_region_info_t *r;
3646
3647         g_assert (code->nins == 0);
3648         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3649         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3650         r->op_count = code->unw_op_count;
3651         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3652         code->unw_op_count = 0;
3653         code->unw_op_pos = 0;
3654         code->region_start = code->buf;
3655
3656         return r;
3657 }
3658
3659 static void
3660 ia64_patch (unsigned char* code, gpointer target)
3661 {
3662         int template, i;
3663         guint64 instructions [3];
3664         guint8 gen_buf [16];
3665         Ia64CodegenState gen;
3666         int ins_to_skip;
3667         gboolean found;
3668
3669         /*
3670          * code encodes both the position inside the buffer and code.nins when
3671          * the instruction was emitted.
3672          */
3673         ins_to_skip = (guint64)code % 16;
3674         code = (unsigned char*)((guint64)code & ~15);
3675
3676         /*
3677          * Search for the first instruction which is 'patchable', skipping
3678          * ins_to_skip instructions.
3679          */
3680
3681         while (TRUE) {
3682
3683         template = ia64_bundle_template (code);
3684         instructions [0] = ia64_bundle_ins1 (code);
3685         instructions [1] = ia64_bundle_ins2 (code);
3686         instructions [2] = ia64_bundle_ins3 (code);
3687
3688         ia64_codegen_init (gen, gen_buf);
3689
3690         found = FALSE;
3691         for (i = 0; i < 3; ++i) {
3692                 guint64 ins = instructions [i];
3693                 int opcode = ia64_ins_opcode (ins);
3694
3695                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3696                         continue;
3697
3698                 if (ins_to_skip) {
3699                         ins_to_skip --;
3700                         continue;
3701                 }
3702
3703                 switch (ins_types_in_template [template][i]) {
3704                 case IA64_INS_TYPE_A:
3705                 case IA64_INS_TYPE_M:
3706                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3707                                 /* adds */
3708                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3709                                 instructions [i] = gen.instructions [0];
3710                                 found = TRUE;
3711                         }
3712                         else
3713                                 NOT_IMPLEMENTED;
3714                         break;
3715                 case IA64_INS_TYPE_B:
3716                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3717                                 /* br.cond */
3718                                 gint64 disp = ((guint8*)target - code) >> 4;
3719
3720                                 /* FIXME: hints */
3721                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3722
3723                                 instructions [i] = gen.instructions [0];
3724                                 found = TRUE;
3725                         }
3726                         else if (opcode == 5) {
3727                                 /* br.call */
3728                                 gint64 disp = ((guint8*)target - code) >> 4;
3729
3730                                 /* FIXME: hints */
3731                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3732                                 instructions [i] = gen.instructions [0];
3733                                 found = TRUE;
3734                         }
3735                         else
3736                                 NOT_IMPLEMENTED;
3737                         break;
3738                 case IA64_INS_TYPE_LX:
3739                         if (i == 1)
3740                                 break;
3741
3742                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3743                                 /* movl */
3744                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3745                                 instructions [1] = gen.instructions [0];
3746                                 instructions [2] = gen.instructions [1];
3747                                 found = TRUE;
3748                         }
3749                         else
3750                                 NOT_IMPLEMENTED;
3751
3752                         break;
3753                 default:
3754                         NOT_IMPLEMENTED;
3755                 }
3756
3757                 if (found) {
3758                         /* Rewrite code */
3759                         ia64_codegen_init (gen, code);
3760                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3761                         return;
3762                 }
3763         }
3764
3765         code += 16;
3766         }
3767 }
3768
3769 void
3770 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3771 {
3772         MonoJumpInfo *patch_info;
3773
3774         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3775                 unsigned char *ip = patch_info->ip.i + code;
3776                 const unsigned char *target;
3777
3778                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3779
3780                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3781                         continue;
3782                 if (mono_compile_aot) {
3783                         NOT_IMPLEMENTED;
3784                 }
3785
3786                 ia64_patch (ip, (gpointer)target);
3787         }
3788 }
3789
3790 guint8 *
3791 mono_arch_emit_prolog (MonoCompile *cfg)
3792 {
3793         MonoMethod *method = cfg->method;
3794         MonoMethodSignature *sig;
3795         MonoInst *inst;
3796         int alloc_size, pos, i;
3797         Ia64CodegenState code;
3798         CallInfo *cinfo;
3799
3800         sig = mono_method_signature (method);
3801         pos = 0;
3802
3803         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3804
3805         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3806
3807         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3808                 cfg->code_size += 1024;
3809         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3810                 cfg->code_size += 1024;
3811
3812         cfg->native_code = g_malloc (cfg->code_size);
3813
3814         ia64_codegen_init (code, cfg->native_code);
3815
3816         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3817         if (cfg->param_area)
3818                 alloc_size += cfg->param_area;
3819         if (alloc_size)
3820                 /* scratch area */
3821                 alloc_size += 16;
3822         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3823
3824         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3825                 /* Force sp to be saved/restored */
3826                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3827
3828         cfg->arch.stack_alloc_size = alloc_size;
3829
3830         pos = 0;
3831
3832         if (method->save_lmf) {
3833                 /* No LMF on IA64 */
3834         }
3835
3836         alloc_size -= pos;
3837
3838         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3839         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3840         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3841         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3842
3843         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3844                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3845                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3846                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3847                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3848         }
3849
3850         if (alloc_size) {
3851 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3852                 int pagesize = getpagesize ();
3853
3854                 if (alloc_size >= pagesize) {
3855                         gint32 remaining_size = alloc_size;
3856
3857                         /* Generate stack touching code */
3858                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3859                         while (remaining_size >= pagesize) {
3860                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3861                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3862                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3863                                 remaining_size -= pagesize;
3864                         }
3865                 }
3866 #endif
3867                 if (ia64_is_imm14 (-alloc_size)) {
3868                         if (cfg->arch.omit_fp)
3869                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3870                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3871                 }
3872                 else {
3873                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3874                         if (cfg->arch.omit_fp)
3875                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3876                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3877                 }
3878         }
3879
3880         ia64_begin_bundle (code);
3881
3882         /* Initialize unwind info */
3883         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3884
3885         if (sig->ret->type != MONO_TYPE_VOID) {
3886                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3887                         /* Save volatile arguments to the stack */
3888                         NOT_IMPLEMENTED;
3889                 }
3890         }
3891
3892         /* Keep this in sync with emit_load_volatile_arguments */
3893         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3894                 ArgInfo *ainfo = cinfo->args + i;
3895                 gint32 stack_offset;
3896                 MonoType *arg_type;
3897
3898                 inst = cfg->args [i];
3899
3900                 if (sig->hasthis && (i == 0))
3901                         arg_type = &mono_defaults.object_class->byval_arg;
3902                 else
3903                         arg_type = sig->params [i - sig->hasthis];
3904
3905                 arg_type = mono_type_get_underlying_type (arg_type);
3906
3907                 stack_offset = ainfo->offset + ARGS_OFFSET;
3908
3909                 /*
3910                  * FIXME: Native code might pass non register sized integers
3911                  * without initializing the upper bits.
3912                  */
3913                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3914                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3915
3916                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3917                         case OP_LOADI1_MEMBASE:
3918                                 ia64_sxt1 (code, reg, reg);
3919                                 break;
3920                         case OP_LOADU1_MEMBASE:
3921                                 ia64_zxt1 (code, reg, reg);
3922                                 break;
3923                         case OP_LOADI2_MEMBASE:
3924                                 ia64_sxt2 (code, reg, reg);
3925                                 break;
3926                         case OP_LOADU2_MEMBASE:
3927                                 ia64_zxt2 (code, reg, reg);
3928                                 break;
3929                         default:
3930                                 break;
3931                         }
3932                 }
3933
3934                 /* Save volatile arguments to the stack */
3935                 if (inst->opcode != OP_REGVAR) {
3936                         switch (ainfo->storage) {
3937                         case ArgInIReg:
3938                         case ArgInFloatReg:
3939                         case ArgInFloatRegR4:
3940                                 g_assert (inst->opcode == OP_REGOFFSET);
3941                                 if (ia64_is_adds_imm (inst->inst_offset))
3942                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3943                                 else {
3944                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3945                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3946                                 }
3947                                 if (arg_type->byref)
3948                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3949                                 else {
3950                                         switch (arg_type->type) {
3951                                         case MONO_TYPE_R4:
3952                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3953                                                 break;
3954                                         case MONO_TYPE_R8:
3955                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3956                                                 break;
3957                                         default:
3958                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3959                                                 break;
3960                                         }
3961                                 }
3962                                 break;
3963                         case ArgOnStack:
3964                                 break;
3965                         case ArgAggregate:
3966                                 if (ainfo->nslots != ainfo->nregs)
3967                                         NOT_IMPLEMENTED;
3968
3969                                 g_assert (inst->opcode == OP_REGOFFSET);
3970                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3971                                 for (i = 0; i < ainfo->nregs; ++i) {
3972                                         switch (ainfo->atype) {
3973                                         case AggregateNormal:
3974                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3975                                                 break;
3976                                         case AggregateSingleHFA:
3977                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3978                                                 break;
3979                                         case AggregateDoubleHFA:
3980                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3981                                                 break;
3982                                         default:
3983                                                 NOT_IMPLEMENTED;
3984                                         }
3985                                 }
3986                                 break;
3987                         default:
3988                                 g_assert_not_reached ();
3989                         }
3990                 }
3991
3992                 if (inst->opcode == OP_REGVAR) {
3993                         /* Argument allocated to (non-volatile) register */
3994                         switch (ainfo->storage) {
3995                         case ArgInIReg:
3996                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
3997                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
3998                                 break;
3999                         case ArgOnStack:
4000                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4001                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4002                                 break;
4003                         default:
4004                                 NOT_IMPLEMENTED;
4005                         }
4006                 }
4007         }
4008
4009         if (method->save_lmf) {
4010                 /* No LMF on IA64 */
4011         }
4012
4013         ia64_codegen_close (code);
4014
4015         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4016                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4017
4018         cfg->code_len = code.buf - cfg->native_code;
4019
4020         g_assert (cfg->code_len < cfg->code_size);
4021
4022         cfg->arch.prolog_end_offset = cfg->code_len;
4023
4024         return code.buf;
4025 }
4026
4027 void
4028 mono_arch_emit_epilog (MonoCompile *cfg)
4029 {
4030         MonoMethod *method = cfg->method;
4031         int i, pos;
4032         int max_epilog_size = 16 * 4;
4033         Ia64CodegenState code;
4034         guint8 *buf;
4035         CallInfo *cinfo;
4036         ArgInfo *ainfo;
4037
4038         if (mono_jit_trace_calls != NULL)
4039                 max_epilog_size += 1024;
4040
4041         cfg->arch.epilog_begin_offset = cfg->code_len;
4042
4043         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4044                 cfg->code_size *= 2;
4045                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4046                 mono_jit_stats.code_reallocs++;
4047         }
4048
4049         /* FIXME: Emit unwind info */
4050
4051         buf = cfg->native_code + cfg->code_len;
4052
4053         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4054                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4055
4056         ia64_codegen_init (code, buf);
4057
4058         /* the code restoring the registers must be kept in sync with OP_JMP */
4059         pos = 0;
4060
4061         if (method->save_lmf) {
4062                 /* No LMF on IA64 */
4063         }
4064
4065         /* Load returned vtypes into registers if needed */
4066         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4067         ainfo = &cinfo->ret;
4068         switch (ainfo->storage) {
4069         case ArgAggregate:
4070                 if (ainfo->nslots != ainfo->nregs)
4071                         NOT_IMPLEMENTED;
4072
4073                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4074                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4075                 for (i = 0; i < ainfo->nregs; ++i) {
4076                         switch (ainfo->atype) {
4077                         case AggregateNormal:
4078                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4079                                 break;
4080                         case AggregateSingleHFA:
4081                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4082                                 break;
4083                         case AggregateDoubleHFA:
4084                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4085                                 break;
4086                         default:
4087                                 g_assert_not_reached ();
4088                         }
4089                 }
4090                 break;
4091         default:
4092                 break;
4093         }
4094
4095         ia64_begin_bundle (code);
4096
4097         code.region_start = cfg->native_code;
4098
4099         /* Label the unwind state at the start of the exception throwing region */
4100         //ia64_unw_label_state (code, 1234);
4101
4102         if (cfg->arch.stack_alloc_size) {
4103                 if (cfg->arch.omit_fp) {
4104                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4105                                 ia64_unw_pop_frames (code, 1);
4106                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4107                         } else {
4108                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4109                                 ia64_unw_pop_frames (code, 1);
4110                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4111                         }
4112                 }
4113                 else {
4114                         ia64_unw_pop_frames (code, 1);
4115                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4116                 }
4117         }
4118         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4119         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4120         ia64_br_ret_reg (code, IA64_B0);
4121
4122         ia64_codegen_close (code);
4123
4124         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4125         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4126
4127         cfg->code_len = code.buf - cfg->native_code;
4128
4129         g_assert (cfg->code_len < cfg->code_size);
4130 }
4131
4132 void
4133 mono_arch_emit_exceptions (MonoCompile *cfg)
4134 {
4135         MonoJumpInfo *patch_info;
4136         int i, nthrows;
4137         Ia64CodegenState code;
4138         gboolean empty = TRUE;
4139         //unw_dyn_region_info_t *r_exceptions;
4140         MonoClass *exc_classes [16];
4141         guint8 *exc_throw_start [16], *exc_throw_end [16];
4142         guint32 code_size = 0;
4143
4144         /* Compute needed space */
4145         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4146                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4147                         code_size += 256;
4148                 if (patch_info->type == MONO_PATCH_INFO_R8)
4149                         code_size += 8 + 7; /* sizeof (double) + alignment */
4150                 if (patch_info->type == MONO_PATCH_INFO_R4)
4151                         code_size += 4 + 7; /* sizeof (float) + alignment */
4152         }
4153
4154         if (code_size == 0)
4155                 return;
4156
4157         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4158                 cfg->code_size *= 2;
4159                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4160                 mono_jit_stats.code_reallocs++;
4161         }
4162
4163         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4164
4165         /* The unwind state here is the same as before the epilog */
4166         //ia64_unw_copy_state (code, 1234);
4167
4168         /* add code to raise exceptions */
4169         /* FIXME: Optimize this */
4170         nthrows = 0;
4171         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4172                 switch (patch_info->type) {
4173                 case MONO_PATCH_INFO_EXC: {
4174                         MonoClass *exc_class;
4175                         guint8* throw_ip;
4176                         guint8* buf;
4177                         guint64 exc_token_index;
4178
4179                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4180                         g_assert (exc_class);
4181                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4182                         throw_ip = cfg->native_code + patch_info->ip.i;
4183
4184                         ia64_begin_bundle (code);
4185
4186                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4187
4188                         /* Find a throw sequence for the same exception class */
4189                         for (i = 0; i < nthrows; ++i)
4190                                 if (exc_classes [i] == exc_class)
4191                                         break;
4192
4193                         if (i < nthrows) {
4194                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4195
4196                                 if (ia64_is_adds_imm (offset))
4197                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4198                                 else
4199                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4200
4201                                 buf = code.buf + code.nins;
4202                                 ia64_br_cond_pred (code, 0, 0);
4203                                 ia64_begin_bundle (code);
4204                                 ia64_patch (buf, exc_throw_start [i]);
4205
4206                                 patch_info->type = MONO_PATCH_INFO_NONE;
4207                         }
4208                         else {
4209                                 /* Arg1 */
4210                                 buf = code.buf;
4211                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4212
4213                                 ia64_begin_bundle (code);
4214
4215                                 if (nthrows < 16) {
4216                                         exc_classes [nthrows] = exc_class;
4217                                         exc_throw_start [nthrows] = code.buf;
4218                                 }
4219
4220                                 /* Arg2 */
4221                                 if (ia64_is_adds_imm (exc_token_index))
4222                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4223                                 else
4224                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4225
4226                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4227                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4228                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4229
4230                                 /* Indirect call */
4231                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4232                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4233                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4234                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4235
4236                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4237
4238                                 /* Patch up the throw offset */
4239                                 ia64_begin_bundle (code);
4240
4241                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4242
4243                                 if (nthrows < 16) {
4244                                         exc_throw_end [nthrows] = code.buf;
4245                                         nthrows ++;
4246                                 }
4247                         }
4248
4249                         empty = FALSE;
4250                         break;
4251                 }
4252                 default:
4253                         break;
4254                 }
4255         }
4256
4257         if (!empty)
4258                 /* The unwinder needs this to work */
4259                 ia64_break_i (code, 0);
4260
4261         ia64_codegen_close (code);
4262
4263         /* FIXME: */
4264         //r_exceptions = mono_ia64_create_unwind_region (&code);
4265         //cfg->arch.r_epilog = r_exceptions;
4266
4267         cfg->code_len = code.buf - cfg->native_code;
4268
4269         g_assert (cfg->code_len < cfg->code_size);
4270 }
4271
4272 void*
4273 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4274 {
4275         Ia64CodegenState code;
4276         CallInfo *cinfo = NULL;
4277         MonoMethodSignature *sig;
4278         MonoInst *ins;
4279         int i, n, stack_area = 0;
4280
4281         ia64_codegen_init (code, p);
4282
4283         /* Keep this in sync with mono_arch_get_argument_info */
4284
4285         if (enable_arguments) {
4286                 /* Allocate a new area on the stack and save arguments there */
4287                 sig = mono_method_signature (cfg->method);
4288
4289                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4290
4291                 n = sig->param_count + sig->hasthis;
4292
4293                 stack_area = ALIGN_TO (n * 8, 16);
4294
4295                 if (n) {
4296                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4297
4298                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4299
4300                         /* FIXME: Allocate out registers */
4301
4302                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4303
4304                         /* Required by the ABI */
4305                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4306
4307                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4308                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4309
4310                         /* Save arguments to the stack */
4311                         for (i = 0; i < n; ++i) {
4312                                 ins = cfg->args [i];
4313
4314                                 if (ins->opcode == OP_REGVAR) {
4315                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4316                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4317                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4318                                 }
4319                                 else {
4320                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4321                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4322                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4323                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4324                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4325                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4326                                 }
4327                         }
4328                 }
4329                 else
4330                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4331         }
4332         else
4333                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4334
4335         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4336         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4337
4338         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4339
4340         if (enable_arguments && stack_area) {
4341                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4342
4343                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4344
4345                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4346         }
4347
4348         ia64_codegen_close (code);
4349
4350         return code.buf;
4351 }
4352
4353 void*
4354 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4355 {
4356         Ia64CodegenState code;
4357         CallInfo *cinfo = NULL;
4358         MonoMethod *method = cfg->method;
4359         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4360
4361         ia64_codegen_init (code, p);
4362
4363         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4364
4365         /* Save return value + pass it to func */
4366         switch (cinfo->ret.storage) {
4367         case ArgNone:
4368                 break;
4369         case ArgInIReg:
4370                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4371                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4372                 break;
4373         case ArgInFloatReg:
4374                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4375                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4376                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4377                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4378                 break;
4379         case ArgValuetypeAddrInIReg:
4380                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4381                 break;
4382         case ArgAggregate:
4383                 NOT_IMPLEMENTED;
4384                 break;
4385         default:
4386                 break;
4387         }
4388
4389         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4390         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4391         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4392
4393         /* Restore return value */
4394         switch (cinfo->ret.storage) {
4395         case ArgNone:
4396                 break;
4397         case ArgInIReg:
4398                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4399                 break;
4400         case ArgInFloatReg:
4401                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4402                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4403                 break;
4404         case ArgValuetypeAddrInIReg:
4405                 break;
4406         case ArgAggregate:
4407                 break;
4408         default:
4409                 break;
4410         }
4411
4412         ia64_codegen_close (code);
4413
4414         return code.buf;
4415 }
4416
4417 void
4418 mono_arch_save_unwind_info (MonoCompile *cfg)
4419 {
4420         unw_dyn_info_t *di;
4421
4422         /* FIXME: Unregister this for dynamic methods */
4423
4424         di = g_malloc0 (sizeof (unw_dyn_info_t));
4425         di->start_ip = (unw_word_t) cfg->native_code;
4426         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4427         di->gp = 0;
4428         di->format = UNW_INFO_FORMAT_DYNAMIC;
4429         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4430         di->u.pi.regions = cfg->arch.r_pro;
4431
4432         _U_dyn_register (di);
4433
4434         /*
4435         {
4436                 unw_dyn_region_info_t *region = di->u.pi.regions;
4437
4438                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4439                 while (region) {
4440                         printf ("    [Region: %d]\n", region->insn_count);
4441                         region = region->next;
4442                 }
4443         }
4444         */
4445 }
4446
4447 void
4448 mono_arch_flush_icache (guint8 *code, gint size)
4449 {
4450         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4451         guint8* end = (guint8*)((guint64)code + size);
4452
4453 #ifdef __INTEL_COMPILER
4454         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4455         while (p < end) {
4456                 __fc ((guint64)p);
4457                 p += 32;
4458         }
4459 #else
4460         while (p < end) {
4461                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4462                 /* FIXME: This could be increased to 128 on some cpus */
4463                 p += 32;
4464         }
4465 #endif
4466 }
4467
4468 void
4469 mono_arch_flush_register_windows (void)
4470 {
4471         /* Not needed because of libunwind */
4472 }
4473
4474 gboolean
4475 mono_arch_is_inst_imm (gint64 imm)
4476 {
4477         /* The lowering pass will take care of it */
4478
4479         return TRUE;
4480 }
4481
4482 /*
4483  * Determine whenever the trap whose info is in SIGINFO is caused by
4484  * integer overflow.
4485  */
4486 gboolean
4487 mono_arch_is_int_overflow (void *sigctx, void *info)
4488 {
4489         /* Division is emulated with explicit overflow checks */
4490         return FALSE;
4491 }
4492
4493 guint32
4494 mono_arch_get_patch_offset (guint8 *code)
4495 {
4496         NOT_IMPLEMENTED;
4497
4498         return 0;
4499 }
4500
4501 gpointer*
4502 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4503 {
4504         NOT_IMPLEMENTED;
4505
4506         return NULL;
4507 }
4508
4509 void
4510 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4511 {
4512 }
4513
4514 void
4515 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4516 {
4517 }
4518
4519 #ifdef MONO_ARCH_HAVE_IMT
4520
4521 /*
4522  * LOCKING: called with the domain lock held
4523  */
4524 gpointer
4525 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4526         gpointer fail_tramp)
4527 {
4528         int i;
4529         int size = 0;
4530         guint8 *start, *buf;
4531         Ia64CodegenState code;
4532
4533         size = count * 256;
4534         buf = g_malloc0 (size);
4535         ia64_codegen_init (code, buf);
4536
4537         /* IA64_R9 contains the IMT method */
4538
4539         for (i = 0; i < count; ++i) {
4540                 MonoIMTCheckItem *item = imt_entries [i];
4541                 ia64_begin_bundle (code);
4542                 item->code_target = (guint8*)code.buf + code.nins;
4543                 if (item->is_equals) {
4544                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4545
4546                         if (item->check_target_idx || fail_case) {
4547                                 if (!item->compare_done || fail_case) {
4548                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4549                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4550                                 }
4551                                 item->jmp_code = (guint8*)code.buf + code.nins;
4552                                 ia64_br_cond_pred (code, 7, 0);
4553
4554                                 if (item->has_target_code) {
4555                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4556                                 } else {
4557                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4558                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4559                                 }
4560                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4561                                 ia64_br_cond_reg (code, IA64_B6);
4562
4563                                 if (fail_case) {
4564                                         ia64_begin_bundle (code);
4565                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4566                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4567                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4568                                         ia64_br_cond_reg (code, IA64_B6);
4569                                         item->jmp_code = NULL;
4570                                 }
4571                         } else {
4572                                 /* enable the commented code to assert on wrong method */
4573 #if ENABLE_WRONG_METHOD_CHECK
4574                                 g_assert_not_reached ();
4575 #endif
4576                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4577                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4578                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4579                                 ia64_br_cond_reg (code, IA64_B6);
4580 #if ENABLE_WRONG_METHOD_CHECK
4581                                 g_assert_not_reached ();
4582 #endif
4583                         }
4584                 } else {
4585                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4586                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4587                         item->jmp_code = (guint8*)code.buf + code.nins;
4588                         ia64_br_cond_pred (code, 6, 0);
4589                 }
4590         }
4591         /* patch the branches to get to the target items */
4592         for (i = 0; i < count; ++i) {
4593                 MonoIMTCheckItem *item = imt_entries [i];
4594                 if (item->jmp_code) {
4595                         if (item->check_target_idx) {
4596                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4597                         }
4598                 }
4599         }
4600
4601         ia64_codegen_close (code);
4602         g_assert (code.buf - buf <= size);
4603
4604         size = code.buf - buf;
4605         if (fail_tramp) {
4606                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4607                 start = (gpointer)ALIGN_TO (start, 16);
4608         } else {
4609                 start = mono_domain_code_reserve (domain, size);
4610         }
4611         memcpy (start, buf, size);
4612
4613         mono_arch_flush_icache (start, size);
4614
4615         mono_stats.imt_thunks_size += size;
4616
4617         return start;
4618 }
4619
4620 MonoMethod*
4621 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4622 {
4623         return (MonoMethod*)regs [IA64_R9];
4624 }
4625
4626 void
4627 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4628 {
4629         /* Done by the implementation of the CALL_MEMBASE opcodes */
4630 }
4631 #endif
4632
4633 gpointer
4634 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4635 {
4636         return (gpointer)regs [IA64_R10];
4637 }
4638
4639 gpointer
4640 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4641 {
4642         return NULL;
4643 }
4644
4645 MonoInst*
4646 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4647 {
4648         MonoInst *ins = NULL;
4649
4650         if (cmethod->klass->image == mono_defaults.corlib &&
4651                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4652                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4653
4654                 /*
4655                  * We don't use the generic version in mini_emit_inst_for_method () since we
4656                  * ia64 has atomic_add_imm opcodes.
4657                  */
4658                 if (strcmp (cmethod->name, "Increment") == 0) {
4659                         guint32 opcode;
4660
4661                         if (fsig->params [0]->type == MONO_TYPE_I4)
4662                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4663                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4664                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4665                         else
4666                                 g_assert_not_reached ();
4667                         MONO_INST_NEW (cfg, ins, opcode);
4668                         ins->dreg = mono_alloc_preg (cfg);
4669                         ins->inst_imm = 1;
4670                         ins->inst_basereg = args [0]->dreg;
4671                         ins->inst_offset = 0;
4672                         MONO_ADD_INS (cfg->cbb, ins);
4673                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4674                         guint32 opcode;
4675
4676                         if (fsig->params [0]->type == MONO_TYPE_I4)
4677                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4678                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4679                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4680                         else
4681                                 g_assert_not_reached ();
4682                         MONO_INST_NEW (cfg, ins, opcode);
4683                         ins->dreg = mono_alloc_preg (cfg);
4684                         ins->inst_imm = -1;
4685                         ins->inst_basereg = args [0]->dreg;
4686                         ins->inst_offset = 0;
4687                         MONO_ADD_INS (cfg->cbb, ins);
4688                 } else if (strcmp (cmethod->name, "Add") == 0) {
4689                         guint32 opcode;
4690                         gboolean is_imm = FALSE;
4691                         gint64 imm = 0;
4692
4693                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4694                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4695
4696                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4697                         }
4698
4699                         if (is_imm) {
4700                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4701                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4702                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4703                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4704                                 else
4705                                         g_assert_not_reached ();
4706
4707                                 MONO_INST_NEW (cfg, ins, opcode);
4708                                 ins->dreg = mono_alloc_ireg (cfg);
4709                                 ins->inst_basereg = args [0]->dreg;
4710                                 ins->inst_offset = 0;
4711                                 ins->inst_imm = imm;
4712                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4713                         } else {
4714                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4715                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4716                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4717                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4718                                 else
4719                                         g_assert_not_reached ();
4720
4721                                 MONO_INST_NEW (cfg, ins, opcode);
4722                                 ins->dreg = mono_alloc_ireg (cfg);
4723                                 ins->inst_basereg = args [0]->dreg;
4724                                 ins->inst_offset = 0;
4725                                 ins->sreg2 = args [1]->dreg;
4726                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4727                         }
4728                         MONO_ADD_INS (cfg->cbb, ins);
4729                 }
4730         }
4731
4732         return ins;
4733 }
4734
4735 gboolean
4736 mono_arch_print_tree (MonoInst *tree, int arity)
4737 {
4738         return 0;
4739 }
4740
4741 MonoInst*
4742 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4743 {
4744         return mono_get_domain_intrinsic (cfg);
4745 }
4746
4747 gpointer
4748 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4749 {
4750         /* FIXME: implement */
4751         g_assert_not_reached ();
4752 }