mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 G_GNUC_UNUSED static void
 113 break_count (void)
 114 {
 115 }
 116
 117 G_GNUC_UNUSED static gboolean
 118 debug_count (void)
 119 {
 120         static int count = 0;
 121         count ++;
 122
 123         if (count == atoi (getenv ("COUNT"))) {
 124                 break_count ();
 125         }
 126
 127         if (count > atoi (getenv ("COUNT"))) {
 128                 return FALSE;
 129         }
 130
 131         return TRUE;
 132 }
 133
 134 static gboolean
 135 debug_ins_sched (void)
 136 {
 137 #if 0
 138         return debug_count ();
 139 #else
 140         return TRUE;
 141 #endif
 142 }
 143
 144 static gboolean
 145 debug_omit_fp (void)
 146 {
 147 #if 0
 148         return debug_count ();
 149 #else
 150         return TRUE;
 151 #endif
 152 }
 153
 154 static void
 155 ia64_patch (unsigned char* code, gpointer target);
 156
 157 typedef enum {
 158         ArgInIReg,
 159         ArgInFloatReg,
 160         ArgInFloatRegR4,
 161         ArgOnStack,
 162         ArgValuetypeAddrInIReg,
 163         ArgAggregate,
 164         ArgSingleHFA,
 165         ArgDoubleHFA,
 166         ArgNone
 167 } ArgStorage;
 168
 169 typedef enum {
 170         AggregateNormal,
 171         AggregateSingleHFA,
 172         AggregateDoubleHFA
 173 } AggregateType;
 174
 175 typedef struct {
 176         gint16 offset;
 177         gint8  reg;
 178         ArgStorage storage;
 179
 180         /* Only if storage == ArgAggregate */
 181         int nregs, nslots;
 182         AggregateType atype;
 183 } ArgInfo;
 184
 185 typedef struct {
 186         int nargs;
 187         guint32 stack_usage;
 188         guint32 reg_usage;
 189         guint32 freg_usage;
 190         gboolean need_stack_align;
 191         ArgInfo ret;
 192         ArgInfo sig_cookie;
 193         ArgInfo args [1];
 194 } CallInfo;
 195
 196 #define DEBUG(a) if (cfg->verbose_level > 1) a
 197
 198 #define PARAM_REGS 8
 199
 200 static void inline
 201 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = ArgInIReg;
 211                 ainfo->reg = *gr;
 212                 *(gr) += 1;
 213     }
 214 }
 215
 216 #define FLOAT_PARAM_REGS 8
 217
 218 static void inline
 219 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 (*stack_size) += sizeof (gpointer);
 226     }
 227     else {
 228                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 229                 ainfo->reg = 8 + *fr;
 230                 (*fr) += 1;
 231                 (*gr) += 1;
 232     }
 233 }
 234
 235 static void
 236 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 237                gboolean is_return,
 238                guint32 *gr, guint32 *fr, guint32 *stack_size)
 239 {
 240         guint32 size, i;
 241         MonoClass *klass;
 242         MonoMarshalType *info;
 243         gboolean is_hfa = TRUE;
 244         guint32 hfa_type = 0;
 245
 246         klass = mono_class_from_mono_type (type);
 247         if (type->type == MONO_TYPE_TYPEDBYREF)
 248                 size = 3 * sizeof (gpointer);
 249         else if (sig->pinvoke)
 250                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 251         else
 252                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 253
 254         if (!sig->pinvoke || (size == 0)) {
 255                 /* Allways pass in memory */
 256                 ainfo->offset = *stack_size;
 257                 *stack_size += ALIGN_TO (size, 8);
 258                 ainfo->storage = ArgOnStack;
 259
 260                 return;
 261         }
 262
 263         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 264         info = mono_marshal_load_type_info (klass);
 265         g_assert (info);
 266         for (i = 0; i < info->num_fields; ++i) {
 267                 guint32 ftype = info->fields [i].field->type->type;
 268                 if (!(info->fields [i].field->type->byref) &&
 269                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 270                         if (hfa_type == 0)
 271                                 hfa_type = ftype;
 272                         else if (hfa_type != ftype)
 273                                 is_hfa = FALSE;
 274                 }
 275                 else
 276                         is_hfa = FALSE;
 277         }
 278         if (hfa_type == 0)
 279                 is_hfa = FALSE;
 280
 281         ainfo->storage = ArgAggregate;
 282         ainfo->atype = AggregateNormal;
 283
 284         if (is_hfa) {
 285                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 286                 if (is_return) {
 287                         if (info->num_fields <= 8) {
 288                                 ainfo->reg = 8;
 289                                 ainfo->nregs = info->num_fields;
 290                                 ainfo->nslots = ainfo->nregs;
 291                                 return;
 292                         }
 293                         /* Fall through */
 294                 }
 295                 else {
 296                         if ((*fr) + info->num_fields > 8)
 297                                 NOT_IMPLEMENTED;
 298
 299                         ainfo->reg = 8 + (*fr);
 300                         ainfo->nregs = info->num_fields;
 301                         ainfo->nslots = ainfo->nregs;
 302                         (*fr) += info->num_fields;
 303                         if (ainfo->atype == AggregateSingleHFA) {
 304                                 /*
 305                                  * FIXME: Have to keep track of the parameter slot number, which is
 306                                  * not the same as *gr.
 307                                  */
 308                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 309                         } else {
 310                                 (*gr) += info->num_fields;
 311                         }
 312                         return;
 313                 }
 314         }
 315
 316         /* This also handles returning of TypedByRef used by some icalls */
 317         if (is_return) {
 318                 if (size <= 32) {
 319                         ainfo->reg = IA64_R8;
 320                         ainfo->nregs = (size + 7) / 8;
 321                         ainfo->nslots = ainfo->nregs;
 322                         return;
 323                 }
 324                 NOT_IMPLEMENTED;
 325         }
 326
 327         ainfo->reg = (*gr);
 328         ainfo->offset = *stack_size;
 329         ainfo->nslots = (size + 7) / 8;
 330
 331         if (((*gr) + ainfo->nslots) <= 8) {
 332                 /* Fits entirely in registers */
 333                 ainfo->nregs = ainfo->nslots;
 334                 (*gr) += ainfo->nregs;
 335                 return;
 336         }
 337
 338         ainfo->nregs = 8 - (*gr);
 339         (*gr) = 8;
 340         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 341 }
 342
 343 /*
 344  * get_call_info:
 345  *
 346  *  Obtain information about a call according to the calling convention.
 347  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 348  * Gude" document for more information.
 349  */
 350 static CallInfo*
 351 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 352 {
 353         guint32 i, gr, fr;
 354         MonoType *ret_type;
 355         int n = sig->hasthis + sig->param_count;
 356         guint32 stack_size = 0;
 357         CallInfo *cinfo;
 358         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 359
 360         if (mp)
 361                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 362         else
 363                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 364
 365         gr = 0;
 366         fr = 0;
 367
 368         /* return value */
 369         {
 370                 ret_type = mono_type_get_underlying_type (sig->ret);
 371                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 372                 switch (ret_type->type) {
 373                 case MONO_TYPE_BOOLEAN:
 374                 case MONO_TYPE_I1:
 375                 case MONO_TYPE_U1:
 376                 case MONO_TYPE_I2:
 377                 case MONO_TYPE_U2:
 378                 case MONO_TYPE_CHAR:
 379                 case MONO_TYPE_I4:
 380                 case MONO_TYPE_U4:
 381                 case MONO_TYPE_I:
 382                 case MONO_TYPE_U:
 383                 case MONO_TYPE_PTR:
 384                 case MONO_TYPE_FNPTR:
 385                 case MONO_TYPE_CLASS:
 386                 case MONO_TYPE_OBJECT:
 387                 case MONO_TYPE_SZARRAY:
 388                 case MONO_TYPE_ARRAY:
 389                 case MONO_TYPE_STRING:
 390                         cinfo->ret.storage = ArgInIReg;
 391                         cinfo->ret.reg = IA64_R8;
 392                         break;
 393                 case MONO_TYPE_U8:
 394                 case MONO_TYPE_I8:
 395                         cinfo->ret.storage = ArgInIReg;
 396                         cinfo->ret.reg = IA64_R8;
 397                         break;
 398                 case MONO_TYPE_R4:
 399                 case MONO_TYPE_R8:
 400                         cinfo->ret.storage = ArgInFloatReg;
 401                         cinfo->ret.reg = 8;
 402                         break;
 403                 case MONO_TYPE_GENERICINST:
 404                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 405                                 cinfo->ret.storage = ArgInIReg;
 406                                 cinfo->ret.reg = IA64_R8;
 407                                 break;
 408                         }
 409                         /* Fall through */
 410                 case MONO_TYPE_VALUETYPE:
 411                 case MONO_TYPE_TYPEDBYREF: {
 412                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 413
 414                         if (sig->ret->byref) {
 415                                 /* This seems to happen with ldfld wrappers */
 416                                 cinfo->ret.storage = ArgInIReg;
 417                         } else {
 418                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 419                                 if (cinfo->ret.storage == ArgOnStack)
 420                                         /* The caller passes the address where the value is stored */
 421                                         add_general (&gr, &stack_size, &cinfo->ret);
 422                                 if (cinfo->ret.storage == ArgInIReg)
 423                                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 424                         }
 425                         break;
 426                 }
 427                 case MONO_TYPE_VOID:
 428                         cinfo->ret.storage = ArgNone;
 429                         break;
 430                 default:
 431                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 432                 }
 433         }
 434
 435         /*
 436          * IA64 has MONO_ARCH_THIS_AS_FIRST_ARG defined, but we don't need to really pass
 437          * this as first, because this is stored in a non-stacked register by the calling
 438          * sequence.
 439          */
 440
 441         /* this */
 442         if (sig->hasthis)
 443                 add_general (&gr, &stack_size, cinfo->args + 0);
 444
 445         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 446                 gr = PARAM_REGS;
 447                 fr = FLOAT_PARAM_REGS;
 448
 449                 /* Emit the signature cookie just before the implicit arguments */
 450                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 451         }
 452
 453         for (i = 0; i < sig->param_count; ++i) {
 454                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 455                 MonoType *ptype;
 456
 457                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 458                         /* We allways pass the sig cookie on the stack for simplicity */
 459                         /*
 460                          * Prevent implicit arguments + the sig cookie from being passed
 461                          * in registers.
 462                          */
 463                         gr = PARAM_REGS;
 464                         fr = FLOAT_PARAM_REGS;
 465
 466                         /* Emit the signature cookie just before the implicit arguments */
 467                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 468                 }
 469
 470                 if (sig->params [i]->byref) {
 471                         add_general (&gr, &stack_size, ainfo);
 472                         continue;
 473                 }
 474                 ptype = mono_type_get_underlying_type (sig->params [i]);
 475                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 476                 switch (ptype->type) {
 477                 case MONO_TYPE_BOOLEAN:
 478                 case MONO_TYPE_I1:
 479                 case MONO_TYPE_U1:
 480                         add_general (&gr, &stack_size, ainfo);
 481                         break;
 482                 case MONO_TYPE_I2:
 483                 case MONO_TYPE_U2:
 484                 case MONO_TYPE_CHAR:
 485                         add_general (&gr, &stack_size, ainfo);
 486                         break;
 487                 case MONO_TYPE_I4:
 488                 case MONO_TYPE_U4:
 489                         add_general (&gr, &stack_size, ainfo);
 490                         break;
 491                 case MONO_TYPE_I:
 492                 case MONO_TYPE_U:
 493                 case MONO_TYPE_PTR:
 494                 case MONO_TYPE_FNPTR:
 495                 case MONO_TYPE_CLASS:
 496                 case MONO_TYPE_OBJECT:
 497                 case MONO_TYPE_STRING:
 498                 case MONO_TYPE_SZARRAY:
 499                 case MONO_TYPE_ARRAY:
 500                         add_general (&gr, &stack_size, ainfo);
 501                         break;
 502                 case MONO_TYPE_GENERICINST:
 503                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 504                                 add_general (&gr, &stack_size, ainfo);
 505                                 break;
 506                         }
 507                         /* Fall through */
 508                 case MONO_TYPE_VALUETYPE:
 509                 case MONO_TYPE_TYPEDBYREF:
 510                         /* FIXME: */
 511                         /* We allways pass valuetypes on the stack */
 512                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 513                         break;
 514                 case MONO_TYPE_U8:
 515                 case MONO_TYPE_I8:
 516                         add_general (&gr, &stack_size, ainfo);
 517                         break;
 518                 case MONO_TYPE_R4:
 519                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 520                         break;
 521                 case MONO_TYPE_R8:
 522                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 523                         break;
 524                 default:
 525                         g_assert_not_reached ();
 526                 }
 527         }
 528
 529         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 530                 gr = PARAM_REGS;
 531                 fr = FLOAT_PARAM_REGS;
 532
 533                 /* Emit the signature cookie just before the implicit arguments */
 534                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 535         }
 536
 537         cinfo->stack_usage = stack_size;
 538         cinfo->reg_usage = gr;
 539         cinfo->freg_usage = fr;
 540         return cinfo;
 541 }
 542
 543 /*
 544  * mono_arch_get_argument_info:
 545  * @csig:  a method signature
 546  * @param_count: the number of parameters to consider
 547  * @arg_info: an array to store the result infos
 548  *
 549  * Gathers information on parameters such as size, alignment and
 550  * padding. arg_info should be large enought to hold param_count + 1 entries.
 551  *
 552  * Returns the size of the argument area on the stack.
 553  */
 554 int
 555 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 556 {
 557         int k;
 558         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 559         guint32 args_size = cinfo->stack_usage;
 560
 561         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 562         if (csig->hasthis) {
 563                 arg_info [0].offset = 0;
 564         }
 565
 566         for (k = 0; k < param_count; k++) {
 567                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 568                 /* FIXME: */
 569                 arg_info [k + 1].size = 0;
 570         }
 571
 572         g_free (cinfo);
 573
 574         return args_size;
 575 }
 576
 577 /*
 578  * Initialize the cpu to execute managed code.
 579  */
 580 void
 581 mono_arch_cpu_init (void)
 582 {
 583 }
 584
 585 /*
 586  * Initialize architecture specific code.
 587  */
 588 void
 589 mono_arch_init (void)
 590 {
 591 }
 592
 593 /*
 594  * Cleanup architecture specific code.
 595  */
 596 void
 597 mono_arch_cleanup (void)
 598 {
 599 }
 600
 601 /*
 602  * This function returns the optimizations supported on this cpu.
 603  */
 604 guint32
 605 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 606 {
 607         *exclude_mask = 0;
 608
 609         return 0;
 610 }
 611
 612 GList *
 613 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 614 {
 615         GList *vars = NULL;
 616         int i;
 617         MonoMethodSignature *sig;
 618         MonoMethodHeader *header;
 619         CallInfo *cinfo;
 620
 621         header = cfg->header;
 622
 623         sig = mono_method_signature (cfg->method);
 624
 625         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 626
 627         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 628                 MonoInst *ins = cfg->args [i];
 629
 630                 ArgInfo *ainfo = &cinfo->args [i];
 631
 632                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 633                         continue;
 634
 635                 if (ainfo->storage == ArgInIReg) {
 636                         /* The input registers are non-volatile */
 637                         ins->opcode = OP_REGVAR;
 638                         ins->dreg = 32 + ainfo->reg;
 639                 }
 640         }
 641
 642         for (i = 0; i < cfg->num_varinfo; i++) {
 643                 MonoInst *ins = cfg->varinfo [i];
 644                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 645
 646                 /* unused vars */
 647                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 648                         continue;
 649
 650                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 651                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 652                         continue;
 653
 654                 if (mono_is_regsize_var (ins->inst_vtype)) {
 655                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 656                         g_assert (i == vmv->idx);
 657                         vars = g_list_prepend (vars, vmv);
 658                 }
 659         }
 660
 661         vars = mono_varlist_sort (cfg, vars, 0);
 662
 663         return vars;
 664 }
 665
 666 static void
 667 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 668 {
 669         CallInfo *cinfo;
 670         guint32 reserved_regs;
 671         MonoMethodHeader *header;
 672
 673         if (cfg->arch.reg_local0 > 0)
 674                 /* Already done */
 675                 return;
 676
 677         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 678
 679         header = cfg->header;
 680
 681         /* Some registers are reserved for use by the prolog/epilog */
 682         reserved_regs = header->num_clauses ? 4 : 3;
 683
 684         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 685                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 686                 /* One registers is needed by instrument_epilog to save the return value */
 687                 reserved_regs ++;
 688                 if (cinfo->reg_usage < 2)
 689                         /* Number of arguments passed to function call in instrument_prolog */
 690                         cinfo->reg_usage = 2;
 691         }
 692
 693         cfg->arch.reg_in0 = 32;
 694         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 695         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 696
 697         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 698         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 699         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 700
 701         /*
 702          * Frames without handlers save sp to fp, frames with handlers save it into
 703          * a dedicated register.
 704          */
 705         if (header->num_clauses)
 706                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 707         else
 708                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 709
 710         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 711                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 712                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 713         }
 714
 715         /*
 716          * Need to allocate at least 2 out register for use by OP_THROW / the system
 717          * exception throwing code.
 718          */
 719         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 720 }
 721
 722 GList *
 723 mono_arch_get_global_int_regs (MonoCompile *cfg)
 724 {
 725         GList *regs = NULL;
 726         int i;
 727
 728         mono_ia64_alloc_stacked_registers (cfg);
 729
 730         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 731                 /* FIXME: regmask */
 732                 g_assert (i < 64);
 733                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 734         }
 735
 736         return regs;
 737 }
 738
 739 /*
 740  * mono_arch_regalloc_cost:
 741  *
 742  *  Return the cost, in number of memory references, of the action of
 743  * allocating the variable VMV into a register during global register
 744  * allocation.
 745  */
 746 guint32
 747 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 748 {
 749         /* FIXME: Increase costs linearly to avoid using all local registers */
 750
 751         return 0;
 752 }
 753
 754 void
 755 mono_arch_allocate_vars (MonoCompile *cfg)
 756 {
 757         MonoMethodSignature *sig;
 758         MonoMethodHeader *header;
 759         MonoInst *inst;
 760         int i, offset;
 761         guint32 locals_stack_size, locals_stack_align;
 762         gint32 *offsets;
 763         CallInfo *cinfo;
 764
 765         header = cfg->header;
 766
 767         sig = mono_method_signature (cfg->method);
 768
 769         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 770
 771         /*
 772          * Determine whenever the frame pointer can be eliminated.
 773          * FIXME: Remove some of the restrictions.
 774          */
 775         cfg->arch.omit_fp = TRUE;
 776
 777         if (!debug_omit_fp ())
 778                 cfg->arch.omit_fp = FALSE;
 779
 780         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 781                 cfg->arch.omit_fp = FALSE;
 782         if (header->num_clauses)
 783                 cfg->arch.omit_fp = FALSE;
 784         if (cfg->param_area)
 785                 cfg->arch.omit_fp = FALSE;
 786         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 787                 cfg->arch.omit_fp = FALSE;
 788         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 789                 cfg->arch.omit_fp = FALSE;
 790         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 791                 ArgInfo *ainfo = &cinfo->args [i];
 792
 793                 if (ainfo->storage == ArgOnStack) {
 794                         /*
 795                          * The stack offset can only be determined when the frame
 796                          * size is known.
 797                          */
 798                         cfg->arch.omit_fp = FALSE;
 799                 }
 800         }
 801
 802         mono_ia64_alloc_stacked_registers (cfg);
 803
 804         /*
 805          * We use the ABI calling conventions for managed code as well.
 806          * Exception: valuetypes are never passed or returned in registers.
 807          */
 808
 809         if (cfg->arch.omit_fp) {
 810                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 811                 cfg->frame_reg = IA64_SP;
 812                 offset = ARGS_OFFSET;
 813         }
 814         else {
 815                 /* Locals are allocated backwards from %fp */
 816                 cfg->frame_reg = cfg->arch.reg_fp;
 817                 offset = 0;
 818         }
 819
 820         if (cfg->method->save_lmf) {
 821                 /* No LMF on IA64 */
 822         }
 823
 824         if (sig->ret->type != MONO_TYPE_VOID) {
 825                 switch (cinfo->ret.storage) {
 826                 case ArgInIReg:
 827                         cfg->ret->opcode = OP_REGVAR;
 828                         cfg->ret->inst_c0 = cinfo->ret.reg;
 829                         break;
 830                 case ArgInFloatReg:
 831                         cfg->ret->opcode = OP_REGVAR;
 832                         cfg->ret->inst_c0 = cinfo->ret.reg;
 833                         break;
 834                 case ArgValuetypeAddrInIReg:
 835                         cfg->vret_addr->opcode = OP_REGVAR;
 836                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 837                         break;
 838                 case ArgAggregate:
 839                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 840                         if (cfg->arch.omit_fp)
 841                                 g_assert_not_reached ();
 842                         offset = ALIGN_TO (offset, 8);
 843                         offset += cinfo->ret.nslots * 8;
 844                         cfg->ret->opcode = OP_REGOFFSET;
 845                         cfg->ret->inst_basereg = cfg->frame_reg;
 846                         cfg->ret->inst_offset = - offset;
 847                         break;
 848                 default:
 849                         g_assert_not_reached ();
 850                 }
 851                 cfg->ret->dreg = cfg->ret->inst_c0;
 852         }
 853
 854         /* Allocate locals */
 855         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 856         if (locals_stack_align) {
 857                 offset = ALIGN_TO (offset, locals_stack_align);
 858         }
 859         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 860                 if (offsets [i] != -1) {
 861                         MonoInst *inst = cfg->varinfo [i];
 862                         inst->opcode = OP_REGOFFSET;
 863                         inst->inst_basereg = cfg->frame_reg;
 864                         if (cfg->arch.omit_fp)
 865                                 inst->inst_offset = (offset + offsets [i]);
 866                         else
 867                                 inst->inst_offset = - (offset + offsets [i]);
 868                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 869                 }
 870         }
 871         offset += locals_stack_size;
 872
 873         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 874                 if (cfg->arch.omit_fp)
 875                         g_assert_not_reached ();
 876                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 877                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 878         }
 879
 880         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 881                 inst = cfg->args [i];
 882                 if (inst->opcode != OP_REGVAR) {
 883                         ArgInfo *ainfo = &cinfo->args [i];
 884                         gboolean inreg = TRUE;
 885                         MonoType *arg_type;
 886
 887                         if (sig->hasthis && (i == 0))
 888                                 arg_type = &mono_defaults.object_class->byval_arg;
 889                         else
 890                                 arg_type = sig->params [i - sig->hasthis];
 891
 892                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 893                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 894                                 inreg = FALSE;
 895
 896                         inst->opcode = OP_REGOFFSET;
 897
 898                         switch (ainfo->storage) {
 899                         case ArgInIReg:
 900                                 inst->opcode = OP_REGVAR;
 901                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 902                                 break;
 903                         case ArgInFloatReg:
 904                         case ArgInFloatRegR4:
 905                                 /*
 906                                  * Since float regs are volatile, we save the arguments to
 907                                  * the stack in the prolog.
 908                                  */
 909                                 inreg = FALSE;
 910                                 break;
 911                         case ArgOnStack:
 912                                 if (cfg->arch.omit_fp)
 913                                         g_assert_not_reached ();
 914                                 inst->opcode = OP_REGOFFSET;
 915                                 inst->inst_basereg = cfg->frame_reg;
 916                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 917                                 break;
 918                         case ArgAggregate:
 919                                 inreg = FALSE;
 920                                 break;
 921                         default:
 922                                 NOT_IMPLEMENTED;
 923                         }
 924
 925                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 926                                 guint32 size = 0;
 927
 928                                 inst->opcode = OP_REGOFFSET;
 929                                 inst->inst_basereg = cfg->frame_reg;
 930                                 /* These arguments are saved to the stack in the prolog */
 931                                 switch (ainfo->storage) {
 932                                 case ArgAggregate:
 933                                         if (ainfo->atype == AggregateSingleHFA)
 934                                                 size = ainfo->nslots * 4;
 935                                         else
 936                                                 size = ainfo->nslots * 8;
 937                                         break;
 938                                 default:
 939                                         size = sizeof (gpointer);
 940                                         break;
 941                                 }
 942
 943                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 944
 945                                 if (cfg->arch.omit_fp) {
 946                                         inst->inst_offset = offset;
 947                                         offset += size;
 948                                 } else {
 949                                         offset += size;
 950                                         inst->inst_offset = - offset;
 951                                 }
 952                         }
 953                 }
 954         }
 955
 956         /*
 957          * FIXME: This doesn't work because some variables are allocated during local
 958          * regalloc.
 959          */
 960         /*
 961         if (cfg->arch.omit_fp && offset == 16)
 962                 offset = 0;
 963         */
 964
 965         cfg->stack_offset = offset;
 966 }
 967
 968 void
 969 mono_arch_create_vars (MonoCompile *cfg)
 970 {
 971         MonoMethodSignature *sig;
 972         CallInfo *cinfo;
 973
 974         sig = mono_method_signature (cfg->method);
 975
 976         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 977
 978         if (cinfo->ret.storage == ArgAggregate)
 979                 cfg->ret_var_is_local = TRUE;
 980         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 981                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 982                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 983                         printf ("vret_addr = ");
 984                         mono_print_ins (cfg->vret_addr);
 985                 }
 986         }
 987 }
 988
 989 static void
 990 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
 991 {
 992         MonoInst *arg;
 993
 994         MONO_INST_NEW (cfg, arg, OP_NOP);
 995         arg->sreg1 = tree->dreg;
 996
 997         switch (storage) {
 998         case ArgInIReg:
 999                 arg->opcode = OP_MOVE;
1000                 arg->dreg = mono_alloc_ireg (cfg);
1001
1002                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1003                 break;
1004         case ArgInFloatReg:
1005                 arg->opcode = OP_FMOVE;
1006                 arg->dreg = mono_alloc_freg (cfg);
1007
1008                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1009                 break;
1010         case ArgInFloatRegR4:
1011                 arg->opcode = OP_FCONV_TO_R4;
1012                 arg->dreg = mono_alloc_freg (cfg);
1013
1014                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1015                 break;
1016         default:
1017                 g_assert_not_reached ();
1018         }
1019
1020         MONO_ADD_INS (cfg->cbb, arg);
1021 }
1022
1023 static void
1024 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1025 {
1026         MonoMethodSignature *tmp_sig;
1027
1028         /* Emit the signature cookie just before the implicit arguments */
1029         MonoInst *sig_arg;
1030         /* FIXME: Add support for signature tokens to AOT */
1031         cfg->disable_aot = TRUE;
1032
1033         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1034
1035         /*
1036          * mono_ArgIterator_Setup assumes the signature cookie is
1037          * passed first and all the arguments which were before it are
1038          * passed on the stack after the signature. So compensate by
1039          * passing a different signature.
1040          */
1041         tmp_sig = mono_metadata_signature_dup (call->signature);
1042         tmp_sig->param_count -= call->signature->sentinelpos;
1043         tmp_sig->sentinelpos = 0;
1044         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1045
1046         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1047         sig_arg->dreg = mono_alloc_ireg (cfg);
1048         sig_arg->inst_p0 = tmp_sig;
1049         MONO_ADD_INS (cfg->cbb, sig_arg);
1050
1051         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1052 }
1053
1054 void
1055 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1056 {
1057         MonoInst *in;
1058         MonoMethodSignature *sig;
1059         int i, n, stack_size;
1060         CallInfo *cinfo;
1061         ArgInfo *ainfo;
1062
1063         stack_size = 0;
1064
1065         mono_ia64_alloc_stacked_registers (cfg);
1066
1067         sig = call->signature;
1068         n = sig->param_count + sig->hasthis;
1069
1070         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1071
1072         if (cinfo->ret.storage == ArgAggregate) {
1073                 MonoInst *vtarg;
1074                 MonoInst *local;
1075
1076                 /*
1077                  * The valuetype is in registers after the call, need to be copied
1078                  * to the stack. Save the address to a local here, so the call
1079                  * instruction can access it.
1080                  */
1081                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1082                 local->flags |= MONO_INST_VOLATILE;
1083                 cfg->arch.ret_var_addr_local = local;
1084
1085                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1086                 vtarg->sreg1 = call->vret_var->dreg;
1087                 vtarg->dreg = local->dreg;
1088                 MONO_ADD_INS (cfg->cbb, vtarg);
1089         }
1090
1091         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1092                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1093         }
1094
1095         for (i = 0; i < n; ++i) {
1096                 MonoType *arg_type;
1097
1098                 ainfo = cinfo->args + i;
1099
1100                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1101                         /* Emit the signature cookie just before the implicit arguments */
1102                         emit_sig_cookie (cfg, call, cinfo);
1103                 }
1104
1105                 in = call->args [i];
1106
1107                 if (sig->hasthis && (i == 0))
1108                         arg_type = &mono_defaults.object_class->byval_arg;
1109                 else
1110                         arg_type = sig->params [i - sig->hasthis];
1111
1112                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1113                         guint32 align;
1114                         guint32 size;
1115
1116                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1117                                 size = sizeof (MonoTypedRef);
1118                                 align = sizeof (gpointer);
1119                         }
1120                         else if (sig->pinvoke)
1121                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1122                         else {
1123                                 /*
1124                                  * Other backends use mono_type_stack_size (), but that
1125                                  * aligns the size to 8, which is larger than the size of
1126                                  * the source, leading to reads of invalid memory if the
1127                                  * source is at the end of address space.
1128                                  */
1129                                 size = mono_class_value_size (in->klass, &align);
1130                         }
1131
1132                         if (size > 0) {
1133                                 MonoInst *arg;
1134
1135                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1136                                 arg->sreg1 = in->dreg;
1137                                 arg->klass = in->klass;
1138                                 arg->backend.size = size;
1139                                 arg->inst_p0 = call;
1140                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1141                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1142
1143                                 MONO_ADD_INS (cfg->cbb, arg);
1144                         }
1145                 }
1146                 else {
1147                         switch (ainfo->storage) {
1148                         case ArgInIReg:
1149                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1150                                 break;
1151                         case ArgInFloatReg:
1152                         case ArgInFloatRegR4:
1153                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1154                                 break;
1155                         case ArgOnStack:
1156                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1157                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1158                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1159                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1160                                 else
1161                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1162                                 break;
1163                         default:
1164                                 g_assert_not_reached ();
1165                         }
1166                 }
1167         }
1168
1169         /* Handle the case where there are no implicit arguments */
1170         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1171                 emit_sig_cookie (cfg, call, cinfo);
1172         }
1173
1174         call->stack_usage = cinfo->stack_usage;
1175         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1176 }
1177
1178 void
1179 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1180 {
1181         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1182         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1183         int size = ins->backend.size;
1184
1185         if (ainfo->storage == ArgAggregate) {
1186                 MonoInst *load, *store;
1187                 int i, slot;
1188
1189                 /*
1190                  * Part of the structure is passed in registers.
1191                  */
1192                 for (i = 0; i < ainfo->nregs; ++i) {
1193                         slot = ainfo->reg + i;
1194
1195                         if (ainfo->atype == AggregateSingleHFA) {
1196                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1197                                 load->inst_basereg = src->dreg;
1198                                 load->inst_offset = i * 4;
1199                                 load->dreg = mono_alloc_freg (cfg);
1200
1201                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1202                         } else if (ainfo->atype == AggregateDoubleHFA) {
1203                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1204                                 load->inst_basereg = src->dreg;
1205                                 load->inst_offset = i * 8;
1206                                 load->dreg = mono_alloc_freg (cfg);
1207
1208                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1209                         } else {
1210                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1211                                 load->inst_basereg = src->dreg;
1212                                 load->inst_offset = i * 8;
1213                                 load->dreg = mono_alloc_ireg (cfg);
1214
1215                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1216                         }
1217                         MONO_ADD_INS (cfg->cbb, load);
1218                 }
1219
1220                 /*
1221                  * Part of the structure is passed on the stack.
1222                  */
1223                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1224                         slot = ainfo->reg + i;
1225
1226                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1227                         load->inst_basereg = src->dreg;
1228                         load->inst_offset = i * sizeof (gpointer);
1229                         load->dreg = mono_alloc_preg (cfg);
1230                         MONO_ADD_INS (cfg->cbb, load);
1231
1232                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1233                         store->sreg1 = load->dreg;
1234                         store->inst_destbasereg = IA64_SP;
1235                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1236                         MONO_ADD_INS (cfg->cbb, store);
1237                 }
1238         } else {
1239                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1240         }
1241 }
1242
1243 void
1244 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1245 {
1246         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1247
1248         switch (cinfo->ret.storage) {
1249         case ArgInIReg:
1250                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1251                 break;
1252         case ArgInFloatReg:
1253                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1254                 break;
1255         default:
1256                 g_assert_not_reached ();
1257         }
1258 }
1259
1260 void
1261 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1262 {
1263 }
1264
1265 void
1266 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1267 {
1268         MonoInst *ins, *n, *last_ins = NULL;
1269         ins = bb->code;
1270
1271         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1272                 switch (ins->opcode) {
1273                 case OP_MOVE:
1274                 case OP_FMOVE:
1275                         /*
1276                          * Removes:
1277                          *
1278                          * OP_MOVE reg, reg
1279                          */
1280                         if (ins->dreg == ins->sreg1) {
1281                                 MONO_DELETE_INS (bb, ins);
1282                                 continue;
1283                         }
1284                         /*
1285                          * Removes:
1286                          *
1287                          * OP_MOVE sreg, dreg
1288                          * OP_MOVE dreg, sreg
1289                          */
1290                         if (last_ins && last_ins->opcode == OP_MOVE &&
1291                             ins->sreg1 == last_ins->dreg &&
1292                             ins->dreg == last_ins->sreg1) {
1293                                 MONO_DELETE_INS (bb, ins);
1294                                 continue;
1295                         }
1296                         break;
1297                 case OP_MUL_IMM:
1298                 case OP_IMUL_IMM:
1299                         /* remove unnecessary multiplication with 1 */
1300                         if (ins->inst_imm == 1) {
1301                                 if (ins->dreg != ins->sreg1) {
1302                                         ins->opcode = OP_MOVE;
1303                                 } else {
1304                                         MONO_DELETE_INS (bb, ins);
1305                                         continue;
1306                                 }
1307                         }
1308                         break;
1309                 }
1310
1311                 last_ins = ins;
1312                 ins = ins->next;
1313         }
1314         bb->last_ins = last_ins;
1315 }
1316
1317 int cond_to_ia64_cmp [][3] = {
1318         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1319         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1320         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1321         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1322         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1323         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1324         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1325         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1326         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1327         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1328 };
1329
1330 static int
1331 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1332 {
1333         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1334 }
1335
1336 int cond_to_ia64_cmp_imm [][3] = {
1337         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1338         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1339         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1340         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1341         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1342         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1343         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1344         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1345         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1346         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1347 };
1348
1349 static int
1350 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1351 {
1352         /* The condition needs to be reversed */
1353         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1354 }
1355
1356 #define NEW_INS(cfg,dest,op) do {       \
1357                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1358                 (dest)->opcode = (op);  \
1359         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1360         last_ins = (dest); \
1361         } while (0)
1362
1363 /*
1364  * mono_arch_lowering_pass:
1365  *
1366  *  Converts complex opcodes into simpler ones so that each IR instruction
1367  * corresponds to one machine instruction.
1368  */
1369 void
1370 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1371 {
1372         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1373         ins = bb->code;
1374
1375         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1376                 switch (ins->opcode) {
1377                 case OP_STOREI1_MEMBASE_IMM:
1378                 case OP_STOREI2_MEMBASE_IMM:
1379                 case OP_STOREI4_MEMBASE_IMM:
1380                 case OP_STOREI8_MEMBASE_IMM:
1381                 case OP_STORE_MEMBASE_IMM:
1382                         /* There are no store_membase instructions on ia64 */
1383                         if (ins->inst_offset == 0) {
1384                                 temp2 = NULL;
1385                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1386                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1387                                 temp2->sreg1 = ins->inst_destbasereg;
1388                                 temp2->inst_imm = ins->inst_offset;
1389                                 temp2->dreg = mono_alloc_ireg (cfg);
1390                         }
1391                         else {
1392                                 NEW_INS (cfg, temp, OP_I8CONST);
1393                                 temp->inst_c0 = ins->inst_offset;
1394                                 temp->dreg = mono_alloc_ireg (cfg);
1395
1396                                 NEW_INS (cfg, temp2, OP_LADD);
1397                                 temp2->sreg1 = ins->inst_destbasereg;
1398                                 temp2->sreg2 = temp->dreg;
1399                                 temp2->dreg = mono_alloc_ireg (cfg);
1400                         }
1401
1402                         switch (ins->opcode) {
1403                         case OP_STOREI1_MEMBASE_IMM:
1404                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1405                                 break;
1406                         case OP_STOREI2_MEMBASE_IMM:
1407                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1408                                 break;
1409                         case OP_STOREI4_MEMBASE_IMM:
1410                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1411                                 break;
1412                         case OP_STOREI8_MEMBASE_IMM:
1413                         case OP_STORE_MEMBASE_IMM:
1414                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1415                                 break;
1416                         default:
1417                                 g_assert_not_reached ();
1418                         }
1419
1420                         if (ins->inst_imm == 0)
1421                                 ins->sreg1 = IA64_R0;
1422                         else {
1423                                 NEW_INS (cfg, temp3, OP_I8CONST);
1424                                 temp3->inst_c0 = ins->inst_imm;
1425                                 temp3->dreg = mono_alloc_ireg (cfg);
1426                                 ins->sreg1 = temp3->dreg;
1427                         }
1428
1429                         ins->inst_offset = 0;
1430                         if (temp2)
1431                                 ins->inst_destbasereg = temp2->dreg;
1432                         break;
1433                 case OP_STOREI1_MEMBASE_REG:
1434                 case OP_STOREI2_MEMBASE_REG:
1435                 case OP_STOREI4_MEMBASE_REG:
1436                 case OP_STOREI8_MEMBASE_REG:
1437                 case OP_STORER4_MEMBASE_REG:
1438                 case OP_STORER8_MEMBASE_REG:
1439                 case OP_STORE_MEMBASE_REG:
1440                         /* There are no store_membase instructions on ia64 */
1441                         if (ins->inst_offset == 0) {
1442                                 break;
1443                         }
1444                         else if (ia64_is_imm14 (ins->inst_offset)) {
1445                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1446                                 temp2->sreg1 = ins->inst_destbasereg;
1447                                 temp2->inst_imm = ins->inst_offset;
1448                                 temp2->dreg = mono_alloc_ireg (cfg);
1449                         }
1450                         else {
1451                                 NEW_INS (cfg, temp, OP_I8CONST);
1452                                 temp->inst_c0 = ins->inst_offset;
1453                                 temp->dreg = mono_alloc_ireg (cfg);
1454                                 NEW_INS (cfg, temp2, OP_LADD);
1455                                 temp2->sreg1 = ins->inst_destbasereg;
1456                                 temp2->sreg2 = temp->dreg;
1457                                 temp2->dreg = mono_alloc_ireg (cfg);
1458                         }
1459
1460                         ins->inst_offset = 0;
1461                         ins->inst_destbasereg = temp2->dreg;
1462                         break;
1463                 case OP_LOADI1_MEMBASE:
1464                 case OP_LOADU1_MEMBASE:
1465                 case OP_LOADI2_MEMBASE:
1466                 case OP_LOADU2_MEMBASE:
1467                 case OP_LOADI4_MEMBASE:
1468                 case OP_LOADU4_MEMBASE:
1469                 case OP_LOADI8_MEMBASE:
1470                 case OP_LOAD_MEMBASE:
1471                 case OP_LOADR4_MEMBASE:
1472                 case OP_LOADR8_MEMBASE:
1473                 case OP_ATOMIC_EXCHANGE_I4:
1474                 case OP_ATOMIC_EXCHANGE_I8:
1475                 case OP_ATOMIC_ADD_NEW_I4:
1476                 case OP_ATOMIC_ADD_NEW_I8:
1477                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1478                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1479                         /* There are no membase instructions on ia64 */
1480                         if (ins->inst_offset == 0) {
1481                                 break;
1482                         }
1483                         else if (ia64_is_imm14 (ins->inst_offset)) {
1484                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1485                                 temp2->sreg1 = ins->inst_basereg;
1486                                 temp2->inst_imm = ins->inst_offset;
1487                                 temp2->dreg = mono_alloc_ireg (cfg);
1488                         }
1489                         else {
1490                                 NEW_INS (cfg, temp, OP_I8CONST);
1491                                 temp->inst_c0 = ins->inst_offset;
1492                                 temp->dreg = mono_alloc_ireg (cfg);
1493                                 NEW_INS (cfg, temp2, OP_LADD);
1494                                 temp2->sreg1 = ins->inst_basereg;
1495                                 temp2->sreg2 = temp->dreg;
1496                                 temp2->dreg = mono_alloc_ireg (cfg);
1497                         }
1498
1499                         ins->inst_offset = 0;
1500                         ins->inst_basereg = temp2->dreg;
1501                         break;
1502                 case OP_ADD_IMM:
1503                 case OP_IADD_IMM:
1504                 case OP_LADD_IMM:
1505                 case OP_ISUB_IMM:
1506                 case OP_LSUB_IMM:
1507                 case OP_AND_IMM:
1508                 case OP_IAND_IMM:
1509                 case OP_LAND_IMM:
1510                 case OP_IOR_IMM:
1511                 case OP_LOR_IMM:
1512                 case OP_IXOR_IMM:
1513                 case OP_LXOR_IMM:
1514                 case OP_SHL_IMM:
1515                 case OP_SHR_IMM:
1516                 case OP_ISHL_IMM:
1517                 case OP_LSHL_IMM:
1518                 case OP_ISHR_IMM:
1519                 case OP_LSHR_IMM:
1520                 case OP_ISHR_UN_IMM:
1521                 case OP_LSHR_UN_IMM: {
1522                         gboolean is_imm = FALSE;
1523                         gboolean switched = FALSE;
1524
1525                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1526                                 ins->opcode = OP_ZEXT_I1;
1527                                 break;
1528                         }
1529
1530                         switch (ins->opcode) {
1531                         case OP_ADD_IMM:
1532                         case OP_IADD_IMM:
1533                         case OP_LADD_IMM:
1534                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1535                                 switched = TRUE;
1536                                 break;
1537                         case OP_ISUB_IMM:
1538                         case OP_LSUB_IMM:
1539                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1540                                 if (is_imm) {
1541                                         /* A = B - IMM -> A = B + (-IMM) */
1542                                         ins->inst_imm = - ins->inst_imm;
1543                                         ins->opcode = OP_IADD_IMM;
1544                                 }
1545                                 switched = TRUE;
1546                                 break;
1547                         case OP_IAND_IMM:
1548                         case OP_IOR_IMM:
1549                         case OP_IXOR_IMM:
1550                         case OP_AND_IMM:
1551                         case OP_LAND_IMM:
1552                         case OP_LOR_IMM:
1553                         case OP_LXOR_IMM:
1554                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1555                                 switched = TRUE;
1556                                 break;
1557                         case OP_SHL_IMM:
1558                         case OP_SHR_IMM:
1559                         case OP_ISHL_IMM:
1560                         case OP_LSHL_IMM:
1561                         case OP_ISHR_IMM:
1562                         case OP_LSHR_IMM:
1563                         case OP_ISHR_UN_IMM:
1564                         case OP_LSHR_UN_IMM:
1565                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1566                                 break;
1567                         default:
1568                                 break;
1569                         }
1570
1571                         if (is_imm) {
1572                                 if (switched)
1573                                         ins->sreg2 = ins->sreg1;
1574                                 break;
1575                         }
1576
1577                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1578
1579                         if (ins->inst_imm == 0)
1580                                 ins->sreg2 = IA64_R0;
1581                         else {
1582                                 NEW_INS (cfg, temp, OP_I8CONST);
1583                                 temp->inst_c0 = ins->inst_imm;
1584                                 temp->dreg = mono_alloc_ireg (cfg);
1585                                 ins->sreg2 = temp->dreg;
1586                         }
1587                         break;
1588                 }
1589                 case OP_COMPARE_IMM:
1590                 case OP_ICOMPARE_IMM:
1591                 case OP_LCOMPARE_IMM: {
1592                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1593                         gboolean imm;
1594                         CompRelation cond;
1595
1596                         next = ins->next;
1597
1598                         /* Branch opts can eliminate the branch */
1599                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1600                                 NULLIFY_INS (ins);
1601                                 break;
1602                         }
1603
1604                         /*
1605                          * The compare_imm instructions have switched up arguments, and
1606                          * some of them take an imm between -127 and 128.
1607                          */
1608                         next = ins->next;
1609                         cond = mono_opcode_to_cond (next->opcode);
1610                         if ((cond == CMP_LT) || (cond == CMP_GE))
1611                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1612                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1613                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1614                         else
1615                                 imm = ia64_is_imm8 (ins->inst_imm);
1616
1617                         if (imm) {
1618                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1619                                 ins->sreg2 = ins->sreg1;
1620                         }
1621                         else {
1622                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1623
1624                                 if (ins->inst_imm == 0)
1625                                         ins->sreg2 = IA64_R0;
1626                                 else {
1627                                         NEW_INS (cfg, temp, OP_I8CONST);
1628                                         temp->inst_c0 = ins->inst_imm;
1629                                         temp->dreg = mono_alloc_ireg (cfg);
1630                                         ins->sreg2 = temp->dreg;
1631                                 }
1632                         }
1633
1634                         if (MONO_IS_COND_BRANCH_OP (next)) {
1635                                 next->opcode = OP_IA64_BR_COND;
1636                                 next->inst_target_bb = next->inst_true_bb;
1637                         } else if (MONO_IS_COND_EXC (next)) {
1638                                 next->opcode = OP_IA64_COND_EXC;
1639                         } else if (MONO_IS_SETCC (next)) {
1640                                 next->opcode = OP_IA64_CSET;
1641                         } else {
1642                                 printf ("%s\n", mono_inst_name (next->opcode));
1643                                 NOT_IMPLEMENTED;
1644                         }
1645
1646                         break;
1647                 }
1648                 case OP_COMPARE:
1649                 case OP_ICOMPARE:
1650                 case OP_LCOMPARE:
1651                 case OP_FCOMPARE: {
1652                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1653
1654                         next = ins->next;
1655
1656                         /* Branch opts can eliminate the branch */
1657                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1658                                 NULLIFY_INS (ins);
1659                                 break;
1660                         }
1661
1662                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1663
1664                         if (MONO_IS_COND_BRANCH_OP (next)) {
1665                                 next->opcode = OP_IA64_BR_COND;
1666                                 next->inst_target_bb = next->inst_true_bb;
1667                         } else if (MONO_IS_COND_EXC (next)) {
1668                                 next->opcode = OP_IA64_COND_EXC;
1669                         } else if (MONO_IS_SETCC (next)) {
1670                                 next->opcode = OP_IA64_CSET;
1671                         } else {
1672                                 printf ("%s\n", mono_inst_name (next->opcode));
1673                                 NOT_IMPLEMENTED;
1674                         }
1675
1676                         break;
1677                 }
1678                 case OP_FCEQ:
1679                 case OP_FCGT:
1680                 case OP_FCGT_UN:
1681                 case OP_FCLT:
1682                 case OP_FCLT_UN:
1683                         /* The front end removes the fcompare, so introduce it again */
1684                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1685                         temp->sreg1 = ins->sreg1;
1686                         temp->sreg2 = ins->sreg2;
1687
1688                         ins->opcode = OP_IA64_CSET;
1689                         MONO_INST_NULLIFY_SREGS (ins);
1690                         break;
1691                 case OP_MUL_IMM:
1692                 case OP_LMUL_IMM:
1693                 case OP_IMUL_IMM: {
1694                         int i, sum_reg;
1695                         gboolean found = FALSE;
1696                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1697
1698                         /* First the easy cases */
1699                         if (ins->inst_imm == 1) {
1700                                 ins->opcode = OP_MOVE;
1701                                 break;
1702                         }
1703                         for (i = 1; i < 64; ++i)
1704                                 if (ins->inst_imm == (((gint64)1) << i)) {
1705                                         ins->opcode = shl_op;
1706                                         ins->inst_imm = i;
1707                                         found = TRUE;
1708                                         break;
1709                                 }
1710
1711                         /* This could be optimized */
1712                         if (!found) {
1713                                 sum_reg = 0;
1714                                 for (i = 0; i < 64; ++i) {
1715                                         if (ins->inst_imm & (((gint64)1) << i)) {
1716                                                 NEW_INS (cfg, temp, shl_op);
1717                                                 temp->dreg = mono_alloc_ireg (cfg);
1718                                                 temp->sreg1 = ins->sreg1;
1719                                                 temp->inst_imm = i;
1720
1721                                                 if (sum_reg == 0)
1722                                                         sum_reg = temp->dreg;
1723                                                 else {
1724                                                         NEW_INS (cfg, temp2, OP_LADD);
1725                                                         temp2->dreg = mono_alloc_ireg (cfg);
1726                                                         temp2->sreg1 = sum_reg;
1727                                                         temp2->sreg2 = temp->dreg;
1728                                                         sum_reg = temp2->dreg;
1729                                                 }
1730                                         }
1731                                 }
1732                                 ins->opcode = OP_MOVE;
1733                                 ins->sreg1 = sum_reg;
1734                         }
1735                         break;
1736                 }
1737                 case OP_LCONV_TO_OVF_U4:
1738                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1739                         temp->sreg1 = ins->sreg1;
1740                         temp->sreg2 = IA64_R0;
1741
1742                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1743                         temp->inst_p1 = (char*)"OverflowException";
1744
1745                         ins->opcode = OP_MOVE;
1746                         break;
1747                 case OP_LCONV_TO_OVF_I4_UN:
1748                         NEW_INS (cfg, temp, OP_ICONST);
1749                         temp->inst_c0 = 0x7fffffff;
1750                         temp->dreg = mono_alloc_ireg (cfg);
1751
1752                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1753                         temp2->sreg1 = ins->sreg1;
1754                         temp2->sreg2 = temp->dreg;
1755
1756                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1757                         temp->inst_p1 = (char*)"OverflowException";
1758
1759                         ins->opcode = OP_MOVE;
1760                         break;
1761                 case OP_FCONV_TO_I4:
1762                 case OP_FCONV_TO_I2:
1763                 case OP_FCONV_TO_U2:
1764                 case OP_FCONV_TO_I1:
1765                 case OP_FCONV_TO_U1:
1766                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1767                         temp->sreg1 = ins->sreg1;
1768                         temp->dreg = ins->dreg;
1769
1770                         switch (ins->opcode) {
1771                         case OP_FCONV_TO_I4:
1772                                 ins->opcode = OP_SEXT_I4;
1773                                 break;
1774                         case OP_FCONV_TO_I2:
1775                                 ins->opcode = OP_SEXT_I2;
1776                                 break;
1777                         case OP_FCONV_TO_U2:
1778                                 ins->opcode = OP_ZEXT_I4;
1779                                 break;
1780                         case OP_FCONV_TO_I1:
1781                                 ins->opcode = OP_SEXT_I1;
1782                                 break;
1783                         case OP_FCONV_TO_U1:
1784                                 ins->opcode = OP_ZEXT_I1;
1785                                 break;
1786                         default:
1787                                 g_assert_not_reached ();
1788                         }
1789                         ins->sreg1 = ins->dreg;
1790                         break;
1791                 default:
1792                         break;
1793                 }
1794                 last_ins = ins;
1795                 ins = ins->next;
1796         }
1797         bb->last_ins = last_ins;
1798
1799         bb->max_vreg = cfg->next_vreg;
1800 }
1801
1802 /*
1803  * emit_load_volatile_arguments:
1804  *
1805  *  Load volatile arguments from the stack to the original input registers.
1806  * Required before a tail call.
1807  */
1808 static Ia64CodegenState
1809 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1810 {
1811         MonoMethod *method = cfg->method;
1812         MonoMethodSignature *sig;
1813         MonoInst *ins;
1814         CallInfo *cinfo;
1815         guint32 i;
1816
1817         /* FIXME: Generate intermediate code instead */
1818
1819         sig = mono_method_signature (method);
1820
1821         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1822
1823         /* This is the opposite of the code in emit_prolog */
1824         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1825                 ArgInfo *ainfo = cinfo->args + i;
1826                 gint32 stack_offset;
1827                 MonoType *arg_type;
1828
1829                 ins = cfg->args [i];
1830
1831                 if (sig->hasthis && (i == 0))
1832                         arg_type = &mono_defaults.object_class->byval_arg;
1833                 else
1834                         arg_type = sig->params [i - sig->hasthis];
1835
1836                 arg_type = mono_type_get_underlying_type (arg_type);
1837
1838                 stack_offset = ainfo->offset + ARGS_OFFSET;
1839
1840                 /* Save volatile arguments to the stack */
1841                 if (ins->opcode != OP_REGVAR) {
1842                         switch (ainfo->storage) {
1843                         case ArgInIReg:
1844                         case ArgInFloatReg:
1845                                 /* FIXME: big offsets */
1846                                 g_assert (ins->opcode == OP_REGOFFSET);
1847                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1848                                 if (arg_type->byref)
1849                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1850                                 else {
1851                                         switch (arg_type->type) {
1852                                         case MONO_TYPE_R4:
1853                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1854                                                 break;
1855                                         case MONO_TYPE_R8:
1856                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1857                                                 break;
1858                                         default:
1859                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1860                                                 break;
1861                                         }
1862                                 }
1863                                 break;
1864                         case ArgOnStack:
1865                                 break;
1866                         default:
1867                                 NOT_IMPLEMENTED;
1868                         }
1869                 }
1870
1871                 if (ins->opcode == OP_REGVAR) {
1872                         /* Argument allocated to (non-volatile) register */
1873                         switch (ainfo->storage) {
1874                         case ArgInIReg:
1875                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1876                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1877                                 break;
1878                         case ArgOnStack:
1879                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1880                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1881                                 break;
1882                         default:
1883                                 NOT_IMPLEMENTED;
1884                         }
1885                 }
1886         }
1887
1888         return code;
1889 }
1890
1891 static Ia64CodegenState
1892 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1893 {
1894         CallInfo *cinfo;
1895         int i;
1896
1897         /* Move return value to the target register */
1898         switch (ins->opcode) {
1899         case OP_VOIDCALL:
1900         case OP_VOIDCALL_REG:
1901         case OP_VOIDCALL_MEMBASE:
1902                 break;
1903         case OP_CALL:
1904         case OP_CALL_REG:
1905         case OP_CALL_MEMBASE:
1906         case OP_LCALL:
1907         case OP_LCALL_REG:
1908         case OP_LCALL_MEMBASE:
1909                 g_assert (ins->dreg == IA64_R8);
1910                 break;
1911         case OP_FCALL:
1912         case OP_FCALL_REG:
1913         case OP_FCALL_MEMBASE:
1914                 g_assert (ins->dreg == 8);
1915                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1916                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1917                 break;
1918         case OP_VCALL:
1919         case OP_VCALL_REG:
1920         case OP_VCALL_MEMBASE:
1921         case OP_VCALL2:
1922         case OP_VCALL2_REG:
1923         case OP_VCALL2_MEMBASE: {
1924                 ArgStorage storage;
1925
1926                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1927                 storage = cinfo->ret.storage;
1928
1929                 if (storage == ArgAggregate) {
1930                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1931
1932                         /* Load address of stack space allocated for the return value */
1933                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1934                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1935                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1936
1937                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1938                                 switch (cinfo->ret.atype) {
1939                                 case AggregateNormal:
1940                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1941                                         break;
1942                                 case AggregateSingleHFA:
1943                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1944                                         break;
1945                                 case AggregateDoubleHFA:
1946                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1947                                         break;
1948                                 default:
1949                                         g_assert_not_reached ();
1950                                 }
1951                         }
1952                 }
1953                 break;
1954         }
1955         default:
1956                 g_assert_not_reached ();
1957         }
1958
1959         return code;
1960 }
1961
1962 #define add_patch_info(cfg,code,patch_type,data) do { \
1963         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1964 } while (0)
1965
1966 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1967         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1968     if (tins == NULL) \
1969         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1970     else \
1971                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1972         ia64_br_cond_pred (code, (predicate), 0); \
1973 } while (0)
1974
1975 static Ia64CodegenState
1976 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1977 {
1978         add_patch_info (cfg, code, patch_type, data);
1979
1980         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1981                 /* Indirect call */
1982                 /* mono_arch_patch_callsite will patch this */
1983                 /* mono_arch_nullify_class_init_trampoline will patch this */
1984                 ia64_movl (code, GP_SCRATCH_REG, 0);
1985                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1986                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1987                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1988                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1989         }
1990         else {
1991                 /* Can't use a direct call since the displacement might be too small */
1992                 /* mono_arch_patch_callsite will patch this */
1993                 ia64_movl (code, GP_SCRATCH_REG, 0);
1994                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
1995                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1996         }
1997
1998         return code;
1999 }
2000
2001 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2002
2003 void
2004 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2005 {
2006         MonoInst *ins;
2007         MonoCallInst *call;
2008         guint offset;
2009         Ia64CodegenState code;
2010         guint8 *code_start = cfg->native_code + cfg->code_len;
2011         MonoInst *last_ins = NULL;
2012         guint last_offset = 0;
2013         int max_len, cpos;
2014
2015         if (cfg->opt & MONO_OPT_LOOP) {
2016                 /* FIXME: */
2017         }
2018
2019         if (cfg->verbose_level > 2)
2020                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2021
2022         cpos = bb->max_offset;
2023
2024         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2025                 NOT_IMPLEMENTED;
2026         }
2027
2028         offset = code_start - cfg->native_code;
2029
2030         ia64_codegen_init (code, code_start);
2031
2032 #if 0
2033         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2034                 break_count ();
2035 #endif
2036
2037         MONO_BB_FOR_EACH_INS (bb, ins) {
2038                 offset = code.buf - cfg->native_code;
2039
2040                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2041
2042                 while (offset + max_len + 16 > cfg->code_size) {
2043                         ia64_codegen_close (code);
2044
2045                         offset = code.buf - cfg->native_code;
2046
2047                         cfg->code_size *= 2;
2048                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2049                         code_start = cfg->native_code + offset;
2050                         mono_jit_stats.code_reallocs++;
2051
2052                         ia64_codegen_init (code, code_start);
2053                 }
2054
2055                 mono_debug_record_line_number (cfg, ins, offset);
2056
2057                 switch (ins->opcode) {
2058                 case OP_ICONST:
2059                 case OP_I8CONST:
2060                         if (ia64_is_imm14 (ins->inst_c0))
2061                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2062                         else
2063                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2064                         break;
2065                 case OP_JUMP_TABLE:
2066                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2067                         ia64_movl (code, ins->dreg, 0);
2068                         break;
2069                 case OP_MOVE:
2070                         ia64_mov (code, ins->dreg, ins->sreg1);
2071                         break;
2072                 case OP_BR:
2073                 case OP_IA64_BR_COND: {
2074                         int pred = 0;
2075                         if (ins->opcode == OP_IA64_BR_COND)
2076                                 pred = 6;
2077                         if (ins->inst_target_bb->native_offset) {
2078                                 guint8 *pos = code.buf + code.nins;
2079
2080                                 ia64_br_cond_pred (code, pred, 0);
2081                                 ia64_begin_bundle (code);
2082                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2083                         } else {
2084                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2085                                 ia64_br_cond_pred (code, pred, 0);
2086                         }
2087                         break;
2088                 }
2089                 case OP_LABEL:
2090                         ia64_begin_bundle (code);
2091                         ins->inst_c0 = code.buf - cfg->native_code;
2092                         break;
2093                 case OP_NOP:
2094                 case OP_RELAXED_NOP:
2095                 case OP_DUMMY_USE:
2096                 case OP_DUMMY_STORE:
2097                 case OP_NOT_REACHED:
2098                 case OP_NOT_NULL:
2099                         break;
2100                 case OP_BR_REG:
2101                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2102                         ia64_br_cond_reg (code, IA64_B6);
2103                         break;
2104                 case OP_IADD:
2105                 case OP_LADD:
2106                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2107                         break;
2108                 case OP_ISUB:
2109                 case OP_LSUB:
2110                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2111                         break;
2112                 case OP_IAND:
2113                 case OP_LAND:
2114                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2115                         break;
2116                 case OP_IOR:
2117                 case OP_LOR:
2118                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2119                         break;
2120                 case OP_IXOR:
2121                 case OP_LXOR:
2122                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2123                         break;
2124                 case OP_INEG:
2125                 case OP_LNEG:
2126                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2127                         break;
2128                 case OP_INOT:
2129                 case OP_LNOT:
2130                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2131                         break;
2132                 case OP_ISHL:
2133                 case OP_LSHL:
2134                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2135                         break;
2136                 case OP_ISHR:
2137                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2138                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2139                         break;
2140                 case OP_LSHR:
2141                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2142                         break;
2143                 case OP_ISHR_UN:
2144                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2145                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2146                         break;
2147                 case OP_LSHR_UN:
2148                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2149                         break;
2150                 case OP_IADDCC:
2151                         /* p6 and p7 is set if there is signed/unsigned overflow */
2152
2153                         /* Set p8-p9 == (sreg2 > 0) */
2154                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2155
2156                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2157
2158                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2159                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2160                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2161                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2162
2163                         /* res <u sreg1 => unsigned overflow */
2164                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2165
2166                         /* FIXME: Predicate this since this is a side effect */
2167                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2168                         break;
2169                 case OP_ISUBCC:
2170                         /* p6 and p7 is set if there is signed/unsigned overflow */
2171
2172                         /* Set p8-p9 == (sreg2 > 0) */
2173                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2174
2175                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2176
2177                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2178                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2179                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2180                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2181
2182                         /* sreg1 <u sreg2 => unsigned overflow */
2183                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2184
2185                         /* FIXME: Predicate this since this is a side effect */
2186                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2187                         break;
2188                 case OP_ADDCC:
2189                         /* Same as OP_IADDCC */
2190                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2191
2192                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2193
2194                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2195                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2196
2197                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2198
2199                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2200                         break;
2201                 case OP_SUBCC:
2202                         /* Same as OP_ISUBCC */
2203
2204                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2205
2206                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2207
2208                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2209                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2210
2211                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2212
2213                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2214                         break;
2215                 case OP_ADD_IMM:
2216                 case OP_IADD_IMM:
2217                 case OP_LADD_IMM:
2218                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2219                         break;
2220                 case OP_IAND_IMM:
2221                 case OP_AND_IMM:
2222                 case OP_LAND_IMM:
2223                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2224                         break;
2225                 case OP_IOR_IMM:
2226                 case OP_LOR_IMM:
2227                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2228                         break;
2229                 case OP_IXOR_IMM:
2230                 case OP_LXOR_IMM:
2231                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2232                         break;
2233                 case OP_SHL_IMM:
2234                 case OP_ISHL_IMM:
2235                 case OP_LSHL_IMM:
2236                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2237                         break;
2238                 case OP_SHR_IMM:
2239                 case OP_LSHR_IMM:
2240                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2241                         break;
2242                 case OP_ISHR_IMM:
2243                         g_assert (ins->inst_imm <= 64);
2244                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2245                         break;
2246                 case OP_ISHR_UN_IMM:
2247                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2248                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2249                         break;
2250                 case OP_LSHR_UN_IMM:
2251                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2252                         break;
2253                 case OP_LMUL:
2254                         /* Based on gcc code */
2255                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2256                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2257                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2258                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2259                         break;
2260
2261                 case OP_STOREI1_MEMBASE_REG:
2262                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2263                         break;
2264                 case OP_STOREI2_MEMBASE_REG:
2265                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2266                         break;
2267                 case OP_STOREI4_MEMBASE_REG:
2268                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2269                         break;
2270                 case OP_STOREI8_MEMBASE_REG:
2271                 case OP_STORE_MEMBASE_REG:
2272                         if (ins->inst_offset != 0) {
2273                                 /* This is generated by local regalloc */
2274                                 if (ia64_is_imm14 (ins->inst_offset)) {
2275                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2276                                 } else {
2277                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2278                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2279                                 }
2280                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2281                         }
2282                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2283                         break;
2284
2285                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2286                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2287                         break;
2288                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2289                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2290                         break;
2291                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2292                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2293                         break;
2294                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2295                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2296                         break;
2297
2298                 case OP_LOADU1_MEMBASE:
2299                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2300                         break;
2301                 case OP_LOADU2_MEMBASE:
2302                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2303                         break;
2304                 case OP_LOADU4_MEMBASE:
2305                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2306                         break;
2307                 case OP_LOADI1_MEMBASE:
2308                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2309                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2310                         break;
2311                 case OP_LOADI2_MEMBASE:
2312                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2313                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2314                         break;
2315                 case OP_LOADI4_MEMBASE:
2316                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2317                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2318                         break;
2319                 case OP_LOAD_MEMBASE:
2320                 case OP_LOADI8_MEMBASE:
2321                         if (ins->inst_offset != 0) {
2322                                 /* This is generated by local regalloc */
2323                                 if (ia64_is_imm14 (ins->inst_offset)) {
2324                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2325                                 } else {
2326                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2327                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2328                                 }
2329                                 ins->inst_basereg = GP_SCRATCH_REG;
2330                         }
2331                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2332                         break;
2333
2334                 case OP_IA64_LOADU1_MEMBASE_INC:
2335                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2336                         break;
2337                 case OP_IA64_LOADU2_MEMBASE_INC:
2338                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2339                         break;
2340                 case OP_IA64_LOADU4_MEMBASE_INC:
2341                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2342                         break;
2343                 case OP_IA64_LOADI8_MEMBASE_INC:
2344                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2345                         break;
2346
2347                 case OP_SEXT_I1:
2348                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2349                         break;
2350                 case OP_SEXT_I2:
2351                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2352                         break;
2353                 case OP_SEXT_I4:
2354                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2355                         break;
2356                 case OP_ZEXT_I1:
2357                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2358                         break;
2359                 case OP_ZEXT_I2:
2360                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2361                         break;
2362                 case OP_ZEXT_I4:
2363                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2364                         break;
2365
2366                         /* Compare opcodes */
2367                 case OP_IA64_CMP4_EQ:
2368                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2369                         break;
2370                 case OP_IA64_CMP4_NE:
2371                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2372                         break;
2373                 case OP_IA64_CMP4_LE:
2374                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2375                         break;
2376                 case OP_IA64_CMP4_LT:
2377                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2378                         break;
2379                 case OP_IA64_CMP4_GE:
2380                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2381                         break;
2382                 case OP_IA64_CMP4_GT:
2383                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2384                         break;
2385                 case OP_IA64_CMP4_LT_UN:
2386                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2387                         break;
2388                 case OP_IA64_CMP4_LE_UN:
2389                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2390                         break;
2391                 case OP_IA64_CMP4_GT_UN:
2392                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2393                         break;
2394                 case OP_IA64_CMP4_GE_UN:
2395                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2396                         break;
2397                 case OP_IA64_CMP_EQ:
2398                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2399                         break;
2400                 case OP_IA64_CMP_NE:
2401                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2402                         break;
2403                 case OP_IA64_CMP_LE:
2404                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2405                         break;
2406                 case OP_IA64_CMP_LT:
2407                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_IA64_CMP_GE:
2410                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2411                         break;
2412                 case OP_IA64_CMP_GT:
2413                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2414                         break;
2415                 case OP_IA64_CMP_GT_UN:
2416                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2417                         break;
2418                 case OP_IA64_CMP_LT_UN:
2419                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2420                         break;
2421                 case OP_IA64_CMP_GE_UN:
2422                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2423                         break;
2424                 case OP_IA64_CMP_LE_UN:
2425                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2426                         break;
2427                 case OP_IA64_CMP4_EQ_IMM:
2428                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2429                         break;
2430                 case OP_IA64_CMP4_NE_IMM:
2431                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2432                         break;
2433                 case OP_IA64_CMP4_LE_IMM:
2434                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2435                         break;
2436                 case OP_IA64_CMP4_LT_IMM:
2437                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2438                         break;
2439                 case OP_IA64_CMP4_GE_IMM:
2440                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2441                         break;
2442                 case OP_IA64_CMP4_GT_IMM:
2443                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2444                         break;
2445                 case OP_IA64_CMP4_LT_UN_IMM:
2446                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2447                         break;
2448                 case OP_IA64_CMP4_LE_UN_IMM:
2449                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2450                         break;
2451                 case OP_IA64_CMP4_GT_UN_IMM:
2452                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2453                         break;
2454                 case OP_IA64_CMP4_GE_UN_IMM:
2455                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2456                         break;
2457                 case OP_IA64_CMP_EQ_IMM:
2458                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2459                         break;
2460                 case OP_IA64_CMP_NE_IMM:
2461                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2462                         break;
2463                 case OP_IA64_CMP_LE_IMM:
2464                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2465                         break;
2466                 case OP_IA64_CMP_LT_IMM:
2467                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2468                         break;
2469                 case OP_IA64_CMP_GE_IMM:
2470                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2471                         break;
2472                 case OP_IA64_CMP_GT_IMM:
2473                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2474                         break;
2475                 case OP_IA64_CMP_GT_UN_IMM:
2476                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2477                         break;
2478                 case OP_IA64_CMP_LT_UN_IMM:
2479                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2480                         break;
2481                 case OP_IA64_CMP_GE_UN_IMM:
2482                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2483                         break;
2484                 case OP_IA64_CMP_LE_UN_IMM:
2485                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2486                         break;
2487                 case OP_IA64_FCMP_EQ:
2488                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2489                         break;
2490                 case OP_IA64_FCMP_NE:
2491                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2492                         break;
2493                 case OP_IA64_FCMP_LT:
2494                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2495                         break;
2496                 case OP_IA64_FCMP_GT:
2497                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2498                         break;
2499                 case OP_IA64_FCMP_LE:
2500                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2501                         break;
2502                 case OP_IA64_FCMP_GE:
2503                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2504                         break;
2505                 case OP_IA64_FCMP_GT_UN:
2506                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2507                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2508                         break;
2509                 case OP_IA64_FCMP_LT_UN:
2510                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2511                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2512                         break;
2513                 case OP_IA64_FCMP_GE_UN:
2514                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2515                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2516                         break;
2517                 case OP_IA64_FCMP_LE_UN:
2518                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2519                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2520                         break;
2521
2522                 case OP_COND_EXC_IOV:
2523                 case OP_COND_EXC_OV:
2524                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2525                         break;
2526                 case OP_COND_EXC_IC:
2527                 case OP_COND_EXC_C:
2528                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2529                         break;
2530                 case OP_IA64_COND_EXC:
2531                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2532                         break;
2533                 case OP_IA64_CSET:
2534                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2535                         ia64_no_stop (code);
2536                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2537                         break;
2538                 case OP_ICONV_TO_I1:
2539                 case OP_LCONV_TO_I1:
2540                         /* FIXME: Is this needed ? */
2541                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2542                         break;
2543                 case OP_ICONV_TO_I2:
2544                 case OP_LCONV_TO_I2:
2545                         /* FIXME: Is this needed ? */
2546                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2547                         break;
2548                 case OP_LCONV_TO_I4:
2549                         /* FIXME: Is this needed ? */
2550                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2551                         break;
2552                 case OP_ICONV_TO_U1:
2553                 case OP_LCONV_TO_U1:
2554                         /* FIXME: Is this needed */
2555                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2556                         break;
2557                 case OP_ICONV_TO_U2:
2558                 case OP_LCONV_TO_U2:
2559                         /* FIXME: Is this needed */
2560                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2561                         break;
2562                 case OP_LCONV_TO_U4:
2563                         /* FIXME: Is this needed */
2564                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2565                         break;
2566                 case OP_ICONV_TO_I8:
2567                 case OP_ICONV_TO_I:
2568                 case OP_LCONV_TO_I8:
2569                 case OP_LCONV_TO_I:
2570                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2571                         break;
2572                 case OP_LCONV_TO_U8:
2573                 case OP_LCONV_TO_U:
2574                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2575                         break;
2576
2577                         /*
2578                          * FLOAT OPCODES
2579                          */
2580                 case OP_R8CONST: {
2581                         double d = *(double *)ins->inst_p0;
2582
2583                         if ((d == 0.0) && (mono_signbit (d) == 0))
2584                                 ia64_fmov (code, ins->dreg, 0);
2585                         else if (d == 1.0)
2586                                 ia64_fmov (code, ins->dreg, 1);
2587                         else {
2588                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2589                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2590                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2591                         }
2592                         break;
2593                 }
2594                 case OP_R4CONST: {
2595                         float f = *(float *)ins->inst_p0;
2596
2597                         if ((f == 0.0) && (mono_signbit (f) == 0))
2598                                 ia64_fmov (code, ins->dreg, 0);
2599                         else if (f == 1.0)
2600                                 ia64_fmov (code, ins->dreg, 1);
2601                         else {
2602                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2603                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2604                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2605                         }
2606                         break;
2607                 }
2608                 case OP_FMOVE:
2609                         ia64_fmov (code, ins->dreg, ins->sreg1);
2610                         break;
2611                 case OP_STORER8_MEMBASE_REG:
2612                         if (ins->inst_offset != 0) {
2613                                 /* This is generated by local regalloc */
2614                                 if (ia64_is_imm14 (ins->inst_offset)) {
2615                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2616                                 } else {
2617                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2618                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2619                                 }
2620                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2621                         }
2622                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2623                         break;
2624                 case OP_STORER4_MEMBASE_REG:
2625                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2626                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2627                         break;
2628                 case OP_LOADR8_MEMBASE:
2629                         if (ins->inst_offset != 0) {
2630                                 /* This is generated by local regalloc */
2631                                 if (ia64_is_imm14 (ins->inst_offset)) {
2632                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2633                                 } else {
2634                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2635                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2636                                 }
2637                                 ins->inst_basereg = GP_SCRATCH_REG;
2638                         }
2639                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2640                         break;
2641                 case OP_LOADR4_MEMBASE:
2642                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2643                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2644                         break;
2645                 case OP_ICONV_TO_R4:
2646                 case OP_LCONV_TO_R4:
2647                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2648                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2649                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2650                         break;
2651                 case OP_ICONV_TO_R8:
2652                 case OP_LCONV_TO_R8:
2653                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2654                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2655                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2656                         break;
2657                 case OP_FCONV_TO_R4:
2658                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2659                         break;
2660                 case OP_FCONV_TO_I8:
2661                 case OP_FCONV_TO_I:
2662                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2663                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2664                         break;
2665                 case OP_FADD:
2666                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2667                         break;
2668                 case OP_FSUB:
2669                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2670                         break;
2671                 case OP_FMUL:
2672                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2673                         break;
2674                 case OP_FNEG:
2675                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2676                         break;
2677                 case OP_CKFINITE:
2678                         /* Quiet NaN */
2679                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2680                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2681                         /* Signaling NaN */
2682                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2683                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2684                         /* Positive infinity */
2685                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2686                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2687                         /* Negative infinity */
2688                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2689                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2690                         break;
2691
2692                 /* Calls */
2693                 case OP_CHECK_THIS:
2694                         /* ensure ins->sreg1 is not NULL */
2695                         /* Can't use ld8 as this could be a vtype address */
2696                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2697                         break;
2698                 case OP_ARGLIST:
2699                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2700                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2701                         break;
2702                 case OP_FCALL:
2703                 case OP_LCALL:
2704                 case OP_VCALL:
2705                 case OP_VCALL2:
2706                 case OP_VOIDCALL:
2707                 case OP_CALL:
2708                         call = (MonoCallInst*)ins;
2709
2710                         if (ins->flags & MONO_INST_HAS_METHOD)
2711                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2712                         else
2713                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2714
2715                         code = emit_move_return_value (cfg, ins, code);
2716                         break;
2717
2718                 case OP_CALL_REG:
2719                 case OP_FCALL_REG:
2720                 case OP_LCALL_REG:
2721                 case OP_VCALL_REG:
2722                 case OP_VCALL2_REG:
2723                 case OP_VOIDCALL_REG: {
2724                         MonoCallInst *call = (MonoCallInst*)ins;
2725                         CallInfo *cinfo;
2726                         int out_reg;
2727
2728                         /*
2729                          * mono_arch_find_this_arg () needs to find the this argument in a global
2730                          * register.
2731                          */
2732                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2733                         out_reg = cfg->arch.reg_out0;
2734                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2735                                 out_reg ++;
2736                         ia64_mov (code, IA64_R10, out_reg);
2737
2738                         /* Indirect call */
2739                         ia64_mov (code, IA64_R8, ins->sreg1);
2740                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2741                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2742                         ia64_ld8 (code, IA64_GP, IA64_R8);
2743                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2744
2745                         code = emit_move_return_value (cfg, ins, code);
2746                         break;
2747                 }
2748                 case OP_FCALL_MEMBASE:
2749                 case OP_LCALL_MEMBASE:
2750                 case OP_VCALL_MEMBASE:
2751                 case OP_VCALL2_MEMBASE:
2752                 case OP_VOIDCALL_MEMBASE:
2753                 case OP_CALL_MEMBASE: {
2754                         MonoCallInst *call = (MonoCallInst*)ins;
2755                         CallInfo *cinfo;
2756                         int out_reg;
2757
2758                         ia64_mov (code, IA64_R11, ins->sreg1);
2759                         if (ia64_is_imm14 (ins->inst_offset))
2760                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2761                         else {
2762                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2763                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2764                         }
2765
2766                         if (call->method && ins->inst_offset < 0) {
2767                                 /*
2768                                  * This is a possible IMT call so save the IMT method in a global
2769                                  * register where mono_arch_find_imt_method () and its friends can
2770                                  * access it.
2771                                  */
2772                                 ia64_movl (code, IA64_R9, call->method);
2773                         }
2774
2775                         /*
2776                          * mono_arch_find_this_arg () needs to find the this argument in a global
2777                          * register.
2778                          */
2779                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2780                         out_reg = cfg->arch.reg_out0;
2781                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2782                                 out_reg ++;
2783                         ia64_mov (code, IA64_R10, out_reg);
2784
2785                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2786
2787                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2788
2789                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2790
2791                         code = emit_move_return_value (cfg, ins, code);
2792                         break;
2793                 }
2794                 case OP_JMP: {
2795                         /*
2796                          * Keep in sync with the code in emit_epilog.
2797                          */
2798
2799                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2800                                 NOT_IMPLEMENTED;
2801
2802                         g_assert (!cfg->method->save_lmf);
2803
2804                         /* Load arguments into their original registers */
2805                         code = emit_load_volatile_arguments (cfg, code);
2806
2807                         if (cfg->arch.stack_alloc_size) {
2808                                 if (cfg->arch.omit_fp) {
2809                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2810                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2811                                         else {
2812                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2813                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2814                                         }
2815                                 }
2816                                 else
2817                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2818                         }
2819                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2820                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2821
2822                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2823                         ia64_movl (code, GP_SCRATCH_REG, 0);
2824                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2825                         ia64_br_cond_reg (code, IA64_B6);
2826
2827                         break;
2828                 }
2829                 case OP_BREAK:
2830                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2831                         break;
2832
2833                 case OP_LOCALLOC: {
2834                         gint32 abi_offset;
2835
2836                         /* FIXME: Sigaltstack support */
2837
2838                         /* keep alignment */
2839                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2840                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2841                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2842
2843                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2844
2845                         ia64_mov (code, ins->dreg, IA64_SP);
2846
2847                         /* An area at sp is reserved by the ABI for parameter passing */
2848                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2849                         if (ia64_is_adds_imm (abi_offset))
2850                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2851                         else {
2852                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2853                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2854                         }
2855
2856                         if (ins->flags & MONO_INST_INIT) {
2857                                 /* Upper limit */
2858                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2859
2860                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2861
2862                                 /* Init loop */
2863                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2864                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2865                                 ia64_br_cond_pred (code, 8, -2);
2866
2867                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2868
2869                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2870                         }
2871
2872                         break;
2873                 }
2874                 case OP_LOCALLOC_IMM: {
2875                         gint32 abi_offset;
2876
2877                         /* FIXME: Sigaltstack support */
2878
2879                         gssize size = ins->inst_imm;
2880                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2881
2882                         if (ia64_is_adds_imm (size))
2883                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2884                         else
2885                                 ia64_movl (code, GP_SCRATCH_REG, size);
2886
2887                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2888                         ia64_mov (code, ins->dreg, IA64_SP);
2889
2890                         /* An area at sp is reserved by the ABI for parameter passing */
2891                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2892                         if (ia64_is_adds_imm (abi_offset))
2893                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2894                         else {
2895                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2896                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2897                         }
2898
2899                         if (ins->flags & MONO_INST_INIT) {
2900                                 /* Upper limit */
2901                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2902
2903                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2904
2905                                 /* Init loop */
2906                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2907                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2908                                 ia64_br_cond_pred (code, 8, -2);
2909
2910                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2911
2912                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2913                         }
2914
2915                         break;
2916                 }
2917                 case OP_TLS_GET:
2918                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2919                         ia64_ld8 (code, ins->dreg, ins->dreg);
2920                         break;
2921
2922                         /* Synchronization */
2923                 case OP_MEMORY_BARRIER:
2924                         ia64_mf (code);
2925                         break;
2926                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2927                         g_assert (ins->inst_offset == 0);
2928                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2929                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2930                         break;
2931                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2932                         g_assert (ins->inst_offset == 0);
2933                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2934                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2935                         break;
2936                 case OP_ATOMIC_EXCHANGE_I4:
2937                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2938                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2939                         break;
2940                 case OP_ATOMIC_EXCHANGE_I8:
2941                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2942                         break;
2943                 case OP_ATOMIC_ADD_NEW_I4: {
2944                         guint8 *label, *buf;
2945
2946                         /* From libatomic_ops */
2947                         ia64_mf (code);
2948
2949                         ia64_begin_bundle (code);
2950                         label = code.buf + code.nins;
2951                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2952                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2953                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2954                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2955                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2956                         buf = code.buf + code.nins;
2957                         ia64_br_cond_pred (code, 7, 0);
2958                         ia64_begin_bundle (code);
2959                         ia64_patch (buf, label);
2960                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2961                         break;
2962                 }
2963                 case OP_ATOMIC_ADD_NEW_I8: {
2964                         guint8 *label, *buf;
2965
2966                         /* From libatomic_ops */
2967                         ia64_mf (code);
2968
2969                         ia64_begin_bundle (code);
2970                         label = code.buf + code.nins;
2971                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2972                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2973                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2974                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2975                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2976                         buf = code.buf + code.nins;
2977                         ia64_br_cond_pred (code, 7, 0);
2978                         ia64_begin_bundle (code);
2979                         ia64_patch (buf, label);
2980                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2981                         break;
2982                 }
2983
2984                         /* Exception handling */
2985                 case OP_CALL_HANDLER:
2986                         /*
2987                          * Using a call instruction would mess up the register stack, so
2988                          * save the return address to a register and use a
2989                          * branch.
2990                          */
2991                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2992                         ia64_mov (code, IA64_R15, IA64_R0);
2993                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
2994                         /* Add the length of OP_CALL_HANDLER */
2995                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
2996                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2997                         ia64_movl (code, GP_SCRATCH_REG2, 0);
2998                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2999                         ia64_br_cond_reg (code, IA64_B6);
3000                         // FIXME:
3001                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3002                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3003                         break;
3004                 case OP_START_HANDLER: {
3005                         /*
3006                          * We receive the return address in GP_SCRATCH_REG.
3007                          */
3008                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3009
3010                         /*
3011                          * R15 determines our caller. It is used since it is writable using
3012                          * libunwind.
3013                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3014                          * R15 != 0 means we are called by call_filter ().
3015                          */
3016                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3017                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3018
3019                         ia64_br_cond_pred (code, 6, 6);
3020
3021                         /*
3022                          * Called by call_filter:
3023                          * Allocate a new stack frame, and set the fp register from the
3024                          * value passed in by the caller.
3025                          * We allocate a similar frame as is done by the prolog, so
3026                          * if an exception is thrown while executing the filter, the
3027                          * unwinder can unwind through the filter frame using the unwind
3028                          * info for the prolog.
3029                          */
3030                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3031                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3032                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3033                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3034                         /* Signal to endfilter that we are called by call_filter */
3035                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3036
3037                         /* Branch target: */
3038                         if (ia64_is_imm14 (spvar->inst_offset))
3039                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3040                         else {
3041                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3042                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3043                         }
3044
3045                         /* Save the return address */
3046                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3047                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3048
3049                         break;
3050                 }
3051                 case OP_ENDFINALLY:
3052                 case OP_ENDFILTER: {
3053                         /* FIXME: Return the value in ENDFILTER */
3054                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3055
3056                         /* Load the return address */
3057                         if (ia64_is_imm14 (spvar->inst_offset)) {
3058                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3059                         } else {
3060                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3061                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3062                         }
3063                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3064
3065                         /* Test caller */
3066                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3067                         ia64_br_cond_pred (code, 7, 4);
3068
3069                         /* Called by call_filter */
3070                         /* Pop frame */
3071                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3072                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3073                         ia64_br_ret_reg (code, IA64_B0);
3074
3075                         /* Called by CALL_HANDLER */
3076                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3077                         ia64_br_cond_reg (code, IA64_B6);
3078                         break;
3079                 }
3080                 case OP_THROW:
3081                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3082                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3083                                                           (gpointer)"mono_arch_throw_exception");
3084
3085                         /*
3086                          * This might be the last instruction in the method, so add a dummy
3087                          * instruction so the unwinder will work.
3088                          */
3089                         ia64_break_i (code, 0);
3090                         break;
3091                 case OP_RETHROW:
3092                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3093                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3094                                                           (gpointer)"mono_arch_rethrow_exception");
3095
3096                         ia64_break_i (code, 0);
3097                         break;
3098
3099                 default:
3100                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3101                         g_assert_not_reached ();
3102                 }
3103
3104                 if ((code.buf - cfg->native_code - offset) > max_len) {
3105                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3106                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3107                         g_assert_not_reached ();
3108                 }
3109
3110                 cpos += max_len;
3111
3112                 last_ins = ins;
3113                 last_offset = offset;
3114         }
3115
3116         ia64_codegen_close (code);
3117
3118         cfg->code_len = code.buf - cfg->native_code;
3119 }
3120
3121 void
3122 mono_arch_register_lowlevel_calls (void)
3123 {
3124 }
3125
3126 static Ia64InsType ins_types_in_template [32][3] = {
3127         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3128         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3129         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3130         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3131         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3132         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3133         {0, 0, 0},
3134         {0, 0, 0},
3135         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3136         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3137         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3138         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3145         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3147         {0, 0, 0},
3148         {0, 0, 0},
3149         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3150         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3153         {0, 0, 0},
3154         {0, 0, 0},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3157         {0, 0, 0},
3158         {0, 0, 0}
3159 };
3160
3161 static gboolean stops_in_template [32][3] = {
3162         { FALSE, FALSE, FALSE },
3163         { FALSE, FALSE, TRUE },
3164         { FALSE, TRUE, FALSE },
3165         { FALSE, TRUE, TRUE },
3166         { FALSE, FALSE, FALSE },
3167         { FALSE, FALSE, TRUE },
3168         { FALSE, FALSE, FALSE },
3169         { FALSE, FALSE, FALSE },
3170
3171         { FALSE, FALSE, FALSE },
3172         { FALSE, FALSE, TRUE },
3173         { TRUE, FALSE, FALSE },
3174         { TRUE, FALSE, TRUE },
3175         { FALSE, FALSE, FALSE },
3176         { FALSE, FALSE, TRUE },
3177         { FALSE, FALSE, FALSE },
3178         { FALSE, FALSE, TRUE },
3179
3180         { FALSE, FALSE, FALSE },
3181         { FALSE, FALSE, TRUE },
3182         { FALSE, FALSE, FALSE },
3183         { FALSE, FALSE, TRUE },
3184         { FALSE, FALSE, FALSE },
3185         { FALSE, FALSE, FALSE },
3186         { FALSE, FALSE, FALSE },
3187         { FALSE, FALSE, TRUE },
3188
3189         { FALSE, FALSE, FALSE },
3190         { FALSE, FALSE, TRUE },
3191         { FALSE, FALSE, FALSE },
3192         { FALSE, FALSE, FALSE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, TRUE },
3195         { FALSE, FALSE, FALSE },
3196         { FALSE, FALSE, FALSE }
3197 };
3198
3199 static int last_stop_in_template [32] = {
3200         -1, 2, 1, 2, -1, 2, -1, -1,
3201         -1, 2, 0, 2, -1, 2, -1, 2,
3202         -1, 2, -1, 2, -1, -1, -1, 2,
3203         -1, 2, -1, -1, -1, 2, -1, -1
3204 };
3205
3206 static guint64 nops_for_ins_types [6] = {
3207         IA64_NOP_I,
3208         IA64_NOP_I,
3209         IA64_NOP_M,
3210         IA64_NOP_F,
3211         IA64_NOP_B,
3212         IA64_NOP_X
3213 };
3214
3215 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3216
3217 /*
3218  * Debugging support
3219  */
3220
3221 #if 0
3222 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3223 #else
3224 #define DEBUG_INS_SCHED(a)
3225 #endif
3226
3227 static void
3228 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3229 {
3230         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3231         guint8 *deps = code->dep_info;
3232         gboolean need_stop, no_stop;
3233
3234         for (i = 0; i < code->nins; ++i)
3235                 stops [i] = FALSE;
3236
3237         ins_index = 0;
3238         current_deps_start = 0;
3239         current_ins_start = 0;
3240         deps_start [ins_index] = current_ins_start;
3241         pos = 0;
3242         no_stop = FALSE;
3243         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3244         while (pos < code->dep_info_pos) {
3245                 need_stop = FALSE;
3246                 switch (deps [pos]) {
3247                 case IA64_END_OF_INS:
3248                         ins_index ++;
3249                         current_ins_start = pos + 2;
3250                         deps_start [ins_index] = current_ins_start;
3251                         no_stop = FALSE;
3252                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3253                         break;
3254                 case IA64_NONE:
3255                         break;
3256                 case IA64_READ_GR:
3257                         reg = deps [pos + 1];
3258
3259                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3260                         for (i = current_deps_start; i < current_ins_start; i += 2)
3261                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3262                                         need_stop = TRUE;
3263                         break;
3264                 case IA64_WRITE_GR:
3265                         reg = code->dep_info [pos + 1];
3266
3267                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3268                         for (i = current_deps_start; i < current_ins_start; i += 2)
3269                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3270                                         need_stop = TRUE;
3271                         break;
3272                 case IA64_READ_PR:
3273                         reg = deps [pos + 1];
3274
3275                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3276                         for (i = current_deps_start; i < current_ins_start; i += 2)
3277                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3278                                         need_stop = TRUE;
3279                         break;
3280                 case IA64_READ_PR_BRANCH:
3281                         reg = deps [pos + 1];
3282
3283                         /* Writes to prs by non-float instructions are visible to branches */
3284                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3285                         for (i = current_deps_start; i < current_ins_start; i += 2)
3286                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3287                                         need_stop = TRUE;
3288                         break;
3289                 case IA64_WRITE_PR:
3290                         reg = code->dep_info [pos + 1];
3291
3292                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3293                         for (i = current_deps_start; i < current_ins_start; i += 2)
3294                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3295                                         need_stop = TRUE;
3296                         break;
3297                 case IA64_WRITE_PR_FLOAT:
3298                         reg = code->dep_info [pos + 1];
3299
3300                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3301                         for (i = current_deps_start; i < current_ins_start; i += 2)
3302                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3303                                         need_stop = TRUE;
3304                         break;
3305                 case IA64_READ_BR:
3306                         reg = deps [pos + 1];
3307
3308                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3309                         for (i = current_deps_start; i < current_ins_start; i += 2)
3310                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3311                                         need_stop = TRUE;
3312                         break;
3313                 case IA64_WRITE_BR:
3314                         reg = code->dep_info [pos + 1];
3315
3316                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3317                         for (i = current_deps_start; i < current_ins_start; i += 2)
3318                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3319                                         need_stop = TRUE;
3320                         break;
3321                 case IA64_READ_BR_BRANCH:
3322                         reg = deps [pos + 1];
3323
3324                         /* Writes to brs are visible to branches */
3325                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3326                         break;
3327                 case IA64_READ_FR:
3328                         reg = deps [pos + 1];
3329
3330                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3331                         for (i = current_deps_start; i < current_ins_start; i += 2)
3332                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3333                                         need_stop = TRUE;
3334                         break;
3335                 case IA64_WRITE_FR:
3336                         reg = code->dep_info [pos + 1];
3337
3338                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3339                         for (i = current_deps_start; i < current_ins_start; i += 2)
3340                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3341                                         need_stop = TRUE;
3342                         break;
3343                 case IA64_READ_AR:
3344                         reg = deps [pos + 1];
3345
3346                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3347                         for (i = current_deps_start; i < current_ins_start; i += 2)
3348                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3349                                         need_stop = TRUE;
3350                         break;
3351                 case IA64_WRITE_AR:
3352                         reg = code->dep_info [pos + 1];
3353
3354                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3355                         for (i = current_deps_start; i < current_ins_start; i += 2)
3356                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3357                                         need_stop = TRUE;
3358                         break;
3359                 case IA64_NO_STOP:
3360                         /*
3361                          * Explicitly indicate that a stop is not required. Useful for
3362                          * example when two predicated instructions with negated predicates
3363                          * write the same registers.
3364                          */
3365                         no_stop = TRUE;
3366                         break;
3367                 default:
3368                         g_assert_not_reached ();
3369                 }
3370                 pos += 2;
3371
3372                 if (need_stop && !no_stop) {
3373                         g_assert (ins_index > 0);
3374                         stops [ins_index - 1] = 1;
3375
3376                         DEBUG_INS_SCHED (printf ("STOP\n"));
3377                         current_deps_start = current_ins_start;
3378
3379                         /* Skip remaining deps for this instruction */
3380                         while (deps [pos] != IA64_END_OF_INS)
3381                                 pos += 2;
3382                 }
3383         }
3384
3385         if (code->nins > 0) {
3386                 /* No dependency info for the last instruction */
3387                 stops [code->nins - 1] = 1;
3388         }
3389
3390         deps_start [code->nins] = code->dep_info_pos;
3391 }
3392
3393 static void
3394 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3395 {
3396         int stop_pos, i, deps_to_shift, dep_shift;
3397
3398         g_assert (n <= code->nins);
3399
3400         // if (n > 1) printf ("FOUND: %ld.\n", template);
3401
3402         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3403
3404         stop_pos = last_stop_in_template [template] + 1;
3405         if (stop_pos > n)
3406                 stop_pos = n;
3407
3408         /* Compute the number of 'real' instructions before the stop */
3409         deps_to_shift = stop_pos;
3410         if (stop_pos >= 3 && (nops & (1 << 2)))
3411                 deps_to_shift --;
3412         if (stop_pos >= 2 && (nops & (1 << 1)))
3413                 deps_to_shift --;
3414         if (stop_pos >= 1 && (nops & (1 << 0)))
3415                 deps_to_shift --;
3416
3417         /*
3418          * We have to keep some dependencies whose instructions have been shifted
3419          * out of the buffer. So nullify the end_of_ins markers in the dependency
3420          * array.
3421          */
3422         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3423                 if (code->dep_info [i] == IA64_END_OF_INS)
3424                         code->dep_info [i] = IA64_NONE;
3425
3426         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3427         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3428         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3429
3430         dep_shift = deps_start [deps_to_shift];
3431         for (i = 0; i < code->nins + 1 - n; ++i)
3432                 deps_start [i] = deps_start [n + i] - dep_shift;
3433
3434         /* Determine the exact positions of instructions with unwind ops */
3435         if (code->unw_op_count) {
3436                 int ins_pos [16];
3437                 int curr_ins, curr_ins_pos;
3438
3439                 curr_ins = 0;
3440                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3441                 for (i = 0; i < 3; ++i) {
3442                         if (! (nops & (1 << i))) {
3443                                 ins_pos [curr_ins] = curr_ins_pos + i;
3444                                 curr_ins ++;
3445                         }
3446                 }
3447
3448                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3449                         if (code->unw_ops_pos [i] < n) {
3450                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3451                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3452                         }
3453                 }
3454                 if (code->unw_op_pos < code->unw_op_count)
3455                         code->unw_op_pos += n;
3456         }
3457
3458         if (n == code->nins) {
3459                 code->template = 0;
3460                 code->nins = 0;
3461         }
3462         else {
3463                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3464                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3465                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3466                 code->nins -= n;
3467         }
3468 }
3469
3470 void
3471 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3472 {
3473         int i, ins_type, template, nins_to_emit;
3474         int deps_start [16];
3475         int stops [16];
3476         gboolean found;
3477
3478         /*
3479          * We implement a simple scheduler which tries to put three instructions
3480          * per bundle, then two, then one.
3481          */
3482         ia64_analyze_deps (code, deps_start, stops);
3483
3484         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3485                 /* Find a suitable template */
3486                 for (template = 0; template < 32; ++template) {
3487                         if (stops_in_template [template][0] != stops [0] ||
3488                                 stops_in_template [template][1] != stops [1] ||
3489                                 stops_in_template [template][2] != stops [2])
3490                                 continue;
3491
3492                         found = TRUE;
3493                         for (i = 0; i < 3; ++i) {
3494                                 ins_type = ins_types_in_template [template][i];
3495                                 switch (code->itypes [i]) {
3496                                 case IA64_INS_TYPE_A:
3497                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3498                                         break;
3499                                 default:
3500                                         found &= (ins_type == code->itypes [i]);
3501                                         break;
3502                                 }
3503                         }
3504
3505                         if (found)
3506                                 found = debug_ins_sched ();
3507
3508                         if (found) {
3509                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3510                                 break;
3511                         }
3512                 }
3513         }
3514
3515         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3516                 /* Wait for more instructions */
3517                 return;
3518
3519         /* If it didn't work out, try putting two instructions into one bundle */
3520         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3521                 /* Try a nop at the end */
3522                 for (template = 0; template < 32; ++template) {
3523                         if (stops_in_template [template][0] != stops [0] ||
3524                                 ((stops_in_template [template][1] != stops [1]) &&
3525                                  (stops_in_template [template][2] != stops [1])))
3526
3527                                 continue;
3528
3529                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3530                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3531                                 continue;
3532
3533                         if (!debug_ins_sched ())
3534                                 continue;
3535
3536                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3537                         break;
3538                 }
3539         }
3540
3541         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3542                 /* Wait for more instructions */
3543                 return;
3544
3545         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3546                 /* Try a nop in the middle */
3547                 for (template = 0; template < 32; ++template) {
3548                         if (((stops_in_template [template][0] != stops [0]) &&
3549                                  (stops_in_template [template][1] != stops [0])) ||
3550                                 stops_in_template [template][2] != stops [1])
3551                                 continue;
3552
3553                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3554                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3555                                 continue;
3556
3557                         if (!debug_ins_sched ())
3558                                 continue;
3559
3560                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3561                         break;
3562                 }
3563         }
3564
3565         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3566                 /* Try a nop at the beginning */
3567                 for (template = 0; template < 32; ++template) {
3568                         if ((stops_in_template [template][1] != stops [0]) ||
3569                                 (stops_in_template [template][2] != stops [1]))
3570                                 continue;
3571
3572                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3573                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3574                                 continue;
3575
3576                         if (!debug_ins_sched ())
3577                                 continue;
3578
3579                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3580                         break;
3581                 }
3582         }
3583
3584         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3585                 /* Wait for more instructions */
3586                 return;
3587
3588         if (flush)
3589                 nins_to_emit = code->nins;
3590         else
3591                 nins_to_emit = 1;
3592
3593         while (nins_to_emit > 0) {
3594                 if (!debug_ins_sched ())
3595                         stops [0] = 1;
3596                 switch (code->itypes [0]) {
3597                 case IA64_INS_TYPE_A:
3598                         if (stops [0])
3599                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3600                         else
3601                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3602                         break;
3603                 case IA64_INS_TYPE_I:
3604                         if (stops [0])
3605                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3606                         else
3607                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3608                         break;
3609                 case IA64_INS_TYPE_M:
3610                         if (stops [0])
3611                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3612                         else
3613                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3614                         break;
3615                 case IA64_INS_TYPE_B:
3616                         if (stops [0])
3617                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3618                         else
3619                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3620                         break;
3621                 case IA64_INS_TYPE_F:
3622                         if (stops [0])
3623                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3624                         else
3625                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3626                         break;
3627                 case IA64_INS_TYPE_LX:
3628                         if (stops [0] || stops [1])
3629                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3630                         else
3631                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3632                         nins_to_emit --;
3633                         break;
3634                 default:
3635                         g_assert_not_reached ();
3636                 }
3637                 nins_to_emit --;
3638         }
3639 }
3640
3641 unw_dyn_region_info_t*
3642 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3643 {
3644         unw_dyn_region_info_t *r;
3645
3646         g_assert (code->nins == 0);
3647         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3648         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3649         r->op_count = code->unw_op_count;
3650         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3651         code->unw_op_count = 0;
3652         code->unw_op_pos = 0;
3653         code->region_start = code->buf;
3654
3655         return r;
3656 }
3657
3658 static void
3659 ia64_patch (unsigned char* code, gpointer target)
3660 {
3661         int template, i;
3662         guint64 instructions [3];
3663         guint8 gen_buf [16];
3664         Ia64CodegenState gen;
3665         int ins_to_skip;
3666         gboolean found;
3667
3668         /*
3669          * code encodes both the position inside the buffer and code.nins when
3670          * the instruction was emitted.
3671          */
3672         ins_to_skip = (guint64)code % 16;
3673         code = (unsigned char*)((guint64)code & ~15);
3674
3675         /*
3676          * Search for the first instruction which is 'patchable', skipping
3677          * ins_to_skip instructions.
3678          */
3679
3680         while (TRUE) {
3681
3682         template = ia64_bundle_template (code);
3683         instructions [0] = ia64_bundle_ins1 (code);
3684         instructions [1] = ia64_bundle_ins2 (code);
3685         instructions [2] = ia64_bundle_ins3 (code);
3686
3687         ia64_codegen_init (gen, gen_buf);
3688
3689         found = FALSE;
3690         for (i = 0; i < 3; ++i) {
3691                 guint64 ins = instructions [i];
3692                 int opcode = ia64_ins_opcode (ins);
3693
3694                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3695                         continue;
3696
3697                 if (ins_to_skip) {
3698                         ins_to_skip --;
3699                         continue;
3700                 }
3701
3702                 switch (ins_types_in_template [template][i]) {
3703                 case IA64_INS_TYPE_A:
3704                 case IA64_INS_TYPE_M:
3705                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3706                                 /* adds */
3707                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3708                                 instructions [i] = gen.instructions [0];
3709                                 found = TRUE;
3710                         }
3711                         else
3712                                 NOT_IMPLEMENTED;
3713                         break;
3714                 case IA64_INS_TYPE_B:
3715                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3716                                 /* br.cond */
3717                                 gint64 disp = ((guint8*)target - code) >> 4;
3718
3719                                 /* FIXME: hints */
3720                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3721
3722                                 instructions [i] = gen.instructions [0];
3723                                 found = TRUE;
3724                         }
3725                         else if (opcode == 5) {
3726                                 /* br.call */
3727                                 gint64 disp = ((guint8*)target - code) >> 4;
3728
3729                                 /* FIXME: hints */
3730                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3731                                 instructions [i] = gen.instructions [0];
3732                                 found = TRUE;
3733                         }
3734                         else
3735                                 NOT_IMPLEMENTED;
3736                         break;
3737                 case IA64_INS_TYPE_LX:
3738                         if (i == 1)
3739                                 break;
3740
3741                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3742                                 /* movl */
3743                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3744                                 instructions [1] = gen.instructions [0];
3745                                 instructions [2] = gen.instructions [1];
3746                                 found = TRUE;
3747                         }
3748                         else
3749                                 NOT_IMPLEMENTED;
3750
3751                         break;
3752                 default:
3753                         NOT_IMPLEMENTED;
3754                 }
3755
3756                 if (found) {
3757                         /* Rewrite code */
3758                         ia64_codegen_init (gen, code);
3759                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3760                         return;
3761                 }
3762         }
3763
3764         code += 16;
3765         }
3766 }
3767
3768 void
3769 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3770 {
3771         MonoJumpInfo *patch_info;
3772
3773         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3774                 unsigned char *ip = patch_info->ip.i + code;
3775                 const unsigned char *target;
3776
3777                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3778
3779                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3780                         continue;
3781                 if (mono_compile_aot) {
3782                         NOT_IMPLEMENTED;
3783                 }
3784
3785                 ia64_patch (ip, (gpointer)target);
3786         }
3787 }
3788
3789 guint8 *
3790 mono_arch_emit_prolog (MonoCompile *cfg)
3791 {
3792         MonoMethod *method = cfg->method;
3793         MonoMethodSignature *sig;
3794         MonoInst *inst;
3795         int alloc_size, pos, i;
3796         Ia64CodegenState code;
3797         CallInfo *cinfo;
3798
3799         sig = mono_method_signature (method);
3800         pos = 0;
3801
3802         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3803
3804         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3805
3806         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3807                 cfg->code_size += 1024;
3808         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3809                 cfg->code_size += 1024;
3810
3811         cfg->native_code = g_malloc (cfg->code_size);
3812
3813         ia64_codegen_init (code, cfg->native_code);
3814
3815         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3816         if (cfg->param_area)
3817                 alloc_size += cfg->param_area;
3818         if (alloc_size)
3819                 /* scratch area */
3820                 alloc_size += 16;
3821         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3822
3823         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3824                 /* Force sp to be saved/restored */
3825                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3826
3827         cfg->arch.stack_alloc_size = alloc_size;
3828
3829         pos = 0;
3830
3831         if (method->save_lmf) {
3832                 /* No LMF on IA64 */
3833         }
3834
3835         alloc_size -= pos;
3836
3837         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3838         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3839         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3840         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3841
3842         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3843                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3844                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3845                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3846                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3847         }
3848
3849         if (alloc_size) {
3850 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3851                 int pagesize = getpagesize ();
3852
3853                 if (alloc_size >= pagesize) {
3854                         gint32 remaining_size = alloc_size;
3855
3856                         /* Generate stack touching code */
3857                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3858                         while (remaining_size >= pagesize) {
3859                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3860                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3861                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3862                                 remaining_size -= pagesize;
3863                         }
3864                 }
3865 #endif
3866                 if (ia64_is_imm14 (-alloc_size)) {
3867                         if (cfg->arch.omit_fp)
3868                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3869                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3870                 }
3871                 else {
3872                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3873                         if (cfg->arch.omit_fp)
3874                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3875                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3876                 }
3877         }
3878
3879         ia64_begin_bundle (code);
3880
3881         /* Initialize unwind info */
3882         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3883
3884         if (sig->ret->type != MONO_TYPE_VOID) {
3885                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3886                         /* Save volatile arguments to the stack */
3887                         NOT_IMPLEMENTED;
3888                 }
3889         }
3890
3891         /* Keep this in sync with emit_load_volatile_arguments */
3892         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3893                 ArgInfo *ainfo = cinfo->args + i;
3894                 gint32 stack_offset;
3895                 MonoType *arg_type;
3896
3897                 inst = cfg->args [i];
3898
3899                 if (sig->hasthis && (i == 0))
3900                         arg_type = &mono_defaults.object_class->byval_arg;
3901                 else
3902                         arg_type = sig->params [i - sig->hasthis];
3903
3904                 arg_type = mono_type_get_underlying_type (arg_type);
3905
3906                 stack_offset = ainfo->offset + ARGS_OFFSET;
3907
3908                 /*
3909                  * FIXME: Native code might pass non register sized integers
3910                  * without initializing the upper bits.
3911                  */
3912                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3913                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3914
3915                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3916                         case OP_LOADI1_MEMBASE:
3917                                 ia64_sxt1 (code, reg, reg);
3918                                 break;
3919                         case OP_LOADU1_MEMBASE:
3920                                 ia64_zxt1 (code, reg, reg);
3921                                 break;
3922                         case OP_LOADI2_MEMBASE:
3923                                 ia64_sxt2 (code, reg, reg);
3924                                 break;
3925                         case OP_LOADU2_MEMBASE:
3926                                 ia64_zxt2 (code, reg, reg);
3927                                 break;
3928                         default:
3929                                 break;
3930                         }
3931                 }
3932
3933                 /* Save volatile arguments to the stack */
3934                 if (inst->opcode != OP_REGVAR) {
3935                         switch (ainfo->storage) {
3936                         case ArgInIReg:
3937                         case ArgInFloatReg:
3938                         case ArgInFloatRegR4:
3939                                 g_assert (inst->opcode == OP_REGOFFSET);
3940                                 if (ia64_is_adds_imm (inst->inst_offset))
3941                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3942                                 else {
3943                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3944                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3945                                 }
3946                                 if (arg_type->byref)
3947                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3948                                 else {
3949                                         switch (arg_type->type) {
3950                                         case MONO_TYPE_R4:
3951                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3952                                                 break;
3953                                         case MONO_TYPE_R8:
3954                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3955                                                 break;
3956                                         default:
3957                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3958                                                 break;
3959                                         }
3960                                 }
3961                                 break;
3962                         case ArgOnStack:
3963                                 break;
3964                         case ArgAggregate:
3965                                 if (ainfo->nslots != ainfo->nregs)
3966                                         NOT_IMPLEMENTED;
3967
3968                                 g_assert (inst->opcode == OP_REGOFFSET);
3969                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3970                                 for (i = 0; i < ainfo->nregs; ++i) {
3971                                         switch (ainfo->atype) {
3972                                         case AggregateNormal:
3973                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3974                                                 break;
3975                                         case AggregateSingleHFA:
3976                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3977                                                 break;
3978                                         case AggregateDoubleHFA:
3979                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3980                                                 break;
3981                                         default:
3982                                                 NOT_IMPLEMENTED;
3983                                         }
3984                                 }
3985                                 break;
3986                         default:
3987                                 g_assert_not_reached ();
3988                         }
3989                 }
3990
3991                 if (inst->opcode == OP_REGVAR) {
3992                         /* Argument allocated to (non-volatile) register */
3993                         switch (ainfo->storage) {
3994                         case ArgInIReg:
3995                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
3996                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
3997                                 break;
3998                         case ArgOnStack:
3999                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4000                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4001                                 break;
4002                         default:
4003                                 NOT_IMPLEMENTED;
4004                         }
4005                 }
4006         }
4007
4008         if (method->save_lmf) {
4009                 /* No LMF on IA64 */
4010         }
4011
4012         ia64_codegen_close (code);
4013
4014         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4015                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4016
4017         cfg->code_len = code.buf - cfg->native_code;
4018
4019         g_assert (cfg->code_len < cfg->code_size);
4020
4021         cfg->arch.prolog_end_offset = cfg->code_len;
4022
4023         return code.buf;
4024 }
4025
4026 void
4027 mono_arch_emit_epilog (MonoCompile *cfg)
4028 {
4029         MonoMethod *method = cfg->method;
4030         int i, pos;
4031         int max_epilog_size = 16 * 4;
4032         Ia64CodegenState code;
4033         guint8 *buf;
4034         CallInfo *cinfo;
4035         ArgInfo *ainfo;
4036
4037         if (mono_jit_trace_calls != NULL)
4038                 max_epilog_size += 1024;
4039
4040         cfg->arch.epilog_begin_offset = cfg->code_len;
4041
4042         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4043                 cfg->code_size *= 2;
4044                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4045                 mono_jit_stats.code_reallocs++;
4046         }
4047
4048         /* FIXME: Emit unwind info */
4049
4050         buf = cfg->native_code + cfg->code_len;
4051
4052         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4053                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4054
4055         ia64_codegen_init (code, buf);
4056
4057         /* the code restoring the registers must be kept in sync with OP_JMP */
4058         pos = 0;
4059
4060         if (method->save_lmf) {
4061                 /* No LMF on IA64 */
4062         }
4063
4064         /* Load returned vtypes into registers if needed */
4065         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4066         ainfo = &cinfo->ret;
4067         switch (ainfo->storage) {
4068         case ArgAggregate:
4069                 if (ainfo->nslots != ainfo->nregs)
4070                         NOT_IMPLEMENTED;
4071
4072                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4073                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4074                 for (i = 0; i < ainfo->nregs; ++i) {
4075                         switch (ainfo->atype) {
4076                         case AggregateNormal:
4077                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4078                                 break;
4079                         case AggregateSingleHFA:
4080                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4081                                 break;
4082                         case AggregateDoubleHFA:
4083                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4084                                 break;
4085                         default:
4086                                 g_assert_not_reached ();
4087                         }
4088                 }
4089                 break;
4090         default:
4091                 break;
4092         }
4093
4094         ia64_begin_bundle (code);
4095
4096         code.region_start = cfg->native_code;
4097
4098         /* Label the unwind state at the start of the exception throwing region */
4099         //ia64_unw_label_state (code, 1234);
4100
4101         if (cfg->arch.stack_alloc_size) {
4102                 if (cfg->arch.omit_fp) {
4103                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4104                                 ia64_unw_pop_frames (code, 1);
4105                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4106                         } else {
4107                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4108                                 ia64_unw_pop_frames (code, 1);
4109                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4110                         }
4111                 }
4112                 else {
4113                         ia64_unw_pop_frames (code, 1);
4114                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4115                 }
4116         }
4117         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4118         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4119         ia64_br_ret_reg (code, IA64_B0);
4120
4121         ia64_codegen_close (code);
4122
4123         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4124         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4125
4126         cfg->code_len = code.buf - cfg->native_code;
4127
4128         g_assert (cfg->code_len < cfg->code_size);
4129 }
4130
4131 void
4132 mono_arch_emit_exceptions (MonoCompile *cfg)
4133 {
4134         MonoJumpInfo *patch_info;
4135         int i, nthrows;
4136         Ia64CodegenState code;
4137         gboolean empty = TRUE;
4138         //unw_dyn_region_info_t *r_exceptions;
4139         MonoClass *exc_classes [16];
4140         guint8 *exc_throw_start [16], *exc_throw_end [16];
4141         guint32 code_size = 0;
4142
4143         /* Compute needed space */
4144         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4145                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4146                         code_size += 256;
4147                 if (patch_info->type == MONO_PATCH_INFO_R8)
4148                         code_size += 8 + 7; /* sizeof (double) + alignment */
4149                 if (patch_info->type == MONO_PATCH_INFO_R4)
4150                         code_size += 4 + 7; /* sizeof (float) + alignment */
4151         }
4152
4153         if (code_size == 0)
4154                 return;
4155
4156         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4157                 cfg->code_size *= 2;
4158                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4159                 mono_jit_stats.code_reallocs++;
4160         }
4161
4162         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4163
4164         /* The unwind state here is the same as before the epilog */
4165         //ia64_unw_copy_state (code, 1234);
4166
4167         /* add code to raise exceptions */
4168         /* FIXME: Optimize this */
4169         nthrows = 0;
4170         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4171                 switch (patch_info->type) {
4172                 case MONO_PATCH_INFO_EXC: {
4173                         MonoClass *exc_class;
4174                         guint8* throw_ip;
4175                         guint8* buf;
4176                         guint64 exc_token_index;
4177
4178                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4179                         g_assert (exc_class);
4180                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4181                         throw_ip = cfg->native_code + patch_info->ip.i;
4182
4183                         ia64_begin_bundle (code);
4184
4185                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4186
4187                         /* Find a throw sequence for the same exception class */
4188                         for (i = 0; i < nthrows; ++i)
4189                                 if (exc_classes [i] == exc_class)
4190                                         break;
4191
4192                         if (i < nthrows) {
4193                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4194
4195                                 if (ia64_is_adds_imm (offset))
4196                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4197                                 else
4198                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4199
4200                                 buf = code.buf + code.nins;
4201                                 ia64_br_cond_pred (code, 0, 0);
4202                                 ia64_begin_bundle (code);
4203                                 ia64_patch (buf, exc_throw_start [i]);
4204
4205                                 patch_info->type = MONO_PATCH_INFO_NONE;
4206                         }
4207                         else {
4208                                 /* Arg1 */
4209                                 buf = code.buf;
4210                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4211
4212                                 ia64_begin_bundle (code);
4213
4214                                 if (nthrows < 16) {
4215                                         exc_classes [nthrows] = exc_class;
4216                                         exc_throw_start [nthrows] = code.buf;
4217                                 }
4218
4219                                 /* Arg2 */
4220                                 if (ia64_is_adds_imm (exc_token_index))
4221                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4222                                 else
4223                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4224
4225                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4226                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4227                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4228
4229                                 /* Indirect call */
4230                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4231                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4232                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4233                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4234
4235                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4236
4237                                 /* Patch up the throw offset */
4238                                 ia64_begin_bundle (code);
4239
4240                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4241
4242                                 if (nthrows < 16) {
4243                                         exc_throw_end [nthrows] = code.buf;
4244                                         nthrows ++;
4245                                 }
4246                         }
4247
4248                         empty = FALSE;
4249                         break;
4250                 }
4251                 default:
4252                         break;
4253                 }
4254         }
4255
4256         if (!empty)
4257                 /* The unwinder needs this to work */
4258                 ia64_break_i (code, 0);
4259
4260         ia64_codegen_close (code);
4261
4262         /* FIXME: */
4263         //r_exceptions = mono_ia64_create_unwind_region (&code);
4264         //cfg->arch.r_epilog = r_exceptions;
4265
4266         cfg->code_len = code.buf - cfg->native_code;
4267
4268         g_assert (cfg->code_len < cfg->code_size);
4269 }
4270
4271 void*
4272 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4273 {
4274         Ia64CodegenState code;
4275         CallInfo *cinfo = NULL;
4276         MonoMethodSignature *sig;
4277         MonoInst *ins;
4278         int i, n, stack_area = 0;
4279
4280         ia64_codegen_init (code, p);
4281
4282         /* Keep this in sync with mono_arch_get_argument_info */
4283
4284         if (enable_arguments) {
4285                 /* Allocate a new area on the stack and save arguments there */
4286                 sig = mono_method_signature (cfg->method);
4287
4288                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4289
4290                 n = sig->param_count + sig->hasthis;
4291
4292                 stack_area = ALIGN_TO (n * 8, 16);
4293
4294                 if (n) {
4295                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4296
4297                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4298
4299                         /* FIXME: Allocate out registers */
4300
4301                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4302
4303                         /* Required by the ABI */
4304                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4305
4306                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4307                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4308
4309                         /* Save arguments to the stack */
4310                         for (i = 0; i < n; ++i) {
4311                                 ins = cfg->args [i];
4312
4313                                 if (ins->opcode == OP_REGVAR) {
4314                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4315                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4316                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4317                                 }
4318                                 else {
4319                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4320                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4321                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4322                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4323                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4324                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4325                                 }
4326                         }
4327                 }
4328                 else
4329                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4330         }
4331         else
4332                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4333
4334         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4335         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4336
4337         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4338
4339         if (enable_arguments && stack_area) {
4340                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4341
4342                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4343
4344                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4345         }
4346
4347         ia64_codegen_close (code);
4348
4349         return code.buf;
4350 }
4351
4352 void*
4353 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4354 {
4355         Ia64CodegenState code;
4356         CallInfo *cinfo = NULL;
4357         MonoMethod *method = cfg->method;
4358         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4359
4360         ia64_codegen_init (code, p);
4361
4362         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4363
4364         /* Save return value + pass it to func */
4365         switch (cinfo->ret.storage) {
4366         case ArgNone:
4367                 break;
4368         case ArgInIReg:
4369                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4370                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4371                 break;
4372         case ArgInFloatReg:
4373                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4374                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4375                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4376                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4377                 break;
4378         case ArgValuetypeAddrInIReg:
4379                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4380                 break;
4381         case ArgAggregate:
4382                 NOT_IMPLEMENTED;
4383                 break;
4384         default:
4385                 break;
4386         }
4387
4388         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4389         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4390         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4391
4392         /* Restore return value */
4393         switch (cinfo->ret.storage) {
4394         case ArgNone:
4395                 break;
4396         case ArgInIReg:
4397                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4398                 break;
4399         case ArgInFloatReg:
4400                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4401                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4402                 break;
4403         case ArgValuetypeAddrInIReg:
4404                 break;
4405         case ArgAggregate:
4406                 break;
4407         default:
4408                 break;
4409         }
4410
4411         ia64_codegen_close (code);
4412
4413         return code.buf;
4414 }
4415
4416 void
4417 mono_arch_save_unwind_info (MonoCompile *cfg)
4418 {
4419         unw_dyn_info_t *di;
4420
4421         /* FIXME: Unregister this for dynamic methods */
4422
4423         di = g_malloc0 (sizeof (unw_dyn_info_t));
4424         di->start_ip = (unw_word_t) cfg->native_code;
4425         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4426         di->gp = 0;
4427         di->format = UNW_INFO_FORMAT_DYNAMIC;
4428         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4429         di->u.pi.regions = cfg->arch.r_pro;
4430
4431         _U_dyn_register (di);
4432
4433         /*
4434         {
4435                 unw_dyn_region_info_t *region = di->u.pi.regions;
4436
4437                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4438                 while (region) {
4439                         printf ("    [Region: %d]\n", region->insn_count);
4440                         region = region->next;
4441                 }
4442         }
4443         */
4444 }
4445
4446 void
4447 mono_arch_flush_icache (guint8 *code, gint size)
4448 {
4449         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4450         guint8* end = (guint8*)((guint64)code + size);
4451
4452 #ifdef __INTEL_COMPILER
4453         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4454         while (p < end) {
4455                 __fc ((guint64)p);
4456                 p += 32;
4457         }
4458 #else
4459         while (p < end) {
4460                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4461                 /* FIXME: This could be increased to 128 on some cpus */
4462                 p += 32;
4463         }
4464 #endif
4465 }
4466
4467 void
4468 mono_arch_flush_register_windows (void)
4469 {
4470         /* Not needed because of libunwind */
4471 }
4472
4473 gboolean
4474 mono_arch_is_inst_imm (gint64 imm)
4475 {
4476         /* The lowering pass will take care of it */
4477
4478         return TRUE;
4479 }
4480
4481 /*
4482  * Determine whenever the trap whose info is in SIGINFO is caused by
4483  * integer overflow.
4484  */
4485 gboolean
4486 mono_arch_is_int_overflow (void *sigctx, void *info)
4487 {
4488         /* Division is emulated with explicit overflow checks */
4489         return FALSE;
4490 }
4491
4492 guint32
4493 mono_arch_get_patch_offset (guint8 *code)
4494 {
4495         NOT_IMPLEMENTED;
4496
4497         return 0;
4498 }
4499
4500 gpointer
4501 mono_arch_get_vcall_slot (guint8* code, mgreg_t *regs, int *displacement)
4502 {
4503         /* Not used on IA64 */
4504         g_assert_not_reached ();
4505         return NULL;
4506 }
4507
4508 gpointer*
4509 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4510 {
4511         NOT_IMPLEMENTED;
4512
4513         return NULL;
4514 }
4515
4516 void
4517 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4518 {
4519 }
4520
4521 void
4522 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4523 {
4524 }
4525
4526 #ifdef MONO_ARCH_HAVE_IMT
4527
4528 /*
4529  * LOCKING: called with the domain lock held
4530  */
4531 gpointer
4532 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4533         gpointer fail_tramp)
4534 {
4535         int i;
4536         int size = 0;
4537         guint8 *start, *buf;
4538         Ia64CodegenState code;
4539
4540         size = count * 256;
4541         buf = g_malloc0 (size);
4542         ia64_codegen_init (code, buf);
4543
4544         /* IA64_R9 contains the IMT method */
4545
4546         for (i = 0; i < count; ++i) {
4547                 MonoIMTCheckItem *item = imt_entries [i];
4548                 ia64_begin_bundle (code);
4549                 item->code_target = (guint8*)code.buf + code.nins;
4550                 if (item->is_equals) {
4551                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4552
4553                         if (item->check_target_idx || fail_case) {
4554                                 if (!item->compare_done || fail_case) {
4555                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4556                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4557                                 }
4558                                 item->jmp_code = (guint8*)code.buf + code.nins;
4559                                 ia64_br_cond_pred (code, 7, 0);
4560
4561                                 if (item->has_target_code) {
4562                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4563                                 } else {
4564                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4565                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4566                                 }
4567                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4568                                 ia64_br_cond_reg (code, IA64_B6);
4569
4570                                 if (fail_case) {
4571                                         ia64_begin_bundle (code);
4572                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4573                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4574                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4575                                         ia64_br_cond_reg (code, IA64_B6);
4576                                         item->jmp_code = NULL;
4577                                 }
4578                         } else {
4579                                 /* enable the commented code to assert on wrong method */
4580 #if ENABLE_WRONG_METHOD_CHECK
4581                                 g_assert_not_reached ();
4582 #endif
4583                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4584                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4585                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4586                                 ia64_br_cond_reg (code, IA64_B6);
4587 #if ENABLE_WRONG_METHOD_CHECK
4588                                 g_assert_not_reached ();
4589 #endif
4590                         }
4591                 } else {
4592                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4593                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4594                         item->jmp_code = (guint8*)code.buf + code.nins;
4595                         ia64_br_cond_pred (code, 6, 0);
4596                 }
4597         }
4598         /* patch the branches to get to the target items */
4599         for (i = 0; i < count; ++i) {
4600                 MonoIMTCheckItem *item = imt_entries [i];
4601                 if (item->jmp_code) {
4602                         if (item->check_target_idx) {
4603                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4604                         }
4605                 }
4606         }
4607
4608         ia64_codegen_close (code);
4609         g_assert (code.buf - buf <= size);
4610
4611         size = code.buf - buf;
4612         if (fail_tramp) {
4613                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4614                 start = (gpointer)ALIGN_TO (start, 16);
4615         } else {
4616                 start = mono_domain_code_reserve (domain, size);
4617         }
4618         memcpy (start, buf, size);
4619
4620         mono_arch_flush_icache (start, size);
4621
4622         mono_stats.imt_thunks_size += size;
4623
4624         return start;
4625 }
4626
4627 MonoMethod*
4628 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4629 {
4630         return (MonoMethod*)regs [IA64_R9];
4631 }
4632
4633 void
4634 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4635 {
4636         /* Done by the implementation of the CALL_MEMBASE opcodes */
4637 }
4638 #endif
4639
4640 gpointer
4641 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
4642 {
4643         return (gpointer)regs [IA64_R10];
4644 }
4645
4646 gpointer
4647 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4648 {
4649         return NULL;
4650 }
4651
4652 MonoInst*
4653 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4654 {
4655         MonoInst *ins = NULL;
4656
4657         if (cmethod->klass->image == mono_defaults.corlib &&
4658                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4659                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4660
4661                 /*
4662                  * We don't use the generic version in mini_emit_inst_for_method () since we
4663                  * ia64 has atomic_add_imm opcodes.
4664                  */
4665                 if (strcmp (cmethod->name, "Increment") == 0) {
4666                         guint32 opcode;
4667
4668                         if (fsig->params [0]->type == MONO_TYPE_I4)
4669                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4670                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4671                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4672                         else
4673                                 g_assert_not_reached ();
4674                         MONO_INST_NEW (cfg, ins, opcode);
4675                         ins->dreg = mono_alloc_preg (cfg);
4676                         ins->inst_imm = 1;
4677                         ins->inst_basereg = args [0]->dreg;
4678                         ins->inst_offset = 0;
4679                         MONO_ADD_INS (cfg->cbb, ins);
4680                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4681                         guint32 opcode;
4682
4683                         if (fsig->params [0]->type == MONO_TYPE_I4)
4684                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4685                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4686                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4687                         else
4688                                 g_assert_not_reached ();
4689                         MONO_INST_NEW (cfg, ins, opcode);
4690                         ins->dreg = mono_alloc_preg (cfg);
4691                         ins->inst_imm = -1;
4692                         ins->inst_basereg = args [0]->dreg;
4693                         ins->inst_offset = 0;
4694                         MONO_ADD_INS (cfg->cbb, ins);
4695                 } else if (strcmp (cmethod->name, "Add") == 0) {
4696                         guint32 opcode;
4697                         gboolean is_imm = FALSE;
4698                         gint64 imm = 0;
4699
4700                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4701                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4702
4703                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4704                         }
4705
4706                         if (is_imm) {
4707                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4708                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4709                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4710                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4711                                 else
4712                                         g_assert_not_reached ();
4713
4714                                 MONO_INST_NEW (cfg, ins, opcode);
4715                                 ins->dreg = mono_alloc_ireg (cfg);
4716                                 ins->inst_basereg = args [0]->dreg;
4717                                 ins->inst_offset = 0;
4718                                 ins->inst_imm = imm;
4719                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4720                         } else {
4721                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4722                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4723                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4724                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4725                                 else
4726                                         g_assert_not_reached ();
4727
4728                                 MONO_INST_NEW (cfg, ins, opcode);
4729                                 ins->dreg = mono_alloc_ireg (cfg);
4730                                 ins->inst_basereg = args [0]->dreg;
4731                                 ins->inst_offset = 0;
4732                                 ins->sreg2 = args [1]->dreg;
4733                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4734                         }
4735                         MONO_ADD_INS (cfg->cbb, ins);
4736                 }
4737         }
4738
4739         return ins;
4740 }
4741
4742 gboolean
4743 mono_arch_print_tree (MonoInst *tree, int arity)
4744 {
4745         return 0;
4746 }
4747
4748 MonoInst*
4749 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4750 {
4751         return mono_get_domain_intrinsic (cfg);
4752 }
4753
4754 gpointer
4755 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4756 {
4757         /* FIXME: implement */
4758         g_assert_not_reached ();
4759 }