mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 G_GNUC_UNUSED static void
 113 break_count (void)
 114 {
 115 }
 116
 117 G_GNUC_UNUSED static gboolean
 118 debug_count (void)
 119 {
 120         static int count = 0;
 121         count ++;
 122
 123         if (count == atoi (getenv ("COUNT"))) {
 124                 break_count ();
 125         }
 126
 127         if (count > atoi (getenv ("COUNT"))) {
 128                 return FALSE;
 129         }
 130
 131         return TRUE;
 132 }
 133
 134 static gboolean
 135 debug_ins_sched (void)
 136 {
 137 #if 0
 138         return debug_count ();
 139 #else
 140         return TRUE;
 141 #endif
 142 }
 143
 144 static gboolean
 145 debug_omit_fp (void)
 146 {
 147 #if 0
 148         return debug_count ();
 149 #else
 150         return TRUE;
 151 #endif
 152 }
 153
 154 static void
 155 ia64_patch (unsigned char* code, gpointer target);
 156
 157 typedef enum {
 158         ArgInIReg,
 159         ArgInFloatReg,
 160         ArgInFloatRegR4,
 161         ArgOnStack,
 162         ArgValuetypeAddrInIReg,
 163         ArgAggregate,
 164         ArgSingleHFA,
 165         ArgDoubleHFA,
 166         ArgNone
 167 } ArgStorage;
 168
 169 typedef enum {
 170         AggregateNormal,
 171         AggregateSingleHFA,
 172         AggregateDoubleHFA
 173 } AggregateType;
 174
 175 typedef struct {
 176         gint16 offset;
 177         gint8  reg;
 178         ArgStorage storage;
 179
 180         /* Only if storage == ArgAggregate */
 181         int nregs, nslots;
 182         AggregateType atype;
 183 } ArgInfo;
 184
 185 typedef struct {
 186         int nargs;
 187         guint32 stack_usage;
 188         guint32 reg_usage;
 189         guint32 freg_usage;
 190         gboolean need_stack_align;
 191         gboolean vtype_retaddr;
 192         /* The index of the vret arg in the argument list */
 193         int vret_arg_index;
 194         ArgInfo ret;
 195         ArgInfo sig_cookie;
 196         ArgInfo args [1];
 197 } CallInfo;
 198
 199 #define DEBUG(a) if (cfg->verbose_level > 1) a
 200
 201 #define PARAM_REGS 8
 202
 203 static void inline
 204 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 205 {
 206     ainfo->offset = *stack_size;
 207
 208     if (*gr >= PARAM_REGS) {
 209                 ainfo->storage = ArgOnStack;
 210                 (*stack_size) += sizeof (gpointer);
 211     }
 212     else {
 213                 ainfo->storage = ArgInIReg;
 214                 ainfo->reg = *gr;
 215                 *(gr) += 1;
 216     }
 217 }
 218
 219 #define FLOAT_PARAM_REGS 8
 220
 221 static void inline
 222 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 (*stack_size) += sizeof (gpointer);
 229     }
 230     else {
 231                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 232                 ainfo->reg = 8 + *fr;
 233                 (*fr) += 1;
 234                 (*gr) += 1;
 235     }
 236 }
 237
 238 static void
 239 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 240                gboolean is_return,
 241                guint32 *gr, guint32 *fr, guint32 *stack_size)
 242 {
 243         guint32 size, i;
 244         MonoClass *klass;
 245         MonoMarshalType *info;
 246         gboolean is_hfa = TRUE;
 247         guint32 hfa_type = 0;
 248
 249         klass = mono_class_from_mono_type (type);
 250         if (type->type == MONO_TYPE_TYPEDBYREF)
 251                 size = 3 * sizeof (gpointer);
 252         else if (sig->pinvoke)
 253                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 254         else
 255                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 256
 257         if (!sig->pinvoke || (size == 0)) {
 258                 /* Allways pass in memory */
 259                 ainfo->offset = *stack_size;
 260                 *stack_size += ALIGN_TO (size, 8);
 261                 ainfo->storage = ArgOnStack;
 262
 263                 return;
 264         }
 265
 266         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 267         info = mono_marshal_load_type_info (klass);
 268         g_assert (info);
 269         for (i = 0; i < info->num_fields; ++i) {
 270                 guint32 ftype = info->fields [i].field->type->type;
 271                 if (!(info->fields [i].field->type->byref) &&
 272                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 273                         if (hfa_type == 0)
 274                                 hfa_type = ftype;
 275                         else if (hfa_type != ftype)
 276                                 is_hfa = FALSE;
 277                 }
 278                 else
 279                         is_hfa = FALSE;
 280         }
 281         if (hfa_type == 0)
 282                 is_hfa = FALSE;
 283
 284         ainfo->storage = ArgAggregate;
 285         ainfo->atype = AggregateNormal;
 286
 287         if (is_hfa) {
 288                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 289                 if (is_return) {
 290                         if (info->num_fields <= 8) {
 291                                 ainfo->reg = 8;
 292                                 ainfo->nregs = info->num_fields;
 293                                 ainfo->nslots = ainfo->nregs;
 294                                 return;
 295                         }
 296                         /* Fall through */
 297                 }
 298                 else {
 299                         if ((*fr) + info->num_fields > 8)
 300                                 NOT_IMPLEMENTED;
 301
 302                         ainfo->reg = 8 + (*fr);
 303                         ainfo->nregs = info->num_fields;
 304                         ainfo->nslots = ainfo->nregs;
 305                         (*fr) += info->num_fields;
 306                         if (ainfo->atype == AggregateSingleHFA) {
 307                                 /*
 308                                  * FIXME: Have to keep track of the parameter slot number, which is
 309                                  * not the same as *gr.
 310                                  */
 311                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 312                         } else {
 313                                 (*gr) += info->num_fields;
 314                         }
 315                         return;
 316                 }
 317         }
 318
 319         /* This also handles returning of TypedByRef used by some icalls */
 320         if (is_return) {
 321                 if (size <= 32) {
 322                         ainfo->reg = IA64_R8;
 323                         ainfo->nregs = (size + 7) / 8;
 324                         ainfo->nslots = ainfo->nregs;
 325                         return;
 326                 }
 327                 NOT_IMPLEMENTED;
 328         }
 329
 330         ainfo->reg = (*gr);
 331         ainfo->offset = *stack_size;
 332         ainfo->nslots = (size + 7) / 8;
 333
 334         if (((*gr) + ainfo->nslots) <= 8) {
 335                 /* Fits entirely in registers */
 336                 ainfo->nregs = ainfo->nslots;
 337                 (*gr) += ainfo->nregs;
 338                 return;
 339         }
 340
 341         ainfo->nregs = 8 - (*gr);
 342         (*gr) = 8;
 343         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 344 }
 345
 346 /*
 347  * get_call_info:
 348  *
 349  *  Obtain information about a call according to the calling convention.
 350  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 351  * Gude" document for more information.
 352  */
 353 static CallInfo*
 354 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 355 {
 356         guint32 i, gr, fr, pstart;
 357         MonoType *ret_type;
 358         int n = sig->hasthis + sig->param_count;
 359         guint32 stack_size = 0;
 360         CallInfo *cinfo;
 361         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 362
 363         if (mp)
 364                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 365         else
 366                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 367
 368         gr = 0;
 369         fr = 0;
 370
 371         /* return value */
 372         {
 373                 ret_type = mono_type_get_underlying_type (sig->ret);
 374                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 375                 switch (ret_type->type) {
 376                 case MONO_TYPE_BOOLEAN:
 377                 case MONO_TYPE_I1:
 378                 case MONO_TYPE_U1:
 379                 case MONO_TYPE_I2:
 380                 case MONO_TYPE_U2:
 381                 case MONO_TYPE_CHAR:
 382                 case MONO_TYPE_I4:
 383                 case MONO_TYPE_U4:
 384                 case MONO_TYPE_I:
 385                 case MONO_TYPE_U:
 386                 case MONO_TYPE_PTR:
 387                 case MONO_TYPE_FNPTR:
 388                 case MONO_TYPE_CLASS:
 389                 case MONO_TYPE_OBJECT:
 390                 case MONO_TYPE_SZARRAY:
 391                 case MONO_TYPE_ARRAY:
 392                 case MONO_TYPE_STRING:
 393                         cinfo->ret.storage = ArgInIReg;
 394                         cinfo->ret.reg = IA64_R8;
 395                         break;
 396                 case MONO_TYPE_U8:
 397                 case MONO_TYPE_I8:
 398                         cinfo->ret.storage = ArgInIReg;
 399                         cinfo->ret.reg = IA64_R8;
 400                         break;
 401                 case MONO_TYPE_R4:
 402                 case MONO_TYPE_R8:
 403                         cinfo->ret.storage = ArgInFloatReg;
 404                         cinfo->ret.reg = 8;
 405                         break;
 406                 case MONO_TYPE_GENERICINST:
 407                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 408                                 cinfo->ret.storage = ArgInIReg;
 409                                 cinfo->ret.reg = IA64_R8;
 410                                 break;
 411                         }
 412                         /* Fall through */
 413                 case MONO_TYPE_VALUETYPE:
 414                 case MONO_TYPE_TYPEDBYREF: {
 415                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 416
 417                         if (sig->ret->byref) {
 418                                 /* This seems to happen with ldfld wrappers */
 419                                 cinfo->ret.storage = ArgInIReg;
 420                         } else {
 421                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 422                                 if (cinfo->ret.storage == ArgOnStack) {
 423                                         /* The caller passes the address where the value is stored */
 424                                         cinfo->vtype_retaddr = TRUE;
 425                                 }
 426                         }
 427                         break;
 428                 }
 429                 case MONO_TYPE_VOID:
 430                         cinfo->ret.storage = ArgNone;
 431                         break;
 432                 default:
 433                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 434                 }
 435         }
 436
 437         pstart = 0;
 438         /*
 439          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 440          * the first argument, allowing 'this' to be always passed in the first arg reg.
 441          * Also do this if the first argument is a reference type, since virtual calls
 442          * are sometimes made using calli without sig->hasthis set, like in the delegate
 443          * invoke wrappers.
 444          */
 445         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 446                 if (sig->hasthis) {
 447                         add_general (&gr, &stack_size, cinfo->args + 0);
 448                 } else {
 449                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 450                         pstart = 1;
 451                 }
 452                 add_general (&gr, &stack_size, &cinfo->ret);
 453                 if (cinfo->ret.storage == ArgInIReg)
 454                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 455                 cinfo->vret_arg_index = 1;
 456         } else {
 457                 /* this */
 458                 if (sig->hasthis)
 459                         add_general (&gr, &stack_size, cinfo->args + 0);
 460
 461                 if (cinfo->vtype_retaddr) {
 462                         add_general (&gr, &stack_size, &cinfo->ret);
 463                         if (cinfo->ret.storage == ArgInIReg)
 464                                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
 465                 }
 466         }
 467
 468         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 469                 gr = PARAM_REGS;
 470                 fr = FLOAT_PARAM_REGS;
 471
 472                 /* Emit the signature cookie just before the implicit arguments */
 473                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 474         }
 475
 476         for (i = pstart; i < sig->param_count; ++i) {
 477                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 478                 MonoType *ptype;
 479
 480                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 481                         /* We allways pass the sig cookie on the stack for simplicity */
 482                         /*
 483                          * Prevent implicit arguments + the sig cookie from being passed
 484                          * in registers.
 485                          */
 486                         gr = PARAM_REGS;
 487                         fr = FLOAT_PARAM_REGS;
 488
 489                         /* Emit the signature cookie just before the implicit arguments */
 490                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 491                 }
 492
 493                 if (sig->params [i]->byref) {
 494                         add_general (&gr, &stack_size, ainfo);
 495                         continue;
 496                 }
 497                 ptype = mono_type_get_underlying_type (sig->params [i]);
 498                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 499                 switch (ptype->type) {
 500                 case MONO_TYPE_BOOLEAN:
 501                 case MONO_TYPE_I1:
 502                 case MONO_TYPE_U1:
 503                         add_general (&gr, &stack_size, ainfo);
 504                         break;
 505                 case MONO_TYPE_I2:
 506                 case MONO_TYPE_U2:
 507                 case MONO_TYPE_CHAR:
 508                         add_general (&gr, &stack_size, ainfo);
 509                         break;
 510                 case MONO_TYPE_I4:
 511                 case MONO_TYPE_U4:
 512                         add_general (&gr, &stack_size, ainfo);
 513                         break;
 514                 case MONO_TYPE_I:
 515                 case MONO_TYPE_U:
 516                 case MONO_TYPE_PTR:
 517                 case MONO_TYPE_FNPTR:
 518                 case MONO_TYPE_CLASS:
 519                 case MONO_TYPE_OBJECT:
 520                 case MONO_TYPE_STRING:
 521                 case MONO_TYPE_SZARRAY:
 522                 case MONO_TYPE_ARRAY:
 523                         add_general (&gr, &stack_size, ainfo);
 524                         break;
 525                 case MONO_TYPE_GENERICINST:
 526                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 527                                 add_general (&gr, &stack_size, ainfo);
 528                                 break;
 529                         }
 530                         /* Fall through */
 531                 case MONO_TYPE_VALUETYPE:
 532                 case MONO_TYPE_TYPEDBYREF:
 533                         /* FIXME: */
 534                         /* We allways pass valuetypes on the stack */
 535                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 536                         break;
 537                 case MONO_TYPE_U8:
 538                 case MONO_TYPE_I8:
 539                         add_general (&gr, &stack_size, ainfo);
 540                         break;
 541                 case MONO_TYPE_R4:
 542                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 543                         break;
 544                 case MONO_TYPE_R8:
 545                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 546                         break;
 547                 default:
 548                         g_assert_not_reached ();
 549                 }
 550         }
 551
 552         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 553                 gr = PARAM_REGS;
 554                 fr = FLOAT_PARAM_REGS;
 555
 556                 /* Emit the signature cookie just before the implicit arguments */
 557                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 558         }
 559
 560         cinfo->stack_usage = stack_size;
 561         cinfo->reg_usage = gr;
 562         cinfo->freg_usage = fr;
 563         return cinfo;
 564 }
 565
 566 /*
 567  * mono_arch_get_argument_info:
 568  * @csig:  a method signature
 569  * @param_count: the number of parameters to consider
 570  * @arg_info: an array to store the result infos
 571  *
 572  * Gathers information on parameters such as size, alignment and
 573  * padding. arg_info should be large enought to hold param_count + 1 entries.
 574  *
 575  * Returns the size of the argument area on the stack.
 576  */
 577 int
 578 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 579 {
 580         int k;
 581         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 582         guint32 args_size = cinfo->stack_usage;
 583
 584         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 585         if (csig->hasthis) {
 586                 arg_info [0].offset = 0;
 587         }
 588
 589         for (k = 0; k < param_count; k++) {
 590                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 591                 /* FIXME: */
 592                 arg_info [k + 1].size = 0;
 593         }
 594
 595         g_free (cinfo);
 596
 597         return args_size;
 598 }
 599
 600 /*
 601  * Initialize the cpu to execute managed code.
 602  */
 603 void
 604 mono_arch_cpu_init (void)
 605 {
 606 }
 607
 608 /*
 609  * Initialize architecture specific code.
 610  */
 611 void
 612 mono_arch_init (void)
 613 {
 614 }
 615
 616 /*
 617  * Cleanup architecture specific code.
 618  */
 619 void
 620 mono_arch_cleanup (void)
 621 {
 622 }
 623
 624 /*
 625  * This function returns the optimizations supported on this cpu.
 626  */
 627 guint32
 628 mono_arch_cpu_optimizations (guint32 *exclude_mask)
 629 {
 630         *exclude_mask = 0;
 631
 632         return 0;
 633 }
 634
 635 /*
 636  * This function test for all SIMD functions supported.
 637  *
 638  * Returns a bitmask corresponding to all supported versions.
 639  *
 640  */
 641 guint32
 642 mono_arch_cpu_enumerate_simd_versions (void)
 643 {
 644         /* SIMD is currently unimplemented */
 645         return 0;
 646 }
 647
 648 GList *
 649 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 650 {
 651         GList *vars = NULL;
 652         int i;
 653         MonoMethodSignature *sig;
 654         MonoMethodHeader *header;
 655         CallInfo *cinfo;
 656
 657         header = cfg->header;
 658
 659         sig = mono_method_signature (cfg->method);
 660
 661         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 662
 663         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 664                 MonoInst *ins = cfg->args [i];
 665
 666                 ArgInfo *ainfo = &cinfo->args [i];
 667
 668                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 669                         continue;
 670
 671                 if (ainfo->storage == ArgInIReg) {
 672                         /* The input registers are non-volatile */
 673                         ins->opcode = OP_REGVAR;
 674                         ins->dreg = 32 + ainfo->reg;
 675                 }
 676         }
 677
 678         for (i = 0; i < cfg->num_varinfo; i++) {
 679                 MonoInst *ins = cfg->varinfo [i];
 680                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 681
 682                 /* unused vars */
 683                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 684                         continue;
 685
 686                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 687                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 688                         continue;
 689
 690                 if (mono_is_regsize_var (ins->inst_vtype)) {
 691                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 692                         g_assert (i == vmv->idx);
 693                         vars = g_list_prepend (vars, vmv);
 694                 }
 695         }
 696
 697         vars = mono_varlist_sort (cfg, vars, 0);
 698
 699         return vars;
 700 }
 701
 702 static void
 703 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 704 {
 705         CallInfo *cinfo;
 706         guint32 reserved_regs;
 707         MonoMethodHeader *header;
 708
 709         if (cfg->arch.reg_local0 > 0)
 710                 /* Already done */
 711                 return;
 712
 713         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 714
 715         header = cfg->header;
 716
 717         /* Some registers are reserved for use by the prolog/epilog */
 718         reserved_regs = header->num_clauses ? 4 : 3;
 719
 720         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 721                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 722                 /* One registers is needed by instrument_epilog to save the return value */
 723                 reserved_regs ++;
 724                 if (cinfo->reg_usage < 2)
 725                         /* Number of arguments passed to function call in instrument_prolog */
 726                         cinfo->reg_usage = 2;
 727         }
 728
 729         cfg->arch.reg_in0 = 32;
 730         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 731         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 732
 733         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 734         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 735         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 736
 737         /*
 738          * Frames without handlers save sp to fp, frames with handlers save it into
 739          * a dedicated register.
 740          */
 741         if (header->num_clauses)
 742                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 743         else
 744                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 745
 746         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 747                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 748                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 749         }
 750
 751         /*
 752          * Need to allocate at least 2 out register for use by OP_THROW / the system
 753          * exception throwing code.
 754          */
 755         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 756 }
 757
 758 GList *
 759 mono_arch_get_global_int_regs (MonoCompile *cfg)
 760 {
 761         GList *regs = NULL;
 762         int i;
 763
 764         mono_ia64_alloc_stacked_registers (cfg);
 765
 766         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 767                 /* FIXME: regmask */
 768                 g_assert (i < 64);
 769                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 770         }
 771
 772         return regs;
 773 }
 774
 775 /*
 776  * mono_arch_regalloc_cost:
 777  *
 778  *  Return the cost, in number of memory references, of the action of
 779  * allocating the variable VMV into a register during global register
 780  * allocation.
 781  */
 782 guint32
 783 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 784 {
 785         /* FIXME: Increase costs linearly to avoid using all local registers */
 786
 787         return 0;
 788 }
 789
 790 void
 791 mono_arch_allocate_vars (MonoCompile *cfg)
 792 {
 793         MonoMethodSignature *sig;
 794         MonoMethodHeader *header;
 795         MonoInst *inst;
 796         int i, offset;
 797         guint32 locals_stack_size, locals_stack_align;
 798         gint32 *offsets;
 799         CallInfo *cinfo;
 800
 801         header = cfg->header;
 802
 803         sig = mono_method_signature (cfg->method);
 804
 805         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 806
 807         /*
 808          * Determine whenever the frame pointer can be eliminated.
 809          * FIXME: Remove some of the restrictions.
 810          */
 811         cfg->arch.omit_fp = TRUE;
 812
 813         if (!debug_omit_fp ())
 814                 cfg->arch.omit_fp = FALSE;
 815
 816         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 817                 cfg->arch.omit_fp = FALSE;
 818         if (header->num_clauses)
 819                 cfg->arch.omit_fp = FALSE;
 820         if (cfg->param_area)
 821                 cfg->arch.omit_fp = FALSE;
 822         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 823                 cfg->arch.omit_fp = FALSE;
 824         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 825                 cfg->arch.omit_fp = FALSE;
 826         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 827                 ArgInfo *ainfo = &cinfo->args [i];
 828
 829                 if (ainfo->storage == ArgOnStack) {
 830                         /*
 831                          * The stack offset can only be determined when the frame
 832                          * size is known.
 833                          */
 834                         cfg->arch.omit_fp = FALSE;
 835                 }
 836         }
 837
 838         mono_ia64_alloc_stacked_registers (cfg);
 839
 840         /*
 841          * We use the ABI calling conventions for managed code as well.
 842          * Exception: valuetypes are never passed or returned in registers.
 843          */
 844
 845         if (cfg->arch.omit_fp) {
 846                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 847                 cfg->frame_reg = IA64_SP;
 848                 offset = ARGS_OFFSET;
 849         }
 850         else {
 851                 /* Locals are allocated backwards from %fp */
 852                 cfg->frame_reg = cfg->arch.reg_fp;
 853                 offset = 0;
 854         }
 855
 856         if (cfg->method->save_lmf) {
 857                 /* No LMF on IA64 */
 858         }
 859
 860         if (sig->ret->type != MONO_TYPE_VOID) {
 861                 switch (cinfo->ret.storage) {
 862                 case ArgInIReg:
 863                         cfg->ret->opcode = OP_REGVAR;
 864                         cfg->ret->inst_c0 = cinfo->ret.reg;
 865                         break;
 866                 case ArgInFloatReg:
 867                         cfg->ret->opcode = OP_REGVAR;
 868                         cfg->ret->inst_c0 = cinfo->ret.reg;
 869                         break;
 870                 case ArgValuetypeAddrInIReg:
 871                         cfg->vret_addr->opcode = OP_REGVAR;
 872                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 873                         break;
 874                 case ArgAggregate:
 875                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 876                         if (cfg->arch.omit_fp)
 877                                 g_assert_not_reached ();
 878                         offset = ALIGN_TO (offset, 8);
 879                         offset += cinfo->ret.nslots * 8;
 880                         cfg->ret->opcode = OP_REGOFFSET;
 881                         cfg->ret->inst_basereg = cfg->frame_reg;
 882                         cfg->ret->inst_offset = - offset;
 883                         break;
 884                 default:
 885                         g_assert_not_reached ();
 886                 }
 887                 cfg->ret->dreg = cfg->ret->inst_c0;
 888         }
 889
 890         /* Allocate locals */
 891         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 892         if (locals_stack_align) {
 893                 offset = ALIGN_TO (offset, locals_stack_align);
 894         }
 895         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 896                 if (offsets [i] != -1) {
 897                         MonoInst *inst = cfg->varinfo [i];
 898                         inst->opcode = OP_REGOFFSET;
 899                         inst->inst_basereg = cfg->frame_reg;
 900                         if (cfg->arch.omit_fp)
 901                                 inst->inst_offset = (offset + offsets [i]);
 902                         else
 903                                 inst->inst_offset = - (offset + offsets [i]);
 904                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 905                 }
 906         }
 907         offset += locals_stack_size;
 908
 909         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 910                 if (cfg->arch.omit_fp)
 911                         g_assert_not_reached ();
 912                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 913                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 914         }
 915
 916         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 917                 inst = cfg->args [i];
 918                 if (inst->opcode != OP_REGVAR) {
 919                         ArgInfo *ainfo = &cinfo->args [i];
 920                         gboolean inreg = TRUE;
 921                         MonoType *arg_type;
 922
 923                         if (sig->hasthis && (i == 0))
 924                                 arg_type = &mono_defaults.object_class->byval_arg;
 925                         else
 926                                 arg_type = sig->params [i - sig->hasthis];
 927
 928                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 929                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 930                                 inreg = FALSE;
 931
 932                         inst->opcode = OP_REGOFFSET;
 933
 934                         switch (ainfo->storage) {
 935                         case ArgInIReg:
 936                                 inst->opcode = OP_REGVAR;
 937                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 938                                 break;
 939                         case ArgInFloatReg:
 940                         case ArgInFloatRegR4:
 941                                 /*
 942                                  * Since float regs are volatile, we save the arguments to
 943                                  * the stack in the prolog.
 944                                  */
 945                                 inreg = FALSE;
 946                                 break;
 947                         case ArgOnStack:
 948                                 if (cfg->arch.omit_fp)
 949                                         g_assert_not_reached ();
 950                                 inst->opcode = OP_REGOFFSET;
 951                                 inst->inst_basereg = cfg->frame_reg;
 952                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 953                                 break;
 954                         case ArgAggregate:
 955                                 inreg = FALSE;
 956                                 break;
 957                         default:
 958                                 NOT_IMPLEMENTED;
 959                         }
 960
 961                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 962                                 guint32 size = 0;
 963
 964                                 inst->opcode = OP_REGOFFSET;
 965                                 inst->inst_basereg = cfg->frame_reg;
 966                                 /* These arguments are saved to the stack in the prolog */
 967                                 switch (ainfo->storage) {
 968                                 case ArgAggregate:
 969                                         if (ainfo->atype == AggregateSingleHFA)
 970                                                 size = ainfo->nslots * 4;
 971                                         else
 972                                                 size = ainfo->nslots * 8;
 973                                         break;
 974                                 default:
 975                                         size = sizeof (gpointer);
 976                                         break;
 977                                 }
 978
 979                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 980
 981                                 if (cfg->arch.omit_fp) {
 982                                         inst->inst_offset = offset;
 983                                         offset += size;
 984                                 } else {
 985                                         offset += size;
 986                                         inst->inst_offset = - offset;
 987                                 }
 988                         }
 989                 }
 990         }
 991
 992         /*
 993          * FIXME: This doesn't work because some variables are allocated during local
 994          * regalloc.
 995          */
 996         /*
 997         if (cfg->arch.omit_fp && offset == 16)
 998                 offset = 0;
 999         */
1000
1001         cfg->stack_offset = offset;
1002 }
1003
1004 void
1005 mono_arch_create_vars (MonoCompile *cfg)
1006 {
1007         MonoMethodSignature *sig;
1008         CallInfo *cinfo;
1009
1010         sig = mono_method_signature (cfg->method);
1011
1012         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1013
1014         if (cinfo->ret.storage == ArgAggregate)
1015                 cfg->ret_var_is_local = TRUE;
1016         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1017                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1018                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1019                         printf ("vret_addr = ");
1020                         mono_print_ins (cfg->vret_addr);
1021                 }
1022         }
1023 }
1024
1025 static void
1026 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1027 {
1028         MonoInst *arg;
1029
1030         MONO_INST_NEW (cfg, arg, OP_NOP);
1031         arg->sreg1 = tree->dreg;
1032
1033         switch (storage) {
1034         case ArgInIReg:
1035                 arg->opcode = OP_MOVE;
1036                 arg->dreg = mono_alloc_ireg (cfg);
1037
1038                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1039                 break;
1040         case ArgInFloatReg:
1041                 arg->opcode = OP_FMOVE;
1042                 arg->dreg = mono_alloc_freg (cfg);
1043
1044                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1045                 break;
1046         case ArgInFloatRegR4:
1047                 arg->opcode = OP_FCONV_TO_R4;
1048                 arg->dreg = mono_alloc_freg (cfg);
1049
1050                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1051                 break;
1052         default:
1053                 g_assert_not_reached ();
1054         }
1055
1056         MONO_ADD_INS (cfg->cbb, arg);
1057 }
1058
1059 static void
1060 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1061 {
1062         MonoMethodSignature *tmp_sig;
1063
1064         /* Emit the signature cookie just before the implicit arguments */
1065         MonoInst *sig_arg;
1066         /* FIXME: Add support for signature tokens to AOT */
1067         cfg->disable_aot = TRUE;
1068
1069         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1070
1071         /*
1072          * mono_ArgIterator_Setup assumes the signature cookie is
1073          * passed first and all the arguments which were before it are
1074          * passed on the stack after the signature. So compensate by
1075          * passing a different signature.
1076          */
1077         tmp_sig = mono_metadata_signature_dup (call->signature);
1078         tmp_sig->param_count -= call->signature->sentinelpos;
1079         tmp_sig->sentinelpos = 0;
1080         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1081
1082         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1083         sig_arg->dreg = mono_alloc_ireg (cfg);
1084         sig_arg->inst_p0 = tmp_sig;
1085         MONO_ADD_INS (cfg->cbb, sig_arg);
1086
1087         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1088 }
1089
1090 void
1091 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1092 {
1093         MonoInst *in;
1094         MonoMethodSignature *sig;
1095         int i, n, stack_size;
1096         CallInfo *cinfo;
1097         ArgInfo *ainfo;
1098
1099         stack_size = 0;
1100
1101         mono_ia64_alloc_stacked_registers (cfg);
1102
1103         sig = call->signature;
1104         n = sig->param_count + sig->hasthis;
1105
1106         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1107
1108         if (cinfo->ret.storage == ArgAggregate) {
1109                 MonoInst *vtarg;
1110                 MonoInst *local;
1111
1112                 /*
1113                  * The valuetype is in registers after the call, need to be copied
1114                  * to the stack. Save the address to a local here, so the call
1115                  * instruction can access it.
1116                  */
1117                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1118                 local->flags |= MONO_INST_VOLATILE;
1119                 cfg->arch.ret_var_addr_local = local;
1120
1121                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1122                 vtarg->sreg1 = call->vret_var->dreg;
1123                 vtarg->dreg = local->dreg;
1124                 MONO_ADD_INS (cfg->cbb, vtarg);
1125         }
1126
1127         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1128                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1129         }
1130
1131         for (i = 0; i < n; ++i) {
1132                 MonoType *arg_type;
1133
1134                 ainfo = cinfo->args + i;
1135
1136                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1137                         /* Emit the signature cookie just before the implicit arguments */
1138                         emit_sig_cookie (cfg, call, cinfo);
1139                 }
1140
1141                 in = call->args [i];
1142
1143                 if (sig->hasthis && (i == 0))
1144                         arg_type = &mono_defaults.object_class->byval_arg;
1145                 else
1146                         arg_type = sig->params [i - sig->hasthis];
1147
1148                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1149                         guint32 align;
1150                         guint32 size;
1151
1152                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1153                                 size = sizeof (MonoTypedRef);
1154                                 align = sizeof (gpointer);
1155                         }
1156                         else if (sig->pinvoke)
1157                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1158                         else {
1159                                 /*
1160                                  * Other backends use mono_type_stack_size (), but that
1161                                  * aligns the size to 8, which is larger than the size of
1162                                  * the source, leading to reads of invalid memory if the
1163                                  * source is at the end of address space.
1164                                  */
1165                                 size = mono_class_value_size (in->klass, &align);
1166                         }
1167
1168                         if (size > 0) {
1169                                 MonoInst *arg;
1170
1171                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1172                                 arg->sreg1 = in->dreg;
1173                                 arg->klass = in->klass;
1174                                 arg->backend.size = size;
1175                                 arg->inst_p0 = call;
1176                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1177                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1178
1179                                 MONO_ADD_INS (cfg->cbb, arg);
1180                         }
1181                 }
1182                 else {
1183                         switch (ainfo->storage) {
1184                         case ArgInIReg:
1185                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1186                                 break;
1187                         case ArgInFloatReg:
1188                         case ArgInFloatRegR4:
1189                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1190                                 break;
1191                         case ArgOnStack:
1192                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1193                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1194                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1195                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1196                                 else
1197                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1198                                 break;
1199                         default:
1200                                 g_assert_not_reached ();
1201                         }
1202                 }
1203         }
1204
1205         /* Handle the case where there are no implicit arguments */
1206         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1207                 emit_sig_cookie (cfg, call, cinfo);
1208         }
1209
1210         call->stack_usage = cinfo->stack_usage;
1211         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1212 }
1213
1214 void
1215 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1216 {
1217         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1218         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1219         int size = ins->backend.size;
1220
1221         if (ainfo->storage == ArgAggregate) {
1222                 MonoInst *load, *store;
1223                 int i, slot;
1224
1225                 /*
1226                  * Part of the structure is passed in registers.
1227                  */
1228                 for (i = 0; i < ainfo->nregs; ++i) {
1229                         slot = ainfo->reg + i;
1230
1231                         if (ainfo->atype == AggregateSingleHFA) {
1232                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1233                                 load->inst_basereg = src->dreg;
1234                                 load->inst_offset = i * 4;
1235                                 load->dreg = mono_alloc_freg (cfg);
1236
1237                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1238                         } else if (ainfo->atype == AggregateDoubleHFA) {
1239                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1240                                 load->inst_basereg = src->dreg;
1241                                 load->inst_offset = i * 8;
1242                                 load->dreg = mono_alloc_freg (cfg);
1243
1244                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1245                         } else {
1246                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1247                                 load->inst_basereg = src->dreg;
1248                                 load->inst_offset = i * 8;
1249                                 load->dreg = mono_alloc_ireg (cfg);
1250
1251                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1252                         }
1253                         MONO_ADD_INS (cfg->cbb, load);
1254                 }
1255
1256                 /*
1257                  * Part of the structure is passed on the stack.
1258                  */
1259                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1260                         slot = ainfo->reg + i;
1261
1262                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1263                         load->inst_basereg = src->dreg;
1264                         load->inst_offset = i * sizeof (gpointer);
1265                         load->dreg = mono_alloc_preg (cfg);
1266                         MONO_ADD_INS (cfg->cbb, load);
1267
1268                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1269                         store->sreg1 = load->dreg;
1270                         store->inst_destbasereg = IA64_SP;
1271                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1272                         MONO_ADD_INS (cfg->cbb, store);
1273                 }
1274         } else {
1275                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1276         }
1277 }
1278
1279 void
1280 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1281 {
1282         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1283
1284         switch (cinfo->ret.storage) {
1285         case ArgInIReg:
1286                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1287                 break;
1288         case ArgInFloatReg:
1289                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1290                 break;
1291         default:
1292                 g_assert_not_reached ();
1293         }
1294 }
1295
1296 void
1297 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1298 {
1299 }
1300
1301 void
1302 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1303 {
1304         MonoInst *ins, *n, *last_ins = NULL;
1305         ins = bb->code;
1306
1307         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1308                 switch (ins->opcode) {
1309                 case OP_MOVE:
1310                 case OP_FMOVE:
1311                         /*
1312                          * Removes:
1313                          *
1314                          * OP_MOVE reg, reg
1315                          */
1316                         if (ins->dreg == ins->sreg1) {
1317                                 MONO_DELETE_INS (bb, ins);
1318                                 continue;
1319                         }
1320                         /*
1321                          * Removes:
1322                          *
1323                          * OP_MOVE sreg, dreg
1324                          * OP_MOVE dreg, sreg
1325                          */
1326                         if (last_ins && last_ins->opcode == OP_MOVE &&
1327                             ins->sreg1 == last_ins->dreg &&
1328                             ins->dreg == last_ins->sreg1) {
1329                                 MONO_DELETE_INS (bb, ins);
1330                                 continue;
1331                         }
1332                         break;
1333                 case OP_MUL_IMM:
1334                 case OP_IMUL_IMM:
1335                         /* remove unnecessary multiplication with 1 */
1336                         if (ins->inst_imm == 1) {
1337                                 if (ins->dreg != ins->sreg1) {
1338                                         ins->opcode = OP_MOVE;
1339                                 } else {
1340                                         MONO_DELETE_INS (bb, ins);
1341                                         continue;
1342                                 }
1343                         }
1344                         break;
1345                 }
1346
1347                 last_ins = ins;
1348                 ins = ins->next;
1349         }
1350         bb->last_ins = last_ins;
1351 }
1352
1353 int cond_to_ia64_cmp [][3] = {
1354         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1355         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1356         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1357         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1358         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1359         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1360         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1361         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1362         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1363         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1364 };
1365
1366 static int
1367 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1368 {
1369         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1370 }
1371
1372 int cond_to_ia64_cmp_imm [][3] = {
1373         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1374         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1375         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1376         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1377         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1378         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1379         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1380         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1381         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1382         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1383 };
1384
1385 static int
1386 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1387 {
1388         /* The condition needs to be reversed */
1389         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1390 }
1391
1392 #define NEW_INS(cfg,dest,op) do {       \
1393                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1394                 (dest)->opcode = (op);  \
1395         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1396         last_ins = (dest); \
1397         } while (0)
1398
1399 /*
1400  * mono_arch_lowering_pass:
1401  *
1402  *  Converts complex opcodes into simpler ones so that each IR instruction
1403  * corresponds to one machine instruction.
1404  */
1405 void
1406 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1407 {
1408         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1409         ins = bb->code;
1410
1411         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1412                 switch (ins->opcode) {
1413                 case OP_STOREI1_MEMBASE_IMM:
1414                 case OP_STOREI2_MEMBASE_IMM:
1415                 case OP_STOREI4_MEMBASE_IMM:
1416                 case OP_STOREI8_MEMBASE_IMM:
1417                 case OP_STORE_MEMBASE_IMM:
1418                         /* There are no store_membase instructions on ia64 */
1419                         if (ins->inst_offset == 0) {
1420                                 temp2 = NULL;
1421                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1422                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1423                                 temp2->sreg1 = ins->inst_destbasereg;
1424                                 temp2->inst_imm = ins->inst_offset;
1425                                 temp2->dreg = mono_alloc_ireg (cfg);
1426                         }
1427                         else {
1428                                 NEW_INS (cfg, temp, OP_I8CONST);
1429                                 temp->inst_c0 = ins->inst_offset;
1430                                 temp->dreg = mono_alloc_ireg (cfg);
1431
1432                                 NEW_INS (cfg, temp2, OP_LADD);
1433                                 temp2->sreg1 = ins->inst_destbasereg;
1434                                 temp2->sreg2 = temp->dreg;
1435                                 temp2->dreg = mono_alloc_ireg (cfg);
1436                         }
1437
1438                         switch (ins->opcode) {
1439                         case OP_STOREI1_MEMBASE_IMM:
1440                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1441                                 break;
1442                         case OP_STOREI2_MEMBASE_IMM:
1443                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1444                                 break;
1445                         case OP_STOREI4_MEMBASE_IMM:
1446                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1447                                 break;
1448                         case OP_STOREI8_MEMBASE_IMM:
1449                         case OP_STORE_MEMBASE_IMM:
1450                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1451                                 break;
1452                         default:
1453                                 g_assert_not_reached ();
1454                         }
1455
1456                         if (ins->inst_imm == 0)
1457                                 ins->sreg1 = IA64_R0;
1458                         else {
1459                                 NEW_INS (cfg, temp3, OP_I8CONST);
1460                                 temp3->inst_c0 = ins->inst_imm;
1461                                 temp3->dreg = mono_alloc_ireg (cfg);
1462                                 ins->sreg1 = temp3->dreg;
1463                         }
1464
1465                         ins->inst_offset = 0;
1466                         if (temp2)
1467                                 ins->inst_destbasereg = temp2->dreg;
1468                         break;
1469                 case OP_STOREI1_MEMBASE_REG:
1470                 case OP_STOREI2_MEMBASE_REG:
1471                 case OP_STOREI4_MEMBASE_REG:
1472                 case OP_STOREI8_MEMBASE_REG:
1473                 case OP_STORER4_MEMBASE_REG:
1474                 case OP_STORER8_MEMBASE_REG:
1475                 case OP_STORE_MEMBASE_REG:
1476                         /* There are no store_membase instructions on ia64 */
1477                         if (ins->inst_offset == 0) {
1478                                 break;
1479                         }
1480                         else if (ia64_is_imm14 (ins->inst_offset)) {
1481                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1482                                 temp2->sreg1 = ins->inst_destbasereg;
1483                                 temp2->inst_imm = ins->inst_offset;
1484                                 temp2->dreg = mono_alloc_ireg (cfg);
1485                         }
1486                         else {
1487                                 NEW_INS (cfg, temp, OP_I8CONST);
1488                                 temp->inst_c0 = ins->inst_offset;
1489                                 temp->dreg = mono_alloc_ireg (cfg);
1490                                 NEW_INS (cfg, temp2, OP_LADD);
1491                                 temp2->sreg1 = ins->inst_destbasereg;
1492                                 temp2->sreg2 = temp->dreg;
1493                                 temp2->dreg = mono_alloc_ireg (cfg);
1494                         }
1495
1496                         ins->inst_offset = 0;
1497                         ins->inst_destbasereg = temp2->dreg;
1498                         break;
1499                 case OP_LOADI1_MEMBASE:
1500                 case OP_LOADU1_MEMBASE:
1501                 case OP_LOADI2_MEMBASE:
1502                 case OP_LOADU2_MEMBASE:
1503                 case OP_LOADI4_MEMBASE:
1504                 case OP_LOADU4_MEMBASE:
1505                 case OP_LOADI8_MEMBASE:
1506                 case OP_LOAD_MEMBASE:
1507                 case OP_LOADR4_MEMBASE:
1508                 case OP_LOADR8_MEMBASE:
1509                 case OP_ATOMIC_EXCHANGE_I4:
1510                 case OP_ATOMIC_EXCHANGE_I8:
1511                 case OP_ATOMIC_ADD_NEW_I4:
1512                 case OP_ATOMIC_ADD_NEW_I8:
1513                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1514                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1515                         /* There are no membase instructions on ia64 */
1516                         if (ins->inst_offset == 0) {
1517                                 break;
1518                         }
1519                         else if (ia64_is_imm14 (ins->inst_offset)) {
1520                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1521                                 temp2->sreg1 = ins->inst_basereg;
1522                                 temp2->inst_imm = ins->inst_offset;
1523                                 temp2->dreg = mono_alloc_ireg (cfg);
1524                         }
1525                         else {
1526                                 NEW_INS (cfg, temp, OP_I8CONST);
1527                                 temp->inst_c0 = ins->inst_offset;
1528                                 temp->dreg = mono_alloc_ireg (cfg);
1529                                 NEW_INS (cfg, temp2, OP_LADD);
1530                                 temp2->sreg1 = ins->inst_basereg;
1531                                 temp2->sreg2 = temp->dreg;
1532                                 temp2->dreg = mono_alloc_ireg (cfg);
1533                         }
1534
1535                         ins->inst_offset = 0;
1536                         ins->inst_basereg = temp2->dreg;
1537                         break;
1538                 case OP_ADD_IMM:
1539                 case OP_IADD_IMM:
1540                 case OP_LADD_IMM:
1541                 case OP_ISUB_IMM:
1542                 case OP_LSUB_IMM:
1543                 case OP_AND_IMM:
1544                 case OP_IAND_IMM:
1545                 case OP_LAND_IMM:
1546                 case OP_IOR_IMM:
1547                 case OP_LOR_IMM:
1548                 case OP_IXOR_IMM:
1549                 case OP_LXOR_IMM:
1550                 case OP_SHL_IMM:
1551                 case OP_SHR_IMM:
1552                 case OP_ISHL_IMM:
1553                 case OP_LSHL_IMM:
1554                 case OP_ISHR_IMM:
1555                 case OP_LSHR_IMM:
1556                 case OP_ISHR_UN_IMM:
1557                 case OP_LSHR_UN_IMM: {
1558                         gboolean is_imm = FALSE;
1559                         gboolean switched = FALSE;
1560
1561                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1562                                 ins->opcode = OP_ZEXT_I1;
1563                                 break;
1564                         }
1565
1566                         switch (ins->opcode) {
1567                         case OP_ADD_IMM:
1568                         case OP_IADD_IMM:
1569                         case OP_LADD_IMM:
1570                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1571                                 switched = TRUE;
1572                                 break;
1573                         case OP_ISUB_IMM:
1574                         case OP_LSUB_IMM:
1575                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1576                                 if (is_imm) {
1577                                         /* A = B - IMM -> A = B + (-IMM) */
1578                                         ins->inst_imm = - ins->inst_imm;
1579                                         ins->opcode = OP_IADD_IMM;
1580                                 }
1581                                 switched = TRUE;
1582                                 break;
1583                         case OP_IAND_IMM:
1584                         case OP_IOR_IMM:
1585                         case OP_IXOR_IMM:
1586                         case OP_AND_IMM:
1587                         case OP_LAND_IMM:
1588                         case OP_LOR_IMM:
1589                         case OP_LXOR_IMM:
1590                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1591                                 switched = TRUE;
1592                                 break;
1593                         case OP_SHL_IMM:
1594                         case OP_SHR_IMM:
1595                         case OP_ISHL_IMM:
1596                         case OP_LSHL_IMM:
1597                         case OP_ISHR_IMM:
1598                         case OP_LSHR_IMM:
1599                         case OP_ISHR_UN_IMM:
1600                         case OP_LSHR_UN_IMM:
1601                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1602                                 break;
1603                         default:
1604                                 break;
1605                         }
1606
1607                         if (is_imm) {
1608                                 if (switched)
1609                                         ins->sreg2 = ins->sreg1;
1610                                 break;
1611                         }
1612
1613                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1614
1615                         if (ins->inst_imm == 0)
1616                                 ins->sreg2 = IA64_R0;
1617                         else {
1618                                 NEW_INS (cfg, temp, OP_I8CONST);
1619                                 temp->inst_c0 = ins->inst_imm;
1620                                 temp->dreg = mono_alloc_ireg (cfg);
1621                                 ins->sreg2 = temp->dreg;
1622                         }
1623                         break;
1624                 }
1625                 case OP_COMPARE_IMM:
1626                 case OP_ICOMPARE_IMM:
1627                 case OP_LCOMPARE_IMM: {
1628                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1629                         gboolean imm;
1630                         CompRelation cond;
1631
1632                         next = ins->next;
1633
1634                         /* Branch opts can eliminate the branch */
1635                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1636                                 NULLIFY_INS (ins);
1637                                 break;
1638                         }
1639
1640                         /*
1641                          * The compare_imm instructions have switched up arguments, and
1642                          * some of them take an imm between -127 and 128.
1643                          */
1644                         next = ins->next;
1645                         cond = mono_opcode_to_cond (next->opcode);
1646                         if ((cond == CMP_LT) || (cond == CMP_GE))
1647                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1648                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1649                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1650                         else
1651                                 imm = ia64_is_imm8 (ins->inst_imm);
1652
1653                         if (imm) {
1654                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1655                                 ins->sreg2 = ins->sreg1;
1656                         }
1657                         else {
1658                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1659
1660                                 if (ins->inst_imm == 0)
1661                                         ins->sreg2 = IA64_R0;
1662                                 else {
1663                                         NEW_INS (cfg, temp, OP_I8CONST);
1664                                         temp->inst_c0 = ins->inst_imm;
1665                                         temp->dreg = mono_alloc_ireg (cfg);
1666                                         ins->sreg2 = temp->dreg;
1667                                 }
1668                         }
1669
1670                         if (MONO_IS_COND_BRANCH_OP (next)) {
1671                                 next->opcode = OP_IA64_BR_COND;
1672                                 next->inst_target_bb = next->inst_true_bb;
1673                         } else if (MONO_IS_COND_EXC (next)) {
1674                                 next->opcode = OP_IA64_COND_EXC;
1675                         } else if (MONO_IS_SETCC (next)) {
1676                                 next->opcode = OP_IA64_CSET;
1677                         } else {
1678                                 printf ("%s\n", mono_inst_name (next->opcode));
1679                                 NOT_IMPLEMENTED;
1680                         }
1681
1682                         break;
1683                 }
1684                 case OP_COMPARE:
1685                 case OP_ICOMPARE:
1686                 case OP_LCOMPARE:
1687                 case OP_FCOMPARE: {
1688                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1689
1690                         next = ins->next;
1691
1692                         /* Branch opts can eliminate the branch */
1693                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1694                                 NULLIFY_INS (ins);
1695                                 break;
1696                         }
1697
1698                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1699
1700                         if (MONO_IS_COND_BRANCH_OP (next)) {
1701                                 next->opcode = OP_IA64_BR_COND;
1702                                 next->inst_target_bb = next->inst_true_bb;
1703                         } else if (MONO_IS_COND_EXC (next)) {
1704                                 next->opcode = OP_IA64_COND_EXC;
1705                         } else if (MONO_IS_SETCC (next)) {
1706                                 next->opcode = OP_IA64_CSET;
1707                         } else {
1708                                 printf ("%s\n", mono_inst_name (next->opcode));
1709                                 NOT_IMPLEMENTED;
1710                         }
1711
1712                         break;
1713                 }
1714                 case OP_FCEQ:
1715                 case OP_FCGT:
1716                 case OP_FCGT_UN:
1717                 case OP_FCLT:
1718                 case OP_FCLT_UN:
1719                         /* The front end removes the fcompare, so introduce it again */
1720                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1721                         temp->sreg1 = ins->sreg1;
1722                         temp->sreg2 = ins->sreg2;
1723
1724                         ins->opcode = OP_IA64_CSET;
1725                         MONO_INST_NULLIFY_SREGS (ins);
1726                         break;
1727                 case OP_MUL_IMM:
1728                 case OP_LMUL_IMM:
1729                 case OP_IMUL_IMM: {
1730                         int i, sum_reg;
1731                         gboolean found = FALSE;
1732                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1733
1734                         /* First the easy cases */
1735                         if (ins->inst_imm == 1) {
1736                                 ins->opcode = OP_MOVE;
1737                                 break;
1738                         }
1739                         for (i = 1; i < 64; ++i)
1740                                 if (ins->inst_imm == (((gint64)1) << i)) {
1741                                         ins->opcode = shl_op;
1742                                         ins->inst_imm = i;
1743                                         found = TRUE;
1744                                         break;
1745                                 }
1746
1747                         /* This could be optimized */
1748                         if (!found) {
1749                                 sum_reg = 0;
1750                                 for (i = 0; i < 64; ++i) {
1751                                         if (ins->inst_imm & (((gint64)1) << i)) {
1752                                                 NEW_INS (cfg, temp, shl_op);
1753                                                 temp->dreg = mono_alloc_ireg (cfg);
1754                                                 temp->sreg1 = ins->sreg1;
1755                                                 temp->inst_imm = i;
1756
1757                                                 if (sum_reg == 0)
1758                                                         sum_reg = temp->dreg;
1759                                                 else {
1760                                                         NEW_INS (cfg, temp2, OP_LADD);
1761                                                         temp2->dreg = mono_alloc_ireg (cfg);
1762                                                         temp2->sreg1 = sum_reg;
1763                                                         temp2->sreg2 = temp->dreg;
1764                                                         sum_reg = temp2->dreg;
1765                                                 }
1766                                         }
1767                                 }
1768                                 ins->opcode = OP_MOVE;
1769                                 ins->sreg1 = sum_reg;
1770                         }
1771                         break;
1772                 }
1773                 case OP_LCONV_TO_OVF_U4:
1774                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1775                         temp->sreg1 = ins->sreg1;
1776                         temp->sreg2 = IA64_R0;
1777
1778                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1779                         temp->inst_p1 = (char*)"OverflowException";
1780
1781                         ins->opcode = OP_MOVE;
1782                         break;
1783                 case OP_LCONV_TO_OVF_I4_UN:
1784                         NEW_INS (cfg, temp, OP_ICONST);
1785                         temp->inst_c0 = 0x7fffffff;
1786                         temp->dreg = mono_alloc_ireg (cfg);
1787
1788                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1789                         temp2->sreg1 = ins->sreg1;
1790                         temp2->sreg2 = temp->dreg;
1791
1792                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1793                         temp->inst_p1 = (char*)"OverflowException";
1794
1795                         ins->opcode = OP_MOVE;
1796                         break;
1797                 case OP_FCONV_TO_I4:
1798                 case OP_FCONV_TO_I2:
1799                 case OP_FCONV_TO_U2:
1800                 case OP_FCONV_TO_I1:
1801                 case OP_FCONV_TO_U1:
1802                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1803                         temp->sreg1 = ins->sreg1;
1804                         temp->dreg = ins->dreg;
1805
1806                         switch (ins->opcode) {
1807                         case OP_FCONV_TO_I4:
1808                                 ins->opcode = OP_SEXT_I4;
1809                                 break;
1810                         case OP_FCONV_TO_I2:
1811                                 ins->opcode = OP_SEXT_I2;
1812                                 break;
1813                         case OP_FCONV_TO_U2:
1814                                 ins->opcode = OP_ZEXT_I4;
1815                                 break;
1816                         case OP_FCONV_TO_I1:
1817                                 ins->opcode = OP_SEXT_I1;
1818                                 break;
1819                         case OP_FCONV_TO_U1:
1820                                 ins->opcode = OP_ZEXT_I1;
1821                                 break;
1822                         default:
1823                                 g_assert_not_reached ();
1824                         }
1825                         ins->sreg1 = ins->dreg;
1826                         break;
1827                 default:
1828                         break;
1829                 }
1830                 last_ins = ins;
1831                 ins = ins->next;
1832         }
1833         bb->last_ins = last_ins;
1834
1835         bb->max_vreg = cfg->next_vreg;
1836 }
1837
1838 /*
1839  * emit_load_volatile_arguments:
1840  *
1841  *  Load volatile arguments from the stack to the original input registers.
1842  * Required before a tail call.
1843  */
1844 static Ia64CodegenState
1845 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1846 {
1847         MonoMethod *method = cfg->method;
1848         MonoMethodSignature *sig;
1849         MonoInst *ins;
1850         CallInfo *cinfo;
1851         guint32 i;
1852
1853         /* FIXME: Generate intermediate code instead */
1854
1855         sig = mono_method_signature (method);
1856
1857         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1858
1859         /* This is the opposite of the code in emit_prolog */
1860         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1861                 ArgInfo *ainfo = cinfo->args + i;
1862                 gint32 stack_offset;
1863                 MonoType *arg_type;
1864
1865                 ins = cfg->args [i];
1866
1867                 if (sig->hasthis && (i == 0))
1868                         arg_type = &mono_defaults.object_class->byval_arg;
1869                 else
1870                         arg_type = sig->params [i - sig->hasthis];
1871
1872                 arg_type = mono_type_get_underlying_type (arg_type);
1873
1874                 stack_offset = ainfo->offset + ARGS_OFFSET;
1875
1876                 /* Save volatile arguments to the stack */
1877                 if (ins->opcode != OP_REGVAR) {
1878                         switch (ainfo->storage) {
1879                         case ArgInIReg:
1880                         case ArgInFloatReg:
1881                                 /* FIXME: big offsets */
1882                                 g_assert (ins->opcode == OP_REGOFFSET);
1883                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1884                                 if (arg_type->byref)
1885                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1886                                 else {
1887                                         switch (arg_type->type) {
1888                                         case MONO_TYPE_R4:
1889                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1890                                                 break;
1891                                         case MONO_TYPE_R8:
1892                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1893                                                 break;
1894                                         default:
1895                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1896                                                 break;
1897                                         }
1898                                 }
1899                                 break;
1900                         case ArgOnStack:
1901                                 break;
1902                         default:
1903                                 NOT_IMPLEMENTED;
1904                         }
1905                 }
1906
1907                 if (ins->opcode == OP_REGVAR) {
1908                         /* Argument allocated to (non-volatile) register */
1909                         switch (ainfo->storage) {
1910                         case ArgInIReg:
1911                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1912                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1913                                 break;
1914                         case ArgOnStack:
1915                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1916                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1917                                 break;
1918                         default:
1919                                 NOT_IMPLEMENTED;
1920                         }
1921                 }
1922         }
1923
1924         return code;
1925 }
1926
1927 static Ia64CodegenState
1928 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1929 {
1930         CallInfo *cinfo;
1931         int i;
1932
1933         /* Move return value to the target register */
1934         switch (ins->opcode) {
1935         case OP_VOIDCALL:
1936         case OP_VOIDCALL_REG:
1937         case OP_VOIDCALL_MEMBASE:
1938                 break;
1939         case OP_CALL:
1940         case OP_CALL_REG:
1941         case OP_CALL_MEMBASE:
1942         case OP_LCALL:
1943         case OP_LCALL_REG:
1944         case OP_LCALL_MEMBASE:
1945                 g_assert (ins->dreg == IA64_R8);
1946                 break;
1947         case OP_FCALL:
1948         case OP_FCALL_REG:
1949         case OP_FCALL_MEMBASE:
1950                 g_assert (ins->dreg == 8);
1951                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1952                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1953                 break;
1954         case OP_VCALL:
1955         case OP_VCALL_REG:
1956         case OP_VCALL_MEMBASE:
1957         case OP_VCALL2:
1958         case OP_VCALL2_REG:
1959         case OP_VCALL2_MEMBASE: {
1960                 ArgStorage storage;
1961
1962                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1963                 storage = cinfo->ret.storage;
1964
1965                 if (storage == ArgAggregate) {
1966                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1967
1968                         /* Load address of stack space allocated for the return value */
1969                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1970                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1971                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1972
1973                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1974                                 switch (cinfo->ret.atype) {
1975                                 case AggregateNormal:
1976                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1977                                         break;
1978                                 case AggregateSingleHFA:
1979                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1980                                         break;
1981                                 case AggregateDoubleHFA:
1982                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1983                                         break;
1984                                 default:
1985                                         g_assert_not_reached ();
1986                                 }
1987                         }
1988                 }
1989                 break;
1990         }
1991         default:
1992                 g_assert_not_reached ();
1993         }
1994
1995         return code;
1996 }
1997
1998 #define add_patch_info(cfg,code,patch_type,data) do { \
1999         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
2000 } while (0)
2001
2002 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
2003         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2004     if (tins == NULL) \
2005         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
2006     else \
2007                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
2008         ia64_br_cond_pred (code, (predicate), 0); \
2009 } while (0)
2010
2011 static Ia64CodegenState
2012 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
2013 {
2014         add_patch_info (cfg, code, patch_type, data);
2015
2016         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
2017                 /* Indirect call */
2018                 /* mono_arch_patch_callsite will patch this */
2019                 /* mono_arch_nullify_class_init_trampoline will patch this */
2020                 ia64_movl (code, GP_SCRATCH_REG, 0);
2021                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
2022                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2023                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2024                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2025         }
2026         else {
2027                 /* Can't use a direct call since the displacement might be too small */
2028                 /* mono_arch_patch_callsite will patch this */
2029                 ia64_movl (code, GP_SCRATCH_REG, 0);
2030                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2031                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2032         }
2033
2034         return code;
2035 }
2036
2037 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2038
2039 void
2040 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2041 {
2042         MonoInst *ins;
2043         MonoCallInst *call;
2044         guint offset;
2045         Ia64CodegenState code;
2046         guint8 *code_start = cfg->native_code + cfg->code_len;
2047         MonoInst *last_ins = NULL;
2048         guint last_offset = 0;
2049         int max_len, cpos;
2050
2051         if (cfg->opt & MONO_OPT_LOOP) {
2052                 /* FIXME: */
2053         }
2054
2055         if (cfg->verbose_level > 2)
2056                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2057
2058         cpos = bb->max_offset;
2059
2060         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2061                 NOT_IMPLEMENTED;
2062         }
2063
2064         offset = code_start - cfg->native_code;
2065
2066         ia64_codegen_init (code, code_start);
2067
2068 #if 0
2069         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2070                 break_count ();
2071 #endif
2072
2073         MONO_BB_FOR_EACH_INS (bb, ins) {
2074                 offset = code.buf - cfg->native_code;
2075
2076                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2077
2078                 while (offset + max_len + 16 > cfg->code_size) {
2079                         ia64_codegen_close (code);
2080
2081                         offset = code.buf - cfg->native_code;
2082
2083                         cfg->code_size *= 2;
2084                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2085                         code_start = cfg->native_code + offset;
2086                         cfg->stat_code_reallocs++;
2087
2088                         ia64_codegen_init (code, code_start);
2089                 }
2090
2091                 mono_debug_record_line_number (cfg, ins, offset);
2092
2093                 switch (ins->opcode) {
2094                 case OP_ICONST:
2095                 case OP_I8CONST:
2096                         if (ia64_is_imm14 (ins->inst_c0))
2097                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2098                         else
2099                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2100                         break;
2101                 case OP_JUMP_TABLE:
2102                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2103                         ia64_movl (code, ins->dreg, 0);
2104                         break;
2105                 case OP_MOVE:
2106                         ia64_mov (code, ins->dreg, ins->sreg1);
2107                         break;
2108                 case OP_BR:
2109                 case OP_IA64_BR_COND: {
2110                         int pred = 0;
2111                         if (ins->opcode == OP_IA64_BR_COND)
2112                                 pred = 6;
2113                         if (ins->inst_target_bb->native_offset) {
2114                                 guint8 *pos = code.buf + code.nins;
2115
2116                                 ia64_br_cond_pred (code, pred, 0);
2117                                 ia64_begin_bundle (code);
2118                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2119                         } else {
2120                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2121                                 ia64_br_cond_pred (code, pred, 0);
2122                         }
2123                         break;
2124                 }
2125                 case OP_LABEL:
2126                         ia64_begin_bundle (code);
2127                         ins->inst_c0 = code.buf - cfg->native_code;
2128                         break;
2129                 case OP_NOP:
2130                 case OP_RELAXED_NOP:
2131                 case OP_DUMMY_USE:
2132                 case OP_DUMMY_STORE:
2133                 case OP_NOT_REACHED:
2134                 case OP_NOT_NULL:
2135                         break;
2136                 case OP_BR_REG:
2137                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2138                         ia64_br_cond_reg (code, IA64_B6);
2139                         break;
2140                 case OP_IADD:
2141                 case OP_LADD:
2142                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2143                         break;
2144                 case OP_ISUB:
2145                 case OP_LSUB:
2146                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2147                         break;
2148                 case OP_IAND:
2149                 case OP_LAND:
2150                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2151                         break;
2152                 case OP_IOR:
2153                 case OP_LOR:
2154                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2155                         break;
2156                 case OP_IXOR:
2157                 case OP_LXOR:
2158                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2159                         break;
2160                 case OP_INEG:
2161                 case OP_LNEG:
2162                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2163                         break;
2164                 case OP_INOT:
2165                 case OP_LNOT:
2166                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2167                         break;
2168                 case OP_ISHL:
2169                 case OP_LSHL:
2170                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2171                         break;
2172                 case OP_ISHR:
2173                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2174                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2175                         break;
2176                 case OP_LSHR:
2177                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2178                         break;
2179                 case OP_ISHR_UN:
2180                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2181                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2182                         break;
2183                 case OP_LSHR_UN:
2184                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2185                         break;
2186                 case OP_IADDCC:
2187                         /* p6 and p7 is set if there is signed/unsigned overflow */
2188
2189                         /* Set p8-p9 == (sreg2 > 0) */
2190                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2191
2192                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2193
2194                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2195                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2196                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2197                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2198
2199                         /* res <u sreg1 => unsigned overflow */
2200                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2201
2202                         /* FIXME: Predicate this since this is a side effect */
2203                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2204                         break;
2205                 case OP_ISUBCC:
2206                         /* p6 and p7 is set if there is signed/unsigned overflow */
2207
2208                         /* Set p8-p9 == (sreg2 > 0) */
2209                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2210
2211                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2212
2213                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2214                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2215                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2216                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2217
2218                         /* sreg1 <u sreg2 => unsigned overflow */
2219                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2220
2221                         /* FIXME: Predicate this since this is a side effect */
2222                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2223                         break;
2224                 case OP_ADDCC:
2225                         /* Same as OP_IADDCC */
2226                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2227
2228                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2229
2230                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2231                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2232
2233                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2234
2235                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2236                         break;
2237                 case OP_SUBCC:
2238                         /* Same as OP_ISUBCC */
2239
2240                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2241
2242                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2243
2244                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2245                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2246
2247                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2248
2249                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2250                         break;
2251                 case OP_ADD_IMM:
2252                 case OP_IADD_IMM:
2253                 case OP_LADD_IMM:
2254                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2255                         break;
2256                 case OP_IAND_IMM:
2257                 case OP_AND_IMM:
2258                 case OP_LAND_IMM:
2259                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2260                         break;
2261                 case OP_IOR_IMM:
2262                 case OP_LOR_IMM:
2263                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2264                         break;
2265                 case OP_IXOR_IMM:
2266                 case OP_LXOR_IMM:
2267                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2268                         break;
2269                 case OP_SHL_IMM:
2270                 case OP_ISHL_IMM:
2271                 case OP_LSHL_IMM:
2272                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2273                         break;
2274                 case OP_SHR_IMM:
2275                 case OP_LSHR_IMM:
2276                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2277                         break;
2278                 case OP_ISHR_IMM:
2279                         g_assert (ins->inst_imm <= 64);
2280                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2281                         break;
2282                 case OP_ISHR_UN_IMM:
2283                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2284                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2285                         break;
2286                 case OP_LSHR_UN_IMM:
2287                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2288                         break;
2289                 case OP_LMUL:
2290                         /* Based on gcc code */
2291                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2292                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2293                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2294                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2295                         break;
2296
2297                 case OP_STOREI1_MEMBASE_REG:
2298                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2299                         break;
2300                 case OP_STOREI2_MEMBASE_REG:
2301                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2302                         break;
2303                 case OP_STOREI4_MEMBASE_REG:
2304                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2305                         break;
2306                 case OP_STOREI8_MEMBASE_REG:
2307                 case OP_STORE_MEMBASE_REG:
2308                         if (ins->inst_offset != 0) {
2309                                 /* This is generated by local regalloc */
2310                                 if (ia64_is_imm14 (ins->inst_offset)) {
2311                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2312                                 } else {
2313                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2314                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2315                                 }
2316                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2317                         }
2318                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2319                         break;
2320
2321                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2322                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2323                         break;
2324                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2325                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2326                         break;
2327                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2328                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2329                         break;
2330                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2331                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2332                         break;
2333
2334                 case OP_LOADU1_MEMBASE:
2335                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2336                         break;
2337                 case OP_LOADU2_MEMBASE:
2338                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2339                         break;
2340                 case OP_LOADU4_MEMBASE:
2341                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2342                         break;
2343                 case OP_LOADI1_MEMBASE:
2344                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2345                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2346                         break;
2347                 case OP_LOADI2_MEMBASE:
2348                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2349                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2350                         break;
2351                 case OP_LOADI4_MEMBASE:
2352                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2353                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2354                         break;
2355                 case OP_LOAD_MEMBASE:
2356                 case OP_LOADI8_MEMBASE:
2357                         if (ins->inst_offset != 0) {
2358                                 /* This is generated by local regalloc */
2359                                 if (ia64_is_imm14 (ins->inst_offset)) {
2360                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2361                                 } else {
2362                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2363                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2364                                 }
2365                                 ins->inst_basereg = GP_SCRATCH_REG;
2366                         }
2367                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2368                         break;
2369
2370                 case OP_IA64_LOADU1_MEMBASE_INC:
2371                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2372                         break;
2373                 case OP_IA64_LOADU2_MEMBASE_INC:
2374                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2375                         break;
2376                 case OP_IA64_LOADU4_MEMBASE_INC:
2377                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2378                         break;
2379                 case OP_IA64_LOADI8_MEMBASE_INC:
2380                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2381                         break;
2382
2383                 case OP_SEXT_I1:
2384                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2385                         break;
2386                 case OP_SEXT_I2:
2387                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2388                         break;
2389                 case OP_SEXT_I4:
2390                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2391                         break;
2392                 case OP_ZEXT_I1:
2393                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2394                         break;
2395                 case OP_ZEXT_I2:
2396                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2397                         break;
2398                 case OP_ZEXT_I4:
2399                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2400                         break;
2401
2402                         /* Compare opcodes */
2403                 case OP_IA64_CMP4_EQ:
2404                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2405                         break;
2406                 case OP_IA64_CMP4_NE:
2407                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_IA64_CMP4_LE:
2410                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2411                         break;
2412                 case OP_IA64_CMP4_LT:
2413                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2414                         break;
2415                 case OP_IA64_CMP4_GE:
2416                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2417                         break;
2418                 case OP_IA64_CMP4_GT:
2419                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2420                         break;
2421                 case OP_IA64_CMP4_LT_UN:
2422                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2423                         break;
2424                 case OP_IA64_CMP4_LE_UN:
2425                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2426                         break;
2427                 case OP_IA64_CMP4_GT_UN:
2428                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2429                         break;
2430                 case OP_IA64_CMP4_GE_UN:
2431                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2432                         break;
2433                 case OP_IA64_CMP_EQ:
2434                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2435                         break;
2436                 case OP_IA64_CMP_NE:
2437                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2438                         break;
2439                 case OP_IA64_CMP_LE:
2440                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2441                         break;
2442                 case OP_IA64_CMP_LT:
2443                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2444                         break;
2445                 case OP_IA64_CMP_GE:
2446                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2447                         break;
2448                 case OP_IA64_CMP_GT:
2449                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2450                         break;
2451                 case OP_IA64_CMP_GT_UN:
2452                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2453                         break;
2454                 case OP_IA64_CMP_LT_UN:
2455                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2456                         break;
2457                 case OP_IA64_CMP_GE_UN:
2458                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2459                         break;
2460                 case OP_IA64_CMP_LE_UN:
2461                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2462                         break;
2463                 case OP_IA64_CMP4_EQ_IMM:
2464                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2465                         break;
2466                 case OP_IA64_CMP4_NE_IMM:
2467                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2468                         break;
2469                 case OP_IA64_CMP4_LE_IMM:
2470                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2471                         break;
2472                 case OP_IA64_CMP4_LT_IMM:
2473                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2474                         break;
2475                 case OP_IA64_CMP4_GE_IMM:
2476                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2477                         break;
2478                 case OP_IA64_CMP4_GT_IMM:
2479                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2480                         break;
2481                 case OP_IA64_CMP4_LT_UN_IMM:
2482                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2483                         break;
2484                 case OP_IA64_CMP4_LE_UN_IMM:
2485                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2486                         break;
2487                 case OP_IA64_CMP4_GT_UN_IMM:
2488                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2489                         break;
2490                 case OP_IA64_CMP4_GE_UN_IMM:
2491                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2492                         break;
2493                 case OP_IA64_CMP_EQ_IMM:
2494                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2495                         break;
2496                 case OP_IA64_CMP_NE_IMM:
2497                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2498                         break;
2499                 case OP_IA64_CMP_LE_IMM:
2500                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2501                         break;
2502                 case OP_IA64_CMP_LT_IMM:
2503                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2504                         break;
2505                 case OP_IA64_CMP_GE_IMM:
2506                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2507                         break;
2508                 case OP_IA64_CMP_GT_IMM:
2509                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2510                         break;
2511                 case OP_IA64_CMP_GT_UN_IMM:
2512                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2513                         break;
2514                 case OP_IA64_CMP_LT_UN_IMM:
2515                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2516                         break;
2517                 case OP_IA64_CMP_GE_UN_IMM:
2518                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2519                         break;
2520                 case OP_IA64_CMP_LE_UN_IMM:
2521                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2522                         break;
2523                 case OP_IA64_FCMP_EQ:
2524                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2525                         break;
2526                 case OP_IA64_FCMP_NE:
2527                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2528                         break;
2529                 case OP_IA64_FCMP_LT:
2530                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2531                         break;
2532                 case OP_IA64_FCMP_GT:
2533                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2534                         break;
2535                 case OP_IA64_FCMP_LE:
2536                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2537                         break;
2538                 case OP_IA64_FCMP_GE:
2539                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2540                         break;
2541                 case OP_IA64_FCMP_GT_UN:
2542                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2543                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2544                         break;
2545                 case OP_IA64_FCMP_LT_UN:
2546                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2547                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2548                         break;
2549                 case OP_IA64_FCMP_GE_UN:
2550                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2551                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2552                         break;
2553                 case OP_IA64_FCMP_LE_UN:
2554                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2555                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2556                         break;
2557
2558                 case OP_COND_EXC_IOV:
2559                 case OP_COND_EXC_OV:
2560                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2561                         break;
2562                 case OP_COND_EXC_IC:
2563                 case OP_COND_EXC_C:
2564                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2565                         break;
2566                 case OP_IA64_COND_EXC:
2567                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2568                         break;
2569                 case OP_IA64_CSET:
2570                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2571                         ia64_no_stop (code);
2572                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2573                         break;
2574                 case OP_ICONV_TO_I1:
2575                 case OP_LCONV_TO_I1:
2576                         /* FIXME: Is this needed ? */
2577                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2578                         break;
2579                 case OP_ICONV_TO_I2:
2580                 case OP_LCONV_TO_I2:
2581                         /* FIXME: Is this needed ? */
2582                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2583                         break;
2584                 case OP_LCONV_TO_I4:
2585                         /* FIXME: Is this needed ? */
2586                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2587                         break;
2588                 case OP_ICONV_TO_U1:
2589                 case OP_LCONV_TO_U1:
2590                         /* FIXME: Is this needed */
2591                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2592                         break;
2593                 case OP_ICONV_TO_U2:
2594                 case OP_LCONV_TO_U2:
2595                         /* FIXME: Is this needed */
2596                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2597                         break;
2598                 case OP_LCONV_TO_U4:
2599                         /* FIXME: Is this needed */
2600                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2601                         break;
2602                 case OP_ICONV_TO_I8:
2603                 case OP_ICONV_TO_I:
2604                 case OP_LCONV_TO_I8:
2605                 case OP_LCONV_TO_I:
2606                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2607                         break;
2608                 case OP_LCONV_TO_U8:
2609                 case OP_LCONV_TO_U:
2610                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2611                         break;
2612
2613                         /*
2614                          * FLOAT OPCODES
2615                          */
2616                 case OP_R8CONST: {
2617                         double d = *(double *)ins->inst_p0;
2618
2619                         if ((d == 0.0) && (mono_signbit (d) == 0))
2620                                 ia64_fmov (code, ins->dreg, 0);
2621                         else if (d == 1.0)
2622                                 ia64_fmov (code, ins->dreg, 1);
2623                         else {
2624                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2625                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2626                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2627                         }
2628                         break;
2629                 }
2630                 case OP_R4CONST: {
2631                         float f = *(float *)ins->inst_p0;
2632
2633                         if ((f == 0.0) && (mono_signbit (f) == 0))
2634                                 ia64_fmov (code, ins->dreg, 0);
2635                         else if (f == 1.0)
2636                                 ia64_fmov (code, ins->dreg, 1);
2637                         else {
2638                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2639                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2640                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2641                         }
2642                         break;
2643                 }
2644                 case OP_FMOVE:
2645                         ia64_fmov (code, ins->dreg, ins->sreg1);
2646                         break;
2647                 case OP_STORER8_MEMBASE_REG:
2648                         if (ins->inst_offset != 0) {
2649                                 /* This is generated by local regalloc */
2650                                 if (ia64_is_imm14 (ins->inst_offset)) {
2651                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2652                                 } else {
2653                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2654                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2655                                 }
2656                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2657                         }
2658                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2659                         break;
2660                 case OP_STORER4_MEMBASE_REG:
2661                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2662                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2663                         break;
2664                 case OP_LOADR8_MEMBASE:
2665                         if (ins->inst_offset != 0) {
2666                                 /* This is generated by local regalloc */
2667                                 if (ia64_is_imm14 (ins->inst_offset)) {
2668                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2669                                 } else {
2670                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2671                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2672                                 }
2673                                 ins->inst_basereg = GP_SCRATCH_REG;
2674                         }
2675                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2676                         break;
2677                 case OP_LOADR4_MEMBASE:
2678                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2679                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2680                         break;
2681                 case OP_ICONV_TO_R4:
2682                 case OP_LCONV_TO_R4:
2683                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2684                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2685                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2686                         break;
2687                 case OP_ICONV_TO_R8:
2688                 case OP_LCONV_TO_R8:
2689                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2690                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2691                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2692                         break;
2693                 case OP_FCONV_TO_R4:
2694                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2695                         break;
2696                 case OP_FCONV_TO_I8:
2697                 case OP_FCONV_TO_I:
2698                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2699                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2700                         break;
2701                 case OP_FADD:
2702                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2703                         break;
2704                 case OP_FSUB:
2705                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2706                         break;
2707                 case OP_FMUL:
2708                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2709                         break;
2710                 case OP_FNEG:
2711                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2712                         break;
2713                 case OP_CKFINITE:
2714                         /* Quiet NaN */
2715                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2716                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2717                         /* Signaling NaN */
2718                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2719                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2720                         /* Positive infinity */
2721                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2722                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2723                         /* Negative infinity */
2724                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2725                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2726                         break;
2727
2728                 /* Calls */
2729                 case OP_CHECK_THIS:
2730                         /* ensure ins->sreg1 is not NULL */
2731                         /* Can't use ld8 as this could be a vtype address */
2732                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2733                         break;
2734                 case OP_ARGLIST:
2735                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2736                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2737                         break;
2738                 case OP_FCALL:
2739                 case OP_LCALL:
2740                 case OP_VCALL:
2741                 case OP_VCALL2:
2742                 case OP_VOIDCALL:
2743                 case OP_CALL:
2744                         call = (MonoCallInst*)ins;
2745
2746                         if (ins->flags & MONO_INST_HAS_METHOD)
2747                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2748                         else
2749                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2750
2751                         code = emit_move_return_value (cfg, ins, code);
2752                         break;
2753
2754                 case OP_CALL_REG:
2755                 case OP_FCALL_REG:
2756                 case OP_LCALL_REG:
2757                 case OP_VCALL_REG:
2758                 case OP_VCALL2_REG:
2759                 case OP_VOIDCALL_REG: {
2760                         MonoCallInst *call = (MonoCallInst*)ins;
2761                         CallInfo *cinfo;
2762                         int out_reg;
2763
2764                         /*
2765                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2766                          * register.
2767                          */
2768                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2769                         out_reg = cfg->arch.reg_out0;
2770                         ia64_mov (code, IA64_R10, out_reg);
2771
2772                         /* Indirect call */
2773                         ia64_mov (code, IA64_R8, ins->sreg1);
2774                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2775                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2776                         ia64_ld8 (code, IA64_GP, IA64_R8);
2777                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2778
2779                         code = emit_move_return_value (cfg, ins, code);
2780                         break;
2781                 }
2782                 case OP_FCALL_MEMBASE:
2783                 case OP_LCALL_MEMBASE:
2784                 case OP_VCALL_MEMBASE:
2785                 case OP_VCALL2_MEMBASE:
2786                 case OP_VOIDCALL_MEMBASE:
2787                 case OP_CALL_MEMBASE: {
2788                         MonoCallInst *call = (MonoCallInst*)ins;
2789                         CallInfo *cinfo;
2790                         int out_reg;
2791
2792                         ia64_mov (code, IA64_R11, ins->sreg1);
2793                         if (ia64_is_imm14 (ins->inst_offset))
2794                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2795                         else {
2796                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2797                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2798                         }
2799
2800                         if (call->method && ins->inst_offset < 0) {
2801                                 /*
2802                                  * This is a possible IMT call so save the IMT method in a global
2803                                  * register where mono_arch_find_imt_method () and its friends can
2804                                  * access it.
2805                                  */
2806                                 ia64_movl (code, IA64_R9, call->method);
2807                         }
2808
2809                         /*
2810                          * mono_arch_find_this_arg () needs to find the this argument in a global
2811                          * register.
2812                          */
2813                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2814                         out_reg = cfg->arch.reg_out0;
2815                         ia64_mov (code, IA64_R10, out_reg);
2816
2817                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2818
2819                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2820
2821                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2822
2823                         code = emit_move_return_value (cfg, ins, code);
2824                         break;
2825                 }
2826                 case OP_JMP: {
2827                         /*
2828                          * Keep in sync with the code in emit_epilog.
2829                          */
2830
2831                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2832                                 NOT_IMPLEMENTED;
2833
2834                         g_assert (!cfg->method->save_lmf);
2835
2836                         /* Load arguments into their original registers */
2837                         code = emit_load_volatile_arguments (cfg, code);
2838
2839                         if (cfg->arch.stack_alloc_size) {
2840                                 if (cfg->arch.omit_fp) {
2841                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2842                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2843                                         else {
2844                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2845                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2846                                         }
2847                                 }
2848                                 else
2849                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2850                         }
2851                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2852                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2853
2854                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2855                         ia64_movl (code, GP_SCRATCH_REG, 0);
2856                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2857                         ia64_br_cond_reg (code, IA64_B6);
2858
2859                         break;
2860                 }
2861                 case OP_BREAK:
2862                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2863                         break;
2864
2865                 case OP_LOCALLOC: {
2866                         gint32 abi_offset;
2867
2868                         /* FIXME: Sigaltstack support */
2869
2870                         /* keep alignment */
2871                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2872                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2873                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2874
2875                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2876
2877                         ia64_mov (code, ins->dreg, IA64_SP);
2878
2879                         /* An area at sp is reserved by the ABI for parameter passing */
2880                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2881                         if (ia64_is_adds_imm (abi_offset))
2882                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2883                         else {
2884                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2885                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2886                         }
2887
2888                         if (ins->flags & MONO_INST_INIT) {
2889                                 /* Upper limit */
2890                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2891
2892                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2893
2894                                 /* Init loop */
2895                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2896                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2897                                 ia64_br_cond_pred (code, 8, -2);
2898
2899                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2900
2901                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2902                         }
2903
2904                         break;
2905                 }
2906                 case OP_LOCALLOC_IMM: {
2907                         gint32 abi_offset;
2908
2909                         /* FIXME: Sigaltstack support */
2910
2911                         gssize size = ins->inst_imm;
2912                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2913
2914                         if (ia64_is_adds_imm (size))
2915                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2916                         else
2917                                 ia64_movl (code, GP_SCRATCH_REG, size);
2918
2919                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2920                         ia64_mov (code, ins->dreg, IA64_SP);
2921
2922                         /* An area at sp is reserved by the ABI for parameter passing */
2923                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2924                         if (ia64_is_adds_imm (abi_offset))
2925                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2926                         else {
2927                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2928                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2929                         }
2930
2931                         if (ins->flags & MONO_INST_INIT) {
2932                                 /* Upper limit */
2933                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2934
2935                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2936
2937                                 /* Init loop */
2938                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2939                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2940                                 ia64_br_cond_pred (code, 8, -2);
2941
2942                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2943
2944                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2945                         }
2946
2947                         break;
2948                 }
2949                 case OP_TLS_GET:
2950                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2951                         ia64_ld8 (code, ins->dreg, ins->dreg);
2952                         break;
2953
2954                         /* Synchronization */
2955                 case OP_MEMORY_BARRIER:
2956                         ia64_mf (code);
2957                         break;
2958                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2959                         g_assert (ins->inst_offset == 0);
2960                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2961                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2962                         break;
2963                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2964                         g_assert (ins->inst_offset == 0);
2965                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2966                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2967                         break;
2968                 case OP_ATOMIC_EXCHANGE_I4:
2969                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2970                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2971                         break;
2972                 case OP_ATOMIC_EXCHANGE_I8:
2973                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2974                         break;
2975                 case OP_ATOMIC_ADD_NEW_I4: {
2976                         guint8 *label, *buf;
2977
2978                         /* From libatomic_ops */
2979                         ia64_mf (code);
2980
2981                         ia64_begin_bundle (code);
2982                         label = code.buf + code.nins;
2983                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2984                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2985                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2986                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2987                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2988                         buf = code.buf + code.nins;
2989                         ia64_br_cond_pred (code, 7, 0);
2990                         ia64_begin_bundle (code);
2991                         ia64_patch (buf, label);
2992                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2993                         break;
2994                 }
2995                 case OP_ATOMIC_ADD_NEW_I8: {
2996                         guint8 *label, *buf;
2997
2998                         /* From libatomic_ops */
2999                         ia64_mf (code);
3000
3001                         ia64_begin_bundle (code);
3002                         label = code.buf + code.nins;
3003                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
3004                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
3005                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
3006                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
3007                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3008                         buf = code.buf + code.nins;
3009                         ia64_br_cond_pred (code, 7, 0);
3010                         ia64_begin_bundle (code);
3011                         ia64_patch (buf, label);
3012                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
3013                         break;
3014                 }
3015
3016                         /* Exception handling */
3017                 case OP_CALL_HANDLER:
3018                         /*
3019                          * Using a call instruction would mess up the register stack, so
3020                          * save the return address to a register and use a
3021                          * branch.
3022                          */
3023                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3024                         ia64_mov (code, IA64_R15, IA64_R0);
3025                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3026                         /* Add the length of OP_CALL_HANDLER */
3027                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3028                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3029                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3030                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3031                         ia64_br_cond_reg (code, IA64_B6);
3032                         // FIXME:
3033                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3034                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3035                         break;
3036                 case OP_START_HANDLER: {
3037                         /*
3038                          * We receive the return address in GP_SCRATCH_REG.
3039                          */
3040                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3041
3042                         /*
3043                          * R15 determines our caller. It is used since it is writable using
3044                          * libunwind.
3045                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3046                          * R15 != 0 means we are called by call_filter ().
3047                          */
3048                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3049                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3050
3051                         ia64_br_cond_pred (code, 6, 6);
3052
3053                         /*
3054                          * Called by call_filter:
3055                          * Allocate a new stack frame, and set the fp register from the
3056                          * value passed in by the caller.
3057                          * We allocate a similar frame as is done by the prolog, so
3058                          * if an exception is thrown while executing the filter, the
3059                          * unwinder can unwind through the filter frame using the unwind
3060                          * info for the prolog.
3061                          */
3062                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3063                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3064                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3065                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3066                         /* Signal to endfilter that we are called by call_filter */
3067                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3068
3069                         /* Branch target: */
3070                         if (ia64_is_imm14 (spvar->inst_offset))
3071                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3072                         else {
3073                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3074                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3075                         }
3076
3077                         /* Save the return address */
3078                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3079                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3080
3081                         break;
3082                 }
3083                 case OP_ENDFINALLY:
3084                 case OP_ENDFILTER: {
3085                         /* FIXME: Return the value in ENDFILTER */
3086                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3087
3088                         /* Load the return address */
3089                         if (ia64_is_imm14 (spvar->inst_offset)) {
3090                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3091                         } else {
3092                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3093                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3094                         }
3095                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3096
3097                         /* Test caller */
3098                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3099                         ia64_br_cond_pred (code, 7, 4);
3100
3101                         /* Called by call_filter */
3102                         /* Pop frame */
3103                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3104                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3105                         ia64_br_ret_reg (code, IA64_B0);
3106
3107                         /* Called by CALL_HANDLER */
3108                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3109                         ia64_br_cond_reg (code, IA64_B6);
3110                         break;
3111                 }
3112                 case OP_THROW:
3113                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3114                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3115                                                           (gpointer)"mono_arch_throw_exception");
3116
3117                         /*
3118                          * This might be the last instruction in the method, so add a dummy
3119                          * instruction so the unwinder will work.
3120                          */
3121                         ia64_break_i (code, 0);
3122                         break;
3123                 case OP_RETHROW:
3124                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3125                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3126                                                           (gpointer)"mono_arch_rethrow_exception");
3127
3128                         ia64_break_i (code, 0);
3129                         break;
3130
3131                 default:
3132                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3133                         g_assert_not_reached ();
3134                 }
3135
3136                 if ((code.buf - cfg->native_code - offset) > max_len) {
3137                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3138                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3139                         g_assert_not_reached ();
3140                 }
3141
3142                 cpos += max_len;
3143
3144                 last_ins = ins;
3145                 last_offset = offset;
3146         }
3147
3148         ia64_codegen_close (code);
3149
3150         cfg->code_len = code.buf - cfg->native_code;
3151 }
3152
3153 void
3154 mono_arch_register_lowlevel_calls (void)
3155 {
3156 }
3157
3158 static Ia64InsType ins_types_in_template [32][3] = {
3159         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3160         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3161         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3162         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3163         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3164         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3165         {0, 0, 0},
3166         {0, 0, 0},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3168         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3169         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3170         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3171         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3172         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3173         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3174         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3175         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3176         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3177         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3178         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3179         {0, 0, 0},
3180         {0, 0, 0},
3181         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3182         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3183         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3184         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3185         {0, 0, 0},
3186         {0, 0, 0},
3187         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3188         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3189         {0, 0, 0},
3190         {0, 0, 0}
3191 };
3192
3193 static gboolean stops_in_template [32][3] = {
3194         { FALSE, FALSE, FALSE },
3195         { FALSE, FALSE, TRUE },
3196         { FALSE, TRUE, FALSE },
3197         { FALSE, TRUE, TRUE },
3198         { FALSE, FALSE, FALSE },
3199         { FALSE, FALSE, TRUE },
3200         { FALSE, FALSE, FALSE },
3201         { FALSE, FALSE, FALSE },
3202
3203         { FALSE, FALSE, FALSE },
3204         { FALSE, FALSE, TRUE },
3205         { TRUE, FALSE, FALSE },
3206         { TRUE, FALSE, TRUE },
3207         { FALSE, FALSE, FALSE },
3208         { FALSE, FALSE, TRUE },
3209         { FALSE, FALSE, FALSE },
3210         { FALSE, FALSE, TRUE },
3211
3212         { FALSE, FALSE, FALSE },
3213         { FALSE, FALSE, TRUE },
3214         { FALSE, FALSE, FALSE },
3215         { FALSE, FALSE, TRUE },
3216         { FALSE, FALSE, FALSE },
3217         { FALSE, FALSE, FALSE },
3218         { FALSE, FALSE, FALSE },
3219         { FALSE, FALSE, TRUE },
3220
3221         { FALSE, FALSE, FALSE },
3222         { FALSE, FALSE, TRUE },
3223         { FALSE, FALSE, FALSE },
3224         { FALSE, FALSE, FALSE },
3225         { FALSE, FALSE, FALSE },
3226         { FALSE, FALSE, TRUE },
3227         { FALSE, FALSE, FALSE },
3228         { FALSE, FALSE, FALSE }
3229 };
3230
3231 static int last_stop_in_template [32] = {
3232         -1, 2, 1, 2, -1, 2, -1, -1,
3233         -1, 2, 0, 2, -1, 2, -1, 2,
3234         -1, 2, -1, 2, -1, -1, -1, 2,
3235         -1, 2, -1, -1, -1, 2, -1, -1
3236 };
3237
3238 static guint64 nops_for_ins_types [6] = {
3239         IA64_NOP_I,
3240         IA64_NOP_I,
3241         IA64_NOP_M,
3242         IA64_NOP_F,
3243         IA64_NOP_B,
3244         IA64_NOP_X
3245 };
3246
3247 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3248
3249 /*
3250  * Debugging support
3251  */
3252
3253 #if 0
3254 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3255 #else
3256 #define DEBUG_INS_SCHED(a)
3257 #endif
3258
3259 static void
3260 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3261 {
3262         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3263         guint8 *deps = code->dep_info;
3264         gboolean need_stop, no_stop;
3265
3266         for (i = 0; i < code->nins; ++i)
3267                 stops [i] = FALSE;
3268
3269         ins_index = 0;
3270         current_deps_start = 0;
3271         current_ins_start = 0;
3272         deps_start [ins_index] = current_ins_start;
3273         pos = 0;
3274         no_stop = FALSE;
3275         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3276         while (pos < code->dep_info_pos) {
3277                 need_stop = FALSE;
3278                 switch (deps [pos]) {
3279                 case IA64_END_OF_INS:
3280                         ins_index ++;
3281                         current_ins_start = pos + 2;
3282                         deps_start [ins_index] = current_ins_start;
3283                         no_stop = FALSE;
3284                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3285                         break;
3286                 case IA64_NONE:
3287                         break;
3288                 case IA64_READ_GR:
3289                         reg = deps [pos + 1];
3290
3291                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3292                         for (i = current_deps_start; i < current_ins_start; i += 2)
3293                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3294                                         need_stop = TRUE;
3295                         break;
3296                 case IA64_WRITE_GR:
3297                         reg = code->dep_info [pos + 1];
3298
3299                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3300                         for (i = current_deps_start; i < current_ins_start; i += 2)
3301                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3302                                         need_stop = TRUE;
3303                         break;
3304                 case IA64_READ_PR:
3305                         reg = deps [pos + 1];
3306
3307                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3308                         for (i = current_deps_start; i < current_ins_start; i += 2)
3309                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3310                                         need_stop = TRUE;
3311                         break;
3312                 case IA64_READ_PR_BRANCH:
3313                         reg = deps [pos + 1];
3314
3315                         /* Writes to prs by non-float instructions are visible to branches */
3316                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3317                         for (i = current_deps_start; i < current_ins_start; i += 2)
3318                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3319                                         need_stop = TRUE;
3320                         break;
3321                 case IA64_WRITE_PR:
3322                         reg = code->dep_info [pos + 1];
3323
3324                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3325                         for (i = current_deps_start; i < current_ins_start; i += 2)
3326                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3327                                         need_stop = TRUE;
3328                         break;
3329                 case IA64_WRITE_PR_FLOAT:
3330                         reg = code->dep_info [pos + 1];
3331
3332                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3333                         for (i = current_deps_start; i < current_ins_start; i += 2)
3334                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3335                                         need_stop = TRUE;
3336                         break;
3337                 case IA64_READ_BR:
3338                         reg = deps [pos + 1];
3339
3340                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3341                         for (i = current_deps_start; i < current_ins_start; i += 2)
3342                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3343                                         need_stop = TRUE;
3344                         break;
3345                 case IA64_WRITE_BR:
3346                         reg = code->dep_info [pos + 1];
3347
3348                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3349                         for (i = current_deps_start; i < current_ins_start; i += 2)
3350                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3351                                         need_stop = TRUE;
3352                         break;
3353                 case IA64_READ_BR_BRANCH:
3354                         reg = deps [pos + 1];
3355
3356                         /* Writes to brs are visible to branches */
3357                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3358                         break;
3359                 case IA64_READ_FR:
3360                         reg = deps [pos + 1];
3361
3362                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3363                         for (i = current_deps_start; i < current_ins_start; i += 2)
3364                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3365                                         need_stop = TRUE;
3366                         break;
3367                 case IA64_WRITE_FR:
3368                         reg = code->dep_info [pos + 1];
3369
3370                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3371                         for (i = current_deps_start; i < current_ins_start; i += 2)
3372                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3373                                         need_stop = TRUE;
3374                         break;
3375                 case IA64_READ_AR:
3376                         reg = deps [pos + 1];
3377
3378                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3379                         for (i = current_deps_start; i < current_ins_start; i += 2)
3380                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3381                                         need_stop = TRUE;
3382                         break;
3383                 case IA64_WRITE_AR:
3384                         reg = code->dep_info [pos + 1];
3385
3386                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3387                         for (i = current_deps_start; i < current_ins_start; i += 2)
3388                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3389                                         need_stop = TRUE;
3390                         break;
3391                 case IA64_NO_STOP:
3392                         /*
3393                          * Explicitly indicate that a stop is not required. Useful for
3394                          * example when two predicated instructions with negated predicates
3395                          * write the same registers.
3396                          */
3397                         no_stop = TRUE;
3398                         break;
3399                 default:
3400                         g_assert_not_reached ();
3401                 }
3402                 pos += 2;
3403
3404                 if (need_stop && !no_stop) {
3405                         g_assert (ins_index > 0);
3406                         stops [ins_index - 1] = 1;
3407
3408                         DEBUG_INS_SCHED (printf ("STOP\n"));
3409                         current_deps_start = current_ins_start;
3410
3411                         /* Skip remaining deps for this instruction */
3412                         while (deps [pos] != IA64_END_OF_INS)
3413                                 pos += 2;
3414                 }
3415         }
3416
3417         if (code->nins > 0) {
3418                 /* No dependency info for the last instruction */
3419                 stops [code->nins - 1] = 1;
3420         }
3421
3422         deps_start [code->nins] = code->dep_info_pos;
3423 }
3424
3425 static void
3426 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3427 {
3428         int stop_pos, i, deps_to_shift, dep_shift;
3429
3430         g_assert (n <= code->nins);
3431
3432         // if (n > 1) printf ("FOUND: %ld.\n", template);
3433
3434         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3435
3436         stop_pos = last_stop_in_template [template] + 1;
3437         if (stop_pos > n)
3438                 stop_pos = n;
3439
3440         /* Compute the number of 'real' instructions before the stop */
3441         deps_to_shift = stop_pos;
3442         if (stop_pos >= 3 && (nops & (1 << 2)))
3443                 deps_to_shift --;
3444         if (stop_pos >= 2 && (nops & (1 << 1)))
3445                 deps_to_shift --;
3446         if (stop_pos >= 1 && (nops & (1 << 0)))
3447                 deps_to_shift --;
3448
3449         /*
3450          * We have to keep some dependencies whose instructions have been shifted
3451          * out of the buffer. So nullify the end_of_ins markers in the dependency
3452          * array.
3453          */
3454         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3455                 if (code->dep_info [i] == IA64_END_OF_INS)
3456                         code->dep_info [i] = IA64_NONE;
3457
3458         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3459         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3460         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3461
3462         dep_shift = deps_start [deps_to_shift];
3463         for (i = 0; i < code->nins + 1 - n; ++i)
3464                 deps_start [i] = deps_start [n + i] - dep_shift;
3465
3466         /* Determine the exact positions of instructions with unwind ops */
3467         if (code->unw_op_count) {
3468                 int ins_pos [16];
3469                 int curr_ins, curr_ins_pos;
3470
3471                 curr_ins = 0;
3472                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3473                 for (i = 0; i < 3; ++i) {
3474                         if (! (nops & (1 << i))) {
3475                                 ins_pos [curr_ins] = curr_ins_pos + i;
3476                                 curr_ins ++;
3477                         }
3478                 }
3479
3480                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3481                         if (code->unw_ops_pos [i] < n) {
3482                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3483                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3484                         }
3485                 }
3486                 if (code->unw_op_pos < code->unw_op_count)
3487                         code->unw_op_pos += n;
3488         }
3489
3490         if (n == code->nins) {
3491                 code->template = 0;
3492                 code->nins = 0;
3493         }
3494         else {
3495                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3496                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3497                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3498                 code->nins -= n;
3499         }
3500 }
3501
3502 void
3503 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3504 {
3505         int i, ins_type, template, nins_to_emit;
3506         int deps_start [16];
3507         int stops [16];
3508         gboolean found;
3509
3510         /*
3511          * We implement a simple scheduler which tries to put three instructions
3512          * per bundle, then two, then one.
3513          */
3514         ia64_analyze_deps (code, deps_start, stops);
3515
3516         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3517                 /* Find a suitable template */
3518                 for (template = 0; template < 32; ++template) {
3519                         if (stops_in_template [template][0] != stops [0] ||
3520                                 stops_in_template [template][1] != stops [1] ||
3521                                 stops_in_template [template][2] != stops [2])
3522                                 continue;
3523
3524                         found = TRUE;
3525                         for (i = 0; i < 3; ++i) {
3526                                 ins_type = ins_types_in_template [template][i];
3527                                 switch (code->itypes [i]) {
3528                                 case IA64_INS_TYPE_A:
3529                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3530                                         break;
3531                                 default:
3532                                         found &= (ins_type == code->itypes [i]);
3533                                         break;
3534                                 }
3535                         }
3536
3537                         if (found)
3538                                 found = debug_ins_sched ();
3539
3540                         if (found) {
3541                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3542                                 break;
3543                         }
3544                 }
3545         }
3546
3547         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3548                 /* Wait for more instructions */
3549                 return;
3550
3551         /* If it didn't work out, try putting two instructions into one bundle */
3552         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3553                 /* Try a nop at the end */
3554                 for (template = 0; template < 32; ++template) {
3555                         if (stops_in_template [template][0] != stops [0] ||
3556                                 ((stops_in_template [template][1] != stops [1]) &&
3557                                  (stops_in_template [template][2] != stops [1])))
3558
3559                                 continue;
3560
3561                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3562                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3563                                 continue;
3564
3565                         if (!debug_ins_sched ())
3566                                 continue;
3567
3568                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3569                         break;
3570                 }
3571         }
3572
3573         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3574                 /* Wait for more instructions */
3575                 return;
3576
3577         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3578                 /* Try a nop in the middle */
3579                 for (template = 0; template < 32; ++template) {
3580                         if (((stops_in_template [template][0] != stops [0]) &&
3581                                  (stops_in_template [template][1] != stops [0])) ||
3582                                 stops_in_template [template][2] != stops [1])
3583                                 continue;
3584
3585                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3586                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3587                                 continue;
3588
3589                         if (!debug_ins_sched ())
3590                                 continue;
3591
3592                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3593                         break;
3594                 }
3595         }
3596
3597         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3598                 /* Try a nop at the beginning */
3599                 for (template = 0; template < 32; ++template) {
3600                         if ((stops_in_template [template][1] != stops [0]) ||
3601                                 (stops_in_template [template][2] != stops [1]))
3602                                 continue;
3603
3604                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3605                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3606                                 continue;
3607
3608                         if (!debug_ins_sched ())
3609                                 continue;
3610
3611                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3612                         break;
3613                 }
3614         }
3615
3616         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3617                 /* Wait for more instructions */
3618                 return;
3619
3620         if (flush)
3621                 nins_to_emit = code->nins;
3622         else
3623                 nins_to_emit = 1;
3624
3625         while (nins_to_emit > 0) {
3626                 if (!debug_ins_sched ())
3627                         stops [0] = 1;
3628                 switch (code->itypes [0]) {
3629                 case IA64_INS_TYPE_A:
3630                         if (stops [0])
3631                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3632                         else
3633                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3634                         break;
3635                 case IA64_INS_TYPE_I:
3636                         if (stops [0])
3637                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3638                         else
3639                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3640                         break;
3641                 case IA64_INS_TYPE_M:
3642                         if (stops [0])
3643                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3644                         else
3645                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3646                         break;
3647                 case IA64_INS_TYPE_B:
3648                         if (stops [0])
3649                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3650                         else
3651                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3652                         break;
3653                 case IA64_INS_TYPE_F:
3654                         if (stops [0])
3655                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3656                         else
3657                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3658                         break;
3659                 case IA64_INS_TYPE_LX:
3660                         if (stops [0] || stops [1])
3661                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3662                         else
3663                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3664                         nins_to_emit --;
3665                         break;
3666                 default:
3667                         g_assert_not_reached ();
3668                 }
3669                 nins_to_emit --;
3670         }
3671 }
3672
3673 unw_dyn_region_info_t*
3674 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3675 {
3676         unw_dyn_region_info_t *r;
3677
3678         g_assert (code->nins == 0);
3679         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3680         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3681         r->op_count = code->unw_op_count;
3682         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3683         code->unw_op_count = 0;
3684         code->unw_op_pos = 0;
3685         code->region_start = code->buf;
3686
3687         return r;
3688 }
3689
3690 static void
3691 ia64_patch (unsigned char* code, gpointer target)
3692 {
3693         int template, i;
3694         guint64 instructions [3];
3695         guint8 gen_buf [16];
3696         Ia64CodegenState gen;
3697         int ins_to_skip;
3698         gboolean found;
3699
3700         /*
3701          * code encodes both the position inside the buffer and code.nins when
3702          * the instruction was emitted.
3703          */
3704         ins_to_skip = (guint64)code % 16;
3705         code = (unsigned char*)((guint64)code & ~15);
3706
3707         /*
3708          * Search for the first instruction which is 'patchable', skipping
3709          * ins_to_skip instructions.
3710          */
3711
3712         while (TRUE) {
3713
3714         template = ia64_bundle_template (code);
3715         instructions [0] = ia64_bundle_ins1 (code);
3716         instructions [1] = ia64_bundle_ins2 (code);
3717         instructions [2] = ia64_bundle_ins3 (code);
3718
3719         ia64_codegen_init (gen, gen_buf);
3720
3721         found = FALSE;
3722         for (i = 0; i < 3; ++i) {
3723                 guint64 ins = instructions [i];
3724                 int opcode = ia64_ins_opcode (ins);
3725
3726                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3727                         continue;
3728
3729                 if (ins_to_skip) {
3730                         ins_to_skip --;
3731                         continue;
3732                 }
3733
3734                 switch (ins_types_in_template [template][i]) {
3735                 case IA64_INS_TYPE_A:
3736                 case IA64_INS_TYPE_M:
3737                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3738                                 /* adds */
3739                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3740                                 instructions [i] = gen.instructions [0];
3741                                 found = TRUE;
3742                         }
3743                         else
3744                                 NOT_IMPLEMENTED;
3745                         break;
3746                 case IA64_INS_TYPE_B:
3747                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3748                                 /* br.cond */
3749                                 gint64 disp = ((guint8*)target - code) >> 4;
3750
3751                                 /* FIXME: hints */
3752                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3753
3754                                 instructions [i] = gen.instructions [0];
3755                                 found = TRUE;
3756                         }
3757                         else if (opcode == 5) {
3758                                 /* br.call */
3759                                 gint64 disp = ((guint8*)target - code) >> 4;
3760
3761                                 /* FIXME: hints */
3762                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3763                                 instructions [i] = gen.instructions [0];
3764                                 found = TRUE;
3765                         }
3766                         else
3767                                 NOT_IMPLEMENTED;
3768                         break;
3769                 case IA64_INS_TYPE_LX:
3770                         if (i == 1)
3771                                 break;
3772
3773                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3774                                 /* movl */
3775                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3776                                 instructions [1] = gen.instructions [0];
3777                                 instructions [2] = gen.instructions [1];
3778                                 found = TRUE;
3779                         }
3780                         else
3781                                 NOT_IMPLEMENTED;
3782
3783                         break;
3784                 default:
3785                         NOT_IMPLEMENTED;
3786                 }
3787
3788                 if (found) {
3789                         /* Rewrite code */
3790                         ia64_codegen_init (gen, code);
3791                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3792                         return;
3793                 }
3794         }
3795
3796         code += 16;
3797         }
3798 }
3799
3800 void
3801 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
3802 {
3803         MonoJumpInfo *patch_info;
3804
3805         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3806                 unsigned char *ip = patch_info->ip.i + code;
3807                 const unsigned char *target;
3808
3809                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3810
3811                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3812                         continue;
3813                 if (mono_compile_aot) {
3814                         NOT_IMPLEMENTED;
3815                 }
3816
3817                 ia64_patch (ip, (gpointer)target);
3818         }
3819 }
3820
3821 guint8 *
3822 mono_arch_emit_prolog (MonoCompile *cfg)
3823 {
3824         MonoMethod *method = cfg->method;
3825         MonoMethodSignature *sig;
3826         MonoInst *inst;
3827         int alloc_size, pos, i;
3828         Ia64CodegenState code;
3829         CallInfo *cinfo;
3830
3831         sig = mono_method_signature (method);
3832         pos = 0;
3833
3834         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3835
3836         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3837
3838         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3839                 cfg->code_size += 1024;
3840         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3841                 cfg->code_size += 1024;
3842
3843         cfg->native_code = g_malloc (cfg->code_size);
3844
3845         ia64_codegen_init (code, cfg->native_code);
3846
3847         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3848         if (cfg->param_area)
3849                 alloc_size += cfg->param_area;
3850         if (alloc_size)
3851                 /* scratch area */
3852                 alloc_size += 16;
3853         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3854
3855         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3856                 /* Force sp to be saved/restored */
3857                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3858
3859         cfg->arch.stack_alloc_size = alloc_size;
3860
3861         pos = 0;
3862
3863         if (method->save_lmf) {
3864                 /* No LMF on IA64 */
3865         }
3866
3867         alloc_size -= pos;
3868
3869         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3870         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3871         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3872         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3873
3874         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3875                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3876                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3877                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3878                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3879         }
3880
3881         if (alloc_size) {
3882 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3883                 int pagesize = getpagesize ();
3884
3885                 if (alloc_size >= pagesize) {
3886                         gint32 remaining_size = alloc_size;
3887
3888                         /* Generate stack touching code */
3889                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3890                         while (remaining_size >= pagesize) {
3891                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3892                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3893                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3894                                 remaining_size -= pagesize;
3895                         }
3896                 }
3897 #endif
3898                 if (ia64_is_imm14 (-alloc_size)) {
3899                         if (cfg->arch.omit_fp)
3900                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3901                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3902                 }
3903                 else {
3904                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3905                         if (cfg->arch.omit_fp)
3906                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3907                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3908                 }
3909         }
3910
3911         ia64_begin_bundle (code);
3912
3913         /* Initialize unwind info */
3914         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3915
3916         if (sig->ret->type != MONO_TYPE_VOID) {
3917                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3918                         /* Save volatile arguments to the stack */
3919                         NOT_IMPLEMENTED;
3920                 }
3921         }
3922
3923         /* Keep this in sync with emit_load_volatile_arguments */
3924         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3925                 ArgInfo *ainfo = cinfo->args + i;
3926                 gint32 stack_offset;
3927                 MonoType *arg_type;
3928
3929                 inst = cfg->args [i];
3930
3931                 if (sig->hasthis && (i == 0))
3932                         arg_type = &mono_defaults.object_class->byval_arg;
3933                 else
3934                         arg_type = sig->params [i - sig->hasthis];
3935
3936                 arg_type = mono_type_get_underlying_type (arg_type);
3937
3938                 stack_offset = ainfo->offset + ARGS_OFFSET;
3939
3940                 /*
3941                  * FIXME: Native code might pass non register sized integers
3942                  * without initializing the upper bits.
3943                  */
3944                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3945                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3946
3947                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3948                         case OP_LOADI1_MEMBASE:
3949                                 ia64_sxt1 (code, reg, reg);
3950                                 break;
3951                         case OP_LOADU1_MEMBASE:
3952                                 ia64_zxt1 (code, reg, reg);
3953                                 break;
3954                         case OP_LOADI2_MEMBASE:
3955                                 ia64_sxt2 (code, reg, reg);
3956                                 break;
3957                         case OP_LOADU2_MEMBASE:
3958                                 ia64_zxt2 (code, reg, reg);
3959                                 break;
3960                         default:
3961                                 break;
3962                         }
3963                 }
3964
3965                 /* Save volatile arguments to the stack */
3966                 if (inst->opcode != OP_REGVAR) {
3967                         switch (ainfo->storage) {
3968                         case ArgInIReg:
3969                         case ArgInFloatReg:
3970                         case ArgInFloatRegR4:
3971                                 g_assert (inst->opcode == OP_REGOFFSET);
3972                                 if (ia64_is_adds_imm (inst->inst_offset))
3973                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3974                                 else {
3975                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3976                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3977                                 }
3978                                 if (arg_type->byref)
3979                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3980                                 else {
3981                                         switch (arg_type->type) {
3982                                         case MONO_TYPE_R4:
3983                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3984                                                 break;
3985                                         case MONO_TYPE_R8:
3986                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3987                                                 break;
3988                                         default:
3989                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3990                                                 break;
3991                                         }
3992                                 }
3993                                 break;
3994                         case ArgOnStack:
3995                                 break;
3996                         case ArgAggregate:
3997                                 if (ainfo->nslots != ainfo->nregs)
3998                                         NOT_IMPLEMENTED;
3999
4000                                 g_assert (inst->opcode == OP_REGOFFSET);
4001                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
4002                                 for (i = 0; i < ainfo->nregs; ++i) {
4003                                         switch (ainfo->atype) {
4004                                         case AggregateNormal:
4005                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
4006                                                 break;
4007                                         case AggregateSingleHFA:
4008                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
4009                                                 break;
4010                                         case AggregateDoubleHFA:
4011                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
4012                                                 break;
4013                                         default:
4014                                                 NOT_IMPLEMENTED;
4015                                         }
4016                                 }
4017                                 break;
4018                         default:
4019                                 g_assert_not_reached ();
4020                         }
4021                 }
4022
4023                 if (inst->opcode == OP_REGVAR) {
4024                         /* Argument allocated to (non-volatile) register */
4025                         switch (ainfo->storage) {
4026                         case ArgInIReg:
4027                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4028                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4029                                 break;
4030                         case ArgOnStack:
4031                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4032                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4033                                 break;
4034                         default:
4035                                 NOT_IMPLEMENTED;
4036                         }
4037                 }
4038         }
4039
4040         if (method->save_lmf) {
4041                 /* No LMF on IA64 */
4042         }
4043
4044         ia64_codegen_close (code);
4045
4046         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4047                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4048
4049         cfg->code_len = code.buf - cfg->native_code;
4050
4051         g_assert (cfg->code_len < cfg->code_size);
4052
4053         cfg->arch.prolog_end_offset = cfg->code_len;
4054
4055         return code.buf;
4056 }
4057
4058 void
4059 mono_arch_emit_epilog (MonoCompile *cfg)
4060 {
4061         MonoMethod *method = cfg->method;
4062         int i, pos;
4063         int max_epilog_size = 16 * 4;
4064         Ia64CodegenState code;
4065         guint8 *buf;
4066         CallInfo *cinfo;
4067         ArgInfo *ainfo;
4068
4069         if (mono_jit_trace_calls != NULL)
4070                 max_epilog_size += 1024;
4071
4072         cfg->arch.epilog_begin_offset = cfg->code_len;
4073
4074         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4075                 cfg->code_size *= 2;
4076                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4077                 cfg->stat_code_reallocs++;
4078         }
4079
4080         /* FIXME: Emit unwind info */
4081
4082         buf = cfg->native_code + cfg->code_len;
4083
4084         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4085                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4086
4087         ia64_codegen_init (code, buf);
4088
4089         /* the code restoring the registers must be kept in sync with OP_JMP */
4090         pos = 0;
4091
4092         if (method->save_lmf) {
4093                 /* No LMF on IA64 */
4094         }
4095
4096         /* Load returned vtypes into registers if needed */
4097         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4098         ainfo = &cinfo->ret;
4099         switch (ainfo->storage) {
4100         case ArgAggregate:
4101                 if (ainfo->nslots != ainfo->nregs)
4102                         NOT_IMPLEMENTED;
4103
4104                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4105                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4106                 for (i = 0; i < ainfo->nregs; ++i) {
4107                         switch (ainfo->atype) {
4108                         case AggregateNormal:
4109                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4110                                 break;
4111                         case AggregateSingleHFA:
4112                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4113                                 break;
4114                         case AggregateDoubleHFA:
4115                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4116                                 break;
4117                         default:
4118                                 g_assert_not_reached ();
4119                         }
4120                 }
4121                 break;
4122         default:
4123                 break;
4124         }
4125
4126         ia64_begin_bundle (code);
4127
4128         code.region_start = cfg->native_code;
4129
4130         /* Label the unwind state at the start of the exception throwing region */
4131         //ia64_unw_label_state (code, 1234);
4132
4133         if (cfg->arch.stack_alloc_size) {
4134                 if (cfg->arch.omit_fp) {
4135                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4136                                 ia64_unw_pop_frames (code, 1);
4137                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4138                         } else {
4139                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4140                                 ia64_unw_pop_frames (code, 1);
4141                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4142                         }
4143                 }
4144                 else {
4145                         ia64_unw_pop_frames (code, 1);
4146                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4147                 }
4148         }
4149         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4150         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4151         ia64_br_ret_reg (code, IA64_B0);
4152
4153         ia64_codegen_close (code);
4154
4155         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4156         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4157
4158         cfg->code_len = code.buf - cfg->native_code;
4159
4160         g_assert (cfg->code_len < cfg->code_size);
4161 }
4162
4163 void
4164 mono_arch_emit_exceptions (MonoCompile *cfg)
4165 {
4166         MonoJumpInfo *patch_info;
4167         int i, nthrows;
4168         Ia64CodegenState code;
4169         gboolean empty = TRUE;
4170         //unw_dyn_region_info_t *r_exceptions;
4171         MonoClass *exc_classes [16];
4172         guint8 *exc_throw_start [16], *exc_throw_end [16];
4173         guint32 code_size = 0;
4174
4175         /* Compute needed space */
4176         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4177                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4178                         code_size += 256;
4179                 if (patch_info->type == MONO_PATCH_INFO_R8)
4180                         code_size += 8 + 7; /* sizeof (double) + alignment */
4181                 if (patch_info->type == MONO_PATCH_INFO_R4)
4182                         code_size += 4 + 7; /* sizeof (float) + alignment */
4183         }
4184
4185         if (code_size == 0)
4186                 return;
4187
4188         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4189                 cfg->code_size *= 2;
4190                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4191                 cfg->stat_code_reallocs++;
4192         }
4193
4194         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4195
4196         /* The unwind state here is the same as before the epilog */
4197         //ia64_unw_copy_state (code, 1234);
4198
4199         /* add code to raise exceptions */
4200         /* FIXME: Optimize this */
4201         nthrows = 0;
4202         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4203                 switch (patch_info->type) {
4204                 case MONO_PATCH_INFO_EXC: {
4205                         MonoClass *exc_class;
4206                         guint8* throw_ip;
4207                         guint8* buf;
4208                         guint64 exc_token_index;
4209
4210                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4211                         g_assert (exc_class);
4212                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4213                         throw_ip = cfg->native_code + patch_info->ip.i;
4214
4215                         ia64_begin_bundle (code);
4216
4217                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4218
4219                         /* Find a throw sequence for the same exception class */
4220                         for (i = 0; i < nthrows; ++i)
4221                                 if (exc_classes [i] == exc_class)
4222                                         break;
4223
4224                         if (i < nthrows) {
4225                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4226
4227                                 if (ia64_is_adds_imm (offset))
4228                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4229                                 else
4230                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4231
4232                                 buf = code.buf + code.nins;
4233                                 ia64_br_cond_pred (code, 0, 0);
4234                                 ia64_begin_bundle (code);
4235                                 ia64_patch (buf, exc_throw_start [i]);
4236
4237                                 patch_info->type = MONO_PATCH_INFO_NONE;
4238                         }
4239                         else {
4240                                 /* Arg1 */
4241                                 buf = code.buf;
4242                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4243
4244                                 ia64_begin_bundle (code);
4245
4246                                 if (nthrows < 16) {
4247                                         exc_classes [nthrows] = exc_class;
4248                                         exc_throw_start [nthrows] = code.buf;
4249                                 }
4250
4251                                 /* Arg2 */
4252                                 if (ia64_is_adds_imm (exc_token_index))
4253                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4254                                 else
4255                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4256
4257                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4258                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4259                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4260
4261                                 /* Indirect call */
4262                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4263                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4264                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4265                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4266
4267                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4268
4269                                 /* Patch up the throw offset */
4270                                 ia64_begin_bundle (code);
4271
4272                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4273
4274                                 if (nthrows < 16) {
4275                                         exc_throw_end [nthrows] = code.buf;
4276                                         nthrows ++;
4277                                 }
4278                         }
4279
4280                         empty = FALSE;
4281                         break;
4282                 }
4283                 default:
4284                         break;
4285                 }
4286         }
4287
4288         if (!empty)
4289                 /* The unwinder needs this to work */
4290                 ia64_break_i (code, 0);
4291
4292         ia64_codegen_close (code);
4293
4294         /* FIXME: */
4295         //r_exceptions = mono_ia64_create_unwind_region (&code);
4296         //cfg->arch.r_epilog = r_exceptions;
4297
4298         cfg->code_len = code.buf - cfg->native_code;
4299
4300         g_assert (cfg->code_len < cfg->code_size);
4301 }
4302
4303 void*
4304 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4305 {
4306         Ia64CodegenState code;
4307         CallInfo *cinfo = NULL;
4308         MonoMethodSignature *sig;
4309         MonoInst *ins;
4310         int i, n, stack_area = 0;
4311
4312         ia64_codegen_init (code, p);
4313
4314         /* Keep this in sync with mono_arch_get_argument_info */
4315
4316         if (enable_arguments) {
4317                 /* Allocate a new area on the stack and save arguments there */
4318                 sig = mono_method_signature (cfg->method);
4319
4320                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4321
4322                 n = sig->param_count + sig->hasthis;
4323
4324                 stack_area = ALIGN_TO (n * 8, 16);
4325
4326                 if (n) {
4327                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4328
4329                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4330
4331                         /* FIXME: Allocate out registers */
4332
4333                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4334
4335                         /* Required by the ABI */
4336                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4337
4338                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4339                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4340
4341                         /* Save arguments to the stack */
4342                         for (i = 0; i < n; ++i) {
4343                                 ins = cfg->args [i];
4344
4345                                 if (ins->opcode == OP_REGVAR) {
4346                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4347                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4348                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4349                                 }
4350                                 else {
4351                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4352                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4353                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4354                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4355                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4356                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4357                                 }
4358                         }
4359                 }
4360                 else
4361                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4362         }
4363         else
4364                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4365
4366         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4367         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4368
4369         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4370
4371         if (enable_arguments && stack_area) {
4372                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4373
4374                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4375
4376                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4377         }
4378
4379         ia64_codegen_close (code);
4380
4381         return code.buf;
4382 }
4383
4384 void*
4385 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4386 {
4387         Ia64CodegenState code;
4388         CallInfo *cinfo = NULL;
4389         MonoMethod *method = cfg->method;
4390         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4391
4392         ia64_codegen_init (code, p);
4393
4394         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4395
4396         /* Save return value + pass it to func */
4397         switch (cinfo->ret.storage) {
4398         case ArgNone:
4399                 break;
4400         case ArgInIReg:
4401                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4402                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4403                 break;
4404         case ArgInFloatReg:
4405                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4406                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4407                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4408                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4409                 break;
4410         case ArgValuetypeAddrInIReg:
4411                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4412                 break;
4413         case ArgAggregate:
4414                 NOT_IMPLEMENTED;
4415                 break;
4416         default:
4417                 break;
4418         }
4419
4420         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4421         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4422         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4423
4424         /* Restore return value */
4425         switch (cinfo->ret.storage) {
4426         case ArgNone:
4427                 break;
4428         case ArgInIReg:
4429                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4430                 break;
4431         case ArgInFloatReg:
4432                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4433                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4434                 break;
4435         case ArgValuetypeAddrInIReg:
4436                 break;
4437         case ArgAggregate:
4438                 break;
4439         default:
4440                 break;
4441         }
4442
4443         ia64_codegen_close (code);
4444
4445         return code.buf;
4446 }
4447
4448 void
4449 mono_arch_save_unwind_info (MonoCompile *cfg)
4450 {
4451         unw_dyn_info_t *di;
4452
4453         /* FIXME: Unregister this for dynamic methods */
4454
4455         di = g_malloc0 (sizeof (unw_dyn_info_t));
4456         di->start_ip = (unw_word_t) cfg->native_code;
4457         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4458         di->gp = 0;
4459         di->format = UNW_INFO_FORMAT_DYNAMIC;
4460         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4461         di->u.pi.regions = cfg->arch.r_pro;
4462
4463         _U_dyn_register (di);
4464
4465         /*
4466         {
4467                 unw_dyn_region_info_t *region = di->u.pi.regions;
4468
4469                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4470                 while (region) {
4471                         printf ("    [Region: %d]\n", region->insn_count);
4472                         region = region->next;
4473                 }
4474         }
4475         */
4476 }
4477
4478 void
4479 mono_arch_flush_icache (guint8 *code, gint size)
4480 {
4481         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4482         guint8* end = (guint8*)((guint64)code + size);
4483
4484 #ifdef __INTEL_COMPILER
4485         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4486         while (p < end) {
4487                 __fc ((guint64)p);
4488                 p += 32;
4489         }
4490 #else
4491         while (p < end) {
4492                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4493                 /* FIXME: This could be increased to 128 on some cpus */
4494                 p += 32;
4495         }
4496 #endif
4497 }
4498
4499 void
4500 mono_arch_flush_register_windows (void)
4501 {
4502         /* Not needed because of libunwind */
4503 }
4504
4505 gboolean
4506 mono_arch_is_inst_imm (gint64 imm)
4507 {
4508         /* The lowering pass will take care of it */
4509
4510         return TRUE;
4511 }
4512
4513 /*
4514  * Determine whenever the trap whose info is in SIGINFO is caused by
4515  * integer overflow.
4516  */
4517 gboolean
4518 mono_arch_is_int_overflow (void *sigctx, void *info)
4519 {
4520         /* Division is emulated with explicit overflow checks */
4521         return FALSE;
4522 }
4523
4524 guint32
4525 mono_arch_get_patch_offset (guint8 *code)
4526 {
4527         NOT_IMPLEMENTED;
4528
4529         return 0;
4530 }
4531
4532 gpointer*
4533 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4534 {
4535         NOT_IMPLEMENTED;
4536
4537         return NULL;
4538 }
4539
4540 void
4541 mono_arch_finish_init (void)
4542 {
4543 }
4544
4545 void
4546 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4547 {
4548 }
4549
4550 #ifdef MONO_ARCH_HAVE_IMT
4551
4552 /*
4553  * LOCKING: called with the domain lock held
4554  */
4555 gpointer
4556 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4557         gpointer fail_tramp)
4558 {
4559         int i;
4560         int size = 0;
4561         guint8 *start, *buf;
4562         Ia64CodegenState code;
4563
4564         size = count * 256;
4565         buf = g_malloc0 (size);
4566         ia64_codegen_init (code, buf);
4567
4568         /* IA64_R9 contains the IMT method */
4569
4570         for (i = 0; i < count; ++i) {
4571                 MonoIMTCheckItem *item = imt_entries [i];
4572                 ia64_begin_bundle (code);
4573                 item->code_target = (guint8*)code.buf + code.nins;
4574                 if (item->is_equals) {
4575                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4576
4577                         if (item->check_target_idx || fail_case) {
4578                                 if (!item->compare_done || fail_case) {
4579                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4580                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4581                                 }
4582                                 item->jmp_code = (guint8*)code.buf + code.nins;
4583                                 ia64_br_cond_pred (code, 7, 0);
4584
4585                                 if (item->has_target_code) {
4586                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4587                                 } else {
4588                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4589                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4590                                 }
4591                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4592                                 ia64_br_cond_reg (code, IA64_B6);
4593
4594                                 if (fail_case) {
4595                                         ia64_begin_bundle (code);
4596                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4597                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4598                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4599                                         ia64_br_cond_reg (code, IA64_B6);
4600                                         item->jmp_code = NULL;
4601                                 }
4602                         } else {
4603                                 /* enable the commented code to assert on wrong method */
4604 #if ENABLE_WRONG_METHOD_CHECK
4605                                 g_assert_not_reached ();
4606 #endif
4607                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4608                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4609                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4610                                 ia64_br_cond_reg (code, IA64_B6);
4611 #if ENABLE_WRONG_METHOD_CHECK
4612                                 g_assert_not_reached ();
4613 #endif
4614                         }
4615                 } else {
4616                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4617                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4618                         item->jmp_code = (guint8*)code.buf + code.nins;
4619                         ia64_br_cond_pred (code, 6, 0);
4620                 }
4621         }
4622         /* patch the branches to get to the target items */
4623         for (i = 0; i < count; ++i) {
4624                 MonoIMTCheckItem *item = imt_entries [i];
4625                 if (item->jmp_code) {
4626                         if (item->check_target_idx) {
4627                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4628                         }
4629                 }
4630         }
4631
4632         ia64_codegen_close (code);
4633         g_assert (code.buf - buf <= size);
4634
4635         size = code.buf - buf;
4636         if (fail_tramp) {
4637                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4638                 start = (gpointer)ALIGN_TO (start, 16);
4639         } else {
4640                 start = mono_domain_code_reserve (domain, size);
4641         }
4642         memcpy (start, buf, size);
4643
4644         mono_arch_flush_icache (start, size);
4645
4646         mono_stats.imt_thunks_size += size;
4647
4648         return start;
4649 }
4650
4651 MonoMethod*
4652 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4653 {
4654         return (MonoMethod*)regs [IA64_R9];
4655 }
4656
4657 void
4658 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4659 {
4660         /* Done by the implementation of the CALL_MEMBASE opcodes */
4661 }
4662 #endif
4663
4664 gpointer
4665 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4666 {
4667         return (gpointer)regs [IA64_R10];
4668 }
4669
4670 gpointer
4671 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4672 {
4673         return NULL;
4674 }
4675
4676 MonoInst*
4677 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4678 {
4679         MonoInst *ins = NULL;
4680
4681         if (cmethod->klass->image == mono_defaults.corlib &&
4682                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4683                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4684
4685                 /*
4686                  * We don't use the generic version in mini_emit_inst_for_method () since we
4687                  * ia64 has atomic_add_imm opcodes.
4688                  */
4689                 if (strcmp (cmethod->name, "Increment") == 0) {
4690                         guint32 opcode;
4691
4692                         if (fsig->params [0]->type == MONO_TYPE_I4)
4693                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4694                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4695                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4696                         else
4697                                 g_assert_not_reached ();
4698                         MONO_INST_NEW (cfg, ins, opcode);
4699                         ins->dreg = mono_alloc_preg (cfg);
4700                         ins->inst_imm = 1;
4701                         ins->inst_basereg = args [0]->dreg;
4702                         ins->inst_offset = 0;
4703                         MONO_ADD_INS (cfg->cbb, ins);
4704                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4705                         guint32 opcode;
4706
4707                         if (fsig->params [0]->type == MONO_TYPE_I4)
4708                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4709                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4710                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4711                         else
4712                                 g_assert_not_reached ();
4713                         MONO_INST_NEW (cfg, ins, opcode);
4714                         ins->dreg = mono_alloc_preg (cfg);
4715                         ins->inst_imm = -1;
4716                         ins->inst_basereg = args [0]->dreg;
4717                         ins->inst_offset = 0;
4718                         MONO_ADD_INS (cfg->cbb, ins);
4719                 } else if (strcmp (cmethod->name, "Add") == 0) {
4720                         guint32 opcode;
4721                         gboolean is_imm = FALSE;
4722                         gint64 imm = 0;
4723
4724                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4725                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4726
4727                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4728                         }
4729
4730                         if (is_imm) {
4731                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4732                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4733                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4734                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4735                                 else
4736                                         g_assert_not_reached ();
4737
4738                                 MONO_INST_NEW (cfg, ins, opcode);
4739                                 ins->dreg = mono_alloc_ireg (cfg);
4740                                 ins->inst_basereg = args [0]->dreg;
4741                                 ins->inst_offset = 0;
4742                                 ins->inst_imm = imm;
4743                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4744                         } else {
4745                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4746                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4747                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4748                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4749                                 else
4750                                         g_assert_not_reached ();
4751
4752                                 MONO_INST_NEW (cfg, ins, opcode);
4753                                 ins->dreg = mono_alloc_ireg (cfg);
4754                                 ins->inst_basereg = args [0]->dreg;
4755                                 ins->inst_offset = 0;
4756                                 ins->sreg2 = args [1]->dreg;
4757                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4758                         }
4759                         MONO_ADD_INS (cfg->cbb, ins);
4760                 }
4761         }
4762
4763         return ins;
4764 }
4765
4766 gboolean
4767 mono_arch_print_tree (MonoInst *tree, int arity)
4768 {
4769         return 0;
4770 }
4771
4772 MonoInst*
4773 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4774 {
4775         return mono_get_domain_intrinsic (cfg);
4776 }
4777
4778 mgreg_t
4779 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4780 {
4781         /* FIXME: implement */
4782         g_assert_not_reached ();
4783 }