mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24 #include <mono/utils/mono-hwcap-ia64.h>
  25
  26 #include "trace.h"
  27 #include "mini-ia64.h"
  28 #include "cpu-ia64.h"
  29 #include "jit-icalls.h"
  30 #include "ir-emit.h"
  31
  32 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  33
  34 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  35
  36 /*
  37  * IA64 register usage:
  38  * - local registers are used for global register allocation
  39  * - r8..r11, r14..r30 is used for local register allocation
  40  * - r31 is a scratch register used within opcode implementations
  41  * - FIXME: Use out registers as well
  42  * - the first three locals are used for saving ar.pfst, b0, and sp
  43  * - compare instructions allways set p6 and p7
  44  */
  45
  46 /*
  47  * There are a lot of places where generated code is disassembled/patched.
  48  * The automatic bundling of instructions done by the code generation macros
  49  * could complicate things, so it is best to call
  50  * ia64_codegen_set_one_ins_per_bundle () at those places.
  51  */
  52
  53 #define ARGS_OFFSET 16
  54
  55 #define GP_SCRATCH_REG 31
  56 #define GP_SCRATCH_REG2 30
  57 #define FP_SCRATCH_REG 32
  58 #define FP_SCRATCH_REG2 33
  59
  60 #define LOOP_ALIGNMENT 8
  61 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  62
  63 static const char* gregs [] = {
  64         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  65         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  66         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  67         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  68         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  69         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  70         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  71         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  72         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  73         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  74         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  75         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  76         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  77 };
  78
  79 const char*
  80 mono_arch_regname (int reg)
  81 {
  82         if (reg < 128)
  83                 return gregs [reg];
  84         else
  85                 return "unknown";
  86 }
  87
  88 static const char* fregs [] = {
  89         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  90         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  91         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  92         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  93         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  94         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  95         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  96         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  97         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  98         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  99         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
 100         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 101         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < 128)
 108                 return fregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 static gboolean
 114 debug_ins_sched (void)
 115 {
 116 #if 0
 117         return mono_debug_count ();
 118 #else
 119         return TRUE;
 120 #endif
 121 }
 122
 123 static gboolean
 124 debug_omit_fp (void)
 125 {
 126 #if 0
 127         return mono_debug_count ();
 128 #else
 129         return TRUE;
 130 #endif
 131 }
 132
 133 static void
 134 ia64_patch (unsigned char* code, gpointer target);
 135
 136 typedef enum {
 137         ArgInIReg,
 138         ArgInFloatReg,
 139         ArgInFloatRegR4,
 140         ArgOnStack,
 141         ArgValuetypeAddrInIReg,
 142         ArgAggregate,
 143         ArgSingleHFA,
 144         ArgDoubleHFA,
 145         ArgNone
 146 } ArgStorage;
 147
 148 typedef enum {
 149         AggregateNormal,
 150         AggregateSingleHFA,
 151         AggregateDoubleHFA
 152 } AggregateType;
 153
 154 typedef struct {
 155         gint16 offset;
 156         gint8  reg;
 157         ArgStorage storage;
 158
 159         /* Only if storage == ArgAggregate */
 160         int nregs, nslots;
 161         AggregateType atype;
 162 } ArgInfo;
 163
 164 typedef struct {
 165         int nargs;
 166         guint32 stack_usage;
 167         guint32 reg_usage;
 168         guint32 freg_usage;
 169         gboolean need_stack_align;
 170         gboolean vtype_retaddr;
 171         /* The index of the vret arg in the argument list */
 172         int vret_arg_index;
 173         ArgInfo ret;
 174         ArgInfo sig_cookie;
 175         ArgInfo args [1];
 176 } CallInfo;
 177
 178 #define DEBUG(a) if (cfg->verbose_level > 1) a
 179
 180 #define PARAM_REGS 8
 181
 182 static void inline
 183 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 184 {
 185     ainfo->offset = *stack_size;
 186
 187     if (*gr >= PARAM_REGS) {
 188                 ainfo->storage = ArgOnStack;
 189                 (*stack_size) += sizeof (gpointer);
 190     }
 191     else {
 192                 ainfo->storage = ArgInIReg;
 193                 ainfo->reg = *gr;
 194                 *(gr) += 1;
 195     }
 196 }
 197
 198 #define FLOAT_PARAM_REGS 8
 199
 200 static void inline
 201 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 211                 ainfo->reg = 8 + *fr;
 212                 (*fr) += 1;
 213                 (*gr) += 1;
 214     }
 215 }
 216
 217 static void
 218 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 219                gboolean is_return,
 220                guint32 *gr, guint32 *fr, guint32 *stack_size)
 221 {
 222         guint32 size, i;
 223         MonoClass *klass;
 224         MonoMarshalType *info;
 225         gboolean is_hfa = TRUE;
 226         guint32 hfa_type = 0;
 227
 228         klass = mono_class_from_mono_type (type);
 229         if (type->type == MONO_TYPE_TYPEDBYREF)
 230                 size = 3 * sizeof (gpointer);
 231         else if (sig->pinvoke)
 232                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 233         else
 234                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 235
 236         if (!sig->pinvoke || (size == 0)) {
 237                 /* Allways pass in memory */
 238                 ainfo->offset = *stack_size;
 239                 *stack_size += ALIGN_TO (size, 8);
 240                 ainfo->storage = ArgOnStack;
 241
 242                 return;
 243         }
 244
 245         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 246         info = mono_marshal_load_type_info (klass);
 247         g_assert (info);
 248         for (i = 0; i < info->num_fields; ++i) {
 249                 guint32 ftype = info->fields [i].field->type->type;
 250                 if (!(info->fields [i].field->type->byref) &&
 251                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 252                         if (hfa_type == 0)
 253                                 hfa_type = ftype;
 254                         else if (hfa_type != ftype)
 255                                 is_hfa = FALSE;
 256                 }
 257                 else
 258                         is_hfa = FALSE;
 259         }
 260         if (hfa_type == 0)
 261                 is_hfa = FALSE;
 262
 263         ainfo->storage = ArgAggregate;
 264         ainfo->atype = AggregateNormal;
 265
 266         if (is_hfa) {
 267                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 268                 if (is_return) {
 269                         if (info->num_fields <= 8) {
 270                                 ainfo->reg = 8;
 271                                 ainfo->nregs = info->num_fields;
 272                                 ainfo->nslots = ainfo->nregs;
 273                                 return;
 274                         }
 275                         /* Fall through */
 276                 }
 277                 else {
 278                         if ((*fr) + info->num_fields > 8)
 279                                 NOT_IMPLEMENTED;
 280
 281                         ainfo->reg = 8 + (*fr);
 282                         ainfo->nregs = info->num_fields;
 283                         ainfo->nslots = ainfo->nregs;
 284                         (*fr) += info->num_fields;
 285                         if (ainfo->atype == AggregateSingleHFA) {
 286                                 /*
 287                                  * FIXME: Have to keep track of the parameter slot number, which is
 288                                  * not the same as *gr.
 289                                  */
 290                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 291                         } else {
 292                                 (*gr) += info->num_fields;
 293                         }
 294                         return;
 295                 }
 296         }
 297
 298         /* This also handles returning of TypedByRef used by some icalls */
 299         if (is_return) {
 300                 if (size <= 32) {
 301                         ainfo->reg = IA64_R8;
 302                         ainfo->nregs = (size + 7) / 8;
 303                         ainfo->nslots = ainfo->nregs;
 304                         return;
 305                 }
 306                 NOT_IMPLEMENTED;
 307         }
 308
 309         ainfo->reg = (*gr);
 310         ainfo->offset = *stack_size;
 311         ainfo->nslots = (size + 7) / 8;
 312
 313         if (((*gr) + ainfo->nslots) <= 8) {
 314                 /* Fits entirely in registers */
 315                 ainfo->nregs = ainfo->nslots;
 316                 (*gr) += ainfo->nregs;
 317                 return;
 318         }
 319
 320         ainfo->nregs = 8 - (*gr);
 321         (*gr) = 8;
 322         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 323 }
 324
 325 /*
 326  * get_call_info:
 327  *
 328  *  Obtain information about a call according to the calling convention.
 329  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 330  * Gude" document for more information.
 331  */
 332 static CallInfo*
 333 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 334 {
 335         guint32 i, gr, fr, pstart;
 336         MonoType *ret_type;
 337         int n = sig->hasthis + sig->param_count;
 338         guint32 stack_size = 0;
 339         CallInfo *cinfo;
 340         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 341
 342         if (mp)
 343                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 344         else
 345                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 346
 347         gr = 0;
 348         fr = 0;
 349
 350         /* return value */
 351         {
 352                 ret_type = mono_type_get_underlying_type (sig->ret);
 353                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 354                 switch (ret_type->type) {
 355                 case MONO_TYPE_BOOLEAN:
 356                 case MONO_TYPE_I1:
 357                 case MONO_TYPE_U1:
 358                 case MONO_TYPE_I2:
 359                 case MONO_TYPE_U2:
 360                 case MONO_TYPE_CHAR:
 361                 case MONO_TYPE_I4:
 362                 case MONO_TYPE_U4:
 363                 case MONO_TYPE_I:
 364                 case MONO_TYPE_U:
 365                 case MONO_TYPE_PTR:
 366                 case MONO_TYPE_FNPTR:
 367                 case MONO_TYPE_CLASS:
 368                 case MONO_TYPE_OBJECT:
 369                 case MONO_TYPE_SZARRAY:
 370                 case MONO_TYPE_ARRAY:
 371                 case MONO_TYPE_STRING:
 372                         cinfo->ret.storage = ArgInIReg;
 373                         cinfo->ret.reg = IA64_R8;
 374                         break;
 375                 case MONO_TYPE_U8:
 376                 case MONO_TYPE_I8:
 377                         cinfo->ret.storage = ArgInIReg;
 378                         cinfo->ret.reg = IA64_R8;
 379                         break;
 380                 case MONO_TYPE_R4:
 381                 case MONO_TYPE_R8:
 382                         cinfo->ret.storage = ArgInFloatReg;
 383                         cinfo->ret.reg = 8;
 384                         break;
 385                 case MONO_TYPE_GENERICINST:
 386                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 387                                 cinfo->ret.storage = ArgInIReg;
 388                                 cinfo->ret.reg = IA64_R8;
 389                                 break;
 390                         }
 391                         /* Fall through */
 392                 case MONO_TYPE_VALUETYPE:
 393                 case MONO_TYPE_TYPEDBYREF: {
 394                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 395
 396                         if (sig->ret->byref) {
 397                                 /* This seems to happen with ldfld wrappers */
 398                                 cinfo->ret.storage = ArgInIReg;
 399                         } else {
 400                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 401                                 if (cinfo->ret.storage == ArgOnStack) {
 402                                         /* The caller passes the address where the value is stored */
 403                                         cinfo->vtype_retaddr = TRUE;
 404                                 }
 405                         }
 406                         break;
 407                 }
 408                 case MONO_TYPE_VOID:
 409                         cinfo->ret.storage = ArgNone;
 410                         break;
 411                 default:
 412                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 413                 }
 414         }
 415
 416         pstart = 0;
 417         /*
 418          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 419          * the first argument, allowing 'this' to be always passed in the first arg reg.
 420          * Also do this if the first argument is a reference type, since virtual calls
 421          * are sometimes made using calli without sig->hasthis set, like in the delegate
 422          * invoke wrappers.
 423          */
 424         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 425                 if (sig->hasthis) {
 426                         add_general (&gr, &stack_size, cinfo->args + 0);
 427                 } else {
 428                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 429                         pstart = 1;
 430                 }
 431                 add_general (&gr, &stack_size, &cinfo->ret);
 432                 if (cinfo->ret.storage == ArgInIReg)
 433                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 434                 cinfo->vret_arg_index = 1;
 435         } else {
 436                 /* this */
 437                 if (sig->hasthis)
 438                         add_general (&gr, &stack_size, cinfo->args + 0);
 439
 440                 if (cinfo->vtype_retaddr) {
 441                         add_general (&gr, &stack_size, &cinfo->ret);
 442                         if (cinfo->ret.storage == ArgInIReg)
 443                                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
 444                 }
 445         }
 446
 447         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 448                 gr = PARAM_REGS;
 449                 fr = FLOAT_PARAM_REGS;
 450
 451                 /* Emit the signature cookie just before the implicit arguments */
 452                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 453         }
 454
 455         for (i = pstart; i < sig->param_count; ++i) {
 456                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 457                 MonoType *ptype;
 458
 459                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 460                         /* We allways pass the sig cookie on the stack for simplicity */
 461                         /*
 462                          * Prevent implicit arguments + the sig cookie from being passed
 463                          * in registers.
 464                          */
 465                         gr = PARAM_REGS;
 466                         fr = FLOAT_PARAM_REGS;
 467
 468                         /* Emit the signature cookie just before the implicit arguments */
 469                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 470                 }
 471
 472                 if (sig->params [i]->byref) {
 473                         add_general (&gr, &stack_size, ainfo);
 474                         continue;
 475                 }
 476                 ptype = mono_type_get_underlying_type (sig->params [i]);
 477                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 478                 switch (ptype->type) {
 479                 case MONO_TYPE_BOOLEAN:
 480                 case MONO_TYPE_I1:
 481                 case MONO_TYPE_U1:
 482                         add_general (&gr, &stack_size, ainfo);
 483                         break;
 484                 case MONO_TYPE_I2:
 485                 case MONO_TYPE_U2:
 486                 case MONO_TYPE_CHAR:
 487                         add_general (&gr, &stack_size, ainfo);
 488                         break;
 489                 case MONO_TYPE_I4:
 490                 case MONO_TYPE_U4:
 491                         add_general (&gr, &stack_size, ainfo);
 492                         break;
 493                 case MONO_TYPE_I:
 494                 case MONO_TYPE_U:
 495                 case MONO_TYPE_PTR:
 496                 case MONO_TYPE_FNPTR:
 497                 case MONO_TYPE_CLASS:
 498                 case MONO_TYPE_OBJECT:
 499                 case MONO_TYPE_STRING:
 500                 case MONO_TYPE_SZARRAY:
 501                 case MONO_TYPE_ARRAY:
 502                         add_general (&gr, &stack_size, ainfo);
 503                         break;
 504                 case MONO_TYPE_GENERICINST:
 505                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 506                                 add_general (&gr, &stack_size, ainfo);
 507                                 break;
 508                         }
 509                         /* Fall through */
 510                 case MONO_TYPE_VALUETYPE:
 511                 case MONO_TYPE_TYPEDBYREF:
 512                         /* FIXME: */
 513                         /* We allways pass valuetypes on the stack */
 514                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 515                         break;
 516                 case MONO_TYPE_U8:
 517                 case MONO_TYPE_I8:
 518                         add_general (&gr, &stack_size, ainfo);
 519                         break;
 520                 case MONO_TYPE_R4:
 521                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 522                         break;
 523                 case MONO_TYPE_R8:
 524                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 525                         break;
 526                 default:
 527                         g_assert_not_reached ();
 528                 }
 529         }
 530
 531         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 532                 gr = PARAM_REGS;
 533                 fr = FLOAT_PARAM_REGS;
 534
 535                 /* Emit the signature cookie just before the implicit arguments */
 536                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 537         }
 538
 539         cinfo->stack_usage = stack_size;
 540         cinfo->reg_usage = gr;
 541         cinfo->freg_usage = fr;
 542         return cinfo;
 543 }
 544
 545 /*
 546  * mono_arch_get_argument_info:
 547  * @csig:  a method signature
 548  * @param_count: the number of parameters to consider
 549  * @arg_info: an array to store the result infos
 550  *
 551  * Gathers information on parameters such as size, alignment and
 552  * padding. arg_info should be large enought to hold param_count + 1 entries.
 553  *
 554  * Returns the size of the argument area on the stack.
 555  */
 556 int
 557 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 558 {
 559         int k;
 560         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 561         guint32 args_size = cinfo->stack_usage;
 562
 563         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 564         if (csig->hasthis) {
 565                 arg_info [0].offset = 0;
 566         }
 567
 568         for (k = 0; k < param_count; k++) {
 569                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 570                 /* FIXME: */
 571                 arg_info [k + 1].size = 0;
 572         }
 573
 574         g_free (cinfo);
 575
 576         return args_size;
 577 }
 578
 579 /*
 580  * Initialize the cpu to execute managed code.
 581  */
 582 void
 583 mono_arch_cpu_init (void)
 584 {
 585 }
 586
 587 /*
 588  * Initialize architecture specific code.
 589  */
 590 void
 591 mono_arch_init (void)
 592 {
 593 }
 594
 595 /*
 596  * Cleanup architecture specific code.
 597  */
 598 void
 599 mono_arch_cleanup (void)
 600 {
 601 }
 602
 603 /*
 604  * This function returns the optimizations supported on this cpu.
 605  */
 606 guint32
 607 mono_arch_cpu_optimizations (guint32 *exclude_mask)
 608 {
 609         *exclude_mask = 0;
 610
 611         return 0;
 612 }
 613
 614 /*
 615  * This function test for all SIMD functions supported.
 616  *
 617  * Returns a bitmask corresponding to all supported versions.
 618  *
 619  */
 620 guint32
 621 mono_arch_cpu_enumerate_simd_versions (void)
 622 {
 623         /* SIMD is currently unimplemented */
 624         return 0;
 625 }
 626
 627 GList *
 628 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 629 {
 630         GList *vars = NULL;
 631         int i;
 632         MonoMethodSignature *sig;
 633         MonoMethodHeader *header;
 634         CallInfo *cinfo;
 635
 636         header = cfg->header;
 637
 638         sig = mono_method_signature (cfg->method);
 639
 640         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 641
 642         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 643                 MonoInst *ins = cfg->args [i];
 644
 645                 ArgInfo *ainfo = &cinfo->args [i];
 646
 647                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 648                         continue;
 649
 650                 if (ainfo->storage == ArgInIReg) {
 651                         /* The input registers are non-volatile */
 652                         ins->opcode = OP_REGVAR;
 653                         ins->dreg = 32 + ainfo->reg;
 654                 }
 655         }
 656
 657         for (i = 0; i < cfg->num_varinfo; i++) {
 658                 MonoInst *ins = cfg->varinfo [i];
 659                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 660
 661                 /* unused vars */
 662                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 663                         continue;
 664
 665                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 666                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 667                         continue;
 668
 669                 if (mono_is_regsize_var (ins->inst_vtype)) {
 670                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 671                         g_assert (i == vmv->idx);
 672                         vars = g_list_prepend (vars, vmv);
 673                 }
 674         }
 675
 676         vars = mono_varlist_sort (cfg, vars, 0);
 677
 678         return vars;
 679 }
 680
 681 static void
 682 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 683 {
 684         CallInfo *cinfo;
 685         guint32 reserved_regs;
 686         MonoMethodHeader *header;
 687
 688         if (cfg->arch.reg_local0 > 0)
 689                 /* Already done */
 690                 return;
 691
 692         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 693
 694         header = cfg->header;
 695
 696         /* Some registers are reserved for use by the prolog/epilog */
 697         reserved_regs = header->num_clauses ? 4 : 3;
 698
 699         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 700                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 701                 /* One registers is needed by instrument_epilog to save the return value */
 702                 reserved_regs ++;
 703                 if (cinfo->reg_usage < 2)
 704                         /* Number of arguments passed to function call in instrument_prolog */
 705                         cinfo->reg_usage = 2;
 706         }
 707
 708         cfg->arch.reg_in0 = 32;
 709         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 710         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 711
 712         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 713         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 714         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 715
 716         /*
 717          * Frames without handlers save sp to fp, frames with handlers save it into
 718          * a dedicated register.
 719          */
 720         if (header->num_clauses)
 721                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 722         else
 723                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 724
 725         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 726                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 727                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 728         }
 729
 730         /*
 731          * Need to allocate at least 2 out register for use by OP_THROW / the system
 732          * exception throwing code.
 733          */
 734         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 735 }
 736
 737 GList *
 738 mono_arch_get_global_int_regs (MonoCompile *cfg)
 739 {
 740         GList *regs = NULL;
 741         int i;
 742
 743         mono_ia64_alloc_stacked_registers (cfg);
 744
 745         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 746                 /* FIXME: regmask */
 747                 g_assert (i < 64);
 748                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 749         }
 750
 751         return regs;
 752 }
 753
 754 /*
 755  * mono_arch_regalloc_cost:
 756  *
 757  *  Return the cost, in number of memory references, of the action of
 758  * allocating the variable VMV into a register during global register
 759  * allocation.
 760  */
 761 guint32
 762 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 763 {
 764         /* FIXME: Increase costs linearly to avoid using all local registers */
 765
 766         return 0;
 767 }
 768
 769 void
 770 mono_arch_allocate_vars (MonoCompile *cfg)
 771 {
 772         MonoMethodSignature *sig;
 773         MonoMethodHeader *header;
 774         MonoInst *inst;
 775         int i, offset;
 776         guint32 locals_stack_size, locals_stack_align;
 777         gint32 *offsets;
 778         CallInfo *cinfo;
 779
 780         header = cfg->header;
 781
 782         sig = mono_method_signature (cfg->method);
 783
 784         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 785
 786         /*
 787          * Determine whenever the frame pointer can be eliminated.
 788          * FIXME: Remove some of the restrictions.
 789          */
 790         cfg->arch.omit_fp = TRUE;
 791
 792         if (!debug_omit_fp ())
 793                 cfg->arch.omit_fp = FALSE;
 794
 795         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 796                 cfg->arch.omit_fp = FALSE;
 797         if (header->num_clauses)
 798                 cfg->arch.omit_fp = FALSE;
 799         if (cfg->param_area)
 800                 cfg->arch.omit_fp = FALSE;
 801         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 802                 cfg->arch.omit_fp = FALSE;
 803         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 804                 cfg->arch.omit_fp = FALSE;
 805         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 806                 ArgInfo *ainfo = &cinfo->args [i];
 807
 808                 if (ainfo->storage == ArgOnStack) {
 809                         /*
 810                          * The stack offset can only be determined when the frame
 811                          * size is known.
 812                          */
 813                         cfg->arch.omit_fp = FALSE;
 814                 }
 815         }
 816
 817         mono_ia64_alloc_stacked_registers (cfg);
 818
 819         /*
 820          * We use the ABI calling conventions for managed code as well.
 821          * Exception: valuetypes are never passed or returned in registers.
 822          */
 823
 824         if (cfg->arch.omit_fp) {
 825                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 826                 cfg->frame_reg = IA64_SP;
 827                 offset = ARGS_OFFSET;
 828         }
 829         else {
 830                 /* Locals are allocated backwards from %fp */
 831                 cfg->frame_reg = cfg->arch.reg_fp;
 832                 offset = 0;
 833         }
 834
 835         if (cfg->method->save_lmf) {
 836                 /* No LMF on IA64 */
 837         }
 838
 839         if (sig->ret->type != MONO_TYPE_VOID) {
 840                 switch (cinfo->ret.storage) {
 841                 case ArgInIReg:
 842                         cfg->ret->opcode = OP_REGVAR;
 843                         cfg->ret->inst_c0 = cinfo->ret.reg;
 844                         break;
 845                 case ArgInFloatReg:
 846                         cfg->ret->opcode = OP_REGVAR;
 847                         cfg->ret->inst_c0 = cinfo->ret.reg;
 848                         break;
 849                 case ArgValuetypeAddrInIReg:
 850                         cfg->vret_addr->opcode = OP_REGVAR;
 851                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 852                         break;
 853                 case ArgAggregate:
 854                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 855                         if (cfg->arch.omit_fp)
 856                                 g_assert_not_reached ();
 857                         offset = ALIGN_TO (offset, 8);
 858                         offset += cinfo->ret.nslots * 8;
 859                         cfg->ret->opcode = OP_REGOFFSET;
 860                         cfg->ret->inst_basereg = cfg->frame_reg;
 861                         cfg->ret->inst_offset = - offset;
 862                         break;
 863                 default:
 864                         g_assert_not_reached ();
 865                 }
 866                 cfg->ret->dreg = cfg->ret->inst_c0;
 867         }
 868
 869         /* Allocate locals */
 870         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 871         if (locals_stack_align) {
 872                 offset = ALIGN_TO (offset, locals_stack_align);
 873         }
 874         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 875                 if (offsets [i] != -1) {
 876                         MonoInst *inst = cfg->varinfo [i];
 877                         inst->opcode = OP_REGOFFSET;
 878                         inst->inst_basereg = cfg->frame_reg;
 879                         if (cfg->arch.omit_fp)
 880                                 inst->inst_offset = (offset + offsets [i]);
 881                         else
 882                                 inst->inst_offset = - (offset + offsets [i]);
 883                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 884                 }
 885         }
 886         offset += locals_stack_size;
 887
 888         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 889                 if (cfg->arch.omit_fp)
 890                         g_assert_not_reached ();
 891                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 892                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 893         }
 894
 895         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 896                 inst = cfg->args [i];
 897                 if (inst->opcode != OP_REGVAR) {
 898                         ArgInfo *ainfo = &cinfo->args [i];
 899                         gboolean inreg = TRUE;
 900                         MonoType *arg_type;
 901
 902                         if (sig->hasthis && (i == 0))
 903                                 arg_type = &mono_defaults.object_class->byval_arg;
 904                         else
 905                                 arg_type = sig->params [i - sig->hasthis];
 906
 907                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 908                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 909                                 inreg = FALSE;
 910
 911                         inst->opcode = OP_REGOFFSET;
 912
 913                         switch (ainfo->storage) {
 914                         case ArgInIReg:
 915                                 inst->opcode = OP_REGVAR;
 916                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 917                                 break;
 918                         case ArgInFloatReg:
 919                         case ArgInFloatRegR4:
 920                                 /*
 921                                  * Since float regs are volatile, we save the arguments to
 922                                  * the stack in the prolog.
 923                                  */
 924                                 inreg = FALSE;
 925                                 break;
 926                         case ArgOnStack:
 927                                 if (cfg->arch.omit_fp)
 928                                         g_assert_not_reached ();
 929                                 inst->opcode = OP_REGOFFSET;
 930                                 inst->inst_basereg = cfg->frame_reg;
 931                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 932                                 break;
 933                         case ArgAggregate:
 934                                 inreg = FALSE;
 935                                 break;
 936                         default:
 937                                 NOT_IMPLEMENTED;
 938                         }
 939
 940                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 941                                 guint32 size = 0;
 942
 943                                 inst->opcode = OP_REGOFFSET;
 944                                 inst->inst_basereg = cfg->frame_reg;
 945                                 /* These arguments are saved to the stack in the prolog */
 946                                 switch (ainfo->storage) {
 947                                 case ArgAggregate:
 948                                         if (ainfo->atype == AggregateSingleHFA)
 949                                                 size = ainfo->nslots * 4;
 950                                         else
 951                                                 size = ainfo->nslots * 8;
 952                                         break;
 953                                 default:
 954                                         size = sizeof (gpointer);
 955                                         break;
 956                                 }
 957
 958                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 959
 960                                 if (cfg->arch.omit_fp) {
 961                                         inst->inst_offset = offset;
 962                                         offset += size;
 963                                 } else {
 964                                         offset += size;
 965                                         inst->inst_offset = - offset;
 966                                 }
 967                         }
 968                 }
 969         }
 970
 971         /*
 972          * FIXME: This doesn't work because some variables are allocated during local
 973          * regalloc.
 974          */
 975         /*
 976         if (cfg->arch.omit_fp && offset == 16)
 977                 offset = 0;
 978         */
 979
 980         cfg->stack_offset = offset;
 981 }
 982
 983 void
 984 mono_arch_create_vars (MonoCompile *cfg)
 985 {
 986         MonoMethodSignature *sig;
 987         CallInfo *cinfo;
 988
 989         sig = mono_method_signature (cfg->method);
 990
 991         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 992
 993         if (cinfo->ret.storage == ArgAggregate)
 994                 cfg->ret_var_is_local = TRUE;
 995         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 996                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 997                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 998                         printf ("vret_addr = ");
 999                         mono_print_ins (cfg->vret_addr);
1000                 }
1001         }
1002 }
1003
1004 static void
1005 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1006 {
1007         MonoInst *arg;
1008
1009         MONO_INST_NEW (cfg, arg, OP_NOP);
1010         arg->sreg1 = tree->dreg;
1011
1012         switch (storage) {
1013         case ArgInIReg:
1014                 arg->opcode = OP_MOVE;
1015                 arg->dreg = mono_alloc_ireg (cfg);
1016
1017                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1018                 break;
1019         case ArgInFloatReg:
1020                 arg->opcode = OP_FMOVE;
1021                 arg->dreg = mono_alloc_freg (cfg);
1022
1023                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1024                 break;
1025         case ArgInFloatRegR4:
1026                 arg->opcode = OP_FCONV_TO_R4;
1027                 arg->dreg = mono_alloc_freg (cfg);
1028
1029                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1030                 break;
1031         default:
1032                 g_assert_not_reached ();
1033         }
1034
1035         MONO_ADD_INS (cfg->cbb, arg);
1036 }
1037
1038 static void
1039 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1040 {
1041         MonoMethodSignature *tmp_sig;
1042
1043         /* Emit the signature cookie just before the implicit arguments */
1044         MonoInst *sig_arg;
1045         /* FIXME: Add support for signature tokens to AOT */
1046         cfg->disable_aot = TRUE;
1047
1048         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1049
1050         /*
1051          * mono_ArgIterator_Setup assumes the signature cookie is
1052          * passed first and all the arguments which were before it are
1053          * passed on the stack after the signature. So compensate by
1054          * passing a different signature.
1055          */
1056         tmp_sig = mono_metadata_signature_dup (call->signature);
1057         tmp_sig->param_count -= call->signature->sentinelpos;
1058         tmp_sig->sentinelpos = 0;
1059         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1060
1061         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1062         sig_arg->dreg = mono_alloc_ireg (cfg);
1063         sig_arg->inst_p0 = tmp_sig;
1064         MONO_ADD_INS (cfg->cbb, sig_arg);
1065
1066         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1067 }
1068
1069 void
1070 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1071 {
1072         MonoInst *in;
1073         MonoMethodSignature *sig;
1074         int i, n, stack_size;
1075         CallInfo *cinfo;
1076         ArgInfo *ainfo;
1077
1078         stack_size = 0;
1079
1080         mono_ia64_alloc_stacked_registers (cfg);
1081
1082         sig = call->signature;
1083         n = sig->param_count + sig->hasthis;
1084
1085         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1086
1087         if (cinfo->ret.storage == ArgAggregate) {
1088                 MonoInst *vtarg;
1089                 MonoInst *local;
1090
1091                 /*
1092                  * The valuetype is in registers after the call, need to be copied
1093                  * to the stack. Save the address to a local here, so the call
1094                  * instruction can access it.
1095                  */
1096                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1097                 local->flags |= MONO_INST_VOLATILE;
1098                 cfg->arch.ret_var_addr_local = local;
1099
1100                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1101                 vtarg->sreg1 = call->vret_var->dreg;
1102                 vtarg->dreg = local->dreg;
1103                 MONO_ADD_INS (cfg->cbb, vtarg);
1104         }
1105
1106         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1107                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1108         }
1109
1110         for (i = 0; i < n; ++i) {
1111                 MonoType *arg_type;
1112
1113                 ainfo = cinfo->args + i;
1114
1115                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1116                         /* Emit the signature cookie just before the implicit arguments */
1117                         emit_sig_cookie (cfg, call, cinfo);
1118                 }
1119
1120                 in = call->args [i];
1121
1122                 if (sig->hasthis && (i == 0))
1123                         arg_type = &mono_defaults.object_class->byval_arg;
1124                 else
1125                         arg_type = sig->params [i - sig->hasthis];
1126
1127                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1128                         guint32 align;
1129                         guint32 size;
1130
1131                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1132                                 size = sizeof (MonoTypedRef);
1133                                 align = sizeof (gpointer);
1134                         }
1135                         else if (sig->pinvoke)
1136                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1137                         else {
1138                                 /*
1139                                  * Other backends use mono_type_stack_size (), but that
1140                                  * aligns the size to 8, which is larger than the size of
1141                                  * the source, leading to reads of invalid memory if the
1142                                  * source is at the end of address space.
1143                                  */
1144                                 size = mono_class_value_size (in->klass, &align);
1145                         }
1146
1147                         if (size > 0) {
1148                                 MonoInst *arg;
1149
1150                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1151                                 arg->sreg1 = in->dreg;
1152                                 arg->klass = in->klass;
1153                                 arg->backend.size = size;
1154                                 arg->inst_p0 = call;
1155                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1156                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1157
1158                                 MONO_ADD_INS (cfg->cbb, arg);
1159                         }
1160                 }
1161                 else {
1162                         switch (ainfo->storage) {
1163                         case ArgInIReg:
1164                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1165                                 break;
1166                         case ArgInFloatReg:
1167                         case ArgInFloatRegR4:
1168                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1169                                 break;
1170                         case ArgOnStack:
1171                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1172                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1173                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1174                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1175                                 else
1176                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1177                                 break;
1178                         default:
1179                                 g_assert_not_reached ();
1180                         }
1181                 }
1182         }
1183
1184         /* Handle the case where there are no implicit arguments */
1185         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1186                 emit_sig_cookie (cfg, call, cinfo);
1187         }
1188
1189         call->stack_usage = cinfo->stack_usage;
1190         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1191 }
1192
1193 void
1194 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1195 {
1196         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1197         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1198         int size = ins->backend.size;
1199
1200         if (ainfo->storage == ArgAggregate) {
1201                 MonoInst *load, *store;
1202                 int i, slot;
1203
1204                 /*
1205                  * Part of the structure is passed in registers.
1206                  */
1207                 for (i = 0; i < ainfo->nregs; ++i) {
1208                         slot = ainfo->reg + i;
1209
1210                         if (ainfo->atype == AggregateSingleHFA) {
1211                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1212                                 load->inst_basereg = src->dreg;
1213                                 load->inst_offset = i * 4;
1214                                 load->dreg = mono_alloc_freg (cfg);
1215
1216                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1217                         } else if (ainfo->atype == AggregateDoubleHFA) {
1218                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1219                                 load->inst_basereg = src->dreg;
1220                                 load->inst_offset = i * 8;
1221                                 load->dreg = mono_alloc_freg (cfg);
1222
1223                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1224                         } else {
1225                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1226                                 load->inst_basereg = src->dreg;
1227                                 load->inst_offset = i * 8;
1228                                 load->dreg = mono_alloc_ireg (cfg);
1229
1230                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1231                         }
1232                         MONO_ADD_INS (cfg->cbb, load);
1233                 }
1234
1235                 /*
1236                  * Part of the structure is passed on the stack.
1237                  */
1238                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1239                         slot = ainfo->reg + i;
1240
1241                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1242                         load->inst_basereg = src->dreg;
1243                         load->inst_offset = i * sizeof (gpointer);
1244                         load->dreg = mono_alloc_preg (cfg);
1245                         MONO_ADD_INS (cfg->cbb, load);
1246
1247                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1248                         store->sreg1 = load->dreg;
1249                         store->inst_destbasereg = IA64_SP;
1250                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1251                         MONO_ADD_INS (cfg->cbb, store);
1252                 }
1253         } else {
1254                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1255         }
1256 }
1257
1258 void
1259 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1260 {
1261         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1262
1263         switch (cinfo->ret.storage) {
1264         case ArgInIReg:
1265                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1266                 break;
1267         case ArgInFloatReg:
1268                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1269                 break;
1270         default:
1271                 g_assert_not_reached ();
1272         }
1273 }
1274
1275 void
1276 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1277 {
1278 }
1279
1280 void
1281 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1282 {
1283         MonoInst *ins, *n, *last_ins = NULL;
1284         ins = bb->code;
1285
1286         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1287                 switch (ins->opcode) {
1288                 case OP_MOVE:
1289                 case OP_FMOVE:
1290                         /*
1291                          * Removes:
1292                          *
1293                          * OP_MOVE reg, reg
1294                          */
1295                         if (ins->dreg == ins->sreg1) {
1296                                 MONO_DELETE_INS (bb, ins);
1297                                 continue;
1298                         }
1299                         /*
1300                          * Removes:
1301                          *
1302                          * OP_MOVE sreg, dreg
1303                          * OP_MOVE dreg, sreg
1304                          */
1305                         if (last_ins && last_ins->opcode == OP_MOVE &&
1306                             ins->sreg1 == last_ins->dreg &&
1307                             ins->dreg == last_ins->sreg1) {
1308                                 MONO_DELETE_INS (bb, ins);
1309                                 continue;
1310                         }
1311                         break;
1312                 case OP_MUL_IMM:
1313                 case OP_IMUL_IMM:
1314                         /* remove unnecessary multiplication with 1 */
1315                         if (ins->inst_imm == 1) {
1316                                 if (ins->dreg != ins->sreg1) {
1317                                         ins->opcode = OP_MOVE;
1318                                 } else {
1319                                         MONO_DELETE_INS (bb, ins);
1320                                         continue;
1321                                 }
1322                         }
1323                         break;
1324                 }
1325
1326                 last_ins = ins;
1327                 ins = ins->next;
1328         }
1329         bb->last_ins = last_ins;
1330 }
1331
1332 int cond_to_ia64_cmp [][3] = {
1333         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1334         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1335         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1336         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1337         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1338         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1339         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1340         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1341         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1342         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1343 };
1344
1345 static int
1346 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1347 {
1348         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1349 }
1350
1351 int cond_to_ia64_cmp_imm [][3] = {
1352         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1353         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1354         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1355         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1356         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1357         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1358         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1359         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1360         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1361         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1362 };
1363
1364 static int
1365 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1366 {
1367         /* The condition needs to be reversed */
1368         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1369 }
1370
1371 #define NEW_INS(cfg,dest,op) do {       \
1372                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1373                 (dest)->opcode = (op);  \
1374         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1375         last_ins = (dest); \
1376         } while (0)
1377
1378 /*
1379  * mono_arch_lowering_pass:
1380  *
1381  *  Converts complex opcodes into simpler ones so that each IR instruction
1382  * corresponds to one machine instruction.
1383  */
1384 void
1385 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1386 {
1387         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1388         ins = bb->code;
1389
1390         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1391                 switch (ins->opcode) {
1392                 case OP_STOREI1_MEMBASE_IMM:
1393                 case OP_STOREI2_MEMBASE_IMM:
1394                 case OP_STOREI4_MEMBASE_IMM:
1395                 case OP_STOREI8_MEMBASE_IMM:
1396                 case OP_STORE_MEMBASE_IMM:
1397                         /* There are no store_membase instructions on ia64 */
1398                         if (ins->inst_offset == 0) {
1399                                 temp2 = NULL;
1400                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1401                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1402                                 temp2->sreg1 = ins->inst_destbasereg;
1403                                 temp2->inst_imm = ins->inst_offset;
1404                                 temp2->dreg = mono_alloc_ireg (cfg);
1405                         }
1406                         else {
1407                                 NEW_INS (cfg, temp, OP_I8CONST);
1408                                 temp->inst_c0 = ins->inst_offset;
1409                                 temp->dreg = mono_alloc_ireg (cfg);
1410
1411                                 NEW_INS (cfg, temp2, OP_LADD);
1412                                 temp2->sreg1 = ins->inst_destbasereg;
1413                                 temp2->sreg2 = temp->dreg;
1414                                 temp2->dreg = mono_alloc_ireg (cfg);
1415                         }
1416
1417                         switch (ins->opcode) {
1418                         case OP_STOREI1_MEMBASE_IMM:
1419                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1420                                 break;
1421                         case OP_STOREI2_MEMBASE_IMM:
1422                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1423                                 break;
1424                         case OP_STOREI4_MEMBASE_IMM:
1425                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1426                                 break;
1427                         case OP_STOREI8_MEMBASE_IMM:
1428                         case OP_STORE_MEMBASE_IMM:
1429                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1430                                 break;
1431                         default:
1432                                 g_assert_not_reached ();
1433                         }
1434
1435                         if (ins->inst_imm == 0)
1436                                 ins->sreg1 = IA64_R0;
1437                         else {
1438                                 NEW_INS (cfg, temp3, OP_I8CONST);
1439                                 temp3->inst_c0 = ins->inst_imm;
1440                                 temp3->dreg = mono_alloc_ireg (cfg);
1441                                 ins->sreg1 = temp3->dreg;
1442                         }
1443
1444                         ins->inst_offset = 0;
1445                         if (temp2)
1446                                 ins->inst_destbasereg = temp2->dreg;
1447                         break;
1448                 case OP_STOREI1_MEMBASE_REG:
1449                 case OP_STOREI2_MEMBASE_REG:
1450                 case OP_STOREI4_MEMBASE_REG:
1451                 case OP_STOREI8_MEMBASE_REG:
1452                 case OP_STORER4_MEMBASE_REG:
1453                 case OP_STORER8_MEMBASE_REG:
1454                 case OP_STORE_MEMBASE_REG:
1455                         /* There are no store_membase instructions on ia64 */
1456                         if (ins->inst_offset == 0) {
1457                                 break;
1458                         }
1459                         else if (ia64_is_imm14 (ins->inst_offset)) {
1460                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1461                                 temp2->sreg1 = ins->inst_destbasereg;
1462                                 temp2->inst_imm = ins->inst_offset;
1463                                 temp2->dreg = mono_alloc_ireg (cfg);
1464                         }
1465                         else {
1466                                 NEW_INS (cfg, temp, OP_I8CONST);
1467                                 temp->inst_c0 = ins->inst_offset;
1468                                 temp->dreg = mono_alloc_ireg (cfg);
1469                                 NEW_INS (cfg, temp2, OP_LADD);
1470                                 temp2->sreg1 = ins->inst_destbasereg;
1471                                 temp2->sreg2 = temp->dreg;
1472                                 temp2->dreg = mono_alloc_ireg (cfg);
1473                         }
1474
1475                         ins->inst_offset = 0;
1476                         ins->inst_destbasereg = temp2->dreg;
1477                         break;
1478                 case OP_LOADI1_MEMBASE:
1479                 case OP_LOADU1_MEMBASE:
1480                 case OP_LOADI2_MEMBASE:
1481                 case OP_LOADU2_MEMBASE:
1482                 case OP_LOADI4_MEMBASE:
1483                 case OP_LOADU4_MEMBASE:
1484                 case OP_LOADI8_MEMBASE:
1485                 case OP_LOAD_MEMBASE:
1486                 case OP_LOADR4_MEMBASE:
1487                 case OP_LOADR8_MEMBASE:
1488                 case OP_ATOMIC_EXCHANGE_I4:
1489                 case OP_ATOMIC_EXCHANGE_I8:
1490                 case OP_ATOMIC_ADD_NEW_I4:
1491                 case OP_ATOMIC_ADD_NEW_I8:
1492                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1493                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1494                         /* There are no membase instructions on ia64 */
1495                         if (ins->inst_offset == 0) {
1496                                 break;
1497                         }
1498                         else if (ia64_is_imm14 (ins->inst_offset)) {
1499                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1500                                 temp2->sreg1 = ins->inst_basereg;
1501                                 temp2->inst_imm = ins->inst_offset;
1502                                 temp2->dreg = mono_alloc_ireg (cfg);
1503                         }
1504                         else {
1505                                 NEW_INS (cfg, temp, OP_I8CONST);
1506                                 temp->inst_c0 = ins->inst_offset;
1507                                 temp->dreg = mono_alloc_ireg (cfg);
1508                                 NEW_INS (cfg, temp2, OP_LADD);
1509                                 temp2->sreg1 = ins->inst_basereg;
1510                                 temp2->sreg2 = temp->dreg;
1511                                 temp2->dreg = mono_alloc_ireg (cfg);
1512                         }
1513
1514                         ins->inst_offset = 0;
1515                         ins->inst_basereg = temp2->dreg;
1516                         break;
1517                 case OP_ADD_IMM:
1518                 case OP_IADD_IMM:
1519                 case OP_LADD_IMM:
1520                 case OP_ISUB_IMM:
1521                 case OP_LSUB_IMM:
1522                 case OP_AND_IMM:
1523                 case OP_IAND_IMM:
1524                 case OP_LAND_IMM:
1525                 case OP_IOR_IMM:
1526                 case OP_LOR_IMM:
1527                 case OP_IXOR_IMM:
1528                 case OP_LXOR_IMM:
1529                 case OP_SHL_IMM:
1530                 case OP_SHR_IMM:
1531                 case OP_ISHL_IMM:
1532                 case OP_LSHL_IMM:
1533                 case OP_ISHR_IMM:
1534                 case OP_LSHR_IMM:
1535                 case OP_ISHR_UN_IMM:
1536                 case OP_LSHR_UN_IMM: {
1537                         gboolean is_imm = FALSE;
1538                         gboolean switched = FALSE;
1539
1540                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1541                                 ins->opcode = OP_ZEXT_I1;
1542                                 break;
1543                         }
1544
1545                         switch (ins->opcode) {
1546                         case OP_ADD_IMM:
1547                         case OP_IADD_IMM:
1548                         case OP_LADD_IMM:
1549                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1550                                 switched = TRUE;
1551                                 break;
1552                         case OP_ISUB_IMM:
1553                         case OP_LSUB_IMM:
1554                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1555                                 if (is_imm) {
1556                                         /* A = B - IMM -> A = B + (-IMM) */
1557                                         ins->inst_imm = - ins->inst_imm;
1558                                         ins->opcode = OP_IADD_IMM;
1559                                 }
1560                                 switched = TRUE;
1561                                 break;
1562                         case OP_IAND_IMM:
1563                         case OP_IOR_IMM:
1564                         case OP_IXOR_IMM:
1565                         case OP_AND_IMM:
1566                         case OP_LAND_IMM:
1567                         case OP_LOR_IMM:
1568                         case OP_LXOR_IMM:
1569                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1570                                 switched = TRUE;
1571                                 break;
1572                         case OP_SHL_IMM:
1573                         case OP_SHR_IMM:
1574                         case OP_ISHL_IMM:
1575                         case OP_LSHL_IMM:
1576                         case OP_ISHR_IMM:
1577                         case OP_LSHR_IMM:
1578                         case OP_ISHR_UN_IMM:
1579                         case OP_LSHR_UN_IMM:
1580                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1581                                 break;
1582                         default:
1583                                 break;
1584                         }
1585
1586                         if (is_imm) {
1587                                 if (switched)
1588                                         ins->sreg2 = ins->sreg1;
1589                                 break;
1590                         }
1591
1592                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1593
1594                         if (ins->inst_imm == 0)
1595                                 ins->sreg2 = IA64_R0;
1596                         else {
1597                                 NEW_INS (cfg, temp, OP_I8CONST);
1598                                 temp->inst_c0 = ins->inst_imm;
1599                                 temp->dreg = mono_alloc_ireg (cfg);
1600                                 ins->sreg2 = temp->dreg;
1601                         }
1602                         break;
1603                 }
1604                 case OP_COMPARE_IMM:
1605                 case OP_ICOMPARE_IMM:
1606                 case OP_LCOMPARE_IMM: {
1607                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1608                         gboolean imm;
1609                         CompRelation cond;
1610
1611                         next = ins->next;
1612
1613                         /* Branch opts can eliminate the branch */
1614                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1615                                 NULLIFY_INS (ins);
1616                                 break;
1617                         }
1618
1619                         /*
1620                          * The compare_imm instructions have switched up arguments, and
1621                          * some of them take an imm between -127 and 128.
1622                          */
1623                         next = ins->next;
1624                         cond = mono_opcode_to_cond (next->opcode);
1625                         if ((cond == CMP_LT) || (cond == CMP_GE))
1626                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1627                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1628                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1629                         else
1630                                 imm = ia64_is_imm8 (ins->inst_imm);
1631
1632                         if (imm) {
1633                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1634                                 ins->sreg2 = ins->sreg1;
1635                         }
1636                         else {
1637                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1638
1639                                 if (ins->inst_imm == 0)
1640                                         ins->sreg2 = IA64_R0;
1641                                 else {
1642                                         NEW_INS (cfg, temp, OP_I8CONST);
1643                                         temp->inst_c0 = ins->inst_imm;
1644                                         temp->dreg = mono_alloc_ireg (cfg);
1645                                         ins->sreg2 = temp->dreg;
1646                                 }
1647                         }
1648
1649                         if (MONO_IS_COND_BRANCH_OP (next)) {
1650                                 next->opcode = OP_IA64_BR_COND;
1651                                 next->inst_target_bb = next->inst_true_bb;
1652                         } else if (MONO_IS_COND_EXC (next)) {
1653                                 next->opcode = OP_IA64_COND_EXC;
1654                         } else if (MONO_IS_SETCC (next)) {
1655                                 next->opcode = OP_IA64_CSET;
1656                         } else {
1657                                 printf ("%s\n", mono_inst_name (next->opcode));
1658                                 NOT_IMPLEMENTED;
1659                         }
1660
1661                         break;
1662                 }
1663                 case OP_COMPARE:
1664                 case OP_ICOMPARE:
1665                 case OP_LCOMPARE:
1666                 case OP_FCOMPARE: {
1667                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1668
1669                         next = ins->next;
1670
1671                         /* Branch opts can eliminate the branch */
1672                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1673                                 NULLIFY_INS (ins);
1674                                 break;
1675                         }
1676
1677                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1678
1679                         if (MONO_IS_COND_BRANCH_OP (next)) {
1680                                 next->opcode = OP_IA64_BR_COND;
1681                                 next->inst_target_bb = next->inst_true_bb;
1682                         } else if (MONO_IS_COND_EXC (next)) {
1683                                 next->opcode = OP_IA64_COND_EXC;
1684                         } else if (MONO_IS_SETCC (next)) {
1685                                 next->opcode = OP_IA64_CSET;
1686                         } else {
1687                                 printf ("%s\n", mono_inst_name (next->opcode));
1688                                 NOT_IMPLEMENTED;
1689                         }
1690
1691                         break;
1692                 }
1693                 case OP_FCEQ:
1694                 case OP_FCGT:
1695                 case OP_FCGT_UN:
1696                 case OP_FCLT:
1697                 case OP_FCLT_UN:
1698                         /* The front end removes the fcompare, so introduce it again */
1699                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1700                         temp->sreg1 = ins->sreg1;
1701                         temp->sreg2 = ins->sreg2;
1702
1703                         ins->opcode = OP_IA64_CSET;
1704                         MONO_INST_NULLIFY_SREGS (ins);
1705                         break;
1706                 case OP_MUL_IMM:
1707                 case OP_LMUL_IMM:
1708                 case OP_IMUL_IMM: {
1709                         int i, sum_reg;
1710                         gboolean found = FALSE;
1711                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1712
1713                         /* First the easy cases */
1714                         if (ins->inst_imm == 1) {
1715                                 ins->opcode = OP_MOVE;
1716                                 break;
1717                         }
1718                         for (i = 1; i < 64; ++i)
1719                                 if (ins->inst_imm == (((gint64)1) << i)) {
1720                                         ins->opcode = shl_op;
1721                                         ins->inst_imm = i;
1722                                         found = TRUE;
1723                                         break;
1724                                 }
1725
1726                         /* This could be optimized */
1727                         if (!found) {
1728                                 sum_reg = 0;
1729                                 for (i = 0; i < 64; ++i) {
1730                                         if (ins->inst_imm & (((gint64)1) << i)) {
1731                                                 NEW_INS (cfg, temp, shl_op);
1732                                                 temp->dreg = mono_alloc_ireg (cfg);
1733                                                 temp->sreg1 = ins->sreg1;
1734                                                 temp->inst_imm = i;
1735
1736                                                 if (sum_reg == 0)
1737                                                         sum_reg = temp->dreg;
1738                                                 else {
1739                                                         NEW_INS (cfg, temp2, OP_LADD);
1740                                                         temp2->dreg = mono_alloc_ireg (cfg);
1741                                                         temp2->sreg1 = sum_reg;
1742                                                         temp2->sreg2 = temp->dreg;
1743                                                         sum_reg = temp2->dreg;
1744                                                 }
1745                                         }
1746                                 }
1747                                 ins->opcode = OP_MOVE;
1748                                 ins->sreg1 = sum_reg;
1749                         }
1750                         break;
1751                 }
1752                 case OP_LCONV_TO_OVF_U4:
1753                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1754                         temp->sreg1 = ins->sreg1;
1755                         temp->sreg2 = IA64_R0;
1756
1757                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1758                         temp->inst_p1 = (char*)"OverflowException";
1759
1760                         ins->opcode = OP_MOVE;
1761                         break;
1762                 case OP_LCONV_TO_OVF_I4_UN:
1763                         NEW_INS (cfg, temp, OP_ICONST);
1764                         temp->inst_c0 = 0x7fffffff;
1765                         temp->dreg = mono_alloc_ireg (cfg);
1766
1767                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1768                         temp2->sreg1 = ins->sreg1;
1769                         temp2->sreg2 = temp->dreg;
1770
1771                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1772                         temp->inst_p1 = (char*)"OverflowException";
1773
1774                         ins->opcode = OP_MOVE;
1775                         break;
1776                 case OP_FCONV_TO_I4:
1777                 case OP_FCONV_TO_I2:
1778                 case OP_FCONV_TO_U2:
1779                 case OP_FCONV_TO_I1:
1780                 case OP_FCONV_TO_U1:
1781                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1782                         temp->sreg1 = ins->sreg1;
1783                         temp->dreg = ins->dreg;
1784
1785                         switch (ins->opcode) {
1786                         case OP_FCONV_TO_I4:
1787                                 ins->opcode = OP_SEXT_I4;
1788                                 break;
1789                         case OP_FCONV_TO_I2:
1790                                 ins->opcode = OP_SEXT_I2;
1791                                 break;
1792                         case OP_FCONV_TO_U2:
1793                                 ins->opcode = OP_ZEXT_I4;
1794                                 break;
1795                         case OP_FCONV_TO_I1:
1796                                 ins->opcode = OP_SEXT_I1;
1797                                 break;
1798                         case OP_FCONV_TO_U1:
1799                                 ins->opcode = OP_ZEXT_I1;
1800                                 break;
1801                         default:
1802                                 g_assert_not_reached ();
1803                         }
1804                         ins->sreg1 = ins->dreg;
1805                         break;
1806                 default:
1807                         break;
1808                 }
1809                 last_ins = ins;
1810                 ins = ins->next;
1811         }
1812         bb->last_ins = last_ins;
1813
1814         bb->max_vreg = cfg->next_vreg;
1815 }
1816
1817 /*
1818  * emit_load_volatile_arguments:
1819  *
1820  *  Load volatile arguments from the stack to the original input registers.
1821  * Required before a tail call.
1822  */
1823 static Ia64CodegenState
1824 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1825 {
1826         MonoMethod *method = cfg->method;
1827         MonoMethodSignature *sig;
1828         MonoInst *ins;
1829         CallInfo *cinfo;
1830         guint32 i;
1831
1832         /* FIXME: Generate intermediate code instead */
1833
1834         sig = mono_method_signature (method);
1835
1836         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1837
1838         /* This is the opposite of the code in emit_prolog */
1839         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1840                 ArgInfo *ainfo = cinfo->args + i;
1841                 gint32 stack_offset;
1842                 MonoType *arg_type;
1843
1844                 ins = cfg->args [i];
1845
1846                 if (sig->hasthis && (i == 0))
1847                         arg_type = &mono_defaults.object_class->byval_arg;
1848                 else
1849                         arg_type = sig->params [i - sig->hasthis];
1850
1851                 arg_type = mono_type_get_underlying_type (arg_type);
1852
1853                 stack_offset = ainfo->offset + ARGS_OFFSET;
1854
1855                 /* Save volatile arguments to the stack */
1856                 if (ins->opcode != OP_REGVAR) {
1857                         switch (ainfo->storage) {
1858                         case ArgInIReg:
1859                         case ArgInFloatReg:
1860                                 /* FIXME: big offsets */
1861                                 g_assert (ins->opcode == OP_REGOFFSET);
1862                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1863                                 if (arg_type->byref)
1864                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1865                                 else {
1866                                         switch (arg_type->type) {
1867                                         case MONO_TYPE_R4:
1868                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1869                                                 break;
1870                                         case MONO_TYPE_R8:
1871                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1872                                                 break;
1873                                         default:
1874                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1875                                                 break;
1876                                         }
1877                                 }
1878                                 break;
1879                         case ArgOnStack:
1880                                 break;
1881                         default:
1882                                 NOT_IMPLEMENTED;
1883                         }
1884                 }
1885
1886                 if (ins->opcode == OP_REGVAR) {
1887                         /* Argument allocated to (non-volatile) register */
1888                         switch (ainfo->storage) {
1889                         case ArgInIReg:
1890                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1891                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1892                                 break;
1893                         case ArgOnStack:
1894                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1895                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1896                                 break;
1897                         default:
1898                                 NOT_IMPLEMENTED;
1899                         }
1900                 }
1901         }
1902
1903         return code;
1904 }
1905
1906 static Ia64CodegenState
1907 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1908 {
1909         CallInfo *cinfo;
1910         int i;
1911
1912         /* Move return value to the target register */
1913         switch (ins->opcode) {
1914         case OP_VOIDCALL:
1915         case OP_VOIDCALL_REG:
1916         case OP_VOIDCALL_MEMBASE:
1917                 break;
1918         case OP_CALL:
1919         case OP_CALL_REG:
1920         case OP_CALL_MEMBASE:
1921         case OP_LCALL:
1922         case OP_LCALL_REG:
1923         case OP_LCALL_MEMBASE:
1924                 g_assert (ins->dreg == IA64_R8);
1925                 break;
1926         case OP_FCALL:
1927         case OP_FCALL_REG:
1928         case OP_FCALL_MEMBASE:
1929                 g_assert (ins->dreg == 8);
1930                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1931                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1932                 break;
1933         case OP_VCALL:
1934         case OP_VCALL_REG:
1935         case OP_VCALL_MEMBASE:
1936         case OP_VCALL2:
1937         case OP_VCALL2_REG:
1938         case OP_VCALL2_MEMBASE: {
1939                 ArgStorage storage;
1940
1941                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1942                 storage = cinfo->ret.storage;
1943
1944                 if (storage == ArgAggregate) {
1945                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1946
1947                         /* Load address of stack space allocated for the return value */
1948                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1949                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1950                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1951
1952                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1953                                 switch (cinfo->ret.atype) {
1954                                 case AggregateNormal:
1955                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1956                                         break;
1957                                 case AggregateSingleHFA:
1958                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1959                                         break;
1960                                 case AggregateDoubleHFA:
1961                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1962                                         break;
1963                                 default:
1964                                         g_assert_not_reached ();
1965                                 }
1966                         }
1967                 }
1968                 break;
1969         }
1970         default:
1971                 g_assert_not_reached ();
1972         }
1973
1974         return code;
1975 }
1976
1977 #define add_patch_info(cfg,code,patch_type,data) do { \
1978         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1979 } while (0)
1980
1981 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1982         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1983     if (tins == NULL) \
1984         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1985     else \
1986                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1987         ia64_br_cond_pred (code, (predicate), 0); \
1988 } while (0)
1989
1990 static Ia64CodegenState
1991 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1992 {
1993         add_patch_info (cfg, code, patch_type, data);
1994
1995         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1996                 /* Indirect call */
1997                 /* mono_arch_patch_callsite will patch this */
1998                 /* mono_arch_nullify_class_init_trampoline will patch this */
1999                 ia64_movl (code, GP_SCRATCH_REG, 0);
2000                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
2001                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2002                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2003                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2004         }
2005         else {
2006                 /* Can't use a direct call since the displacement might be too small */
2007                 /* mono_arch_patch_callsite will patch this */
2008                 ia64_movl (code, GP_SCRATCH_REG, 0);
2009                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2010                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2011         }
2012
2013         return code;
2014 }
2015
2016 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2017
2018 void
2019 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2020 {
2021         MonoInst *ins;
2022         MonoCallInst *call;
2023         guint offset;
2024         Ia64CodegenState code;
2025         guint8 *code_start = cfg->native_code + cfg->code_len;
2026         MonoInst *last_ins = NULL;
2027         guint last_offset = 0;
2028         int max_len, cpos;
2029
2030         if (cfg->opt & MONO_OPT_LOOP) {
2031                 /* FIXME: */
2032         }
2033
2034         if (cfg->verbose_level > 2)
2035                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2036
2037         cpos = bb->max_offset;
2038
2039         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2040                 NOT_IMPLEMENTED;
2041         }
2042
2043         offset = code_start - cfg->native_code;
2044
2045         ia64_codegen_init (code, code_start);
2046
2047 #if 0
2048         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2049                 break_count ();
2050 #endif
2051
2052         MONO_BB_FOR_EACH_INS (bb, ins) {
2053                 offset = code.buf - cfg->native_code;
2054
2055                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2056
2057                 while (offset + max_len + 16 > cfg->code_size) {
2058                         ia64_codegen_close (code);
2059
2060                         offset = code.buf - cfg->native_code;
2061
2062                         cfg->code_size *= 2;
2063                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2064                         code_start = cfg->native_code + offset;
2065                         cfg->stat_code_reallocs++;
2066
2067                         ia64_codegen_init (code, code_start);
2068                 }
2069
2070                 mono_debug_record_line_number (cfg, ins, offset);
2071
2072                 switch (ins->opcode) {
2073                 case OP_ICONST:
2074                 case OP_I8CONST:
2075                         if (ia64_is_imm14 (ins->inst_c0))
2076                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2077                         else
2078                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2079                         break;
2080                 case OP_JUMP_TABLE:
2081                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2082                         ia64_movl (code, ins->dreg, 0);
2083                         break;
2084                 case OP_MOVE:
2085                         ia64_mov (code, ins->dreg, ins->sreg1);
2086                         break;
2087                 case OP_BR:
2088                 case OP_IA64_BR_COND: {
2089                         int pred = 0;
2090                         if (ins->opcode == OP_IA64_BR_COND)
2091                                 pred = 6;
2092                         if (ins->inst_target_bb->native_offset) {
2093                                 guint8 *pos = code.buf + code.nins;
2094
2095                                 ia64_br_cond_pred (code, pred, 0);
2096                                 ia64_begin_bundle (code);
2097                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2098                         } else {
2099                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2100                                 ia64_br_cond_pred (code, pred, 0);
2101                         }
2102                         break;
2103                 }
2104                 case OP_LABEL:
2105                         ia64_begin_bundle (code);
2106                         ins->inst_c0 = code.buf - cfg->native_code;
2107                         break;
2108                 case OP_NOP:
2109                 case OP_RELAXED_NOP:
2110                 case OP_DUMMY_USE:
2111                 case OP_DUMMY_STORE:
2112                 case OP_NOT_REACHED:
2113                 case OP_NOT_NULL:
2114                         break;
2115                 case OP_BR_REG:
2116                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2117                         ia64_br_cond_reg (code, IA64_B6);
2118                         break;
2119                 case OP_IADD:
2120                 case OP_LADD:
2121                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2122                         break;
2123                 case OP_ISUB:
2124                 case OP_LSUB:
2125                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2126                         break;
2127                 case OP_IAND:
2128                 case OP_LAND:
2129                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2130                         break;
2131                 case OP_IOR:
2132                 case OP_LOR:
2133                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2134                         break;
2135                 case OP_IXOR:
2136                 case OP_LXOR:
2137                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2138                         break;
2139                 case OP_INEG:
2140                 case OP_LNEG:
2141                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2142                         break;
2143                 case OP_INOT:
2144                 case OP_LNOT:
2145                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2146                         break;
2147                 case OP_ISHL:
2148                 case OP_LSHL:
2149                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2150                         break;
2151                 case OP_ISHR:
2152                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2153                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2154                         break;
2155                 case OP_LSHR:
2156                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2157                         break;
2158                 case OP_ISHR_UN:
2159                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2160                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2161                         break;
2162                 case OP_LSHR_UN:
2163                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2164                         break;
2165                 case OP_IADDCC:
2166                         /* p6 and p7 is set if there is signed/unsigned overflow */
2167
2168                         /* Set p8-p9 == (sreg2 > 0) */
2169                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2170
2171                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2172
2173                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2174                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2175                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2176                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2177
2178                         /* res <u sreg1 => unsigned overflow */
2179                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2180
2181                         /* FIXME: Predicate this since this is a side effect */
2182                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2183                         break;
2184                 case OP_ISUBCC:
2185                         /* p6 and p7 is set if there is signed/unsigned overflow */
2186
2187                         /* Set p8-p9 == (sreg2 > 0) */
2188                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2189
2190                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2191
2192                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2193                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2194                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2195                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2196
2197                         /* sreg1 <u sreg2 => unsigned overflow */
2198                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2199
2200                         /* FIXME: Predicate this since this is a side effect */
2201                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2202                         break;
2203                 case OP_ADDCC:
2204                         /* Same as OP_IADDCC */
2205                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2206
2207                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2208
2209                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2210                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2211
2212                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2213
2214                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2215                         break;
2216                 case OP_SUBCC:
2217                         /* Same as OP_ISUBCC */
2218
2219                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2220
2221                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2222
2223                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2224                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2225
2226                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2227
2228                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2229                         break;
2230                 case OP_ADD_IMM:
2231                 case OP_IADD_IMM:
2232                 case OP_LADD_IMM:
2233                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2234                         break;
2235                 case OP_IAND_IMM:
2236                 case OP_AND_IMM:
2237                 case OP_LAND_IMM:
2238                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2239                         break;
2240                 case OP_IOR_IMM:
2241                 case OP_LOR_IMM:
2242                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2243                         break;
2244                 case OP_IXOR_IMM:
2245                 case OP_LXOR_IMM:
2246                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2247                         break;
2248                 case OP_SHL_IMM:
2249                 case OP_ISHL_IMM:
2250                 case OP_LSHL_IMM:
2251                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2252                         break;
2253                 case OP_SHR_IMM:
2254                 case OP_LSHR_IMM:
2255                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2256                         break;
2257                 case OP_ISHR_IMM:
2258                         g_assert (ins->inst_imm <= 64);
2259                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2260                         break;
2261                 case OP_ISHR_UN_IMM:
2262                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2263                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2264                         break;
2265                 case OP_LSHR_UN_IMM:
2266                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2267                         break;
2268                 case OP_LMUL:
2269                         /* Based on gcc code */
2270                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2271                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2272                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2273                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2274                         break;
2275
2276                 case OP_STOREI1_MEMBASE_REG:
2277                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2278                         break;
2279                 case OP_STOREI2_MEMBASE_REG:
2280                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2281                         break;
2282                 case OP_STOREI4_MEMBASE_REG:
2283                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2284                         break;
2285                 case OP_STOREI8_MEMBASE_REG:
2286                 case OP_STORE_MEMBASE_REG:
2287                         if (ins->inst_offset != 0) {
2288                                 /* This is generated by local regalloc */
2289                                 if (ia64_is_imm14 (ins->inst_offset)) {
2290                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2291                                 } else {
2292                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2293                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2294                                 }
2295                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2296                         }
2297                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2298                         break;
2299
2300                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2301                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2302                         break;
2303                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2304                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2305                         break;
2306                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2307                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2308                         break;
2309                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2310                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2311                         break;
2312
2313                 case OP_LOADU1_MEMBASE:
2314                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2315                         break;
2316                 case OP_LOADU2_MEMBASE:
2317                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2318                         break;
2319                 case OP_LOADU4_MEMBASE:
2320                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2321                         break;
2322                 case OP_LOADI1_MEMBASE:
2323                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2324                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2325                         break;
2326                 case OP_LOADI2_MEMBASE:
2327                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2328                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2329                         break;
2330                 case OP_LOADI4_MEMBASE:
2331                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2332                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2333                         break;
2334                 case OP_LOAD_MEMBASE:
2335                 case OP_LOADI8_MEMBASE:
2336                         if (ins->inst_offset != 0) {
2337                                 /* This is generated by local regalloc */
2338                                 if (ia64_is_imm14 (ins->inst_offset)) {
2339                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2340                                 } else {
2341                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2342                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2343                                 }
2344                                 ins->inst_basereg = GP_SCRATCH_REG;
2345                         }
2346                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2347                         break;
2348
2349                 case OP_IA64_LOADU1_MEMBASE_INC:
2350                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2351                         break;
2352                 case OP_IA64_LOADU2_MEMBASE_INC:
2353                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2354                         break;
2355                 case OP_IA64_LOADU4_MEMBASE_INC:
2356                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2357                         break;
2358                 case OP_IA64_LOADI8_MEMBASE_INC:
2359                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2360                         break;
2361
2362                 case OP_SEXT_I1:
2363                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2364                         break;
2365                 case OP_SEXT_I2:
2366                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2367                         break;
2368                 case OP_SEXT_I4:
2369                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2370                         break;
2371                 case OP_ZEXT_I1:
2372                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2373                         break;
2374                 case OP_ZEXT_I2:
2375                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2376                         break;
2377                 case OP_ZEXT_I4:
2378                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2379                         break;
2380
2381                         /* Compare opcodes */
2382                 case OP_IA64_CMP4_EQ:
2383                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2384                         break;
2385                 case OP_IA64_CMP4_NE:
2386                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2387                         break;
2388                 case OP_IA64_CMP4_LE:
2389                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2390                         break;
2391                 case OP_IA64_CMP4_LT:
2392                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2393                         break;
2394                 case OP_IA64_CMP4_GE:
2395                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2396                         break;
2397                 case OP_IA64_CMP4_GT:
2398                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2399                         break;
2400                 case OP_IA64_CMP4_LT_UN:
2401                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2402                         break;
2403                 case OP_IA64_CMP4_LE_UN:
2404                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2405                         break;
2406                 case OP_IA64_CMP4_GT_UN:
2407                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_IA64_CMP4_GE_UN:
2410                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2411                         break;
2412                 case OP_IA64_CMP_EQ:
2413                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2414                         break;
2415                 case OP_IA64_CMP_NE:
2416                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2417                         break;
2418                 case OP_IA64_CMP_LE:
2419                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2420                         break;
2421                 case OP_IA64_CMP_LT:
2422                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2423                         break;
2424                 case OP_IA64_CMP_GE:
2425                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2426                         break;
2427                 case OP_IA64_CMP_GT:
2428                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2429                         break;
2430                 case OP_IA64_CMP_GT_UN:
2431                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2432                         break;
2433                 case OP_IA64_CMP_LT_UN:
2434                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2435                         break;
2436                 case OP_IA64_CMP_GE_UN:
2437                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2438                         break;
2439                 case OP_IA64_CMP_LE_UN:
2440                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2441                         break;
2442                 case OP_IA64_CMP4_EQ_IMM:
2443                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2444                         break;
2445                 case OP_IA64_CMP4_NE_IMM:
2446                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2447                         break;
2448                 case OP_IA64_CMP4_LE_IMM:
2449                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2450                         break;
2451                 case OP_IA64_CMP4_LT_IMM:
2452                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2453                         break;
2454                 case OP_IA64_CMP4_GE_IMM:
2455                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2456                         break;
2457                 case OP_IA64_CMP4_GT_IMM:
2458                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2459                         break;
2460                 case OP_IA64_CMP4_LT_UN_IMM:
2461                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2462                         break;
2463                 case OP_IA64_CMP4_LE_UN_IMM:
2464                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2465                         break;
2466                 case OP_IA64_CMP4_GT_UN_IMM:
2467                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2468                         break;
2469                 case OP_IA64_CMP4_GE_UN_IMM:
2470                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2471                         break;
2472                 case OP_IA64_CMP_EQ_IMM:
2473                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2474                         break;
2475                 case OP_IA64_CMP_NE_IMM:
2476                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2477                         break;
2478                 case OP_IA64_CMP_LE_IMM:
2479                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2480                         break;
2481                 case OP_IA64_CMP_LT_IMM:
2482                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2483                         break;
2484                 case OP_IA64_CMP_GE_IMM:
2485                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2486                         break;
2487                 case OP_IA64_CMP_GT_IMM:
2488                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2489                         break;
2490                 case OP_IA64_CMP_GT_UN_IMM:
2491                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2492                         break;
2493                 case OP_IA64_CMP_LT_UN_IMM:
2494                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2495                         break;
2496                 case OP_IA64_CMP_GE_UN_IMM:
2497                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2498                         break;
2499                 case OP_IA64_CMP_LE_UN_IMM:
2500                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2501                         break;
2502                 case OP_IA64_FCMP_EQ:
2503                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2504                         break;
2505                 case OP_IA64_FCMP_NE:
2506                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2507                         break;
2508                 case OP_IA64_FCMP_LT:
2509                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2510                         break;
2511                 case OP_IA64_FCMP_GT:
2512                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2513                         break;
2514                 case OP_IA64_FCMP_LE:
2515                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2516                         break;
2517                 case OP_IA64_FCMP_GE:
2518                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2519                         break;
2520                 case OP_IA64_FCMP_GT_UN:
2521                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2522                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2523                         break;
2524                 case OP_IA64_FCMP_LT_UN:
2525                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2526                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2527                         break;
2528                 case OP_IA64_FCMP_GE_UN:
2529                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2530                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2531                         break;
2532                 case OP_IA64_FCMP_LE_UN:
2533                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2534                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2535                         break;
2536
2537                 case OP_COND_EXC_IOV:
2538                 case OP_COND_EXC_OV:
2539                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2540                         break;
2541                 case OP_COND_EXC_IC:
2542                 case OP_COND_EXC_C:
2543                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2544                         break;
2545                 case OP_IA64_COND_EXC:
2546                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2547                         break;
2548                 case OP_IA64_CSET:
2549                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2550                         ia64_no_stop (code);
2551                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2552                         break;
2553                 case OP_ICONV_TO_I1:
2554                 case OP_LCONV_TO_I1:
2555                         /* FIXME: Is this needed ? */
2556                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2557                         break;
2558                 case OP_ICONV_TO_I2:
2559                 case OP_LCONV_TO_I2:
2560                         /* FIXME: Is this needed ? */
2561                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2562                         break;
2563                 case OP_LCONV_TO_I4:
2564                         /* FIXME: Is this needed ? */
2565                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2566                         break;
2567                 case OP_ICONV_TO_U1:
2568                 case OP_LCONV_TO_U1:
2569                         /* FIXME: Is this needed */
2570                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2571                         break;
2572                 case OP_ICONV_TO_U2:
2573                 case OP_LCONV_TO_U2:
2574                         /* FIXME: Is this needed */
2575                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2576                         break;
2577                 case OP_LCONV_TO_U4:
2578                         /* FIXME: Is this needed */
2579                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2580                         break;
2581                 case OP_ICONV_TO_I8:
2582                 case OP_ICONV_TO_I:
2583                 case OP_LCONV_TO_I8:
2584                 case OP_LCONV_TO_I:
2585                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2586                         break;
2587                 case OP_LCONV_TO_U8:
2588                 case OP_LCONV_TO_U:
2589                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2590                         break;
2591
2592                         /*
2593                          * FLOAT OPCODES
2594                          */
2595                 case OP_R8CONST: {
2596                         double d = *(double *)ins->inst_p0;
2597
2598                         if ((d == 0.0) && (mono_signbit (d) == 0))
2599                                 ia64_fmov (code, ins->dreg, 0);
2600                         else if (d == 1.0)
2601                                 ia64_fmov (code, ins->dreg, 1);
2602                         else {
2603                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2604                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2605                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2606                         }
2607                         break;
2608                 }
2609                 case OP_R4CONST: {
2610                         float f = *(float *)ins->inst_p0;
2611
2612                         if ((f == 0.0) && (mono_signbit (f) == 0))
2613                                 ia64_fmov (code, ins->dreg, 0);
2614                         else if (f == 1.0)
2615                                 ia64_fmov (code, ins->dreg, 1);
2616                         else {
2617                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2618                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2619                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2620                         }
2621                         break;
2622                 }
2623                 case OP_FMOVE:
2624                         ia64_fmov (code, ins->dreg, ins->sreg1);
2625                         break;
2626                 case OP_STORER8_MEMBASE_REG:
2627                         if (ins->inst_offset != 0) {
2628                                 /* This is generated by local regalloc */
2629                                 if (ia64_is_imm14 (ins->inst_offset)) {
2630                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2631                                 } else {
2632                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2633                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2634                                 }
2635                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2636                         }
2637                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2638                         break;
2639                 case OP_STORER4_MEMBASE_REG:
2640                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2641                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2642                         break;
2643                 case OP_LOADR8_MEMBASE:
2644                         if (ins->inst_offset != 0) {
2645                                 /* This is generated by local regalloc */
2646                                 if (ia64_is_imm14 (ins->inst_offset)) {
2647                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2648                                 } else {
2649                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2650                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2651                                 }
2652                                 ins->inst_basereg = GP_SCRATCH_REG;
2653                         }
2654                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2655                         break;
2656                 case OP_LOADR4_MEMBASE:
2657                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2658                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2659                         break;
2660                 case OP_ICONV_TO_R4:
2661                 case OP_LCONV_TO_R4:
2662                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2663                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2664                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2665                         break;
2666                 case OP_ICONV_TO_R8:
2667                 case OP_LCONV_TO_R8:
2668                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2669                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2670                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2671                         break;
2672                 case OP_FCONV_TO_R4:
2673                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2674                         break;
2675                 case OP_FCONV_TO_I8:
2676                 case OP_FCONV_TO_I:
2677                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2678                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2679                         break;
2680                 case OP_FADD:
2681                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2682                         break;
2683                 case OP_FSUB:
2684                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2685                         break;
2686                 case OP_FMUL:
2687                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2688                         break;
2689                 case OP_FNEG:
2690                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2691                         break;
2692                 case OP_CKFINITE:
2693                         /* Quiet NaN */
2694                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2695                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2696                         /* Signaling NaN */
2697                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2698                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2699                         /* Positive infinity */
2700                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2701                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2702                         /* Negative infinity */
2703                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2704                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2705                         break;
2706
2707                 /* Calls */
2708                 case OP_CHECK_THIS:
2709                         /* ensure ins->sreg1 is not NULL */
2710                         /* Can't use ld8 as this could be a vtype address */
2711                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2712                         break;
2713                 case OP_ARGLIST:
2714                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2715                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2716                         break;
2717                 case OP_FCALL:
2718                 case OP_LCALL:
2719                 case OP_VCALL:
2720                 case OP_VCALL2:
2721                 case OP_VOIDCALL:
2722                 case OP_CALL:
2723                         call = (MonoCallInst*)ins;
2724
2725                         if (ins->flags & MONO_INST_HAS_METHOD)
2726                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2727                         else
2728                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2729
2730                         code = emit_move_return_value (cfg, ins, code);
2731                         break;
2732
2733                 case OP_CALL_REG:
2734                 case OP_FCALL_REG:
2735                 case OP_LCALL_REG:
2736                 case OP_VCALL_REG:
2737                 case OP_VCALL2_REG:
2738                 case OP_VOIDCALL_REG: {
2739                         MonoCallInst *call = (MonoCallInst*)ins;
2740                         CallInfo *cinfo;
2741                         int out_reg;
2742
2743                         /*
2744                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2745                          * register.
2746                          */
2747                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2748                         out_reg = cfg->arch.reg_out0;
2749                         ia64_mov (code, IA64_R10, out_reg);
2750
2751                         /* Indirect call */
2752                         ia64_mov (code, IA64_R8, ins->sreg1);
2753                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2754                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2755                         ia64_ld8 (code, IA64_GP, IA64_R8);
2756                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2757
2758                         code = emit_move_return_value (cfg, ins, code);
2759                         break;
2760                 }
2761                 case OP_FCALL_MEMBASE:
2762                 case OP_LCALL_MEMBASE:
2763                 case OP_VCALL_MEMBASE:
2764                 case OP_VCALL2_MEMBASE:
2765                 case OP_VOIDCALL_MEMBASE:
2766                 case OP_CALL_MEMBASE: {
2767                         MonoCallInst *call = (MonoCallInst*)ins;
2768                         CallInfo *cinfo;
2769                         int out_reg;
2770
2771                         ia64_mov (code, IA64_R11, ins->sreg1);
2772                         if (ia64_is_imm14 (ins->inst_offset))
2773                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2774                         else {
2775                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2776                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2777                         }
2778
2779                         if (call->method && ins->inst_offset < 0) {
2780                                 /*
2781                                  * This is a possible IMT call so save the IMT method in a global
2782                                  * register where mono_arch_find_imt_method () and its friends can
2783                                  * access it.
2784                                  */
2785                                 ia64_movl (code, IA64_R9, call->method);
2786                         }
2787
2788                         /*
2789                          * mono_arch_find_this_arg () needs to find the this argument in a global
2790                          * register.
2791                          */
2792                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2793                         out_reg = cfg->arch.reg_out0;
2794                         ia64_mov (code, IA64_R10, out_reg);
2795
2796                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2797
2798                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2799
2800                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2801
2802                         code = emit_move_return_value (cfg, ins, code);
2803                         break;
2804                 }
2805                 case OP_JMP: {
2806                         /*
2807                          * Keep in sync with the code in emit_epilog.
2808                          */
2809
2810                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2811                                 NOT_IMPLEMENTED;
2812
2813                         g_assert (!cfg->method->save_lmf);
2814
2815                         /* Load arguments into their original registers */
2816                         code = emit_load_volatile_arguments (cfg, code);
2817
2818                         if (cfg->arch.stack_alloc_size) {
2819                                 if (cfg->arch.omit_fp) {
2820                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2821                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2822                                         else {
2823                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2824                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2825                                         }
2826                                 }
2827                                 else
2828                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2829                         }
2830                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2831                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2832
2833                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2834                         ia64_movl (code, GP_SCRATCH_REG, 0);
2835                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2836                         ia64_br_cond_reg (code, IA64_B6);
2837
2838                         break;
2839                 }
2840                 case OP_BREAK:
2841                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2842                         break;
2843
2844                 case OP_LOCALLOC: {
2845                         gint32 abi_offset;
2846
2847                         /* FIXME: Sigaltstack support */
2848
2849                         /* keep alignment */
2850                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2851                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2852                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2853
2854                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2855
2856                         ia64_mov (code, ins->dreg, IA64_SP);
2857
2858                         /* An area at sp is reserved by the ABI for parameter passing */
2859                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2860                         if (ia64_is_adds_imm (abi_offset))
2861                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2862                         else {
2863                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2864                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2865                         }
2866
2867                         if (ins->flags & MONO_INST_INIT) {
2868                                 /* Upper limit */
2869                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2870
2871                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2872
2873                                 /* Init loop */
2874                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2875                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2876                                 ia64_br_cond_pred (code, 8, -2);
2877
2878                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2879
2880                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2881                         }
2882
2883                         break;
2884                 }
2885                 case OP_LOCALLOC_IMM: {
2886                         gint32 abi_offset;
2887
2888                         /* FIXME: Sigaltstack support */
2889
2890                         gssize size = ins->inst_imm;
2891                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2892
2893                         if (ia64_is_adds_imm (size))
2894                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2895                         else
2896                                 ia64_movl (code, GP_SCRATCH_REG, size);
2897
2898                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2899                         ia64_mov (code, ins->dreg, IA64_SP);
2900
2901                         /* An area at sp is reserved by the ABI for parameter passing */
2902                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2903                         if (ia64_is_adds_imm (abi_offset))
2904                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2905                         else {
2906                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2907                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2908                         }
2909
2910                         if (ins->flags & MONO_INST_INIT) {
2911                                 /* Upper limit */
2912                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2913
2914                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2915
2916                                 /* Init loop */
2917                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2918                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2919                                 ia64_br_cond_pred (code, 8, -2);
2920
2921                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2922
2923                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2924                         }
2925
2926                         break;
2927                 }
2928                 case OP_TLS_GET:
2929                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2930                         ia64_ld8 (code, ins->dreg, ins->dreg);
2931                         break;
2932
2933                         /* Synchronization */
2934                 case OP_MEMORY_BARRIER:
2935                         ia64_mf (code);
2936                         break;
2937                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2938                         g_assert (ins->inst_offset == 0);
2939                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2940                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2941                         break;
2942                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2943                         g_assert (ins->inst_offset == 0);
2944                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2945                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2946                         break;
2947                 case OP_ATOMIC_EXCHANGE_I4:
2948                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2949                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2950                         break;
2951                 case OP_ATOMIC_EXCHANGE_I8:
2952                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2953                         break;
2954                 case OP_ATOMIC_ADD_NEW_I4: {
2955                         guint8 *label, *buf;
2956
2957                         /* From libatomic_ops */
2958                         ia64_mf (code);
2959
2960                         ia64_begin_bundle (code);
2961                         label = code.buf + code.nins;
2962                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2963                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2964                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2965                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2966                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2967                         buf = code.buf + code.nins;
2968                         ia64_br_cond_pred (code, 7, 0);
2969                         ia64_begin_bundle (code);
2970                         ia64_patch (buf, label);
2971                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2972                         break;
2973                 }
2974                 case OP_ATOMIC_ADD_NEW_I8: {
2975                         guint8 *label, *buf;
2976
2977                         /* From libatomic_ops */
2978                         ia64_mf (code);
2979
2980                         ia64_begin_bundle (code);
2981                         label = code.buf + code.nins;
2982                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2983                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2984                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2985                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2986                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2987                         buf = code.buf + code.nins;
2988                         ia64_br_cond_pred (code, 7, 0);
2989                         ia64_begin_bundle (code);
2990                         ia64_patch (buf, label);
2991                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2992                         break;
2993                 }
2994
2995                         /* Exception handling */
2996                 case OP_CALL_HANDLER:
2997                         /*
2998                          * Using a call instruction would mess up the register stack, so
2999                          * save the return address to a register and use a
3000                          * branch.
3001                          */
3002                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3003                         ia64_mov (code, IA64_R15, IA64_R0);
3004                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3005                         /* Add the length of OP_CALL_HANDLER */
3006                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3007                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3008                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3009                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3010                         ia64_br_cond_reg (code, IA64_B6);
3011                         // FIXME:
3012                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3013                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3014                         break;
3015                 case OP_START_HANDLER: {
3016                         /*
3017                          * We receive the return address in GP_SCRATCH_REG.
3018                          */
3019                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3020
3021                         /*
3022                          * R15 determines our caller. It is used since it is writable using
3023                          * libunwind.
3024                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3025                          * R15 != 0 means we are called by call_filter ().
3026                          */
3027                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3028                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3029
3030                         ia64_br_cond_pred (code, 6, 6);
3031
3032                         /*
3033                          * Called by call_filter:
3034                          * Allocate a new stack frame, and set the fp register from the
3035                          * value passed in by the caller.
3036                          * We allocate a similar frame as is done by the prolog, so
3037                          * if an exception is thrown while executing the filter, the
3038                          * unwinder can unwind through the filter frame using the unwind
3039                          * info for the prolog.
3040                          */
3041                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3042                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3043                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3044                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3045                         /* Signal to endfilter that we are called by call_filter */
3046                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3047
3048                         /* Branch target: */
3049                         if (ia64_is_imm14 (spvar->inst_offset))
3050                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3051                         else {
3052                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3053                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3054                         }
3055
3056                         /* Save the return address */
3057                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3058                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3059
3060                         break;
3061                 }
3062                 case OP_ENDFINALLY:
3063                 case OP_ENDFILTER: {
3064                         /* FIXME: Return the value in ENDFILTER */
3065                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3066
3067                         /* Load the return address */
3068                         if (ia64_is_imm14 (spvar->inst_offset)) {
3069                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3070                         } else {
3071                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3072                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3073                         }
3074                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3075
3076                         /* Test caller */
3077                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3078                         ia64_br_cond_pred (code, 7, 4);
3079
3080                         /* Called by call_filter */
3081                         /* Pop frame */
3082                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3083                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3084                         ia64_br_ret_reg (code, IA64_B0);
3085
3086                         /* Called by CALL_HANDLER */
3087                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3088                         ia64_br_cond_reg (code, IA64_B6);
3089                         break;
3090                 }
3091                 case OP_THROW:
3092                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3093                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3094                                                           (gpointer)"mono_arch_throw_exception");
3095
3096                         /*
3097                          * This might be the last instruction in the method, so add a dummy
3098                          * instruction so the unwinder will work.
3099                          */
3100                         ia64_break_i (code, 0);
3101                         break;
3102                 case OP_RETHROW:
3103                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3104                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3105                                                           (gpointer)"mono_arch_rethrow_exception");
3106
3107                         ia64_break_i (code, 0);
3108                         break;
3109
3110                 default:
3111                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3112                         g_assert_not_reached ();
3113                 }
3114
3115                 if ((code.buf - cfg->native_code - offset) > max_len) {
3116                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3117                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3118                         g_assert_not_reached ();
3119                 }
3120
3121                 cpos += max_len;
3122
3123                 last_ins = ins;
3124                 last_offset = offset;
3125         }
3126
3127         ia64_codegen_close (code);
3128
3129         cfg->code_len = code.buf - cfg->native_code;
3130 }
3131
3132 void
3133 mono_arch_register_lowlevel_calls (void)
3134 {
3135 }
3136
3137 static Ia64InsType ins_types_in_template [32][3] = {
3138         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3144         {0, 0, 0},
3145         {0, 0, 0},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3149         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3150         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158         {0, 0, 0},
3159         {0, 0, 0},
3160         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3161         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3163         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3164         {0, 0, 0},
3165         {0, 0, 0},
3166         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168         {0, 0, 0},
3169         {0, 0, 0}
3170 };
3171
3172 static gboolean stops_in_template [32][3] = {
3173         { FALSE, FALSE, FALSE },
3174         { FALSE, FALSE, TRUE },
3175         { FALSE, TRUE, FALSE },
3176         { FALSE, TRUE, TRUE },
3177         { FALSE, FALSE, FALSE },
3178         { FALSE, FALSE, TRUE },
3179         { FALSE, FALSE, FALSE },
3180         { FALSE, FALSE, FALSE },
3181
3182         { FALSE, FALSE, FALSE },
3183         { FALSE, FALSE, TRUE },
3184         { TRUE, FALSE, FALSE },
3185         { TRUE, FALSE, TRUE },
3186         { FALSE, FALSE, FALSE },
3187         { FALSE, FALSE, TRUE },
3188         { FALSE, FALSE, FALSE },
3189         { FALSE, FALSE, TRUE },
3190
3191         { FALSE, FALSE, FALSE },
3192         { FALSE, FALSE, TRUE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, TRUE },
3195         { FALSE, FALSE, FALSE },
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, FALSE },
3198         { FALSE, FALSE, TRUE },
3199
3200         { FALSE, FALSE, FALSE },
3201         { FALSE, FALSE, TRUE },
3202         { FALSE, FALSE, FALSE },
3203         { FALSE, FALSE, FALSE },
3204         { FALSE, FALSE, FALSE },
3205         { FALSE, FALSE, TRUE },
3206         { FALSE, FALSE, FALSE },
3207         { FALSE, FALSE, FALSE }
3208 };
3209
3210 static int last_stop_in_template [32] = {
3211         -1, 2, 1, 2, -1, 2, -1, -1,
3212         -1, 2, 0, 2, -1, 2, -1, 2,
3213         -1, 2, -1, 2, -1, -1, -1, 2,
3214         -1, 2, -1, -1, -1, 2, -1, -1
3215 };
3216
3217 static guint64 nops_for_ins_types [6] = {
3218         IA64_NOP_I,
3219         IA64_NOP_I,
3220         IA64_NOP_M,
3221         IA64_NOP_F,
3222         IA64_NOP_B,
3223         IA64_NOP_X
3224 };
3225
3226 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3227
3228 /*
3229  * Debugging support
3230  */
3231
3232 #if 0
3233 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3234 #else
3235 #define DEBUG_INS_SCHED(a)
3236 #endif
3237
3238 static void
3239 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3240 {
3241         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3242         guint8 *deps = code->dep_info;
3243         gboolean need_stop, no_stop;
3244
3245         for (i = 0; i < code->nins; ++i)
3246                 stops [i] = FALSE;
3247
3248         ins_index = 0;
3249         current_deps_start = 0;
3250         current_ins_start = 0;
3251         deps_start [ins_index] = current_ins_start;
3252         pos = 0;
3253         no_stop = FALSE;
3254         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3255         while (pos < code->dep_info_pos) {
3256                 need_stop = FALSE;
3257                 switch (deps [pos]) {
3258                 case IA64_END_OF_INS:
3259                         ins_index ++;
3260                         current_ins_start = pos + 2;
3261                         deps_start [ins_index] = current_ins_start;
3262                         no_stop = FALSE;
3263                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3264                         break;
3265                 case IA64_NONE:
3266                         break;
3267                 case IA64_READ_GR:
3268                         reg = deps [pos + 1];
3269
3270                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3271                         for (i = current_deps_start; i < current_ins_start; i += 2)
3272                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3273                                         need_stop = TRUE;
3274                         break;
3275                 case IA64_WRITE_GR:
3276                         reg = code->dep_info [pos + 1];
3277
3278                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3279                         for (i = current_deps_start; i < current_ins_start; i += 2)
3280                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3281                                         need_stop = TRUE;
3282                         break;
3283                 case IA64_READ_PR:
3284                         reg = deps [pos + 1];
3285
3286                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3287                         for (i = current_deps_start; i < current_ins_start; i += 2)
3288                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3289                                         need_stop = TRUE;
3290                         break;
3291                 case IA64_READ_PR_BRANCH:
3292                         reg = deps [pos + 1];
3293
3294                         /* Writes to prs by non-float instructions are visible to branches */
3295                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3296                         for (i = current_deps_start; i < current_ins_start; i += 2)
3297                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3298                                         need_stop = TRUE;
3299                         break;
3300                 case IA64_WRITE_PR:
3301                         reg = code->dep_info [pos + 1];
3302
3303                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3304                         for (i = current_deps_start; i < current_ins_start; i += 2)
3305                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3306                                         need_stop = TRUE;
3307                         break;
3308                 case IA64_WRITE_PR_FLOAT:
3309                         reg = code->dep_info [pos + 1];
3310
3311                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3312                         for (i = current_deps_start; i < current_ins_start; i += 2)
3313                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3314                                         need_stop = TRUE;
3315                         break;
3316                 case IA64_READ_BR:
3317                         reg = deps [pos + 1];
3318
3319                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3320                         for (i = current_deps_start; i < current_ins_start; i += 2)
3321                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3322                                         need_stop = TRUE;
3323                         break;
3324                 case IA64_WRITE_BR:
3325                         reg = code->dep_info [pos + 1];
3326
3327                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3328                         for (i = current_deps_start; i < current_ins_start; i += 2)
3329                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3330                                         need_stop = TRUE;
3331                         break;
3332                 case IA64_READ_BR_BRANCH:
3333                         reg = deps [pos + 1];
3334
3335                         /* Writes to brs are visible to branches */
3336                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3337                         break;
3338                 case IA64_READ_FR:
3339                         reg = deps [pos + 1];
3340
3341                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3342                         for (i = current_deps_start; i < current_ins_start; i += 2)
3343                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3344                                         need_stop = TRUE;
3345                         break;
3346                 case IA64_WRITE_FR:
3347                         reg = code->dep_info [pos + 1];
3348
3349                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3350                         for (i = current_deps_start; i < current_ins_start; i += 2)
3351                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3352                                         need_stop = TRUE;
3353                         break;
3354                 case IA64_READ_AR:
3355                         reg = deps [pos + 1];
3356
3357                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3358                         for (i = current_deps_start; i < current_ins_start; i += 2)
3359                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3360                                         need_stop = TRUE;
3361                         break;
3362                 case IA64_WRITE_AR:
3363                         reg = code->dep_info [pos + 1];
3364
3365                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3366                         for (i = current_deps_start; i < current_ins_start; i += 2)
3367                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3368                                         need_stop = TRUE;
3369                         break;
3370                 case IA64_NO_STOP:
3371                         /*
3372                          * Explicitly indicate that a stop is not required. Useful for
3373                          * example when two predicated instructions with negated predicates
3374                          * write the same registers.
3375                          */
3376                         no_stop = TRUE;
3377                         break;
3378                 default:
3379                         g_assert_not_reached ();
3380                 }
3381                 pos += 2;
3382
3383                 if (need_stop && !no_stop) {
3384                         g_assert (ins_index > 0);
3385                         stops [ins_index - 1] = 1;
3386
3387                         DEBUG_INS_SCHED (printf ("STOP\n"));
3388                         current_deps_start = current_ins_start;
3389
3390                         /* Skip remaining deps for this instruction */
3391                         while (deps [pos] != IA64_END_OF_INS)
3392                                 pos += 2;
3393                 }
3394         }
3395
3396         if (code->nins > 0) {
3397                 /* No dependency info for the last instruction */
3398                 stops [code->nins - 1] = 1;
3399         }
3400
3401         deps_start [code->nins] = code->dep_info_pos;
3402 }
3403
3404 static void
3405 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3406 {
3407         int stop_pos, i, deps_to_shift, dep_shift;
3408
3409         g_assert (n <= code->nins);
3410
3411         // if (n > 1) printf ("FOUND: %ld.\n", template);
3412
3413         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3414
3415         stop_pos = last_stop_in_template [template] + 1;
3416         if (stop_pos > n)
3417                 stop_pos = n;
3418
3419         /* Compute the number of 'real' instructions before the stop */
3420         deps_to_shift = stop_pos;
3421         if (stop_pos >= 3 && (nops & (1 << 2)))
3422                 deps_to_shift --;
3423         if (stop_pos >= 2 && (nops & (1 << 1)))
3424                 deps_to_shift --;
3425         if (stop_pos >= 1 && (nops & (1 << 0)))
3426                 deps_to_shift --;
3427
3428         /*
3429          * We have to keep some dependencies whose instructions have been shifted
3430          * out of the buffer. So nullify the end_of_ins markers in the dependency
3431          * array.
3432          */
3433         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3434                 if (code->dep_info [i] == IA64_END_OF_INS)
3435                         code->dep_info [i] = IA64_NONE;
3436
3437         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3438         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3439         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3440
3441         dep_shift = deps_start [deps_to_shift];
3442         for (i = 0; i < code->nins + 1 - n; ++i)
3443                 deps_start [i] = deps_start [n + i] - dep_shift;
3444
3445         /* Determine the exact positions of instructions with unwind ops */
3446         if (code->unw_op_count) {
3447                 int ins_pos [16];
3448                 int curr_ins, curr_ins_pos;
3449
3450                 curr_ins = 0;
3451                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3452                 for (i = 0; i < 3; ++i) {
3453                         if (! (nops & (1 << i))) {
3454                                 ins_pos [curr_ins] = curr_ins_pos + i;
3455                                 curr_ins ++;
3456                         }
3457                 }
3458
3459                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3460                         if (code->unw_ops_pos [i] < n) {
3461                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3462                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3463                         }
3464                 }
3465                 if (code->unw_op_pos < code->unw_op_count)
3466                         code->unw_op_pos += n;
3467         }
3468
3469         if (n == code->nins) {
3470                 code->template = 0;
3471                 code->nins = 0;
3472         }
3473         else {
3474                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3475                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3476                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3477                 code->nins -= n;
3478         }
3479 }
3480
3481 void
3482 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3483 {
3484         int i, ins_type, template, nins_to_emit;
3485         int deps_start [16];
3486         int stops [16];
3487         gboolean found;
3488
3489         /*
3490          * We implement a simple scheduler which tries to put three instructions
3491          * per bundle, then two, then one.
3492          */
3493         ia64_analyze_deps (code, deps_start, stops);
3494
3495         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3496                 /* Find a suitable template */
3497                 for (template = 0; template < 32; ++template) {
3498                         if (stops_in_template [template][0] != stops [0] ||
3499                                 stops_in_template [template][1] != stops [1] ||
3500                                 stops_in_template [template][2] != stops [2])
3501                                 continue;
3502
3503                         found = TRUE;
3504                         for (i = 0; i < 3; ++i) {
3505                                 ins_type = ins_types_in_template [template][i];
3506                                 switch (code->itypes [i]) {
3507                                 case IA64_INS_TYPE_A:
3508                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3509                                         break;
3510                                 default:
3511                                         found &= (ins_type == code->itypes [i]);
3512                                         break;
3513                                 }
3514                         }
3515
3516                         if (found)
3517                                 found = debug_ins_sched ();
3518
3519                         if (found) {
3520                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3521                                 break;
3522                         }
3523                 }
3524         }
3525
3526         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3527                 /* Wait for more instructions */
3528                 return;
3529
3530         /* If it didn't work out, try putting two instructions into one bundle */
3531         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3532                 /* Try a nop at the end */
3533                 for (template = 0; template < 32; ++template) {
3534                         if (stops_in_template [template][0] != stops [0] ||
3535                                 ((stops_in_template [template][1] != stops [1]) &&
3536                                  (stops_in_template [template][2] != stops [1])))
3537
3538                                 continue;
3539
3540                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3541                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3542                                 continue;
3543
3544                         if (!debug_ins_sched ())
3545                                 continue;
3546
3547                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3548                         break;
3549                 }
3550         }
3551
3552         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3553                 /* Wait for more instructions */
3554                 return;
3555
3556         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3557                 /* Try a nop in the middle */
3558                 for (template = 0; template < 32; ++template) {
3559                         if (((stops_in_template [template][0] != stops [0]) &&
3560                                  (stops_in_template [template][1] != stops [0])) ||
3561                                 stops_in_template [template][2] != stops [1])
3562                                 continue;
3563
3564                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3565                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3566                                 continue;
3567
3568                         if (!debug_ins_sched ())
3569                                 continue;
3570
3571                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3572                         break;
3573                 }
3574         }
3575
3576         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3577                 /* Try a nop at the beginning */
3578                 for (template = 0; template < 32; ++template) {
3579                         if ((stops_in_template [template][1] != stops [0]) ||
3580                                 (stops_in_template [template][2] != stops [1]))
3581                                 continue;
3582
3583                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3584                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3585                                 continue;
3586
3587                         if (!debug_ins_sched ())
3588                                 continue;
3589
3590                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3591                         break;
3592                 }
3593         }
3594
3595         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3596                 /* Wait for more instructions */
3597                 return;
3598
3599         if (flush)
3600                 nins_to_emit = code->nins;
3601         else
3602                 nins_to_emit = 1;
3603
3604         while (nins_to_emit > 0) {
3605                 if (!debug_ins_sched ())
3606                         stops [0] = 1;
3607                 switch (code->itypes [0]) {
3608                 case IA64_INS_TYPE_A:
3609                         if (stops [0])
3610                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3611                         else
3612                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3613                         break;
3614                 case IA64_INS_TYPE_I:
3615                         if (stops [0])
3616                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3617                         else
3618                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3619                         break;
3620                 case IA64_INS_TYPE_M:
3621                         if (stops [0])
3622                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3623                         else
3624                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3625                         break;
3626                 case IA64_INS_TYPE_B:
3627                         if (stops [0])
3628                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3629                         else
3630                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3631                         break;
3632                 case IA64_INS_TYPE_F:
3633                         if (stops [0])
3634                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3635                         else
3636                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3637                         break;
3638                 case IA64_INS_TYPE_LX:
3639                         if (stops [0] || stops [1])
3640                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3641                         else
3642                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3643                         nins_to_emit --;
3644                         break;
3645                 default:
3646                         g_assert_not_reached ();
3647                 }
3648                 nins_to_emit --;
3649         }
3650 }
3651
3652 unw_dyn_region_info_t*
3653 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3654 {
3655         unw_dyn_region_info_t *r;
3656
3657         g_assert (code->nins == 0);
3658         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3659         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3660         r->op_count = code->unw_op_count;
3661         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3662         code->unw_op_count = 0;
3663         code->unw_op_pos = 0;
3664         code->region_start = code->buf;
3665
3666         return r;
3667 }
3668
3669 static void
3670 ia64_patch (unsigned char* code, gpointer target)
3671 {
3672         int template, i;
3673         guint64 instructions [3];
3674         guint8 gen_buf [16];
3675         Ia64CodegenState gen;
3676         int ins_to_skip;
3677         gboolean found;
3678
3679         /*
3680          * code encodes both the position inside the buffer and code.nins when
3681          * the instruction was emitted.
3682          */
3683         ins_to_skip = (guint64)code % 16;
3684         code = (unsigned char*)((guint64)code & ~15);
3685
3686         /*
3687          * Search for the first instruction which is 'patchable', skipping
3688          * ins_to_skip instructions.
3689          */
3690
3691         while (TRUE) {
3692
3693         template = ia64_bundle_template (code);
3694         instructions [0] = ia64_bundle_ins1 (code);
3695         instructions [1] = ia64_bundle_ins2 (code);
3696         instructions [2] = ia64_bundle_ins3 (code);
3697
3698         ia64_codegen_init (gen, gen_buf);
3699
3700         found = FALSE;
3701         for (i = 0; i < 3; ++i) {
3702                 guint64 ins = instructions [i];
3703                 int opcode = ia64_ins_opcode (ins);
3704
3705                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3706                         continue;
3707
3708                 if (ins_to_skip) {
3709                         ins_to_skip --;
3710                         continue;
3711                 }
3712
3713                 switch (ins_types_in_template [template][i]) {
3714                 case IA64_INS_TYPE_A:
3715                 case IA64_INS_TYPE_M:
3716                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3717                                 /* adds */
3718                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3719                                 instructions [i] = gen.instructions [0];
3720                                 found = TRUE;
3721                         }
3722                         else
3723                                 NOT_IMPLEMENTED;
3724                         break;
3725                 case IA64_INS_TYPE_B:
3726                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3727                                 /* br.cond */
3728                                 gint64 disp = ((guint8*)target - code) >> 4;
3729
3730                                 /* FIXME: hints */
3731                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3732
3733                                 instructions [i] = gen.instructions [0];
3734                                 found = TRUE;
3735                         }
3736                         else if (opcode == 5) {
3737                                 /* br.call */
3738                                 gint64 disp = ((guint8*)target - code) >> 4;
3739
3740                                 /* FIXME: hints */
3741                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3742                                 instructions [i] = gen.instructions [0];
3743                                 found = TRUE;
3744                         }
3745                         else
3746                                 NOT_IMPLEMENTED;
3747                         break;
3748                 case IA64_INS_TYPE_LX:
3749                         if (i == 1)
3750                                 break;
3751
3752                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3753                                 /* movl */
3754                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3755                                 instructions [1] = gen.instructions [0];
3756                                 instructions [2] = gen.instructions [1];
3757                                 found = TRUE;
3758                         }
3759                         else
3760                                 NOT_IMPLEMENTED;
3761
3762                         break;
3763                 default:
3764                         NOT_IMPLEMENTED;
3765                 }
3766
3767                 if (found) {
3768                         /* Rewrite code */
3769                         ia64_codegen_init (gen, code);
3770                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3771                         return;
3772                 }
3773         }
3774
3775         code += 16;
3776         }
3777 }
3778
3779 void
3780 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
3781 {
3782         MonoJumpInfo *patch_info;
3783
3784         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3785                 unsigned char *ip = patch_info->ip.i + code;
3786                 const unsigned char *target;
3787
3788                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3789
3790                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3791                         continue;
3792                 if (mono_compile_aot) {
3793                         NOT_IMPLEMENTED;
3794                 }
3795
3796                 ia64_patch (ip, (gpointer)target);
3797         }
3798 }
3799
3800 guint8 *
3801 mono_arch_emit_prolog (MonoCompile *cfg)
3802 {
3803         MonoMethod *method = cfg->method;
3804         MonoMethodSignature *sig;
3805         MonoInst *inst;
3806         int alloc_size, pos, i;
3807         Ia64CodegenState code;
3808         CallInfo *cinfo;
3809
3810         sig = mono_method_signature (method);
3811         pos = 0;
3812
3813         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3814
3815         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3816
3817         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3818                 cfg->code_size += 1024;
3819         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3820                 cfg->code_size += 1024;
3821
3822         cfg->native_code = g_malloc (cfg->code_size);
3823
3824         ia64_codegen_init (code, cfg->native_code);
3825
3826         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3827         if (cfg->param_area)
3828                 alloc_size += cfg->param_area;
3829         if (alloc_size)
3830                 /* scratch area */
3831                 alloc_size += 16;
3832         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3833
3834         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3835                 /* Force sp to be saved/restored */
3836                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3837
3838         cfg->arch.stack_alloc_size = alloc_size;
3839
3840         pos = 0;
3841
3842         if (method->save_lmf) {
3843                 /* No LMF on IA64 */
3844         }
3845
3846         alloc_size -= pos;
3847
3848         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3849         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3850         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3851         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3852
3853         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3854                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3855                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3856                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3857                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3858         }
3859
3860         if (alloc_size) {
3861 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3862                 int pagesize = getpagesize ();
3863
3864                 if (alloc_size >= pagesize) {
3865                         gint32 remaining_size = alloc_size;
3866
3867                         /* Generate stack touching code */
3868                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3869                         while (remaining_size >= pagesize) {
3870                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3871                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3872                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3873                                 remaining_size -= pagesize;
3874                         }
3875                 }
3876 #endif
3877                 if (ia64_is_imm14 (-alloc_size)) {
3878                         if (cfg->arch.omit_fp)
3879                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3880                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3881                 }
3882                 else {
3883                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3884                         if (cfg->arch.omit_fp)
3885                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3886                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3887                 }
3888         }
3889
3890         ia64_begin_bundle (code);
3891
3892         /* Initialize unwind info */
3893         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3894
3895         if (sig->ret->type != MONO_TYPE_VOID) {
3896                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3897                         /* Save volatile arguments to the stack */
3898                         NOT_IMPLEMENTED;
3899                 }
3900         }
3901
3902         /* Keep this in sync with emit_load_volatile_arguments */
3903         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3904                 ArgInfo *ainfo = cinfo->args + i;
3905                 gint32 stack_offset;
3906                 MonoType *arg_type;
3907
3908                 inst = cfg->args [i];
3909
3910                 if (sig->hasthis && (i == 0))
3911                         arg_type = &mono_defaults.object_class->byval_arg;
3912                 else
3913                         arg_type = sig->params [i - sig->hasthis];
3914
3915                 arg_type = mono_type_get_underlying_type (arg_type);
3916
3917                 stack_offset = ainfo->offset + ARGS_OFFSET;
3918
3919                 /*
3920                  * FIXME: Native code might pass non register sized integers
3921                  * without initializing the upper bits.
3922                  */
3923                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3924                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3925
3926                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3927                         case OP_LOADI1_MEMBASE:
3928                                 ia64_sxt1 (code, reg, reg);
3929                                 break;
3930                         case OP_LOADU1_MEMBASE:
3931                                 ia64_zxt1 (code, reg, reg);
3932                                 break;
3933                         case OP_LOADI2_MEMBASE:
3934                                 ia64_sxt2 (code, reg, reg);
3935                                 break;
3936                         case OP_LOADU2_MEMBASE:
3937                                 ia64_zxt2 (code, reg, reg);
3938                                 break;
3939                         default:
3940                                 break;
3941                         }
3942                 }
3943
3944                 /* Save volatile arguments to the stack */
3945                 if (inst->opcode != OP_REGVAR) {
3946                         switch (ainfo->storage) {
3947                         case ArgInIReg:
3948                         case ArgInFloatReg:
3949                         case ArgInFloatRegR4:
3950                                 g_assert (inst->opcode == OP_REGOFFSET);
3951                                 if (ia64_is_adds_imm (inst->inst_offset))
3952                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3953                                 else {
3954                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3955                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3956                                 }
3957                                 if (arg_type->byref)
3958                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3959                                 else {
3960                                         switch (arg_type->type) {
3961                                         case MONO_TYPE_R4:
3962                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3963                                                 break;
3964                                         case MONO_TYPE_R8:
3965                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3966                                                 break;
3967                                         default:
3968                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3969                                                 break;
3970                                         }
3971                                 }
3972                                 break;
3973                         case ArgOnStack:
3974                                 break;
3975                         case ArgAggregate:
3976                                 if (ainfo->nslots != ainfo->nregs)
3977                                         NOT_IMPLEMENTED;
3978
3979                                 g_assert (inst->opcode == OP_REGOFFSET);
3980                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3981                                 for (i = 0; i < ainfo->nregs; ++i) {
3982                                         switch (ainfo->atype) {
3983                                         case AggregateNormal:
3984                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3985                                                 break;
3986                                         case AggregateSingleHFA:
3987                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3988                                                 break;
3989                                         case AggregateDoubleHFA:
3990                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3991                                                 break;
3992                                         default:
3993                                                 NOT_IMPLEMENTED;
3994                                         }
3995                                 }
3996                                 break;
3997                         default:
3998                                 g_assert_not_reached ();
3999                         }
4000                 }
4001
4002                 if (inst->opcode == OP_REGVAR) {
4003                         /* Argument allocated to (non-volatile) register */
4004                         switch (ainfo->storage) {
4005                         case ArgInIReg:
4006                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4007                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4008                                 break;
4009                         case ArgOnStack:
4010                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4011                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4012                                 break;
4013                         default:
4014                                 NOT_IMPLEMENTED;
4015                         }
4016                 }
4017         }
4018
4019         if (method->save_lmf) {
4020                 /* No LMF on IA64 */
4021         }
4022
4023         ia64_codegen_close (code);
4024
4025         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4026                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4027
4028         cfg->code_len = code.buf - cfg->native_code;
4029
4030         g_assert (cfg->code_len < cfg->code_size);
4031
4032         cfg->arch.prolog_end_offset = cfg->code_len;
4033
4034         return code.buf;
4035 }
4036
4037 void
4038 mono_arch_emit_epilog (MonoCompile *cfg)
4039 {
4040         MonoMethod *method = cfg->method;
4041         int i, pos;
4042         int max_epilog_size = 16 * 4;
4043         Ia64CodegenState code;
4044         guint8 *buf;
4045         CallInfo *cinfo;
4046         ArgInfo *ainfo;
4047
4048         if (mono_jit_trace_calls != NULL)
4049                 max_epilog_size += 1024;
4050
4051         cfg->arch.epilog_begin_offset = cfg->code_len;
4052
4053         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4054                 cfg->code_size *= 2;
4055                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4056                 cfg->stat_code_reallocs++;
4057         }
4058
4059         /* FIXME: Emit unwind info */
4060
4061         buf = cfg->native_code + cfg->code_len;
4062
4063         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4064                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4065
4066         ia64_codegen_init (code, buf);
4067
4068         /* the code restoring the registers must be kept in sync with OP_JMP */
4069         pos = 0;
4070
4071         if (method->save_lmf) {
4072                 /* No LMF on IA64 */
4073         }
4074
4075         /* Load returned vtypes into registers if needed */
4076         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4077         ainfo = &cinfo->ret;
4078         switch (ainfo->storage) {
4079         case ArgAggregate:
4080                 if (ainfo->nslots != ainfo->nregs)
4081                         NOT_IMPLEMENTED;
4082
4083                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4084                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4085                 for (i = 0; i < ainfo->nregs; ++i) {
4086                         switch (ainfo->atype) {
4087                         case AggregateNormal:
4088                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4089                                 break;
4090                         case AggregateSingleHFA:
4091                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4092                                 break;
4093                         case AggregateDoubleHFA:
4094                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4095                                 break;
4096                         default:
4097                                 g_assert_not_reached ();
4098                         }
4099                 }
4100                 break;
4101         default:
4102                 break;
4103         }
4104
4105         ia64_begin_bundle (code);
4106
4107         code.region_start = cfg->native_code;
4108
4109         /* Label the unwind state at the start of the exception throwing region */
4110         //ia64_unw_label_state (code, 1234);
4111
4112         if (cfg->arch.stack_alloc_size) {
4113                 if (cfg->arch.omit_fp) {
4114                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4115                                 ia64_unw_pop_frames (code, 1);
4116                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4117                         } else {
4118                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4119                                 ia64_unw_pop_frames (code, 1);
4120                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4121                         }
4122                 }
4123                 else {
4124                         ia64_unw_pop_frames (code, 1);
4125                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4126                 }
4127         }
4128         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4129         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4130         ia64_br_ret_reg (code, IA64_B0);
4131
4132         ia64_codegen_close (code);
4133
4134         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4135         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4136
4137         cfg->code_len = code.buf - cfg->native_code;
4138
4139         g_assert (cfg->code_len < cfg->code_size);
4140 }
4141
4142 void
4143 mono_arch_emit_exceptions (MonoCompile *cfg)
4144 {
4145         MonoJumpInfo *patch_info;
4146         int i, nthrows;
4147         Ia64CodegenState code;
4148         gboolean empty = TRUE;
4149         //unw_dyn_region_info_t *r_exceptions;
4150         MonoClass *exc_classes [16];
4151         guint8 *exc_throw_start [16], *exc_throw_end [16];
4152         guint32 code_size = 0;
4153
4154         /* Compute needed space */
4155         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4156                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4157                         code_size += 256;
4158                 if (patch_info->type == MONO_PATCH_INFO_R8)
4159                         code_size += 8 + 7; /* sizeof (double) + alignment */
4160                 if (patch_info->type == MONO_PATCH_INFO_R4)
4161                         code_size += 4 + 7; /* sizeof (float) + alignment */
4162         }
4163
4164         if (code_size == 0)
4165                 return;
4166
4167         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4168                 cfg->code_size *= 2;
4169                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4170                 cfg->stat_code_reallocs++;
4171         }
4172
4173         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4174
4175         /* The unwind state here is the same as before the epilog */
4176         //ia64_unw_copy_state (code, 1234);
4177
4178         /* add code to raise exceptions */
4179         /* FIXME: Optimize this */
4180         nthrows = 0;
4181         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4182                 switch (patch_info->type) {
4183                 case MONO_PATCH_INFO_EXC: {
4184                         MonoClass *exc_class;
4185                         guint8* throw_ip;
4186                         guint8* buf;
4187                         guint64 exc_token_index;
4188
4189                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4190                         g_assert (exc_class);
4191                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4192                         throw_ip = cfg->native_code + patch_info->ip.i;
4193
4194                         ia64_begin_bundle (code);
4195
4196                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4197
4198                         /* Find a throw sequence for the same exception class */
4199                         for (i = 0; i < nthrows; ++i)
4200                                 if (exc_classes [i] == exc_class)
4201                                         break;
4202
4203                         if (i < nthrows) {
4204                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4205
4206                                 if (ia64_is_adds_imm (offset))
4207                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4208                                 else
4209                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4210
4211                                 buf = code.buf + code.nins;
4212                                 ia64_br_cond_pred (code, 0, 0);
4213                                 ia64_begin_bundle (code);
4214                                 ia64_patch (buf, exc_throw_start [i]);
4215
4216                                 patch_info->type = MONO_PATCH_INFO_NONE;
4217                         }
4218                         else {
4219                                 /* Arg1 */
4220                                 buf = code.buf;
4221                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4222
4223                                 ia64_begin_bundle (code);
4224
4225                                 if (nthrows < 16) {
4226                                         exc_classes [nthrows] = exc_class;
4227                                         exc_throw_start [nthrows] = code.buf;
4228                                 }
4229
4230                                 /* Arg2 */
4231                                 if (ia64_is_adds_imm (exc_token_index))
4232                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4233                                 else
4234                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4235
4236                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4237                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4238                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4239
4240                                 /* Indirect call */
4241                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4242                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4243                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4244                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4245
4246                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4247
4248                                 /* Patch up the throw offset */
4249                                 ia64_begin_bundle (code);
4250
4251                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4252
4253                                 if (nthrows < 16) {
4254                                         exc_throw_end [nthrows] = code.buf;
4255                                         nthrows ++;
4256                                 }
4257                         }
4258
4259                         empty = FALSE;
4260                         break;
4261                 }
4262                 default:
4263                         break;
4264                 }
4265         }
4266
4267         if (!empty)
4268                 /* The unwinder needs this to work */
4269                 ia64_break_i (code, 0);
4270
4271         ia64_codegen_close (code);
4272
4273         /* FIXME: */
4274         //r_exceptions = mono_ia64_create_unwind_region (&code);
4275         //cfg->arch.r_epilog = r_exceptions;
4276
4277         cfg->code_len = code.buf - cfg->native_code;
4278
4279         g_assert (cfg->code_len < cfg->code_size);
4280 }
4281
4282 void*
4283 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4284 {
4285         Ia64CodegenState code;
4286         CallInfo *cinfo = NULL;
4287         MonoMethodSignature *sig;
4288         MonoInst *ins;
4289         int i, n, stack_area = 0;
4290
4291         ia64_codegen_init (code, p);
4292
4293         /* Keep this in sync with mono_arch_get_argument_info */
4294
4295         if (enable_arguments) {
4296                 /* Allocate a new area on the stack and save arguments there */
4297                 sig = mono_method_signature (cfg->method);
4298
4299                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4300
4301                 n = sig->param_count + sig->hasthis;
4302
4303                 stack_area = ALIGN_TO (n * 8, 16);
4304
4305                 if (n) {
4306                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4307
4308                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4309
4310                         /* FIXME: Allocate out registers */
4311
4312                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4313
4314                         /* Required by the ABI */
4315                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4316
4317                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4318                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4319
4320                         /* Save arguments to the stack */
4321                         for (i = 0; i < n; ++i) {
4322                                 ins = cfg->args [i];
4323
4324                                 if (ins->opcode == OP_REGVAR) {
4325                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4326                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4327                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4328                                 }
4329                                 else {
4330                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4331                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4332                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4333                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4334                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4335                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4336                                 }
4337                         }
4338                 }
4339                 else
4340                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4341         }
4342         else
4343                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4344
4345         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4346         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4347
4348         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4349
4350         if (enable_arguments && stack_area) {
4351                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4352
4353                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4354
4355                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4356         }
4357
4358         ia64_codegen_close (code);
4359
4360         return code.buf;
4361 }
4362
4363 void*
4364 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4365 {
4366         Ia64CodegenState code;
4367         CallInfo *cinfo = NULL;
4368         MonoMethod *method = cfg->method;
4369         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4370
4371         ia64_codegen_init (code, p);
4372
4373         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4374
4375         /* Save return value + pass it to func */
4376         switch (cinfo->ret.storage) {
4377         case ArgNone:
4378                 break;
4379         case ArgInIReg:
4380                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4381                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4382                 break;
4383         case ArgInFloatReg:
4384                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4385                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4386                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4387                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4388                 break;
4389         case ArgValuetypeAddrInIReg:
4390                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4391                 break;
4392         case ArgAggregate:
4393                 NOT_IMPLEMENTED;
4394                 break;
4395         default:
4396                 break;
4397         }
4398
4399         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4400         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4401         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4402
4403         /* Restore return value */
4404         switch (cinfo->ret.storage) {
4405         case ArgNone:
4406                 break;
4407         case ArgInIReg:
4408                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4409                 break;
4410         case ArgInFloatReg:
4411                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4412                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4413                 break;
4414         case ArgValuetypeAddrInIReg:
4415                 break;
4416         case ArgAggregate:
4417                 break;
4418         default:
4419                 break;
4420         }
4421
4422         ia64_codegen_close (code);
4423
4424         return code.buf;
4425 }
4426
4427 void
4428 mono_arch_save_unwind_info (MonoCompile *cfg)
4429 {
4430         unw_dyn_info_t *di;
4431
4432         /* FIXME: Unregister this for dynamic methods */
4433
4434         di = g_malloc0 (sizeof (unw_dyn_info_t));
4435         di->start_ip = (unw_word_t) cfg->native_code;
4436         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4437         di->gp = 0;
4438         di->format = UNW_INFO_FORMAT_DYNAMIC;
4439         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4440         di->u.pi.regions = cfg->arch.r_pro;
4441
4442         _U_dyn_register (di);
4443
4444         /*
4445         {
4446                 unw_dyn_region_info_t *region = di->u.pi.regions;
4447
4448                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4449                 while (region) {
4450                         printf ("    [Region: %d]\n", region->insn_count);
4451                         region = region->next;
4452                 }
4453         }
4454         */
4455 }
4456
4457 void
4458 mono_arch_flush_icache (guint8 *code, gint size)
4459 {
4460         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4461         guint8* end = (guint8*)((guint64)code + size);
4462
4463 #ifdef __INTEL_COMPILER
4464         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4465         while (p < end) {
4466                 __fc ((guint64)p);
4467                 p += 32;
4468         }
4469 #else
4470         while (p < end) {
4471                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4472                 /* FIXME: This could be increased to 128 on some cpus */
4473                 p += 32;
4474         }
4475 #endif
4476 }
4477
4478 void
4479 mono_arch_flush_register_windows (void)
4480 {
4481         /* Not needed because of libunwind */
4482 }
4483
4484 gboolean
4485 mono_arch_is_inst_imm (gint64 imm)
4486 {
4487         /* The lowering pass will take care of it */
4488
4489         return TRUE;
4490 }
4491
4492 /*
4493  * Determine whenever the trap whose info is in SIGINFO is caused by
4494  * integer overflow.
4495  */
4496 gboolean
4497 mono_arch_is_int_overflow (void *sigctx, void *info)
4498 {
4499         /* Division is emulated with explicit overflow checks */
4500         return FALSE;
4501 }
4502
4503 guint32
4504 mono_arch_get_patch_offset (guint8 *code)
4505 {
4506         NOT_IMPLEMENTED;
4507
4508         return 0;
4509 }
4510
4511 gpointer*
4512 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4513 {
4514         NOT_IMPLEMENTED;
4515
4516         return NULL;
4517 }
4518
4519 void
4520 mono_arch_finish_init (void)
4521 {
4522 }
4523
4524 void
4525 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4526 {
4527 }
4528
4529 #ifdef MONO_ARCH_HAVE_IMT
4530
4531 /*
4532  * LOCKING: called with the domain lock held
4533  */
4534 gpointer
4535 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4536         gpointer fail_tramp)
4537 {
4538         int i;
4539         int size = 0;
4540         guint8 *start, *buf;
4541         Ia64CodegenState code;
4542
4543         size = count * 256;
4544         buf = g_malloc0 (size);
4545         ia64_codegen_init (code, buf);
4546
4547         /* IA64_R9 contains the IMT method */
4548
4549         for (i = 0; i < count; ++i) {
4550                 MonoIMTCheckItem *item = imt_entries [i];
4551                 ia64_begin_bundle (code);
4552                 item->code_target = (guint8*)code.buf + code.nins;
4553                 if (item->is_equals) {
4554                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4555
4556                         if (item->check_target_idx || fail_case) {
4557                                 if (!item->compare_done || fail_case) {
4558                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4559                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4560                                 }
4561                                 item->jmp_code = (guint8*)code.buf + code.nins;
4562                                 ia64_br_cond_pred (code, 7, 0);
4563
4564                                 if (item->has_target_code) {
4565                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4566                                 } else {
4567                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4568                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4569                                 }
4570                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4571                                 ia64_br_cond_reg (code, IA64_B6);
4572
4573                                 if (fail_case) {
4574                                         ia64_begin_bundle (code);
4575                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4576                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4577                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4578                                         ia64_br_cond_reg (code, IA64_B6);
4579                                         item->jmp_code = NULL;
4580                                 }
4581                         } else {
4582                                 /* enable the commented code to assert on wrong method */
4583 #if ENABLE_WRONG_METHOD_CHECK
4584                                 g_assert_not_reached ();
4585 #endif
4586                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4587                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4588                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4589                                 ia64_br_cond_reg (code, IA64_B6);
4590 #if ENABLE_WRONG_METHOD_CHECK
4591                                 g_assert_not_reached ();
4592 #endif
4593                         }
4594                 } else {
4595                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4596                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4597                         item->jmp_code = (guint8*)code.buf + code.nins;
4598                         ia64_br_cond_pred (code, 6, 0);
4599                 }
4600         }
4601         /* patch the branches to get to the target items */
4602         for (i = 0; i < count; ++i) {
4603                 MonoIMTCheckItem *item = imt_entries [i];
4604                 if (item->jmp_code) {
4605                         if (item->check_target_idx) {
4606                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4607                         }
4608                 }
4609         }
4610
4611         ia64_codegen_close (code);
4612         g_assert (code.buf - buf <= size);
4613
4614         size = code.buf - buf;
4615         if (fail_tramp) {
4616                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4617                 start = (gpointer)ALIGN_TO (start, 16);
4618         } else {
4619                 start = mono_domain_code_reserve (domain, size);
4620         }
4621         memcpy (start, buf, size);
4622
4623         mono_arch_flush_icache (start, size);
4624
4625         mono_stats.imt_thunks_size += size;
4626
4627         return start;
4628 }
4629
4630 MonoMethod*
4631 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4632 {
4633         return (MonoMethod*)regs [IA64_R9];
4634 }
4635
4636 void
4637 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4638 {
4639         /* Done by the implementation of the CALL_MEMBASE opcodes */
4640 }
4641 #endif
4642
4643 gpointer
4644 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4645 {
4646         return (gpointer)regs [IA64_R10];
4647 }
4648
4649 gpointer
4650 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4651 {
4652         return NULL;
4653 }
4654
4655 MonoInst*
4656 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4657 {
4658         MonoInst *ins = NULL;
4659
4660         if (cmethod->klass->image == mono_defaults.corlib &&
4661                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4662                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4663
4664                 /*
4665                  * We don't use the generic version in mini_emit_inst_for_method () since we
4666                  * ia64 has atomic_add_imm opcodes.
4667                  */
4668                 if (strcmp (cmethod->name, "Increment") == 0) {
4669                         guint32 opcode;
4670
4671                         if (fsig->params [0]->type == MONO_TYPE_I4)
4672                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4673                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4674                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4675                         else
4676                                 g_assert_not_reached ();
4677                         MONO_INST_NEW (cfg, ins, opcode);
4678                         ins->dreg = mono_alloc_preg (cfg);
4679                         ins->inst_imm = 1;
4680                         ins->inst_basereg = args [0]->dreg;
4681                         ins->inst_offset = 0;
4682                         MONO_ADD_INS (cfg->cbb, ins);
4683                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4684                         guint32 opcode;
4685
4686                         if (fsig->params [0]->type == MONO_TYPE_I4)
4687                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4688                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4689                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4690                         else
4691                                 g_assert_not_reached ();
4692                         MONO_INST_NEW (cfg, ins, opcode);
4693                         ins->dreg = mono_alloc_preg (cfg);
4694                         ins->inst_imm = -1;
4695                         ins->inst_basereg = args [0]->dreg;
4696                         ins->inst_offset = 0;
4697                         MONO_ADD_INS (cfg->cbb, ins);
4698                 } else if (strcmp (cmethod->name, "Add") == 0) {
4699                         guint32 opcode;
4700                         gboolean is_imm = FALSE;
4701                         gint64 imm = 0;
4702
4703                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4704                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4705
4706                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4707                         }
4708
4709                         if (is_imm) {
4710                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4711                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4712                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4713                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4714                                 else
4715                                         g_assert_not_reached ();
4716
4717                                 MONO_INST_NEW (cfg, ins, opcode);
4718                                 ins->dreg = mono_alloc_ireg (cfg);
4719                                 ins->inst_basereg = args [0]->dreg;
4720                                 ins->inst_offset = 0;
4721                                 ins->inst_imm = imm;
4722                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4723                         } else {
4724                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4725                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4726                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4727                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4728                                 else
4729                                         g_assert_not_reached ();
4730
4731                                 MONO_INST_NEW (cfg, ins, opcode);
4732                                 ins->dreg = mono_alloc_ireg (cfg);
4733                                 ins->inst_basereg = args [0]->dreg;
4734                                 ins->inst_offset = 0;
4735                                 ins->sreg2 = args [1]->dreg;
4736                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4737                         }
4738                         MONO_ADD_INS (cfg->cbb, ins);
4739                 }
4740         }
4741
4742         return ins;
4743 }
4744
4745 gboolean
4746 mono_arch_print_tree (MonoInst *tree, int arity)
4747 {
4748         return 0;
4749 }
4750
4751 MonoInst*
4752 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4753 {
4754         return mono_get_domain_intrinsic (cfg);
4755 }
4756
4757 mgreg_t
4758 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4759 {
4760         /* FIXME: implement */
4761         g_assert_not_reached ();
4762 }