mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24 #include <mono/utils/mono-hwcap.h>
  25
  26 #include "trace.h"
  27 #include "mini-ia64.h"
  28 #include "cpu-ia64.h"
  29 #include "jit-icalls.h"
  30 #include "ir-emit.h"
  31
  32 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  33
  34 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  35
  36 /*
  37  * IA64 register usage:
  38  * - local registers are used for global register allocation
  39  * - r8..r11, r14..r30 is used for local register allocation
  40  * - r31 is a scratch register used within opcode implementations
  41  * - FIXME: Use out registers as well
  42  * - the first three locals are used for saving ar.pfst, b0, and sp
  43  * - compare instructions allways set p6 and p7
  44  */
  45
  46 /*
  47  * There are a lot of places where generated code is disassembled/patched.
  48  * The automatic bundling of instructions done by the code generation macros
  49  * could complicate things, so it is best to call
  50  * ia64_codegen_set_one_ins_per_bundle () at those places.
  51  */
  52
  53 #define ARGS_OFFSET 16
  54
  55 #define GP_SCRATCH_REG 31
  56 #define GP_SCRATCH_REG2 30
  57 #define FP_SCRATCH_REG 32
  58 #define FP_SCRATCH_REG2 33
  59
  60 #define LOOP_ALIGNMENT 8
  61 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  62
  63 static const char* gregs [] = {
  64         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  65         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  66         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  67         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  68         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  69         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  70         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  71         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  72         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  73         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  74         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  75         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  76         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  77 };
  78
  79 const char*
  80 mono_arch_regname (int reg)
  81 {
  82         if (reg < 128)
  83                 return gregs [reg];
  84         else
  85                 return "unknown";
  86 }
  87
  88 static const char* fregs [] = {
  89         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  90         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  91         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  92         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  93         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  94         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  95         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  96         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  97         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  98         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  99         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
 100         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 101         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < 128)
 108                 return fregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 static gboolean
 114 debug_ins_sched (void)
 115 {
 116 #if 0
 117         return mono_debug_count ();
 118 #else
 119         return TRUE;
 120 #endif
 121 }
 122
 123 static gboolean
 124 debug_omit_fp (void)
 125 {
 126 #if 0
 127         return mono_debug_count ();
 128 #else
 129         return TRUE;
 130 #endif
 131 }
 132
 133 static void
 134 ia64_patch (unsigned char* code, gpointer target);
 135
 136 typedef enum {
 137         ArgInIReg,
 138         ArgInFloatReg,
 139         ArgInFloatRegR4,
 140         ArgOnStack,
 141         ArgValuetypeAddrInIReg,
 142         ArgAggregate,
 143         ArgSingleHFA,
 144         ArgDoubleHFA,
 145         ArgNone
 146 } ArgStorage;
 147
 148 typedef enum {
 149         AggregateNormal,
 150         AggregateSingleHFA,
 151         AggregateDoubleHFA
 152 } AggregateType;
 153
 154 typedef struct {
 155         gint16 offset;
 156         gint8  reg;
 157         ArgStorage storage;
 158
 159         /* Only if storage == ArgAggregate */
 160         int nregs, nslots;
 161         AggregateType atype;
 162 } ArgInfo;
 163
 164 typedef struct {
 165         int nargs;
 166         guint32 stack_usage;
 167         guint32 reg_usage;
 168         guint32 freg_usage;
 169         gboolean need_stack_align;
 170         gboolean vtype_retaddr;
 171         /* The index of the vret arg in the argument list */
 172         int vret_arg_index;
 173         ArgInfo ret;
 174         ArgInfo sig_cookie;
 175         ArgInfo args [1];
 176 } CallInfo;
 177
 178 #define DEBUG(a) if (cfg->verbose_level > 1) a
 179
 180 #define PARAM_REGS 8
 181
 182 static void inline
 183 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 184 {
 185     ainfo->offset = *stack_size;
 186
 187     if (*gr >= PARAM_REGS) {
 188                 ainfo->storage = ArgOnStack;
 189                 (*stack_size) += sizeof (gpointer);
 190     }
 191     else {
 192                 ainfo->storage = ArgInIReg;
 193                 ainfo->reg = *gr;
 194                 *(gr) += 1;
 195     }
 196 }
 197
 198 #define FLOAT_PARAM_REGS 8
 199
 200 static void inline
 201 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 211                 ainfo->reg = 8 + *fr;
 212                 (*fr) += 1;
 213                 (*gr) += 1;
 214     }
 215 }
 216
 217 static void
 218 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 219                gboolean is_return,
 220                guint32 *gr, guint32 *fr, guint32 *stack_size)
 221 {
 222         guint32 size, i;
 223         MonoClass *klass;
 224         MonoMarshalType *info;
 225         gboolean is_hfa = TRUE;
 226         guint32 hfa_type = 0;
 227
 228         klass = mono_class_from_mono_type (type);
 229         if (type->type == MONO_TYPE_TYPEDBYREF)
 230                 size = 3 * sizeof (gpointer);
 231         else if (sig->pinvoke)
 232                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 233         else
 234                 size = mini_type_stack_size (&klass->byval_arg, NULL);
 235
 236         if (!sig->pinvoke || (size == 0)) {
 237                 /* Allways pass in memory */
 238                 ainfo->offset = *stack_size;
 239                 *stack_size += ALIGN_TO (size, 8);
 240                 ainfo->storage = ArgOnStack;
 241
 242                 return;
 243         }
 244
 245         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 246         info = mono_marshal_load_type_info (klass);
 247         g_assert (info);
 248         for (i = 0; i < info->num_fields; ++i) {
 249                 guint32 ftype = info->fields [i].field->type->type;
 250                 if (!(info->fields [i].field->type->byref) &&
 251                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 252                         if (hfa_type == 0)
 253                                 hfa_type = ftype;
 254                         else if (hfa_type != ftype)
 255                                 is_hfa = FALSE;
 256                 }
 257                 else
 258                         is_hfa = FALSE;
 259         }
 260         if (hfa_type == 0)
 261                 is_hfa = FALSE;
 262
 263         ainfo->storage = ArgAggregate;
 264         ainfo->atype = AggregateNormal;
 265
 266         if (is_hfa) {
 267                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 268                 if (is_return) {
 269                         if (info->num_fields <= 8) {
 270                                 ainfo->reg = 8;
 271                                 ainfo->nregs = info->num_fields;
 272                                 ainfo->nslots = ainfo->nregs;
 273                                 return;
 274                         }
 275                         /* Fall through */
 276                 }
 277                 else {
 278                         if ((*fr) + info->num_fields > 8)
 279                                 NOT_IMPLEMENTED;
 280
 281                         ainfo->reg = 8 + (*fr);
 282                         ainfo->nregs = info->num_fields;
 283                         ainfo->nslots = ainfo->nregs;
 284                         (*fr) += info->num_fields;
 285                         if (ainfo->atype == AggregateSingleHFA) {
 286                                 /*
 287                                  * FIXME: Have to keep track of the parameter slot number, which is
 288                                  * not the same as *gr.
 289                                  */
 290                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 291                         } else {
 292                                 (*gr) += info->num_fields;
 293                         }
 294                         return;
 295                 }
 296         }
 297
 298         /* This also handles returning of TypedByRef used by some icalls */
 299         if (is_return) {
 300                 if (size <= 32) {
 301                         ainfo->reg = IA64_R8;
 302                         ainfo->nregs = (size + 7) / 8;
 303                         ainfo->nslots = ainfo->nregs;
 304                         return;
 305                 }
 306                 NOT_IMPLEMENTED;
 307         }
 308
 309         ainfo->reg = (*gr);
 310         ainfo->offset = *stack_size;
 311         ainfo->nslots = (size + 7) / 8;
 312
 313         if (((*gr) + ainfo->nslots) <= 8) {
 314                 /* Fits entirely in registers */
 315                 ainfo->nregs = ainfo->nslots;
 316                 (*gr) += ainfo->nregs;
 317                 return;
 318         }
 319
 320         ainfo->nregs = 8 - (*gr);
 321         (*gr) = 8;
 322         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 323 }
 324
 325 /*
 326  * get_call_info:
 327  *
 328  *  Obtain information about a call according to the calling convention.
 329  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 330  * Gude" document for more information.
 331  */
 332 static CallInfo*
 333 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 334 {
 335         guint32 i, gr, fr, pstart;
 336         MonoType *ret_type;
 337         int n = sig->hasthis + sig->param_count;
 338         guint32 stack_size = 0;
 339         CallInfo *cinfo;
 340
 341         if (mp)
 342                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 343         else
 344                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 345
 346         gr = 0;
 347         fr = 0;
 348
 349         /* return value */
 350         {
 351                 ret_type = mini_get_underlying_type (sig->ret);
 352                 switch (ret_type->type) {
 353                 case MONO_TYPE_BOOLEAN:
 354                 case MONO_TYPE_I1:
 355                 case MONO_TYPE_U1:
 356                 case MONO_TYPE_I2:
 357                 case MONO_TYPE_U2:
 358                 case MONO_TYPE_CHAR:
 359                 case MONO_TYPE_I4:
 360                 case MONO_TYPE_U4:
 361                 case MONO_TYPE_I:
 362                 case MONO_TYPE_U:
 363                 case MONO_TYPE_PTR:
 364                 case MONO_TYPE_FNPTR:
 365                 case MONO_TYPE_CLASS:
 366                 case MONO_TYPE_OBJECT:
 367                 case MONO_TYPE_SZARRAY:
 368                 case MONO_TYPE_ARRAY:
 369                 case MONO_TYPE_STRING:
 370                         cinfo->ret.storage = ArgInIReg;
 371                         cinfo->ret.reg = IA64_R8;
 372                         break;
 373                 case MONO_TYPE_U8:
 374                 case MONO_TYPE_I8:
 375                         cinfo->ret.storage = ArgInIReg;
 376                         cinfo->ret.reg = IA64_R8;
 377                         break;
 378                 case MONO_TYPE_R4:
 379                 case MONO_TYPE_R8:
 380                         cinfo->ret.storage = ArgInFloatReg;
 381                         cinfo->ret.reg = 8;
 382                         break;
 383                 case MONO_TYPE_GENERICINST:
 384                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 385                                 cinfo->ret.storage = ArgInIReg;
 386                                 cinfo->ret.reg = IA64_R8;
 387                                 break;
 388                         }
 389                         /* Fall through */
 390                 case MONO_TYPE_VALUETYPE:
 391                 case MONO_TYPE_TYPEDBYREF: {
 392                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 393
 394                         if (sig->ret->byref) {
 395                                 /* This seems to happen with ldfld wrappers */
 396                                 cinfo->ret.storage = ArgInIReg;
 397                         } else {
 398                                 add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 399                                 if (cinfo->ret.storage == ArgOnStack) {
 400                                         /* The caller passes the address where the value is stored */
 401                                         cinfo->vtype_retaddr = TRUE;
 402                                 }
 403                         }
 404                         break;
 405                 }
 406                 case MONO_TYPE_VOID:
 407                         cinfo->ret.storage = ArgNone;
 408                         break;
 409                 default:
 410                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 411                 }
 412         }
 413
 414         pstart = 0;
 415         /*
 416          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 417          * the first argument, allowing 'this' to be always passed in the first arg reg.
 418          * Also do this if the first argument is a reference type, since virtual calls
 419          * are sometimes made using calli without sig->hasthis set, like in the delegate
 420          * invoke wrappers.
 421          */
 422         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 423                 if (sig->hasthis) {
 424                         add_general (&gr, &stack_size, cinfo->args + 0);
 425                 } else {
 426                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 427                         pstart = 1;
 428                 }
 429                 add_general (&gr, &stack_size, &cinfo->ret);
 430                 if (cinfo->ret.storage == ArgInIReg)
 431                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 432                 cinfo->vret_arg_index = 1;
 433         } else {
 434                 /* this */
 435                 if (sig->hasthis)
 436                         add_general (&gr, &stack_size, cinfo->args + 0);
 437
 438                 if (cinfo->vtype_retaddr) {
 439                         add_general (&gr, &stack_size, &cinfo->ret);
 440                         if (cinfo->ret.storage == ArgInIReg)
 441                                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
 442                 }
 443         }
 444
 445         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 446                 gr = PARAM_REGS;
 447                 fr = FLOAT_PARAM_REGS;
 448
 449                 /* Emit the signature cookie just before the implicit arguments */
 450                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 451         }
 452
 453         for (i = pstart; i < sig->param_count; ++i) {
 454                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 455                 MonoType *ptype;
 456
 457                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 458                         /* We allways pass the sig cookie on the stack for simplicity */
 459                         /*
 460                          * Prevent implicit arguments + the sig cookie from being passed
 461                          * in registers.
 462                          */
 463                         gr = PARAM_REGS;
 464                         fr = FLOAT_PARAM_REGS;
 465
 466                         /* Emit the signature cookie just before the implicit arguments */
 467                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 468                 }
 469
 470                 if (sig->params [i]->byref) {
 471                         add_general (&gr, &stack_size, ainfo);
 472                         continue;
 473                 }
 474                 ptype = mini_get_underlying_type (sig->params [i]);
 475                 switch (ptype->type) {
 476                 case MONO_TYPE_BOOLEAN:
 477                 case MONO_TYPE_I1:
 478                 case MONO_TYPE_U1:
 479                         add_general (&gr, &stack_size, ainfo);
 480                         break;
 481                 case MONO_TYPE_I2:
 482                 case MONO_TYPE_U2:
 483                 case MONO_TYPE_CHAR:
 484                         add_general (&gr, &stack_size, ainfo);
 485                         break;
 486                 case MONO_TYPE_I4:
 487                 case MONO_TYPE_U4:
 488                         add_general (&gr, &stack_size, ainfo);
 489                         break;
 490                 case MONO_TYPE_I:
 491                 case MONO_TYPE_U:
 492                 case MONO_TYPE_PTR:
 493                 case MONO_TYPE_FNPTR:
 494                 case MONO_TYPE_CLASS:
 495                 case MONO_TYPE_OBJECT:
 496                 case MONO_TYPE_STRING:
 497                 case MONO_TYPE_SZARRAY:
 498                 case MONO_TYPE_ARRAY:
 499                         add_general (&gr, &stack_size, ainfo);
 500                         break;
 501                 case MONO_TYPE_GENERICINST:
 502                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 503                                 add_general (&gr, &stack_size, ainfo);
 504                                 break;
 505                         }
 506                         /* Fall through */
 507                 case MONO_TYPE_VALUETYPE:
 508                 case MONO_TYPE_TYPEDBYREF:
 509                         /* FIXME: */
 510                         /* We allways pass valuetypes on the stack */
 511                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 512                         break;
 513                 case MONO_TYPE_U8:
 514                 case MONO_TYPE_I8:
 515                         add_general (&gr, &stack_size, ainfo);
 516                         break;
 517                 case MONO_TYPE_R4:
 518                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 519                         break;
 520                 case MONO_TYPE_R8:
 521                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 522                         break;
 523                 default:
 524                         g_assert_not_reached ();
 525                 }
 526         }
 527
 528         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 529                 gr = PARAM_REGS;
 530                 fr = FLOAT_PARAM_REGS;
 531
 532                 /* Emit the signature cookie just before the implicit arguments */
 533                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 534         }
 535
 536         cinfo->stack_usage = stack_size;
 537         cinfo->reg_usage = gr;
 538         cinfo->freg_usage = fr;
 539         return cinfo;
 540 }
 541
 542 /*
 543  * mono_arch_get_argument_info:
 544  * @csig:  a method signature
 545  * @param_count: the number of parameters to consider
 546  * @arg_info: an array to store the result infos
 547  *
 548  * Gathers information on parameters such as size, alignment and
 549  * padding. arg_info should be large enought to hold param_count + 1 entries.
 550  *
 551  * Returns the size of the argument area on the stack.
 552  */
 553 int
 554 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 555 {
 556         int k;
 557         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 558         guint32 args_size = cinfo->stack_usage;
 559
 560         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 561         if (csig->hasthis) {
 562                 arg_info [0].offset = 0;
 563         }
 564
 565         for (k = 0; k < param_count; k++) {
 566                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 567                 /* FIXME: */
 568                 arg_info [k + 1].size = 0;
 569         }
 570
 571         g_free (cinfo);
 572
 573         return args_size;
 574 }
 575
 576 /*
 577  * Initialize the cpu to execute managed code.
 578  */
 579 void
 580 mono_arch_cpu_init (void)
 581 {
 582 }
 583
 584 /*
 585  * Initialize architecture specific code.
 586  */
 587 void
 588 mono_arch_init (void)
 589 {
 590 }
 591
 592 /*
 593  * Cleanup architecture specific code.
 594  */
 595 void
 596 mono_arch_cleanup (void)
 597 {
 598 }
 599
 600 gboolean
 601 mono_arch_have_fast_tls (void)
 602 {
 603         return FALSE;
 604 }
 605
 606 /*
 607  * This function returns the optimizations supported on this cpu.
 608  */
 609 guint32
 610 mono_arch_cpu_optimizations (guint32 *exclude_mask)
 611 {
 612         *exclude_mask = 0;
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * This function test for all SIMD functions supported.
 619  *
 620  * Returns a bitmask corresponding to all supported versions.
 621  *
 622  */
 623 guint32
 624 mono_arch_cpu_enumerate_simd_versions (void)
 625 {
 626         /* SIMD is currently unimplemented */
 627         return 0;
 628 }
 629
 630 GList *
 631 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 632 {
 633         GList *vars = NULL;
 634         int i;
 635         MonoMethodSignature *sig;
 636         MonoMethodHeader *header;
 637         CallInfo *cinfo;
 638
 639         header = cfg->header;
 640
 641         sig = mono_method_signature (cfg->method);
 642
 643         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 644
 645         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 646                 MonoInst *ins = cfg->args [i];
 647
 648                 ArgInfo *ainfo = &cinfo->args [i];
 649
 650                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 651                         continue;
 652
 653                 if (ainfo->storage == ArgInIReg) {
 654                         /* The input registers are non-volatile */
 655                         ins->opcode = OP_REGVAR;
 656                         ins->dreg = 32 + ainfo->reg;
 657                 }
 658         }
 659
 660         for (i = 0; i < cfg->num_varinfo; i++) {
 661                 MonoInst *ins = cfg->varinfo [i];
 662                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 663
 664                 /* unused vars */
 665                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 666                         continue;
 667
 668                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 669                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 670                         continue;
 671
 672                 if (mono_is_regsize_var (ins->inst_vtype)) {
 673                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 674                         g_assert (i == vmv->idx);
 675                         vars = g_list_prepend (vars, vmv);
 676                 }
 677         }
 678
 679         vars = mono_varlist_sort (cfg, vars, 0);
 680
 681         return vars;
 682 }
 683
 684 static void
 685 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 686 {
 687         CallInfo *cinfo;
 688         guint32 reserved_regs;
 689         MonoMethodHeader *header;
 690
 691         if (cfg->arch.reg_local0 > 0)
 692                 /* Already done */
 693                 return;
 694
 695         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 696
 697         header = cfg->header;
 698
 699         /* Some registers are reserved for use by the prolog/epilog */
 700         reserved_regs = header->num_clauses ? 4 : 3;
 701
 702         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 703                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 704                 /* One registers is needed by instrument_epilog to save the return value */
 705                 reserved_regs ++;
 706                 if (cinfo->reg_usage < 2)
 707                         /* Number of arguments passed to function call in instrument_prolog */
 708                         cinfo->reg_usage = 2;
 709         }
 710
 711         cfg->arch.reg_in0 = 32;
 712         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 713         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 714
 715         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 716         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 717         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 718
 719         /*
 720          * Frames without handlers save sp to fp, frames with handlers save it into
 721          * a dedicated register.
 722          */
 723         if (header->num_clauses)
 724                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 725         else
 726                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 727
 728         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 729                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 730                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 731         }
 732
 733         /*
 734          * Need to allocate at least 2 out register for use by OP_THROW / the system
 735          * exception throwing code.
 736          */
 737         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 738 }
 739
 740 GList *
 741 mono_arch_get_global_int_regs (MonoCompile *cfg)
 742 {
 743         GList *regs = NULL;
 744         int i;
 745
 746         mono_ia64_alloc_stacked_registers (cfg);
 747
 748         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 749                 /* FIXME: regmask */
 750                 g_assert (i < 64);
 751                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 752         }
 753
 754         return regs;
 755 }
 756
 757 /*
 758  * mono_arch_regalloc_cost:
 759  *
 760  *  Return the cost, in number of memory references, of the action of
 761  * allocating the variable VMV into a register during global register
 762  * allocation.
 763  */
 764 guint32
 765 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 766 {
 767         /* FIXME: Increase costs linearly to avoid using all local registers */
 768
 769         return 0;
 770 }
 771
 772 void
 773 mono_arch_allocate_vars (MonoCompile *cfg)
 774 {
 775         MonoMethodSignature *sig;
 776         MonoMethodHeader *header;
 777         MonoInst *inst;
 778         int i, offset;
 779         guint32 locals_stack_size, locals_stack_align;
 780         gint32 *offsets;
 781         CallInfo *cinfo;
 782
 783         header = cfg->header;
 784
 785         sig = mono_method_signature (cfg->method);
 786
 787         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 788
 789         /*
 790          * Determine whenever the frame pointer can be eliminated.
 791          * FIXME: Remove some of the restrictions.
 792          */
 793         cfg->arch.omit_fp = TRUE;
 794
 795         if (!debug_omit_fp ())
 796                 cfg->arch.omit_fp = FALSE;
 797
 798         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 799                 cfg->arch.omit_fp = FALSE;
 800         if (header->num_clauses)
 801                 cfg->arch.omit_fp = FALSE;
 802         if (cfg->param_area)
 803                 cfg->arch.omit_fp = FALSE;
 804         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 805                 cfg->arch.omit_fp = FALSE;
 806         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 807                 cfg->arch.omit_fp = FALSE;
 808         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 809                 ArgInfo *ainfo = &cinfo->args [i];
 810
 811                 if (ainfo->storage == ArgOnStack) {
 812                         /*
 813                          * The stack offset can only be determined when the frame
 814                          * size is known.
 815                          */
 816                         cfg->arch.omit_fp = FALSE;
 817                 }
 818         }
 819
 820         mono_ia64_alloc_stacked_registers (cfg);
 821
 822         /*
 823          * We use the ABI calling conventions for managed code as well.
 824          * Exception: valuetypes are never passed or returned in registers.
 825          */
 826
 827         if (cfg->arch.omit_fp) {
 828                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 829                 cfg->frame_reg = IA64_SP;
 830                 offset = ARGS_OFFSET;
 831         }
 832         else {
 833                 /* Locals are allocated backwards from %fp */
 834                 cfg->frame_reg = cfg->arch.reg_fp;
 835                 offset = 0;
 836         }
 837
 838         if (cfg->method->save_lmf) {
 839                 /* No LMF on IA64 */
 840         }
 841
 842         if (sig->ret->type != MONO_TYPE_VOID) {
 843                 switch (cinfo->ret.storage) {
 844                 case ArgInIReg:
 845                         cfg->ret->opcode = OP_REGVAR;
 846                         cfg->ret->inst_c0 = cinfo->ret.reg;
 847                         break;
 848                 case ArgInFloatReg:
 849                         cfg->ret->opcode = OP_REGVAR;
 850                         cfg->ret->inst_c0 = cinfo->ret.reg;
 851                         break;
 852                 case ArgValuetypeAddrInIReg:
 853                         cfg->vret_addr->opcode = OP_REGVAR;
 854                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 855                         break;
 856                 case ArgAggregate:
 857                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 858                         if (cfg->arch.omit_fp)
 859                                 g_assert_not_reached ();
 860                         offset = ALIGN_TO (offset, 8);
 861                         offset += cinfo->ret.nslots * 8;
 862                         cfg->ret->opcode = OP_REGOFFSET;
 863                         cfg->ret->inst_basereg = cfg->frame_reg;
 864                         cfg->ret->inst_offset = - offset;
 865                         break;
 866                 default:
 867                         g_assert_not_reached ();
 868                 }
 869                 cfg->ret->dreg = cfg->ret->inst_c0;
 870         }
 871
 872         /* Allocate locals */
 873         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 874         if (locals_stack_align) {
 875                 offset = ALIGN_TO (offset, locals_stack_align);
 876         }
 877         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 878                 if (offsets [i] != -1) {
 879                         MonoInst *inst = cfg->varinfo [i];
 880                         inst->opcode = OP_REGOFFSET;
 881                         inst->inst_basereg = cfg->frame_reg;
 882                         if (cfg->arch.omit_fp)
 883                                 inst->inst_offset = (offset + offsets [i]);
 884                         else
 885                                 inst->inst_offset = - (offset + offsets [i]);
 886                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 887                 }
 888         }
 889         offset += locals_stack_size;
 890
 891         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 892                 if (cfg->arch.omit_fp)
 893                         g_assert_not_reached ();
 894                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 895                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 896         }
 897
 898         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 899                 inst = cfg->args [i];
 900                 if (inst->opcode != OP_REGVAR) {
 901                         ArgInfo *ainfo = &cinfo->args [i];
 902                         gboolean inreg = TRUE;
 903                         MonoType *arg_type;
 904
 905                         if (sig->hasthis && (i == 0))
 906                                 arg_type = &mono_defaults.object_class->byval_arg;
 907                         else
 908                                 arg_type = sig->params [i - sig->hasthis];
 909
 910                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 911                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 912                                 inreg = FALSE;
 913
 914                         inst->opcode = OP_REGOFFSET;
 915
 916                         switch (ainfo->storage) {
 917                         case ArgInIReg:
 918                                 inst->opcode = OP_REGVAR;
 919                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 920                                 break;
 921                         case ArgInFloatReg:
 922                         case ArgInFloatRegR4:
 923                                 /*
 924                                  * Since float regs are volatile, we save the arguments to
 925                                  * the stack in the prolog.
 926                                  */
 927                                 inreg = FALSE;
 928                                 break;
 929                         case ArgOnStack:
 930                                 if (cfg->arch.omit_fp)
 931                                         g_assert_not_reached ();
 932                                 inst->opcode = OP_REGOFFSET;
 933                                 inst->inst_basereg = cfg->frame_reg;
 934                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 935                                 break;
 936                         case ArgAggregate:
 937                                 inreg = FALSE;
 938                                 break;
 939                         default:
 940                                 NOT_IMPLEMENTED;
 941                         }
 942
 943                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 944                                 guint32 size = 0;
 945
 946                                 inst->opcode = OP_REGOFFSET;
 947                                 inst->inst_basereg = cfg->frame_reg;
 948                                 /* These arguments are saved to the stack in the prolog */
 949                                 switch (ainfo->storage) {
 950                                 case ArgAggregate:
 951                                         if (ainfo->atype == AggregateSingleHFA)
 952                                                 size = ainfo->nslots * 4;
 953                                         else
 954                                                 size = ainfo->nslots * 8;
 955                                         break;
 956                                 default:
 957                                         size = sizeof (gpointer);
 958                                         break;
 959                                 }
 960
 961                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 962
 963                                 if (cfg->arch.omit_fp) {
 964                                         inst->inst_offset = offset;
 965                                         offset += size;
 966                                 } else {
 967                                         offset += size;
 968                                         inst->inst_offset = - offset;
 969                                 }
 970                         }
 971                 }
 972         }
 973
 974         /*
 975          * FIXME: This doesn't work because some variables are allocated during local
 976          * regalloc.
 977          */
 978         /*
 979         if (cfg->arch.omit_fp && offset == 16)
 980                 offset = 0;
 981         */
 982
 983         cfg->stack_offset = offset;
 984 }
 985
 986 void
 987 mono_arch_create_vars (MonoCompile *cfg)
 988 {
 989         MonoMethodSignature *sig;
 990         CallInfo *cinfo;
 991
 992         sig = mono_method_signature (cfg->method);
 993
 994         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 995
 996         if (cinfo->ret.storage == ArgAggregate)
 997                 cfg->ret_var_is_local = TRUE;
 998         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 999                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1000                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1001                         printf ("vret_addr = ");
1002                         mono_print_ins (cfg->vret_addr);
1003                 }
1004         }
1005 }
1006
1007 static void
1008 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1009 {
1010         MonoInst *arg;
1011
1012         MONO_INST_NEW (cfg, arg, OP_NOP);
1013         arg->sreg1 = tree->dreg;
1014
1015         switch (storage) {
1016         case ArgInIReg:
1017                 arg->opcode = OP_MOVE;
1018                 arg->dreg = mono_alloc_ireg (cfg);
1019
1020                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1021                 break;
1022         case ArgInFloatReg:
1023                 arg->opcode = OP_FMOVE;
1024                 arg->dreg = mono_alloc_freg (cfg);
1025
1026                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1027                 break;
1028         case ArgInFloatRegR4:
1029                 arg->opcode = OP_FCONV_TO_R4;
1030                 arg->dreg = mono_alloc_freg (cfg);
1031
1032                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1033                 break;
1034         default:
1035                 g_assert_not_reached ();
1036         }
1037
1038         MONO_ADD_INS (cfg->cbb, arg);
1039 }
1040
1041 static void
1042 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1043 {
1044         MonoMethodSignature *tmp_sig;
1045
1046         /* Emit the signature cookie just before the implicit arguments */
1047         MonoInst *sig_arg;
1048         /* FIXME: Add support for signature tokens to AOT */
1049         cfg->disable_aot = TRUE;
1050
1051         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1052
1053         /*
1054          * mono_ArgIterator_Setup assumes the signature cookie is
1055          * passed first and all the arguments which were before it are
1056          * passed on the stack after the signature. So compensate by
1057          * passing a different signature.
1058          */
1059         tmp_sig = mono_metadata_signature_dup (call->signature);
1060         tmp_sig->param_count -= call->signature->sentinelpos;
1061         tmp_sig->sentinelpos = 0;
1062         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1063
1064         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1065         sig_arg->dreg = mono_alloc_ireg (cfg);
1066         sig_arg->inst_p0 = tmp_sig;
1067         MONO_ADD_INS (cfg->cbb, sig_arg);
1068
1069         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1070 }
1071
1072 void
1073 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1074 {
1075         MonoInst *in;
1076         MonoMethodSignature *sig;
1077         int i, n, stack_size;
1078         CallInfo *cinfo;
1079         ArgInfo *ainfo;
1080
1081         stack_size = 0;
1082
1083         mono_ia64_alloc_stacked_registers (cfg);
1084
1085         sig = call->signature;
1086         n = sig->param_count + sig->hasthis;
1087
1088         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1089
1090         if (cinfo->ret.storage == ArgAggregate) {
1091                 MonoInst *vtarg;
1092                 MonoInst *local;
1093
1094                 /*
1095                  * The valuetype is in registers after the call, need to be copied
1096                  * to the stack. Save the address to a local here, so the call
1097                  * instruction can access it.
1098                  */
1099                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1100                 local->flags |= MONO_INST_VOLATILE;
1101                 cfg->arch.ret_var_addr_local = local;
1102
1103                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1104                 vtarg->sreg1 = call->vret_var->dreg;
1105                 vtarg->dreg = local->dreg;
1106                 MONO_ADD_INS (cfg->cbb, vtarg);
1107         }
1108
1109         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1110                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1111         }
1112
1113         for (i = 0; i < n; ++i) {
1114                 MonoType *arg_type;
1115
1116                 ainfo = cinfo->args + i;
1117
1118                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1119                         /* Emit the signature cookie just before the implicit arguments */
1120                         emit_sig_cookie (cfg, call, cinfo);
1121                 }
1122
1123                 in = call->args [i];
1124
1125                 if (sig->hasthis && (i == 0))
1126                         arg_type = &mono_defaults.object_class->byval_arg;
1127                 else
1128                         arg_type = sig->params [i - sig->hasthis];
1129
1130                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1131                         guint32 align;
1132                         guint32 size;
1133
1134                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1135                                 size = sizeof (MonoTypedRef);
1136                                 align = sizeof (gpointer);
1137                         }
1138                         else if (sig->pinvoke)
1139                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1140                         else {
1141                                 /*
1142                                  * Other backends use mono_type_stack_size (), but that
1143                                  * aligns the size to 8, which is larger than the size of
1144                                  * the source, leading to reads of invalid memory if the
1145                                  * source is at the end of address space.
1146                                  */
1147                                 size = mono_class_value_size (in->klass, &align);
1148                         }
1149
1150                         if (size > 0) {
1151                                 MonoInst *arg;
1152
1153                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1154                                 arg->sreg1 = in->dreg;
1155                                 arg->klass = in->klass;
1156                                 arg->backend.size = size;
1157                                 arg->inst_p0 = call;
1158                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1159                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1160
1161                                 MONO_ADD_INS (cfg->cbb, arg);
1162                         }
1163                 }
1164                 else {
1165                         switch (ainfo->storage) {
1166                         case ArgInIReg:
1167                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1168                                 break;
1169                         case ArgInFloatReg:
1170                         case ArgInFloatRegR4:
1171                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1172                                 break;
1173                         case ArgOnStack:
1174                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1175                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1176                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1177                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1178                                 else
1179                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1180                                 break;
1181                         default:
1182                                 g_assert_not_reached ();
1183                         }
1184                 }
1185         }
1186
1187         /* Handle the case where there are no implicit arguments */
1188         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1189                 emit_sig_cookie (cfg, call, cinfo);
1190         }
1191
1192         call->stack_usage = cinfo->stack_usage;
1193         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1194 }
1195
1196 void
1197 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1198 {
1199         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1200         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1201         int size = ins->backend.size;
1202
1203         if (ainfo->storage == ArgAggregate) {
1204                 MonoInst *load, *store;
1205                 int i, slot;
1206
1207                 /*
1208                  * Part of the structure is passed in registers.
1209                  */
1210                 for (i = 0; i < ainfo->nregs; ++i) {
1211                         slot = ainfo->reg + i;
1212
1213                         if (ainfo->atype == AggregateSingleHFA) {
1214                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1215                                 load->inst_basereg = src->dreg;
1216                                 load->inst_offset = i * 4;
1217                                 load->dreg = mono_alloc_freg (cfg);
1218
1219                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1220                         } else if (ainfo->atype == AggregateDoubleHFA) {
1221                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1222                                 load->inst_basereg = src->dreg;
1223                                 load->inst_offset = i * 8;
1224                                 load->dreg = mono_alloc_freg (cfg);
1225
1226                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1227                         } else {
1228                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1229                                 load->inst_basereg = src->dreg;
1230                                 load->inst_offset = i * 8;
1231                                 load->dreg = mono_alloc_ireg (cfg);
1232
1233                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1234                         }
1235                         MONO_ADD_INS (cfg->cbb, load);
1236                 }
1237
1238                 /*
1239                  * Part of the structure is passed on the stack.
1240                  */
1241                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1242                         slot = ainfo->reg + i;
1243
1244                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1245                         load->inst_basereg = src->dreg;
1246                         load->inst_offset = i * sizeof (gpointer);
1247                         load->dreg = mono_alloc_preg (cfg);
1248                         MONO_ADD_INS (cfg->cbb, load);
1249
1250                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1251                         store->sreg1 = load->dreg;
1252                         store->inst_destbasereg = IA64_SP;
1253                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1254                         MONO_ADD_INS (cfg->cbb, store);
1255                 }
1256         } else {
1257                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1258         }
1259 }
1260
1261 void
1262 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1263 {
1264         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1265
1266         switch (cinfo->ret.storage) {
1267         case ArgInIReg:
1268                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1269                 break;
1270         case ArgInFloatReg:
1271                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1272                 break;
1273         default:
1274                 g_assert_not_reached ();
1275         }
1276 }
1277
1278 void
1279 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1280 {
1281 }
1282
1283 void
1284 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1285 {
1286         MonoInst *ins, *n, *last_ins = NULL;
1287         ins = bb->code;
1288
1289         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1290                 switch (ins->opcode) {
1291                 case OP_MOVE:
1292                 case OP_FMOVE:
1293                         /*
1294                          * Removes:
1295                          *
1296                          * OP_MOVE reg, reg
1297                          */
1298                         if (ins->dreg == ins->sreg1) {
1299                                 MONO_DELETE_INS (bb, ins);
1300                                 continue;
1301                         }
1302                         /*
1303                          * Removes:
1304                          *
1305                          * OP_MOVE sreg, dreg
1306                          * OP_MOVE dreg, sreg
1307                          */
1308                         if (last_ins && last_ins->opcode == OP_MOVE &&
1309                             ins->sreg1 == last_ins->dreg &&
1310                             ins->dreg == last_ins->sreg1) {
1311                                 MONO_DELETE_INS (bb, ins);
1312                                 continue;
1313                         }
1314                         break;
1315                 case OP_MUL_IMM:
1316                 case OP_IMUL_IMM:
1317                         /* remove unnecessary multiplication with 1 */
1318                         if (ins->inst_imm == 1) {
1319                                 if (ins->dreg != ins->sreg1) {
1320                                         ins->opcode = OP_MOVE;
1321                                 } else {
1322                                         MONO_DELETE_INS (bb, ins);
1323                                         continue;
1324                                 }
1325                         }
1326                         break;
1327                 }
1328
1329                 last_ins = ins;
1330                 ins = ins->next;
1331         }
1332         bb->last_ins = last_ins;
1333 }
1334
1335 int cond_to_ia64_cmp [][3] = {
1336         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1337         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1338         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1339         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1340         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1341         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1342         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1343         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1344         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1345         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1346 };
1347
1348 static int
1349 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1350 {
1351         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1352 }
1353
1354 int cond_to_ia64_cmp_imm [][3] = {
1355         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1356         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1357         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1358         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1359         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1360         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1361         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1362         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1363         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1364         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1365 };
1366
1367 static int
1368 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1369 {
1370         /* The condition needs to be reversed */
1371         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1372 }
1373
1374 #define NEW_INS(cfg,dest,op) do {       \
1375                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1376                 (dest)->opcode = (op);  \
1377         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1378         last_ins = (dest); \
1379         } while (0)
1380
1381 /*
1382  * mono_arch_lowering_pass:
1383  *
1384  *  Converts complex opcodes into simpler ones so that each IR instruction
1385  * corresponds to one machine instruction.
1386  */
1387 void
1388 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1389 {
1390         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1391         ins = bb->code;
1392
1393         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1394                 switch (ins->opcode) {
1395                 case OP_STOREI1_MEMBASE_IMM:
1396                 case OP_STOREI2_MEMBASE_IMM:
1397                 case OP_STOREI4_MEMBASE_IMM:
1398                 case OP_STOREI8_MEMBASE_IMM:
1399                 case OP_STORE_MEMBASE_IMM:
1400                         /* There are no store_membase instructions on ia64 */
1401                         if (ins->inst_offset == 0) {
1402                                 temp2 = NULL;
1403                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1404                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1405                                 temp2->sreg1 = ins->inst_destbasereg;
1406                                 temp2->inst_imm = ins->inst_offset;
1407                                 temp2->dreg = mono_alloc_ireg (cfg);
1408                         }
1409                         else {
1410                                 NEW_INS (cfg, temp, OP_I8CONST);
1411                                 temp->inst_c0 = ins->inst_offset;
1412                                 temp->dreg = mono_alloc_ireg (cfg);
1413
1414                                 NEW_INS (cfg, temp2, OP_LADD);
1415                                 temp2->sreg1 = ins->inst_destbasereg;
1416                                 temp2->sreg2 = temp->dreg;
1417                                 temp2->dreg = mono_alloc_ireg (cfg);
1418                         }
1419
1420                         switch (ins->opcode) {
1421                         case OP_STOREI1_MEMBASE_IMM:
1422                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1423                                 break;
1424                         case OP_STOREI2_MEMBASE_IMM:
1425                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1426                                 break;
1427                         case OP_STOREI4_MEMBASE_IMM:
1428                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1429                                 break;
1430                         case OP_STOREI8_MEMBASE_IMM:
1431                         case OP_STORE_MEMBASE_IMM:
1432                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1433                                 break;
1434                         default:
1435                                 g_assert_not_reached ();
1436                         }
1437
1438                         if (ins->inst_imm == 0)
1439                                 ins->sreg1 = IA64_R0;
1440                         else {
1441                                 NEW_INS (cfg, temp3, OP_I8CONST);
1442                                 temp3->inst_c0 = ins->inst_imm;
1443                                 temp3->dreg = mono_alloc_ireg (cfg);
1444                                 ins->sreg1 = temp3->dreg;
1445                         }
1446
1447                         ins->inst_offset = 0;
1448                         if (temp2)
1449                                 ins->inst_destbasereg = temp2->dreg;
1450                         break;
1451                 case OP_STOREI1_MEMBASE_REG:
1452                 case OP_STOREI2_MEMBASE_REG:
1453                 case OP_STOREI4_MEMBASE_REG:
1454                 case OP_STOREI8_MEMBASE_REG:
1455                 case OP_STORER4_MEMBASE_REG:
1456                 case OP_STORER8_MEMBASE_REG:
1457                 case OP_STORE_MEMBASE_REG:
1458                         /* There are no store_membase instructions on ia64 */
1459                         if (ins->inst_offset == 0) {
1460                                 break;
1461                         }
1462                         else if (ia64_is_imm14 (ins->inst_offset)) {
1463                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1464                                 temp2->sreg1 = ins->inst_destbasereg;
1465                                 temp2->inst_imm = ins->inst_offset;
1466                                 temp2->dreg = mono_alloc_ireg (cfg);
1467                         }
1468                         else {
1469                                 NEW_INS (cfg, temp, OP_I8CONST);
1470                                 temp->inst_c0 = ins->inst_offset;
1471                                 temp->dreg = mono_alloc_ireg (cfg);
1472                                 NEW_INS (cfg, temp2, OP_LADD);
1473                                 temp2->sreg1 = ins->inst_destbasereg;
1474                                 temp2->sreg2 = temp->dreg;
1475                                 temp2->dreg = mono_alloc_ireg (cfg);
1476                         }
1477
1478                         ins->inst_offset = 0;
1479                         ins->inst_destbasereg = temp2->dreg;
1480                         break;
1481                 case OP_LOADI1_MEMBASE:
1482                 case OP_LOADU1_MEMBASE:
1483                 case OP_LOADI2_MEMBASE:
1484                 case OP_LOADU2_MEMBASE:
1485                 case OP_LOADI4_MEMBASE:
1486                 case OP_LOADU4_MEMBASE:
1487                 case OP_LOADI8_MEMBASE:
1488                 case OP_LOAD_MEMBASE:
1489                 case OP_LOADR4_MEMBASE:
1490                 case OP_LOADR8_MEMBASE:
1491                 case OP_ATOMIC_EXCHANGE_I4:
1492                 case OP_ATOMIC_EXCHANGE_I8:
1493                 case OP_ATOMIC_ADD_I4:
1494                 case OP_ATOMIC_ADD_I8:
1495                 case OP_ATOMIC_ADD_IMM_I4:
1496                 case OP_ATOMIC_ADD_IMM_I8:
1497                         /* There are no membase instructions on ia64 */
1498                         if (ins->inst_offset == 0) {
1499                                 break;
1500                         }
1501                         else if (ia64_is_imm14 (ins->inst_offset)) {
1502                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1503                                 temp2->sreg1 = ins->inst_basereg;
1504                                 temp2->inst_imm = ins->inst_offset;
1505                                 temp2->dreg = mono_alloc_ireg (cfg);
1506                         }
1507                         else {
1508                                 NEW_INS (cfg, temp, OP_I8CONST);
1509                                 temp->inst_c0 = ins->inst_offset;
1510                                 temp->dreg = mono_alloc_ireg (cfg);
1511                                 NEW_INS (cfg, temp2, OP_LADD);
1512                                 temp2->sreg1 = ins->inst_basereg;
1513                                 temp2->sreg2 = temp->dreg;
1514                                 temp2->dreg = mono_alloc_ireg (cfg);
1515                         }
1516
1517                         ins->inst_offset = 0;
1518                         ins->inst_basereg = temp2->dreg;
1519                         break;
1520                 case OP_ADD_IMM:
1521                 case OP_IADD_IMM:
1522                 case OP_LADD_IMM:
1523                 case OP_ISUB_IMM:
1524                 case OP_LSUB_IMM:
1525                 case OP_AND_IMM:
1526                 case OP_IAND_IMM:
1527                 case OP_LAND_IMM:
1528                 case OP_IOR_IMM:
1529                 case OP_LOR_IMM:
1530                 case OP_IXOR_IMM:
1531                 case OP_LXOR_IMM:
1532                 case OP_SHL_IMM:
1533                 case OP_SHR_IMM:
1534                 case OP_ISHL_IMM:
1535                 case OP_LSHL_IMM:
1536                 case OP_ISHR_IMM:
1537                 case OP_LSHR_IMM:
1538                 case OP_ISHR_UN_IMM:
1539                 case OP_LSHR_UN_IMM: {
1540                         gboolean is_imm = FALSE;
1541                         gboolean switched = FALSE;
1542
1543                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1544                                 ins->opcode = OP_ZEXT_I1;
1545                                 break;
1546                         }
1547
1548                         switch (ins->opcode) {
1549                         case OP_ADD_IMM:
1550                         case OP_IADD_IMM:
1551                         case OP_LADD_IMM:
1552                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1553                                 switched = TRUE;
1554                                 break;
1555                         case OP_ISUB_IMM:
1556                         case OP_LSUB_IMM:
1557                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1558                                 if (is_imm) {
1559                                         /* A = B - IMM -> A = B + (-IMM) */
1560                                         ins->inst_imm = - ins->inst_imm;
1561                                         ins->opcode = OP_IADD_IMM;
1562                                 }
1563                                 switched = TRUE;
1564                                 break;
1565                         case OP_IAND_IMM:
1566                         case OP_IOR_IMM:
1567                         case OP_IXOR_IMM:
1568                         case OP_AND_IMM:
1569                         case OP_LAND_IMM:
1570                         case OP_LOR_IMM:
1571                         case OP_LXOR_IMM:
1572                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1573                                 switched = TRUE;
1574                                 break;
1575                         case OP_SHL_IMM:
1576                         case OP_SHR_IMM:
1577                         case OP_ISHL_IMM:
1578                         case OP_LSHL_IMM:
1579                         case OP_ISHR_IMM:
1580                         case OP_LSHR_IMM:
1581                         case OP_ISHR_UN_IMM:
1582                         case OP_LSHR_UN_IMM:
1583                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1584                                 break;
1585                         default:
1586                                 break;
1587                         }
1588
1589                         if (is_imm) {
1590                                 if (switched)
1591                                         ins->sreg2 = ins->sreg1;
1592                                 break;
1593                         }
1594
1595                         if (mono_op_imm_to_op (ins->opcode) == -1)
1596                                 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
1597                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1598
1599                         if (ins->inst_imm == 0)
1600                                 ins->sreg2 = IA64_R0;
1601                         else {
1602                                 NEW_INS (cfg, temp, OP_I8CONST);
1603                                 temp->inst_c0 = ins->inst_imm;
1604                                 temp->dreg = mono_alloc_ireg (cfg);
1605                                 ins->sreg2 = temp->dreg;
1606                         }
1607                         break;
1608                 }
1609                 case OP_COMPARE_IMM:
1610                 case OP_ICOMPARE_IMM:
1611                 case OP_LCOMPARE_IMM: {
1612                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1613                         gboolean imm;
1614                         CompRelation cond;
1615
1616                         next = ins->next;
1617
1618                         /* Branch opts can eliminate the branch */
1619                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1620                                 NULLIFY_INS (ins);
1621                                 break;
1622                         }
1623
1624                         /*
1625                          * The compare_imm instructions have switched up arguments, and
1626                          * some of them take an imm between -127 and 128.
1627                          */
1628                         next = ins->next;
1629                         cond = mono_opcode_to_cond (next->opcode);
1630                         if ((cond == CMP_LT) || (cond == CMP_GE))
1631                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1632                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1633                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1634                         else
1635                                 imm = ia64_is_imm8 (ins->inst_imm);
1636
1637                         if (imm) {
1638                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1639                                 ins->sreg2 = ins->sreg1;
1640                         }
1641                         else {
1642                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1643
1644                                 if (ins->inst_imm == 0)
1645                                         ins->sreg2 = IA64_R0;
1646                                 else {
1647                                         NEW_INS (cfg, temp, OP_I8CONST);
1648                                         temp->inst_c0 = ins->inst_imm;
1649                                         temp->dreg = mono_alloc_ireg (cfg);
1650                                         ins->sreg2 = temp->dreg;
1651                                 }
1652                         }
1653
1654                         if (MONO_IS_COND_BRANCH_OP (next)) {
1655                                 next->opcode = OP_IA64_BR_COND;
1656                                 next->inst_target_bb = next->inst_true_bb;
1657                         } else if (MONO_IS_COND_EXC (next)) {
1658                                 next->opcode = OP_IA64_COND_EXC;
1659                         } else if (MONO_IS_SETCC (next)) {
1660                                 next->opcode = OP_IA64_CSET;
1661                         } else {
1662                                 printf ("%s\n", mono_inst_name (next->opcode));
1663                                 NOT_IMPLEMENTED;
1664                         }
1665
1666                         break;
1667                 }
1668                 case OP_COMPARE:
1669                 case OP_ICOMPARE:
1670                 case OP_LCOMPARE:
1671                 case OP_FCOMPARE: {
1672                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1673
1674                         next = ins->next;
1675
1676                         /* Branch opts can eliminate the branch */
1677                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1678                                 NULLIFY_INS (ins);
1679                                 break;
1680                         }
1681
1682                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1683
1684                         if (MONO_IS_COND_BRANCH_OP (next)) {
1685                                 next->opcode = OP_IA64_BR_COND;
1686                                 next->inst_target_bb = next->inst_true_bb;
1687                         } else if (MONO_IS_COND_EXC (next)) {
1688                                 next->opcode = OP_IA64_COND_EXC;
1689                         } else if (MONO_IS_SETCC (next)) {
1690                                 next->opcode = OP_IA64_CSET;
1691                         } else {
1692                                 printf ("%s\n", mono_inst_name (next->opcode));
1693                                 NOT_IMPLEMENTED;
1694                         }
1695
1696                         break;
1697                 }
1698                 case OP_FCEQ:
1699                 case OP_FCGT:
1700                 case OP_FCGT_UN:
1701                 case OP_FCLT:
1702                 case OP_FCLT_UN:
1703                         /* The front end removes the fcompare, so introduce it again */
1704                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1705                         temp->sreg1 = ins->sreg1;
1706                         temp->sreg2 = ins->sreg2;
1707
1708                         ins->opcode = OP_IA64_CSET;
1709                         MONO_INST_NULLIFY_SREGS (ins);
1710                         break;
1711                 case OP_MUL_IMM:
1712                 case OP_LMUL_IMM:
1713                 case OP_IMUL_IMM: {
1714                         int i, sum_reg;
1715                         gboolean found = FALSE;
1716                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1717
1718                         /* First the easy cases */
1719                         if (ins->inst_imm == 1) {
1720                                 ins->opcode = OP_MOVE;
1721                                 break;
1722                         }
1723                         for (i = 1; i < 64; ++i)
1724                                 if (ins->inst_imm == (((gint64)1) << i)) {
1725                                         ins->opcode = shl_op;
1726                                         ins->inst_imm = i;
1727                                         found = TRUE;
1728                                         break;
1729                                 }
1730
1731                         /* This could be optimized */
1732                         if (!found) {
1733                                 sum_reg = 0;
1734                                 for (i = 0; i < 64; ++i) {
1735                                         if (ins->inst_imm & (((gint64)1) << i)) {
1736                                                 NEW_INS (cfg, temp, shl_op);
1737                                                 temp->dreg = mono_alloc_ireg (cfg);
1738                                                 temp->sreg1 = ins->sreg1;
1739                                                 temp->inst_imm = i;
1740
1741                                                 if (sum_reg == 0)
1742                                                         sum_reg = temp->dreg;
1743                                                 else {
1744                                                         NEW_INS (cfg, temp2, OP_LADD);
1745                                                         temp2->dreg = mono_alloc_ireg (cfg);
1746                                                         temp2->sreg1 = sum_reg;
1747                                                         temp2->sreg2 = temp->dreg;
1748                                                         sum_reg = temp2->dreg;
1749                                                 }
1750                                         }
1751                                 }
1752                                 ins->opcode = OP_MOVE;
1753                                 ins->sreg1 = sum_reg;
1754                         }
1755                         break;
1756                 }
1757                 case OP_LCONV_TO_OVF_U4:
1758                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1759                         temp->sreg1 = ins->sreg1;
1760                         temp->sreg2 = IA64_R0;
1761
1762                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1763                         temp->inst_p1 = (char*)"OverflowException";
1764
1765                         ins->opcode = OP_MOVE;
1766                         break;
1767                 case OP_LCONV_TO_OVF_I4_UN:
1768                         NEW_INS (cfg, temp, OP_ICONST);
1769                         temp->inst_c0 = 0x7fffffff;
1770                         temp->dreg = mono_alloc_ireg (cfg);
1771
1772                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1773                         temp2->sreg1 = ins->sreg1;
1774                         temp2->sreg2 = temp->dreg;
1775
1776                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1777                         temp->inst_p1 = (char*)"OverflowException";
1778
1779                         ins->opcode = OP_MOVE;
1780                         break;
1781                 case OP_FCONV_TO_I4:
1782                 case OP_FCONV_TO_I2:
1783                 case OP_FCONV_TO_U2:
1784                 case OP_FCONV_TO_I1:
1785                 case OP_FCONV_TO_U1:
1786                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1787                         temp->sreg1 = ins->sreg1;
1788                         temp->dreg = ins->dreg;
1789
1790                         switch (ins->opcode) {
1791                         case OP_FCONV_TO_I4:
1792                                 ins->opcode = OP_SEXT_I4;
1793                                 break;
1794                         case OP_FCONV_TO_I2:
1795                                 ins->opcode = OP_SEXT_I2;
1796                                 break;
1797                         case OP_FCONV_TO_U2:
1798                                 ins->opcode = OP_ZEXT_I4;
1799                                 break;
1800                         case OP_FCONV_TO_I1:
1801                                 ins->opcode = OP_SEXT_I1;
1802                                 break;
1803                         case OP_FCONV_TO_U1:
1804                                 ins->opcode = OP_ZEXT_I1;
1805                                 break;
1806                         default:
1807                                 g_assert_not_reached ();
1808                         }
1809                         ins->sreg1 = ins->dreg;
1810                         break;
1811                 default:
1812                         break;
1813                 }
1814                 last_ins = ins;
1815                 ins = ins->next;
1816         }
1817         bb->last_ins = last_ins;
1818
1819         bb->max_vreg = cfg->next_vreg;
1820 }
1821
1822 /*
1823  * emit_load_volatile_arguments:
1824  *
1825  *  Load volatile arguments from the stack to the original input registers.
1826  * Required before a tail call.
1827  */
1828 static Ia64CodegenState
1829 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1830 {
1831         MonoMethod *method = cfg->method;
1832         MonoMethodSignature *sig;
1833         MonoInst *ins;
1834         CallInfo *cinfo;
1835         guint32 i;
1836
1837         /* FIXME: Generate intermediate code instead */
1838
1839         sig = mono_method_signature (method);
1840
1841         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1842
1843         /* This is the opposite of the code in emit_prolog */
1844         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1845                 ArgInfo *ainfo = cinfo->args + i;
1846                 gint32 stack_offset;
1847                 MonoType *arg_type;
1848
1849                 ins = cfg->args [i];
1850
1851                 if (sig->hasthis && (i == 0))
1852                         arg_type = &mono_defaults.object_class->byval_arg;
1853                 else
1854                         arg_type = sig->params [i - sig->hasthis];
1855
1856                 arg_type = mini_get_underlying_type (arg_type);
1857
1858                 stack_offset = ainfo->offset + ARGS_OFFSET;
1859
1860                 /* Save volatile arguments to the stack */
1861                 if (ins->opcode != OP_REGVAR) {
1862                         switch (ainfo->storage) {
1863                         case ArgInIReg:
1864                         case ArgInFloatReg:
1865                                 /* FIXME: big offsets */
1866                                 g_assert (ins->opcode == OP_REGOFFSET);
1867                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1868                                 if (arg_type->byref)
1869                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1870                                 else {
1871                                         switch (arg_type->type) {
1872                                         case MONO_TYPE_R4:
1873                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1874                                                 break;
1875                                         case MONO_TYPE_R8:
1876                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1877                                                 break;
1878                                         default:
1879                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1880                                                 break;
1881                                         }
1882                                 }
1883                                 break;
1884                         case ArgOnStack:
1885                                 break;
1886                         default:
1887                                 NOT_IMPLEMENTED;
1888                         }
1889                 }
1890
1891                 if (ins->opcode == OP_REGVAR) {
1892                         /* Argument allocated to (non-volatile) register */
1893                         switch (ainfo->storage) {
1894                         case ArgInIReg:
1895                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1896                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1897                                 break;
1898                         case ArgOnStack:
1899                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1900                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1901                                 break;
1902                         default:
1903                                 NOT_IMPLEMENTED;
1904                         }
1905                 }
1906         }
1907
1908         return code;
1909 }
1910
1911 static Ia64CodegenState
1912 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1913 {
1914         CallInfo *cinfo;
1915         int i;
1916
1917         /* Move return value to the target register */
1918         switch (ins->opcode) {
1919         case OP_VOIDCALL:
1920         case OP_VOIDCALL_REG:
1921         case OP_VOIDCALL_MEMBASE:
1922                 break;
1923         case OP_CALL:
1924         case OP_CALL_REG:
1925         case OP_CALL_MEMBASE:
1926         case OP_LCALL:
1927         case OP_LCALL_REG:
1928         case OP_LCALL_MEMBASE:
1929                 g_assert (ins->dreg == IA64_R8);
1930                 break;
1931         case OP_FCALL:
1932         case OP_FCALL_REG:
1933         case OP_FCALL_MEMBASE:
1934                 g_assert (ins->dreg == 8);
1935                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1936                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1937                 break;
1938         case OP_VCALL:
1939         case OP_VCALL_REG:
1940         case OP_VCALL_MEMBASE:
1941         case OP_VCALL2:
1942         case OP_VCALL2_REG:
1943         case OP_VCALL2_MEMBASE: {
1944                 ArgStorage storage;
1945
1946                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1947                 storage = cinfo->ret.storage;
1948
1949                 if (storage == ArgAggregate) {
1950                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1951
1952                         /* Load address of stack space allocated for the return value */
1953                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1954                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1955                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1956
1957                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1958                                 switch (cinfo->ret.atype) {
1959                                 case AggregateNormal:
1960                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1961                                         break;
1962                                 case AggregateSingleHFA:
1963                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1964                                         break;
1965                                 case AggregateDoubleHFA:
1966                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1967                                         break;
1968                                 default:
1969                                         g_assert_not_reached ();
1970                                 }
1971                         }
1972                 }
1973                 break;
1974         }
1975         default:
1976                 g_assert_not_reached ();
1977         }
1978
1979         return code;
1980 }
1981
1982 #define add_patch_info(cfg,code,patch_type,data) do { \
1983         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1984 } while (0)
1985
1986 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1987         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1988     if (tins == NULL) \
1989         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1990     else \
1991                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1992         ia64_br_cond_pred (code, (predicate), 0); \
1993 } while (0)
1994
1995 static Ia64CodegenState
1996 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1997 {
1998         add_patch_info (cfg, code, patch_type, data);
1999
2000         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
2001                 /* Indirect call */
2002                 /* mono_arch_patch_callsite will patch this */
2003                 ia64_movl (code, GP_SCRATCH_REG, 0);
2004                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
2005                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2006                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2007                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2008         }
2009         else {
2010                 /* Can't use a direct call since the displacement might be too small */
2011                 /* mono_arch_patch_callsite will patch this */
2012                 ia64_movl (code, GP_SCRATCH_REG, 0);
2013                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2014                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2015         }
2016
2017         return code;
2018 }
2019
2020 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2021
2022 void
2023 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2024 {
2025         MonoInst *ins;
2026         MonoCallInst *call;
2027         guint offset;
2028         Ia64CodegenState code;
2029         guint8 *code_start = cfg->native_code + cfg->code_len;
2030         MonoInst *last_ins = NULL;
2031         guint last_offset = 0;
2032         int max_len, cpos;
2033
2034         if (cfg->opt & MONO_OPT_LOOP) {
2035                 /* FIXME: */
2036         }
2037
2038         if (cfg->verbose_level > 2)
2039                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2040
2041         cpos = bb->max_offset;
2042
2043         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2044                 NOT_IMPLEMENTED;
2045         }
2046
2047         offset = code_start - cfg->native_code;
2048
2049         ia64_codegen_init (code, code_start);
2050
2051 #if 0
2052         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2053                 break_count ();
2054 #endif
2055
2056         MONO_BB_FOR_EACH_INS (bb, ins) {
2057                 offset = code.buf - cfg->native_code;
2058
2059                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2060
2061                 while (offset + max_len + 16 > cfg->code_size) {
2062                         ia64_codegen_close (code);
2063
2064                         offset = code.buf - cfg->native_code;
2065
2066                         cfg->code_size *= 2;
2067                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2068                         code_start = cfg->native_code + offset;
2069                         cfg->stat_code_reallocs++;
2070
2071                         ia64_codegen_init (code, code_start);
2072                 }
2073
2074                 mono_debug_record_line_number (cfg, ins, offset);
2075
2076                 switch (ins->opcode) {
2077                 case OP_ICONST:
2078                 case OP_I8CONST:
2079                         if (ia64_is_imm14 (ins->inst_c0))
2080                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2081                         else
2082                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2083                         break;
2084                 case OP_JUMP_TABLE:
2085                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2086                         ia64_movl (code, ins->dreg, 0);
2087                         break;
2088                 case OP_MOVE:
2089                         ia64_mov (code, ins->dreg, ins->sreg1);
2090                         break;
2091                 case OP_BR:
2092                 case OP_IA64_BR_COND: {
2093                         int pred = 0;
2094                         if (ins->opcode == OP_IA64_BR_COND)
2095                                 pred = 6;
2096                         if (ins->inst_target_bb->native_offset) {
2097                                 guint8 *pos = code.buf + code.nins;
2098
2099                                 ia64_br_cond_pred (code, pred, 0);
2100                                 ia64_begin_bundle (code);
2101                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2102                         } else {
2103                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2104                                 ia64_br_cond_pred (code, pred, 0);
2105                         }
2106                         break;
2107                 }
2108                 case OP_LABEL:
2109                         ia64_begin_bundle (code);
2110                         ins->inst_c0 = code.buf - cfg->native_code;
2111                         break;
2112                 case OP_NOP:
2113                 case OP_RELAXED_NOP:
2114                 case OP_DUMMY_USE:
2115                 case OP_DUMMY_STORE:
2116                 case OP_NOT_REACHED:
2117                 case OP_NOT_NULL:
2118                         break;
2119                 case OP_BR_REG:
2120                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2121                         ia64_br_cond_reg (code, IA64_B6);
2122                         break;
2123                 case OP_IADD:
2124                 case OP_LADD:
2125                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2126                         break;
2127                 case OP_ISUB:
2128                 case OP_LSUB:
2129                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2130                         break;
2131                 case OP_IAND:
2132                 case OP_LAND:
2133                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2134                         break;
2135                 case OP_IOR:
2136                 case OP_LOR:
2137                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2138                         break;
2139                 case OP_IXOR:
2140                 case OP_LXOR:
2141                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2142                         break;
2143                 case OP_INEG:
2144                 case OP_LNEG:
2145                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2146                         break;
2147                 case OP_INOT:
2148                 case OP_LNOT:
2149                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2150                         break;
2151                 case OP_ISHL:
2152                 case OP_LSHL:
2153                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2154                         break;
2155                 case OP_ISHR:
2156                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2157                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2158                         break;
2159                 case OP_LSHR:
2160                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2161                         break;
2162                 case OP_ISHR_UN:
2163                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2164                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2165                         break;
2166                 case OP_LSHR_UN:
2167                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2168                         break;
2169                 case OP_IADDCC:
2170                         /* p6 and p7 is set if there is signed/unsigned overflow */
2171
2172                         /* Set p8-p9 == (sreg2 > 0) */
2173                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2174
2175                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2176
2177                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2178                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2179                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2180                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2181
2182                         /* res <u sreg1 => unsigned overflow */
2183                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2184
2185                         /* FIXME: Predicate this since this is a side effect */
2186                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2187                         break;
2188                 case OP_ISUBCC:
2189                         /* p6 and p7 is set if there is signed/unsigned overflow */
2190
2191                         /* Set p8-p9 == (sreg2 > 0) */
2192                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2193
2194                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2195
2196                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2197                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2198                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2199                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2200
2201                         /* sreg1 <u sreg2 => unsigned overflow */
2202                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2203
2204                         /* FIXME: Predicate this since this is a side effect */
2205                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2206                         break;
2207                 case OP_ADDCC:
2208                         /* Same as OP_IADDCC */
2209                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2210
2211                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2212
2213                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2214                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2215
2216                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2217
2218                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2219                         break;
2220                 case OP_SUBCC:
2221                         /* Same as OP_ISUBCC */
2222
2223                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2224
2225                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2226
2227                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2228                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2229
2230                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2231
2232                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2233                         break;
2234                 case OP_ADD_IMM:
2235                 case OP_IADD_IMM:
2236                 case OP_LADD_IMM:
2237                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2238                         break;
2239                 case OP_IAND_IMM:
2240                 case OP_AND_IMM:
2241                 case OP_LAND_IMM:
2242                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2243                         break;
2244                 case OP_IOR_IMM:
2245                 case OP_LOR_IMM:
2246                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2247                         break;
2248                 case OP_IXOR_IMM:
2249                 case OP_LXOR_IMM:
2250                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2251                         break;
2252                 case OP_SHL_IMM:
2253                 case OP_ISHL_IMM:
2254                 case OP_LSHL_IMM:
2255                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2256                         break;
2257                 case OP_SHR_IMM:
2258                 case OP_LSHR_IMM:
2259                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2260                         break;
2261                 case OP_ISHR_IMM:
2262                         g_assert (ins->inst_imm <= 64);
2263                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2264                         break;
2265                 case OP_ISHR_UN_IMM:
2266                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2267                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2268                         break;
2269                 case OP_LSHR_UN_IMM:
2270                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2271                         break;
2272                 case OP_LMUL:
2273                         /* Based on gcc code */
2274                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2275                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2276                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2277                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2278                         break;
2279
2280                 case OP_STOREI1_MEMBASE_REG:
2281                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2282                         break;
2283                 case OP_STOREI2_MEMBASE_REG:
2284                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2285                         break;
2286                 case OP_STOREI4_MEMBASE_REG:
2287                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2288                         break;
2289                 case OP_STOREI8_MEMBASE_REG:
2290                 case OP_STORE_MEMBASE_REG:
2291                         if (ins->inst_offset != 0) {
2292                                 /* This is generated by local regalloc */
2293                                 if (ia64_is_imm14 (ins->inst_offset)) {
2294                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2295                                 } else {
2296                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2297                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2298                                 }
2299                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2300                         }
2301                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2302                         break;
2303
2304                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2305                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2306                         break;
2307                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2308                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2309                         break;
2310                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2311                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2312                         break;
2313                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2314                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2315                         break;
2316
2317                 case OP_LOADU1_MEMBASE:
2318                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2319                         break;
2320                 case OP_LOADU2_MEMBASE:
2321                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2322                         break;
2323                 case OP_LOADU4_MEMBASE:
2324                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2325                         break;
2326                 case OP_LOADI1_MEMBASE:
2327                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2328                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2329                         break;
2330                 case OP_LOADI2_MEMBASE:
2331                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2332                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2333                         break;
2334                 case OP_LOADI4_MEMBASE:
2335                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2336                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2337                         break;
2338                 case OP_LOAD_MEMBASE:
2339                 case OP_LOADI8_MEMBASE:
2340                         if (ins->inst_offset != 0) {
2341                                 /* This is generated by local regalloc */
2342                                 if (ia64_is_imm14 (ins->inst_offset)) {
2343                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2344                                 } else {
2345                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2346                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2347                                 }
2348                                 ins->inst_basereg = GP_SCRATCH_REG;
2349                         }
2350                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2351                         break;
2352
2353                 case OP_IA64_LOADU1_MEMBASE_INC:
2354                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2355                         break;
2356                 case OP_IA64_LOADU2_MEMBASE_INC:
2357                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2358                         break;
2359                 case OP_IA64_LOADU4_MEMBASE_INC:
2360                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2361                         break;
2362                 case OP_IA64_LOADI8_MEMBASE_INC:
2363                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2364                         break;
2365
2366                 case OP_SEXT_I1:
2367                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2368                         break;
2369                 case OP_SEXT_I2:
2370                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2371                         break;
2372                 case OP_SEXT_I4:
2373                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2374                         break;
2375                 case OP_ZEXT_I1:
2376                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2377                         break;
2378                 case OP_ZEXT_I2:
2379                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2380                         break;
2381                 case OP_ZEXT_I4:
2382                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2383                         break;
2384
2385                         /* Compare opcodes */
2386                 case OP_IA64_CMP4_EQ:
2387                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2388                         break;
2389                 case OP_IA64_CMP4_NE:
2390                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2391                         break;
2392                 case OP_IA64_CMP4_LE:
2393                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2394                         break;
2395                 case OP_IA64_CMP4_LT:
2396                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2397                         break;
2398                 case OP_IA64_CMP4_GE:
2399                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2400                         break;
2401                 case OP_IA64_CMP4_GT:
2402                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2403                         break;
2404                 case OP_IA64_CMP4_LT_UN:
2405                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2406                         break;
2407                 case OP_IA64_CMP4_LE_UN:
2408                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2409                         break;
2410                 case OP_IA64_CMP4_GT_UN:
2411                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2412                         break;
2413                 case OP_IA64_CMP4_GE_UN:
2414                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2415                         break;
2416                 case OP_IA64_CMP_EQ:
2417                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2418                         break;
2419                 case OP_IA64_CMP_NE:
2420                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2421                         break;
2422                 case OP_IA64_CMP_LE:
2423                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2424                         break;
2425                 case OP_IA64_CMP_LT:
2426                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2427                         break;
2428                 case OP_IA64_CMP_GE:
2429                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2430                         break;
2431                 case OP_IA64_CMP_GT:
2432                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2433                         break;
2434                 case OP_IA64_CMP_GT_UN:
2435                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2436                         break;
2437                 case OP_IA64_CMP_LT_UN:
2438                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2439                         break;
2440                 case OP_IA64_CMP_GE_UN:
2441                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2442                         break;
2443                 case OP_IA64_CMP_LE_UN:
2444                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2445                         break;
2446                 case OP_IA64_CMP4_EQ_IMM:
2447                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2448                         break;
2449                 case OP_IA64_CMP4_NE_IMM:
2450                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2451                         break;
2452                 case OP_IA64_CMP4_LE_IMM:
2453                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2454                         break;
2455                 case OP_IA64_CMP4_LT_IMM:
2456                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2457                         break;
2458                 case OP_IA64_CMP4_GE_IMM:
2459                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2460                         break;
2461                 case OP_IA64_CMP4_GT_IMM:
2462                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2463                         break;
2464                 case OP_IA64_CMP4_LT_UN_IMM:
2465                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2466                         break;
2467                 case OP_IA64_CMP4_LE_UN_IMM:
2468                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2469                         break;
2470                 case OP_IA64_CMP4_GT_UN_IMM:
2471                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2472                         break;
2473                 case OP_IA64_CMP4_GE_UN_IMM:
2474                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2475                         break;
2476                 case OP_IA64_CMP_EQ_IMM:
2477                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2478                         break;
2479                 case OP_IA64_CMP_NE_IMM:
2480                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2481                         break;
2482                 case OP_IA64_CMP_LE_IMM:
2483                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2484                         break;
2485                 case OP_IA64_CMP_LT_IMM:
2486                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2487                         break;
2488                 case OP_IA64_CMP_GE_IMM:
2489                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2490                         break;
2491                 case OP_IA64_CMP_GT_IMM:
2492                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2493                         break;
2494                 case OP_IA64_CMP_GT_UN_IMM:
2495                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2496                         break;
2497                 case OP_IA64_CMP_LT_UN_IMM:
2498                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2499                         break;
2500                 case OP_IA64_CMP_GE_UN_IMM:
2501                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2502                         break;
2503                 case OP_IA64_CMP_LE_UN_IMM:
2504                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2505                         break;
2506                 case OP_IA64_FCMP_EQ:
2507                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2508                         break;
2509                 case OP_IA64_FCMP_NE:
2510                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2511                         break;
2512                 case OP_IA64_FCMP_LT:
2513                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2514                         break;
2515                 case OP_IA64_FCMP_GT:
2516                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2517                         break;
2518                 case OP_IA64_FCMP_LE:
2519                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2520                         break;
2521                 case OP_IA64_FCMP_GE:
2522                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2523                         break;
2524                 case OP_IA64_FCMP_GT_UN:
2525                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2526                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2527                         break;
2528                 case OP_IA64_FCMP_LT_UN:
2529                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2530                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2531                         break;
2532                 case OP_IA64_FCMP_GE_UN:
2533                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2534                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2535                         break;
2536                 case OP_IA64_FCMP_LE_UN:
2537                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2538                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2539                         break;
2540
2541                 case OP_COND_EXC_IOV:
2542                 case OP_COND_EXC_OV:
2543                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2544                         break;
2545                 case OP_COND_EXC_IC:
2546                 case OP_COND_EXC_C:
2547                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2548                         break;
2549                 case OP_IA64_COND_EXC:
2550                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2551                         break;
2552                 case OP_IA64_CSET:
2553                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2554                         ia64_no_stop (code);
2555                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2556                         break;
2557                 case OP_ICONV_TO_I1:
2558                 case OP_LCONV_TO_I1:
2559                         /* FIXME: Is this needed ? */
2560                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2561                         break;
2562                 case OP_ICONV_TO_I2:
2563                 case OP_LCONV_TO_I2:
2564                         /* FIXME: Is this needed ? */
2565                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2566                         break;
2567                 case OP_LCONV_TO_I4:
2568                         /* FIXME: Is this needed ? */
2569                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2570                         break;
2571                 case OP_ICONV_TO_U1:
2572                 case OP_LCONV_TO_U1:
2573                         /* FIXME: Is this needed */
2574                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2575                         break;
2576                 case OP_ICONV_TO_U2:
2577                 case OP_LCONV_TO_U2:
2578                         /* FIXME: Is this needed */
2579                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2580                         break;
2581                 case OP_LCONV_TO_U4:
2582                         /* FIXME: Is this needed */
2583                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2584                         break;
2585                 case OP_ICONV_TO_I8:
2586                 case OP_ICONV_TO_I:
2587                 case OP_LCONV_TO_I8:
2588                 case OP_LCONV_TO_I:
2589                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2590                         break;
2591                 case OP_LCONV_TO_U8:
2592                 case OP_LCONV_TO_U:
2593                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2594                         break;
2595
2596                         /*
2597                          * FLOAT OPCODES
2598                          */
2599                 case OP_R8CONST: {
2600                         double d = *(double *)ins->inst_p0;
2601
2602                         if ((d == 0.0) && (mono_signbit (d) == 0))
2603                                 ia64_fmov (code, ins->dreg, 0);
2604                         else if (d == 1.0)
2605                                 ia64_fmov (code, ins->dreg, 1);
2606                         else {
2607                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2608                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2609                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2610                         }
2611                         break;
2612                 }
2613                 case OP_R4CONST: {
2614                         float f = *(float *)ins->inst_p0;
2615
2616                         if ((f == 0.0) && (mono_signbit (f) == 0))
2617                                 ia64_fmov (code, ins->dreg, 0);
2618                         else if (f == 1.0)
2619                                 ia64_fmov (code, ins->dreg, 1);
2620                         else {
2621                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2622                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2623                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2624                         }
2625                         break;
2626                 }
2627                 case OP_FMOVE:
2628                         ia64_fmov (code, ins->dreg, ins->sreg1);
2629                         break;
2630                 case OP_STORER8_MEMBASE_REG:
2631                         if (ins->inst_offset != 0) {
2632                                 /* This is generated by local regalloc */
2633                                 if (ia64_is_imm14 (ins->inst_offset)) {
2634                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2635                                 } else {
2636                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2637                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2638                                 }
2639                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2640                         }
2641                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2642                         break;
2643                 case OP_STORER4_MEMBASE_REG:
2644                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2645                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2646                         break;
2647                 case OP_LOADR8_MEMBASE:
2648                         if (ins->inst_offset != 0) {
2649                                 /* This is generated by local regalloc */
2650                                 if (ia64_is_imm14 (ins->inst_offset)) {
2651                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2652                                 } else {
2653                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2654                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2655                                 }
2656                                 ins->inst_basereg = GP_SCRATCH_REG;
2657                         }
2658                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2659                         break;
2660                 case OP_LOADR4_MEMBASE:
2661                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2662                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2663                         break;
2664                 case OP_ICONV_TO_R4:
2665                 case OP_LCONV_TO_R4:
2666                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2667                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2668                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2669                         break;
2670                 case OP_ICONV_TO_R8:
2671                 case OP_LCONV_TO_R8:
2672                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2673                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2674                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2675                         break;
2676                 case OP_FCONV_TO_R4:
2677                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2678                         break;
2679                 case OP_FCONV_TO_I8:
2680                 case OP_FCONV_TO_I:
2681                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2682                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2683                         break;
2684                 case OP_FADD:
2685                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2686                         break;
2687                 case OP_FSUB:
2688                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2689                         break;
2690                 case OP_FMUL:
2691                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2692                         break;
2693                 case OP_FNEG:
2694                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2695                         break;
2696                 case OP_CKFINITE:
2697                         /* Quiet NaN */
2698                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2699                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2700                         /* Signaling NaN */
2701                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2702                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2703                         /* Positive infinity */
2704                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2705                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2706                         /* Negative infinity */
2707                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2708                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2709                         break;
2710
2711                 /* Calls */
2712                 case OP_CHECK_THIS:
2713                         /* ensure ins->sreg1 is not NULL */
2714                         /* Can't use ld8 as this could be a vtype address */
2715                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2716                         break;
2717                 case OP_ARGLIST:
2718                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2719                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2720                         break;
2721                 case OP_FCALL:
2722                 case OP_LCALL:
2723                 case OP_VCALL:
2724                 case OP_VCALL2:
2725                 case OP_VOIDCALL:
2726                 case OP_CALL:
2727                         call = (MonoCallInst*)ins;
2728
2729                         if (ins->flags & MONO_INST_HAS_METHOD)
2730                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2731                         else
2732                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2733
2734                         code = emit_move_return_value (cfg, ins, code);
2735                         break;
2736
2737                 case OP_CALL_REG:
2738                 case OP_FCALL_REG:
2739                 case OP_LCALL_REG:
2740                 case OP_VCALL_REG:
2741                 case OP_VCALL2_REG:
2742                 case OP_VOIDCALL_REG: {
2743                         MonoCallInst *call = (MonoCallInst*)ins;
2744                         CallInfo *cinfo;
2745                         int out_reg;
2746
2747                         /*
2748                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2749                          * register.
2750                          */
2751                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2752                         out_reg = cfg->arch.reg_out0;
2753                         ia64_mov (code, IA64_R10, out_reg);
2754
2755                         /* Indirect call */
2756                         ia64_mov (code, IA64_R8, ins->sreg1);
2757                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2758                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2759                         ia64_ld8 (code, IA64_GP, IA64_R8);
2760                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2761
2762                         code = emit_move_return_value (cfg, ins, code);
2763                         break;
2764                 }
2765                 case OP_FCALL_MEMBASE:
2766                 case OP_LCALL_MEMBASE:
2767                 case OP_VCALL_MEMBASE:
2768                 case OP_VCALL2_MEMBASE:
2769                 case OP_VOIDCALL_MEMBASE:
2770                 case OP_CALL_MEMBASE: {
2771                         MonoCallInst *call = (MonoCallInst*)ins;
2772                         CallInfo *cinfo;
2773                         int out_reg;
2774
2775                         ia64_mov (code, IA64_R11, ins->sreg1);
2776                         if (ia64_is_imm14 (ins->inst_offset))
2777                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2778                         else {
2779                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2780                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2781                         }
2782
2783                         if (call->method && ins->inst_offset < 0) {
2784                                 /*
2785                                  * This is a possible IMT call so save the IMT method in a global
2786                                  * register where mono_arch_find_imt_method () and its friends can
2787                                  * access it.
2788                                  */
2789                                 ia64_movl (code, IA64_R9, call->method);
2790                         }
2791
2792                         /*
2793                          * mono_arch_find_this_arg () needs to find the this argument in a global
2794                          * register.
2795                          */
2796                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2797                         out_reg = cfg->arch.reg_out0;
2798                         ia64_mov (code, IA64_R10, out_reg);
2799
2800                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2801
2802                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2803
2804                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2805
2806                         code = emit_move_return_value (cfg, ins, code);
2807                         break;
2808                 }
2809                 case OP_JMP: {
2810                         /*
2811                          * Keep in sync with the code in emit_epilog.
2812                          */
2813
2814                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2815                                 NOT_IMPLEMENTED;
2816
2817                         g_assert (!cfg->method->save_lmf);
2818
2819                         /* Load arguments into their original registers */
2820                         code = emit_load_volatile_arguments (cfg, code);
2821
2822                         if (cfg->arch.stack_alloc_size) {
2823                                 if (cfg->arch.omit_fp) {
2824                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2825                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2826                                         else {
2827                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2828                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2829                                         }
2830                                 }
2831                                 else
2832                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2833                         }
2834                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2835                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2836
2837                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2838                         ia64_movl (code, GP_SCRATCH_REG, 0);
2839                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2840                         ia64_br_cond_reg (code, IA64_B6);
2841
2842                         break;
2843                 }
2844                 case OP_BREAK:
2845                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2846                         break;
2847
2848                 case OP_LOCALLOC: {
2849                         gint32 abi_offset;
2850
2851                         /* FIXME: Sigaltstack support */
2852
2853                         /* keep alignment */
2854                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2855                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2856                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2857
2858                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2859
2860                         ia64_mov (code, ins->dreg, IA64_SP);
2861
2862                         /* An area at sp is reserved by the ABI for parameter passing */
2863                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2864                         if (ia64_is_adds_imm (abi_offset))
2865                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2866                         else {
2867                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2868                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2869                         }
2870
2871                         if (ins->flags & MONO_INST_INIT) {
2872                                 /* Upper limit */
2873                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2874
2875                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2876
2877                                 /* Init loop */
2878                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2879                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2880                                 ia64_br_cond_pred (code, 8, -2);
2881
2882                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2883
2884                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2885                         }
2886
2887                         break;
2888                 }
2889                 case OP_LOCALLOC_IMM: {
2890                         gint32 abi_offset;
2891
2892                         /* FIXME: Sigaltstack support */
2893
2894                         gssize size = ins->inst_imm;
2895                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2896
2897                         if (ia64_is_adds_imm (size))
2898                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2899                         else
2900                                 ia64_movl (code, GP_SCRATCH_REG, size);
2901
2902                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2903                         ia64_mov (code, ins->dreg, IA64_SP);
2904
2905                         /* An area at sp is reserved by the ABI for parameter passing */
2906                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2907                         if (ia64_is_adds_imm (abi_offset))
2908                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2909                         else {
2910                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2911                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2912                         }
2913
2914                         if (ins->flags & MONO_INST_INIT) {
2915                                 /* Upper limit */
2916                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2917
2918                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2919
2920                                 /* Init loop */
2921                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2922                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2923                                 ia64_br_cond_pred (code, 8, -2);
2924
2925                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2926
2927                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2928                         }
2929
2930                         break;
2931                 }
2932                         /* Synchronization */
2933                 case OP_MEMORY_BARRIER:
2934                         ia64_mf (code);
2935                         break;
2936                 case OP_ATOMIC_ADD_IMM_I4:
2937                         g_assert (ins->inst_offset == 0);
2938                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2939                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2940                         break;
2941                 case OP_ATOMIC_ADD_IMM_I8:
2942                         g_assert (ins->inst_offset == 0);
2943                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2944                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2945                         break;
2946                 case OP_ATOMIC_EXCHANGE_I4:
2947                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2948                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2949                         break;
2950                 case OP_ATOMIC_EXCHANGE_I8:
2951                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2952                         break;
2953                 case OP_ATOMIC_ADD_I4: {
2954                         guint8 *label, *buf;
2955
2956                         /* From libatomic_ops */
2957                         ia64_mf (code);
2958
2959                         ia64_begin_bundle (code);
2960                         label = code.buf + code.nins;
2961                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2962                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2963                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2964                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2965                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2966                         buf = code.buf + code.nins;
2967                         ia64_br_cond_pred (code, 7, 0);
2968                         ia64_begin_bundle (code);
2969                         ia64_patch (buf, label);
2970                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2971                         break;
2972                 }
2973                 case OP_ATOMIC_ADD_I8: {
2974                         guint8 *label, *buf;
2975
2976                         /* From libatomic_ops */
2977                         ia64_mf (code);
2978
2979                         ia64_begin_bundle (code);
2980                         label = code.buf + code.nins;
2981                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2982                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2983                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2984                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2985                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2986                         buf = code.buf + code.nins;
2987                         ia64_br_cond_pred (code, 7, 0);
2988                         ia64_begin_bundle (code);
2989                         ia64_patch (buf, label);
2990                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2991                         break;
2992                 }
2993
2994                         /* Exception handling */
2995                 case OP_CALL_HANDLER:
2996                         /*
2997                          * Using a call instruction would mess up the register stack, so
2998                          * save the return address to a register and use a
2999                          * branch.
3000                          */
3001                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3002                         ia64_mov (code, IA64_R15, IA64_R0);
3003                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3004                         /* Add the length of OP_CALL_HANDLER */
3005                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3006                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3007                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3008                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3009                         ia64_br_cond_reg (code, IA64_B6);
3010                         // FIXME:
3011                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3012                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3013                         break;
3014                 case OP_START_HANDLER: {
3015                         /*
3016                          * We receive the return address in GP_SCRATCH_REG.
3017                          */
3018                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3019
3020                         /*
3021                          * R15 determines our caller. It is used since it is writable using
3022                          * libunwind.
3023                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3024                          * R15 != 0 means we are called by call_filter ().
3025                          */
3026                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3027                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3028
3029                         ia64_br_cond_pred (code, 6, 6);
3030
3031                         /*
3032                          * Called by call_filter:
3033                          * Allocate a new stack frame, and set the fp register from the
3034                          * value passed in by the caller.
3035                          * We allocate a similar frame as is done by the prolog, so
3036                          * if an exception is thrown while executing the filter, the
3037                          * unwinder can unwind through the filter frame using the unwind
3038                          * info for the prolog.
3039                          */
3040                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3041                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3042                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3043                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3044                         /* Signal to endfilter that we are called by call_filter */
3045                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3046
3047                         /* Branch target: */
3048                         if (ia64_is_imm14 (spvar->inst_offset))
3049                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3050                         else {
3051                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3052                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3053                         }
3054
3055                         /* Save the return address */
3056                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3057                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3058
3059                         break;
3060                 }
3061                 case OP_ENDFINALLY:
3062                 case OP_ENDFILTER: {
3063                         /* FIXME: Return the value in ENDFILTER */
3064                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3065
3066                         /* Load the return address */
3067                         if (ia64_is_imm14 (spvar->inst_offset)) {
3068                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3069                         } else {
3070                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3071                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3072                         }
3073                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3074
3075                         /* Test caller */
3076                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3077                         ia64_br_cond_pred (code, 7, 4);
3078
3079                         /* Called by call_filter */
3080                         /* Pop frame */
3081                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3082                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3083                         ia64_br_ret_reg (code, IA64_B0);
3084
3085                         /* Called by CALL_HANDLER */
3086                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3087                         ia64_br_cond_reg (code, IA64_B6);
3088                         break;
3089                 }
3090                 case OP_THROW:
3091                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3092                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3093                                                           (gpointer)"mono_arch_throw_exception");
3094
3095                         /*
3096                          * This might be the last instruction in the method, so add a dummy
3097                          * instruction so the unwinder will work.
3098                          */
3099                         ia64_break_i (code, 0);
3100                         break;
3101                 case OP_RETHROW:
3102                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3103                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3104                                                           (gpointer)"mono_arch_rethrow_exception");
3105
3106                         ia64_break_i (code, 0);
3107                         break;
3108                 case OP_GC_SAFE_POINT:
3109                         break;
3110
3111                 default:
3112                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3113                         g_assert_not_reached ();
3114                 }
3115
3116                 if ((code.buf - cfg->native_code - offset) > max_len) {
3117                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3118                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3119                         g_assert_not_reached ();
3120                 }
3121
3122                 cpos += max_len;
3123
3124                 last_ins = ins;
3125                 last_offset = offset;
3126         }
3127
3128         ia64_codegen_close (code);
3129
3130         cfg->code_len = code.buf - cfg->native_code;
3131 }
3132
3133 void
3134 mono_arch_register_lowlevel_calls (void)
3135 {
3136 }
3137
3138 static Ia64InsType ins_types_in_template [32][3] = {
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3145         {0, 0, 0},
3146         {0, 0, 0},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3149         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3150         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3159         {0, 0, 0},
3160         {0, 0, 0},
3161         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3163         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3164         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3165         {0, 0, 0},
3166         {0, 0, 0},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3169         {0, 0, 0},
3170         {0, 0, 0}
3171 };
3172
3173 static gboolean stops_in_template [32][3] = {
3174         { FALSE, FALSE, FALSE },
3175         { FALSE, FALSE, TRUE },
3176         { FALSE, TRUE, FALSE },
3177         { FALSE, TRUE, TRUE },
3178         { FALSE, FALSE, FALSE },
3179         { FALSE, FALSE, TRUE },
3180         { FALSE, FALSE, FALSE },
3181         { FALSE, FALSE, FALSE },
3182
3183         { FALSE, FALSE, FALSE },
3184         { FALSE, FALSE, TRUE },
3185         { TRUE, FALSE, FALSE },
3186         { TRUE, FALSE, TRUE },
3187         { FALSE, FALSE, FALSE },
3188         { FALSE, FALSE, TRUE },
3189         { FALSE, FALSE, FALSE },
3190         { FALSE, FALSE, TRUE },
3191
3192         { FALSE, FALSE, FALSE },
3193         { FALSE, FALSE, TRUE },
3194         { FALSE, FALSE, FALSE },
3195         { FALSE, FALSE, TRUE },
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, FALSE },
3198         { FALSE, FALSE, FALSE },
3199         { FALSE, FALSE, TRUE },
3200
3201         { FALSE, FALSE, FALSE },
3202         { FALSE, FALSE, TRUE },
3203         { FALSE, FALSE, FALSE },
3204         { FALSE, FALSE, FALSE },
3205         { FALSE, FALSE, FALSE },
3206         { FALSE, FALSE, TRUE },
3207         { FALSE, FALSE, FALSE },
3208         { FALSE, FALSE, FALSE }
3209 };
3210
3211 static int last_stop_in_template [32] = {
3212         -1, 2, 1, 2, -1, 2, -1, -1,
3213         -1, 2, 0, 2, -1, 2, -1, 2,
3214         -1, 2, -1, 2, -1, -1, -1, 2,
3215         -1, 2, -1, -1, -1, 2, -1, -1
3216 };
3217
3218 static guint64 nops_for_ins_types [6] = {
3219         IA64_NOP_I,
3220         IA64_NOP_I,
3221         IA64_NOP_M,
3222         IA64_NOP_F,
3223         IA64_NOP_B,
3224         IA64_NOP_X
3225 };
3226
3227 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3228
3229 /*
3230  * Debugging support
3231  */
3232
3233 #if 0
3234 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3235 #else
3236 #define DEBUG_INS_SCHED(a)
3237 #endif
3238
3239 static void
3240 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3241 {
3242         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3243         guint8 *deps = code->dep_info;
3244         gboolean need_stop, no_stop;
3245
3246         for (i = 0; i < code->nins; ++i)
3247                 stops [i] = FALSE;
3248
3249         ins_index = 0;
3250         current_deps_start = 0;
3251         current_ins_start = 0;
3252         deps_start [ins_index] = current_ins_start;
3253         pos = 0;
3254         no_stop = FALSE;
3255         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3256         while (pos < code->dep_info_pos) {
3257                 need_stop = FALSE;
3258                 switch (deps [pos]) {
3259                 case IA64_END_OF_INS:
3260                         ins_index ++;
3261                         current_ins_start = pos + 2;
3262                         deps_start [ins_index] = current_ins_start;
3263                         no_stop = FALSE;
3264                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3265                         break;
3266                 case IA64_NONE:
3267                         break;
3268                 case IA64_READ_GR:
3269                         reg = deps [pos + 1];
3270
3271                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3272                         for (i = current_deps_start; i < current_ins_start; i += 2)
3273                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3274                                         need_stop = TRUE;
3275                         break;
3276                 case IA64_WRITE_GR:
3277                         reg = code->dep_info [pos + 1];
3278
3279                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3280                         for (i = current_deps_start; i < current_ins_start; i += 2)
3281                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3282                                         need_stop = TRUE;
3283                         break;
3284                 case IA64_READ_PR:
3285                         reg = deps [pos + 1];
3286
3287                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3288                         for (i = current_deps_start; i < current_ins_start; i += 2)
3289                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3290                                         need_stop = TRUE;
3291                         break;
3292                 case IA64_READ_PR_BRANCH:
3293                         reg = deps [pos + 1];
3294
3295                         /* Writes to prs by non-float instructions are visible to branches */
3296                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3297                         for (i = current_deps_start; i < current_ins_start; i += 2)
3298                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3299                                         need_stop = TRUE;
3300                         break;
3301                 case IA64_WRITE_PR:
3302                         reg = code->dep_info [pos + 1];
3303
3304                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3305                         for (i = current_deps_start; i < current_ins_start; i += 2)
3306                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3307                                         need_stop = TRUE;
3308                         break;
3309                 case IA64_WRITE_PR_FLOAT:
3310                         reg = code->dep_info [pos + 1];
3311
3312                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3313                         for (i = current_deps_start; i < current_ins_start; i += 2)
3314                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3315                                         need_stop = TRUE;
3316                         break;
3317                 case IA64_READ_BR:
3318                         reg = deps [pos + 1];
3319
3320                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3321                         for (i = current_deps_start; i < current_ins_start; i += 2)
3322                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3323                                         need_stop = TRUE;
3324                         break;
3325                 case IA64_WRITE_BR:
3326                         reg = code->dep_info [pos + 1];
3327
3328                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3329                         for (i = current_deps_start; i < current_ins_start; i += 2)
3330                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3331                                         need_stop = TRUE;
3332                         break;
3333                 case IA64_READ_BR_BRANCH:
3334                         reg = deps [pos + 1];
3335
3336                         /* Writes to brs are visible to branches */
3337                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3338                         break;
3339                 case IA64_READ_FR:
3340                         reg = deps [pos + 1];
3341
3342                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3343                         for (i = current_deps_start; i < current_ins_start; i += 2)
3344                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3345                                         need_stop = TRUE;
3346                         break;
3347                 case IA64_WRITE_FR:
3348                         reg = code->dep_info [pos + 1];
3349
3350                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3351                         for (i = current_deps_start; i < current_ins_start; i += 2)
3352                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3353                                         need_stop = TRUE;
3354                         break;
3355                 case IA64_READ_AR:
3356                         reg = deps [pos + 1];
3357
3358                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3359                         for (i = current_deps_start; i < current_ins_start; i += 2)
3360                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3361                                         need_stop = TRUE;
3362                         break;
3363                 case IA64_WRITE_AR:
3364                         reg = code->dep_info [pos + 1];
3365
3366                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3367                         for (i = current_deps_start; i < current_ins_start; i += 2)
3368                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3369                                         need_stop = TRUE;
3370                         break;
3371                 case IA64_NO_STOP:
3372                         /*
3373                          * Explicitly indicate that a stop is not required. Useful for
3374                          * example when two predicated instructions with negated predicates
3375                          * write the same registers.
3376                          */
3377                         no_stop = TRUE;
3378                         break;
3379                 default:
3380                         g_assert_not_reached ();
3381                 }
3382                 pos += 2;
3383
3384                 if (need_stop && !no_stop) {
3385                         g_assert (ins_index > 0);
3386                         stops [ins_index - 1] = 1;
3387
3388                         DEBUG_INS_SCHED (printf ("STOP\n"));
3389                         current_deps_start = current_ins_start;
3390
3391                         /* Skip remaining deps for this instruction */
3392                         while (deps [pos] != IA64_END_OF_INS)
3393                                 pos += 2;
3394                 }
3395         }
3396
3397         if (code->nins > 0) {
3398                 /* No dependency info for the last instruction */
3399                 stops [code->nins - 1] = 1;
3400         }
3401
3402         deps_start [code->nins] = code->dep_info_pos;
3403 }
3404
3405 static void
3406 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3407 {
3408         int stop_pos, i, deps_to_shift, dep_shift;
3409
3410         g_assert (n <= code->nins);
3411
3412         // if (n > 1) printf ("FOUND: %ld.\n", template);
3413
3414         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3415
3416         stop_pos = last_stop_in_template [template] + 1;
3417         if (stop_pos > n)
3418                 stop_pos = n;
3419
3420         /* Compute the number of 'real' instructions before the stop */
3421         deps_to_shift = stop_pos;
3422         if (stop_pos >= 3 && (nops & (1 << 2)))
3423                 deps_to_shift --;
3424         if (stop_pos >= 2 && (nops & (1 << 1)))
3425                 deps_to_shift --;
3426         if (stop_pos >= 1 && (nops & (1 << 0)))
3427                 deps_to_shift --;
3428
3429         /*
3430          * We have to keep some dependencies whose instructions have been shifted
3431          * out of the buffer. So nullify the end_of_ins markers in the dependency
3432          * array.
3433          */
3434         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3435                 if (code->dep_info [i] == IA64_END_OF_INS)
3436                         code->dep_info [i] = IA64_NONE;
3437
3438         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3439         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3440         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3441
3442         dep_shift = deps_start [deps_to_shift];
3443         for (i = 0; i < code->nins + 1 - n; ++i)
3444                 deps_start [i] = deps_start [n + i] - dep_shift;
3445
3446         /* Determine the exact positions of instructions with unwind ops */
3447         if (code->unw_op_count) {
3448                 int ins_pos [16];
3449                 int curr_ins, curr_ins_pos;
3450
3451                 curr_ins = 0;
3452                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3453                 for (i = 0; i < 3; ++i) {
3454                         if (! (nops & (1 << i))) {
3455                                 ins_pos [curr_ins] = curr_ins_pos + i;
3456                                 curr_ins ++;
3457                         }
3458                 }
3459
3460                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3461                         if (code->unw_ops_pos [i] < n) {
3462                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3463                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3464                         }
3465                 }
3466                 if (code->unw_op_pos < code->unw_op_count)
3467                         code->unw_op_pos += n;
3468         }
3469
3470         if (n == code->nins) {
3471                 code->template = 0;
3472                 code->nins = 0;
3473         }
3474         else {
3475                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3476                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3477                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3478                 code->nins -= n;
3479         }
3480 }
3481
3482 void
3483 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3484 {
3485         int i, ins_type, template, nins_to_emit;
3486         int deps_start [16];
3487         int stops [16];
3488         gboolean found;
3489
3490         /*
3491          * We implement a simple scheduler which tries to put three instructions
3492          * per bundle, then two, then one.
3493          */
3494         ia64_analyze_deps (code, deps_start, stops);
3495
3496         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3497                 /* Find a suitable template */
3498                 for (template = 0; template < 32; ++template) {
3499                         if (stops_in_template [template][0] != stops [0] ||
3500                                 stops_in_template [template][1] != stops [1] ||
3501                                 stops_in_template [template][2] != stops [2])
3502                                 continue;
3503
3504                         found = TRUE;
3505                         for (i = 0; i < 3; ++i) {
3506                                 ins_type = ins_types_in_template [template][i];
3507                                 switch (code->itypes [i]) {
3508                                 case IA64_INS_TYPE_A:
3509                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3510                                         break;
3511                                 default:
3512                                         found &= (ins_type == code->itypes [i]);
3513                                         break;
3514                                 }
3515                         }
3516
3517                         if (found)
3518                                 found = debug_ins_sched ();
3519
3520                         if (found) {
3521                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3522                                 break;
3523                         }
3524                 }
3525         }
3526
3527         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3528                 /* Wait for more instructions */
3529                 return;
3530
3531         /* If it didn't work out, try putting two instructions into one bundle */
3532         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3533                 /* Try a nop at the end */
3534                 for (template = 0; template < 32; ++template) {
3535                         if (stops_in_template [template][0] != stops [0] ||
3536                                 ((stops_in_template [template][1] != stops [1]) &&
3537                                  (stops_in_template [template][2] != stops [1])))
3538
3539                                 continue;
3540
3541                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3542                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3543                                 continue;
3544
3545                         if (!debug_ins_sched ())
3546                                 continue;
3547
3548                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3549                         break;
3550                 }
3551         }
3552
3553         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3554                 /* Wait for more instructions */
3555                 return;
3556
3557         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3558                 /* Try a nop in the middle */
3559                 for (template = 0; template < 32; ++template) {
3560                         if (((stops_in_template [template][0] != stops [0]) &&
3561                                  (stops_in_template [template][1] != stops [0])) ||
3562                                 stops_in_template [template][2] != stops [1])
3563                                 continue;
3564
3565                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3566                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3567                                 continue;
3568
3569                         if (!debug_ins_sched ())
3570                                 continue;
3571
3572                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3573                         break;
3574                 }
3575         }
3576
3577         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3578                 /* Try a nop at the beginning */
3579                 for (template = 0; template < 32; ++template) {
3580                         if ((stops_in_template [template][1] != stops [0]) ||
3581                                 (stops_in_template [template][2] != stops [1]))
3582                                 continue;
3583
3584                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3585                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3586                                 continue;
3587
3588                         if (!debug_ins_sched ())
3589                                 continue;
3590
3591                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3592                         break;
3593                 }
3594         }
3595
3596         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3597                 /* Wait for more instructions */
3598                 return;
3599
3600         if (flush)
3601                 nins_to_emit = code->nins;
3602         else
3603                 nins_to_emit = 1;
3604
3605         while (nins_to_emit > 0) {
3606                 if (!debug_ins_sched ())
3607                         stops [0] = 1;
3608                 switch (code->itypes [0]) {
3609                 case IA64_INS_TYPE_A:
3610                         if (stops [0])
3611                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3612                         else
3613                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3614                         break;
3615                 case IA64_INS_TYPE_I:
3616                         if (stops [0])
3617                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3618                         else
3619                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3620                         break;
3621                 case IA64_INS_TYPE_M:
3622                         if (stops [0])
3623                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3624                         else
3625                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3626                         break;
3627                 case IA64_INS_TYPE_B:
3628                         if (stops [0])
3629                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3630                         else
3631                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3632                         break;
3633                 case IA64_INS_TYPE_F:
3634                         if (stops [0])
3635                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3636                         else
3637                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3638                         break;
3639                 case IA64_INS_TYPE_LX:
3640                         if (stops [0] || stops [1])
3641                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3642                         else
3643                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3644                         nins_to_emit --;
3645                         break;
3646                 default:
3647                         g_assert_not_reached ();
3648                 }
3649                 nins_to_emit --;
3650         }
3651 }
3652
3653 unw_dyn_region_info_t*
3654 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3655 {
3656         unw_dyn_region_info_t *r;
3657
3658         g_assert (code->nins == 0);
3659         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3660         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3661         r->op_count = code->unw_op_count;
3662         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3663         code->unw_op_count = 0;
3664         code->unw_op_pos = 0;
3665         code->region_start = code->buf;
3666
3667         return r;
3668 }
3669
3670 static void
3671 ia64_patch (unsigned char* code, gpointer target)
3672 {
3673         int template, i;
3674         guint64 instructions [3];
3675         guint8 gen_buf [16];
3676         Ia64CodegenState gen;
3677         int ins_to_skip;
3678         gboolean found;
3679
3680         /*
3681          * code encodes both the position inside the buffer and code.nins when
3682          * the instruction was emitted.
3683          */
3684         ins_to_skip = (guint64)code % 16;
3685         code = (unsigned char*)((guint64)code & ~15);
3686
3687         /*
3688          * Search for the first instruction which is 'patchable', skipping
3689          * ins_to_skip instructions.
3690          */
3691
3692         while (TRUE) {
3693
3694         template = ia64_bundle_template (code);
3695         instructions [0] = ia64_bundle_ins1 (code);
3696         instructions [1] = ia64_bundle_ins2 (code);
3697         instructions [2] = ia64_bundle_ins3 (code);
3698
3699         ia64_codegen_init (gen, gen_buf);
3700
3701         found = FALSE;
3702         for (i = 0; i < 3; ++i) {
3703                 guint64 ins = instructions [i];
3704                 int opcode = ia64_ins_opcode (ins);
3705
3706                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3707                         continue;
3708
3709                 if (ins_to_skip) {
3710                         ins_to_skip --;
3711                         continue;
3712                 }
3713
3714                 switch (ins_types_in_template [template][i]) {
3715                 case IA64_INS_TYPE_A:
3716                 case IA64_INS_TYPE_M:
3717                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3718                                 /* adds */
3719                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3720                                 instructions [i] = gen.instructions [0];
3721                                 found = TRUE;
3722                         }
3723                         else
3724                                 NOT_IMPLEMENTED;
3725                         break;
3726                 case IA64_INS_TYPE_B:
3727                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3728                                 /* br.cond */
3729                                 gint64 disp = ((guint8*)target - code) >> 4;
3730
3731                                 /* FIXME: hints */
3732                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3733
3734                                 instructions [i] = gen.instructions [0];
3735                                 found = TRUE;
3736                         }
3737                         else if (opcode == 5) {
3738                                 /* br.call */
3739                                 gint64 disp = ((guint8*)target - code) >> 4;
3740
3741                                 /* FIXME: hints */
3742                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3743                                 instructions [i] = gen.instructions [0];
3744                                 found = TRUE;
3745                         }
3746                         else
3747                                 NOT_IMPLEMENTED;
3748                         break;
3749                 case IA64_INS_TYPE_LX:
3750                         if (i == 1)
3751                                 break;
3752
3753                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3754                                 /* movl */
3755                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3756                                 instructions [1] = gen.instructions [0];
3757                                 instructions [2] = gen.instructions [1];
3758                                 found = TRUE;
3759                         }
3760                         else
3761                                 NOT_IMPLEMENTED;
3762
3763                         break;
3764                 default:
3765                         NOT_IMPLEMENTED;
3766                 }
3767
3768                 if (found) {
3769                         /* Rewrite code */
3770                         ia64_codegen_init (gen, code);
3771                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3772                         return;
3773                 }
3774         }
3775
3776         code += 16;
3777         }
3778 }
3779
3780 void
3781 mono_arch_patch_code (MonoCompile *cfg, MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors, MonoError *error)
3782 {
3783         MonoJumpInfo *patch_info;
3784
3785         mono_error_init (error);
3786
3787         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3788                 unsigned char *ip = patch_info->ip.i + code;
3789                 const unsigned char *target;
3790
3791                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors, error);
3792                 return_if_nok (error);
3793
3794                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3795                         continue;
3796                 if (mono_compile_aot) {
3797                         NOT_IMPLEMENTED;
3798                 }
3799
3800                 ia64_patch (ip, (gpointer)target);
3801         }
3802 }
3803
3804 guint8 *
3805 mono_arch_emit_prolog (MonoCompile *cfg)
3806 {
3807         MonoMethod *method = cfg->method;
3808         MonoMethodSignature *sig;
3809         MonoInst *inst;
3810         int alloc_size, pos, i;
3811         Ia64CodegenState code;
3812         CallInfo *cinfo;
3813
3814         sig = mono_method_signature (method);
3815         pos = 0;
3816
3817         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3818
3819         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3820
3821         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3822                 cfg->code_size += 1024;
3823         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3824                 cfg->code_size += 1024;
3825
3826         cfg->native_code = g_malloc (cfg->code_size);
3827
3828         ia64_codegen_init (code, cfg->native_code);
3829
3830         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3831         if (cfg->param_area)
3832                 alloc_size += cfg->param_area;
3833         if (alloc_size)
3834                 /* scratch area */
3835                 alloc_size += 16;
3836         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3837
3838         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3839                 /* Force sp to be saved/restored */
3840                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3841
3842         cfg->arch.stack_alloc_size = alloc_size;
3843
3844         pos = 0;
3845
3846         if (method->save_lmf) {
3847                 /* No LMF on IA64 */
3848         }
3849
3850         alloc_size -= pos;
3851
3852         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3853         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3854         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3855         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3856
3857         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3858                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3859                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3860                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3861                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3862         }
3863
3864         if (alloc_size) {
3865 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3866                 int pagesize = getpagesize ();
3867
3868                 if (alloc_size >= pagesize) {
3869                         gint32 remaining_size = alloc_size;
3870
3871                         /* Generate stack touching code */
3872                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3873                         while (remaining_size >= pagesize) {
3874                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3875                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3876                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3877                                 remaining_size -= pagesize;
3878                         }
3879                 }
3880 #endif
3881                 if (ia64_is_imm14 (-alloc_size)) {
3882                         if (cfg->arch.omit_fp)
3883                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3884                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3885                 }
3886                 else {
3887                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3888                         if (cfg->arch.omit_fp)
3889                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3890                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3891                 }
3892         }
3893
3894         ia64_begin_bundle (code);
3895
3896         /* Initialize unwind info */
3897         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3898
3899         if (sig->ret->type != MONO_TYPE_VOID) {
3900                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3901                         /* Save volatile arguments to the stack */
3902                         NOT_IMPLEMENTED;
3903                 }
3904         }
3905
3906         /* Keep this in sync with emit_load_volatile_arguments */
3907         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3908                 ArgInfo *ainfo = cinfo->args + i;
3909                 gint32 stack_offset;
3910                 MonoType *arg_type;
3911
3912                 inst = cfg->args [i];
3913
3914                 if (sig->hasthis && (i == 0))
3915                         arg_type = &mono_defaults.object_class->byval_arg;
3916                 else
3917                         arg_type = sig->params [i - sig->hasthis];
3918
3919                 arg_type = mini_get_underlying_type (arg_type);
3920
3921                 stack_offset = ainfo->offset + ARGS_OFFSET;
3922
3923                 /*
3924                  * FIXME: Native code might pass non register sized integers
3925                  * without initializing the upper bits.
3926                  */
3927                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3928                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3929
3930                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3931                         case OP_LOADI1_MEMBASE:
3932                                 ia64_sxt1 (code, reg, reg);
3933                                 break;
3934                         case OP_LOADU1_MEMBASE:
3935                                 ia64_zxt1 (code, reg, reg);
3936                                 break;
3937                         case OP_LOADI2_MEMBASE:
3938                                 ia64_sxt2 (code, reg, reg);
3939                                 break;
3940                         case OP_LOADU2_MEMBASE:
3941                                 ia64_zxt2 (code, reg, reg);
3942                                 break;
3943                         default:
3944                                 break;
3945                         }
3946                 }
3947
3948                 /* Save volatile arguments to the stack */
3949                 if (inst->opcode != OP_REGVAR) {
3950                         switch (ainfo->storage) {
3951                         case ArgInIReg:
3952                         case ArgInFloatReg:
3953                         case ArgInFloatRegR4:
3954                                 g_assert (inst->opcode == OP_REGOFFSET);
3955                                 if (ia64_is_adds_imm (inst->inst_offset))
3956                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3957                                 else {
3958                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3959                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3960                                 }
3961                                 if (arg_type->byref)
3962                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3963                                 else {
3964                                         switch (arg_type->type) {
3965                                         case MONO_TYPE_R4:
3966                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3967                                                 break;
3968                                         case MONO_TYPE_R8:
3969                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3970                                                 break;
3971                                         default:
3972                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3973                                                 break;
3974                                         }
3975                                 }
3976                                 break;
3977                         case ArgOnStack:
3978                                 break;
3979                         case ArgAggregate:
3980                                 if (ainfo->nslots != ainfo->nregs)
3981                                         NOT_IMPLEMENTED;
3982
3983                                 g_assert (inst->opcode == OP_REGOFFSET);
3984                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3985                                 for (i = 0; i < ainfo->nregs; ++i) {
3986                                         switch (ainfo->atype) {
3987                                         case AggregateNormal:
3988                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3989                                                 break;
3990                                         case AggregateSingleHFA:
3991                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3992                                                 break;
3993                                         case AggregateDoubleHFA:
3994                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3995                                                 break;
3996                                         default:
3997                                                 NOT_IMPLEMENTED;
3998                                         }
3999                                 }
4000                                 break;
4001                         default:
4002                                 g_assert_not_reached ();
4003                         }
4004                 }
4005
4006                 if (inst->opcode == OP_REGVAR) {
4007                         /* Argument allocated to (non-volatile) register */
4008                         switch (ainfo->storage) {
4009                         case ArgInIReg:
4010                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4011                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4012                                 break;
4013                         case ArgOnStack:
4014                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4015                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4016                                 break;
4017                         default:
4018                                 NOT_IMPLEMENTED;
4019                         }
4020                 }
4021         }
4022
4023         if (method->save_lmf) {
4024                 /* No LMF on IA64 */
4025         }
4026
4027         ia64_codegen_close (code);
4028
4029         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4030                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4031
4032         cfg->code_len = code.buf - cfg->native_code;
4033
4034         g_assert (cfg->code_len < cfg->code_size);
4035
4036         cfg->arch.prolog_end_offset = cfg->code_len;
4037
4038         return code.buf;
4039 }
4040
4041 void
4042 mono_arch_emit_epilog (MonoCompile *cfg)
4043 {
4044         MonoMethod *method = cfg->method;
4045         int i, pos;
4046         int max_epilog_size = 16 * 4;
4047         Ia64CodegenState code;
4048         guint8 *buf;
4049         CallInfo *cinfo;
4050         ArgInfo *ainfo;
4051
4052         if (mono_jit_trace_calls != NULL)
4053                 max_epilog_size += 1024;
4054
4055         cfg->arch.epilog_begin_offset = cfg->code_len;
4056
4057         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4058                 cfg->code_size *= 2;
4059                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4060                 cfg->stat_code_reallocs++;
4061         }
4062
4063         /* FIXME: Emit unwind info */
4064
4065         buf = cfg->native_code + cfg->code_len;
4066
4067         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4068                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4069
4070         ia64_codegen_init (code, buf);
4071
4072         /* the code restoring the registers must be kept in sync with OP_JMP */
4073         pos = 0;
4074
4075         if (method->save_lmf) {
4076                 /* No LMF on IA64 */
4077         }
4078
4079         /* Load returned vtypes into registers if needed */
4080         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4081         ainfo = &cinfo->ret;
4082         switch (ainfo->storage) {
4083         case ArgAggregate:
4084                 if (ainfo->nslots != ainfo->nregs)
4085                         NOT_IMPLEMENTED;
4086
4087                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4088                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4089                 for (i = 0; i < ainfo->nregs; ++i) {
4090                         switch (ainfo->atype) {
4091                         case AggregateNormal:
4092                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4093                                 break;
4094                         case AggregateSingleHFA:
4095                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4096                                 break;
4097                         case AggregateDoubleHFA:
4098                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4099                                 break;
4100                         default:
4101                                 g_assert_not_reached ();
4102                         }
4103                 }
4104                 break;
4105         default:
4106                 break;
4107         }
4108
4109         ia64_begin_bundle (code);
4110
4111         code.region_start = cfg->native_code;
4112
4113         /* Label the unwind state at the start of the exception throwing region */
4114         //ia64_unw_label_state (code, 1234);
4115
4116         if (cfg->arch.stack_alloc_size) {
4117                 if (cfg->arch.omit_fp) {
4118                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4119                                 ia64_unw_pop_frames (code, 1);
4120                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4121                         } else {
4122                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4123                                 ia64_unw_pop_frames (code, 1);
4124                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4125                         }
4126                 }
4127                 else {
4128                         ia64_unw_pop_frames (code, 1);
4129                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4130                 }
4131         }
4132         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4133         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4134         ia64_br_ret_reg (code, IA64_B0);
4135
4136         ia64_codegen_close (code);
4137
4138         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4139         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4140
4141         cfg->code_len = code.buf - cfg->native_code;
4142
4143         g_assert (cfg->code_len < cfg->code_size);
4144 }
4145
4146 void
4147 mono_arch_emit_exceptions (MonoCompile *cfg)
4148 {
4149         MonoJumpInfo *patch_info;
4150         int i, nthrows;
4151         Ia64CodegenState code;
4152         gboolean empty = TRUE;
4153         //unw_dyn_region_info_t *r_exceptions;
4154         MonoClass *exc_classes [16];
4155         guint8 *exc_throw_start [16], *exc_throw_end [16];
4156         guint32 code_size = 0;
4157
4158         /* Compute needed space */
4159         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4160                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4161                         code_size += 256;
4162                 if (patch_info->type == MONO_PATCH_INFO_R8)
4163                         code_size += 8 + 7; /* sizeof (double) + alignment */
4164                 if (patch_info->type == MONO_PATCH_INFO_R4)
4165                         code_size += 4 + 7; /* sizeof (float) + alignment */
4166         }
4167
4168         if (code_size == 0)
4169                 return;
4170
4171         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4172                 cfg->code_size *= 2;
4173                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4174                 cfg->stat_code_reallocs++;
4175         }
4176
4177         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4178
4179         /* The unwind state here is the same as before the epilog */
4180         //ia64_unw_copy_state (code, 1234);
4181
4182         /* add code to raise exceptions */
4183         /* FIXME: Optimize this */
4184         nthrows = 0;
4185         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4186                 switch (patch_info->type) {
4187                 case MONO_PATCH_INFO_EXC: {
4188                         MonoClass *exc_class;
4189                         guint8* throw_ip;
4190                         guint8* buf;
4191                         guint64 exc_token_index;
4192
4193                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4194                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4195                         throw_ip = cfg->native_code + patch_info->ip.i;
4196
4197                         ia64_begin_bundle (code);
4198
4199                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4200
4201                         /* Find a throw sequence for the same exception class */
4202                         for (i = 0; i < nthrows; ++i)
4203                                 if (exc_classes [i] == exc_class)
4204                                         break;
4205
4206                         if (i < nthrows) {
4207                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4208
4209                                 if (ia64_is_adds_imm (offset))
4210                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4211                                 else
4212                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4213
4214                                 buf = code.buf + code.nins;
4215                                 ia64_br_cond_pred (code, 0, 0);
4216                                 ia64_begin_bundle (code);
4217                                 ia64_patch (buf, exc_throw_start [i]);
4218
4219                                 patch_info->type = MONO_PATCH_INFO_NONE;
4220                         }
4221                         else {
4222                                 /* Arg1 */
4223                                 buf = code.buf;
4224                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4225
4226                                 ia64_begin_bundle (code);
4227
4228                                 if (nthrows < 16) {
4229                                         exc_classes [nthrows] = exc_class;
4230                                         exc_throw_start [nthrows] = code.buf;
4231                                 }
4232
4233                                 /* Arg2 */
4234                                 if (ia64_is_adds_imm (exc_token_index))
4235                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4236                                 else
4237                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4238
4239                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4240                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4241                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4242
4243                                 /* Indirect call */
4244                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4245                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4246                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4247                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4248
4249                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4250
4251                                 /* Patch up the throw offset */
4252                                 ia64_begin_bundle (code);
4253
4254                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4255
4256                                 if (nthrows < 16) {
4257                                         exc_throw_end [nthrows] = code.buf;
4258                                         nthrows ++;
4259                                 }
4260                         }
4261
4262                         empty = FALSE;
4263                         break;
4264                 }
4265                 default:
4266                         break;
4267                 }
4268         }
4269
4270         if (!empty)
4271                 /* The unwinder needs this to work */
4272                 ia64_break_i (code, 0);
4273
4274         ia64_codegen_close (code);
4275
4276         /* FIXME: */
4277         //r_exceptions = mono_ia64_create_unwind_region (&code);
4278         //cfg->arch.r_epilog = r_exceptions;
4279
4280         cfg->code_len = code.buf - cfg->native_code;
4281
4282         g_assert (cfg->code_len < cfg->code_size);
4283 }
4284
4285 void*
4286 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4287 {
4288         Ia64CodegenState code;
4289         CallInfo *cinfo = NULL;
4290         MonoMethodSignature *sig;
4291         MonoInst *ins;
4292         int i, n, stack_area = 0;
4293
4294         ia64_codegen_init (code, p);
4295
4296         /* Keep this in sync with mono_arch_get_argument_info */
4297
4298         if (enable_arguments) {
4299                 /* Allocate a new area on the stack and save arguments there */
4300                 sig = mono_method_signature (cfg->method);
4301
4302                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4303
4304                 n = sig->param_count + sig->hasthis;
4305
4306                 stack_area = ALIGN_TO (n * 8, 16);
4307
4308                 if (n) {
4309                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4310
4311                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4312
4313                         /* FIXME: Allocate out registers */
4314
4315                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4316
4317                         /* Required by the ABI */
4318                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4319
4320                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4321                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4322
4323                         /* Save arguments to the stack */
4324                         for (i = 0; i < n; ++i) {
4325                                 ins = cfg->args [i];
4326
4327                                 if (ins->opcode == OP_REGVAR) {
4328                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4329                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4330                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4331                                 }
4332                                 else {
4333                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4334                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4335                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4336                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4337                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4338                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4339                                 }
4340                         }
4341                 }
4342                 else
4343                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4344         }
4345         else
4346                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4347
4348         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4349         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4350
4351         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4352
4353         if (enable_arguments && stack_area) {
4354                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4355
4356                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4357
4358                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4359         }
4360
4361         ia64_codegen_close (code);
4362
4363         return code.buf;
4364 }
4365
4366 void*
4367 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4368 {
4369         Ia64CodegenState code;
4370         CallInfo *cinfo = NULL;
4371         MonoMethod *method = cfg->method;
4372         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4373
4374         ia64_codegen_init (code, p);
4375
4376         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4377
4378         /* Save return value + pass it to func */
4379         switch (cinfo->ret.storage) {
4380         case ArgNone:
4381                 break;
4382         case ArgInIReg:
4383                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4384                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4385                 break;
4386         case ArgInFloatReg:
4387                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4388                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4389                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4390                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4391                 break;
4392         case ArgValuetypeAddrInIReg:
4393                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4394                 break;
4395         case ArgAggregate:
4396                 NOT_IMPLEMENTED;
4397                 break;
4398         default:
4399                 break;
4400         }
4401
4402         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4403         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4404         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4405
4406         /* Restore return value */
4407         switch (cinfo->ret.storage) {
4408         case ArgNone:
4409                 break;
4410         case ArgInIReg:
4411                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4412                 break;
4413         case ArgInFloatReg:
4414                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4415                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4416                 break;
4417         case ArgValuetypeAddrInIReg:
4418                 break;
4419         case ArgAggregate:
4420                 break;
4421         default:
4422                 break;
4423         }
4424
4425         ia64_codegen_close (code);
4426
4427         return code.buf;
4428 }
4429
4430 void
4431 mono_arch_save_unwind_info (MonoCompile *cfg)
4432 {
4433         unw_dyn_info_t *di;
4434
4435         /* FIXME: Unregister this for dynamic methods */
4436
4437         di = g_malloc0 (sizeof (unw_dyn_info_t));
4438         di->start_ip = (unw_word_t) cfg->native_code;
4439         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4440         di->gp = 0;
4441         di->format = UNW_INFO_FORMAT_DYNAMIC;
4442         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4443         di->u.pi.regions = cfg->arch.r_pro;
4444
4445         _U_dyn_register (di);
4446
4447         /*
4448         {
4449                 unw_dyn_region_info_t *region = di->u.pi.regions;
4450
4451                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4452                 while (region) {
4453                         printf ("    [Region: %d]\n", region->insn_count);
4454                         region = region->next;
4455                 }
4456         }
4457         */
4458 }
4459
4460 void
4461 mono_arch_flush_icache (guint8 *code, gint size)
4462 {
4463         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4464         guint8* end = (guint8*)((guint64)code + size);
4465
4466 #ifdef __INTEL_COMPILER
4467         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4468         while (p < end) {
4469                 __fc ((guint64)p);
4470                 p += 32;
4471         }
4472 #else
4473         while (p < end) {
4474                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4475                 /* FIXME: This could be increased to 128 on some cpus */
4476                 p += 32;
4477         }
4478 #endif
4479 }
4480
4481 void
4482 mono_arch_flush_register_windows (void)
4483 {
4484         /* Not needed because of libunwind */
4485 }
4486
4487 gboolean
4488 mono_arch_is_inst_imm (gint64 imm)
4489 {
4490         /* The lowering pass will take care of it */
4491
4492         return TRUE;
4493 }
4494
4495 /*
4496  * Determine whenever the trap whose info is in SIGINFO is caused by
4497  * integer overflow.
4498  */
4499 gboolean
4500 mono_arch_is_int_overflow (void *sigctx, void *info)
4501 {
4502         /* Division is emulated with explicit overflow checks */
4503         return FALSE;
4504 }
4505
4506 guint32
4507 mono_arch_get_patch_offset (guint8 *code)
4508 {
4509         NOT_IMPLEMENTED;
4510
4511         return 0;
4512 }
4513
4514 gpointer*
4515 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4516 {
4517         NOT_IMPLEMENTED;
4518
4519         return NULL;
4520 }
4521
4522 void
4523 mono_arch_finish_init (void)
4524 {
4525 }
4526
4527 void
4528 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4529 {
4530 }
4531
4532 /*
4533  * LOCKING: called with the domain lock held
4534  */
4535 gpointer
4536 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4537                                                                 gpointer fail_tramp)
4538 {
4539         int i;
4540         int size = 0;
4541         guint8 *start, *buf;
4542         Ia64CodegenState code;
4543
4544         size = count * 256;
4545         buf = g_malloc0 (size);
4546         ia64_codegen_init (code, buf);
4547
4548         /* IA64_R9 contains the IMT method */
4549
4550         for (i = 0; i < count; ++i) {
4551                 MonoIMTCheckItem *item = imt_entries [i];
4552                 ia64_begin_bundle (code);
4553                 item->code_target = (guint8*)code.buf + code.nins;
4554                 if (item->is_equals) {
4555                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4556
4557                         if (item->check_target_idx || fail_case) {
4558                                 if (!item->compare_done || fail_case) {
4559                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4560                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4561                                 }
4562                                 item->jmp_code = (guint8*)code.buf + code.nins;
4563                                 ia64_br_cond_pred (code, 7, 0);
4564
4565                                 if (item->has_target_code) {
4566                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4567                                 } else {
4568                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4569                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4570                                 }
4571                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4572                                 ia64_br_cond_reg (code, IA64_B6);
4573
4574                                 if (fail_case) {
4575                                         ia64_begin_bundle (code);
4576                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4577                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4578                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4579                                         ia64_br_cond_reg (code, IA64_B6);
4580                                         item->jmp_code = NULL;
4581                                 }
4582                         } else {
4583                                 /* enable the commented code to assert on wrong method */
4584 #if ENABLE_WRONG_METHOD_CHECK
4585                                 g_assert_not_reached ();
4586 #endif
4587                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4588                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4589                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4590                                 ia64_br_cond_reg (code, IA64_B6);
4591 #if ENABLE_WRONG_METHOD_CHECK
4592                                 g_assert_not_reached ();
4593 #endif
4594                         }
4595                 } else {
4596                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4597                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4598                         item->jmp_code = (guint8*)code.buf + code.nins;
4599                         ia64_br_cond_pred (code, 6, 0);
4600                 }
4601         }
4602         /* patch the branches to get to the target items */
4603         for (i = 0; i < count; ++i) {
4604                 MonoIMTCheckItem *item = imt_entries [i];
4605                 if (item->jmp_code) {
4606                         if (item->check_target_idx) {
4607                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4608                         }
4609                 }
4610         }
4611
4612         ia64_codegen_close (code);
4613         g_assert (code.buf - buf <= size);
4614
4615         size = code.buf - buf;
4616         if (fail_tramp) {
4617                 start = mono_method_alloc_generic_virtual_trampoline (domain, size + 16);
4618                 start = (gpointer)ALIGN_TO (start, 16);
4619         } else {
4620                 start = mono_domain_code_reserve (domain, size);
4621         }
4622         memcpy (start, buf, size);
4623
4624         mono_arch_flush_icache (start, size);
4625
4626         mono_stats.imt_thunks_size += size;
4627
4628         mono_tramp_info_register (mono_tramp_info_create (NULL, start, size, NULL, NULL), domain);
4629
4630         return start;
4631 }
4632
4633 MonoMethod*
4634 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4635 {
4636         return (MonoMethod*)regs [IA64_R9];
4637 }
4638
4639 gpointer
4640 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4641 {
4642         return (gpointer)regs [IA64_R10];
4643 }
4644
4645 gpointer
4646 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4647 {
4648         return NULL;
4649 }
4650
4651 gpointer
4652 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
4653 {
4654         return NULL;
4655 }
4656
4657 MonoInst*
4658 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4659 {
4660         MonoInst *ins = NULL;
4661
4662         if (cmethod->klass->image == mono_defaults.corlib &&
4663                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4664                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4665
4666                 /*
4667                  * We don't use the generic version in mini_emit_inst_for_method () since we
4668                  * ia64 has atomic_add_imm opcodes.
4669                  */
4670                 if (strcmp (cmethod->name, "Increment") == 0) {
4671                         guint32 opcode;
4672
4673                         if (fsig->params [0]->type == MONO_TYPE_I4)
4674                                 opcode = OP_ATOMIC_ADD_IMM_I4;
4675                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4676                                 opcode = OP_ATOMIC_ADD_IMM_I8;
4677                         else
4678                                 g_assert_not_reached ();
4679                         MONO_INST_NEW (cfg, ins, opcode);
4680                         ins->dreg = mono_alloc_preg (cfg);
4681                         ins->inst_imm = 1;
4682                         ins->inst_basereg = args [0]->dreg;
4683                         ins->inst_offset = 0;
4684                         MONO_ADD_INS (cfg->cbb, ins);
4685                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4686                         guint32 opcode;
4687
4688                         if (fsig->params [0]->type == MONO_TYPE_I4)
4689                                 opcode = OP_ATOMIC_ADD_IMM_I4;
4690                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4691                                 opcode = OP_ATOMIC_ADD_IMM_I8;
4692                         else
4693                                 g_assert_not_reached ();
4694                         MONO_INST_NEW (cfg, ins, opcode);
4695                         ins->dreg = mono_alloc_preg (cfg);
4696                         ins->inst_imm = -1;
4697                         ins->inst_basereg = args [0]->dreg;
4698                         ins->inst_offset = 0;
4699                         MONO_ADD_INS (cfg->cbb, ins);
4700                 } else if (strcmp (cmethod->name, "Add") == 0) {
4701                         guint32 opcode;
4702                         gboolean is_imm = FALSE;
4703                         gint64 imm = 0;
4704
4705                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4706                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4707
4708                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4709                         }
4710
4711                         if (is_imm) {
4712                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4713                                         opcode = OP_ATOMIC_ADD_IMM_I4;
4714                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4715                                         opcode = OP_ATOMIC_ADD_IMM_I8;
4716                                 else
4717                                         g_assert_not_reached ();
4718
4719                                 MONO_INST_NEW (cfg, ins, opcode);
4720                                 ins->dreg = mono_alloc_ireg (cfg);
4721                                 ins->inst_basereg = args [0]->dreg;
4722                                 ins->inst_offset = 0;
4723                                 ins->inst_imm = imm;
4724                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_I4) ? STACK_I4 : STACK_I8;
4725                         } else {
4726                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4727                                         opcode = OP_ATOMIC_ADD_I4;
4728                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4729                                         opcode = OP_ATOMIC_ADD_I8;
4730                                 else
4731                                         g_assert_not_reached ();
4732
4733                                 MONO_INST_NEW (cfg, ins, opcode);
4734                                 ins->dreg = mono_alloc_ireg (cfg);
4735                                 ins->inst_basereg = args [0]->dreg;
4736                                 ins->inst_offset = 0;
4737                                 ins->sreg2 = args [1]->dreg;
4738                                 ins->type = (opcode == OP_ATOMIC_ADD_I4) ? STACK_I4 : STACK_I8;
4739                         }
4740                         MONO_ADD_INS (cfg->cbb, ins);
4741                 }
4742         }
4743
4744         return ins;
4745 }
4746
4747 gboolean
4748 mono_arch_print_tree (MonoInst *tree, int arity)
4749 {
4750         return 0;
4751 }
4752
4753 mgreg_t
4754 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4755 {
4756         /* FIXME: implement */
4757         g_assert_not_reached ();
4758 }
4759
4760 gboolean
4761 mono_arch_opcode_supported (int opcode)
4762 {
4763         switch (opcode) {
4764         case OP_ATOMIC_ADD_I4:
4765         case OP_ATOMIC_ADD_I8:
4766         case OP_ATOMIC_EXCHANGE_I4:
4767         case OP_ATOMIC_EXCHANGE_I8:
4768                 return TRUE;
4769         default:
4770                 return FALSE;
4771         }
4772 }