mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583                 printf (" [%d]", (int)ins->inst_imm);
 584                 break;
 585         case OP_ADD_IMM:
 586         case OP_LADD_IMM:
 587                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 588                 break;
 589         case OP_I8CONST:
 590                 printf (" [%lld]", (long long)ins->inst_l);
 591                 break;
 592         case OP_R8CONST:
 593                 printf (" [%f]", *(double*)ins->inst_p0);
 594                 break;
 595         case OP_R4CONST:
 596                 printf (" [%f]", *(float*)ins->inst_p0);
 597                 break;
 598         case OP_CALL:
 599         case OP_CALL_MEMBASE:
 600         case OP_CALL_REG:
 601         case OP_FCALL:
 602         case OP_LCALL:
 603         case OP_VCALL:
 604         case OP_VCALL_REG:
 605         case OP_VCALL_MEMBASE:
 606         case OP_VCALL2:
 607         case OP_VCALL2_REG:
 608         case OP_VCALL2_MEMBASE:
 609         case OP_VOIDCALL:
 610         case OP_VOIDCALL_MEMBASE:
 611         case OP_TAILCALL: {
 612                 MonoCallInst *call = (MonoCallInst*)ins;
 613                 GSList *list;
 614
 615                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 616                         /*
 617                          * These are lowered opcodes, but they are in the .md files since the old
 618                          * JIT passes them to backends.
 619                          */
 620                         if (ins->dreg != -1)
 621                                 printf (" R%d <-", ins->dreg);
 622                 }
 623
 624                 if (call->method) {
 625                         char *full_name = mono_method_full_name (call->method, TRUE);
 626                         printf (" [%s]", full_name);
 627                         g_free (full_name);
 628                 } else if (call->fptr_is_patch) {
 629                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 630
 631                         printf (" ");
 632                         mono_print_ji (ji);
 633                 } else if (call->fptr) {
 634                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 635                         if (info)
 636                                 printf (" [%s]", info->name);
 637                 }
 638
 639                 list = call->out_ireg_args;
 640                 while (list) {
 641                         guint32 regpair;
 642                         int reg, hreg;
 643
 644                         regpair = (guint32)(gssize)(list->data);
 645                         hreg = regpair >> 24;
 646                         reg = regpair & 0xffffff;
 647
 648                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 649
 650                         list = g_slist_next (list);
 651                 }
 652                 break;
 653         }
 654         case OP_BR:
 655         case OP_CALL_HANDLER:
 656                 printf (" [B%d]", ins->inst_target_bb->block_num);
 657                 break;
 658         case OP_IBNE_UN:
 659         case OP_IBEQ:
 660         case OP_IBLT:
 661         case OP_IBLT_UN:
 662         case OP_IBGT:
 663         case OP_IBGT_UN:
 664         case OP_IBGE:
 665         case OP_IBGE_UN:
 666         case OP_IBLE:
 667         case OP_IBLE_UN:
 668         case OP_LBNE_UN:
 669         case OP_LBEQ:
 670         case OP_LBLT:
 671         case OP_LBLT_UN:
 672         case OP_LBGT:
 673         case OP_LBGT_UN:
 674         case OP_LBGE:
 675         case OP_LBGE_UN:
 676         case OP_LBLE:
 677         case OP_LBLE_UN:
 678                 if (!ins->inst_false_bb)
 679                         printf (" [B%d]", ins->inst_true_bb->block_num);
 680                 else
 681                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 682                 break;
 683         case OP_LIVERANGE_START:
 684         case OP_LIVERANGE_END:
 685         case OP_GC_LIVENESS_DEF:
 686         case OP_GC_LIVENESS_USE:
 687                 printf (" R%d", (int)ins->inst_c1);
 688                 break;
 689         case OP_SEQ_POINT:
 690                 printf (" il: %x", (int)ins->inst_imm);
 691                 break;
 692         default:
 693                 break;
 694         }
 695
 696         if (spec [MONO_INST_CLOB])
 697                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 698         printf ("\n");
 699 }
 700
 701 static void
 702 print_regtrack (RegTrack *t, int num)
 703 {
 704         int i;
 705         char buf [32];
 706         const char *r;
 707
 708         for (i = 0; i < num; ++i) {
 709                 if (!t [i].born_in)
 710                         continue;
 711                 if (i >= MONO_MAX_IREGS) {
 712                         g_snprintf (buf, sizeof(buf), "R%d", i);
 713                         r = buf;
 714                 } else
 715                         r = mono_arch_regname (i);
 716                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 717         }
 718 }
 719 #else
 720
 721 void
 722 mono_print_ji (const MonoJumpInfo *ji)
 723 {
 724 }
 725
 726 void
 727 mono_print_ins_index (int i, MonoInst *ins)
 728 {
 729 }
 730 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 731
 732 void
 733 mono_print_ins (MonoInst *ins)
 734 {
 735         mono_print_ins_index (-1, ins);
 736 }
 737
 738 static inline void
 739 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 740 {
 741         /*
 742          * If this function is called multiple times, the new instructions are inserted
 743          * in the proper order.
 744          */
 745         mono_bblock_insert_before_ins (bb, ins, to_insert);
 746 }
 747
 748 static inline void
 749 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 750 {
 751         /*
 752          * If this function is called multiple times, the new instructions are inserted in
 753          * proper order.
 754          */
 755         mono_bblock_insert_after_ins (bb, *last, to_insert);
 756
 757         *last = to_insert;
 758 }
 759
 760 static inline int
 761 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 762 {
 763         if (vreg_is_ref (cfg, reg))
 764                 return MONO_REG_INT_REF;
 765         else if (vreg_is_mp (cfg, reg))
 766                 return MONO_REG_INT_MP;
 767         else
 768                 return bank;
 769 }
 770
 771 /*
 772  * Force the spilling of the variable in the symbolic register 'reg', and free
 773  * the hreg it was assigned to.
 774  */
 775 static void
 776 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 777 {
 778         MonoInst *load;
 779         int i, sel, spill;
 780         int *symbolic;
 781         MonoRegState *rs = cfg->rs;
 782
 783         symbolic = rs->symbolic [bank];
 784         sel = rs->vassign [reg];
 785
 786         /* the vreg we need to spill lives in another logical reg bank */
 787         bank = translate_bank (cfg->rs, bank, sel);
 788
 789         /*i = rs->isymbolic [sel];
 790         g_assert (i == reg);*/
 791         i = reg;
 792         spill = ++cfg->spill_count;
 793         rs->vassign [i] = -spill - 1;
 794         if (G_UNLIKELY (bank))
 795                 mono_regstate_free_general (rs, sel, bank);
 796         else
 797                 mono_regstate_free_int (rs, sel);
 798         /* we need to create a spill var and insert a load to sel after the current instruction */
 799         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 800         load->dreg = sel;
 801         load->inst_basereg = cfg->frame_reg;
 802         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 803         insert_after_ins (bb, ins, last, load);
 804         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 805         if (G_UNLIKELY (bank))
 806                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 807         else
 808                 i = mono_regstate_alloc_int (rs, regmask (sel));
 809         g_assert (i == sel);
 810
 811         if (G_UNLIKELY (bank))
 812                 mono_regstate_free_general (rs, sel, bank);
 813         else
 814                 mono_regstate_free_int (rs, sel);
 815 }
 816
 817 /* This isn't defined on older glib versions and on some platforms */
 818 #ifndef G_GUINT64_FORMAT
 819 #define G_GUINT64_FORMAT "ul"
 820 #endif
 821
 822 static int
 823 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 824 {
 825         MonoInst *load;
 826         int i, sel, spill, num_sregs;
 827         int sregs [MONO_MAX_SRC_REGS];
 828         int *symbolic;
 829         MonoRegState *rs = cfg->rs;
 830
 831         symbolic = rs->symbolic [bank];
 832
 833         g_assert (bank < MONO_NUM_REGBANKS);
 834
 835         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 836         /* exclude the registers in the current instruction */
 837         num_sregs = mono_inst_get_src_registers (ins, sregs);
 838         for (i = 0; i < num_sregs; ++i) {
 839                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 840                         if (is_soft_reg (sregs [i], bank))
 841                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 842                         else
 843                                 regmask &= ~ (regmask (sregs [i]));
 844                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 845                 }
 846         }
 847         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 848                 regmask &= ~ (regmask (ins->dreg));
 849                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 850         }
 851
 852         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 853         g_assert (regmask); /* need at least a register we can free */
 854         sel = 0;
 855         /* we should track prev_use and spill the register that's farther */
 856         if (G_UNLIKELY (bank)) {
 857                 for (i = 0; i < regbank_size [bank]; ++i) {
 858                         if (regmask & (regmask (i))) {
 859                                 sel = i;
 860
 861                                 /* the vreg we need to load lives in another logical bank */
 862                                 bank = translate_bank (cfg->rs, bank, sel);
 863
 864                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 865                                 break;
 866                         }
 867                 }
 868
 869                 i = rs->symbolic [bank] [sel];
 870                 spill = ++cfg->spill_count;
 871                 rs->vassign [i] = -spill - 1;
 872                 mono_regstate_free_general (rs, sel, bank);
 873         }
 874         else {
 875                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 876                         if (regmask & (regmask (i))) {
 877                                 sel = i;
 878                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 879                                 break;
 880                         }
 881                 }
 882
 883                 i = rs->isymbolic [sel];
 884                 spill = ++cfg->spill_count;
 885                 rs->vassign [i] = -spill - 1;
 886                 mono_regstate_free_int (rs, sel);
 887         }
 888
 889         /* we need to create a spill var and insert a load to sel after the current instruction */
 890         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 891         load->dreg = sel;
 892         load->inst_basereg = cfg->frame_reg;
 893         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 894         insert_after_ins (bb, ins, last, load);
 895         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 896         if (G_UNLIKELY (bank))
 897                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 898         else
 899                 i = mono_regstate_alloc_int (rs, regmask (sel));
 900         g_assert (i == sel);
 901
 902         return sel;
 903 }
 904
 905 /*
 906  * free_up_hreg:
 907  *
 908  *   Free up the hreg HREG by spilling the vreg allocated to it.
 909  */
 910 static void
 911 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 912 {
 913         if (G_UNLIKELY (bank)) {
 914                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 915                         bank = translate_bank (cfg->rs, bank, hreg);
 916                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 917                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 918                 }
 919         }
 920         else {
 921                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 922                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 923                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 924                 }
 925         }
 926 }
 927
 928 static MonoInst*
 929 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 930 {
 931         MonoInst *copy;
 932
 933         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 934
 935         copy->dreg = dest;
 936         copy->sreg1 = src;
 937         copy->cil_code = ip;
 938         if (ins) {
 939                 mono_bblock_insert_after_ins (bb, ins, copy);
 940                 *last = copy;
 941         }
 942         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 943         return copy;
 944 }
 945
 946 static inline const char*
 947 regbank_to_string (int bank)
 948 {
 949         if (bank == MONO_REG_INT_REF)
 950                 return "REF ";
 951         else if (bank == MONO_REG_INT_MP)
 952                 return "MP ";
 953         else
 954                 return "";
 955 }
 956
 957 static void
 958 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 959 {
 960         MonoInst *store, *def;
 961
 962         bank = get_vreg_bank (cfg, prev_reg, bank);
 963
 964         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 965         store->sreg1 = reg;
 966         store->inst_destbasereg = cfg->frame_reg;
 967         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 968         if (ins) {
 969                 mono_bblock_insert_after_ins (bb, ins, store);
 970                 *last = store;
 971         } else if (insert_before) {
 972                 insert_before_ins (bb, insert_before, store);
 973         } else {
 974                 g_assert_not_reached ();
 975         }
 976         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 977
 978         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 979                 g_assert (prev_reg != -1);
 980                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 981                 def->inst_c0 = spill;
 982                 def->inst_c1 = bank;
 983                 mono_bblock_insert_after_ins (bb, store, def);
 984         }
 985 }
 986
 987 /* flags used in reginfo->flags */
 988 enum {
 989         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 990         MONO_FP_NEEDS_SPILL                     = regmask (1),
 991         MONO_FP_NEEDS_LOAD                      = regmask (2)
 992 };
 993
 994 static inline int
 995 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 996 {
 997         int val;
 998
 999         if (info && info->preferred_mask) {
1000                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1001                 if (val >= 0) {
1002                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1003                         return val;
1004                 }
1005         }
1006
1007         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1008         if (val < 0)
1009                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1010
1011         return val;
1012 }
1013
1014 static inline int
1015 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1016 {
1017         int val;
1018
1019         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1020
1021         if (val < 0)
1022                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1023
1024         return val;
1025 }
1026
1027 static inline int
1028 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1029 {
1030         if (G_UNLIKELY (bank))
1031                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1032         else
1033                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1034 }
1035
1036 static inline void
1037 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1038 {
1039         if (G_UNLIKELY (bank)) {
1040                 int mirrored_bank;
1041
1042                 g_assert (reg >= regbank_size [bank]);
1043                 g_assert (hreg < regbank_size [bank]);
1044                 g_assert (! is_global_freg (hreg));
1045
1046                 rs->vassign [reg] = hreg;
1047                 rs->symbolic [bank] [hreg] = reg;
1048                 rs->free_mask [bank] &= ~ (regmask (hreg));
1049
1050                 mirrored_bank = get_mirrored_bank (bank);
1051                 if (mirrored_bank == -1)
1052                         return;
1053
1054                 /* Make sure the other logical reg bank that this bank shares
1055                  * a single hard reg bank knows that this hard reg is not free.
1056                  */
1057                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1058
1059                 /* Mark the other logical bank that the this bank shares
1060                  * a single hard reg bank with as mirrored.
1061                  */
1062                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1063
1064         }
1065         else {
1066                 g_assert (reg >= MONO_MAX_IREGS);
1067                 g_assert (hreg < MONO_MAX_IREGS);
1068 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1069                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1070                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1071                 g_assert (! is_global_ireg (hreg));
1072 #endif
1073
1074                 rs->vassign [reg] = hreg;
1075                 rs->isymbolic [hreg] = reg;
1076                 rs->ifree_mask &= ~ (regmask (hreg));
1077         }
1078 }
1079
1080 static inline regmask_t
1081 get_callee_mask (const char spec)
1082 {
1083         if (G_UNLIKELY (reg_bank (spec)))
1084                 return regbank_callee_regs [reg_bank (spec)];
1085         return MONO_ARCH_CALLEE_REGS;
1086 }
1087
1088 static gint8 desc_to_fixed_reg [256];
1089 static gboolean desc_to_fixed_reg_inited = FALSE;
1090
1091 #ifndef DISABLE_JIT
1092
1093 /*
1094  * Local register allocation.
1095  * We first scan the list of instructions and we save the liveness info of
1096  * each register (when the register is first used, when it's value is set etc.).
1097  * We also reverse the list of instructions because assigning registers backwards allows
1098  * for more tricks to be used.
1099  */
1100 void
1101 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1102 {
1103         MonoInst *ins, *prev, *last;
1104         MonoInst **tmp;
1105         MonoRegState *rs = cfg->rs;
1106         int i, j, val, max;
1107         RegTrack *reginfo;
1108         const char *spec;
1109         unsigned char spec_src1, spec_dest;
1110         int bank = 0;
1111 #if MONO_ARCH_USE_FPSTACK
1112         gboolean has_fp = FALSE;
1113         int fpstack [8];
1114         int sp = 0;
1115 #endif
1116         int num_sregs = 0;
1117         int sregs [MONO_MAX_SRC_REGS];
1118
1119         if (!bb->code)
1120                 return;
1121
1122         if (!desc_to_fixed_reg_inited) {
1123                 for (i = 0; i < 256; ++i)
1124                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1125                 desc_to_fixed_reg_inited = TRUE;
1126
1127                 /* Validate the cpu description against the info in mini-ops.h */
1128 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1129                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1130                         const char *ispec;
1131
1132                         spec = ins_get_spec (i);
1133                         ispec = INS_INFO (i);
1134
1135                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1136                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1137                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1138                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1139                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1140                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1141                 }
1142 #endif
1143         }
1144
1145         rs->next_vreg = bb->max_vreg;
1146         mono_regstate_assign (rs);
1147
1148         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1149         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1150                 rs->free_mask [i] = regbank_callee_regs [i];
1151
1152         max = rs->next_vreg;
1153
1154         if (cfg->reginfo && cfg->reginfo_len < max)
1155                 cfg->reginfo = NULL;
1156
1157         reginfo = cfg->reginfo;
1158         if (!reginfo) {
1159                 cfg->reginfo_len = MAX (1024, max * 2);
1160                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1161         }
1162         else
1163                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1164
1165         if (cfg->verbose_level > 1) {
1166                 /* print_regtrack reads the info of all variables */
1167                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1168         }
1169
1170         /*
1171          * For large methods, next_vreg can be very large, so g_malloc0 time can
1172          * be prohibitive. So we manually init the reginfo entries used by the
1173          * bblock.
1174          */
1175         for (ins = bb->code; ins; ins = ins->next) {
1176                 gboolean modify = FALSE;
1177
1178                 spec = ins_get_spec (ins->opcode);
1179
1180                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1181                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1182 #if SIZEOF_REGISTER == 4
1183                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1184                                 /**
1185                                  * In the new IR, the two vregs of the regpair do not alias the
1186                                  * original long vreg. shift the vreg here so the rest of the
1187                                  * allocator doesn't have to care about it.
1188                                  */
1189                                 ins->dreg ++;
1190                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1191                         }
1192 #endif
1193                 }
1194
1195                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1196                 for (j = 0; j < num_sregs; ++j) {
1197                         g_assert (sregs [j] != -1);
1198                         if (sregs [j] < max) {
1199                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1200 #if SIZEOF_REGISTER == 4
1201                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1202                                         sregs [j]++;
1203                                         modify = TRUE;
1204                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1205                                 }
1206 #endif
1207                         }
1208                 }
1209                 if (modify)
1210                         mono_inst_set_src_registers (ins, sregs);
1211         }
1212
1213         /*if (cfg->opt & MONO_OPT_COPYPROP)
1214                 local_copy_prop (cfg, ins);*/
1215
1216         i = 1;
1217         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1218         /* forward pass on the instructions to collect register liveness info */
1219         MONO_BB_FOR_EACH_INS (bb, ins) {
1220                 spec = ins_get_spec (ins->opcode);
1221                 spec_dest = spec [MONO_INST_DEST];
1222
1223                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1224                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1225                 }
1226
1227                 DEBUG (mono_print_ins_index (i, ins));
1228
1229                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1230
1231 #if MONO_ARCH_USE_FPSTACK
1232                 if (dreg_is_fp (spec)) {
1233                         has_fp = TRUE;
1234                 } else {
1235                         for (j = 0; j < num_sregs; ++j) {
1236                                 if (sreg_is_fp (j, spec))
1237                                         has_fp = TRUE;
1238                         }
1239                 }
1240 #endif
1241
1242                 for (j = 0; j < num_sregs; ++j) {
1243                         int sreg = sregs [j];
1244                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1245                         if (sreg_spec) {
1246                                 bank = sreg_bank (j, spec);
1247                                 g_assert (sreg != -1);
1248                                 if (is_soft_reg (sreg, bank))
1249                                         /* This means the vreg is not local to this bb */
1250                                         g_assert (reginfo [sreg].born_in > 0);
1251                                 rs->vassign [sreg] = -1;
1252                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1253                                 //reginfo [ins->sreg2].last_use = i;
1254                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1255                                         /* The virtual register is allocated sequentially */
1256                                         rs->vassign [sreg + 1] = -1;
1257                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1258                                         //reginfo [ins->sreg2 + 1].last_use = i;
1259                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1260                                                 reginfo [sreg + 1].born_in = i;
1261                                 }
1262                         } else {
1263                                 sregs [j] = -1;
1264                         }
1265                 }
1266                 mono_inst_set_src_registers (ins, sregs);
1267
1268                 if (spec_dest) {
1269                         int dest_dreg;
1270
1271                         bank = dreg_bank (spec);
1272                         if (spec_dest != 'b') /* it's not just a base register */
1273                                 reginfo [ins->dreg].killed_in = i;
1274                         g_assert (ins->dreg != -1);
1275                         rs->vassign [ins->dreg] = -1;
1276                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1277                         //reginfo [ins->dreg].last_use = i;
1278                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1279                                 reginfo [ins->dreg].born_in = i;
1280
1281                         dest_dreg = desc_to_fixed_reg [spec_dest];
1282                         if (dest_dreg != -1)
1283                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1284
1285 #ifdef MONO_ARCH_INST_FIXED_MASK
1286                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1287 #endif
1288
1289                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1290                                 /* The virtual register is allocated sequentially */
1291                                 rs->vassign [ins->dreg + 1] = -1;
1292                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1293                                 //reginfo [ins->dreg + 1].last_use = i;
1294                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1295                                         reginfo [ins->dreg + 1].born_in = i;
1296                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1297                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1298                         }
1299                 } else {
1300                         ins->dreg = -1;
1301                 }
1302
1303                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1304                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1305
1306                         MonoCallInst *call = (MonoCallInst*)ins;
1307                         GSList *list;
1308
1309                         list = call->out_ireg_args;
1310                         if (list) {
1311                                 while (list) {
1312                                         guint32 regpair;
1313                                         int reg, hreg;
1314
1315                                         regpair = (guint32)(gssize)(list->data);
1316                                         hreg = regpair >> 24;
1317                                         reg = regpair & 0xffffff;
1318
1319                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1320                                         //reginfo [reg].last_use = i;
1321
1322                                         list = g_slist_next (list);
1323                                 }
1324                         }
1325
1326                         list = call->out_freg_args;
1327                         if (list) {
1328                                 while (list) {
1329                                         guint32 regpair;
1330                                         int reg, hreg;
1331
1332                                         regpair = (guint32)(gssize)(list->data);
1333                                         hreg = regpair >> 24;
1334                                         reg = regpair & 0xffffff;
1335
1336                                         list = g_slist_next (list);
1337                                 }
1338                         }
1339                 }
1340
1341                 ++i;
1342         }
1343
1344         tmp = &last;
1345
1346         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1347         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1348                 int prev_dreg, clob_dreg;
1349                 int dest_dreg, clob_reg;
1350                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1351                 int dreg_high, sreg1_high;
1352                 regmask_t dreg_mask, mask;
1353                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1354                 regmask_t dreg_fixed_mask;
1355                 const unsigned char *ip;
1356                 --i;
1357                 spec = ins_get_spec (ins->opcode);
1358                 spec_src1 = spec [MONO_INST_SRC1];
1359                 spec_dest = spec [MONO_INST_DEST];
1360                 prev_dreg = -1;
1361                 clob_dreg = -1;
1362                 clob_reg = -1;
1363                 dest_dreg = -1;
1364                 dreg_high = -1;
1365                 sreg1_high = -1;
1366                 dreg_mask = get_callee_mask (spec_dest);
1367                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1368                         prev_sregs [j] = -1;
1369                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1370                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1371 #ifdef MONO_ARCH_INST_FIXED_MASK
1372                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1373 #else
1374                         sreg_fixed_masks [j] = 0;
1375 #endif
1376                 }
1377
1378                 DEBUG (printf ("processing:"));
1379                 DEBUG (mono_print_ins_index (i, ins));
1380
1381                 ip = ins->cil_code;
1382
1383                 last = ins;
1384
1385                 /*
1386                  * FIXED REGS
1387                  */
1388                 dest_dreg = desc_to_fixed_reg [spec_dest];
1389                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1390                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1391
1392 #ifdef MONO_ARCH_INST_FIXED_MASK
1393                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1394 #else
1395                 dreg_fixed_mask = 0;
1396 #endif
1397
1398                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1399
1400                 /*
1401                  * TRACK FIXED SREG2, 3, ...
1402                  */
1403                 for (j = 1; j < num_sregs; ++j) {
1404                         int sreg = sregs [j];
1405                         int dest_sreg = dest_sregs [j];
1406
1407                         if (dest_sreg == -1)
1408                                 continue;
1409
1410                         if (j == 2) {
1411                                 int k;
1412
1413                                 /*
1414                                  * CAS.
1415                                  * We need to special case this, since on x86, there are only 3
1416                                  * free registers, and the code below assigns one of them to
1417                                  * sreg, so we can run out of registers when trying to assign
1418                                  * dreg. Instead, we just set up the register masks, and let the
1419                                  * normal sreg2 assignment code handle this. It would be nice to
1420                                  * do this for all the fixed reg cases too, but there is too much
1421                                  * risk of breakage.
1422                                  */
1423
1424                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1425                                 sreg_masks [j] = regmask (dest_sreg);
1426                                 for (k = 0; k < num_sregs; ++k) {
1427                                         if (k != j)
1428                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1429                                 }
1430
1431                                 /*
1432                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1433                                  */
1434                                 for (k = 0; k < num_sregs; ++k) {
1435                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1436                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1437                                 }
1438
1439                                 /*
1440                                  * We can also run out of registers while processing sreg2 if sreg3 is
1441                                  * assigned to another hreg, so spill sreg3 now.
1442                                  */
1443                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1444                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1445                                 }
1446                                 continue;
1447                         }
1448
1449                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1450                                 if (is_global_ireg (sreg)) {
1451                                         int k;
1452                                         /* Argument already in hard reg, need to copy */
1453                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1454                                         insert_before_ins (bb, ins, copy);
1455                                         for (k = 0; k < num_sregs; ++k) {
1456                                                 if (k != j)
1457                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1458                                         }
1459                                         /* See below */
1460                                         dreg_mask &= ~ (regmask (dest_sreg));
1461                                 } else {
1462                                         val = rs->vassign [sreg];
1463                                         if (val == -1) {
1464                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1465                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1466                                         } else if (val < -1) {
1467                                                 /* FIXME: */
1468                                                 g_assert_not_reached ();
1469                                         } else {
1470                                                 /* Argument already in hard reg, need to copy */
1471                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1472                                                 int k;
1473
1474                                                 insert_before_ins (bb, ins, copy);
1475                                                 for (k = 0; k < num_sregs; ++k) {
1476                                                         if (k != j)
1477                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1478                                                 }
1479                                                 /*
1480                                                  * Prevent the dreg from being allocated to dest_sreg
1481                                                  * too, since it could force sreg1 to be allocated to
1482                                                  * the same reg on x86.
1483                                                  */
1484                                                 dreg_mask &= ~ (regmask (dest_sreg));
1485                                         }
1486                                 }
1487                         } else {
1488                                 gboolean need_spill = TRUE;
1489                                 gboolean need_assign = TRUE;
1490                                 int k;
1491
1492                                 dreg_mask &= ~ (regmask (dest_sreg));
1493                                 for (k = 0; k < num_sregs; ++k) {
1494                                         if (k != j)
1495                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1496                                 }
1497
1498                                 /*
1499                                  * First check if dreg is assigned to dest_sreg2, since we
1500                                  * can't spill a dreg.
1501                                  */
1502                                 if (spec [MONO_INST_DEST])
1503                                         val = rs->vassign [ins->dreg];
1504                                 else
1505                                         val = -1;
1506                                 if (val == dest_sreg && ins->dreg != sreg) {
1507                                         /*
1508                                          * the destination register is already assigned to
1509                                          * dest_sreg2: we need to allocate another register for it
1510                                          * and then copy from this to dest_sreg2.
1511                                          */
1512                                         int new_dest;
1513                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1514                                         g_assert (new_dest >= 0);
1515                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1516
1517                                         prev_dreg = ins->dreg;
1518                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1519                                         clob_dreg = ins->dreg;
1520                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1521                                         mono_regstate_free_int (rs, dest_sreg);
1522                                         need_spill = FALSE;
1523                                 }
1524
1525                                 if (is_global_ireg (sreg)) {
1526                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1527                                         insert_before_ins (bb, ins, copy);
1528                                         need_assign = FALSE;
1529                                 }
1530                                 else {
1531                                         val = rs->vassign [sreg];
1532                                         if (val == dest_sreg) {
1533                                                 /* sreg2 is already assigned to the correct register */
1534                                                 need_spill = FALSE;
1535                                         } else if (val < -1) {
1536                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1537                                         } else if (val >= 0) {
1538                                                 /* sreg2 already assigned to another register */
1539                                                 /*
1540                                                  * We couldn't emit a copy from val to dest_sreg2, because
1541                                                  * val might be spilled later while processing this
1542                                                  * instruction. So we spill sreg2 so it can be allocated to
1543                                                  * dest_sreg2.
1544                                                  */
1545                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1546                                         }
1547                                 }
1548
1549                                 if (need_spill) {
1550                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1551                                 }
1552
1553                                 if (need_assign) {
1554                                         if (rs->vassign [sreg] < -1) {
1555                                                 int spill;
1556
1557                                                 /* Need to emit a spill store */
1558                                                 spill = - rs->vassign [sreg] - 1;
1559                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1560                                         }
1561                                         /* force-set sreg2 */
1562                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1563                                 }
1564                         }
1565                         sregs [j] = dest_sreg;
1566                 }
1567                 mono_inst_set_src_registers (ins, sregs);
1568
1569                 /*
1570                  * TRACK DREG
1571                  */
1572                 bank = dreg_bank (spec);
1573                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1574                         prev_dreg = ins->dreg;
1575                 }
1576
1577                 if (spec_dest == 'b') {
1578                         /*
1579                          * The dest reg is read by the instruction, not written, so
1580                          * avoid allocating sreg1/sreg2 to the same reg.
1581                          */
1582                         if (dest_sregs [0] != -1)
1583                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1584                         for (j = 1; j < num_sregs; ++j) {
1585                                 if (dest_sregs [j] != -1)
1586                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1587                         }
1588
1589                         val = rs->vassign [ins->dreg];
1590                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1591                                 /* DREG is already allocated to a register needed for sreg1 */
1592                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1593                         }
1594                 }
1595
1596                 /*
1597                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1598                  * various complex situations.
1599                  */
1600                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1601                         guint32 dreg2, dest_dreg2;
1602
1603                         g_assert (is_soft_reg (ins->dreg, bank));
1604
1605                         if (dest_dreg != -1) {
1606                                 if (rs->vassign [ins->dreg] != dest_dreg)
1607                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1608
1609                                 dreg2 = ins->dreg + 1;
1610                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1611                                 if (dest_dreg2 != -1) {
1612                                         if (rs->vassign [dreg2] != dest_dreg2)
1613                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1614                                 }
1615                         }
1616                 }
1617
1618                 if (dreg_fixed_mask) {
1619                         g_assert (!bank);
1620                         if (is_global_ireg (ins->dreg)) {
1621                                 /*
1622                                  * The argument is already in a hard reg, but that reg is
1623                                  * not usable by this instruction, so allocate a new one.
1624                                  */
1625                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1626                                 if (val < 0)
1627                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1628                                 mono_regstate_free_int (rs, val);
1629                                 dest_dreg = val;
1630
1631                                 /* Fall through */
1632                         }
1633                         else
1634                                 dreg_mask &= dreg_fixed_mask;
1635                 }
1636
1637                 if (is_soft_reg (ins->dreg, bank)) {
1638                         val = rs->vassign [ins->dreg];
1639
1640                         if (val < 0) {
1641                                 int spill = 0;
1642                                 if (val < -1) {
1643                                         /* the register gets spilled after this inst */
1644                                         spill = -val -1;
1645                                 }
1646                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1647                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1648                                 if (spill)
1649                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1650                         }
1651
1652                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1653                         ins->dreg = val;
1654                 }
1655
1656                 /* Handle regpairs */
1657                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1658                         int reg2 = prev_dreg + 1;
1659
1660                         g_assert (!bank);
1661                         g_assert (prev_dreg > -1);
1662                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1663                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1664 #ifdef TARGET_X86
1665                         /* bug #80489 */
1666                         mask &= ~regmask (X86_ECX);
1667 #endif
1668                         val = rs->vassign [reg2];
1669                         if (val < 0) {
1670                                 int spill = 0;
1671                                 if (val < -1) {
1672                                         /* the register gets spilled after this inst */
1673                                         spill = -val -1;
1674                                 }
1675                                 val = mono_regstate_alloc_int (rs, mask);
1676                                 if (val < 0)
1677                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1678                                 if (spill)
1679                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1680                         }
1681                         else {
1682                                 if (! (mask & (regmask (val)))) {
1683                                         val = mono_regstate_alloc_int (rs, mask);
1684                                         if (val < 0)
1685                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1686
1687                                         /* Reallocate hreg to the correct register */
1688                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1689
1690                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1691                                 }
1692                         }
1693
1694                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1695                         assign_reg (cfg, rs, reg2, val, bank);
1696
1697                         dreg_high = val;
1698                         ins->backend.reg3 = val;
1699
1700                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1701                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1702                                 mono_regstate_free_int (rs, val);
1703                         }
1704                 }
1705
1706                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1707                         /*
1708                          * In theory, we could free up the hreg even if the vreg is alive,
1709                          * but branches inside bblocks force us to assign the same hreg
1710                          * to a vreg every time it is encountered.
1711                          */
1712                         int dreg = rs->vassign [prev_dreg];
1713                         g_assert (dreg >= 0);
1714                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1715                         if (G_UNLIKELY (bank))
1716                                 mono_regstate_free_general (rs, dreg, bank);
1717                         else
1718                                 mono_regstate_free_int (rs, dreg);
1719                         rs->vassign [prev_dreg] = -1;
1720                 }
1721
1722                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1723                         /* this instruction only outputs to dest_dreg, need to copy */
1724                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1725                         ins->dreg = dest_dreg;
1726
1727                         if (G_UNLIKELY (bank)) {
1728                                 /* the register we need to free up may be used in another logical regbank
1729                                  * so do a translate just in case.
1730                                  */
1731                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1732                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1733                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1734                         }
1735                         else {
1736                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1737                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1738                         }
1739                 }
1740
1741                 if (spec_dest == 'b') {
1742                         /*
1743                          * The dest reg is read by the instruction, not written, so
1744                          * avoid allocating sreg1/sreg2 to the same reg.
1745                          */
1746                         for (j = 0; j < num_sregs; ++j)
1747                                 if (!sreg_bank (j, spec))
1748                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1749                 }
1750
1751                 /*
1752                  * TRACK CLOBBERING
1753                  */
1754                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1755                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1756                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1757                 }
1758
1759                 if (spec [MONO_INST_CLOB] == 'c') {
1760                         int j, s, dreg, dreg2, cur_bank;
1761                         guint64 clob_mask;
1762
1763                         clob_mask = MONO_ARCH_CALLEE_REGS;
1764
1765                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1766                                 /*
1767                                  * Need to avoid spilling the dreg since the dreg is not really
1768                                  * clobbered by the call.
1769                                  */
1770                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1771                                         dreg = rs->vassign [prev_dreg];
1772                                 else
1773                                         dreg = -1;
1774
1775                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1776                                         dreg2 = rs->vassign [prev_dreg + 1];
1777                                 else
1778                                         dreg2 = -1;
1779
1780                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1781                                         s = regmask (j);
1782                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1783                                                 if ((j != dreg) && (j != dreg2))
1784                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1785                                                 else if (rs->isymbolic [j])
1786                                                         /* The hreg is assigned to the dreg of this instruction */
1787                                                         rs->vassign [rs->isymbolic [j]] = -1;
1788                                                 mono_regstate_free_int (rs, j);
1789                                         }
1790                                 }
1791                         }
1792
1793                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1794                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1795                                         clob_mask = regbank_callee_regs [cur_bank];
1796                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1797                                                 dreg = rs->vassign [prev_dreg];
1798                                         else
1799                                                 dreg = -1;
1800
1801                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1802
1803                                                 /* we are looping though the banks in the outer loop
1804                                                  * so, we don't need to deal with mirrored hregs
1805                                                  * because we will get them in one of the other bank passes.
1806                                                  */
1807                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1808                                                         continue;
1809
1810                                                 s = regmask (j);
1811                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1812                                                         if (j != dreg)
1813                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1814                                                         else if (rs->symbolic [cur_bank] [j])
1815                                                                 /* The hreg is assigned to the dreg of this instruction */
1816                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1817                                                         mono_regstate_free_general (rs, j, cur_bank);
1818                                                 }
1819                                         }
1820                                 }
1821                         }
1822                 }
1823
1824                 /*
1825                  * TRACK ARGUMENT REGS
1826                  */
1827                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1828                         MonoCallInst *call = (MonoCallInst*)ins;
1829                         GSList *list;
1830
1831                         /*
1832                          * This needs to be done before assigning sreg1, so sreg1 will
1833                          * not be assigned one of the argument regs.
1834                          */
1835
1836                         /*
1837                          * Assign all registers in call->out_reg_args to the proper
1838                          * argument registers.
1839                          */
1840
1841                         list = call->out_ireg_args;
1842                         if (list) {
1843                                 while (list) {
1844                                         guint32 regpair;
1845                                         int reg, hreg;
1846
1847                                         regpair = (guint32)(gssize)(list->data);
1848                                         hreg = regpair >> 24;
1849                                         reg = regpair & 0xffffff;
1850
1851                                         assign_reg (cfg, rs, reg, hreg, 0);
1852
1853                                         sreg_masks [0] &= ~(regmask (hreg));
1854
1855                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1856
1857                                         list = g_slist_next (list);
1858                                 }
1859                         }
1860
1861                         list = call->out_freg_args;
1862                         if (list) {
1863                                 while (list) {
1864                                         guint32 regpair;
1865                                         int reg, hreg;
1866
1867                                         regpair = (guint32)(gssize)(list->data);
1868                                         hreg = regpair >> 24;
1869                                         reg = regpair & 0xffffff;
1870
1871                                         assign_reg (cfg, rs, reg, hreg, 1);
1872
1873                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1874
1875                                         list = g_slist_next (list);
1876                                 }
1877                         }
1878                 }
1879
1880                 /*
1881                  * TRACK SREG1
1882                  */
1883                 bank = sreg1_bank (spec);
1884                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1885                         int sreg1 = sregs [0];
1886                         int dest_sreg1 = dest_sregs [0];
1887
1888                         g_assert (is_soft_reg (sreg1, bank));
1889
1890                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1891                         if (dest_sreg1 != -1)
1892                                 g_assert (dest_sreg1 == ins->dreg);
1893                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1894                         g_assert (val >= 0);
1895
1896                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1897                                 // FIXME:
1898                                 g_assert_not_reached ();
1899
1900                         assign_reg (cfg, rs, sreg1, val, bank);
1901
1902                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1903
1904                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1905                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1906                         g_assert (val >= 0);
1907
1908                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1909                                 // FIXME:
1910                                 g_assert_not_reached ();
1911
1912                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1913
1914                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1915
1916                         /* Skip rest of this section */
1917                         dest_sregs [0] = -1;
1918                 }
1919
1920                 if (sreg_fixed_masks [0]) {
1921                         g_assert (!bank);
1922                         if (is_global_ireg (sregs [0])) {
1923                                 /*
1924                                  * The argument is already in a hard reg, but that reg is
1925                                  * not usable by this instruction, so allocate a new one.
1926                                  */
1927                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1928                                 if (val < 0)
1929                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1930                                 mono_regstate_free_int (rs, val);
1931                                 dest_sregs [0] = val;
1932
1933                                 /* Fall through to the dest_sreg1 != -1 case */
1934                         }
1935                         else
1936                                 sreg_masks [0] &= sreg_fixed_masks [0];
1937                 }
1938
1939                 if (dest_sregs [0] != -1) {
1940                         sreg_masks [0] = regmask (dest_sregs [0]);
1941
1942                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1943                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1944                         }
1945                         if (is_global_ireg (sregs [0])) {
1946                                 /* The argument is already in a hard reg, need to copy */
1947                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1948                                 insert_before_ins (bb, ins, copy);
1949                                 sregs [0] = dest_sregs [0];
1950                         }
1951                 }
1952
1953                 if (is_soft_reg (sregs [0], bank)) {
1954                         val = rs->vassign [sregs [0]];
1955                         prev_sregs [0] = sregs [0];
1956                         if (val < 0) {
1957                                 int spill = 0;
1958                                 if (val < -1) {
1959                                         /* the register gets spilled after this inst */
1960                                         spill = -val -1;
1961                                 }
1962
1963                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1964                                         /*
1965                                          * Allocate the same hreg to sreg1 as well so the
1966                                          * peephole can get rid of the move.
1967                                          */
1968                                         sreg_masks [0] = regmask (ins->dreg);
1969                                 }
1970
1971                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1972                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1973                                         sreg_masks [0] = regmask (ins->dreg);
1974
1975                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1976                                 assign_reg (cfg, rs, sregs [0], val, bank);
1977                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1978
1979                                 if (spill) {
1980                                         /*
1981                                          * Need to insert before the instruction since it can
1982                                          * overwrite sreg1.
1983                                          */
1984                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1985                                 }
1986                         }
1987                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1988                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1989                                 insert_before_ins (bb, ins, copy);
1990                                 for (j = 1; j < num_sregs; ++j)
1991                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1992                                 val = dest_sregs [0];
1993                         }
1994
1995                         sregs [0] = val;
1996                 }
1997                 else {
1998                         prev_sregs [0] = -1;
1999                 }
2000                 mono_inst_set_src_registers (ins, sregs);
2001
2002                 for (j = 1; j < num_sregs; ++j)
2003                         sreg_masks [j] &= ~(regmask (sregs [0]));
2004
2005                 /* Handle the case when sreg1 is a regpair but dreg is not */
2006                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2007                         int reg2 = prev_sregs [0] + 1;
2008
2009                         g_assert (!bank);
2010                         g_assert (prev_sregs [0] > -1);
2011                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2012                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2013                         val = rs->vassign [reg2];
2014                         if (val < 0) {
2015                                 int spill = 0;
2016                                 if (val < -1) {
2017                                         /* the register gets spilled after this inst */
2018                                         spill = -val -1;
2019                                 }
2020                                 val = mono_regstate_alloc_int (rs, mask);
2021                                 if (val < 0)
2022                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2023                                 if (spill)
2024                                         g_assert_not_reached ();
2025                         }
2026                         else {
2027                                 if (! (mask & (regmask (val)))) {
2028                                         /* The vreg is already allocated to a wrong hreg */
2029                                         /* FIXME: */
2030                                         g_assert_not_reached ();
2031 #if 0
2032                                         val = mono_regstate_alloc_int (rs, mask);
2033                                         if (val < 0)
2034                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2035
2036                                         /* Reallocate hreg to the correct register */
2037                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2038
2039                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2040 #endif
2041                                 }
2042                         }
2043
2044                         sreg1_high = val;
2045                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2046                         assign_reg (cfg, rs, reg2, val, bank);
2047                 }
2048
2049                 /* Handle dreg==sreg1 */
2050                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2051                         MonoInst *sreg2_copy = NULL;
2052                         MonoInst *copy;
2053                         int bank = reg_bank (spec_src1);
2054
2055                         if (ins->dreg == sregs [1]) {
2056                                 /*
2057                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2058                                  * register for it.
2059                                  */
2060                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2061
2062                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2063                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2064                                 prev_sregs [1] = sregs [1] = reg2;
2065
2066                                 if (G_UNLIKELY (bank))
2067                                         mono_regstate_free_general (rs, reg2, bank);
2068                                 else
2069                                         mono_regstate_free_int (rs, reg2);
2070                         }
2071
2072                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2073                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2074                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2075                                         /* FIXME: */
2076                                         g_assert_not_reached ();
2077
2078                                 /*
2079                                  * sreg1 and dest are already allocated to the same regpair by the
2080                                  * SREG1 allocation code.
2081                                  */
2082                                 g_assert (sregs [0] == ins->dreg);
2083                                 g_assert (dreg_high == sreg1_high);
2084                         }
2085
2086                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2087                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2088                         insert_before_ins (bb, ins, copy);
2089
2090                         if (sreg2_copy)
2091                                 insert_before_ins (bb, copy, sreg2_copy);
2092
2093                         /*
2094                          * Need to prevent sreg2 to be allocated to sreg1, since that
2095                          * would screw up the previous copy.
2096                          */
2097                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2098                         /* we set sreg1 to dest as well */
2099                         prev_sregs [0] = sregs [0] = ins->dreg;
2100                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2101                 }
2102                 mono_inst_set_src_registers (ins, sregs);
2103
2104                 /*
2105                  * TRACK SREG2, 3, ...
2106                  */
2107                 for (j = 1; j < num_sregs; ++j) {
2108                         int k;
2109
2110                         bank = sreg_bank (j, spec);
2111                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2112                                 g_assert_not_reached ();
2113
2114                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2115                                 /*
2116                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2117                                  * allocating it to the fixed reg.
2118                                  */
2119                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2120                                 insert_before_ins (bb, ins, copy);
2121                                 sregs [j] = dest_sregs [j];
2122                         } else if (is_soft_reg (sregs [j], bank)) {
2123                                 val = rs->vassign [sregs [j]];
2124
2125                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2126                                         /*
2127                                          * The sreg is already allocated to a hreg, but not to the fixed
2128                                          * reg required by the instruction. Spill the sreg, so it can be
2129                                          * allocated to the fixed reg by the code below.
2130                                          */
2131                                         /* Currently, this code should only be hit for CAS */
2132                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2133                                         val = rs->vassign [sregs [j]];
2134                                 }
2135
2136                                 if (val < 0) {
2137                                         int spill = 0;
2138                                         if (val < -1) {
2139                                                 /* the register gets spilled after this inst */
2140                                                 spill = -val -1;
2141                                         }
2142                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2143                                         assign_reg (cfg, rs, sregs [j], val, bank);
2144                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2145                                         if (spill) {
2146                                                 /*
2147                                                  * Need to insert before the instruction since it can
2148                                                  * overwrite sreg2.
2149                                                  */
2150                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2151                                         }
2152                                 }
2153                                 sregs [j] = val;
2154                                 for (k = j + 1; k < num_sregs; ++k)
2155                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2156                         }
2157                         else {
2158                                 prev_sregs [j] = -1;
2159                         }
2160                 }
2161                 mono_inst_set_src_registers (ins, sregs);
2162
2163                 /* Sanity check */
2164                 /* Do this only for CAS for now */
2165                 for (j = 1; j < num_sregs; ++j) {
2166                         int sreg = sregs [j];
2167                         int dest_sreg = dest_sregs [j];
2168
2169                         if (j == 2 && dest_sreg != -1) {
2170                                 int k;
2171
2172                                 g_assert (sreg == dest_sreg);
2173
2174                                 for (k = 0; k < num_sregs; ++k) {
2175                                         if (k != j)
2176                                                 g_assert (sregs [k] != dest_sreg);
2177                                 }
2178                         }
2179                 }
2180
2181                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2182                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2183                         mono_regstate_free_int (rs, ins->sreg1);
2184                 }
2185                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2186                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2187                         mono_regstate_free_int (rs, ins->sreg2);
2188                 }*/
2189
2190                 DEBUG (mono_print_ins_index (i, ins));
2191         }
2192
2193         // FIXME: Set MAX_FREGS to 8
2194         // FIXME: Optimize generated code
2195 #if MONO_ARCH_USE_FPSTACK
2196         /*
2197          * Make a forward pass over the code, simulating the fp stack, making sure the
2198          * arguments required by the fp opcodes are at the top of the stack.
2199          */
2200         if (has_fp) {
2201                 MonoInst *prev = NULL;
2202                 MonoInst *fxch;
2203                 int tmp;
2204
2205                 g_assert (num_sregs <= 2);
2206
2207                 for (ins = bb->code; ins; ins = ins->next) {
2208                         spec = ins_get_spec (ins->opcode);
2209
2210                         DEBUG (printf ("processing:"));
2211                         DEBUG (mono_print_ins_index (0, ins));
2212
2213                         if (ins->opcode == OP_FMOVE) {
2214                                 /* Do it by renaming the source to the destination on the stack */
2215                                 // FIXME: Is this correct ?
2216                                 for (i = 0; i < sp; ++i)
2217                                         if (fpstack [i] == ins->sreg1)
2218                                                 fpstack [i] = ins->dreg;
2219                                 prev = ins;
2220                                 continue;
2221                         }
2222
2223                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2224                                 /* Arg1 must be in %st(1) */
2225                                 g_assert (prev);
2226
2227                                 i = 0;
2228                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2229                                         i ++;
2230                                 g_assert (i < sp);
2231
2232                                 if (sp - 1 - i > 0) {
2233                                         /* First move it to %st(0) */
2234                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2235
2236                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2237                                         fxch->inst_imm = sp - 1 - i;
2238
2239                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2240                                         prev = fxch;
2241
2242                                         tmp = fpstack [sp - 1];
2243                                         fpstack [sp - 1] = fpstack [i];
2244                                         fpstack [i] = tmp;
2245                                 }
2246
2247                                 /* Then move it to %st(1) */
2248                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2249
2250                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2251                                 fxch->inst_imm = 1;
2252
2253                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2254                                 prev = fxch;
2255
2256                                 tmp = fpstack [sp - 1];
2257                                 fpstack [sp - 1] = fpstack [sp - 2];
2258                                 fpstack [sp - 2] = tmp;
2259                         }
2260
2261                         if (sreg2_is_fp (spec)) {
2262                                 g_assert (sp > 0);
2263
2264                                 if (fpstack [sp - 1] != ins->sreg2) {
2265                                         g_assert (prev);
2266
2267                                         i = 0;
2268                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2269                                                 i ++;
2270                                         g_assert (i < sp);
2271
2272                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2273
2274                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2275                                         fxch->inst_imm = sp - 1 - i;
2276
2277                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2278                                         prev = fxch;
2279
2280                                         tmp = fpstack [sp - 1];
2281                                         fpstack [sp - 1] = fpstack [i];
2282                                         fpstack [i] = tmp;
2283                                 }
2284
2285                                 sp --;
2286                         }
2287
2288                         if (sreg1_is_fp (spec)) {
2289                                 g_assert (sp > 0);
2290
2291                                 if (fpstack [sp - 1] != ins->sreg1) {
2292                                         g_assert (prev);
2293
2294                                         i = 0;
2295                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2296                                                 i ++;
2297                                         g_assert (i < sp);
2298
2299                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2300
2301                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2302                                         fxch->inst_imm = sp - 1 - i;
2303
2304                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2305                                         prev = fxch;
2306
2307                                         tmp = fpstack [sp - 1];
2308                                         fpstack [sp - 1] = fpstack [i];
2309                                         fpstack [i] = tmp;
2310                                 }
2311
2312                                 sp --;
2313                         }
2314
2315                         if (dreg_is_fp (spec)) {
2316                                 g_assert (sp < 8);
2317                                 fpstack [sp ++] = ins->dreg;
2318                         }
2319
2320                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2321                                 printf ("\t[");
2322                                 for (i = 0; i < sp; ++i)
2323                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2324                                 printf ("]\n");
2325                         }
2326
2327                         prev = ins;
2328                 }
2329
2330                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2331                         /* Remove remaining items from the fp stack */
2332                         /*
2333                          * These can remain for example as a result of a dead fmove like in
2334                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2335                          */
2336                         while (sp) {
2337                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2338                                 mono_add_ins_to_end (bb, ins);
2339                                 sp --;
2340                         }
2341                 }
2342         }
2343 #endif
2344 }
2345
2346 CompRelation
2347 mono_opcode_to_cond (int opcode)
2348 {
2349         switch (opcode) {
2350         case OP_CEQ:
2351         case OP_IBEQ:
2352         case OP_ICEQ:
2353         case OP_LBEQ:
2354         case OP_LCEQ:
2355         case OP_FBEQ:
2356         case OP_FCEQ:
2357         case OP_COND_EXC_EQ:
2358         case OP_COND_EXC_IEQ:
2359         case OP_CMOV_IEQ:
2360         case OP_CMOV_LEQ:
2361                 return CMP_EQ;
2362         case OP_FCNEQ:
2363         case OP_ICNEQ:
2364         case OP_IBNE_UN:
2365         case OP_LBNE_UN:
2366         case OP_FBNE_UN:
2367         case OP_COND_EXC_NE_UN:
2368         case OP_COND_EXC_INE_UN:
2369         case OP_CMOV_INE_UN:
2370         case OP_CMOV_LNE_UN:
2371                 return CMP_NE;
2372         case OP_FCLE:
2373         case OP_ICLE:
2374         case OP_IBLE:
2375         case OP_LBLE:
2376         case OP_FBLE:
2377         case OP_CMOV_ILE:
2378         case OP_CMOV_LLE:
2379                 return CMP_LE;
2380         case OP_FCGE:
2381         case OP_ICGE:
2382         case OP_IBGE:
2383         case OP_LBGE:
2384         case OP_FBGE:
2385         case OP_CMOV_IGE:
2386         case OP_CMOV_LGE:
2387                 return CMP_GE;
2388         case OP_CLT:
2389         case OP_IBLT:
2390         case OP_ICLT:
2391         case OP_LBLT:
2392         case OP_LCLT:
2393         case OP_FBLT:
2394         case OP_FCLT:
2395         case OP_COND_EXC_LT:
2396         case OP_COND_EXC_ILT:
2397         case OP_CMOV_ILT:
2398         case OP_CMOV_LLT:
2399                 return CMP_LT;
2400         case OP_CGT:
2401         case OP_IBGT:
2402         case OP_ICGT:
2403         case OP_LBGT:
2404         case OP_LCGT:
2405         case OP_FBGT:
2406         case OP_FCGT:
2407         case OP_COND_EXC_GT:
2408         case OP_COND_EXC_IGT:
2409         case OP_CMOV_IGT:
2410         case OP_CMOV_LGT:
2411                 return CMP_GT;
2412
2413         case OP_ICLE_UN:
2414         case OP_IBLE_UN:
2415         case OP_LBLE_UN:
2416         case OP_FBLE_UN:
2417         case OP_COND_EXC_LE_UN:
2418         case OP_COND_EXC_ILE_UN:
2419         case OP_CMOV_ILE_UN:
2420         case OP_CMOV_LLE_UN:
2421                 return CMP_LE_UN;
2422
2423         case OP_ICGE_UN:
2424         case OP_IBGE_UN:
2425         case OP_LBGE_UN:
2426         case OP_FBGE_UN:
2427         case OP_CMOV_IGE_UN:
2428         case OP_CMOV_LGE_UN:
2429                 return CMP_GE_UN;
2430         case OP_CLT_UN:
2431         case OP_IBLT_UN:
2432         case OP_ICLT_UN:
2433         case OP_LBLT_UN:
2434         case OP_LCLT_UN:
2435         case OP_FBLT_UN:
2436         case OP_FCLT_UN:
2437         case OP_COND_EXC_LT_UN:
2438         case OP_COND_EXC_ILT_UN:
2439         case OP_CMOV_ILT_UN:
2440         case OP_CMOV_LLT_UN:
2441                 return CMP_LT_UN;
2442         case OP_CGT_UN:
2443         case OP_IBGT_UN:
2444         case OP_ICGT_UN:
2445         case OP_LBGT_UN:
2446         case OP_LCGT_UN:
2447         case OP_FCGT_UN:
2448         case OP_FBGT_UN:
2449         case OP_COND_EXC_GT_UN:
2450         case OP_COND_EXC_IGT_UN:
2451         case OP_CMOV_IGT_UN:
2452         case OP_CMOV_LGT_UN:
2453                 return CMP_GT_UN;
2454         default:
2455                 printf ("%s\n", mono_inst_name (opcode));
2456                 g_assert_not_reached ();
2457                 return 0;
2458         }
2459 }
2460
2461 CompRelation
2462 mono_negate_cond (CompRelation cond)
2463 {
2464         switch (cond) {
2465         case CMP_EQ:
2466                 return CMP_NE;
2467         case CMP_NE:
2468                 return CMP_EQ;
2469         case CMP_LE:
2470                 return CMP_GT;
2471         case CMP_GE:
2472                 return CMP_LT;
2473         case CMP_LT:
2474                 return CMP_GE;
2475         case CMP_GT:
2476                 return CMP_LE;
2477         case CMP_LE_UN:
2478                 return CMP_GT_UN;
2479         case CMP_GE_UN:
2480                 return CMP_LT_UN;
2481         case CMP_LT_UN:
2482                 return CMP_GE_UN;
2483         case CMP_GT_UN:
2484                 return CMP_LE_UN;
2485         default:
2486                 g_assert_not_reached ();
2487         }
2488 }
2489
2490 CompType
2491 mono_opcode_to_type (int opcode, int cmp_opcode)
2492 {
2493         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2494                 return CMP_TYPE_L;
2495         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2496                 return CMP_TYPE_I;
2497         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2498                 return CMP_TYPE_I;
2499         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2500                 return CMP_TYPE_L;
2501         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2502                 return CMP_TYPE_L;
2503         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2504                 return CMP_TYPE_F;
2505         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2506                 return CMP_TYPE_F;
2507         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2508                 return CMP_TYPE_I;
2509         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2510                 switch (cmp_opcode) {
2511                 case OP_ICOMPARE:
2512                 case OP_ICOMPARE_IMM:
2513                         return CMP_TYPE_I;
2514                 default:
2515                         return CMP_TYPE_L;
2516                 }
2517         } else {
2518                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2519                 return 0;
2520         }
2521 }
2522
2523 #endif /* DISABLE_JIT */
2524
2525 gboolean
2526 mono_is_regsize_var (MonoType *t)
2527 {
2528         if (t->byref)
2529                 return TRUE;
2530         t = mono_type_get_underlying_type (t);
2531         switch (t->type) {
2532         case MONO_TYPE_BOOLEAN:
2533         case MONO_TYPE_CHAR:
2534         case MONO_TYPE_I1:
2535         case MONO_TYPE_U1:
2536         case MONO_TYPE_I2:
2537         case MONO_TYPE_U2:
2538         case MONO_TYPE_I4:
2539         case MONO_TYPE_U4:
2540         case MONO_TYPE_I:
2541         case MONO_TYPE_U:
2542         case MONO_TYPE_PTR:
2543         case MONO_TYPE_FNPTR:
2544 #if SIZEOF_REGISTER == 8
2545         case MONO_TYPE_I8:
2546         case MONO_TYPE_U8:
2547 #endif
2548                 return TRUE;
2549         case MONO_TYPE_OBJECT:
2550         case MONO_TYPE_STRING:
2551         case MONO_TYPE_CLASS:
2552         case MONO_TYPE_SZARRAY:
2553         case MONO_TYPE_ARRAY:
2554                 return TRUE;
2555         case MONO_TYPE_GENERICINST:
2556                 if (!mono_type_generic_inst_is_valuetype (t))
2557                         return TRUE;
2558                 return FALSE;
2559         case MONO_TYPE_VALUETYPE:
2560                 return FALSE;
2561         default:
2562                 return FALSE;
2563         }
2564 }
2565
2566 #ifndef DISABLE_JIT
2567
2568 /*
2569  * mono_peephole_ins:
2570  *
2571  *   Perform some architecture independent peephole optimizations.
2572  */
2573 void
2574 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2575 {
2576         MonoInst *last_ins = ins->prev;
2577
2578         switch (ins->opcode) {
2579         case OP_MUL_IMM:
2580                 /* remove unnecessary multiplication with 1 */
2581                 if (ins->inst_imm == 1) {
2582                         if (ins->dreg != ins->sreg1)
2583                                 ins->opcode = OP_MOVE;
2584                         else
2585                                 MONO_DELETE_INS (bb, ins);
2586                 }
2587                 break;
2588         case OP_LOAD_MEMBASE:
2589         case OP_LOADI4_MEMBASE:
2590                 /*
2591                  * Note: if reg1 = reg2 the load op is removed
2592                  *
2593                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2594                  * OP_LOAD_MEMBASE offset(basereg), reg2
2595                  * -->
2596                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2597                  * OP_MOVE reg1, reg2
2598                  */
2599                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2600                         last_ins = last_ins->prev;
2601                 if (last_ins &&
2602                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2603                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2604                         ins->inst_basereg == last_ins->inst_destbasereg &&
2605                         ins->inst_offset == last_ins->inst_offset) {
2606                         if (ins->dreg == last_ins->sreg1) {
2607                                 MONO_DELETE_INS (bb, ins);
2608                                 break;
2609                         } else {
2610                                 ins->opcode = OP_MOVE;
2611                                 ins->sreg1 = last_ins->sreg1;
2612                         }
2613
2614                         /*
2615                          * Note: reg1 must be different from the basereg in the second load
2616                          * Note: if reg1 = reg2 is equal then second load is removed
2617                          *
2618                          * OP_LOAD_MEMBASE offset(basereg), reg1
2619                          * OP_LOAD_MEMBASE offset(basereg), reg2
2620                          * -->
2621                          * OP_LOAD_MEMBASE offset(basereg), reg1
2622                          * OP_MOVE reg1, reg2
2623                          */
2624                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2625                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2626                           ins->inst_basereg != last_ins->dreg &&
2627                           ins->inst_basereg == last_ins->inst_basereg &&
2628                           ins->inst_offset == last_ins->inst_offset) {
2629
2630                         if (ins->dreg == last_ins->dreg) {
2631                                 MONO_DELETE_INS (bb, ins);
2632                         } else {
2633                                 ins->opcode = OP_MOVE;
2634                                 ins->sreg1 = last_ins->dreg;
2635                         }
2636
2637                         //g_assert_not_reached ();
2638
2639 #if 0
2640                         /*
2641                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2642                          * OP_LOAD_MEMBASE offset(basereg), reg
2643                          * -->
2644                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2645                          * OP_ICONST reg, imm
2646                          */
2647                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2648                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2649                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2650                                    ins->inst_offset == last_ins->inst_offset) {
2651                         ins->opcode = OP_ICONST;
2652                         ins->inst_c0 = last_ins->inst_imm;
2653                         g_assert_not_reached (); // check this rule
2654 #endif
2655                 }
2656                 break;
2657         case OP_LOADI1_MEMBASE:
2658         case OP_LOADU1_MEMBASE:
2659                 /*
2660                  * Note: if reg1 = reg2 the load op is removed
2661                  *
2662                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2663                  * OP_LOAD_MEMBASE offset(basereg), reg2
2664                  * -->
2665                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2666                  * OP_MOVE reg1, reg2
2667                  */
2668                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2669                         ins->inst_basereg == last_ins->inst_destbasereg &&
2670                         ins->inst_offset == last_ins->inst_offset) {
2671                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2672                         ins->sreg1 = last_ins->sreg1;
2673                 }
2674                 break;
2675         case OP_LOADI2_MEMBASE:
2676         case OP_LOADU2_MEMBASE:
2677                 /*
2678                  * Note: if reg1 = reg2 the load op is removed
2679                  *
2680                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2681                  * OP_LOAD_MEMBASE offset(basereg), reg2
2682                  * -->
2683                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2684                  * OP_MOVE reg1, reg2
2685                  */
2686                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2687                         ins->inst_basereg == last_ins->inst_destbasereg &&
2688                         ins->inst_offset == last_ins->inst_offset) {
2689 #if SIZEOF_REGISTER == 8
2690                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2691 #else
2692                         /* The definition of OP_PCONV_TO_U2 is wrong */
2693                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2694 #endif
2695                         ins->sreg1 = last_ins->sreg1;
2696                 }
2697                 break;
2698         case OP_MOVE:
2699         case OP_FMOVE:
2700                 /*
2701                  * Removes:
2702                  *
2703                  * OP_MOVE reg, reg
2704                  */
2705                 if (ins->dreg == ins->sreg1) {
2706                         MONO_DELETE_INS (bb, ins);
2707                         break;
2708                 }
2709                 /*
2710                  * Removes:
2711                  *
2712                  * OP_MOVE sreg, dreg
2713                  * OP_MOVE dreg, sreg
2714                  */
2715                 if (last_ins && last_ins->opcode == ins->opcode &&
2716                         ins->sreg1 == last_ins->dreg &&
2717                         ins->dreg == last_ins->sreg1) {
2718                         MONO_DELETE_INS (bb, ins);
2719                 }
2720                 break;
2721         case OP_NOP:
2722                 MONO_DELETE_INS (bb, ins);
2723                 break;
2724         }
2725 }
2726
2727 int
2728 mini_exception_id_by_name (const char *name)
2729 {
2730         if (strcmp (name, "IndexOutOfRangeException") == 0)
2731                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2732         if (strcmp (name, "OverflowException") == 0)
2733                 return MONO_EXC_OVERFLOW;
2734         if (strcmp (name, "ArithmeticException") == 0)
2735                 return MONO_EXC_ARITHMETIC;
2736         if (strcmp (name, "DivideByZeroException") == 0)
2737                 return MONO_EXC_DIVIDE_BY_ZERO;
2738         if (strcmp (name, "InvalidCastException") == 0)
2739                 return MONO_EXC_INVALID_CAST;
2740         if (strcmp (name, "NullReferenceException") == 0)
2741                 return MONO_EXC_NULL_REF;
2742         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2743                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2744         if (strcmp (name, "ArgumentException") == 0)
2745                 return MONO_EXC_ARGUMENT;
2746         g_error ("Unknown intrinsic exception %s\n", name);
2747         return -1;
2748 }
2749
2750 #endif /* DISABLE_JIT */