mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413
 414 static const char*
 415 info_type_to_str (MonoRgctxInfoType type)
 416 {
 417         switch (type) {
 418         case MONO_RGCTX_INFO_STATIC_DATA: return "STATIC_DATA";
 419         case MONO_RGCTX_INFO_KLASS: return "KLASS";
 420         case MONO_RGCTX_INFO_VTABLE: return "VTABLE";
 421         case MONO_RGCTX_INFO_TYPE: return "TYPE";
 422         case MONO_RGCTX_INFO_REFLECTION_TYPE: return "REFLECTION_TYPE";
 423         case MONO_RGCTX_INFO_METHOD: return "METHOD";
 424         case MONO_RGCTX_INFO_GENERIC_METHOD_CODE: return "GENERIC_METHOD_CODE";
 425         case MONO_RGCTX_INFO_CLASS_FIELD: return "CLASS_FIELD";
 426         case MONO_RGCTX_INFO_METHOD_RGCTX: return "METHOD_RGCTX";
 427         case MONO_RGCTX_INFO_METHOD_CONTEXT: return "METHOD_CONTEXT";
 428         case MONO_RGCTX_INFO_REMOTING_INVOKE_WITH_CHECK: return "REMOTING_INVOKE_WITH_CHECK";
 429         case MONO_RGCTX_INFO_METHOD_DELEGATE_CODE: return "METHOD_DELEGATE_CODE";
 430         case MONO_RGCTX_INFO_CAST_CACHE: return "CAST_CACHE";
 431         default:
 432                 return "<UNKNOWN RGCTX INFO TYPE>";
 433         }
 434 }
 435
 436 static void
 437 print_ji (MonoJumpInfo *ji)
 438 {
 439         switch (ji->type) {
 440         case MONO_PATCH_INFO_RGCTX_FETCH: {
 441                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 442
 443                 printf ("[RGCTX_FETCH ");
 444                 print_ji (entry->data);
 445                 printf (" - %s]", info_type_to_str (entry->info_type));
 446                 break;
 447         }
 448         case MONO_PATCH_INFO_METHODCONST: {
 449                 char *s = mono_method_full_name (ji->data.method, TRUE);
 450                 printf ("[METHODCONST - %s]", s);
 451                 g_free (s);
 452                 break;
 453         }
 454         default:
 455                 printf ("[%d]", ji->type);
 456                 break;
 457         }
 458 }
 459
 460 void
 461 mono_print_ins_index (int i, MonoInst *ins)
 462 {
 463         const char *spec = ins_get_spec (ins->opcode);
 464         int num_sregs, j;
 465         int sregs [MONO_MAX_SRC_REGS];
 466
 467         if (i != -1)
 468                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 469         else
 470                 printf (" %s", mono_inst_name (ins->opcode));
 471         if (spec == MONO_ARCH_CPU_SPEC) {
 472                 /* This is a lowered opcode */
 473                 if (ins->dreg != -1)
 474                         printf (" R%d <-", ins->dreg);
 475                 if (ins->sreg1 != -1)
 476                         printf (" R%d", ins->sreg1);
 477                 if (ins->sreg2 != -1)
 478                         printf (" R%d", ins->sreg2);
 479                 if (ins->sreg3 != -1)
 480                         printf (" R%d", ins->sreg3);
 481
 482                 switch (ins->opcode) {
 483                 case OP_LBNE_UN:
 484                 case OP_LBEQ:
 485                 case OP_LBLT:
 486                 case OP_LBLT_UN:
 487                 case OP_LBGT:
 488                 case OP_LBGT_UN:
 489                 case OP_LBGE:
 490                 case OP_LBGE_UN:
 491                 case OP_LBLE:
 492                 case OP_LBLE_UN:
 493                         if (!ins->inst_false_bb)
 494                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 495                         else
 496                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 497                         break;
 498                 case OP_PHI:
 499                 case OP_VPHI:
 500                 case OP_XPHI:
 501                 case OP_FPHI: {
 502                         int i;
 503                         printf (" [%d (", (int)ins->inst_c0);
 504                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 505                                 if (i)
 506                                         printf (", ");
 507                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 508                         }
 509                         printf (")]");
 510                         break;
 511                 }
 512                 case OP_LDADDR:
 513                 case OP_OUTARG_VTRETADDR:
 514                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 515                         break;
 516                 case OP_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583                 printf (" [%d]", (int)ins->inst_imm);
 584                 break;
 585         case OP_ADD_IMM:
 586         case OP_LADD_IMM:
 587                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 588                 break;
 589         case OP_I8CONST:
 590                 printf (" [%lld]", (long long)ins->inst_l);
 591                 break;
 592         case OP_R8CONST:
 593                 printf (" [%f]", *(double*)ins->inst_p0);
 594                 break;
 595         case OP_R4CONST:
 596                 printf (" [%f]", *(float*)ins->inst_p0);
 597                 break;
 598         case OP_CALL:
 599         case OP_CALL_MEMBASE:
 600         case OP_CALL_REG:
 601         case OP_FCALL:
 602         case OP_FCALLVIRT:
 603         case OP_LCALL:
 604         case OP_LCALLVIRT:
 605         case OP_VCALL:
 606         case OP_VCALLVIRT:
 607         case OP_VCALL_REG:
 608         case OP_VCALL_MEMBASE:
 609         case OP_VCALL2:
 610         case OP_VCALL2_REG:
 611         case OP_VCALL2_MEMBASE:
 612         case OP_VOIDCALL:
 613         case OP_VOIDCALL_MEMBASE:
 614         case OP_VOIDCALLVIRT:
 615         case OP_TAILCALL: {
 616                 MonoCallInst *call = (MonoCallInst*)ins;
 617                 GSList *list;
 618
 619                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 620                         /*
 621                          * These are lowered opcodes, but they are in the .md files since the old
 622                          * JIT passes them to backends.
 623                          */
 624                         if (ins->dreg != -1)
 625                                 printf (" R%d <-", ins->dreg);
 626                 }
 627
 628                 if (call->method) {
 629                         char *full_name = mono_method_full_name (call->method, TRUE);
 630                         printf (" [%s]", full_name);
 631                         g_free (full_name);
 632                 } else if (call->fptr_is_patch) {
 633                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 634
 635                         printf (" ");
 636                         print_ji (ji);
 637                 } else if (call->fptr) {
 638                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 639                         if (info)
 640                                 printf (" [%s]", info->name);
 641                 }
 642
 643                 list = call->out_ireg_args;
 644                 while (list) {
 645                         guint32 regpair;
 646                         int reg, hreg;
 647
 648                         regpair = (guint32)(gssize)(list->data);
 649                         hreg = regpair >> 24;
 650                         reg = regpair & 0xffffff;
 651
 652                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 653
 654                         list = g_slist_next (list);
 655                 }
 656                 break;
 657         }
 658         case OP_BR:
 659         case OP_CALL_HANDLER:
 660                 printf (" [B%d]", ins->inst_target_bb->block_num);
 661                 break;
 662         case OP_IBNE_UN:
 663         case OP_IBEQ:
 664         case OP_IBLT:
 665         case OP_IBLT_UN:
 666         case OP_IBGT:
 667         case OP_IBGT_UN:
 668         case OP_IBGE:
 669         case OP_IBGE_UN:
 670         case OP_IBLE:
 671         case OP_IBLE_UN:
 672         case OP_LBNE_UN:
 673         case OP_LBEQ:
 674         case OP_LBLT:
 675         case OP_LBLT_UN:
 676         case OP_LBGT:
 677         case OP_LBGT_UN:
 678         case OP_LBGE:
 679         case OP_LBGE_UN:
 680         case OP_LBLE:
 681         case OP_LBLE_UN:
 682                 if (!ins->inst_false_bb)
 683                         printf (" [B%d]", ins->inst_true_bb->block_num);
 684                 else
 685                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 686                 break;
 687         case OP_LIVERANGE_START:
 688         case OP_LIVERANGE_END:
 689         case OP_GC_LIVENESS_DEF:
 690         case OP_GC_LIVENESS_USE:
 691                 printf (" R%d", (int)ins->inst_c1);
 692                 break;
 693         case OP_SEQ_POINT:
 694                 printf (" il: %x", (int)ins->inst_imm);
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         if (spec [MONO_INST_CLOB])
 701                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 702         printf ("\n");
 703 }
 704
 705 static void
 706 print_regtrack (RegTrack *t, int num)
 707 {
 708         int i;
 709         char buf [32];
 710         const char *r;
 711
 712         for (i = 0; i < num; ++i) {
 713                 if (!t [i].born_in)
 714                         continue;
 715                 if (i >= MONO_MAX_IREGS) {
 716                         g_snprintf (buf, sizeof(buf), "R%d", i);
 717                         r = buf;
 718                 } else
 719                         r = mono_arch_regname (i);
 720                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 721         }
 722 }
 723 #else
 724 void
 725 mono_print_ins_index (int i, MonoInst *ins)
 726 {
 727 }
 728 #endif /* DISABLE_LOGGING */
 729
 730 void
 731 mono_print_ins (MonoInst *ins)
 732 {
 733         mono_print_ins_index (-1, ins);
 734 }
 735
 736 static inline void
 737 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 738 {
 739         /*
 740          * If this function is called multiple times, the new instructions are inserted
 741          * in the proper order.
 742          */
 743         mono_bblock_insert_before_ins (bb, ins, to_insert);
 744 }
 745
 746 static inline void
 747 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 748 {
 749         /*
 750          * If this function is called multiple times, the new instructions are inserted in
 751          * proper order.
 752          */
 753         mono_bblock_insert_after_ins (bb, *last, to_insert);
 754
 755         *last = to_insert;
 756 }
 757
 758 static inline int
 759 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 760 {
 761         if (vreg_is_ref (cfg, reg))
 762                 return MONO_REG_INT_REF;
 763         else if (vreg_is_mp (cfg, reg))
 764                 return MONO_REG_INT_MP;
 765         else
 766                 return bank;
 767 }
 768
 769 /*
 770  * Force the spilling of the variable in the symbolic register 'reg', and free
 771  * the hreg it was assigned to.
 772  */
 773 static void
 774 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 775 {
 776         MonoInst *load;
 777         int i, sel, spill;
 778         int *symbolic;
 779         MonoRegState *rs = cfg->rs;
 780
 781         symbolic = rs->symbolic [bank];
 782         sel = rs->vassign [reg];
 783
 784         /* the vreg we need to spill lives in another logical reg bank */
 785         bank = translate_bank (cfg->rs, bank, sel);
 786
 787         /*i = rs->isymbolic [sel];
 788         g_assert (i == reg);*/
 789         i = reg;
 790         spill = ++cfg->spill_count;
 791         rs->vassign [i] = -spill - 1;
 792         if (G_UNLIKELY (bank))
 793                 mono_regstate_free_general (rs, sel, bank);
 794         else
 795                 mono_regstate_free_int (rs, sel);
 796         /* we need to create a spill var and insert a load to sel after the current instruction */
 797         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 798         load->dreg = sel;
 799         load->inst_basereg = cfg->frame_reg;
 800         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 801         insert_after_ins (bb, ins, last, load);
 802         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 803         if (G_UNLIKELY (bank))
 804                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 805         else
 806                 i = mono_regstate_alloc_int (rs, regmask (sel));
 807         g_assert (i == sel);
 808
 809         if (G_UNLIKELY (bank))
 810                 mono_regstate_free_general (rs, sel, bank);
 811         else
 812                 mono_regstate_free_int (rs, sel);
 813 }
 814
 815 /* This isn't defined on older glib versions and on some platforms */
 816 #ifndef G_GUINT64_FORMAT
 817 #define G_GUINT64_FORMAT "ul"
 818 #endif
 819
 820 static int
 821 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 822 {
 823         MonoInst *load;
 824         int i, sel, spill, num_sregs;
 825         int sregs [MONO_MAX_SRC_REGS];
 826         int *symbolic;
 827         MonoRegState *rs = cfg->rs;
 828
 829         symbolic = rs->symbolic [bank];
 830
 831         g_assert (bank < MONO_NUM_REGBANKS);
 832
 833         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 834         /* exclude the registers in the current instruction */
 835         num_sregs = mono_inst_get_src_registers (ins, sregs);
 836         for (i = 0; i < num_sregs; ++i) {
 837                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 838                         if (is_soft_reg (sregs [i], bank))
 839                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 840                         else
 841                                 regmask &= ~ (regmask (sregs [i]));
 842                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 843                 }
 844         }
 845         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 846                 regmask &= ~ (regmask (ins->dreg));
 847                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 848         }
 849
 850         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 851         g_assert (regmask); /* need at least a register we can free */
 852         sel = 0;
 853         /* we should track prev_use and spill the register that's farther */
 854         if (G_UNLIKELY (bank)) {
 855                 for (i = 0; i < regbank_size [bank]; ++i) {
 856                         if (regmask & (regmask (i))) {
 857                                 sel = i;
 858
 859                                 /* the vreg we need to load lives in another logical bank */
 860                                 bank = translate_bank (cfg->rs, bank, sel);
 861
 862                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 863                                 break;
 864                         }
 865                 }
 866
 867                 i = rs->symbolic [bank] [sel];
 868                 spill = ++cfg->spill_count;
 869                 rs->vassign [i] = -spill - 1;
 870                 mono_regstate_free_general (rs, sel, bank);
 871         }
 872         else {
 873                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 874                         if (regmask & (regmask (i))) {
 875                                 sel = i;
 876                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 877                                 break;
 878                         }
 879                 }
 880
 881                 i = rs->isymbolic [sel];
 882                 spill = ++cfg->spill_count;
 883                 rs->vassign [i] = -spill - 1;
 884                 mono_regstate_free_int (rs, sel);
 885         }
 886
 887         /* we need to create a spill var and insert a load to sel after the current instruction */
 888         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 889         load->dreg = sel;
 890         load->inst_basereg = cfg->frame_reg;
 891         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 892         insert_after_ins (bb, ins, last, load);
 893         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 894         if (G_UNLIKELY (bank))
 895                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 896         else
 897                 i = mono_regstate_alloc_int (rs, regmask (sel));
 898         g_assert (i == sel);
 899
 900         return sel;
 901 }
 902
 903 /*
 904  * free_up_hreg:
 905  *
 906  *   Free up the hreg HREG by spilling the vreg allocated to it.
 907  */
 908 static void
 909 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 910 {
 911         if (G_UNLIKELY (bank)) {
 912                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 913                         bank = translate_bank (cfg->rs, bank, hreg);
 914                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 915                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 916                 }
 917         }
 918         else {
 919                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 920                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 921                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 922                 }
 923         }
 924 }
 925
 926 static MonoInst*
 927 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 928 {
 929         MonoInst *copy;
 930
 931         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 932
 933         copy->dreg = dest;
 934         copy->sreg1 = src;
 935         copy->cil_code = ip;
 936         if (ins) {
 937                 mono_bblock_insert_after_ins (bb, ins, copy);
 938                 *last = copy;
 939         }
 940         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 941         return copy;
 942 }
 943
 944 static inline const char*
 945 regbank_to_string (int bank)
 946 {
 947         if (bank == MONO_REG_INT_REF)
 948                 return "REF ";
 949         else if (bank == MONO_REG_INT_MP)
 950                 return "MP ";
 951         else
 952                 return "";
 953 }
 954
 955 static void
 956 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 957 {
 958         MonoInst *store, *def;
 959
 960         bank = get_vreg_bank (cfg, prev_reg, bank);
 961
 962         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 963         store->sreg1 = reg;
 964         store->inst_destbasereg = cfg->frame_reg;
 965         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 966         if (ins) {
 967                 mono_bblock_insert_after_ins (bb, ins, store);
 968                 *last = store;
 969         } else if (insert_before) {
 970                 insert_before_ins (bb, insert_before, store);
 971         } else {
 972                 g_assert_not_reached ();
 973         }
 974         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 975
 976         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 977                 g_assert (prev_reg != -1);
 978                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 979                 def->inst_c0 = spill;
 980                 def->inst_c1 = bank;
 981                 mono_bblock_insert_after_ins (bb, store, def);
 982         }
 983 }
 984
 985 /* flags used in reginfo->flags */
 986 enum {
 987         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 988         MONO_FP_NEEDS_SPILL                     = regmask (1),
 989         MONO_FP_NEEDS_LOAD                      = regmask (2)
 990 };
 991
 992 static inline int
 993 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 994 {
 995         int val;
 996
 997         if (info && info->preferred_mask) {
 998                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 999                 if (val >= 0) {
1000                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1001                         return val;
1002                 }
1003         }
1004
1005         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1006         if (val < 0)
1007                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1008
1009         return val;
1010 }
1011
1012 static inline int
1013 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1014 {
1015         int val;
1016
1017         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1018
1019         if (val < 0)
1020                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1021
1022         return val;
1023 }
1024
1025 static inline int
1026 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1027 {
1028         if (G_UNLIKELY (bank))
1029                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1030         else
1031                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1032 }
1033
1034 static inline void
1035 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1036 {
1037         if (G_UNLIKELY (bank)) {
1038                 int mirrored_bank;
1039
1040                 g_assert (reg >= regbank_size [bank]);
1041                 g_assert (hreg < regbank_size [bank]);
1042                 g_assert (! is_global_freg (hreg));
1043
1044                 rs->vassign [reg] = hreg;
1045                 rs->symbolic [bank] [hreg] = reg;
1046                 rs->free_mask [bank] &= ~ (regmask (hreg));
1047
1048                 mirrored_bank = get_mirrored_bank (bank);
1049                 if (mirrored_bank == -1)
1050                         return;
1051
1052                 /* Make sure the other logical reg bank that this bank shares
1053                  * a single hard reg bank knows that this hard reg is not free.
1054                  */
1055                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1056
1057                 /* Mark the other logical bank that the this bank shares
1058                  * a single hard reg bank with as mirrored.
1059                  */
1060                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1061
1062         }
1063         else {
1064                 g_assert (reg >= MONO_MAX_IREGS);
1065                 g_assert (hreg < MONO_MAX_IREGS);
1066 #ifndef TARGET_ARM
1067                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1068                 g_assert (! is_global_ireg (hreg));
1069 #endif
1070
1071                 rs->vassign [reg] = hreg;
1072                 rs->isymbolic [hreg] = reg;
1073                 rs->ifree_mask &= ~ (regmask (hreg));
1074         }
1075 }
1076
1077 static inline regmask_t
1078 get_callee_mask (const char spec)
1079 {
1080         if (G_UNLIKELY (reg_bank (spec)))
1081                 return regbank_callee_regs [reg_bank (spec)];
1082         return MONO_ARCH_CALLEE_REGS;
1083 }
1084
1085 static gint8 desc_to_fixed_reg [256];
1086 static gboolean desc_to_fixed_reg_inited = FALSE;
1087
1088 #ifndef DISABLE_JIT
1089
1090 /*
1091  * Local register allocation.
1092  * We first scan the list of instructions and we save the liveness info of
1093  * each register (when the register is first used, when it's value is set etc.).
1094  * We also reverse the list of instructions because assigning registers backwards allows
1095  * for more tricks to be used.
1096  */
1097 void
1098 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1099 {
1100         MonoInst *ins, *prev, *last;
1101         MonoInst **tmp;
1102         MonoRegState *rs = cfg->rs;
1103         int i, j, val, max;
1104         RegTrack *reginfo;
1105         const char *spec;
1106         unsigned char spec_src1, spec_dest;
1107         int bank = 0;
1108 #if MONO_ARCH_USE_FPSTACK
1109         gboolean has_fp = FALSE;
1110         int fpstack [8];
1111         int sp = 0;
1112 #endif
1113         int num_sregs = 0;
1114         int sregs [MONO_MAX_SRC_REGS];
1115
1116         if (!bb->code)
1117                 return;
1118
1119         if (!desc_to_fixed_reg_inited) {
1120                 for (i = 0; i < 256; ++i)
1121                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1122                 desc_to_fixed_reg_inited = TRUE;
1123
1124                 /* Validate the cpu description against the info in mini-ops.h */
1125 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1126                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1127                         const char *ispec;
1128
1129                         spec = ins_get_spec (i);
1130                         ispec = INS_INFO (i);
1131
1132                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1133                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1134                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1135                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1136                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1137                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1138                 }
1139 #endif
1140         }
1141
1142         rs->next_vreg = bb->max_vreg;
1143         mono_regstate_assign (rs);
1144
1145         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1146         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1147                 rs->free_mask [i] = regbank_callee_regs [i];
1148
1149         max = rs->next_vreg;
1150
1151         if (cfg->reginfo && cfg->reginfo_len < max)
1152                 cfg->reginfo = NULL;
1153
1154         reginfo = cfg->reginfo;
1155         if (!reginfo) {
1156                 cfg->reginfo_len = MAX (1024, max * 2);
1157                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1158         }
1159         else
1160                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1161
1162         if (cfg->verbose_level > 1) {
1163                 /* print_regtrack reads the info of all variables */
1164                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1165         }
1166
1167         /*
1168          * For large methods, next_vreg can be very large, so g_malloc0 time can
1169          * be prohibitive. So we manually init the reginfo entries used by the
1170          * bblock.
1171          */
1172         for (ins = bb->code; ins; ins = ins->next) {
1173                 spec = ins_get_spec (ins->opcode);
1174
1175                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1176                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1177 #if SIZEOF_REGISTER == 4
1178                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1179                                 /**
1180                                  * In the new IR, the two vregs of the regpair do not alias the
1181                                  * original long vreg. shift the vreg here so the rest of the
1182                                  * allocator doesn't have to care about it.
1183                                  */
1184                                 ins->dreg ++;
1185                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1186                         }
1187 #endif
1188                 }
1189
1190                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1191                 for (j = 0; j < num_sregs; ++j) {
1192                         g_assert (sregs [j] != -1);
1193                         if (sregs [j] < max) {
1194                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1195 #if SIZEOF_REGISTER == 4
1196                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1197                                         sregs [j]++;
1198                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1199                                 }
1200 #endif
1201                         }
1202                 }
1203                 mono_inst_set_src_registers (ins, sregs);
1204         }
1205
1206         /*if (cfg->opt & MONO_OPT_COPYPROP)
1207                 local_copy_prop (cfg, ins);*/
1208
1209         i = 1;
1210         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1211         /* forward pass on the instructions to collect register liveness info */
1212         MONO_BB_FOR_EACH_INS (bb, ins) {
1213                 spec = ins_get_spec (ins->opcode);
1214                 spec_dest = spec [MONO_INST_DEST];
1215
1216                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1217                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1218                 }
1219
1220                 DEBUG (mono_print_ins_index (i, ins));
1221
1222                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1223
1224 #if MONO_ARCH_USE_FPSTACK
1225                 if (dreg_is_fp (spec)) {
1226                         has_fp = TRUE;
1227                 } else {
1228                         for (j = 0; j < num_sregs; ++j) {
1229                                 if (sreg_is_fp (j, spec))
1230                                         has_fp = TRUE;
1231                         }
1232                 }
1233 #endif
1234
1235                 for (j = 0; j < num_sregs; ++j) {
1236                         int sreg = sregs [j];
1237                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1238                         if (sreg_spec) {
1239                                 bank = sreg_bank (j, spec);
1240                                 g_assert (sreg != -1);
1241                                 if (is_soft_reg (sreg, bank))
1242                                         /* This means the vreg is not local to this bb */
1243                                         g_assert (reginfo [sreg].born_in > 0);
1244                                 rs->vassign [sreg] = -1;
1245                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1246                                 //reginfo [ins->sreg2].last_use = i;
1247                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1248                                         /* The virtual register is allocated sequentially */
1249                                         rs->vassign [sreg + 1] = -1;
1250                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1251                                         //reginfo [ins->sreg2 + 1].last_use = i;
1252                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1253                                                 reginfo [sreg + 1].born_in = i;
1254                                 }
1255                         } else {
1256                                 sregs [j] = -1;
1257                         }
1258                 }
1259                 mono_inst_set_src_registers (ins, sregs);
1260
1261                 if (spec_dest) {
1262                         int dest_dreg;
1263
1264                         bank = dreg_bank (spec);
1265                         if (spec_dest != 'b') /* it's not just a base register */
1266                                 reginfo [ins->dreg].killed_in = i;
1267                         g_assert (ins->dreg != -1);
1268                         rs->vassign [ins->dreg] = -1;
1269                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1270                         //reginfo [ins->dreg].last_use = i;
1271                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1272                                 reginfo [ins->dreg].born_in = i;
1273
1274                         dest_dreg = desc_to_fixed_reg [spec_dest];
1275                         if (dest_dreg != -1)
1276                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1277
1278 #ifdef MONO_ARCH_INST_FIXED_MASK
1279                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1280 #endif
1281
1282                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1283                                 /* The virtual register is allocated sequentially */
1284                                 rs->vassign [ins->dreg + 1] = -1;
1285                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1286                                 //reginfo [ins->dreg + 1].last_use = i;
1287                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1288                                         reginfo [ins->dreg + 1].born_in = i;
1289                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1290                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1291                         }
1292                 } else {
1293                         ins->dreg = -1;
1294                 }
1295
1296                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1297                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1298
1299                         MonoCallInst *call = (MonoCallInst*)ins;
1300                         GSList *list;
1301
1302                         list = call->out_ireg_args;
1303                         if (list) {
1304                                 while (list) {
1305                                         guint32 regpair;
1306                                         int reg, hreg;
1307
1308                                         regpair = (guint32)(gssize)(list->data);
1309                                         hreg = regpair >> 24;
1310                                         reg = regpair & 0xffffff;
1311
1312                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1313                                         //reginfo [reg].last_use = i;
1314
1315                                         list = g_slist_next (list);
1316                                 }
1317                         }
1318
1319                         list = call->out_freg_args;
1320                         if (list) {
1321                                 while (list) {
1322                                         guint32 regpair;
1323                                         int reg, hreg;
1324
1325                                         regpair = (guint32)(gssize)(list->data);
1326                                         hreg = regpair >> 24;
1327                                         reg = regpair & 0xffffff;
1328
1329                                         list = g_slist_next (list);
1330                                 }
1331                         }
1332                 }
1333
1334                 ++i;
1335         }
1336
1337         tmp = &last;
1338
1339         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1340         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1341                 int prev_dreg, clob_dreg;
1342                 int dest_dreg, clob_reg;
1343                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1344                 int dreg_high, sreg1_high;
1345                 regmask_t dreg_mask, mask;
1346                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1347                 regmask_t dreg_fixed_mask;
1348                 const unsigned char *ip;
1349                 --i;
1350                 spec = ins_get_spec (ins->opcode);
1351                 spec_src1 = spec [MONO_INST_SRC1];
1352                 spec_dest = spec [MONO_INST_DEST];
1353                 prev_dreg = -1;
1354                 clob_dreg = -1;
1355                 clob_reg = -1;
1356                 dest_dreg = -1;
1357                 dreg_high = -1;
1358                 sreg1_high = -1;
1359                 dreg_mask = get_callee_mask (spec_dest);
1360                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1361                         prev_sregs [j] = -1;
1362                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1363                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1364 #ifdef MONO_ARCH_INST_FIXED_MASK
1365                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1366 #else
1367                         sreg_fixed_masks [j] = 0;
1368 #endif
1369                 }
1370
1371                 DEBUG (printf ("processing:"));
1372                 DEBUG (mono_print_ins_index (i, ins));
1373
1374                 ip = ins->cil_code;
1375
1376                 last = ins;
1377
1378                 /*
1379                  * FIXED REGS
1380                  */
1381                 dest_dreg = desc_to_fixed_reg [spec_dest];
1382                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1383                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1384
1385 #ifdef MONO_ARCH_INST_FIXED_MASK
1386                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1387 #else
1388                 dreg_fixed_mask = 0;
1389 #endif
1390
1391                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1392
1393                 /*
1394                  * TRACK FIXED SREG2, 3, ...
1395                  */
1396                 for (j = 1; j < num_sregs; ++j) {
1397                         int sreg = sregs [j];
1398                         int dest_sreg = dest_sregs [j];
1399
1400                         if (dest_sreg == -1)
1401                                 continue;
1402
1403                         if (j == 2) {
1404                                 int k;
1405
1406                                 /*
1407                                  * CAS.
1408                                  * We need to special case this, since on x86, there are only 3
1409                                  * free registers, and the code below assigns one of them to
1410                                  * sreg, so we can run out of registers when trying to assign
1411                                  * dreg. Instead, we just set up the register masks, and let the
1412                                  * normal sreg2 assignment code handle this. It would be nice to
1413                                  * do this for all the fixed reg cases too, but there is too much
1414                                  * risk of breakage.
1415                                  */
1416
1417                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1418                                 sreg_masks [j] = regmask (dest_sreg);
1419                                 for (k = 0; k < num_sregs; ++k) {
1420                                         if (k != j)
1421                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1422                                 }
1423
1424                                 /*
1425                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1426                                  */
1427                                 for (k = 0; k < num_sregs; ++k) {
1428                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1429                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1430                                 }
1431
1432                                 /*
1433                                  * We can also run out of registers while processing sreg2 if sreg3 is
1434                                  * assigned to another hreg, so spill sreg3 now.
1435                                  */
1436                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1437                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1438                                 }
1439                                 continue;
1440                         }
1441
1442                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1443                                 if (is_global_ireg (sreg)) {
1444                                         int k;
1445                                         /* Argument already in hard reg, need to copy */
1446                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1447                                         insert_before_ins (bb, ins, copy);
1448                                         for (k = 0; k < num_sregs; ++k) {
1449                                                 if (k != j)
1450                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1451                                         }
1452                                 } else {
1453                                         val = rs->vassign [sreg];
1454                                         if (val == -1) {
1455                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1456                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1457                                         } else if (val < -1) {
1458                                                 /* FIXME: */
1459                                                 g_assert_not_reached ();
1460                                         } else {
1461                                                 /* Argument already in hard reg, need to copy */
1462                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1463                                                 int k;
1464
1465                                                 insert_before_ins (bb, ins, copy);
1466                                                 for (k = 0; k < num_sregs; ++k) {
1467                                                         if (k != j)
1468                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1469                                                 }
1470                                                 /*
1471                                                  * Prevent the dreg from being allocate to dest_sreg
1472                                                  * too, since it could force sreg1 to be allocated to
1473                                                  * the same reg on x86.
1474                                                  */
1475                                                 dreg_mask &= ~ (regmask (dest_sreg));
1476                                         }
1477                                 }
1478                         } else {
1479                                 gboolean need_spill = TRUE;
1480                                 gboolean need_assign = TRUE;
1481                                 int k;
1482
1483                                 dreg_mask &= ~ (regmask (dest_sreg));
1484                                 for (k = 0; k < num_sregs; ++k) {
1485                                         if (k != j)
1486                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1487                                 }
1488
1489                                 /*
1490                                  * First check if dreg is assigned to dest_sreg2, since we
1491                                  * can't spill a dreg.
1492                                  */
1493                                 if (spec [MONO_INST_DEST])
1494                                         val = rs->vassign [ins->dreg];
1495                                 else
1496                                         val = -1;
1497                                 if (val == dest_sreg && ins->dreg != sreg) {
1498                                         /*
1499                                          * the destination register is already assigned to
1500                                          * dest_sreg2: we need to allocate another register for it
1501                                          * and then copy from this to dest_sreg2.
1502                                          */
1503                                         int new_dest;
1504                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1505                                         g_assert (new_dest >= 0);
1506                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1507
1508                                         prev_dreg = ins->dreg;
1509                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1510                                         clob_dreg = ins->dreg;
1511                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1512                                         mono_regstate_free_int (rs, dest_sreg);
1513                                         need_spill = FALSE;
1514                                 }
1515
1516                                 if (is_global_ireg (sreg)) {
1517                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1518                                         insert_before_ins (bb, ins, copy);
1519                                         need_assign = FALSE;
1520                                 }
1521                                 else {
1522                                         val = rs->vassign [sreg];
1523                                         if (val == dest_sreg) {
1524                                                 /* sreg2 is already assigned to the correct register */
1525                                                 need_spill = FALSE;
1526                                         } else if (val < -1) {
1527                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1528                                         } else if (val >= 0) {
1529                                                 /* sreg2 already assigned to another register */
1530                                                 /*
1531                                                  * We couldn't emit a copy from val to dest_sreg2, because
1532                                                  * val might be spilled later while processing this
1533                                                  * instruction. So we spill sreg2 so it can be allocated to
1534                                                  * dest_sreg2.
1535                                                  */
1536                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1537                                         }
1538                                 }
1539
1540                                 if (need_spill) {
1541                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1542                                 }
1543
1544                                 if (need_assign) {
1545                                         if (rs->vassign [sreg] < -1) {
1546                                                 int spill;
1547
1548                                                 /* Need to emit a spill store */
1549                                                 spill = - rs->vassign [sreg] - 1;
1550                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1551                                         }
1552                                         /* force-set sreg2 */
1553                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1554                                 }
1555                         }
1556                         sregs [j] = dest_sreg;
1557                 }
1558                 mono_inst_set_src_registers (ins, sregs);
1559
1560                 /*
1561                  * TRACK DREG
1562                  */
1563                 bank = dreg_bank (spec);
1564                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1565                         prev_dreg = ins->dreg;
1566                 }
1567
1568                 if (spec_dest == 'b') {
1569                         /*
1570                          * The dest reg is read by the instruction, not written, so
1571                          * avoid allocating sreg1/sreg2 to the same reg.
1572                          */
1573                         if (dest_sregs [0] != -1)
1574                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1575                         for (j = 1; j < num_sregs; ++j) {
1576                                 if (dest_sregs [j] != -1)
1577                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1578                         }
1579
1580                         val = rs->vassign [ins->dreg];
1581                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1582                                 /* DREG is already allocated to a register needed for sreg1 */
1583                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1584                         }
1585                 }
1586
1587                 /*
1588                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1589                  * various complex situations.
1590                  */
1591                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1592                         guint32 dreg2, dest_dreg2;
1593
1594                         g_assert (is_soft_reg (ins->dreg, bank));
1595
1596                         if (dest_dreg != -1) {
1597                                 if (rs->vassign [ins->dreg] != dest_dreg)
1598                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1599
1600                                 dreg2 = ins->dreg + 1;
1601                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1602                                 if (dest_dreg2 != -1) {
1603                                         if (rs->vassign [dreg2] != dest_dreg2)
1604                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1605                                 }
1606                         }
1607                 }
1608
1609                 if (dreg_fixed_mask) {
1610                         g_assert (!bank);
1611                         if (is_global_ireg (ins->dreg)) {
1612                                 /*
1613                                  * The argument is already in a hard reg, but that reg is
1614                                  * not usable by this instruction, so allocate a new one.
1615                                  */
1616                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1617                                 if (val < 0)
1618                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1619                                 mono_regstate_free_int (rs, val);
1620                                 dest_dreg = val;
1621
1622                                 /* Fall through */
1623                         }
1624                         else
1625                                 dreg_mask &= dreg_fixed_mask;
1626                 }
1627
1628                 if (is_soft_reg (ins->dreg, bank)) {
1629                         val = rs->vassign [ins->dreg];
1630
1631                         if (val < 0) {
1632                                 int spill = 0;
1633                                 if (val < -1) {
1634                                         /* the register gets spilled after this inst */
1635                                         spill = -val -1;
1636                                 }
1637                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1638                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1639                                 if (spill)
1640                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1641                         }
1642
1643                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1644                         ins->dreg = val;
1645                 }
1646
1647                 /* Handle regpairs */
1648                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1649                         int reg2 = prev_dreg + 1;
1650
1651                         g_assert (!bank);
1652                         g_assert (prev_dreg > -1);
1653                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1654                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1655 #ifdef TARGET_X86
1656                         /* bug #80489 */
1657                         mask &= ~regmask (X86_ECX);
1658 #endif
1659                         val = rs->vassign [reg2];
1660                         if (val < 0) {
1661                                 int spill = 0;
1662                                 if (val < -1) {
1663                                         /* the register gets spilled after this inst */
1664                                         spill = -val -1;
1665                                 }
1666                                 val = mono_regstate_alloc_int (rs, mask);
1667                                 if (val < 0)
1668                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1669                                 if (spill)
1670                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1671                         }
1672                         else {
1673                                 if (! (mask & (regmask (val)))) {
1674                                         val = mono_regstate_alloc_int (rs, mask);
1675                                         if (val < 0)
1676                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1677
1678                                         /* Reallocate hreg to the correct register */
1679                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1680
1681                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1682                                 }
1683                         }
1684
1685                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1686                         assign_reg (cfg, rs, reg2, val, bank);
1687
1688                         dreg_high = val;
1689                         ins->backend.reg3 = val;
1690
1691                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1692                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1693                                 mono_regstate_free_int (rs, val);
1694                         }
1695                 }
1696
1697                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1698                         /*
1699                          * In theory, we could free up the hreg even if the vreg is alive,
1700                          * but branches inside bblocks force us to assign the same hreg
1701                          * to a vreg every time it is encountered.
1702                          */
1703                         int dreg = rs->vassign [prev_dreg];
1704                         g_assert (dreg >= 0);
1705                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1706                         if (G_UNLIKELY (bank))
1707                                 mono_regstate_free_general (rs, dreg, bank);
1708                         else
1709                                 mono_regstate_free_int (rs, dreg);
1710                         rs->vassign [prev_dreg] = -1;
1711                 }
1712
1713                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1714                         /* this instruction only outputs to dest_dreg, need to copy */
1715                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1716                         ins->dreg = dest_dreg;
1717
1718                         if (G_UNLIKELY (bank)) {
1719                                 /* the register we need to free up may be used in another logical regbank
1720                                  * so do a translate just in case.
1721                                  */
1722                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1723                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1724                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1725                         }
1726                         else {
1727                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1728                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1729                         }
1730                 }
1731
1732                 if (spec_dest == 'b') {
1733                         /*
1734                          * The dest reg is read by the instruction, not written, so
1735                          * avoid allocating sreg1/sreg2 to the same reg.
1736                          */
1737                         for (j = 0; j < num_sregs; ++j)
1738                                 if (!sreg_bank (j, spec))
1739                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1740                 }
1741
1742                 /*
1743                  * TRACK CLOBBERING
1744                  */
1745                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1746                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1747                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1748                 }
1749
1750                 if (spec [MONO_INST_CLOB] == 'c') {
1751                         int j, s, dreg, dreg2, cur_bank;
1752                         guint64 clob_mask;
1753
1754                         clob_mask = MONO_ARCH_CALLEE_REGS;
1755
1756                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1757                                 /*
1758                                  * Need to avoid spilling the dreg since the dreg is not really
1759                                  * clobbered by the call.
1760                                  */
1761                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1762                                         dreg = rs->vassign [prev_dreg];
1763                                 else
1764                                         dreg = -1;
1765
1766                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1767                                         dreg2 = rs->vassign [prev_dreg + 1];
1768                                 else
1769                                         dreg2 = -1;
1770
1771                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1772                                         s = regmask (j);
1773                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1774                                                 if ((j != dreg) && (j != dreg2))
1775                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1776                                                 else if (rs->isymbolic [j])
1777                                                         /* The hreg is assigned to the dreg of this instruction */
1778                                                         rs->vassign [rs->isymbolic [j]] = -1;
1779                                                 mono_regstate_free_int (rs, j);
1780                                         }
1781                                 }
1782                         }
1783
1784                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1785                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1786                                         clob_mask = regbank_callee_regs [cur_bank];
1787                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1788                                                 dreg = rs->vassign [prev_dreg];
1789                                         else
1790                                                 dreg = -1;
1791
1792                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1793
1794                                                 /* we are looping though the banks in the outer loop
1795                                                  * so, we don't need to deal with mirrored hregs
1796                                                  * because we will get them in one of the other bank passes.
1797                                                  */
1798                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1799                                                         continue;
1800
1801                                                 s = regmask (j);
1802                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1803                                                         if (j != dreg)
1804                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1805                                                         else if (rs->symbolic [cur_bank] [j])
1806                                                                 /* The hreg is assigned to the dreg of this instruction */
1807                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1808                                                         mono_regstate_free_general (rs, j, cur_bank);
1809                                                 }
1810                                         }
1811                                 }
1812                         }
1813                 }
1814
1815                 /*
1816                  * TRACK ARGUMENT REGS
1817                  */
1818                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1819                         MonoCallInst *call = (MonoCallInst*)ins;
1820                         GSList *list;
1821
1822                         /*
1823                          * This needs to be done before assigning sreg1, so sreg1 will
1824                          * not be assigned one of the argument regs.
1825                          */
1826
1827                         /*
1828                          * Assign all registers in call->out_reg_args to the proper
1829                          * argument registers.
1830                          */
1831
1832                         list = call->out_ireg_args;
1833                         if (list) {
1834                                 while (list) {
1835                                         guint32 regpair;
1836                                         int reg, hreg;
1837
1838                                         regpair = (guint32)(gssize)(list->data);
1839                                         hreg = regpair >> 24;
1840                                         reg = regpair & 0xffffff;
1841
1842                                         assign_reg (cfg, rs, reg, hreg, 0);
1843
1844                                         sreg_masks [0] &= ~(regmask (hreg));
1845
1846                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1847
1848                                         list = g_slist_next (list);
1849                                 }
1850                         }
1851
1852                         list = call->out_freg_args;
1853                         if (list) {
1854                                 while (list) {
1855                                         guint32 regpair;
1856                                         int reg, hreg;
1857
1858                                         regpair = (guint32)(gssize)(list->data);
1859                                         hreg = regpair >> 24;
1860                                         reg = regpair & 0xffffff;
1861
1862                                         assign_reg (cfg, rs, reg, hreg, 1);
1863
1864                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1865
1866                                         list = g_slist_next (list);
1867                                 }
1868                         }
1869                 }
1870
1871                 /*
1872                  * TRACK SREG1
1873                  */
1874                 bank = sreg1_bank (spec);
1875                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1876                         int sreg1 = sregs [0];
1877                         int dest_sreg1 = dest_sregs [0];
1878
1879                         g_assert (is_soft_reg (sreg1, bank));
1880
1881                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1882                         if (dest_sreg1 != -1)
1883                                 g_assert (dest_sreg1 == ins->dreg);
1884                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1885                         g_assert (val >= 0);
1886
1887                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1888                                 // FIXME:
1889                                 g_assert_not_reached ();
1890
1891                         assign_reg (cfg, rs, sreg1, val, bank);
1892
1893                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1894
1895                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1896                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1897                         g_assert (val >= 0);
1898
1899                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1900                                 // FIXME:
1901                                 g_assert_not_reached ();
1902
1903                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1904
1905                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1906
1907                         /* Skip rest of this section */
1908                         dest_sregs [0] = -1;
1909                 }
1910
1911                 if (sreg_fixed_masks [0]) {
1912                         g_assert (!bank);
1913                         if (is_global_ireg (sregs [0])) {
1914                                 /*
1915                                  * The argument is already in a hard reg, but that reg is
1916                                  * not usable by this instruction, so allocate a new one.
1917                                  */
1918                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1919                                 if (val < 0)
1920                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1921                                 mono_regstate_free_int (rs, val);
1922                                 dest_sregs [0] = val;
1923
1924                                 /* Fall through to the dest_sreg1 != -1 case */
1925                         }
1926                         else
1927                                 sreg_masks [0] &= sreg_fixed_masks [0];
1928                 }
1929
1930                 if (dest_sregs [0] != -1) {
1931                         sreg_masks [0] = regmask (dest_sregs [0]);
1932
1933                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1934                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1935                         }
1936                         if (is_global_ireg (sregs [0])) {
1937                                 /* The argument is already in a hard reg, need to copy */
1938                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1939                                 insert_before_ins (bb, ins, copy);
1940                                 sregs [0] = dest_sregs [0];
1941                         }
1942                 }
1943
1944                 if (is_soft_reg (sregs [0], bank)) {
1945                         val = rs->vassign [sregs [0]];
1946                         prev_sregs [0] = sregs [0];
1947                         if (val < 0) {
1948                                 int spill = 0;
1949                                 if (val < -1) {
1950                                         /* the register gets spilled after this inst */
1951                                         spill = -val -1;
1952                                 }
1953
1954                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1955                                         /*
1956                                          * Allocate the same hreg to sreg1 as well so the
1957                                          * peephole can get rid of the move.
1958                                          */
1959                                         sreg_masks [0] = regmask (ins->dreg);
1960                                 }
1961
1962                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1963                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1964                                         sreg_masks [0] = regmask (ins->dreg);
1965
1966                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1967                                 assign_reg (cfg, rs, sregs [0], val, bank);
1968                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1969
1970                                 if (spill) {
1971                                         /*
1972                                          * Need to insert before the instruction since it can
1973                                          * overwrite sreg1.
1974                                          */
1975                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1976                                 }
1977                         }
1978                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1979                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1980                                 insert_before_ins (bb, ins, copy);
1981                                 for (j = 1; j < num_sregs; ++j)
1982                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1983                                 val = dest_sregs [0];
1984                         }
1985
1986                         sregs [0] = val;
1987                 }
1988                 else {
1989                         prev_sregs [0] = -1;
1990                 }
1991                 mono_inst_set_src_registers (ins, sregs);
1992
1993                 for (j = 1; j < num_sregs; ++j)
1994                         sreg_masks [j] &= ~(regmask (sregs [0]));
1995
1996                 /* Handle the case when sreg1 is a regpair but dreg is not */
1997                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1998                         int reg2 = prev_sregs [0] + 1;
1999
2000                         g_assert (!bank);
2001                         g_assert (prev_sregs [0] > -1);
2002                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2003                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2004                         val = rs->vassign [reg2];
2005                         if (val < 0) {
2006                                 int spill = 0;
2007                                 if (val < -1) {
2008                                         /* the register gets spilled after this inst */
2009                                         spill = -val -1;
2010                                 }
2011                                 val = mono_regstate_alloc_int (rs, mask);
2012                                 if (val < 0)
2013                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2014                                 if (spill)
2015                                         g_assert_not_reached ();
2016                         }
2017                         else {
2018                                 if (! (mask & (regmask (val)))) {
2019                                         /* The vreg is already allocated to a wrong hreg */
2020                                         /* FIXME: */
2021                                         g_assert_not_reached ();
2022 #if 0
2023                                         val = mono_regstate_alloc_int (rs, mask);
2024                                         if (val < 0)
2025                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2026
2027                                         /* Reallocate hreg to the correct register */
2028                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2029
2030                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2031 #endif
2032                                 }
2033                         }
2034
2035                         sreg1_high = val;
2036                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2037                         assign_reg (cfg, rs, reg2, val, bank);
2038                 }
2039
2040                 /* Handle dreg==sreg1 */
2041                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2042                         MonoInst *sreg2_copy = NULL;
2043                         MonoInst *copy;
2044                         int bank = reg_bank (spec_src1);
2045
2046                         if (ins->dreg == sregs [1]) {
2047                                 /*
2048                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2049                                  * register for it.
2050                                  */
2051                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2052
2053                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2054                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2055                                 prev_sregs [1] = sregs [1] = reg2;
2056
2057                                 if (G_UNLIKELY (bank))
2058                                         mono_regstate_free_general (rs, reg2, bank);
2059                                 else
2060                                         mono_regstate_free_int (rs, reg2);
2061                         }
2062
2063                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2064                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2065                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2066                                         /* FIXME: */
2067                                         g_assert_not_reached ();
2068
2069                                 /*
2070                                  * sreg1 and dest are already allocated to the same regpair by the
2071                                  * SREG1 allocation code.
2072                                  */
2073                                 g_assert (sregs [0] == ins->dreg);
2074                                 g_assert (dreg_high == sreg1_high);
2075                         }
2076
2077                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2078                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2079                         insert_before_ins (bb, ins, copy);
2080
2081                         if (sreg2_copy)
2082                                 insert_before_ins (bb, copy, sreg2_copy);
2083
2084                         /*
2085                          * Need to prevent sreg2 to be allocated to sreg1, since that
2086                          * would screw up the previous copy.
2087                          */
2088                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2089                         /* we set sreg1 to dest as well */
2090                         prev_sregs [0] = sregs [0] = ins->dreg;
2091                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2092                 }
2093                 mono_inst_set_src_registers (ins, sregs);
2094
2095                 /*
2096                  * TRACK SREG2, 3, ...
2097                  */
2098                 for (j = 1; j < num_sregs; ++j) {
2099                         int k;
2100
2101                         bank = sreg_bank (j, spec);
2102                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2103                                 g_assert_not_reached ();
2104
2105                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2106                                 /*
2107                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2108                                  * allocating it to the fixed reg.
2109                                  */
2110                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2111                                 insert_before_ins (bb, ins, copy);
2112                                 sregs [j] = dest_sregs [j];
2113                         } else if (is_soft_reg (sregs [j], bank)) {
2114                                 val = rs->vassign [sregs [j]];
2115
2116                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2117                                         /*
2118                                          * The sreg is already allocated to a hreg, but not to the fixed
2119                                          * reg required by the instruction. Spill the sreg, so it can be
2120                                          * allocated to the fixed reg by the code below.
2121                                          */
2122                                         /* Currently, this code should only be hit for CAS */
2123                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2124                                         val = rs->vassign [sregs [j]];
2125                                 }
2126
2127                                 if (val < 0) {
2128                                         int spill = 0;
2129                                         if (val < -1) {
2130                                                 /* the register gets spilled after this inst */
2131                                                 spill = -val -1;
2132                                         }
2133                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2134                                         assign_reg (cfg, rs, sregs [j], val, bank);
2135                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2136                                         if (spill) {
2137                                                 /*
2138                                                  * Need to insert before the instruction since it can
2139                                                  * overwrite sreg2.
2140                                                  */
2141                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2142                                         }
2143                                 }
2144                                 sregs [j] = val;
2145                                 for (k = j + 1; k < num_sregs; ++k)
2146                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2147                         }
2148                         else {
2149                                 prev_sregs [j] = -1;
2150                         }
2151                 }
2152                 mono_inst_set_src_registers (ins, sregs);
2153
2154                 /* Sanity check */
2155                 /* Do this only for CAS for now */
2156                 for (j = 1; j < num_sregs; ++j) {
2157                         int sreg = sregs [j];
2158                         int dest_sreg = dest_sregs [j];
2159
2160                         if (j == 2 && dest_sreg != -1) {
2161                                 int k;
2162
2163                                 g_assert (sreg == dest_sreg);
2164
2165                                 for (k = 0; k < num_sregs; ++k) {
2166                                         if (k != j)
2167                                                 g_assert (sregs [k] != dest_sreg);
2168                                 }
2169                         }
2170                 }
2171
2172                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2173                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2174                         mono_regstate_free_int (rs, ins->sreg1);
2175                 }
2176                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2177                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2178                         mono_regstate_free_int (rs, ins->sreg2);
2179                 }*/
2180
2181                 DEBUG (mono_print_ins_index (i, ins));
2182         }
2183
2184         // FIXME: Set MAX_FREGS to 8
2185         // FIXME: Optimize generated code
2186 #if MONO_ARCH_USE_FPSTACK
2187         /*
2188          * Make a forward pass over the code, simulating the fp stack, making sure the
2189          * arguments required by the fp opcodes are at the top of the stack.
2190          */
2191         if (has_fp) {
2192                 MonoInst *prev = NULL;
2193                 MonoInst *fxch;
2194                 int tmp;
2195
2196                 g_assert (num_sregs <= 2);
2197
2198                 for (ins = bb->code; ins; ins = ins->next) {
2199                         spec = ins_get_spec (ins->opcode);
2200
2201                         DEBUG (printf ("processing:"));
2202                         DEBUG (mono_print_ins_index (0, ins));
2203
2204                         if (ins->opcode == OP_FMOVE) {
2205                                 /* Do it by renaming the source to the destination on the stack */
2206                                 // FIXME: Is this correct ?
2207                                 for (i = 0; i < sp; ++i)
2208                                         if (fpstack [i] == ins->sreg1)
2209                                                 fpstack [i] = ins->dreg;
2210                                 prev = ins;
2211                                 continue;
2212                         }
2213
2214                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2215                                 /* Arg1 must be in %st(1) */
2216                                 g_assert (prev);
2217
2218                                 i = 0;
2219                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2220                                         i ++;
2221                                 g_assert (i < sp);
2222
2223                                 if (sp - 1 - i > 0) {
2224                                         /* First move it to %st(0) */
2225                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2226
2227                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2228                                         fxch->inst_imm = sp - 1 - i;
2229
2230                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2231                                         prev = fxch;
2232
2233                                         tmp = fpstack [sp - 1];
2234                                         fpstack [sp - 1] = fpstack [i];
2235                                         fpstack [i] = tmp;
2236                                 }
2237
2238                                 /* Then move it to %st(1) */
2239                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2240
2241                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2242                                 fxch->inst_imm = 1;
2243
2244                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2245                                 prev = fxch;
2246
2247                                 tmp = fpstack [sp - 1];
2248                                 fpstack [sp - 1] = fpstack [sp - 2];
2249                                 fpstack [sp - 2] = tmp;
2250                         }
2251
2252                         if (sreg2_is_fp (spec)) {
2253                                 g_assert (sp > 0);
2254
2255                                 if (fpstack [sp - 1] != ins->sreg2) {
2256                                         g_assert (prev);
2257
2258                                         i = 0;
2259                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2260                                                 i ++;
2261                                         g_assert (i < sp);
2262
2263                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2264
2265                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2266                                         fxch->inst_imm = sp - 1 - i;
2267
2268                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2269                                         prev = fxch;
2270
2271                                         tmp = fpstack [sp - 1];
2272                                         fpstack [sp - 1] = fpstack [i];
2273                                         fpstack [i] = tmp;
2274                                 }
2275
2276                                 sp --;
2277                         }
2278
2279                         if (sreg1_is_fp (spec)) {
2280                                 g_assert (sp > 0);
2281
2282                                 if (fpstack [sp - 1] != ins->sreg1) {
2283                                         g_assert (prev);
2284
2285                                         i = 0;
2286                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2287                                                 i ++;
2288                                         g_assert (i < sp);
2289
2290                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2291
2292                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2293                                         fxch->inst_imm = sp - 1 - i;
2294
2295                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2296                                         prev = fxch;
2297
2298                                         tmp = fpstack [sp - 1];
2299                                         fpstack [sp - 1] = fpstack [i];
2300                                         fpstack [i] = tmp;
2301                                 }
2302
2303                                 sp --;
2304                         }
2305
2306                         if (dreg_is_fp (spec)) {
2307                                 g_assert (sp < 8);
2308                                 fpstack [sp ++] = ins->dreg;
2309                         }
2310
2311                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2312                                 printf ("\t[");
2313                                 for (i = 0; i < sp; ++i)
2314                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2315                                 printf ("]\n");
2316                         }
2317
2318                         prev = ins;
2319                 }
2320
2321                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2322                         /* Remove remaining items from the fp stack */
2323                         /*
2324                          * These can remain for example as a result of a dead fmove like in
2325                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2326                          */
2327                         while (sp) {
2328                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2329                                 mono_add_ins_to_end (bb, ins);
2330                                 sp --;
2331                         }
2332                 }
2333         }
2334 #endif
2335 }
2336
2337 CompRelation
2338 mono_opcode_to_cond (int opcode)
2339 {
2340         switch (opcode) {
2341         case OP_CEQ:
2342         case OP_IBEQ:
2343         case OP_ICEQ:
2344         case OP_LBEQ:
2345         case OP_LCEQ:
2346         case OP_FBEQ:
2347         case OP_FCEQ:
2348         case OP_COND_EXC_EQ:
2349         case OP_COND_EXC_IEQ:
2350         case OP_CMOV_IEQ:
2351         case OP_CMOV_LEQ:
2352                 return CMP_EQ;
2353         case OP_IBNE_UN:
2354         case OP_LBNE_UN:
2355         case OP_FBNE_UN:
2356         case OP_COND_EXC_NE_UN:
2357         case OP_COND_EXC_INE_UN:
2358         case OP_CMOV_INE_UN:
2359         case OP_CMOV_LNE_UN:
2360                 return CMP_NE;
2361         case OP_IBLE:
2362         case OP_LBLE:
2363         case OP_FBLE:
2364         case OP_CMOV_ILE:
2365         case OP_CMOV_LLE:
2366                 return CMP_LE;
2367         case OP_IBGE:
2368         case OP_LBGE:
2369         case OP_FBGE:
2370         case OP_CMOV_IGE:
2371         case OP_CMOV_LGE:
2372                 return CMP_GE;
2373         case OP_CLT:
2374         case OP_IBLT:
2375         case OP_ICLT:
2376         case OP_LBLT:
2377         case OP_LCLT:
2378         case OP_FBLT:
2379         case OP_FCLT:
2380         case OP_COND_EXC_LT:
2381         case OP_COND_EXC_ILT:
2382         case OP_CMOV_ILT:
2383         case OP_CMOV_LLT:
2384                 return CMP_LT;
2385         case OP_CGT:
2386         case OP_IBGT:
2387         case OP_ICGT:
2388         case OP_LBGT:
2389         case OP_LCGT:
2390         case OP_FBGT:
2391         case OP_FCGT:
2392         case OP_COND_EXC_GT:
2393         case OP_COND_EXC_IGT:
2394         case OP_CMOV_IGT:
2395         case OP_CMOV_LGT:
2396                 return CMP_GT;
2397
2398         case OP_IBLE_UN:
2399         case OP_LBLE_UN:
2400         case OP_FBLE_UN:
2401         case OP_COND_EXC_LE_UN:
2402         case OP_COND_EXC_ILE_UN:
2403         case OP_CMOV_ILE_UN:
2404         case OP_CMOV_LLE_UN:
2405                 return CMP_LE_UN;
2406         case OP_IBGE_UN:
2407         case OP_LBGE_UN:
2408         case OP_FBGE_UN:
2409         case OP_CMOV_IGE_UN:
2410         case OP_CMOV_LGE_UN:
2411                 return CMP_GE_UN;
2412         case OP_CLT_UN:
2413         case OP_IBLT_UN:
2414         case OP_ICLT_UN:
2415         case OP_LBLT_UN:
2416         case OP_LCLT_UN:
2417         case OP_FBLT_UN:
2418         case OP_FCLT_UN:
2419         case OP_COND_EXC_LT_UN:
2420         case OP_COND_EXC_ILT_UN:
2421         case OP_CMOV_ILT_UN:
2422         case OP_CMOV_LLT_UN:
2423                 return CMP_LT_UN;
2424         case OP_CGT_UN:
2425         case OP_IBGT_UN:
2426         case OP_ICGT_UN:
2427         case OP_LBGT_UN:
2428         case OP_LCGT_UN:
2429         case OP_FCGT_UN:
2430         case OP_FBGT_UN:
2431         case OP_COND_EXC_GT_UN:
2432         case OP_COND_EXC_IGT_UN:
2433         case OP_CMOV_IGT_UN:
2434         case OP_CMOV_LGT_UN:
2435                 return CMP_GT_UN;
2436         default:
2437                 printf ("%s\n", mono_inst_name (opcode));
2438                 g_assert_not_reached ();
2439                 return 0;
2440         }
2441 }
2442
2443 CompRelation
2444 mono_negate_cond (CompRelation cond)
2445 {
2446         switch (cond) {
2447         case CMP_EQ:
2448                 return CMP_NE;
2449         case CMP_NE:
2450                 return CMP_EQ;
2451         case CMP_LE:
2452                 return CMP_GT;
2453         case CMP_GE:
2454                 return CMP_LT;
2455         case CMP_LT:
2456                 return CMP_GE;
2457         case CMP_GT:
2458                 return CMP_LE;
2459         case CMP_LE_UN:
2460                 return CMP_GT_UN;
2461         case CMP_GE_UN:
2462                 return CMP_LT_UN;
2463         case CMP_LT_UN:
2464                 return CMP_GE_UN;
2465         case CMP_GT_UN:
2466                 return CMP_LE_UN;
2467         default:
2468                 g_assert_not_reached ();
2469         }
2470 }
2471
2472 CompType
2473 mono_opcode_to_type (int opcode, int cmp_opcode)
2474 {
2475         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2476                 return CMP_TYPE_L;
2477         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2478                 return CMP_TYPE_I;
2479         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2480                 return CMP_TYPE_I;
2481         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2482                 return CMP_TYPE_L;
2483         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2484                 return CMP_TYPE_L;
2485         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2486                 return CMP_TYPE_F;
2487         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2488                 return CMP_TYPE_F;
2489         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2490                 return CMP_TYPE_I;
2491         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2492                 switch (cmp_opcode) {
2493                 case OP_ICOMPARE:
2494                 case OP_ICOMPARE_IMM:
2495                         return CMP_TYPE_I;
2496                 default:
2497                         return CMP_TYPE_L;
2498                 }
2499         } else {
2500                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2501                 return 0;
2502         }
2503 }
2504
2505 #endif /* DISABLE_JIT */
2506
2507 gboolean
2508 mono_is_regsize_var (MonoType *t)
2509 {
2510         if (t->byref)
2511                 return TRUE;
2512         t = mono_type_get_underlying_type (t);
2513         switch (t->type) {
2514         case MONO_TYPE_BOOLEAN:
2515         case MONO_TYPE_CHAR:
2516         case MONO_TYPE_I1:
2517         case MONO_TYPE_U1:
2518         case MONO_TYPE_I2:
2519         case MONO_TYPE_U2:
2520         case MONO_TYPE_I4:
2521         case MONO_TYPE_U4:
2522         case MONO_TYPE_I:
2523         case MONO_TYPE_U:
2524         case MONO_TYPE_PTR:
2525         case MONO_TYPE_FNPTR:
2526 #if SIZEOF_REGISTER == 8
2527         case MONO_TYPE_I8:
2528         case MONO_TYPE_U8:
2529 #endif
2530                 return TRUE;
2531         case MONO_TYPE_OBJECT:
2532         case MONO_TYPE_STRING:
2533         case MONO_TYPE_CLASS:
2534         case MONO_TYPE_SZARRAY:
2535         case MONO_TYPE_ARRAY:
2536                 return TRUE;
2537         case MONO_TYPE_GENERICINST:
2538                 if (!mono_type_generic_inst_is_valuetype (t))
2539                         return TRUE;
2540                 return FALSE;
2541         case MONO_TYPE_VALUETYPE:
2542                 return FALSE;
2543         default:
2544                 return FALSE;
2545         }
2546 }
2547
2548 #ifndef DISABLE_JIT
2549
2550 /*
2551  * mono_peephole_ins:
2552  *
2553  *   Perform some architecture independent peephole optimizations.
2554  */
2555 void
2556 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2557 {
2558         MonoInst *last_ins = ins->prev;
2559
2560         switch (ins->opcode) {
2561         case OP_MUL_IMM:
2562                 /* remove unnecessary multiplication with 1 */
2563                 if (ins->inst_imm == 1) {
2564                         if (ins->dreg != ins->sreg1)
2565                                 ins->opcode = OP_MOVE;
2566                         else
2567                                 MONO_DELETE_INS (bb, ins);
2568                 }
2569                 break;
2570         case OP_LOAD_MEMBASE:
2571         case OP_LOADI4_MEMBASE:
2572                 /*
2573                  * Note: if reg1 = reg2 the load op is removed
2574                  *
2575                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2576                  * OP_LOAD_MEMBASE offset(basereg), reg2
2577                  * -->
2578                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2579                  * OP_MOVE reg1, reg2
2580                  */
2581                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2582                         last_ins = last_ins->prev;
2583                 if (last_ins &&
2584                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2585                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2586                         ins->inst_basereg == last_ins->inst_destbasereg &&
2587                         ins->inst_offset == last_ins->inst_offset) {
2588                         if (ins->dreg == last_ins->sreg1) {
2589                                 MONO_DELETE_INS (bb, ins);
2590                                 break;
2591                         } else {
2592                                 ins->opcode = OP_MOVE;
2593                                 ins->sreg1 = last_ins->sreg1;
2594                         }
2595
2596                         /*
2597                          * Note: reg1 must be different from the basereg in the second load
2598                          * Note: if reg1 = reg2 is equal then second load is removed
2599                          *
2600                          * OP_LOAD_MEMBASE offset(basereg), reg1
2601                          * OP_LOAD_MEMBASE offset(basereg), reg2
2602                          * -->
2603                          * OP_LOAD_MEMBASE offset(basereg), reg1
2604                          * OP_MOVE reg1, reg2
2605                          */
2606                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2607                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2608                           ins->inst_basereg != last_ins->dreg &&
2609                           ins->inst_basereg == last_ins->inst_basereg &&
2610                           ins->inst_offset == last_ins->inst_offset) {
2611
2612                         if (ins->dreg == last_ins->dreg) {
2613                                 MONO_DELETE_INS (bb, ins);
2614                         } else {
2615                                 ins->opcode = OP_MOVE;
2616                                 ins->sreg1 = last_ins->dreg;
2617                         }
2618
2619                         //g_assert_not_reached ();
2620
2621 #if 0
2622                         /*
2623                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2624                          * OP_LOAD_MEMBASE offset(basereg), reg
2625                          * -->
2626                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2627                          * OP_ICONST reg, imm
2628                          */
2629                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2630                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2631                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2632                                    ins->inst_offset == last_ins->inst_offset) {
2633                         ins->opcode = OP_ICONST;
2634                         ins->inst_c0 = last_ins->inst_imm;
2635                         g_assert_not_reached (); // check this rule
2636 #endif
2637                 }
2638                 break;
2639         case OP_LOADI1_MEMBASE:
2640         case OP_LOADU1_MEMBASE:
2641                 /*
2642                  * Note: if reg1 = reg2 the load op is removed
2643                  *
2644                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2645                  * OP_LOAD_MEMBASE offset(basereg), reg2
2646                  * -->
2647                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2648                  * OP_MOVE reg1, reg2
2649                  */
2650                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2651                         ins->inst_basereg == last_ins->inst_destbasereg &&
2652                         ins->inst_offset == last_ins->inst_offset) {
2653                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2654                         ins->sreg1 = last_ins->sreg1;
2655                 }
2656                 break;
2657         case OP_LOADI2_MEMBASE:
2658         case OP_LOADU2_MEMBASE:
2659                 /*
2660                  * Note: if reg1 = reg2 the load op is removed
2661                  *
2662                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2663                  * OP_LOAD_MEMBASE offset(basereg), reg2
2664                  * -->
2665                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2666                  * OP_MOVE reg1, reg2
2667                  */
2668                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2669                         ins->inst_basereg == last_ins->inst_destbasereg &&
2670                         ins->inst_offset == last_ins->inst_offset) {
2671 #if SIZEOF_REGISTER == 8
2672                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2673 #else
2674                         /* The definition of OP_PCONV_TO_U2 is wrong */
2675                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2676 #endif
2677                         ins->sreg1 = last_ins->sreg1;
2678                 }
2679                 break;
2680         case OP_MOVE:
2681         case OP_FMOVE:
2682                 /*
2683                  * Removes:
2684                  *
2685                  * OP_MOVE reg, reg
2686                  */
2687                 if (ins->dreg == ins->sreg1) {
2688                         MONO_DELETE_INS (bb, ins);
2689                         break;
2690                 }
2691                 /*
2692                  * Removes:
2693                  *
2694                  * OP_MOVE sreg, dreg
2695                  * OP_MOVE dreg, sreg
2696                  */
2697                 if (last_ins && last_ins->opcode == ins->opcode &&
2698                         ins->sreg1 == last_ins->dreg &&
2699                         ins->dreg == last_ins->sreg1) {
2700                         MONO_DELETE_INS (bb, ins);
2701                 }
2702                 break;
2703         case OP_NOP:
2704                 MONO_DELETE_INS (bb, ins);
2705                 break;
2706         }
2707 }
2708
2709 #endif /* DISABLE_JIT */