mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413 void
 414 mono_print_ins_index (int i, MonoInst *ins)
 415 {
 416         const char *spec = ins_get_spec (ins->opcode);
 417         int num_sregs, j;
 418         int sregs [MONO_MAX_SRC_REGS];
 419
 420         if (i != -1)
 421                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 422         else
 423                 printf (" %s", mono_inst_name (ins->opcode));
 424         if (spec == MONO_ARCH_CPU_SPEC) {
 425                 /* This is a lowered opcode */
 426                 if (ins->dreg != -1)
 427                         printf (" R%d <-", ins->dreg);
 428                 if (ins->sreg1 != -1)
 429                         printf (" R%d", ins->sreg1);
 430                 if (ins->sreg2 != -1)
 431                         printf (" R%d", ins->sreg2);
 432                 if (ins->sreg3 != -1)
 433                         printf (" R%d", ins->sreg3);
 434
 435                 switch (ins->opcode) {
 436                 case OP_LBNE_UN:
 437                 case OP_LBEQ:
 438                 case OP_LBLT:
 439                 case OP_LBLT_UN:
 440                 case OP_LBGT:
 441                 case OP_LBGT_UN:
 442                 case OP_LBGE:
 443                 case OP_LBGE_UN:
 444                 case OP_LBLE:
 445                 case OP_LBLE_UN:
 446                         if (!ins->inst_false_bb)
 447                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 448                         else
 449                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 450                         break;
 451                 case OP_PHI:
 452                 case OP_VPHI:
 453                 case OP_XPHI:
 454                 case OP_FPHI: {
 455                         int i;
 456                         printf (" [%d (", (int)ins->inst_c0);
 457                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 458                                 if (i)
 459                                         printf (", ");
 460                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 461                         }
 462                         printf (")]");
 463                         break;
 464                 }
 465                 case OP_LDADDR:
 466                 case OP_OUTARG_VTRETADDR:
 467                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 468                         break;
 469                 case OP_REGOFFSET:
 470                         printf (" + 0x%lx", (long)ins->inst_offset);
 471                         break;
 472                 default:
 473                         break;
 474                 }
 475
 476                 printf ("\n");
 477                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 478                 return;
 479         }
 480
 481         if (spec [MONO_INST_DEST]) {
 482                 int bank = dreg_bank (spec);
 483                 if (is_soft_reg (ins->dreg, bank)) {
 484                         if (spec [MONO_INST_DEST] == 'b') {
 485                                 if (ins->inst_offset == 0)
 486                                         printf (" [R%d] <-", ins->dreg);
 487                                 else
 488                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 489                         }
 490                         else
 491                                 printf (" R%d <-", ins->dreg);
 492                 } else if (spec [MONO_INST_DEST] == 'b') {
 493                         if (ins->inst_offset == 0)
 494                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 495                         else
 496                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 497                 } else
 498                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 499         }
 500         if (spec [MONO_INST_SRC1]) {
 501                 int bank = sreg1_bank (spec);
 502                 if (is_soft_reg (ins->sreg1, bank)) {
 503                         if (spec [MONO_INST_SRC1] == 'b')
 504                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 505                         else
 506                                 printf (" R%d", ins->sreg1);
 507                 } else if (spec [MONO_INST_SRC1] == 'b')
 508                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 509                 else
 510                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 511         }
 512         num_sregs = mono_inst_get_src_registers (ins, sregs);
 513         for (j = 1; j < num_sregs; ++j) {
 514                 int bank = sreg_bank (j, spec);
 515                 if (is_soft_reg (sregs [j], bank))
 516                         printf (" R%d", sregs [j]);
 517                 else
 518                         printf (" %s", mono_regname_full (sregs [j], bank));
 519         }
 520
 521         switch (ins->opcode) {
 522         case OP_ICONST:
 523                 printf (" [%d]", (int)ins->inst_c0);
 524                 break;
 525 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 526         case OP_X86_PUSH_IMM:
 527 #endif
 528         case OP_ICOMPARE_IMM:
 529         case OP_COMPARE_IMM:
 530         case OP_IADD_IMM:
 531         case OP_ISUB_IMM:
 532         case OP_IAND_IMM:
 533         case OP_IOR_IMM:
 534         case OP_IXOR_IMM:
 535                 printf (" [%d]", (int)ins->inst_imm);
 536                 break;
 537         case OP_ADD_IMM:
 538         case OP_LADD_IMM:
 539                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 540                 break;
 541         case OP_I8CONST:
 542                 printf (" [%lld]", (long long)ins->inst_l);
 543                 break;
 544         case OP_R8CONST:
 545                 printf (" [%f]", *(double*)ins->inst_p0);
 546                 break;
 547         case OP_R4CONST:
 548                 printf (" [%f]", *(float*)ins->inst_p0);
 549                 break;
 550         case OP_CALL:
 551         case OP_CALL_MEMBASE:
 552         case OP_CALL_REG:
 553         case OP_FCALL:
 554         case OP_FCALLVIRT:
 555         case OP_LCALL:
 556         case OP_LCALLVIRT:
 557         case OP_VCALL:
 558         case OP_VCALLVIRT:
 559         case OP_VCALL_REG:
 560         case OP_VCALL_MEMBASE:
 561         case OP_VCALL2:
 562         case OP_VCALL2_REG:
 563         case OP_VCALL2_MEMBASE:
 564         case OP_VOIDCALL:
 565         case OP_VOIDCALL_MEMBASE:
 566         case OP_VOIDCALLVIRT:
 567         case OP_TAILCALL: {
 568                 MonoCallInst *call = (MonoCallInst*)ins;
 569                 GSList *list;
 570
 571                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 572                         /*
 573                          * These are lowered opcodes, but they are in the .md files since the old
 574                          * JIT passes them to backends.
 575                          */
 576                         if (ins->dreg != -1)
 577                                 printf (" R%d <-", ins->dreg);
 578                 }
 579
 580                 if (call->method) {
 581                         char *full_name = mono_method_full_name (call->method, TRUE);
 582                         printf (" [%s]", full_name);
 583                         g_free (full_name);
 584                 } else if (call->fptr) {
 585                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 586                         if (info)
 587                                 printf (" [%s]", info->name);
 588                 }
 589
 590                 list = call->out_ireg_args;
 591                 while (list) {
 592                         guint32 regpair;
 593                         int reg, hreg;
 594
 595                         regpair = (guint32)(gssize)(list->data);
 596                         hreg = regpair >> 24;
 597                         reg = regpair & 0xffffff;
 598
 599                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 600
 601                         list = g_slist_next (list);
 602                 }
 603                 break;
 604         }
 605         case OP_BR:
 606         case OP_CALL_HANDLER:
 607                 printf (" [B%d]", ins->inst_target_bb->block_num);
 608                 break;
 609         case OP_IBNE_UN:
 610         case OP_IBEQ:
 611         case OP_IBLT:
 612         case OP_IBLT_UN:
 613         case OP_IBGT:
 614         case OP_IBGT_UN:
 615         case OP_IBGE:
 616         case OP_IBGE_UN:
 617         case OP_IBLE:
 618         case OP_IBLE_UN:
 619         case OP_LBNE_UN:
 620         case OP_LBEQ:
 621         case OP_LBLT:
 622         case OP_LBLT_UN:
 623         case OP_LBGT:
 624         case OP_LBGT_UN:
 625         case OP_LBGE:
 626         case OP_LBGE_UN:
 627         case OP_LBLE:
 628         case OP_LBLE_UN:
 629                 if (!ins->inst_false_bb)
 630                         printf (" [B%d]", ins->inst_true_bb->block_num);
 631                 else
 632                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 633                 break;
 634         case OP_LIVERANGE_START:
 635         case OP_LIVERANGE_END:
 636         case OP_GC_LIVENESS_DEF:
 637         case OP_GC_LIVENESS_USE:
 638                 printf (" R%d", (int)ins->inst_c1);
 639                 break;
 640         case OP_SEQ_POINT:
 641                 printf (" il: %x", (int)ins->inst_imm);
 642                 break;
 643         default:
 644                 break;
 645         }
 646
 647         if (spec [MONO_INST_CLOB])
 648                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 649         printf ("\n");
 650 }
 651
 652 static void
 653 print_regtrack (RegTrack *t, int num)
 654 {
 655         int i;
 656         char buf [32];
 657         const char *r;
 658
 659         for (i = 0; i < num; ++i) {
 660                 if (!t [i].born_in)
 661                         continue;
 662                 if (i >= MONO_MAX_IREGS) {
 663                         g_snprintf (buf, sizeof(buf), "R%d", i);
 664                         r = buf;
 665                 } else
 666                         r = mono_arch_regname (i);
 667                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 668         }
 669 }
 670 #else
 671 void
 672 mono_print_ins_index (int i, MonoInst *ins)
 673 {
 674 }
 675 #endif /* DISABLE_LOGGING */
 676
 677 void
 678 mono_print_ins (MonoInst *ins)
 679 {
 680         mono_print_ins_index (-1, ins);
 681 }
 682
 683 static inline void
 684 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 685 {
 686         /*
 687          * If this function is called multiple times, the new instructions are inserted
 688          * in the proper order.
 689          */
 690         mono_bblock_insert_before_ins (bb, ins, to_insert);
 691 }
 692
 693 static inline void
 694 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 695 {
 696         /*
 697          * If this function is called multiple times, the new instructions are inserted in
 698          * proper order.
 699          */
 700         mono_bblock_insert_after_ins (bb, *last, to_insert);
 701
 702         *last = to_insert;
 703 }
 704
 705 static inline int
 706 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 707 {
 708         if (vreg_is_ref (cfg, reg))
 709                 return MONO_REG_INT_REF;
 710         else if (vreg_is_mp (cfg, reg))
 711                 return MONO_REG_INT_MP;
 712         else
 713                 return bank;
 714 }
 715
 716 /*
 717  * Force the spilling of the variable in the symbolic register 'reg', and free
 718  * the hreg it was assigned to.
 719  */
 720 static void
 721 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 722 {
 723         MonoInst *load;
 724         int i, sel, spill;
 725         int *symbolic;
 726         MonoRegState *rs = cfg->rs;
 727
 728         symbolic = rs->symbolic [bank];
 729         sel = rs->vassign [reg];
 730
 731         /* the vreg we need to spill lives in another logical reg bank */
 732         bank = translate_bank (cfg->rs, bank, sel);
 733
 734         /*i = rs->isymbolic [sel];
 735         g_assert (i == reg);*/
 736         i = reg;
 737         spill = ++cfg->spill_count;
 738         rs->vassign [i] = -spill - 1;
 739         if (G_UNLIKELY (bank))
 740                 mono_regstate_free_general (rs, sel, bank);
 741         else
 742                 mono_regstate_free_int (rs, sel);
 743         /* we need to create a spill var and insert a load to sel after the current instruction */
 744         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 745         load->dreg = sel;
 746         load->inst_basereg = cfg->frame_reg;
 747         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 748         insert_after_ins (bb, ins, last, load);
 749         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 750         if (G_UNLIKELY (bank))
 751                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 752         else
 753                 i = mono_regstate_alloc_int (rs, regmask (sel));
 754         g_assert (i == sel);
 755
 756         if (G_UNLIKELY (bank))
 757                 mono_regstate_free_general (rs, sel, bank);
 758         else
 759                 mono_regstate_free_int (rs, sel);
 760 }
 761
 762 /* This isn't defined on older glib versions and on some platforms */
 763 #ifndef G_GUINT64_FORMAT
 764 #define G_GUINT64_FORMAT "ul"
 765 #endif
 766
 767 static int
 768 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 769 {
 770         MonoInst *load;
 771         int i, sel, spill, num_sregs;
 772         int sregs [MONO_MAX_SRC_REGS];
 773         int *symbolic;
 774         MonoRegState *rs = cfg->rs;
 775
 776         symbolic = rs->symbolic [bank];
 777
 778         g_assert (bank < MONO_NUM_REGBANKS);
 779
 780         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 781         /* exclude the registers in the current instruction */
 782         num_sregs = mono_inst_get_src_registers (ins, sregs);
 783         for (i = 0; i < num_sregs; ++i) {
 784                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 785                         if (is_soft_reg (sregs [i], bank))
 786                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 787                         else
 788                                 regmask &= ~ (regmask (sregs [i]));
 789                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 790                 }
 791         }
 792         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 793                 regmask &= ~ (regmask (ins->dreg));
 794                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 795         }
 796
 797         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 798         g_assert (regmask); /* need at least a register we can free */
 799         sel = 0;
 800         /* we should track prev_use and spill the register that's farther */
 801         if (G_UNLIKELY (bank)) {
 802                 for (i = 0; i < regbank_size [bank]; ++i) {
 803                         if (regmask & (regmask (i))) {
 804                                 sel = i;
 805
 806                                 /* the vreg we need to load lives in another logical bank */
 807                                 bank = translate_bank (cfg->rs, bank, sel);
 808
 809                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 810                                 break;
 811                         }
 812                 }
 813
 814                 i = rs->symbolic [bank] [sel];
 815                 spill = ++cfg->spill_count;
 816                 rs->vassign [i] = -spill - 1;
 817                 mono_regstate_free_general (rs, sel, bank);
 818         }
 819         else {
 820                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 821                         if (regmask & (regmask (i))) {
 822                                 sel = i;
 823                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 824                                 break;
 825                         }
 826                 }
 827
 828                 i = rs->isymbolic [sel];
 829                 spill = ++cfg->spill_count;
 830                 rs->vassign [i] = -spill - 1;
 831                 mono_regstate_free_int (rs, sel);
 832         }
 833
 834         /* we need to create a spill var and insert a load to sel after the current instruction */
 835         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 836         load->dreg = sel;
 837         load->inst_basereg = cfg->frame_reg;
 838         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 839         insert_after_ins (bb, ins, last, load);
 840         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 841         if (G_UNLIKELY (bank))
 842                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 843         else
 844                 i = mono_regstate_alloc_int (rs, regmask (sel));
 845         g_assert (i == sel);
 846
 847         return sel;
 848 }
 849
 850 /*
 851  * free_up_hreg:
 852  *
 853  *   Free up the hreg HREG by spilling the vreg allocated to it.
 854  */
 855 static void
 856 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 857 {
 858         if (G_UNLIKELY (bank)) {
 859                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 860                         bank = translate_bank (cfg->rs, bank, hreg);
 861                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 862                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 863                 }
 864         }
 865         else {
 866                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 867                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 868                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 869                 }
 870         }
 871 }
 872
 873 static MonoInst*
 874 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 875 {
 876         MonoInst *copy;
 877
 878         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 879
 880         copy->dreg = dest;
 881         copy->sreg1 = src;
 882         copy->cil_code = ip;
 883         if (ins) {
 884                 mono_bblock_insert_after_ins (bb, ins, copy);
 885                 *last = copy;
 886         }
 887         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 888         return copy;
 889 }
 890
 891 static inline const char*
 892 regbank_to_string (int bank)
 893 {
 894         if (bank == MONO_REG_INT_REF)
 895                 return "REF ";
 896         else if (bank == MONO_REG_INT_MP)
 897                 return "MP ";
 898         else
 899                 return "";
 900 }
 901
 902 static void
 903 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 904 {
 905         MonoInst *store, *def;
 906
 907         bank = get_vreg_bank (cfg, prev_reg, bank);
 908
 909         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 910         store->sreg1 = reg;
 911         store->inst_destbasereg = cfg->frame_reg;
 912         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 913         if (ins) {
 914                 mono_bblock_insert_after_ins (bb, ins, store);
 915                 *last = store;
 916         } else if (insert_before) {
 917                 insert_before_ins (bb, insert_before, store);
 918         } else {
 919                 g_assert_not_reached ();
 920         }
 921         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 922
 923         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 924                 g_assert (prev_reg != -1);
 925                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 926                 def->inst_c0 = spill;
 927                 def->inst_c1 = bank;
 928                 mono_bblock_insert_after_ins (bb, store, def);
 929         }
 930 }
 931
 932 /* flags used in reginfo->flags */
 933 enum {
 934         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 935         MONO_FP_NEEDS_SPILL                     = regmask (1),
 936         MONO_FP_NEEDS_LOAD                      = regmask (2)
 937 };
 938
 939 static inline int
 940 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 941 {
 942         int val;
 943
 944         if (info && info->preferred_mask) {
 945                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 946                 if (val >= 0) {
 947                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 948                         return val;
 949                 }
 950         }
 951
 952         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 953         if (val < 0)
 954                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 955
 956         return val;
 957 }
 958
 959 static inline int
 960 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 961 {
 962         int val;
 963
 964         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 965
 966         if (val < 0)
 967                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 968
 969         return val;
 970 }
 971
 972 static inline int
 973 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 974 {
 975         if (G_UNLIKELY (bank))
 976                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 977         else
 978                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 979 }
 980
 981 static inline void
 982 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 983 {
 984         if (G_UNLIKELY (bank)) {
 985                 int mirrored_bank;
 986
 987                 g_assert (reg >= regbank_size [bank]);
 988                 g_assert (hreg < regbank_size [bank]);
 989                 g_assert (! is_global_freg (hreg));
 990
 991                 rs->vassign [reg] = hreg;
 992                 rs->symbolic [bank] [hreg] = reg;
 993                 rs->free_mask [bank] &= ~ (regmask (hreg));
 994
 995                 mirrored_bank = get_mirrored_bank (bank);
 996                 if (mirrored_bank == -1)
 997                         return;
 998
 999                 /* Make sure the other logical reg bank that this bank shares
1000                  * a single hard reg bank knows that this hard reg is not free.
1001                  */
1002                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1003
1004                 /* Mark the other logical bank that the this bank shares
1005                  * a single hard reg bank with as mirrored.
1006                  */
1007                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1008
1009         }
1010         else {
1011                 g_assert (reg >= MONO_MAX_IREGS);
1012                 g_assert (hreg < MONO_MAX_IREGS);
1013 #ifndef TARGET_ARM
1014                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1015                 g_assert (! is_global_ireg (hreg));
1016 #endif
1017
1018                 rs->vassign [reg] = hreg;
1019                 rs->isymbolic [hreg] = reg;
1020                 rs->ifree_mask &= ~ (regmask (hreg));
1021         }
1022 }
1023
1024 static inline regmask_t
1025 get_callee_mask (const char spec)
1026 {
1027         if (G_UNLIKELY (reg_bank (spec)))
1028                 return regbank_callee_regs [reg_bank (spec)];
1029         return MONO_ARCH_CALLEE_REGS;
1030 }
1031
1032 static gint8 desc_to_fixed_reg [256];
1033 static gboolean desc_to_fixed_reg_inited = FALSE;
1034
1035 #ifndef DISABLE_JIT
1036
1037 /*
1038  * Local register allocation.
1039  * We first scan the list of instructions and we save the liveness info of
1040  * each register (when the register is first used, when it's value is set etc.).
1041  * We also reverse the list of instructions because assigning registers backwards allows
1042  * for more tricks to be used.
1043  */
1044 void
1045 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1046 {
1047         MonoInst *ins, *prev, *last;
1048         MonoInst **tmp;
1049         MonoRegState *rs = cfg->rs;
1050         int i, j, val, max;
1051         RegTrack *reginfo;
1052         const char *spec;
1053         unsigned char spec_src1, spec_dest;
1054         int bank = 0;
1055 #if MONO_ARCH_USE_FPSTACK
1056         gboolean has_fp = FALSE;
1057         int fpstack [8];
1058         int sp = 0;
1059 #endif
1060         int num_sregs = 0;
1061         int sregs [MONO_MAX_SRC_REGS];
1062
1063         if (!bb->code)
1064                 return;
1065
1066         if (!desc_to_fixed_reg_inited) {
1067                 for (i = 0; i < 256; ++i)
1068                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1069                 desc_to_fixed_reg_inited = TRUE;
1070
1071                 /* Validate the cpu description against the info in mini-ops.h */
1072 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1073                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1074                         const char *ispec;
1075
1076                         spec = ins_get_spec (i);
1077                         ispec = INS_INFO (i);
1078
1079                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1080                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1081                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1082                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1083                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1084                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1085                 }
1086 #endif
1087         }
1088
1089         rs->next_vreg = bb->max_vreg;
1090         mono_regstate_assign (rs);
1091
1092         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1093         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1094                 rs->free_mask [i] = regbank_callee_regs [i];
1095
1096         max = rs->next_vreg;
1097
1098         if (cfg->reginfo && cfg->reginfo_len < max)
1099                 cfg->reginfo = NULL;
1100
1101         reginfo = cfg->reginfo;
1102         if (!reginfo) {
1103                 cfg->reginfo_len = MAX (1024, max * 2);
1104                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1105         }
1106         else
1107                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1108
1109         if (cfg->verbose_level > 1) {
1110                 /* print_regtrack reads the info of all variables */
1111                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1112         }
1113
1114         /*
1115          * For large methods, next_vreg can be very large, so g_malloc0 time can
1116          * be prohibitive. So we manually init the reginfo entries used by the
1117          * bblock.
1118          */
1119         for (ins = bb->code; ins; ins = ins->next) {
1120                 spec = ins_get_spec (ins->opcode);
1121
1122                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1123                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1124 #if SIZEOF_REGISTER == 4
1125                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1126                                 /**
1127                                  * In the new IR, the two vregs of the regpair do not alias the
1128                                  * original long vreg. shift the vreg here so the rest of the
1129                                  * allocator doesn't have to care about it.
1130                                  */
1131                                 ins->dreg ++;
1132                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1133                         }
1134 #endif
1135                 }
1136
1137                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1138                 for (j = 0; j < num_sregs; ++j) {
1139                         g_assert (sregs [j] != -1);
1140                         if (sregs [j] < max) {
1141                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1142 #if SIZEOF_REGISTER == 4
1143                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1144                                         sregs [j]++;
1145                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1146                                 }
1147 #endif
1148                         }
1149                 }
1150                 mono_inst_set_src_registers (ins, sregs);
1151         }
1152
1153         /*if (cfg->opt & MONO_OPT_COPYPROP)
1154                 local_copy_prop (cfg, ins);*/
1155
1156         i = 1;
1157         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1158         /* forward pass on the instructions to collect register liveness info */
1159         MONO_BB_FOR_EACH_INS (bb, ins) {
1160                 spec = ins_get_spec (ins->opcode);
1161                 spec_dest = spec [MONO_INST_DEST];
1162
1163                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1164                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1165                 }
1166
1167                 DEBUG (mono_print_ins_index (i, ins));
1168
1169                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1170
1171 #if MONO_ARCH_USE_FPSTACK
1172                 if (dreg_is_fp (spec)) {
1173                         has_fp = TRUE;
1174                 } else {
1175                         for (j = 0; j < num_sregs; ++j) {
1176                                 if (sreg_is_fp (j, spec))
1177                                         has_fp = TRUE;
1178                         }
1179                 }
1180 #endif
1181
1182                 for (j = 0; j < num_sregs; ++j) {
1183                         int sreg = sregs [j];
1184                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1185                         if (sreg_spec) {
1186                                 bank = sreg_bank (j, spec);
1187                                 g_assert (sreg != -1);
1188                                 if (is_soft_reg (sreg, bank))
1189                                         /* This means the vreg is not local to this bb */
1190                                         g_assert (reginfo [sreg].born_in > 0);
1191                                 rs->vassign [sreg] = -1;
1192                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1193                                 //reginfo [ins->sreg2].last_use = i;
1194                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1195                                         /* The virtual register is allocated sequentially */
1196                                         rs->vassign [sreg + 1] = -1;
1197                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1198                                         //reginfo [ins->sreg2 + 1].last_use = i;
1199                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1200                                                 reginfo [sreg + 1].born_in = i;
1201                                 }
1202                         } else {
1203                                 sregs [j] = -1;
1204                         }
1205                 }
1206                 mono_inst_set_src_registers (ins, sregs);
1207
1208                 if (spec_dest) {
1209                         int dest_dreg;
1210
1211                         bank = dreg_bank (spec);
1212                         if (spec_dest != 'b') /* it's not just a base register */
1213                                 reginfo [ins->dreg].killed_in = i;
1214                         g_assert (ins->dreg != -1);
1215                         rs->vassign [ins->dreg] = -1;
1216                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1217                         //reginfo [ins->dreg].last_use = i;
1218                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1219                                 reginfo [ins->dreg].born_in = i;
1220
1221                         dest_dreg = desc_to_fixed_reg [spec_dest];
1222                         if (dest_dreg != -1)
1223                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1224
1225 #ifdef MONO_ARCH_INST_FIXED_MASK
1226                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1227 #endif
1228
1229                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1230                                 /* The virtual register is allocated sequentially */
1231                                 rs->vassign [ins->dreg + 1] = -1;
1232                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1233                                 //reginfo [ins->dreg + 1].last_use = i;
1234                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1235                                         reginfo [ins->dreg + 1].born_in = i;
1236                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1237                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1238                         }
1239                 } else {
1240                         ins->dreg = -1;
1241                 }
1242
1243                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1244                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1245
1246                         MonoCallInst *call = (MonoCallInst*)ins;
1247                         GSList *list;
1248
1249                         list = call->out_ireg_args;
1250                         if (list) {
1251                                 while (list) {
1252                                         guint32 regpair;
1253                                         int reg, hreg;
1254
1255                                         regpair = (guint32)(gssize)(list->data);
1256                                         hreg = regpair >> 24;
1257                                         reg = regpair & 0xffffff;
1258
1259                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1260                                         //reginfo [reg].last_use = i;
1261
1262                                         list = g_slist_next (list);
1263                                 }
1264                         }
1265
1266                         list = call->out_freg_args;
1267                         if (list) {
1268                                 while (list) {
1269                                         guint32 regpair;
1270                                         int reg, hreg;
1271
1272                                         regpair = (guint32)(gssize)(list->data);
1273                                         hreg = regpair >> 24;
1274                                         reg = regpair & 0xffffff;
1275
1276                                         list = g_slist_next (list);
1277                                 }
1278                         }
1279                 }
1280
1281                 ++i;
1282         }
1283
1284         tmp = &last;
1285
1286         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1287         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1288                 int prev_dreg, clob_dreg;
1289                 int dest_dreg, clob_reg;
1290                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1291                 int dreg_high, sreg1_high;
1292                 regmask_t dreg_mask, mask;
1293                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1294                 regmask_t dreg_fixed_mask;
1295                 const unsigned char *ip;
1296                 --i;
1297                 spec = ins_get_spec (ins->opcode);
1298                 spec_src1 = spec [MONO_INST_SRC1];
1299                 spec_dest = spec [MONO_INST_DEST];
1300                 prev_dreg = -1;
1301                 clob_dreg = -1;
1302                 clob_reg = -1;
1303                 dest_dreg = -1;
1304                 dreg_high = -1;
1305                 sreg1_high = -1;
1306                 dreg_mask = get_callee_mask (spec_dest);
1307                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1308                         prev_sregs [j] = -1;
1309                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1310                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1311 #ifdef MONO_ARCH_INST_FIXED_MASK
1312                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1313 #else
1314                         sreg_fixed_masks [j] = 0;
1315 #endif
1316                 }
1317
1318                 DEBUG (printf ("processing:"));
1319                 DEBUG (mono_print_ins_index (i, ins));
1320
1321                 ip = ins->cil_code;
1322
1323                 last = ins;
1324
1325                 /*
1326                  * FIXED REGS
1327                  */
1328                 dest_dreg = desc_to_fixed_reg [spec_dest];
1329                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1330                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1331
1332 #ifdef MONO_ARCH_INST_FIXED_MASK
1333                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1334 #else
1335                 dreg_fixed_mask = 0;
1336 #endif
1337
1338                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1339
1340                 /*
1341                  * TRACK FIXED SREG2, 3, ...
1342                  */
1343                 for (j = 1; j < num_sregs; ++j) {
1344                         int sreg = sregs [j];
1345                         int dest_sreg = dest_sregs [j];
1346
1347                         if (dest_sreg == -1)
1348                                 continue;
1349
1350                         if (j == 2) {
1351                                 int k;
1352
1353                                 /*
1354                                  * CAS.
1355                                  * We need to special case this, since on x86, there are only 3
1356                                  * free registers, and the code below assigns one of them to
1357                                  * sreg, so we can run out of registers when trying to assign
1358                                  * dreg. Instead, we just set up the register masks, and let the
1359                                  * normal sreg2 assignment code handle this. It would be nice to
1360                                  * do this for all the fixed reg cases too, but there is too much
1361                                  * risk of breakage.
1362                                  */
1363
1364                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1365                                 sreg_masks [j] = regmask (dest_sreg);
1366                                 for (k = 0; k < num_sregs; ++k) {
1367                                         if (k != j)
1368                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1369                                 }
1370
1371                                 /*
1372                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1373                                  */
1374                                 for (k = 0; k < num_sregs; ++k) {
1375                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1376                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1377                                 }
1378
1379                                 /*
1380                                  * We can also run out of registers while processing sreg2 if sreg3 is
1381                                  * assigned to another hreg, so spill sreg3 now.
1382                                  */
1383                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1384                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1385                                 }
1386                                 continue;
1387                         }
1388
1389                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1390                                 if (is_global_ireg (sreg)) {
1391                                         int k;
1392                                         /* Argument already in hard reg, need to copy */
1393                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1394                                         insert_before_ins (bb, ins, copy);
1395                                         for (k = 0; k < num_sregs; ++k) {
1396                                                 if (k != j)
1397                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1398                                         }
1399                                 } else {
1400                                         val = rs->vassign [sreg];
1401                                         if (val == -1) {
1402                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1403                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1404                                         } else if (val < -1) {
1405                                                 /* FIXME: */
1406                                                 g_assert_not_reached ();
1407                                         } else {
1408                                                 /* Argument already in hard reg, need to copy */
1409                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1410                                                 int k;
1411
1412                                                 insert_before_ins (bb, ins, copy);
1413                                                 for (k = 0; k < num_sregs; ++k) {
1414                                                         if (k != j)
1415                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1416                                                 }
1417                                                 /*
1418                                                  * Prevent the dreg from being allocate to dest_sreg
1419                                                  * too, since it could force sreg1 to be allocated to
1420                                                  * the same reg on x86.
1421                                                  */
1422                                                 dreg_mask &= ~ (regmask (dest_sreg));
1423                                         }
1424                                 }
1425                         } else {
1426                                 gboolean need_spill = TRUE;
1427                                 gboolean need_assign = TRUE;
1428                                 int k;
1429
1430                                 dreg_mask &= ~ (regmask (dest_sreg));
1431                                 for (k = 0; k < num_sregs; ++k) {
1432                                         if (k != j)
1433                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1434                                 }
1435
1436                                 /*
1437                                  * First check if dreg is assigned to dest_sreg2, since we
1438                                  * can't spill a dreg.
1439                                  */
1440                                 if (spec [MONO_INST_DEST])
1441                                         val = rs->vassign [ins->dreg];
1442                                 else
1443                                         val = -1;
1444                                 if (val == dest_sreg && ins->dreg != sreg) {
1445                                         /*
1446                                          * the destination register is already assigned to
1447                                          * dest_sreg2: we need to allocate another register for it
1448                                          * and then copy from this to dest_sreg2.
1449                                          */
1450                                         int new_dest;
1451                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1452                                         g_assert (new_dest >= 0);
1453                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1454
1455                                         prev_dreg = ins->dreg;
1456                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1457                                         clob_dreg = ins->dreg;
1458                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1459                                         mono_regstate_free_int (rs, dest_sreg);
1460                                         need_spill = FALSE;
1461                                 }
1462
1463                                 if (is_global_ireg (sreg)) {
1464                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1465                                         insert_before_ins (bb, ins, copy);
1466                                         need_assign = FALSE;
1467                                 }
1468                                 else {
1469                                         val = rs->vassign [sreg];
1470                                         if (val == dest_sreg) {
1471                                                 /* sreg2 is already assigned to the correct register */
1472                                                 need_spill = FALSE;
1473                                         } else if (val < -1) {
1474                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1475                                         } else if (val >= 0) {
1476                                                 /* sreg2 already assigned to another register */
1477                                                 /*
1478                                                  * We couldn't emit a copy from val to dest_sreg2, because
1479                                                  * val might be spilled later while processing this
1480                                                  * instruction. So we spill sreg2 so it can be allocated to
1481                                                  * dest_sreg2.
1482                                                  */
1483                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1484                                         }
1485                                 }
1486
1487                                 if (need_spill) {
1488                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1489                                 }
1490
1491                                 if (need_assign) {
1492                                         if (rs->vassign [sreg] < -1) {
1493                                                 int spill;
1494
1495                                                 /* Need to emit a spill store */
1496                                                 spill = - rs->vassign [sreg] - 1;
1497                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1498                                         }
1499                                         /* force-set sreg2 */
1500                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1501                                 }
1502                         }
1503                         sregs [j] = dest_sreg;
1504                 }
1505                 mono_inst_set_src_registers (ins, sregs);
1506
1507                 /*
1508                  * TRACK DREG
1509                  */
1510                 bank = dreg_bank (spec);
1511                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1512                         prev_dreg = ins->dreg;
1513                 }
1514
1515                 if (spec_dest == 'b') {
1516                         /*
1517                          * The dest reg is read by the instruction, not written, so
1518                          * avoid allocating sreg1/sreg2 to the same reg.
1519                          */
1520                         if (dest_sregs [0] != -1)
1521                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1522                         for (j = 1; j < num_sregs; ++j) {
1523                                 if (dest_sregs [j] != -1)
1524                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1525                         }
1526
1527                         val = rs->vassign [ins->dreg];
1528                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1529                                 /* DREG is already allocated to a register needed for sreg1 */
1530                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1531                         }
1532                 }
1533
1534                 /*
1535                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1536                  * various complex situations.
1537                  */
1538                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1539                         guint32 dreg2, dest_dreg2;
1540
1541                         g_assert (is_soft_reg (ins->dreg, bank));
1542
1543                         if (dest_dreg != -1) {
1544                                 if (rs->vassign [ins->dreg] != dest_dreg)
1545                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1546
1547                                 dreg2 = ins->dreg + 1;
1548                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1549                                 if (dest_dreg2 != -1) {
1550                                         if (rs->vassign [dreg2] != dest_dreg2)
1551                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1552                                 }
1553                         }
1554                 }
1555
1556                 if (dreg_fixed_mask) {
1557                         g_assert (!bank);
1558                         if (is_global_ireg (ins->dreg)) {
1559                                 /*
1560                                  * The argument is already in a hard reg, but that reg is
1561                                  * not usable by this instruction, so allocate a new one.
1562                                  */
1563                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1564                                 if (val < 0)
1565                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1566                                 mono_regstate_free_int (rs, val);
1567                                 dest_dreg = val;
1568
1569                                 /* Fall through */
1570                         }
1571                         else
1572                                 dreg_mask &= dreg_fixed_mask;
1573                 }
1574
1575                 if (is_soft_reg (ins->dreg, bank)) {
1576                         val = rs->vassign [ins->dreg];
1577
1578                         if (val < 0) {
1579                                 int spill = 0;
1580                                 if (val < -1) {
1581                                         /* the register gets spilled after this inst */
1582                                         spill = -val -1;
1583                                 }
1584                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1585                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1586                                 if (spill)
1587                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1588                         }
1589
1590                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1591                         ins->dreg = val;
1592                 }
1593
1594                 /* Handle regpairs */
1595                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1596                         int reg2 = prev_dreg + 1;
1597
1598                         g_assert (!bank);
1599                         g_assert (prev_dreg > -1);
1600                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1601                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1602 #ifdef TARGET_X86
1603                         /* bug #80489 */
1604                         mask &= ~regmask (X86_ECX);
1605 #endif
1606                         val = rs->vassign [reg2];
1607                         if (val < 0) {
1608                                 int spill = 0;
1609                                 if (val < -1) {
1610                                         /* the register gets spilled after this inst */
1611                                         spill = -val -1;
1612                                 }
1613                                 val = mono_regstate_alloc_int (rs, mask);
1614                                 if (val < 0)
1615                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1616                                 if (spill)
1617                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1618                         }
1619                         else {
1620                                 if (! (mask & (regmask (val)))) {
1621                                         val = mono_regstate_alloc_int (rs, mask);
1622                                         if (val < 0)
1623                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1624
1625                                         /* Reallocate hreg to the correct register */
1626                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1627
1628                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1629                                 }
1630                         }
1631
1632                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1633                         assign_reg (cfg, rs, reg2, val, bank);
1634
1635                         dreg_high = val;
1636                         ins->backend.reg3 = val;
1637
1638                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1639                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1640                                 mono_regstate_free_int (rs, val);
1641                         }
1642                 }
1643
1644                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1645                         /*
1646                          * In theory, we could free up the hreg even if the vreg is alive,
1647                          * but branches inside bblocks force us to assign the same hreg
1648                          * to a vreg every time it is encountered.
1649                          */
1650                         int dreg = rs->vassign [prev_dreg];
1651                         g_assert (dreg >= 0);
1652                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1653                         if (G_UNLIKELY (bank))
1654                                 mono_regstate_free_general (rs, dreg, bank);
1655                         else
1656                                 mono_regstate_free_int (rs, dreg);
1657                         rs->vassign [prev_dreg] = -1;
1658                 }
1659
1660                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1661                         /* this instruction only outputs to dest_dreg, need to copy */
1662                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1663                         ins->dreg = dest_dreg;
1664
1665                         if (G_UNLIKELY (bank)) {
1666                                 /* the register we need to free up may be used in another logical regbank
1667                                  * so do a translate just in case.
1668                                  */
1669                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1670                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1671                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1672                         }
1673                         else {
1674                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1675                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1676                         }
1677                 }
1678
1679                 if (spec_dest == 'b') {
1680                         /*
1681                          * The dest reg is read by the instruction, not written, so
1682                          * avoid allocating sreg1/sreg2 to the same reg.
1683                          */
1684                         for (j = 0; j < num_sregs; ++j)
1685                                 if (!sreg_bank (j, spec))
1686                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1687                 }
1688
1689                 /*
1690                  * TRACK CLOBBERING
1691                  */
1692                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1693                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1694                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1695                 }
1696
1697                 if (spec [MONO_INST_CLOB] == 'c') {
1698                         int j, s, dreg, dreg2, cur_bank;
1699                         guint64 clob_mask;
1700
1701                         clob_mask = MONO_ARCH_CALLEE_REGS;
1702
1703                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1704                                 /*
1705                                  * Need to avoid spilling the dreg since the dreg is not really
1706                                  * clobbered by the call.
1707                                  */
1708                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1709                                         dreg = rs->vassign [prev_dreg];
1710                                 else
1711                                         dreg = -1;
1712
1713                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1714                                         dreg2 = rs->vassign [prev_dreg + 1];
1715                                 else
1716                                         dreg2 = -1;
1717
1718                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1719                                         s = regmask (j);
1720                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1721                                                 if ((j != dreg) && (j != dreg2))
1722                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1723                                                 else if (rs->isymbolic [j])
1724                                                         /* The hreg is assigned to the dreg of this instruction */
1725                                                         rs->vassign [rs->isymbolic [j]] = -1;
1726                                                 mono_regstate_free_int (rs, j);
1727                                         }
1728                                 }
1729                         }
1730
1731                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1732                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1733                                         clob_mask = regbank_callee_regs [cur_bank];
1734                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1735                                                 dreg = rs->vassign [prev_dreg];
1736                                         else
1737                                                 dreg = -1;
1738
1739                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1740
1741                                                 /* we are looping though the banks in the outer loop
1742                                                  * so, we don't need to deal with mirrored hregs
1743                                                  * because we will get them in one of the other bank passes.
1744                                                  */
1745                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1746                                                         continue;
1747
1748                                                 s = regmask (j);
1749                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1750                                                         if (j != dreg)
1751                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1752                                                         else if (rs->symbolic [cur_bank] [j])
1753                                                                 /* The hreg is assigned to the dreg of this instruction */
1754                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1755                                                         mono_regstate_free_general (rs, j, cur_bank);
1756                                                 }
1757                                         }
1758                                 }
1759                         }
1760                 }
1761
1762                 /*
1763                  * TRACK ARGUMENT REGS
1764                  */
1765                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1766                         MonoCallInst *call = (MonoCallInst*)ins;
1767                         GSList *list;
1768
1769                         /*
1770                          * This needs to be done before assigning sreg1, so sreg1 will
1771                          * not be assigned one of the argument regs.
1772                          */
1773
1774                         /*
1775                          * Assign all registers in call->out_reg_args to the proper
1776                          * argument registers.
1777                          */
1778
1779                         list = call->out_ireg_args;
1780                         if (list) {
1781                                 while (list) {
1782                                         guint32 regpair;
1783                                         int reg, hreg;
1784
1785                                         regpair = (guint32)(gssize)(list->data);
1786                                         hreg = regpair >> 24;
1787                                         reg = regpair & 0xffffff;
1788
1789                                         assign_reg (cfg, rs, reg, hreg, 0);
1790
1791                                         sreg_masks [0] &= ~(regmask (hreg));
1792
1793                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1794
1795                                         list = g_slist_next (list);
1796                                 }
1797                         }
1798
1799                         list = call->out_freg_args;
1800                         if (list) {
1801                                 while (list) {
1802                                         guint32 regpair;
1803                                         int reg, hreg;
1804
1805                                         regpair = (guint32)(gssize)(list->data);
1806                                         hreg = regpair >> 24;
1807                                         reg = regpair & 0xffffff;
1808
1809                                         assign_reg (cfg, rs, reg, hreg, 1);
1810
1811                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1812
1813                                         list = g_slist_next (list);
1814                                 }
1815                         }
1816                 }
1817
1818                 /*
1819                  * TRACK SREG1
1820                  */
1821                 bank = sreg1_bank (spec);
1822                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1823                         int sreg1 = sregs [0];
1824                         int dest_sreg1 = dest_sregs [0];
1825
1826                         g_assert (is_soft_reg (sreg1, bank));
1827
1828                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1829                         if (dest_sreg1 != -1)
1830                                 g_assert (dest_sreg1 == ins->dreg);
1831                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1832                         g_assert (val >= 0);
1833
1834                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1835                                 // FIXME:
1836                                 g_assert_not_reached ();
1837
1838                         assign_reg (cfg, rs, sreg1, val, bank);
1839
1840                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1841
1842                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1843                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1844                         g_assert (val >= 0);
1845
1846                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1847                                 // FIXME:
1848                                 g_assert_not_reached ();
1849
1850                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1851
1852                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1853
1854                         /* Skip rest of this section */
1855                         dest_sregs [0] = -1;
1856                 }
1857
1858                 if (sreg_fixed_masks [0]) {
1859                         g_assert (!bank);
1860                         if (is_global_ireg (sregs [0])) {
1861                                 /*
1862                                  * The argument is already in a hard reg, but that reg is
1863                                  * not usable by this instruction, so allocate a new one.
1864                                  */
1865                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1866                                 if (val < 0)
1867                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1868                                 mono_regstate_free_int (rs, val);
1869                                 dest_sregs [0] = val;
1870
1871                                 /* Fall through to the dest_sreg1 != -1 case */
1872                         }
1873                         else
1874                                 sreg_masks [0] &= sreg_fixed_masks [0];
1875                 }
1876
1877                 if (dest_sregs [0] != -1) {
1878                         sreg_masks [0] = regmask (dest_sregs [0]);
1879
1880                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1881                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1882                         }
1883                         if (is_global_ireg (sregs [0])) {
1884                                 /* The argument is already in a hard reg, need to copy */
1885                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1886                                 insert_before_ins (bb, ins, copy);
1887                                 sregs [0] = dest_sregs [0];
1888                         }
1889                 }
1890
1891                 if (is_soft_reg (sregs [0], bank)) {
1892                         val = rs->vassign [sregs [0]];
1893                         prev_sregs [0] = sregs [0];
1894                         if (val < 0) {
1895                                 int spill = 0;
1896                                 if (val < -1) {
1897                                         /* the register gets spilled after this inst */
1898                                         spill = -val -1;
1899                                 }
1900
1901                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1902                                         /*
1903                                          * Allocate the same hreg to sreg1 as well so the
1904                                          * peephole can get rid of the move.
1905                                          */
1906                                         sreg_masks [0] = regmask (ins->dreg);
1907                                 }
1908
1909                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1910                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1911                                         sreg_masks [0] = regmask (ins->dreg);
1912
1913                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1914                                 assign_reg (cfg, rs, sregs [0], val, bank);
1915                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1916
1917                                 if (spill) {
1918                                         /*
1919                                          * Need to insert before the instruction since it can
1920                                          * overwrite sreg1.
1921                                          */
1922                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1923                                 }
1924                         }
1925                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1926                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1927                                 insert_before_ins (bb, ins, copy);
1928                                 for (j = 1; j < num_sregs; ++j)
1929                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1930                                 val = dest_sregs [0];
1931                         }
1932
1933                         sregs [0] = val;
1934                 }
1935                 else {
1936                         prev_sregs [0] = -1;
1937                 }
1938                 mono_inst_set_src_registers (ins, sregs);
1939
1940                 for (j = 1; j < num_sregs; ++j)
1941                         sreg_masks [j] &= ~(regmask (sregs [0]));
1942
1943                 /* Handle the case when sreg1 is a regpair but dreg is not */
1944                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1945                         int reg2 = prev_sregs [0] + 1;
1946
1947                         g_assert (!bank);
1948                         g_assert (prev_sregs [0] > -1);
1949                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1950                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1951                         val = rs->vassign [reg2];
1952                         if (val < 0) {
1953                                 int spill = 0;
1954                                 if (val < -1) {
1955                                         /* the register gets spilled after this inst */
1956                                         spill = -val -1;
1957                                 }
1958                                 val = mono_regstate_alloc_int (rs, mask);
1959                                 if (val < 0)
1960                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1961                                 if (spill)
1962                                         g_assert_not_reached ();
1963                         }
1964                         else {
1965                                 if (! (mask & (regmask (val)))) {
1966                                         /* The vreg is already allocated to a wrong hreg */
1967                                         /* FIXME: */
1968                                         g_assert_not_reached ();
1969 #if 0
1970                                         val = mono_regstate_alloc_int (rs, mask);
1971                                         if (val < 0)
1972                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1973
1974                                         /* Reallocate hreg to the correct register */
1975                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1976
1977                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1978 #endif
1979                                 }
1980                         }
1981
1982                         sreg1_high = val;
1983                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1984                         assign_reg (cfg, rs, reg2, val, bank);
1985                 }
1986
1987                 /* Handle dreg==sreg1 */
1988                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1989                         MonoInst *sreg2_copy = NULL;
1990                         MonoInst *copy;
1991                         int bank = reg_bank (spec_src1);
1992
1993                         if (ins->dreg == sregs [1]) {
1994                                 /*
1995                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1996                                  * register for it.
1997                                  */
1998                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1999
2000                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2001                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2002                                 prev_sregs [1] = sregs [1] = reg2;
2003
2004                                 if (G_UNLIKELY (bank))
2005                                         mono_regstate_free_general (rs, reg2, bank);
2006                                 else
2007                                         mono_regstate_free_int (rs, reg2);
2008                         }
2009
2010                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2011                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2012                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2013                                         /* FIXME: */
2014                                         g_assert_not_reached ();
2015
2016                                 /*
2017                                  * sreg1 and dest are already allocated to the same regpair by the
2018                                  * SREG1 allocation code.
2019                                  */
2020                                 g_assert (sregs [0] == ins->dreg);
2021                                 g_assert (dreg_high == sreg1_high);
2022                         }
2023
2024                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2025                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2026                         insert_before_ins (bb, ins, copy);
2027
2028                         if (sreg2_copy)
2029                                 insert_before_ins (bb, copy, sreg2_copy);
2030
2031                         /*
2032                          * Need to prevent sreg2 to be allocated to sreg1, since that
2033                          * would screw up the previous copy.
2034                          */
2035                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2036                         /* we set sreg1 to dest as well */
2037                         prev_sregs [0] = sregs [0] = ins->dreg;
2038                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2039                 }
2040                 mono_inst_set_src_registers (ins, sregs);
2041
2042                 /*
2043                  * TRACK SREG2, 3, ...
2044                  */
2045                 for (j = 1; j < num_sregs; ++j) {
2046                         int k;
2047
2048                         bank = sreg_bank (j, spec);
2049                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2050                                 g_assert_not_reached ();
2051
2052                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2053                                 /*
2054                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2055                                  * allocating it to the fixed reg.
2056                                  */
2057                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2058                                 insert_before_ins (bb, ins, copy);
2059                                 sregs [j] = dest_sregs [j];
2060                         } else if (is_soft_reg (sregs [j], bank)) {
2061                                 val = rs->vassign [sregs [j]];
2062
2063                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2064                                         /*
2065                                          * The sreg is already allocated to a hreg, but not to the fixed
2066                                          * reg required by the instruction. Spill the sreg, so it can be
2067                                          * allocated to the fixed reg by the code below.
2068                                          */
2069                                         /* Currently, this code should only be hit for CAS */
2070                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2071                                         val = rs->vassign [sregs [j]];
2072                                 }
2073
2074                                 if (val < 0) {
2075                                         int spill = 0;
2076                                         if (val < -1) {
2077                                                 /* the register gets spilled after this inst */
2078                                                 spill = -val -1;
2079                                         }
2080                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2081                                         assign_reg (cfg, rs, sregs [j], val, bank);
2082                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2083                                         if (spill) {
2084                                                 /*
2085                                                  * Need to insert before the instruction since it can
2086                                                  * overwrite sreg2.
2087                                                  */
2088                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2089                                         }
2090                                 }
2091                                 sregs [j] = val;
2092                                 for (k = j + 1; k < num_sregs; ++k)
2093                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2094                         }
2095                         else {
2096                                 prev_sregs [j] = -1;
2097                         }
2098                 }
2099                 mono_inst_set_src_registers (ins, sregs);
2100
2101                 /* Sanity check */
2102                 /* Do this only for CAS for now */
2103                 for (j = 1; j < num_sregs; ++j) {
2104                         int sreg = sregs [j];
2105                         int dest_sreg = dest_sregs [j];
2106
2107                         if (j == 2 && dest_sreg != -1) {
2108                                 int k;
2109
2110                                 g_assert (sreg == dest_sreg);
2111
2112                                 for (k = 0; k < num_sregs; ++k) {
2113                                         if (k != j)
2114                                                 g_assert (sregs [k] != dest_sreg);
2115                                 }
2116                         }
2117                 }
2118
2119                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2120                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2121                         mono_regstate_free_int (rs, ins->sreg1);
2122                 }
2123                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2124                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2125                         mono_regstate_free_int (rs, ins->sreg2);
2126                 }*/
2127
2128                 DEBUG (mono_print_ins_index (i, ins));
2129         }
2130
2131         // FIXME: Set MAX_FREGS to 8
2132         // FIXME: Optimize generated code
2133 #if MONO_ARCH_USE_FPSTACK
2134         /*
2135          * Make a forward pass over the code, simulating the fp stack, making sure the
2136          * arguments required by the fp opcodes are at the top of the stack.
2137          */
2138         if (has_fp) {
2139                 MonoInst *prev = NULL;
2140                 MonoInst *fxch;
2141                 int tmp;
2142
2143                 g_assert (num_sregs <= 2);
2144
2145                 for (ins = bb->code; ins; ins = ins->next) {
2146                         spec = ins_get_spec (ins->opcode);
2147
2148                         DEBUG (printf ("processing:"));
2149                         DEBUG (mono_print_ins_index (0, ins));
2150
2151                         if (ins->opcode == OP_FMOVE) {
2152                                 /* Do it by renaming the source to the destination on the stack */
2153                                 // FIXME: Is this correct ?
2154                                 for (i = 0; i < sp; ++i)
2155                                         if (fpstack [i] == ins->sreg1)
2156                                                 fpstack [i] = ins->dreg;
2157                                 prev = ins;
2158                                 continue;
2159                         }
2160
2161                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2162                                 /* Arg1 must be in %st(1) */
2163                                 g_assert (prev);
2164
2165                                 i = 0;
2166                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2167                                         i ++;
2168                                 g_assert (i < sp);
2169
2170                                 if (sp - 1 - i > 0) {
2171                                         /* First move it to %st(0) */
2172                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2173
2174                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2175                                         fxch->inst_imm = sp - 1 - i;
2176
2177                                         prev->next = fxch;
2178                                         fxch->next = ins;
2179                                         prev = fxch;
2180
2181                                         tmp = fpstack [sp - 1];
2182                                         fpstack [sp - 1] = fpstack [i];
2183                                         fpstack [i] = tmp;
2184                                 }
2185
2186                                 /* Then move it to %st(1) */
2187                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2188
2189                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2190                                 fxch->inst_imm = 1;
2191
2192                                 prev->next = fxch;
2193                                 fxch->next = ins;
2194                                 prev = fxch;
2195
2196                                 tmp = fpstack [sp - 1];
2197                                 fpstack [sp - 1] = fpstack [sp - 2];
2198                                 fpstack [sp - 2] = tmp;
2199                         }
2200
2201                         if (sreg2_is_fp (spec)) {
2202                                 g_assert (sp > 0);
2203
2204                                 if (fpstack [sp - 1] != ins->sreg2) {
2205                                         g_assert (prev);
2206
2207                                         i = 0;
2208                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2209                                                 i ++;
2210                                         g_assert (i < sp);
2211
2212                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2213
2214                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2215                                         fxch->inst_imm = sp - 1 - i;
2216
2217                                         prev->next = fxch;
2218                                         fxch->next = ins;
2219                                         prev = fxch;
2220
2221                                         tmp = fpstack [sp - 1];
2222                                         fpstack [sp - 1] = fpstack [i];
2223                                         fpstack [i] = tmp;
2224                                 }
2225
2226                                 sp --;
2227                         }
2228
2229                         if (sreg1_is_fp (spec)) {
2230                                 g_assert (sp > 0);
2231
2232                                 if (fpstack [sp - 1] != ins->sreg1) {
2233                                         g_assert (prev);
2234
2235                                         i = 0;
2236                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2237                                                 i ++;
2238                                         g_assert (i < sp);
2239
2240                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2241
2242                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2243                                         fxch->inst_imm = sp - 1 - i;
2244
2245                                         prev->next = fxch;
2246                                         fxch->next = ins;
2247                                         prev = fxch;
2248
2249                                         tmp = fpstack [sp - 1];
2250                                         fpstack [sp - 1] = fpstack [i];
2251                                         fpstack [i] = tmp;
2252                                 }
2253
2254                                 sp --;
2255                         }
2256
2257                         if (dreg_is_fp (spec)) {
2258                                 g_assert (sp < 8);
2259                                 fpstack [sp ++] = ins->dreg;
2260                         }
2261
2262                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2263                                 printf ("\t[");
2264                                 for (i = 0; i < sp; ++i)
2265                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2266                                 printf ("]\n");
2267                         }
2268
2269                         prev = ins;
2270                 }
2271
2272                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2273                         /* Remove remaining items from the fp stack */
2274                         /*
2275                          * These can remain for example as a result of a dead fmove like in
2276                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2277                          */
2278                         while (sp) {
2279                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2280                                 mono_add_ins_to_end (bb, ins);
2281                                 sp --;
2282                         }
2283                 }
2284         }
2285 #endif
2286 }
2287
2288 CompRelation
2289 mono_opcode_to_cond (int opcode)
2290 {
2291         switch (opcode) {
2292         case OP_CEQ:
2293         case OP_IBEQ:
2294         case OP_ICEQ:
2295         case OP_LBEQ:
2296         case OP_LCEQ:
2297         case OP_FBEQ:
2298         case OP_FCEQ:
2299         case OP_COND_EXC_EQ:
2300         case OP_COND_EXC_IEQ:
2301         case OP_CMOV_IEQ:
2302         case OP_CMOV_LEQ:
2303                 return CMP_EQ;
2304         case OP_IBNE_UN:
2305         case OP_LBNE_UN:
2306         case OP_FBNE_UN:
2307         case OP_COND_EXC_NE_UN:
2308         case OP_COND_EXC_INE_UN:
2309         case OP_CMOV_INE_UN:
2310         case OP_CMOV_LNE_UN:
2311                 return CMP_NE;
2312         case OP_IBLE:
2313         case OP_LBLE:
2314         case OP_FBLE:
2315         case OP_CMOV_ILE:
2316         case OP_CMOV_LLE:
2317                 return CMP_LE;
2318         case OP_IBGE:
2319         case OP_LBGE:
2320         case OP_FBGE:
2321         case OP_CMOV_IGE:
2322         case OP_CMOV_LGE:
2323                 return CMP_GE;
2324         case OP_CLT:
2325         case OP_IBLT:
2326         case OP_ICLT:
2327         case OP_LBLT:
2328         case OP_LCLT:
2329         case OP_FBLT:
2330         case OP_FCLT:
2331         case OP_COND_EXC_LT:
2332         case OP_COND_EXC_ILT:
2333         case OP_CMOV_ILT:
2334         case OP_CMOV_LLT:
2335                 return CMP_LT;
2336         case OP_CGT:
2337         case OP_IBGT:
2338         case OP_ICGT:
2339         case OP_LBGT:
2340         case OP_LCGT:
2341         case OP_FBGT:
2342         case OP_FCGT:
2343         case OP_COND_EXC_GT:
2344         case OP_COND_EXC_IGT:
2345         case OP_CMOV_IGT:
2346         case OP_CMOV_LGT:
2347                 return CMP_GT;
2348
2349         case OP_IBLE_UN:
2350         case OP_LBLE_UN:
2351         case OP_FBLE_UN:
2352         case OP_COND_EXC_LE_UN:
2353         case OP_COND_EXC_ILE_UN:
2354         case OP_CMOV_ILE_UN:
2355         case OP_CMOV_LLE_UN:
2356                 return CMP_LE_UN;
2357         case OP_IBGE_UN:
2358         case OP_LBGE_UN:
2359         case OP_FBGE_UN:
2360         case OP_CMOV_IGE_UN:
2361         case OP_CMOV_LGE_UN:
2362                 return CMP_GE_UN;
2363         case OP_CLT_UN:
2364         case OP_IBLT_UN:
2365         case OP_ICLT_UN:
2366         case OP_LBLT_UN:
2367         case OP_LCLT_UN:
2368         case OP_FBLT_UN:
2369         case OP_FCLT_UN:
2370         case OP_COND_EXC_LT_UN:
2371         case OP_COND_EXC_ILT_UN:
2372         case OP_CMOV_ILT_UN:
2373         case OP_CMOV_LLT_UN:
2374                 return CMP_LT_UN;
2375         case OP_CGT_UN:
2376         case OP_IBGT_UN:
2377         case OP_ICGT_UN:
2378         case OP_LBGT_UN:
2379         case OP_LCGT_UN:
2380         case OP_FCGT_UN:
2381         case OP_FBGT_UN:
2382         case OP_COND_EXC_GT_UN:
2383         case OP_COND_EXC_IGT_UN:
2384         case OP_CMOV_IGT_UN:
2385         case OP_CMOV_LGT_UN:
2386                 return CMP_GT_UN;
2387         default:
2388                 printf ("%s\n", mono_inst_name (opcode));
2389                 g_assert_not_reached ();
2390                 return 0;
2391         }
2392 }
2393
2394 CompRelation
2395 mono_negate_cond (CompRelation cond)
2396 {
2397         switch (cond) {
2398         case CMP_EQ:
2399                 return CMP_NE;
2400         case CMP_NE:
2401                 return CMP_EQ;
2402         case CMP_LE:
2403                 return CMP_GT;
2404         case CMP_GE:
2405                 return CMP_LT;
2406         case CMP_LT:
2407                 return CMP_GE;
2408         case CMP_GT:
2409                 return CMP_LE;
2410         case CMP_LE_UN:
2411                 return CMP_GT_UN;
2412         case CMP_GE_UN:
2413                 return CMP_LT_UN;
2414         case CMP_LT_UN:
2415                 return CMP_GE_UN;
2416         case CMP_GT_UN:
2417                 return CMP_LE_UN;
2418         default:
2419                 g_assert_not_reached ();
2420         }
2421 }
2422
2423 CompType
2424 mono_opcode_to_type (int opcode, int cmp_opcode)
2425 {
2426         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2427                 return CMP_TYPE_L;
2428         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2429                 return CMP_TYPE_I;
2430         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2431                 return CMP_TYPE_I;
2432         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2433                 return CMP_TYPE_L;
2434         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2435                 return CMP_TYPE_L;
2436         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2437                 return CMP_TYPE_F;
2438         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2439                 return CMP_TYPE_F;
2440         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2441                 return CMP_TYPE_I;
2442         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2443                 switch (cmp_opcode) {
2444                 case OP_ICOMPARE:
2445                 case OP_ICOMPARE_IMM:
2446                         return CMP_TYPE_I;
2447                 default:
2448                         return CMP_TYPE_L;
2449                 }
2450         } else {
2451                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2452                 return 0;
2453         }
2454 }
2455
2456 #endif /* DISABLE_JIT */
2457
2458 gboolean
2459 mono_is_regsize_var (MonoType *t)
2460 {
2461         if (t->byref)
2462                 return TRUE;
2463         t = mono_type_get_underlying_type (t);
2464         switch (t->type) {
2465         case MONO_TYPE_BOOLEAN:
2466         case MONO_TYPE_CHAR:
2467         case MONO_TYPE_I1:
2468         case MONO_TYPE_U1:
2469         case MONO_TYPE_I2:
2470         case MONO_TYPE_U2:
2471         case MONO_TYPE_I4:
2472         case MONO_TYPE_U4:
2473         case MONO_TYPE_I:
2474         case MONO_TYPE_U:
2475         case MONO_TYPE_PTR:
2476         case MONO_TYPE_FNPTR:
2477 #if SIZEOF_REGISTER == 8
2478         case MONO_TYPE_I8:
2479         case MONO_TYPE_U8:
2480 #endif
2481                 return TRUE;
2482         case MONO_TYPE_OBJECT:
2483         case MONO_TYPE_STRING:
2484         case MONO_TYPE_CLASS:
2485         case MONO_TYPE_SZARRAY:
2486         case MONO_TYPE_ARRAY:
2487                 return TRUE;
2488         case MONO_TYPE_GENERICINST:
2489                 if (!mono_type_generic_inst_is_valuetype (t))
2490                         return TRUE;
2491                 return FALSE;
2492         case MONO_TYPE_VALUETYPE:
2493                 return FALSE;
2494         default:
2495                 return FALSE;
2496         }
2497 }
2498
2499 #ifndef DISABLE_JIT
2500
2501 /*
2502  * mono_peephole_ins:
2503  *
2504  *   Perform some architecture independent peephole optimizations.
2505  */
2506 void
2507 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2508 {
2509         MonoInst *last_ins = ins->prev;
2510
2511         switch (ins->opcode) {
2512         case OP_MUL_IMM:
2513                 /* remove unnecessary multiplication with 1 */
2514                 if (ins->inst_imm == 1) {
2515                         if (ins->dreg != ins->sreg1)
2516                                 ins->opcode = OP_MOVE;
2517                         else
2518                                 MONO_DELETE_INS (bb, ins);
2519                 }
2520                 break;
2521         case OP_LOAD_MEMBASE:
2522         case OP_LOADI4_MEMBASE:
2523                 /*
2524                  * Note: if reg1 = reg2 the load op is removed
2525                  *
2526                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2527                  * OP_LOAD_MEMBASE offset(basereg), reg2
2528                  * -->
2529                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2530                  * OP_MOVE reg1, reg2
2531                  */
2532                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2533                         last_ins = last_ins->prev;
2534                 if (last_ins &&
2535                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2536                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2537                         ins->inst_basereg == last_ins->inst_destbasereg &&
2538                         ins->inst_offset == last_ins->inst_offset) {
2539                         if (ins->dreg == last_ins->sreg1) {
2540                                 MONO_DELETE_INS (bb, ins);
2541                                 break;
2542                         } else {
2543                                 ins->opcode = OP_MOVE;
2544                                 ins->sreg1 = last_ins->sreg1;
2545                         }
2546
2547                         /*
2548                          * Note: reg1 must be different from the basereg in the second load
2549                          * Note: if reg1 = reg2 is equal then second load is removed
2550                          *
2551                          * OP_LOAD_MEMBASE offset(basereg), reg1
2552                          * OP_LOAD_MEMBASE offset(basereg), reg2
2553                          * -->
2554                          * OP_LOAD_MEMBASE offset(basereg), reg1
2555                          * OP_MOVE reg1, reg2
2556                          */
2557                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2558                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2559                           ins->inst_basereg != last_ins->dreg &&
2560                           ins->inst_basereg == last_ins->inst_basereg &&
2561                           ins->inst_offset == last_ins->inst_offset) {
2562
2563                         if (ins->dreg == last_ins->dreg) {
2564                                 MONO_DELETE_INS (bb, ins);
2565                         } else {
2566                                 ins->opcode = OP_MOVE;
2567                                 ins->sreg1 = last_ins->dreg;
2568                         }
2569
2570                         //g_assert_not_reached ();
2571
2572 #if 0
2573                         /*
2574                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2575                          * OP_LOAD_MEMBASE offset(basereg), reg
2576                          * -->
2577                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2578                          * OP_ICONST reg, imm
2579                          */
2580                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2581                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2582                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2583                                    ins->inst_offset == last_ins->inst_offset) {
2584                         ins->opcode = OP_ICONST;
2585                         ins->inst_c0 = last_ins->inst_imm;
2586                         g_assert_not_reached (); // check this rule
2587 #endif
2588                 }
2589                 break;
2590         case OP_LOADI1_MEMBASE:
2591         case OP_LOADU1_MEMBASE:
2592                 /*
2593                  * Note: if reg1 = reg2 the load op is removed
2594                  *
2595                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2596                  * OP_LOAD_MEMBASE offset(basereg), reg2
2597                  * -->
2598                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2599                  * OP_MOVE reg1, reg2
2600                  */
2601                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2602                         ins->inst_basereg == last_ins->inst_destbasereg &&
2603                         ins->inst_offset == last_ins->inst_offset) {
2604                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2605                         ins->sreg1 = last_ins->sreg1;
2606                 }
2607                 break;
2608         case OP_LOADI2_MEMBASE:
2609         case OP_LOADU2_MEMBASE:
2610                 /*
2611                  * Note: if reg1 = reg2 the load op is removed
2612                  *
2613                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2614                  * OP_LOAD_MEMBASE offset(basereg), reg2
2615                  * -->
2616                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2617                  * OP_MOVE reg1, reg2
2618                  */
2619                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2620                         ins->inst_basereg == last_ins->inst_destbasereg &&
2621                         ins->inst_offset == last_ins->inst_offset) {
2622 #if SIZEOF_REGISTER == 8
2623                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2624 #else
2625                         /* The definition of OP_PCONV_TO_U2 is wrong */
2626                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2627 #endif
2628                         ins->sreg1 = last_ins->sreg1;
2629                 }
2630                 break;
2631         case OP_MOVE:
2632         case OP_FMOVE:
2633                 /*
2634                  * Removes:
2635                  *
2636                  * OP_MOVE reg, reg
2637                  */
2638                 if (ins->dreg == ins->sreg1) {
2639                         MONO_DELETE_INS (bb, ins);
2640                         break;
2641                 }
2642                 /*
2643                  * Removes:
2644                  *
2645                  * OP_MOVE sreg, dreg
2646                  * OP_MOVE dreg, sreg
2647                  */
2648                 if (last_ins && last_ins->opcode == ins->opcode &&
2649                         ins->sreg1 == last_ins->dreg &&
2650                         ins->dreg == last_ins->sreg1) {
2651                         MONO_DELETE_INS (bb, ins);
2652                 }
2653                 break;
2654         case OP_NOP:
2655                 MONO_DELETE_INS (bb, ins);
2656                 break;
2657         }
2658 }
2659
2660 #endif /* DISABLE_JIT */