mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         case MONO_PATCH_INFO_INTERNAL_METHOD: {
 441                 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
 442                 break;
 443         }
 444         default:
 445                 printf ("[%s]", patch_info_str [ji->type]);
 446                 break;
 447         }
 448 }
 449
 450 void
 451 mono_print_ins_index (int i, MonoInst *ins)
 452 {
 453         const char *spec = ins_get_spec (ins->opcode);
 454         int num_sregs, j;
 455         int sregs [MONO_MAX_SRC_REGS];
 456
 457         if (i != -1)
 458                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 459         else
 460                 printf (" %s", mono_inst_name (ins->opcode));
 461         if (spec == MONO_ARCH_CPU_SPEC) {
 462                 gboolean dest_base = FALSE;
 463                 switch (ins->opcode) {
 464                 case OP_STOREV_MEMBASE:
 465                         dest_base = TRUE;
 466                         break;
 467                 default:
 468                         break;
 469                 }
 470
 471                 /* This is a lowered opcode */
 472                 if (ins->dreg != -1) {
 473                         if (dest_base)
 474                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 475                         else
 476                                 printf (" R%d <-", ins->dreg);
 477                 }
 478                 if (ins->sreg1 != -1)
 479                         printf (" R%d", ins->sreg1);
 480                 if (ins->sreg2 != -1)
 481                         printf (" R%d", ins->sreg2);
 482                 if (ins->sreg3 != -1)
 483                         printf (" R%d", ins->sreg3);
 484
 485                 switch (ins->opcode) {
 486                 case OP_LBNE_UN:
 487                 case OP_LBEQ:
 488                 case OP_LBLT:
 489                 case OP_LBLT_UN:
 490                 case OP_LBGT:
 491                 case OP_LBGT_UN:
 492                 case OP_LBGE:
 493                 case OP_LBGE_UN:
 494                 case OP_LBLE:
 495                 case OP_LBLE_UN:
 496                         if (!ins->inst_false_bb)
 497                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 498                         else
 499                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 500                         break;
 501                 case OP_PHI:
 502                 case OP_VPHI:
 503                 case OP_XPHI:
 504                 case OP_FPHI: {
 505                         int i;
 506                         printf (" [%d (", (int)ins->inst_c0);
 507                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 508                                 if (i)
 509                                         printf (", ");
 510                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 511                         }
 512                         printf (")]");
 513                         break;
 514                 }
 515                 case OP_LDADDR:
 516                 case OP_OUTARG_VTRETADDR:
 517                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 518                         break;
 519                 case OP_REGOFFSET:
 520                 case OP_GSHAREDVT_ARG_REGOFFSET:
 521                         printf (" + 0x%lx", (long)ins->inst_offset);
 522                         break;
 523                 default:
 524                         break;
 525                 }
 526
 527                 printf ("\n");
 528                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 529                 return;
 530         }
 531
 532         if (spec [MONO_INST_DEST]) {
 533                 int bank = dreg_bank (spec);
 534                 if (is_soft_reg (ins->dreg, bank)) {
 535                         if (spec [MONO_INST_DEST] == 'b') {
 536                                 if (ins->inst_offset == 0)
 537                                         printf (" [R%d] <-", ins->dreg);
 538                                 else
 539                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 540                         }
 541                         else
 542                                 printf (" R%d <-", ins->dreg);
 543                 } else if (spec [MONO_INST_DEST] == 'b') {
 544                         if (ins->inst_offset == 0)
 545                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 546                         else
 547                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 548                 } else
 549                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 550         }
 551         if (spec [MONO_INST_SRC1]) {
 552                 int bank = sreg1_bank (spec);
 553                 if (is_soft_reg (ins->sreg1, bank)) {
 554                         if (spec [MONO_INST_SRC1] == 'b')
 555                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 556                         else
 557                                 printf (" R%d", ins->sreg1);
 558                 } else if (spec [MONO_INST_SRC1] == 'b')
 559                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 560                 else
 561                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 562         }
 563         num_sregs = mono_inst_get_src_registers (ins, sregs);
 564         for (j = 1; j < num_sregs; ++j) {
 565                 int bank = sreg_bank (j, spec);
 566                 if (is_soft_reg (sregs [j], bank))
 567                         printf (" R%d", sregs [j]);
 568                 else
 569                         printf (" %s", mono_regname_full (sregs [j], bank));
 570         }
 571
 572         switch (ins->opcode) {
 573         case OP_ICONST:
 574                 printf (" [%d]", (int)ins->inst_c0);
 575                 break;
 576 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 577         case OP_X86_PUSH_IMM:
 578 #endif
 579         case OP_ICOMPARE_IMM:
 580         case OP_COMPARE_IMM:
 581         case OP_IADD_IMM:
 582         case OP_ISUB_IMM:
 583         case OP_IAND_IMM:
 584         case OP_IOR_IMM:
 585         case OP_IXOR_IMM:
 586         case OP_SUB_IMM:
 587         case OP_STORE_MEMBASE_IMM:
 588                 printf (" [%d]", (int)ins->inst_imm);
 589                 break;
 590         case OP_ADD_IMM:
 591         case OP_LADD_IMM:
 592                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 593                 break;
 594         case OP_I8CONST:
 595                 printf (" [%lld]", (long long)ins->inst_l);
 596                 break;
 597         case OP_R8CONST:
 598                 printf (" [%f]", *(double*)ins->inst_p0);
 599                 break;
 600         case OP_R4CONST:
 601                 printf (" [%f]", *(float*)ins->inst_p0);
 602                 break;
 603         case OP_CALL:
 604         case OP_CALL_MEMBASE:
 605         case OP_CALL_REG:
 606         case OP_FCALL:
 607         case OP_LCALL:
 608         case OP_VCALL:
 609         case OP_VCALL_REG:
 610         case OP_VCALL_MEMBASE:
 611         case OP_VCALL2:
 612         case OP_VCALL2_REG:
 613         case OP_VCALL2_MEMBASE:
 614         case OP_VOIDCALL:
 615         case OP_VOIDCALL_MEMBASE:
 616         case OP_TAILCALL: {
 617                 MonoCallInst *call = (MonoCallInst*)ins;
 618                 GSList *list;
 619
 620                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 621                         /*
 622                          * These are lowered opcodes, but they are in the .md files since the old
 623                          * JIT passes them to backends.
 624                          */
 625                         if (ins->dreg != -1)
 626                                 printf (" R%d <-", ins->dreg);
 627                 }
 628
 629                 if (call->method) {
 630                         char *full_name = mono_method_full_name (call->method, TRUE);
 631                         printf (" [%s]", full_name);
 632                         g_free (full_name);
 633                 } else if (call->fptr_is_patch) {
 634                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 635
 636                         printf (" ");
 637                         mono_print_ji (ji);
 638                 } else if (call->fptr) {
 639                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 640                         if (info)
 641                                 printf (" [%s]", info->name);
 642                 }
 643
 644                 list = call->out_ireg_args;
 645                 while (list) {
 646                         guint32 regpair;
 647                         int reg, hreg;
 648
 649                         regpair = (guint32)(gssize)(list->data);
 650                         hreg = regpair >> 24;
 651                         reg = regpair & 0xffffff;
 652
 653                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 654
 655                         list = g_slist_next (list);
 656                 }
 657                 list = call->out_freg_args;
 658                 while (list) {
 659                         guint32 regpair;
 660                         int reg, hreg;
 661
 662                         regpair = (guint32)(gssize)(list->data);
 663                         hreg = regpair >> 24;
 664                         reg = regpair & 0xffffff;
 665
 666                         printf (" [%s <- R%d]", mono_arch_fregname (hreg), reg);
 667
 668                         list = g_slist_next (list);
 669                 }
 670                 break;
 671         }
 672         case OP_BR:
 673         case OP_CALL_HANDLER:
 674                 printf (" [B%d]", ins->inst_target_bb->block_num);
 675                 break;
 676         case OP_IBNE_UN:
 677         case OP_IBEQ:
 678         case OP_IBLT:
 679         case OP_IBLT_UN:
 680         case OP_IBGT:
 681         case OP_IBGT_UN:
 682         case OP_IBGE:
 683         case OP_IBGE_UN:
 684         case OP_IBLE:
 685         case OP_IBLE_UN:
 686         case OP_LBNE_UN:
 687         case OP_LBEQ:
 688         case OP_LBLT:
 689         case OP_LBLT_UN:
 690         case OP_LBGT:
 691         case OP_LBGT_UN:
 692         case OP_LBGE:
 693         case OP_LBGE_UN:
 694         case OP_LBLE:
 695         case OP_LBLE_UN:
 696                 if (!ins->inst_false_bb)
 697                         printf (" [B%d]", ins->inst_true_bb->block_num);
 698                 else
 699                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 700                 break;
 701         case OP_LIVERANGE_START:
 702         case OP_LIVERANGE_END:
 703         case OP_GC_LIVENESS_DEF:
 704         case OP_GC_LIVENESS_USE:
 705                 printf (" R%d", (int)ins->inst_c1);
 706                 break;
 707         case OP_IL_SEQ_POINT:
 708         case OP_SEQ_POINT:
 709                 printf (" il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 710                 break;
 711         default:
 712                 break;
 713         }
 714
 715         if (spec [MONO_INST_CLOB])
 716                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 717         printf ("\n");
 718 }
 719
 720 static void
 721 print_regtrack (RegTrack *t, int num)
 722 {
 723         int i;
 724         char buf [32];
 725         const char *r;
 726
 727         for (i = 0; i < num; ++i) {
 728                 if (!t [i].born_in)
 729                         continue;
 730                 if (i >= MONO_MAX_IREGS) {
 731                         g_snprintf (buf, sizeof(buf), "R%d", i);
 732                         r = buf;
 733                 } else
 734                         r = mono_arch_regname (i);
 735                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 736         }
 737 }
 738 #else
 739
 740 void
 741 mono_print_ji (const MonoJumpInfo *ji)
 742 {
 743 }
 744
 745 void
 746 mono_print_ins_index (int i, MonoInst *ins)
 747 {
 748 }
 749 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 750
 751 void
 752 mono_print_ins (MonoInst *ins)
 753 {
 754         mono_print_ins_index (-1, ins);
 755 }
 756
 757 static inline void
 758 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 759 {
 760         /*
 761          * If this function is called multiple times, the new instructions are inserted
 762          * in the proper order.
 763          */
 764         mono_bblock_insert_before_ins (bb, ins, to_insert);
 765 }
 766
 767 static inline void
 768 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 769 {
 770         /*
 771          * If this function is called multiple times, the new instructions are inserted in
 772          * proper order.
 773          */
 774         mono_bblock_insert_after_ins (bb, *last, to_insert);
 775
 776         *last = to_insert;
 777 }
 778
 779 static inline int
 780 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 781 {
 782         if (vreg_is_ref (cfg, reg))
 783                 return MONO_REG_INT_REF;
 784         else if (vreg_is_mp (cfg, reg))
 785                 return MONO_REG_INT_MP;
 786         else
 787                 return bank;
 788 }
 789
 790 /*
 791  * Force the spilling of the variable in the symbolic register 'reg', and free
 792  * the hreg it was assigned to.
 793  */
 794 static void
 795 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 796 {
 797         MonoInst *load;
 798         int i, sel, spill;
 799         MonoRegState *rs = cfg->rs;
 800
 801         sel = rs->vassign [reg];
 802
 803         /* the vreg we need to spill lives in another logical reg bank */
 804         bank = translate_bank (cfg->rs, bank, sel);
 805
 806         /*i = rs->isymbolic [sel];
 807         g_assert (i == reg);*/
 808         i = reg;
 809         spill = ++cfg->spill_count;
 810         rs->vassign [i] = -spill - 1;
 811         if (G_UNLIKELY (bank))
 812                 mono_regstate_free_general (rs, sel, bank);
 813         else
 814                 mono_regstate_free_int (rs, sel);
 815         /* we need to create a spill var and insert a load to sel after the current instruction */
 816         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 817         load->dreg = sel;
 818         load->inst_basereg = cfg->frame_reg;
 819         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 820         insert_after_ins (bb, ins, last, load);
 821         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 822         if (G_UNLIKELY (bank))
 823                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 824         else
 825                 i = mono_regstate_alloc_int (rs, regmask (sel));
 826         g_assert (i == sel);
 827
 828         if (G_UNLIKELY (bank))
 829                 mono_regstate_free_general (rs, sel, bank);
 830         else
 831                 mono_regstate_free_int (rs, sel);
 832 }
 833
 834 /* This isn't defined on older glib versions and on some platforms */
 835 #ifndef G_GUINT64_FORMAT
 836 #define G_GUINT64_FORMAT "ul"
 837 #endif
 838
 839 static int
 840 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 841 {
 842         MonoInst *load;
 843         int i, sel, spill, num_sregs;
 844         int sregs [MONO_MAX_SRC_REGS];
 845         MonoRegState *rs = cfg->rs;
 846
 847         g_assert (bank < MONO_NUM_REGBANKS);
 848
 849         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 850         /* exclude the registers in the current instruction */
 851         num_sregs = mono_inst_get_src_registers (ins, sregs);
 852         for (i = 0; i < num_sregs; ++i) {
 853                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 854                         if (is_soft_reg (sregs [i], bank))
 855                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 856                         else
 857                                 regmask &= ~ (regmask (sregs [i]));
 858                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 859                 }
 860         }
 861         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 862                 regmask &= ~ (regmask (ins->dreg));
 863                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 864         }
 865
 866         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 867         g_assert (regmask); /* need at least a register we can free */
 868         sel = 0;
 869         /* we should track prev_use and spill the register that's farther */
 870         if (G_UNLIKELY (bank)) {
 871                 for (i = 0; i < regbank_size [bank]; ++i) {
 872                         if (regmask & (regmask (i))) {
 873                                 sel = i;
 874
 875                                 /* the vreg we need to load lives in another logical bank */
 876                                 bank = translate_bank (cfg->rs, bank, sel);
 877
 878                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 879                                 break;
 880                         }
 881                 }
 882
 883                 i = rs->symbolic [bank] [sel];
 884                 spill = ++cfg->spill_count;
 885                 rs->vassign [i] = -spill - 1;
 886                 mono_regstate_free_general (rs, sel, bank);
 887         }
 888         else {
 889                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 890                         if (regmask & (regmask (i))) {
 891                                 sel = i;
 892                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 893                                 break;
 894                         }
 895                 }
 896
 897                 i = rs->isymbolic [sel];
 898                 spill = ++cfg->spill_count;
 899                 rs->vassign [i] = -spill - 1;
 900                 mono_regstate_free_int (rs, sel);
 901         }
 902
 903         /* we need to create a spill var and insert a load to sel after the current instruction */
 904         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 905         load->dreg = sel;
 906         load->inst_basereg = cfg->frame_reg;
 907         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 908         insert_after_ins (bb, ins, last, load);
 909         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 910         if (G_UNLIKELY (bank))
 911                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 912         else
 913                 i = mono_regstate_alloc_int (rs, regmask (sel));
 914         g_assert (i == sel);
 915
 916         return sel;
 917 }
 918
 919 /*
 920  * free_up_hreg:
 921  *
 922  *   Free up the hreg HREG by spilling the vreg allocated to it.
 923  */
 924 static void
 925 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 926 {
 927         if (G_UNLIKELY (bank)) {
 928                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 929                         bank = translate_bank (cfg->rs, bank, hreg);
 930                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 931                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 932                 }
 933         }
 934         else {
 935                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 936                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 937                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 938                 }
 939         }
 940 }
 941
 942 static MonoInst*
 943 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 944 {
 945         MonoInst *copy;
 946
 947         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 948
 949         copy->dreg = dest;
 950         copy->sreg1 = src;
 951         copy->cil_code = ip;
 952         if (ins) {
 953                 mono_bblock_insert_after_ins (bb, ins, copy);
 954                 *last = copy;
 955         }
 956         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 957         return copy;
 958 }
 959
 960 static inline const char*
 961 regbank_to_string (int bank)
 962 {
 963         if (bank == MONO_REG_INT_REF)
 964                 return "REF ";
 965         else if (bank == MONO_REG_INT_MP)
 966                 return "MP ";
 967         else
 968                 return "";
 969 }
 970
 971 static void
 972 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 973 {
 974         MonoInst *store, *def;
 975
 976         bank = get_vreg_bank (cfg, prev_reg, bank);
 977
 978         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 979         store->sreg1 = reg;
 980         store->inst_destbasereg = cfg->frame_reg;
 981         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 982         if (ins) {
 983                 mono_bblock_insert_after_ins (bb, ins, store);
 984                 *last = store;
 985         } else if (insert_before) {
 986                 insert_before_ins (bb, insert_before, store);
 987         } else {
 988                 g_assert_not_reached ();
 989         }
 990         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 991
 992         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 993                 g_assert (prev_reg != -1);
 994                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 995                 def->inst_c0 = spill;
 996                 def->inst_c1 = bank;
 997                 mono_bblock_insert_after_ins (bb, store, def);
 998         }
 999 }
1000
1001 /* flags used in reginfo->flags */
1002 enum {
1003         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1004         MONO_FP_NEEDS_SPILL                     = regmask (1),
1005         MONO_FP_NEEDS_LOAD                      = regmask (2)
1006 };
1007
1008 static inline int
1009 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1010 {
1011         int val;
1012
1013         if (info && info->preferred_mask) {
1014                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1015                 if (val >= 0) {
1016                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1017                         return val;
1018                 }
1019         }
1020
1021         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1022         if (val < 0)
1023                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1024
1025         return val;
1026 }
1027
1028 static inline int
1029 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1030 {
1031         int val;
1032
1033         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1034
1035         if (val < 0)
1036                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1037
1038         return val;
1039 }
1040
1041 static inline int
1042 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1043 {
1044         if (G_UNLIKELY (bank))
1045                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1046         else
1047                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1048 }
1049
1050 static inline void
1051 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1052 {
1053         if (G_UNLIKELY (bank)) {
1054                 int mirrored_bank;
1055
1056                 g_assert (reg >= regbank_size [bank]);
1057                 g_assert (hreg < regbank_size [bank]);
1058                 g_assert (! is_global_freg (hreg));
1059
1060                 rs->vassign [reg] = hreg;
1061                 rs->symbolic [bank] [hreg] = reg;
1062                 rs->free_mask [bank] &= ~ (regmask (hreg));
1063
1064                 mirrored_bank = get_mirrored_bank (bank);
1065                 if (mirrored_bank == -1)
1066                         return;
1067
1068                 /* Make sure the other logical reg bank that this bank shares
1069                  * a single hard reg bank knows that this hard reg is not free.
1070                  */
1071                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1072
1073                 /* Mark the other logical bank that the this bank shares
1074                  * a single hard reg bank with as mirrored.
1075                  */
1076                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1077
1078         }
1079         else {
1080                 g_assert (reg >= MONO_MAX_IREGS);
1081                 g_assert (hreg < MONO_MAX_IREGS);
1082 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1083                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1084                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1085                 g_assert (! is_global_ireg (hreg));
1086 #endif
1087
1088                 rs->vassign [reg] = hreg;
1089                 rs->isymbolic [hreg] = reg;
1090                 rs->ifree_mask &= ~ (regmask (hreg));
1091         }
1092 }
1093
1094 static inline regmask_t
1095 get_callee_mask (const char spec)
1096 {
1097         if (G_UNLIKELY (reg_bank (spec)))
1098                 return regbank_callee_regs [reg_bank (spec)];
1099         return MONO_ARCH_CALLEE_REGS;
1100 }
1101
1102 static gint8 desc_to_fixed_reg [256];
1103 static gboolean desc_to_fixed_reg_inited = FALSE;
1104
1105 #ifndef DISABLE_JIT
1106
1107 /*
1108  * Local register allocation.
1109  * We first scan the list of instructions and we save the liveness info of
1110  * each register (when the register is first used, when it's value is set etc.).
1111  * We also reverse the list of instructions because assigning registers backwards allows
1112  * for more tricks to be used.
1113  */
1114 void
1115 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1116 {
1117         MonoInst *ins, *prev, *last;
1118         MonoInst **tmp;
1119         MonoRegState *rs = cfg->rs;
1120         int i, j, val, max;
1121         RegTrack *reginfo;
1122         const char *spec;
1123         unsigned char spec_src1, spec_dest;
1124         int bank = 0;
1125 #if MONO_ARCH_USE_FPSTACK
1126         gboolean has_fp = FALSE;
1127         int fpstack [8];
1128         int sp = 0;
1129 #endif
1130         int num_sregs = 0;
1131         int sregs [MONO_MAX_SRC_REGS];
1132
1133         if (!bb->code)
1134                 return;
1135
1136         if (!desc_to_fixed_reg_inited) {
1137                 for (i = 0; i < 256; ++i)
1138                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1139                 desc_to_fixed_reg_inited = TRUE;
1140
1141                 /* Validate the cpu description against the info in mini-ops.h */
1142 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1143                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1144                         const char *ispec;
1145
1146                         spec = ins_get_spec (i);
1147                         ispec = INS_INFO (i);
1148
1149                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1150                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1151                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1152                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1153                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1154                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1155                 }
1156 #endif
1157         }
1158
1159         rs->next_vreg = bb->max_vreg;
1160         mono_regstate_assign (rs);
1161
1162         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1163         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1164                 rs->free_mask [i] = regbank_callee_regs [i];
1165
1166         max = rs->next_vreg;
1167
1168         if (cfg->reginfo && cfg->reginfo_len < max)
1169                 cfg->reginfo = NULL;
1170
1171         reginfo = cfg->reginfo;
1172         if (!reginfo) {
1173                 cfg->reginfo_len = MAX (1024, max * 2);
1174                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1175         }
1176         else
1177                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1178
1179         if (cfg->verbose_level > 1) {
1180                 /* print_regtrack reads the info of all variables */
1181                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1182         }
1183
1184         /*
1185          * For large methods, next_vreg can be very large, so g_malloc0 time can
1186          * be prohibitive. So we manually init the reginfo entries used by the
1187          * bblock.
1188          */
1189         for (ins = bb->code; ins; ins = ins->next) {
1190                 gboolean modify = FALSE;
1191
1192                 spec = ins_get_spec (ins->opcode);
1193
1194                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1195                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1196 #if SIZEOF_REGISTER == 4
1197                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1198                                 /**
1199                                  * In the new IR, the two vregs of the regpair do not alias the
1200                                  * original long vreg. shift the vreg here so the rest of the
1201                                  * allocator doesn't have to care about it.
1202                                  */
1203                                 ins->dreg ++;
1204                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1205                         }
1206 #endif
1207                 }
1208
1209                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1210                 for (j = 0; j < num_sregs; ++j) {
1211                         g_assert (sregs [j] != -1);
1212                         if (sregs [j] < max) {
1213                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1214 #if SIZEOF_REGISTER == 4
1215                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1216                                         sregs [j]++;
1217                                         modify = TRUE;
1218                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1219                                 }
1220 #endif
1221                         }
1222                 }
1223                 if (modify)
1224                         mono_inst_set_src_registers (ins, sregs);
1225         }
1226
1227         /*if (cfg->opt & MONO_OPT_COPYPROP)
1228                 local_copy_prop (cfg, ins);*/
1229
1230         i = 1;
1231         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1232         /* forward pass on the instructions to collect register liveness info */
1233         MONO_BB_FOR_EACH_INS (bb, ins) {
1234                 spec = ins_get_spec (ins->opcode);
1235                 spec_dest = spec [MONO_INST_DEST];
1236
1237                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1238                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1239                 }
1240
1241                 DEBUG (mono_print_ins_index (i, ins));
1242
1243                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1244
1245 #if MONO_ARCH_USE_FPSTACK
1246                 if (dreg_is_fp (spec)) {
1247                         has_fp = TRUE;
1248                 } else {
1249                         for (j = 0; j < num_sregs; ++j) {
1250                                 if (sreg_is_fp (j, spec))
1251                                         has_fp = TRUE;
1252                         }
1253                 }
1254 #endif
1255
1256                 for (j = 0; j < num_sregs; ++j) {
1257                         int sreg = sregs [j];
1258                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1259                         if (sreg_spec) {
1260                                 bank = sreg_bank (j, spec);
1261                                 g_assert (sreg != -1);
1262                                 if (is_soft_reg (sreg, bank))
1263                                         /* This means the vreg is not local to this bb */
1264                                         g_assert (reginfo [sreg].born_in > 0);
1265                                 rs->vassign [sreg] = -1;
1266                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1267                                 //reginfo [ins->sreg2].last_use = i;
1268                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1269                                         /* The virtual register is allocated sequentially */
1270                                         rs->vassign [sreg + 1] = -1;
1271                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1272                                         //reginfo [ins->sreg2 + 1].last_use = i;
1273                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1274                                                 reginfo [sreg + 1].born_in = i;
1275                                 }
1276                         } else {
1277                                 sregs [j] = -1;
1278                         }
1279                 }
1280                 mono_inst_set_src_registers (ins, sregs);
1281
1282                 if (spec_dest) {
1283                         int dest_dreg;
1284
1285                         bank = dreg_bank (spec);
1286                         if (spec_dest != 'b') /* it's not just a base register */
1287                                 reginfo [ins->dreg].killed_in = i;
1288                         g_assert (ins->dreg != -1);
1289                         rs->vassign [ins->dreg] = -1;
1290                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1291                         //reginfo [ins->dreg].last_use = i;
1292                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1293                                 reginfo [ins->dreg].born_in = i;
1294
1295                         dest_dreg = desc_to_fixed_reg [spec_dest];
1296                         if (dest_dreg != -1)
1297                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1298
1299 #ifdef MONO_ARCH_INST_FIXED_MASK
1300                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1301 #endif
1302
1303                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1304                                 /* The virtual register is allocated sequentially */
1305                                 rs->vassign [ins->dreg + 1] = -1;
1306                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1307                                 //reginfo [ins->dreg + 1].last_use = i;
1308                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1309                                         reginfo [ins->dreg + 1].born_in = i;
1310                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1311                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1312                         }
1313                 } else {
1314                         ins->dreg = -1;
1315                 }
1316
1317                 ++i;
1318         }
1319
1320         tmp = &last;
1321
1322         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1323         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1324                 int prev_dreg;
1325                 int dest_dreg, clob_reg;
1326                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1327                 int dreg_high, sreg1_high;
1328                 regmask_t dreg_mask, mask;
1329                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1330                 regmask_t dreg_fixed_mask;
1331                 const unsigned char *ip;
1332                 --i;
1333                 spec = ins_get_spec (ins->opcode);
1334                 spec_src1 = spec [MONO_INST_SRC1];
1335                 spec_dest = spec [MONO_INST_DEST];
1336                 prev_dreg = -1;
1337                 clob_reg = -1;
1338                 dest_dreg = -1;
1339                 dreg_high = -1;
1340                 sreg1_high = -1;
1341                 dreg_mask = get_callee_mask (spec_dest);
1342                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1343                         prev_sregs [j] = -1;
1344                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1345                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1346 #ifdef MONO_ARCH_INST_FIXED_MASK
1347                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1348 #else
1349                         sreg_fixed_masks [j] = 0;
1350 #endif
1351                 }
1352
1353                 DEBUG (printf ("processing:"));
1354                 DEBUG (mono_print_ins_index (i, ins));
1355
1356                 ip = ins->cil_code;
1357
1358                 last = ins;
1359
1360                 /*
1361                  * FIXED REGS
1362                  */
1363                 dest_dreg = desc_to_fixed_reg [spec_dest];
1364                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1365                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1366
1367 #ifdef MONO_ARCH_INST_FIXED_MASK
1368                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1369 #else
1370                 dreg_fixed_mask = 0;
1371 #endif
1372
1373                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1374
1375                 /*
1376                  * TRACK FIXED SREG2, 3, ...
1377                  */
1378                 for (j = 1; j < num_sregs; ++j) {
1379                         int sreg = sregs [j];
1380                         int dest_sreg = dest_sregs [j];
1381
1382                         if (dest_sreg == -1)
1383                                 continue;
1384
1385                         if (j == 2) {
1386                                 int k;
1387
1388                                 /*
1389                                  * CAS.
1390                                  * We need to special case this, since on x86, there are only 3
1391                                  * free registers, and the code below assigns one of them to
1392                                  * sreg, so we can run out of registers when trying to assign
1393                                  * dreg. Instead, we just set up the register masks, and let the
1394                                  * normal sreg2 assignment code handle this. It would be nice to
1395                                  * do this for all the fixed reg cases too, but there is too much
1396                                  * risk of breakage.
1397                                  */
1398
1399                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1400                                 sreg_masks [j] = regmask (dest_sreg);
1401                                 for (k = 0; k < num_sregs; ++k) {
1402                                         if (k != j)
1403                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1404                                 }
1405
1406                                 /*
1407                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1408                                  */
1409                                 for (k = 0; k < num_sregs; ++k) {
1410                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1411                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1412                                 }
1413
1414                                 /*
1415                                  * We can also run out of registers while processing sreg2 if sreg3 is
1416                                  * assigned to another hreg, so spill sreg3 now.
1417                                  */
1418                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1419                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1420                                 }
1421                                 continue;
1422                         }
1423
1424                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1425                                 if (is_global_ireg (sreg)) {
1426                                         int k;
1427                                         /* Argument already in hard reg, need to copy */
1428                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1429                                         insert_before_ins (bb, ins, copy);
1430                                         for (k = 0; k < num_sregs; ++k) {
1431                                                 if (k != j)
1432                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1433                                         }
1434                                         /* See below */
1435                                         dreg_mask &= ~ (regmask (dest_sreg));
1436                                 } else {
1437                                         val = rs->vassign [sreg];
1438                                         if (val == -1) {
1439                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1440                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1441                                         } else if (val < -1) {
1442                                                 /* FIXME: */
1443                                                 g_assert_not_reached ();
1444                                         } else {
1445                                                 /* Argument already in hard reg, need to copy */
1446                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1447                                                 int k;
1448
1449                                                 insert_before_ins (bb, ins, copy);
1450                                                 for (k = 0; k < num_sregs; ++k) {
1451                                                         if (k != j)
1452                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1453                                                 }
1454                                                 /*
1455                                                  * Prevent the dreg from being allocated to dest_sreg
1456                                                  * too, since it could force sreg1 to be allocated to
1457                                                  * the same reg on x86.
1458                                                  */
1459                                                 dreg_mask &= ~ (regmask (dest_sreg));
1460                                         }
1461                                 }
1462                         } else {
1463                                 gboolean need_spill = TRUE;
1464                                 gboolean need_assign = TRUE;
1465                                 int k;
1466
1467                                 dreg_mask &= ~ (regmask (dest_sreg));
1468                                 for (k = 0; k < num_sregs; ++k) {
1469                                         if (k != j)
1470                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1471                                 }
1472
1473                                 /*
1474                                  * First check if dreg is assigned to dest_sreg2, since we
1475                                  * can't spill a dreg.
1476                                  */
1477                                 if (spec [MONO_INST_DEST])
1478                                         val = rs->vassign [ins->dreg];
1479                                 else
1480                                         val = -1;
1481                                 if (val == dest_sreg && ins->dreg != sreg) {
1482                                         /*
1483                                          * the destination register is already assigned to
1484                                          * dest_sreg2: we need to allocate another register for it
1485                                          * and then copy from this to dest_sreg2.
1486                                          */
1487                                         int new_dest;
1488                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1489                                         g_assert (new_dest >= 0);
1490                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1491
1492                                         prev_dreg = ins->dreg;
1493                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1494                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1495                                         mono_regstate_free_int (rs, dest_sreg);
1496                                         need_spill = FALSE;
1497                                 }
1498
1499                                 if (is_global_ireg (sreg)) {
1500                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1501                                         insert_before_ins (bb, ins, copy);
1502                                         need_assign = FALSE;
1503                                 }
1504                                 else {
1505                                         val = rs->vassign [sreg];
1506                                         if (val == dest_sreg) {
1507                                                 /* sreg2 is already assigned to the correct register */
1508                                                 need_spill = FALSE;
1509                                         } else if (val < -1) {
1510                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1511                                         } else if (val >= 0) {
1512                                                 /* sreg2 already assigned to another register */
1513                                                 /*
1514                                                  * We couldn't emit a copy from val to dest_sreg2, because
1515                                                  * val might be spilled later while processing this
1516                                                  * instruction. So we spill sreg2 so it can be allocated to
1517                                                  * dest_sreg2.
1518                                                  */
1519                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1520                                         }
1521                                 }
1522
1523                                 if (need_spill) {
1524                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1525                                 }
1526
1527                                 if (need_assign) {
1528                                         if (rs->vassign [sreg] < -1) {
1529                                                 int spill;
1530
1531                                                 /* Need to emit a spill store */
1532                                                 spill = - rs->vassign [sreg] - 1;
1533                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1534                                         }
1535                                         /* force-set sreg2 */
1536                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1537                                 }
1538                         }
1539                         sregs [j] = dest_sreg;
1540                 }
1541                 mono_inst_set_src_registers (ins, sregs);
1542
1543                 /*
1544                  * TRACK DREG
1545                  */
1546                 bank = dreg_bank (spec);
1547                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1548                         prev_dreg = ins->dreg;
1549                 }
1550
1551                 if (spec_dest == 'b') {
1552                         /*
1553                          * The dest reg is read by the instruction, not written, so
1554                          * avoid allocating sreg1/sreg2 to the same reg.
1555                          */
1556                         if (dest_sregs [0] != -1)
1557                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1558                         for (j = 1; j < num_sregs; ++j) {
1559                                 if (dest_sregs [j] != -1)
1560                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1561                         }
1562
1563                         val = rs->vassign [ins->dreg];
1564                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1565                                 /* DREG is already allocated to a register needed for sreg1 */
1566                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1567                         }
1568                 }
1569
1570                 /*
1571                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1572                  * various complex situations.
1573                  */
1574                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1575                         guint32 dreg2, dest_dreg2;
1576
1577                         g_assert (is_soft_reg (ins->dreg, bank));
1578
1579                         if (dest_dreg != -1) {
1580                                 if (rs->vassign [ins->dreg] != dest_dreg)
1581                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1582
1583                                 dreg2 = ins->dreg + 1;
1584                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1585                                 if (dest_dreg2 != -1) {
1586                                         if (rs->vassign [dreg2] != dest_dreg2)
1587                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1588                                 }
1589                         }
1590                 }
1591
1592                 if (dreg_fixed_mask) {
1593                         g_assert (!bank);
1594                         if (is_global_ireg (ins->dreg)) {
1595                                 /*
1596                                  * The argument is already in a hard reg, but that reg is
1597                                  * not usable by this instruction, so allocate a new one.
1598                                  */
1599                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1600                                 if (val < 0)
1601                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1602                                 mono_regstate_free_int (rs, val);
1603                                 dest_dreg = val;
1604
1605                                 /* Fall through */
1606                         }
1607                         else
1608                                 dreg_mask &= dreg_fixed_mask;
1609                 }
1610
1611                 if (is_soft_reg (ins->dreg, bank)) {
1612                         val = rs->vassign [ins->dreg];
1613
1614                         if (val < 0) {
1615                                 int spill = 0;
1616                                 if (val < -1) {
1617                                         /* the register gets spilled after this inst */
1618                                         spill = -val -1;
1619                                 }
1620                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1621                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1622                                 if (spill)
1623                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1624                         }
1625
1626                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1627                         ins->dreg = val;
1628                 }
1629
1630                 /* Handle regpairs */
1631                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1632                         int reg2 = prev_dreg + 1;
1633
1634                         g_assert (!bank);
1635                         g_assert (prev_dreg > -1);
1636                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1637                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1638 #ifdef TARGET_X86
1639                         /* bug #80489 */
1640                         mask &= ~regmask (X86_ECX);
1641 #endif
1642                         val = rs->vassign [reg2];
1643                         if (val < 0) {
1644                                 int spill = 0;
1645                                 if (val < -1) {
1646                                         /* the register gets spilled after this inst */
1647                                         spill = -val -1;
1648                                 }
1649                                 val = mono_regstate_alloc_int (rs, mask);
1650                                 if (val < 0)
1651                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1652                                 if (spill)
1653                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1654                         }
1655                         else {
1656                                 if (! (mask & (regmask (val)))) {
1657                                         val = mono_regstate_alloc_int (rs, mask);
1658                                         if (val < 0)
1659                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1660
1661                                         /* Reallocate hreg to the correct register */
1662                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1663
1664                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1665                                 }
1666                         }
1667
1668                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1669                         assign_reg (cfg, rs, reg2, val, bank);
1670
1671                         dreg_high = val;
1672                         ins->backend.reg3 = val;
1673
1674                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1675                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1676                                 mono_regstate_free_int (rs, val);
1677                         }
1678                 }
1679
1680                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1681                         /*
1682                          * In theory, we could free up the hreg even if the vreg is alive,
1683                          * but branches inside bblocks force us to assign the same hreg
1684                          * to a vreg every time it is encountered.
1685                          */
1686                         int dreg = rs->vassign [prev_dreg];
1687                         g_assert (dreg >= 0);
1688                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1689                         if (G_UNLIKELY (bank))
1690                                 mono_regstate_free_general (rs, dreg, bank);
1691                         else
1692                                 mono_regstate_free_int (rs, dreg);
1693                         rs->vassign [prev_dreg] = -1;
1694                 }
1695
1696                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1697                         /* this instruction only outputs to dest_dreg, need to copy */
1698                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1699                         ins->dreg = dest_dreg;
1700
1701                         if (G_UNLIKELY (bank)) {
1702                                 /* the register we need to free up may be used in another logical regbank
1703                                  * so do a translate just in case.
1704                                  */
1705                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1706                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1707                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1708                         }
1709                         else {
1710                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1711                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1712                         }
1713                 }
1714
1715                 if (spec_dest == 'b') {
1716                         /*
1717                          * The dest reg is read by the instruction, not written, so
1718                          * avoid allocating sreg1/sreg2 to the same reg.
1719                          */
1720                         for (j = 0; j < num_sregs; ++j)
1721                                 if (!sreg_bank (j, spec))
1722                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1723                 }
1724
1725                 /*
1726                  * TRACK CLOBBERING
1727                  */
1728                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1729                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1730                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1731                 }
1732
1733                 if (spec [MONO_INST_CLOB] == 'c') {
1734                         int j, s, dreg, dreg2, cur_bank;
1735                         guint64 clob_mask;
1736
1737                         clob_mask = MONO_ARCH_CALLEE_REGS;
1738
1739                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1740                                 /*
1741                                  * Need to avoid spilling the dreg since the dreg is not really
1742                                  * clobbered by the call.
1743                                  */
1744                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1745                                         dreg = rs->vassign [prev_dreg];
1746                                 else
1747                                         dreg = -1;
1748
1749                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1750                                         dreg2 = rs->vassign [prev_dreg + 1];
1751                                 else
1752                                         dreg2 = -1;
1753
1754                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1755                                         s = regmask (j);
1756                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1757                                                 if ((j != dreg) && (j != dreg2))
1758                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1759                                                 else if (rs->isymbolic [j])
1760                                                         /* The hreg is assigned to the dreg of this instruction */
1761                                                         rs->vassign [rs->isymbolic [j]] = -1;
1762                                                 mono_regstate_free_int (rs, j);
1763                                         }
1764                                 }
1765                         }
1766
1767                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1768                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1769                                         clob_mask = regbank_callee_regs [cur_bank];
1770                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1771                                                 dreg = rs->vassign [prev_dreg];
1772                                         else
1773                                                 dreg = -1;
1774
1775                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1776
1777                                                 /* we are looping though the banks in the outer loop
1778                                                  * so, we don't need to deal with mirrored hregs
1779                                                  * because we will get them in one of the other bank passes.
1780                                                  */
1781                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1782                                                         continue;
1783
1784                                                 s = regmask (j);
1785                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1786                                                         if (j != dreg)
1787                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1788                                                         else if (rs->symbolic [cur_bank] [j])
1789                                                                 /* The hreg is assigned to the dreg of this instruction */
1790                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1791                                                         mono_regstate_free_general (rs, j, cur_bank);
1792                                                 }
1793                                         }
1794                                 }
1795                         }
1796                 }
1797
1798                 /*
1799                  * TRACK ARGUMENT REGS
1800                  */
1801                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1802                         MonoCallInst *call = (MonoCallInst*)ins;
1803                         GSList *list;
1804
1805                         /*
1806                          * This needs to be done before assigning sreg1, so sreg1 will
1807                          * not be assigned one of the argument regs.
1808                          */
1809
1810                         /*
1811                          * Assign all registers in call->out_reg_args to the proper
1812                          * argument registers.
1813                          */
1814
1815                         list = call->out_ireg_args;
1816                         if (list) {
1817                                 while (list) {
1818                                         guint32 regpair;
1819                                         int reg, hreg;
1820
1821                                         regpair = (guint32)(gssize)(list->data);
1822                                         hreg = regpair >> 24;
1823                                         reg = regpair & 0xffffff;
1824
1825                                         assign_reg (cfg, rs, reg, hreg, 0);
1826
1827                                         sreg_masks [0] &= ~(regmask (hreg));
1828
1829                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1830
1831                                         list = g_slist_next (list);
1832                                 }
1833                         }
1834
1835                         list = call->out_freg_args;
1836                         if (list) {
1837                                 while (list) {
1838                                         guint32 regpair;
1839                                         int reg, hreg;
1840
1841                                         regpair = (guint32)(gssize)(list->data);
1842                                         hreg = regpair >> 24;
1843                                         reg = regpair & 0xffffff;
1844
1845                                         assign_reg (cfg, rs, reg, hreg, 1);
1846
1847                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1848
1849                                         list = g_slist_next (list);
1850                                 }
1851                         }
1852                 }
1853
1854                 /*
1855                  * TRACK SREG1
1856                  */
1857                 bank = sreg1_bank (spec);
1858                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1859                         int sreg1 = sregs [0];
1860                         int dest_sreg1 = dest_sregs [0];
1861
1862                         g_assert (is_soft_reg (sreg1, bank));
1863
1864                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1865                         if (dest_sreg1 != -1)
1866                                 g_assert (dest_sreg1 == ins->dreg);
1867                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1868                         g_assert (val >= 0);
1869
1870                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1871                                 // FIXME:
1872                                 g_assert_not_reached ();
1873
1874                         assign_reg (cfg, rs, sreg1, val, bank);
1875
1876                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1877
1878                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1879                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1880                         g_assert (val >= 0);
1881
1882                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1883                                 // FIXME:
1884                                 g_assert_not_reached ();
1885
1886                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1887
1888                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1889
1890                         /* Skip rest of this section */
1891                         dest_sregs [0] = -1;
1892                 }
1893
1894                 if (sreg_fixed_masks [0]) {
1895                         g_assert (!bank);
1896                         if (is_global_ireg (sregs [0])) {
1897                                 /*
1898                                  * The argument is already in a hard reg, but that reg is
1899                                  * not usable by this instruction, so allocate a new one.
1900                                  */
1901                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1902                                 if (val < 0)
1903                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1904                                 mono_regstate_free_int (rs, val);
1905                                 dest_sregs [0] = val;
1906
1907                                 /* Fall through to the dest_sreg1 != -1 case */
1908                         }
1909                         else
1910                                 sreg_masks [0] &= sreg_fixed_masks [0];
1911                 }
1912
1913                 if (dest_sregs [0] != -1) {
1914                         sreg_masks [0] = regmask (dest_sregs [0]);
1915
1916                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1917                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1918                         }
1919                         if (is_global_ireg (sregs [0])) {
1920                                 /* The argument is already in a hard reg, need to copy */
1921                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1922                                 insert_before_ins (bb, ins, copy);
1923                                 sregs [0] = dest_sregs [0];
1924                         }
1925                 }
1926
1927                 if (is_soft_reg (sregs [0], bank)) {
1928                         val = rs->vassign [sregs [0]];
1929                         prev_sregs [0] = sregs [0];
1930                         if (val < 0) {
1931                                 int spill = 0;
1932                                 if (val < -1) {
1933                                         /* the register gets spilled after this inst */
1934                                         spill = -val -1;
1935                                 }
1936
1937                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1938                                         /*
1939                                          * Allocate the same hreg to sreg1 as well so the
1940                                          * peephole can get rid of the move.
1941                                          */
1942                                         sreg_masks [0] = regmask (ins->dreg);
1943                                 }
1944
1945                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1946                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1947                                         sreg_masks [0] = regmask (ins->dreg);
1948
1949                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1950                                 assign_reg (cfg, rs, sregs [0], val, bank);
1951                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1952
1953                                 if (spill) {
1954                                         /*
1955                                          * Need to insert before the instruction since it can
1956                                          * overwrite sreg1.
1957                                          */
1958                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1959                                 }
1960                         }
1961                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1962                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1963                                 insert_before_ins (bb, ins, copy);
1964                                 for (j = 1; j < num_sregs; ++j)
1965                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1966                                 val = dest_sregs [0];
1967                         }
1968
1969                         sregs [0] = val;
1970                 }
1971                 else {
1972                         prev_sregs [0] = -1;
1973                 }
1974                 mono_inst_set_src_registers (ins, sregs);
1975
1976                 for (j = 1; j < num_sregs; ++j)
1977                         sreg_masks [j] &= ~(regmask (sregs [0]));
1978
1979                 /* Handle the case when sreg1 is a regpair but dreg is not */
1980                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1981                         int reg2 = prev_sregs [0] + 1;
1982
1983                         g_assert (!bank);
1984                         g_assert (prev_sregs [0] > -1);
1985                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1986                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1987                         val = rs->vassign [reg2];
1988                         if (val < 0) {
1989                                 int spill = 0;
1990                                 if (val < -1) {
1991                                         /* the register gets spilled after this inst */
1992                                         spill = -val -1;
1993                                 }
1994                                 val = mono_regstate_alloc_int (rs, mask);
1995                                 if (val < 0)
1996                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1997                                 if (spill)
1998                                         g_assert_not_reached ();
1999                         }
2000                         else {
2001                                 if (! (mask & (regmask (val)))) {
2002                                         /* The vreg is already allocated to a wrong hreg */
2003                                         /* FIXME: */
2004                                         g_assert_not_reached ();
2005 #if 0
2006                                         val = mono_regstate_alloc_int (rs, mask);
2007                                         if (val < 0)
2008                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2009
2010                                         /* Reallocate hreg to the correct register */
2011                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2012
2013                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2014 #endif
2015                                 }
2016                         }
2017
2018                         sreg1_high = val;
2019                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2020                         assign_reg (cfg, rs, reg2, val, bank);
2021                 }
2022
2023                 /* Handle dreg==sreg1 */
2024                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2025                         MonoInst *sreg2_copy = NULL;
2026                         MonoInst *copy;
2027                         int bank = reg_bank (spec_src1);
2028
2029                         if (ins->dreg == sregs [1]) {
2030                                 /*
2031                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2032                                  * register for it.
2033                                  */
2034                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2035
2036                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2037                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2038                                 prev_sregs [1] = sregs [1] = reg2;
2039
2040                                 if (G_UNLIKELY (bank))
2041                                         mono_regstate_free_general (rs, reg2, bank);
2042                                 else
2043                                         mono_regstate_free_int (rs, reg2);
2044                         }
2045
2046                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2047                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2048                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2049                                         /* FIXME: */
2050                                         g_assert_not_reached ();
2051
2052                                 /*
2053                                  * sreg1 and dest are already allocated to the same regpair by the
2054                                  * SREG1 allocation code.
2055                                  */
2056                                 g_assert (sregs [0] == ins->dreg);
2057                                 g_assert (dreg_high == sreg1_high);
2058                         }
2059
2060                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2061                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2062                         insert_before_ins (bb, ins, copy);
2063
2064                         if (sreg2_copy)
2065                                 insert_before_ins (bb, copy, sreg2_copy);
2066
2067                         /*
2068                          * Need to prevent sreg2 to be allocated to sreg1, since that
2069                          * would screw up the previous copy.
2070                          */
2071                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2072                         /* we set sreg1 to dest as well */
2073                         prev_sregs [0] = sregs [0] = ins->dreg;
2074                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2075                 }
2076                 mono_inst_set_src_registers (ins, sregs);
2077
2078                 /*
2079                  * TRACK SREG2, 3, ...
2080                  */
2081                 for (j = 1; j < num_sregs; ++j) {
2082                         int k;
2083
2084                         bank = sreg_bank (j, spec);
2085                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2086                                 g_assert_not_reached ();
2087
2088                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2089                                 /*
2090                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2091                                  * allocating it to the fixed reg.
2092                                  */
2093                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2094                                 insert_before_ins (bb, ins, copy);
2095                                 sregs [j] = dest_sregs [j];
2096                         } else if (is_soft_reg (sregs [j], bank)) {
2097                                 val = rs->vassign [sregs [j]];
2098
2099                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2100                                         /*
2101                                          * The sreg is already allocated to a hreg, but not to the fixed
2102                                          * reg required by the instruction. Spill the sreg, so it can be
2103                                          * allocated to the fixed reg by the code below.
2104                                          */
2105                                         /* Currently, this code should only be hit for CAS */
2106                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2107                                         val = rs->vassign [sregs [j]];
2108                                 }
2109
2110                                 if (val < 0) {
2111                                         int spill = 0;
2112                                         if (val < -1) {
2113                                                 /* the register gets spilled after this inst */
2114                                                 spill = -val -1;
2115                                         }
2116                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2117                                         assign_reg (cfg, rs, sregs [j], val, bank);
2118                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2119                                         if (spill) {
2120                                                 /*
2121                                                  * Need to insert before the instruction since it can
2122                                                  * overwrite sreg2.
2123                                                  */
2124                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2125                                         }
2126                                 }
2127                                 sregs [j] = val;
2128                                 for (k = j + 1; k < num_sregs; ++k)
2129                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2130                         }
2131                         else {
2132                                 prev_sregs [j] = -1;
2133                         }
2134                 }
2135                 mono_inst_set_src_registers (ins, sregs);
2136
2137                 /* Sanity check */
2138                 /* Do this only for CAS for now */
2139                 for (j = 1; j < num_sregs; ++j) {
2140                         int sreg = sregs [j];
2141                         int dest_sreg = dest_sregs [j];
2142
2143                         if (j == 2 && dest_sreg != -1) {
2144                                 int k;
2145
2146                                 g_assert (sreg == dest_sreg);
2147
2148                                 for (k = 0; k < num_sregs; ++k) {
2149                                         if (k != j)
2150                                                 g_assert (sregs [k] != dest_sreg);
2151                                 }
2152                         }
2153                 }
2154
2155                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2156                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2157                         mono_regstate_free_int (rs, ins->sreg1);
2158                 }
2159                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2160                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2161                         mono_regstate_free_int (rs, ins->sreg2);
2162                 }*/
2163
2164                 DEBUG (mono_print_ins_index (i, ins));
2165         }
2166
2167         // FIXME: Set MAX_FREGS to 8
2168         // FIXME: Optimize generated code
2169 #if MONO_ARCH_USE_FPSTACK
2170         /*
2171          * Make a forward pass over the code, simulating the fp stack, making sure the
2172          * arguments required by the fp opcodes are at the top of the stack.
2173          */
2174         if (has_fp) {
2175                 MonoInst *prev = NULL;
2176                 MonoInst *fxch;
2177                 int tmp;
2178
2179                 g_assert (num_sregs <= 2);
2180
2181                 for (ins = bb->code; ins; ins = ins->next) {
2182                         spec = ins_get_spec (ins->opcode);
2183
2184                         DEBUG (printf ("processing:"));
2185                         DEBUG (mono_print_ins_index (0, ins));
2186
2187                         if (ins->opcode == OP_FMOVE) {
2188                                 /* Do it by renaming the source to the destination on the stack */
2189                                 // FIXME: Is this correct ?
2190                                 for (i = 0; i < sp; ++i)
2191                                         if (fpstack [i] == ins->sreg1)
2192                                                 fpstack [i] = ins->dreg;
2193                                 prev = ins;
2194                                 continue;
2195                         }
2196
2197                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2198                                 /* Arg1 must be in %st(1) */
2199                                 g_assert (prev);
2200
2201                                 i = 0;
2202                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2203                                         i ++;
2204                                 g_assert (i < sp);
2205
2206                                 if (sp - 1 - i > 0) {
2207                                         /* First move it to %st(0) */
2208                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2209
2210                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2211                                         fxch->inst_imm = sp - 1 - i;
2212
2213                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2214                                         prev = fxch;
2215
2216                                         tmp = fpstack [sp - 1];
2217                                         fpstack [sp - 1] = fpstack [i];
2218                                         fpstack [i] = tmp;
2219                                 }
2220
2221                                 /* Then move it to %st(1) */
2222                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2223
2224                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2225                                 fxch->inst_imm = 1;
2226
2227                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2228                                 prev = fxch;
2229
2230                                 tmp = fpstack [sp - 1];
2231                                 fpstack [sp - 1] = fpstack [sp - 2];
2232                                 fpstack [sp - 2] = tmp;
2233                         }
2234
2235                         if (sreg2_is_fp (spec)) {
2236                                 g_assert (sp > 0);
2237
2238                                 if (fpstack [sp - 1] != ins->sreg2) {
2239                                         g_assert (prev);
2240
2241                                         i = 0;
2242                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2243                                                 i ++;
2244                                         g_assert (i < sp);
2245
2246                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2247
2248                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2249                                         fxch->inst_imm = sp - 1 - i;
2250
2251                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2252                                         prev = fxch;
2253
2254                                         tmp = fpstack [sp - 1];
2255                                         fpstack [sp - 1] = fpstack [i];
2256                                         fpstack [i] = tmp;
2257                                 }
2258
2259                                 sp --;
2260                         }
2261
2262                         if (sreg1_is_fp (spec)) {
2263                                 g_assert (sp > 0);
2264
2265                                 if (fpstack [sp - 1] != ins->sreg1) {
2266                                         g_assert (prev);
2267
2268                                         i = 0;
2269                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2270                                                 i ++;
2271                                         g_assert (i < sp);
2272
2273                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2274
2275                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2276                                         fxch->inst_imm = sp - 1 - i;
2277
2278                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2279                                         prev = fxch;
2280
2281                                         tmp = fpstack [sp - 1];
2282                                         fpstack [sp - 1] = fpstack [i];
2283                                         fpstack [i] = tmp;
2284                                 }
2285
2286                                 sp --;
2287                         }
2288
2289                         if (dreg_is_fp (spec)) {
2290                                 g_assert (sp < 8);
2291                                 fpstack [sp ++] = ins->dreg;
2292                         }
2293
2294                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2295                                 printf ("\t[");
2296                                 for (i = 0; i < sp; ++i)
2297                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2298                                 printf ("]\n");
2299                         }
2300
2301                         prev = ins;
2302                 }
2303
2304                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2305                         /* Remove remaining items from the fp stack */
2306                         /*
2307                          * These can remain for example as a result of a dead fmove like in
2308                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2309                          */
2310                         while (sp) {
2311                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2312                                 mono_add_ins_to_end (bb, ins);
2313                                 sp --;
2314                         }
2315                 }
2316         }
2317 #endif
2318 }
2319
2320 CompRelation
2321 mono_opcode_to_cond (int opcode)
2322 {
2323         switch (opcode) {
2324         case OP_CEQ:
2325         case OP_IBEQ:
2326         case OP_ICEQ:
2327         case OP_LBEQ:
2328         case OP_LCEQ:
2329         case OP_FBEQ:
2330         case OP_FCEQ:
2331         case OP_RBEQ:
2332         case OP_RCEQ:
2333         case OP_COND_EXC_EQ:
2334         case OP_COND_EXC_IEQ:
2335         case OP_CMOV_IEQ:
2336         case OP_CMOV_LEQ:
2337                 return CMP_EQ;
2338         case OP_FCNEQ:
2339         case OP_ICNEQ:
2340         case OP_IBNE_UN:
2341         case OP_LBNE_UN:
2342         case OP_FBNE_UN:
2343         case OP_COND_EXC_NE_UN:
2344         case OP_COND_EXC_INE_UN:
2345         case OP_CMOV_INE_UN:
2346         case OP_CMOV_LNE_UN:
2347                 return CMP_NE;
2348         case OP_FCLE:
2349         case OP_ICLE:
2350         case OP_IBLE:
2351         case OP_LBLE:
2352         case OP_FBLE:
2353         case OP_CMOV_ILE:
2354         case OP_CMOV_LLE:
2355                 return CMP_LE;
2356         case OP_FCGE:
2357         case OP_ICGE:
2358         case OP_IBGE:
2359         case OP_LBGE:
2360         case OP_FBGE:
2361         case OP_CMOV_IGE:
2362         case OP_CMOV_LGE:
2363                 return CMP_GE;
2364         case OP_CLT:
2365         case OP_IBLT:
2366         case OP_ICLT:
2367         case OP_LBLT:
2368         case OP_LCLT:
2369         case OP_FBLT:
2370         case OP_FCLT:
2371         case OP_RBLT:
2372         case OP_RCLT:
2373         case OP_COND_EXC_LT:
2374         case OP_COND_EXC_ILT:
2375         case OP_CMOV_ILT:
2376         case OP_CMOV_LLT:
2377                 return CMP_LT;
2378         case OP_CGT:
2379         case OP_IBGT:
2380         case OP_ICGT:
2381         case OP_LBGT:
2382         case OP_LCGT:
2383         case OP_FBGT:
2384         case OP_FCGT:
2385         case OP_RBGT:
2386         case OP_RCGT:
2387         case OP_COND_EXC_GT:
2388         case OP_COND_EXC_IGT:
2389         case OP_CMOV_IGT:
2390         case OP_CMOV_LGT:
2391                 return CMP_GT;
2392
2393         case OP_ICLE_UN:
2394         case OP_IBLE_UN:
2395         case OP_LBLE_UN:
2396         case OP_FBLE_UN:
2397         case OP_COND_EXC_LE_UN:
2398         case OP_COND_EXC_ILE_UN:
2399         case OP_CMOV_ILE_UN:
2400         case OP_CMOV_LLE_UN:
2401                 return CMP_LE_UN;
2402
2403         case OP_ICGE_UN:
2404         case OP_IBGE_UN:
2405         case OP_LBGE_UN:
2406         case OP_FBGE_UN:
2407         case OP_CMOV_IGE_UN:
2408         case OP_CMOV_LGE_UN:
2409                 return CMP_GE_UN;
2410         case OP_CLT_UN:
2411         case OP_IBLT_UN:
2412         case OP_ICLT_UN:
2413         case OP_LBLT_UN:
2414         case OP_LCLT_UN:
2415         case OP_FBLT_UN:
2416         case OP_FCLT_UN:
2417         case OP_RBLT_UN:
2418         case OP_RCLT_UN:
2419         case OP_COND_EXC_LT_UN:
2420         case OP_COND_EXC_ILT_UN:
2421         case OP_CMOV_ILT_UN:
2422         case OP_CMOV_LLT_UN:
2423                 return CMP_LT_UN;
2424         case OP_CGT_UN:
2425         case OP_IBGT_UN:
2426         case OP_ICGT_UN:
2427         case OP_LBGT_UN:
2428         case OP_LCGT_UN:
2429         case OP_FCGT_UN:
2430         case OP_FBGT_UN:
2431         case OP_RCGT_UN:
2432         case OP_RBGT_UN:
2433         case OP_COND_EXC_GT_UN:
2434         case OP_COND_EXC_IGT_UN:
2435         case OP_CMOV_IGT_UN:
2436         case OP_CMOV_LGT_UN:
2437                 return CMP_GT_UN;
2438         default:
2439                 printf ("%s\n", mono_inst_name (opcode));
2440                 g_assert_not_reached ();
2441                 return 0;
2442         }
2443 }
2444
2445 CompRelation
2446 mono_negate_cond (CompRelation cond)
2447 {
2448         switch (cond) {
2449         case CMP_EQ:
2450                 return CMP_NE;
2451         case CMP_NE:
2452                 return CMP_EQ;
2453         case CMP_LE:
2454                 return CMP_GT;
2455         case CMP_GE:
2456                 return CMP_LT;
2457         case CMP_LT:
2458                 return CMP_GE;
2459         case CMP_GT:
2460                 return CMP_LE;
2461         case CMP_LE_UN:
2462                 return CMP_GT_UN;
2463         case CMP_GE_UN:
2464                 return CMP_LT_UN;
2465         case CMP_LT_UN:
2466                 return CMP_GE_UN;
2467         case CMP_GT_UN:
2468                 return CMP_LE_UN;
2469         default:
2470                 g_assert_not_reached ();
2471         }
2472 }
2473
2474 CompType
2475 mono_opcode_to_type (int opcode, int cmp_opcode)
2476 {
2477         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2478                 return CMP_TYPE_L;
2479         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2480                 return CMP_TYPE_I;
2481         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2482                 return CMP_TYPE_I;
2483         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2484                 return CMP_TYPE_L;
2485         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2486                 return CMP_TYPE_L;
2487         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2488                 return CMP_TYPE_F;
2489         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2490                 return CMP_TYPE_F;
2491         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2492                 return CMP_TYPE_I;
2493         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2494                 switch (cmp_opcode) {
2495                 case OP_ICOMPARE:
2496                 case OP_ICOMPARE_IMM:
2497                         return CMP_TYPE_I;
2498                 default:
2499                         return CMP_TYPE_L;
2500                 }
2501         } else {
2502                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2503                 return 0;
2504         }
2505 }
2506
2507 #endif /* DISABLE_JIT */
2508
2509 gboolean
2510 mono_is_regsize_var (MonoType *t)
2511 {
2512         t = mini_get_underlying_type (t);
2513         switch (t->type) {
2514         case MONO_TYPE_I1:
2515         case MONO_TYPE_U1:
2516         case MONO_TYPE_I2:
2517         case MONO_TYPE_U2:
2518         case MONO_TYPE_I4:
2519         case MONO_TYPE_U4:
2520         case MONO_TYPE_I:
2521         case MONO_TYPE_U:
2522         case MONO_TYPE_PTR:
2523         case MONO_TYPE_FNPTR:
2524 #if SIZEOF_REGISTER == 8
2525         case MONO_TYPE_I8:
2526         case MONO_TYPE_U8:
2527 #endif
2528                 return TRUE;
2529         case MONO_TYPE_OBJECT:
2530         case MONO_TYPE_STRING:
2531         case MONO_TYPE_CLASS:
2532         case MONO_TYPE_SZARRAY:
2533         case MONO_TYPE_ARRAY:
2534                 return TRUE;
2535         case MONO_TYPE_GENERICINST:
2536                 if (!mono_type_generic_inst_is_valuetype (t))
2537                         return TRUE;
2538                 return FALSE;
2539         case MONO_TYPE_VALUETYPE:
2540                 return FALSE;
2541         default:
2542                 return FALSE;
2543         }
2544 }
2545
2546 #ifndef DISABLE_JIT
2547
2548 /*
2549  * mono_peephole_ins:
2550  *
2551  *   Perform some architecture independent peephole optimizations.
2552  */
2553 void
2554 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2555 {
2556         int filter = FILTER_IL_SEQ_POINT;
2557         MonoInst *last_ins = mono_inst_prev (ins, filter);
2558
2559         switch (ins->opcode) {
2560         case OP_MUL_IMM:
2561                 /* remove unnecessary multiplication with 1 */
2562                 if (ins->inst_imm == 1) {
2563                         if (ins->dreg != ins->sreg1)
2564                                 ins->opcode = OP_MOVE;
2565                         else
2566                                 MONO_DELETE_INS (bb, ins);
2567                 }
2568                 break;
2569         case OP_LOAD_MEMBASE:
2570         case OP_LOADI4_MEMBASE:
2571                 /*
2572                  * Note: if reg1 = reg2 the load op is removed
2573                  *
2574                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2575                  * OP_LOAD_MEMBASE offset(basereg), reg2
2576                  * -->
2577                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2578                  * OP_MOVE reg1, reg2
2579                  */
2580                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2581                         last_ins = mono_inst_prev (ins, filter);
2582                 if (last_ins &&
2583                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2584                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2585                         ins->inst_basereg == last_ins->inst_destbasereg &&
2586                         ins->inst_offset == last_ins->inst_offset) {
2587                         if (ins->dreg == last_ins->sreg1) {
2588                                 MONO_DELETE_INS (bb, ins);
2589                                 break;
2590                         } else {
2591                                 ins->opcode = OP_MOVE;
2592                                 ins->sreg1 = last_ins->sreg1;
2593                         }
2594
2595                         /*
2596                          * Note: reg1 must be different from the basereg in the second load
2597                          * Note: if reg1 = reg2 is equal then second load is removed
2598                          *
2599                          * OP_LOAD_MEMBASE offset(basereg), reg1
2600                          * OP_LOAD_MEMBASE offset(basereg), reg2
2601                          * -->
2602                          * OP_LOAD_MEMBASE offset(basereg), reg1
2603                          * OP_MOVE reg1, reg2
2604                          */
2605                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2606                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2607                           ins->inst_basereg != last_ins->dreg &&
2608                           ins->inst_basereg == last_ins->inst_basereg &&
2609                           ins->inst_offset == last_ins->inst_offset) {
2610
2611                         if (ins->dreg == last_ins->dreg) {
2612                                 MONO_DELETE_INS (bb, ins);
2613                         } else {
2614                                 ins->opcode = OP_MOVE;
2615                                 ins->sreg1 = last_ins->dreg;
2616                         }
2617
2618                         //g_assert_not_reached ();
2619
2620 #if 0
2621                         /*
2622                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2623                          * OP_LOAD_MEMBASE offset(basereg), reg
2624                          * -->
2625                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2626                          * OP_ICONST reg, imm
2627                          */
2628                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2629                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2630                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2631                                    ins->inst_offset == last_ins->inst_offset) {
2632                         ins->opcode = OP_ICONST;
2633                         ins->inst_c0 = last_ins->inst_imm;
2634                         g_assert_not_reached (); // check this rule
2635 #endif
2636                 }
2637                 break;
2638         case OP_LOADI1_MEMBASE:
2639         case OP_LOADU1_MEMBASE:
2640                 /*
2641                  * Note: if reg1 = reg2 the load op is removed
2642                  *
2643                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2644                  * OP_LOAD_MEMBASE offset(basereg), reg2
2645                  * -->
2646                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2647                  * OP_MOVE reg1, reg2
2648                  */
2649                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2650                         ins->inst_basereg == last_ins->inst_destbasereg &&
2651                         ins->inst_offset == last_ins->inst_offset) {
2652                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2653                         ins->sreg1 = last_ins->sreg1;
2654                 }
2655                 break;
2656         case OP_LOADI2_MEMBASE:
2657         case OP_LOADU2_MEMBASE:
2658                 /*
2659                  * Note: if reg1 = reg2 the load op is removed
2660                  *
2661                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2662                  * OP_LOAD_MEMBASE offset(basereg), reg2
2663                  * -->
2664                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2665                  * OP_MOVE reg1, reg2
2666                  */
2667                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2668                         ins->inst_basereg == last_ins->inst_destbasereg &&
2669                         ins->inst_offset == last_ins->inst_offset) {
2670 #if SIZEOF_REGISTER == 8
2671                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2672 #else
2673                         /* The definition of OP_PCONV_TO_U2 is wrong */
2674                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2675 #endif
2676                         ins->sreg1 = last_ins->sreg1;
2677                 }
2678                 break;
2679         case OP_MOVE:
2680         case OP_FMOVE:
2681                 /*
2682                  * Removes:
2683                  *
2684                  * OP_MOVE reg, reg
2685                  */
2686                 if (ins->dreg == ins->sreg1) {
2687                         MONO_DELETE_INS (bb, ins);
2688                         break;
2689                 }
2690                 /*
2691                  * Removes:
2692                  *
2693                  * OP_MOVE sreg, dreg
2694                  * OP_MOVE dreg, sreg
2695                  */
2696                 if (last_ins && last_ins->opcode == ins->opcode &&
2697                         ins->sreg1 == last_ins->dreg &&
2698                         ins->dreg == last_ins->sreg1) {
2699                         MONO_DELETE_INS (bb, ins);
2700                 }
2701                 break;
2702         case OP_NOP:
2703                 MONO_DELETE_INS (bb, ins);
2704                 break;
2705         }
2706 }
2707
2708 int
2709 mini_exception_id_by_name (const char *name)
2710 {
2711         if (strcmp (name, "IndexOutOfRangeException") == 0)
2712                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2713         if (strcmp (name, "OverflowException") == 0)
2714                 return MONO_EXC_OVERFLOW;
2715         if (strcmp (name, "ArithmeticException") == 0)
2716                 return MONO_EXC_ARITHMETIC;
2717         if (strcmp (name, "DivideByZeroException") == 0)
2718                 return MONO_EXC_DIVIDE_BY_ZERO;
2719         if (strcmp (name, "InvalidCastException") == 0)
2720                 return MONO_EXC_INVALID_CAST;
2721         if (strcmp (name, "NullReferenceException") == 0)
2722                 return MONO_EXC_NULL_REF;
2723         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2724                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2725         if (strcmp (name, "ArgumentException") == 0)
2726                 return MONO_EXC_ARGUMENT;
2727         g_error ("Unknown intrinsic exception %s\n", name);
2728         return -1;
2729 }
2730
2731 gboolean
2732 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2733 {
2734         MonoClass *klass;
2735         gpointer iter;
2736         MonoClassField *field;
2737         MonoType *ftype, *prev_ftype = NULL;
2738         int nfields = 0;
2739
2740         klass = mono_class_from_mono_type (t);
2741         iter = NULL;
2742         while ((field = mono_class_get_fields (klass, &iter))) {
2743                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2744                         continue;
2745                 ftype = mono_field_get_type (field);
2746                 ftype = mini_native_type_replace_type (ftype);
2747
2748                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2749                         int nested_nfields, nested_esize;
2750
2751                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2752                                 return FALSE;
2753                         if (nested_esize == 4)
2754                                 ftype = &mono_defaults.single_class->byval_arg;
2755                         else
2756                                 ftype = &mono_defaults.double_class->byval_arg;
2757                         if (prev_ftype && prev_ftype->type != ftype->type)
2758                                 return FALSE;
2759                         prev_ftype = ftype;
2760                         nfields += nested_nfields;
2761                 } else {
2762                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2763                                 return FALSE;
2764                         if (prev_ftype && prev_ftype->type != ftype->type)
2765                                 return FALSE;
2766                         prev_ftype = ftype;
2767                         nfields ++;
2768                 }
2769         }
2770         if (nfields == 0)
2771                 return FALSE;
2772         *out_nfields = nfields;
2773         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2774         return TRUE;
2775 }
2776
2777 MonoRegState*
2778 mono_regstate_new (void)
2779 {
2780         MonoRegState* rs = g_new0 (MonoRegState, 1);
2781
2782         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2783 #ifdef MONO_ARCH_NEED_SIMD_BANK
2784         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2785 #endif
2786
2787         return rs;
2788 }
2789
2790 void
2791 mono_regstate_free (MonoRegState *rs) {
2792         g_free (rs->vassign);
2793         g_free (rs);
2794 }
2795
2796 #endif /* DISABLE_JIT */