mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413
 414 static const char* const patch_info_str[] = {
 415 #define PATCH_INFO(a,b) "" #a,
 416 #include "patch-info.h"
 417 #undef PATCH_INFO
 418 };
 419
 420 void
 421 mono_print_ji (const MonoJumpInfo *ji)
 422 {
 423         switch (ji->type) {
 424         case MONO_PATCH_INFO_RGCTX_FETCH: {
 425                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 426
 427                 printf ("[RGCTX_FETCH ");
 428                 mono_print_ji (entry->data);
 429                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 430                 break;
 431         }
 432         case MONO_PATCH_INFO_METHODCONST: {
 433                 char *s = mono_method_full_name (ji->data.method, TRUE);
 434                 printf ("[METHODCONST - %s]", s);
 435                 g_free (s);
 436                 break;
 437         }
 438         default:
 439                 printf ("[%s]", patch_info_str [ji->type]);
 440                 break;
 441         }
 442 }
 443
 444 void
 445 mono_print_ins_index (int i, MonoInst *ins)
 446 {
 447         const char *spec = ins_get_spec (ins->opcode);
 448         int num_sregs, j;
 449         int sregs [MONO_MAX_SRC_REGS];
 450
 451         if (i != -1)
 452                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 453         else
 454                 printf (" %s", mono_inst_name (ins->opcode));
 455         if (spec == MONO_ARCH_CPU_SPEC) {
 456                 /* This is a lowered opcode */
 457                 if (ins->dreg != -1)
 458                         printf (" R%d <-", ins->dreg);
 459                 if (ins->sreg1 != -1)
 460                         printf (" R%d", ins->sreg1);
 461                 if (ins->sreg2 != -1)
 462                         printf (" R%d", ins->sreg2);
 463                 if (ins->sreg3 != -1)
 464                         printf (" R%d", ins->sreg3);
 465
 466                 switch (ins->opcode) {
 467                 case OP_LBNE_UN:
 468                 case OP_LBEQ:
 469                 case OP_LBLT:
 470                 case OP_LBLT_UN:
 471                 case OP_LBGT:
 472                 case OP_LBGT_UN:
 473                 case OP_LBGE:
 474                 case OP_LBGE_UN:
 475                 case OP_LBLE:
 476                 case OP_LBLE_UN:
 477                         if (!ins->inst_false_bb)
 478                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 479                         else
 480                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 481                         break;
 482                 case OP_PHI:
 483                 case OP_VPHI:
 484                 case OP_XPHI:
 485                 case OP_FPHI: {
 486                         int i;
 487                         printf (" [%d (", (int)ins->inst_c0);
 488                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 489                                 if (i)
 490                                         printf (", ");
 491                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 492                         }
 493                         printf (")]");
 494                         break;
 495                 }
 496                 case OP_LDADDR:
 497                 case OP_OUTARG_VTRETADDR:
 498                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 499                         break;
 500                 case OP_REGOFFSET:
 501                         printf (" + 0x%lx", (long)ins->inst_offset);
 502                         break;
 503                 default:
 504                         break;
 505                 }
 506
 507                 printf ("\n");
 508                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 509                 return;
 510         }
 511
 512         if (spec [MONO_INST_DEST]) {
 513                 int bank = dreg_bank (spec);
 514                 if (is_soft_reg (ins->dreg, bank)) {
 515                         if (spec [MONO_INST_DEST] == 'b') {
 516                                 if (ins->inst_offset == 0)
 517                                         printf (" [R%d] <-", ins->dreg);
 518                                 else
 519                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 520                         }
 521                         else
 522                                 printf (" R%d <-", ins->dreg);
 523                 } else if (spec [MONO_INST_DEST] == 'b') {
 524                         if (ins->inst_offset == 0)
 525                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 526                         else
 527                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 528                 } else
 529                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 530         }
 531         if (spec [MONO_INST_SRC1]) {
 532                 int bank = sreg1_bank (spec);
 533                 if (is_soft_reg (ins->sreg1, bank)) {
 534                         if (spec [MONO_INST_SRC1] == 'b')
 535                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 536                         else
 537                                 printf (" R%d", ins->sreg1);
 538                 } else if (spec [MONO_INST_SRC1] == 'b')
 539                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 540                 else
 541                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 542         }
 543         num_sregs = mono_inst_get_src_registers (ins, sregs);
 544         for (j = 1; j < num_sregs; ++j) {
 545                 int bank = sreg_bank (j, spec);
 546                 if (is_soft_reg (sregs [j], bank))
 547                         printf (" R%d", sregs [j]);
 548                 else
 549                         printf (" %s", mono_regname_full (sregs [j], bank));
 550         }
 551
 552         switch (ins->opcode) {
 553         case OP_ICONST:
 554                 printf (" [%d]", (int)ins->inst_c0);
 555                 break;
 556 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 557         case OP_X86_PUSH_IMM:
 558 #endif
 559         case OP_ICOMPARE_IMM:
 560         case OP_COMPARE_IMM:
 561         case OP_IADD_IMM:
 562         case OP_ISUB_IMM:
 563         case OP_IAND_IMM:
 564         case OP_IOR_IMM:
 565         case OP_IXOR_IMM:
 566         case OP_SUB_IMM:
 567                 printf (" [%d]", (int)ins->inst_imm);
 568                 break;
 569         case OP_ADD_IMM:
 570         case OP_LADD_IMM:
 571                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 572                 break;
 573         case OP_I8CONST:
 574                 printf (" [%lld]", (long long)ins->inst_l);
 575                 break;
 576         case OP_R8CONST:
 577                 printf (" [%f]", *(double*)ins->inst_p0);
 578                 break;
 579         case OP_R4CONST:
 580                 printf (" [%f]", *(float*)ins->inst_p0);
 581                 break;
 582         case OP_CALL:
 583         case OP_CALL_MEMBASE:
 584         case OP_CALL_REG:
 585         case OP_FCALL:
 586         case OP_FCALLVIRT:
 587         case OP_LCALL:
 588         case OP_LCALLVIRT:
 589         case OP_VCALL:
 590         case OP_VCALLVIRT:
 591         case OP_VCALL_REG:
 592         case OP_VCALL_MEMBASE:
 593         case OP_VCALL2:
 594         case OP_VCALL2_REG:
 595         case OP_VCALL2_MEMBASE:
 596         case OP_VOIDCALL:
 597         case OP_VOIDCALL_MEMBASE:
 598         case OP_VOIDCALLVIRT:
 599         case OP_TAILCALL: {
 600                 MonoCallInst *call = (MonoCallInst*)ins;
 601                 GSList *list;
 602
 603                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 604                         /*
 605                          * These are lowered opcodes, but they are in the .md files since the old
 606                          * JIT passes them to backends.
 607                          */
 608                         if (ins->dreg != -1)
 609                                 printf (" R%d <-", ins->dreg);
 610                 }
 611
 612                 if (call->method) {
 613                         char *full_name = mono_method_full_name (call->method, TRUE);
 614                         printf (" [%s]", full_name);
 615                         g_free (full_name);
 616                 } else if (call->fptr_is_patch) {
 617                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 618
 619                         printf (" ");
 620                         mono_print_ji (ji);
 621                 } else if (call->fptr) {
 622                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 623                         if (info)
 624                                 printf (" [%s]", info->name);
 625                 }
 626
 627                 list = call->out_ireg_args;
 628                 while (list) {
 629                         guint32 regpair;
 630                         int reg, hreg;
 631
 632                         regpair = (guint32)(gssize)(list->data);
 633                         hreg = regpair >> 24;
 634                         reg = regpair & 0xffffff;
 635
 636                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 637
 638                         list = g_slist_next (list);
 639                 }
 640                 break;
 641         }
 642         case OP_BR:
 643         case OP_CALL_HANDLER:
 644                 printf (" [B%d]", ins->inst_target_bb->block_num);
 645                 break;
 646         case OP_IBNE_UN:
 647         case OP_IBEQ:
 648         case OP_IBLT:
 649         case OP_IBLT_UN:
 650         case OP_IBGT:
 651         case OP_IBGT_UN:
 652         case OP_IBGE:
 653         case OP_IBGE_UN:
 654         case OP_IBLE:
 655         case OP_IBLE_UN:
 656         case OP_LBNE_UN:
 657         case OP_LBEQ:
 658         case OP_LBLT:
 659         case OP_LBLT_UN:
 660         case OP_LBGT:
 661         case OP_LBGT_UN:
 662         case OP_LBGE:
 663         case OP_LBGE_UN:
 664         case OP_LBLE:
 665         case OP_LBLE_UN:
 666                 if (!ins->inst_false_bb)
 667                         printf (" [B%d]", ins->inst_true_bb->block_num);
 668                 else
 669                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 670                 break;
 671         case OP_LIVERANGE_START:
 672         case OP_LIVERANGE_END:
 673         case OP_GC_LIVENESS_DEF:
 674         case OP_GC_LIVENESS_USE:
 675                 printf (" R%d", (int)ins->inst_c1);
 676                 break;
 677         case OP_SEQ_POINT:
 678                 printf (" il: %x", (int)ins->inst_imm);
 679                 break;
 680         default:
 681                 break;
 682         }
 683
 684         if (spec [MONO_INST_CLOB])
 685                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 686         printf ("\n");
 687 }
 688
 689 static void
 690 print_regtrack (RegTrack *t, int num)
 691 {
 692         int i;
 693         char buf [32];
 694         const char *r;
 695
 696         for (i = 0; i < num; ++i) {
 697                 if (!t [i].born_in)
 698                         continue;
 699                 if (i >= MONO_MAX_IREGS) {
 700                         g_snprintf (buf, sizeof(buf), "R%d", i);
 701                         r = buf;
 702                 } else
 703                         r = mono_arch_regname (i);
 704                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 705         }
 706 }
 707 #else
 708
 709 void
 710 mono_print_ji (const MonoJumpInfo *ji)
 711 {
 712 }
 713
 714 void
 715 mono_print_ins_index (int i, MonoInst *ins)
 716 {
 717 }
 718 #endif /* DISABLE_LOGGING */
 719
 720 void
 721 mono_print_ins (MonoInst *ins)
 722 {
 723         mono_print_ins_index (-1, ins);
 724 }
 725
 726 static inline void
 727 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 728 {
 729         /*
 730          * If this function is called multiple times, the new instructions are inserted
 731          * in the proper order.
 732          */
 733         mono_bblock_insert_before_ins (bb, ins, to_insert);
 734 }
 735
 736 static inline void
 737 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 738 {
 739         /*
 740          * If this function is called multiple times, the new instructions are inserted in
 741          * proper order.
 742          */
 743         mono_bblock_insert_after_ins (bb, *last, to_insert);
 744
 745         *last = to_insert;
 746 }
 747
 748 static inline int
 749 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 750 {
 751         if (vreg_is_ref (cfg, reg))
 752                 return MONO_REG_INT_REF;
 753         else if (vreg_is_mp (cfg, reg))
 754                 return MONO_REG_INT_MP;
 755         else
 756                 return bank;
 757 }
 758
 759 /*
 760  * Force the spilling of the variable in the symbolic register 'reg', and free
 761  * the hreg it was assigned to.
 762  */
 763 static void
 764 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 765 {
 766         MonoInst *load;
 767         int i, sel, spill;
 768         int *symbolic;
 769         MonoRegState *rs = cfg->rs;
 770
 771         symbolic = rs->symbolic [bank];
 772         sel = rs->vassign [reg];
 773
 774         /* the vreg we need to spill lives in another logical reg bank */
 775         bank = translate_bank (cfg->rs, bank, sel);
 776
 777         /*i = rs->isymbolic [sel];
 778         g_assert (i == reg);*/
 779         i = reg;
 780         spill = ++cfg->spill_count;
 781         rs->vassign [i] = -spill - 1;
 782         if (G_UNLIKELY (bank))
 783                 mono_regstate_free_general (rs, sel, bank);
 784         else
 785                 mono_regstate_free_int (rs, sel);
 786         /* we need to create a spill var and insert a load to sel after the current instruction */
 787         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 788         load->dreg = sel;
 789         load->inst_basereg = cfg->frame_reg;
 790         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 791         insert_after_ins (bb, ins, last, load);
 792         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 793         if (G_UNLIKELY (bank))
 794                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 795         else
 796                 i = mono_regstate_alloc_int (rs, regmask (sel));
 797         g_assert (i == sel);
 798
 799         if (G_UNLIKELY (bank))
 800                 mono_regstate_free_general (rs, sel, bank);
 801         else
 802                 mono_regstate_free_int (rs, sel);
 803 }
 804
 805 /* This isn't defined on older glib versions and on some platforms */
 806 #ifndef G_GUINT64_FORMAT
 807 #define G_GUINT64_FORMAT "ul"
 808 #endif
 809
 810 static int
 811 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 812 {
 813         MonoInst *load;
 814         int i, sel, spill, num_sregs;
 815         int sregs [MONO_MAX_SRC_REGS];
 816         int *symbolic;
 817         MonoRegState *rs = cfg->rs;
 818
 819         symbolic = rs->symbolic [bank];
 820
 821         g_assert (bank < MONO_NUM_REGBANKS);
 822
 823         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 824         /* exclude the registers in the current instruction */
 825         num_sregs = mono_inst_get_src_registers (ins, sregs);
 826         for (i = 0; i < num_sregs; ++i) {
 827                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 828                         if (is_soft_reg (sregs [i], bank))
 829                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 830                         else
 831                                 regmask &= ~ (regmask (sregs [i]));
 832                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 833                 }
 834         }
 835         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 836                 regmask &= ~ (regmask (ins->dreg));
 837                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 838         }
 839
 840         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 841         g_assert (regmask); /* need at least a register we can free */
 842         sel = 0;
 843         /* we should track prev_use and spill the register that's farther */
 844         if (G_UNLIKELY (bank)) {
 845                 for (i = 0; i < regbank_size [bank]; ++i) {
 846                         if (regmask & (regmask (i))) {
 847                                 sel = i;
 848
 849                                 /* the vreg we need to load lives in another logical bank */
 850                                 bank = translate_bank (cfg->rs, bank, sel);
 851
 852                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 853                                 break;
 854                         }
 855                 }
 856
 857                 i = rs->symbolic [bank] [sel];
 858                 spill = ++cfg->spill_count;
 859                 rs->vassign [i] = -spill - 1;
 860                 mono_regstate_free_general (rs, sel, bank);
 861         }
 862         else {
 863                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 864                         if (regmask & (regmask (i))) {
 865                                 sel = i;
 866                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 867                                 break;
 868                         }
 869                 }
 870
 871                 i = rs->isymbolic [sel];
 872                 spill = ++cfg->spill_count;
 873                 rs->vassign [i] = -spill - 1;
 874                 mono_regstate_free_int (rs, sel);
 875         }
 876
 877         /* we need to create a spill var and insert a load to sel after the current instruction */
 878         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 879         load->dreg = sel;
 880         load->inst_basereg = cfg->frame_reg;
 881         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 882         insert_after_ins (bb, ins, last, load);
 883         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 884         if (G_UNLIKELY (bank))
 885                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 886         else
 887                 i = mono_regstate_alloc_int (rs, regmask (sel));
 888         g_assert (i == sel);
 889
 890         return sel;
 891 }
 892
 893 /*
 894  * free_up_hreg:
 895  *
 896  *   Free up the hreg HREG by spilling the vreg allocated to it.
 897  */
 898 static void
 899 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 900 {
 901         if (G_UNLIKELY (bank)) {
 902                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 903                         bank = translate_bank (cfg->rs, bank, hreg);
 904                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 905                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 906                 }
 907         }
 908         else {
 909                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 910                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 911                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 912                 }
 913         }
 914 }
 915
 916 static MonoInst*
 917 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 918 {
 919         MonoInst *copy;
 920
 921         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 922
 923         copy->dreg = dest;
 924         copy->sreg1 = src;
 925         copy->cil_code = ip;
 926         if (ins) {
 927                 mono_bblock_insert_after_ins (bb, ins, copy);
 928                 *last = copy;
 929         }
 930         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 931         return copy;
 932 }
 933
 934 static inline const char*
 935 regbank_to_string (int bank)
 936 {
 937         if (bank == MONO_REG_INT_REF)
 938                 return "REF ";
 939         else if (bank == MONO_REG_INT_MP)
 940                 return "MP ";
 941         else
 942                 return "";
 943 }
 944
 945 static void
 946 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 947 {
 948         MonoInst *store, *def;
 949
 950         bank = get_vreg_bank (cfg, prev_reg, bank);
 951
 952         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 953         store->sreg1 = reg;
 954         store->inst_destbasereg = cfg->frame_reg;
 955         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 956         if (ins) {
 957                 mono_bblock_insert_after_ins (bb, ins, store);
 958                 *last = store;
 959         } else if (insert_before) {
 960                 insert_before_ins (bb, insert_before, store);
 961         } else {
 962                 g_assert_not_reached ();
 963         }
 964         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 965
 966         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 967                 g_assert (prev_reg != -1);
 968                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 969                 def->inst_c0 = spill;
 970                 def->inst_c1 = bank;
 971                 mono_bblock_insert_after_ins (bb, store, def);
 972         }
 973 }
 974
 975 /* flags used in reginfo->flags */
 976 enum {
 977         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 978         MONO_FP_NEEDS_SPILL                     = regmask (1),
 979         MONO_FP_NEEDS_LOAD                      = regmask (2)
 980 };
 981
 982 static inline int
 983 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 984 {
 985         int val;
 986
 987         if (info && info->preferred_mask) {
 988                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 989                 if (val >= 0) {
 990                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 991                         return val;
 992                 }
 993         }
 994
 995         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 996         if (val < 0)
 997                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 998
 999         return val;
1000 }
1001
1002 static inline int
1003 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1004 {
1005         int val;
1006
1007         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1008
1009         if (val < 0)
1010                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1011
1012         return val;
1013 }
1014
1015 static inline int
1016 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1017 {
1018         if (G_UNLIKELY (bank))
1019                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1020         else
1021                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1022 }
1023
1024 static inline void
1025 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1026 {
1027         if (G_UNLIKELY (bank)) {
1028                 int mirrored_bank;
1029
1030                 g_assert (reg >= regbank_size [bank]);
1031                 g_assert (hreg < regbank_size [bank]);
1032                 g_assert (! is_global_freg (hreg));
1033
1034                 rs->vassign [reg] = hreg;
1035                 rs->symbolic [bank] [hreg] = reg;
1036                 rs->free_mask [bank] &= ~ (regmask (hreg));
1037
1038                 mirrored_bank = get_mirrored_bank (bank);
1039                 if (mirrored_bank == -1)
1040                         return;
1041
1042                 /* Make sure the other logical reg bank that this bank shares
1043                  * a single hard reg bank knows that this hard reg is not free.
1044                  */
1045                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1046
1047                 /* Mark the other logical bank that the this bank shares
1048                  * a single hard reg bank with as mirrored.
1049                  */
1050                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1051
1052         }
1053         else {
1054                 g_assert (reg >= MONO_MAX_IREGS);
1055                 g_assert (hreg < MONO_MAX_IREGS);
1056 #ifndef TARGET_ARM
1057                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1058                 g_assert (! is_global_ireg (hreg));
1059 #endif
1060
1061                 rs->vassign [reg] = hreg;
1062                 rs->isymbolic [hreg] = reg;
1063                 rs->ifree_mask &= ~ (regmask (hreg));
1064         }
1065 }
1066
1067 static inline regmask_t
1068 get_callee_mask (const char spec)
1069 {
1070         if (G_UNLIKELY (reg_bank (spec)))
1071                 return regbank_callee_regs [reg_bank (spec)];
1072         return MONO_ARCH_CALLEE_REGS;
1073 }
1074
1075 static gint8 desc_to_fixed_reg [256];
1076 static gboolean desc_to_fixed_reg_inited = FALSE;
1077
1078 #ifndef DISABLE_JIT
1079
1080 /*
1081  * Local register allocation.
1082  * We first scan the list of instructions and we save the liveness info of
1083  * each register (when the register is first used, when it's value is set etc.).
1084  * We also reverse the list of instructions because assigning registers backwards allows
1085  * for more tricks to be used.
1086  */
1087 void
1088 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1089 {
1090         MonoInst *ins, *prev, *last;
1091         MonoInst **tmp;
1092         MonoRegState *rs = cfg->rs;
1093         int i, j, val, max;
1094         RegTrack *reginfo;
1095         const char *spec;
1096         unsigned char spec_src1, spec_dest;
1097         int bank = 0;
1098 #if MONO_ARCH_USE_FPSTACK
1099         gboolean has_fp = FALSE;
1100         int fpstack [8];
1101         int sp = 0;
1102 #endif
1103         int num_sregs = 0;
1104         int sregs [MONO_MAX_SRC_REGS];
1105
1106         if (!bb->code)
1107                 return;
1108
1109         if (!desc_to_fixed_reg_inited) {
1110                 for (i = 0; i < 256; ++i)
1111                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1112                 desc_to_fixed_reg_inited = TRUE;
1113
1114                 /* Validate the cpu description against the info in mini-ops.h */
1115 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1116                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1117                         const char *ispec;
1118
1119                         spec = ins_get_spec (i);
1120                         ispec = INS_INFO (i);
1121
1122                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1123                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1124                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1125                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1126                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1127                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1128                 }
1129 #endif
1130         }
1131
1132         rs->next_vreg = bb->max_vreg;
1133         mono_regstate_assign (rs);
1134
1135         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1136         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1137                 rs->free_mask [i] = regbank_callee_regs [i];
1138
1139         max = rs->next_vreg;
1140
1141         if (cfg->reginfo && cfg->reginfo_len < max)
1142                 cfg->reginfo = NULL;
1143
1144         reginfo = cfg->reginfo;
1145         if (!reginfo) {
1146                 cfg->reginfo_len = MAX (1024, max * 2);
1147                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1148         }
1149         else
1150                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1151
1152         if (cfg->verbose_level > 1) {
1153                 /* print_regtrack reads the info of all variables */
1154                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1155         }
1156
1157         /*
1158          * For large methods, next_vreg can be very large, so g_malloc0 time can
1159          * be prohibitive. So we manually init the reginfo entries used by the
1160          * bblock.
1161          */
1162         for (ins = bb->code; ins; ins = ins->next) {
1163                 spec = ins_get_spec (ins->opcode);
1164
1165                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1166                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1167 #if SIZEOF_REGISTER == 4
1168                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1169                                 /**
1170                                  * In the new IR, the two vregs of the regpair do not alias the
1171                                  * original long vreg. shift the vreg here so the rest of the
1172                                  * allocator doesn't have to care about it.
1173                                  */
1174                                 ins->dreg ++;
1175                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1176                         }
1177 #endif
1178                 }
1179
1180                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1181                 for (j = 0; j < num_sregs; ++j) {
1182                         g_assert (sregs [j] != -1);
1183                         if (sregs [j] < max) {
1184                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1185 #if SIZEOF_REGISTER == 4
1186                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1187                                         sregs [j]++;
1188                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1189                                 }
1190 #endif
1191                         }
1192                 }
1193                 mono_inst_set_src_registers (ins, sregs);
1194         }
1195
1196         /*if (cfg->opt & MONO_OPT_COPYPROP)
1197                 local_copy_prop (cfg, ins);*/
1198
1199         i = 1;
1200         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1201         /* forward pass on the instructions to collect register liveness info */
1202         MONO_BB_FOR_EACH_INS (bb, ins) {
1203                 spec = ins_get_spec (ins->opcode);
1204                 spec_dest = spec [MONO_INST_DEST];
1205
1206                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1207                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1208                 }
1209
1210                 DEBUG (mono_print_ins_index (i, ins));
1211
1212                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1213
1214 #if MONO_ARCH_USE_FPSTACK
1215                 if (dreg_is_fp (spec)) {
1216                         has_fp = TRUE;
1217                 } else {
1218                         for (j = 0; j < num_sregs; ++j) {
1219                                 if (sreg_is_fp (j, spec))
1220                                         has_fp = TRUE;
1221                         }
1222                 }
1223 #endif
1224
1225                 for (j = 0; j < num_sregs; ++j) {
1226                         int sreg = sregs [j];
1227                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1228                         if (sreg_spec) {
1229                                 bank = sreg_bank (j, spec);
1230                                 g_assert (sreg != -1);
1231                                 if (is_soft_reg (sreg, bank))
1232                                         /* This means the vreg is not local to this bb */
1233                                         g_assert (reginfo [sreg].born_in > 0);
1234                                 rs->vassign [sreg] = -1;
1235                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1236                                 //reginfo [ins->sreg2].last_use = i;
1237                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1238                                         /* The virtual register is allocated sequentially */
1239                                         rs->vassign [sreg + 1] = -1;
1240                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1241                                         //reginfo [ins->sreg2 + 1].last_use = i;
1242                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1243                                                 reginfo [sreg + 1].born_in = i;
1244                                 }
1245                         } else {
1246                                 sregs [j] = -1;
1247                         }
1248                 }
1249                 mono_inst_set_src_registers (ins, sregs);
1250
1251                 if (spec_dest) {
1252                         int dest_dreg;
1253
1254                         bank = dreg_bank (spec);
1255                         if (spec_dest != 'b') /* it's not just a base register */
1256                                 reginfo [ins->dreg].killed_in = i;
1257                         g_assert (ins->dreg != -1);
1258                         rs->vassign [ins->dreg] = -1;
1259                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1260                         //reginfo [ins->dreg].last_use = i;
1261                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1262                                 reginfo [ins->dreg].born_in = i;
1263
1264                         dest_dreg = desc_to_fixed_reg [spec_dest];
1265                         if (dest_dreg != -1)
1266                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1267
1268 #ifdef MONO_ARCH_INST_FIXED_MASK
1269                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1270 #endif
1271
1272                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1273                                 /* The virtual register is allocated sequentially */
1274                                 rs->vassign [ins->dreg + 1] = -1;
1275                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1276                                 //reginfo [ins->dreg + 1].last_use = i;
1277                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1278                                         reginfo [ins->dreg + 1].born_in = i;
1279                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1280                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1281                         }
1282                 } else {
1283                         ins->dreg = -1;
1284                 }
1285
1286                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1287                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1288
1289                         MonoCallInst *call = (MonoCallInst*)ins;
1290                         GSList *list;
1291
1292                         list = call->out_ireg_args;
1293                         if (list) {
1294                                 while (list) {
1295                                         guint32 regpair;
1296                                         int reg, hreg;
1297
1298                                         regpair = (guint32)(gssize)(list->data);
1299                                         hreg = regpair >> 24;
1300                                         reg = regpair & 0xffffff;
1301
1302                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1303                                         //reginfo [reg].last_use = i;
1304
1305                                         list = g_slist_next (list);
1306                                 }
1307                         }
1308
1309                         list = call->out_freg_args;
1310                         if (list) {
1311                                 while (list) {
1312                                         guint32 regpair;
1313                                         int reg, hreg;
1314
1315                                         regpair = (guint32)(gssize)(list->data);
1316                                         hreg = regpair >> 24;
1317                                         reg = regpair & 0xffffff;
1318
1319                                         list = g_slist_next (list);
1320                                 }
1321                         }
1322                 }
1323
1324                 ++i;
1325         }
1326
1327         tmp = &last;
1328
1329         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1330         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1331                 int prev_dreg, clob_dreg;
1332                 int dest_dreg, clob_reg;
1333                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1334                 int dreg_high, sreg1_high;
1335                 regmask_t dreg_mask, mask;
1336                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1337                 regmask_t dreg_fixed_mask;
1338                 const unsigned char *ip;
1339                 --i;
1340                 spec = ins_get_spec (ins->opcode);
1341                 spec_src1 = spec [MONO_INST_SRC1];
1342                 spec_dest = spec [MONO_INST_DEST];
1343                 prev_dreg = -1;
1344                 clob_dreg = -1;
1345                 clob_reg = -1;
1346                 dest_dreg = -1;
1347                 dreg_high = -1;
1348                 sreg1_high = -1;
1349                 dreg_mask = get_callee_mask (spec_dest);
1350                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1351                         prev_sregs [j] = -1;
1352                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1353                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1354 #ifdef MONO_ARCH_INST_FIXED_MASK
1355                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1356 #else
1357                         sreg_fixed_masks [j] = 0;
1358 #endif
1359                 }
1360
1361                 DEBUG (printf ("processing:"));
1362                 DEBUG (mono_print_ins_index (i, ins));
1363
1364                 ip = ins->cil_code;
1365
1366                 last = ins;
1367
1368                 /*
1369                  * FIXED REGS
1370                  */
1371                 dest_dreg = desc_to_fixed_reg [spec_dest];
1372                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1373                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1374
1375 #ifdef MONO_ARCH_INST_FIXED_MASK
1376                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1377 #else
1378                 dreg_fixed_mask = 0;
1379 #endif
1380
1381                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1382
1383                 /*
1384                  * TRACK FIXED SREG2, 3, ...
1385                  */
1386                 for (j = 1; j < num_sregs; ++j) {
1387                         int sreg = sregs [j];
1388                         int dest_sreg = dest_sregs [j];
1389
1390                         if (dest_sreg == -1)
1391                                 continue;
1392
1393                         if (j == 2) {
1394                                 int k;
1395
1396                                 /*
1397                                  * CAS.
1398                                  * We need to special case this, since on x86, there are only 3
1399                                  * free registers, and the code below assigns one of them to
1400                                  * sreg, so we can run out of registers when trying to assign
1401                                  * dreg. Instead, we just set up the register masks, and let the
1402                                  * normal sreg2 assignment code handle this. It would be nice to
1403                                  * do this for all the fixed reg cases too, but there is too much
1404                                  * risk of breakage.
1405                                  */
1406
1407                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1408                                 sreg_masks [j] = regmask (dest_sreg);
1409                                 for (k = 0; k < num_sregs; ++k) {
1410                                         if (k != j)
1411                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1412                                 }
1413
1414                                 /*
1415                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1416                                  */
1417                                 for (k = 0; k < num_sregs; ++k) {
1418                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1419                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1420                                 }
1421
1422                                 /*
1423                                  * We can also run out of registers while processing sreg2 if sreg3 is
1424                                  * assigned to another hreg, so spill sreg3 now.
1425                                  */
1426                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1427                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1428                                 }
1429                                 continue;
1430                         }
1431
1432                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1433                                 if (is_global_ireg (sreg)) {
1434                                         int k;
1435                                         /* Argument already in hard reg, need to copy */
1436                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1437                                         insert_before_ins (bb, ins, copy);
1438                                         for (k = 0; k < num_sregs; ++k) {
1439                                                 if (k != j)
1440                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1441                                         }
1442                                 } else {
1443                                         val = rs->vassign [sreg];
1444                                         if (val == -1) {
1445                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1446                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1447                                         } else if (val < -1) {
1448                                                 /* FIXME: */
1449                                                 g_assert_not_reached ();
1450                                         } else {
1451                                                 /* Argument already in hard reg, need to copy */
1452                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1453                                                 int k;
1454
1455                                                 insert_before_ins (bb, ins, copy);
1456                                                 for (k = 0; k < num_sregs; ++k) {
1457                                                         if (k != j)
1458                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1459                                                 }
1460                                                 /*
1461                                                  * Prevent the dreg from being allocate to dest_sreg
1462                                                  * too, since it could force sreg1 to be allocated to
1463                                                  * the same reg on x86.
1464                                                  */
1465                                                 dreg_mask &= ~ (regmask (dest_sreg));
1466                                         }
1467                                 }
1468                         } else {
1469                                 gboolean need_spill = TRUE;
1470                                 gboolean need_assign = TRUE;
1471                                 int k;
1472
1473                                 dreg_mask &= ~ (regmask (dest_sreg));
1474                                 for (k = 0; k < num_sregs; ++k) {
1475                                         if (k != j)
1476                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1477                                 }
1478
1479                                 /*
1480                                  * First check if dreg is assigned to dest_sreg2, since we
1481                                  * can't spill a dreg.
1482                                  */
1483                                 if (spec [MONO_INST_DEST])
1484                                         val = rs->vassign [ins->dreg];
1485                                 else
1486                                         val = -1;
1487                                 if (val == dest_sreg && ins->dreg != sreg) {
1488                                         /*
1489                                          * the destination register is already assigned to
1490                                          * dest_sreg2: we need to allocate another register for it
1491                                          * and then copy from this to dest_sreg2.
1492                                          */
1493                                         int new_dest;
1494                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1495                                         g_assert (new_dest >= 0);
1496                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1497
1498                                         prev_dreg = ins->dreg;
1499                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1500                                         clob_dreg = ins->dreg;
1501                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1502                                         mono_regstate_free_int (rs, dest_sreg);
1503                                         need_spill = FALSE;
1504                                 }
1505
1506                                 if (is_global_ireg (sreg)) {
1507                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1508                                         insert_before_ins (bb, ins, copy);
1509                                         need_assign = FALSE;
1510                                 }
1511                                 else {
1512                                         val = rs->vassign [sreg];
1513                                         if (val == dest_sreg) {
1514                                                 /* sreg2 is already assigned to the correct register */
1515                                                 need_spill = FALSE;
1516                                         } else if (val < -1) {
1517                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1518                                         } else if (val >= 0) {
1519                                                 /* sreg2 already assigned to another register */
1520                                                 /*
1521                                                  * We couldn't emit a copy from val to dest_sreg2, because
1522                                                  * val might be spilled later while processing this
1523                                                  * instruction. So we spill sreg2 so it can be allocated to
1524                                                  * dest_sreg2.
1525                                                  */
1526                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1527                                         }
1528                                 }
1529
1530                                 if (need_spill) {
1531                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1532                                 }
1533
1534                                 if (need_assign) {
1535                                         if (rs->vassign [sreg] < -1) {
1536                                                 int spill;
1537
1538                                                 /* Need to emit a spill store */
1539                                                 spill = - rs->vassign [sreg] - 1;
1540                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1541                                         }
1542                                         /* force-set sreg2 */
1543                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1544                                 }
1545                         }
1546                         sregs [j] = dest_sreg;
1547                 }
1548                 mono_inst_set_src_registers (ins, sregs);
1549
1550                 /*
1551                  * TRACK DREG
1552                  */
1553                 bank = dreg_bank (spec);
1554                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1555                         prev_dreg = ins->dreg;
1556                 }
1557
1558                 if (spec_dest == 'b') {
1559                         /*
1560                          * The dest reg is read by the instruction, not written, so
1561                          * avoid allocating sreg1/sreg2 to the same reg.
1562                          */
1563                         if (dest_sregs [0] != -1)
1564                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1565                         for (j = 1; j < num_sregs; ++j) {
1566                                 if (dest_sregs [j] != -1)
1567                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1568                         }
1569
1570                         val = rs->vassign [ins->dreg];
1571                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1572                                 /* DREG is already allocated to a register needed for sreg1 */
1573                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1574                         }
1575                 }
1576
1577                 /*
1578                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1579                  * various complex situations.
1580                  */
1581                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1582                         guint32 dreg2, dest_dreg2;
1583
1584                         g_assert (is_soft_reg (ins->dreg, bank));
1585
1586                         if (dest_dreg != -1) {
1587                                 if (rs->vassign [ins->dreg] != dest_dreg)
1588                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1589
1590                                 dreg2 = ins->dreg + 1;
1591                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1592                                 if (dest_dreg2 != -1) {
1593                                         if (rs->vassign [dreg2] != dest_dreg2)
1594                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1595                                 }
1596                         }
1597                 }
1598
1599                 if (dreg_fixed_mask) {
1600                         g_assert (!bank);
1601                         if (is_global_ireg (ins->dreg)) {
1602                                 /*
1603                                  * The argument is already in a hard reg, but that reg is
1604                                  * not usable by this instruction, so allocate a new one.
1605                                  */
1606                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1607                                 if (val < 0)
1608                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1609                                 mono_regstate_free_int (rs, val);
1610                                 dest_dreg = val;
1611
1612                                 /* Fall through */
1613                         }
1614                         else
1615                                 dreg_mask &= dreg_fixed_mask;
1616                 }
1617
1618                 if (is_soft_reg (ins->dreg, bank)) {
1619                         val = rs->vassign [ins->dreg];
1620
1621                         if (val < 0) {
1622                                 int spill = 0;
1623                                 if (val < -1) {
1624                                         /* the register gets spilled after this inst */
1625                                         spill = -val -1;
1626                                 }
1627                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1628                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1629                                 if (spill)
1630                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1631                         }
1632
1633                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1634                         ins->dreg = val;
1635                 }
1636
1637                 /* Handle regpairs */
1638                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1639                         int reg2 = prev_dreg + 1;
1640
1641                         g_assert (!bank);
1642                         g_assert (prev_dreg > -1);
1643                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1644                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1645 #ifdef TARGET_X86
1646                         /* bug #80489 */
1647                         mask &= ~regmask (X86_ECX);
1648 #endif
1649                         val = rs->vassign [reg2];
1650                         if (val < 0) {
1651                                 int spill = 0;
1652                                 if (val < -1) {
1653                                         /* the register gets spilled after this inst */
1654                                         spill = -val -1;
1655                                 }
1656                                 val = mono_regstate_alloc_int (rs, mask);
1657                                 if (val < 0)
1658                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1659                                 if (spill)
1660                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1661                         }
1662                         else {
1663                                 if (! (mask & (regmask (val)))) {
1664                                         val = mono_regstate_alloc_int (rs, mask);
1665                                         if (val < 0)
1666                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1667
1668                                         /* Reallocate hreg to the correct register */
1669                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1670
1671                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1672                                 }
1673                         }
1674
1675                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1676                         assign_reg (cfg, rs, reg2, val, bank);
1677
1678                         dreg_high = val;
1679                         ins->backend.reg3 = val;
1680
1681                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1682                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1683                                 mono_regstate_free_int (rs, val);
1684                         }
1685                 }
1686
1687                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1688                         /*
1689                          * In theory, we could free up the hreg even if the vreg is alive,
1690                          * but branches inside bblocks force us to assign the same hreg
1691                          * to a vreg every time it is encountered.
1692                          */
1693                         int dreg = rs->vassign [prev_dreg];
1694                         g_assert (dreg >= 0);
1695                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1696                         if (G_UNLIKELY (bank))
1697                                 mono_regstate_free_general (rs, dreg, bank);
1698                         else
1699                                 mono_regstate_free_int (rs, dreg);
1700                         rs->vassign [prev_dreg] = -1;
1701                 }
1702
1703                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1704                         /* this instruction only outputs to dest_dreg, need to copy */
1705                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1706                         ins->dreg = dest_dreg;
1707
1708                         if (G_UNLIKELY (bank)) {
1709                                 /* the register we need to free up may be used in another logical regbank
1710                                  * so do a translate just in case.
1711                                  */
1712                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1713                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1714                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1715                         }
1716                         else {
1717                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1718                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1719                         }
1720                 }
1721
1722                 if (spec_dest == 'b') {
1723                         /*
1724                          * The dest reg is read by the instruction, not written, so
1725                          * avoid allocating sreg1/sreg2 to the same reg.
1726                          */
1727                         for (j = 0; j < num_sregs; ++j)
1728                                 if (!sreg_bank (j, spec))
1729                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1730                 }
1731
1732                 /*
1733                  * TRACK CLOBBERING
1734                  */
1735                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1736                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1737                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1738                 }
1739
1740                 if (spec [MONO_INST_CLOB] == 'c') {
1741                         int j, s, dreg, dreg2, cur_bank;
1742                         guint64 clob_mask;
1743
1744                         clob_mask = MONO_ARCH_CALLEE_REGS;
1745
1746                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1747                                 /*
1748                                  * Need to avoid spilling the dreg since the dreg is not really
1749                                  * clobbered by the call.
1750                                  */
1751                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1752                                         dreg = rs->vassign [prev_dreg];
1753                                 else
1754                                         dreg = -1;
1755
1756                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1757                                         dreg2 = rs->vassign [prev_dreg + 1];
1758                                 else
1759                                         dreg2 = -1;
1760
1761                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1762                                         s = regmask (j);
1763                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1764                                                 if ((j != dreg) && (j != dreg2))
1765                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1766                                                 else if (rs->isymbolic [j])
1767                                                         /* The hreg is assigned to the dreg of this instruction */
1768                                                         rs->vassign [rs->isymbolic [j]] = -1;
1769                                                 mono_regstate_free_int (rs, j);
1770                                         }
1771                                 }
1772                         }
1773
1774                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1775                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1776                                         clob_mask = regbank_callee_regs [cur_bank];
1777                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1778                                                 dreg = rs->vassign [prev_dreg];
1779                                         else
1780                                                 dreg = -1;
1781
1782                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1783
1784                                                 /* we are looping though the banks in the outer loop
1785                                                  * so, we don't need to deal with mirrored hregs
1786                                                  * because we will get them in one of the other bank passes.
1787                                                  */
1788                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1789                                                         continue;
1790
1791                                                 s = regmask (j);
1792                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1793                                                         if (j != dreg)
1794                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1795                                                         else if (rs->symbolic [cur_bank] [j])
1796                                                                 /* The hreg is assigned to the dreg of this instruction */
1797                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1798                                                         mono_regstate_free_general (rs, j, cur_bank);
1799                                                 }
1800                                         }
1801                                 }
1802                         }
1803                 }
1804
1805                 /*
1806                  * TRACK ARGUMENT REGS
1807                  */
1808                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1809                         MonoCallInst *call = (MonoCallInst*)ins;
1810                         GSList *list;
1811
1812                         /*
1813                          * This needs to be done before assigning sreg1, so sreg1 will
1814                          * not be assigned one of the argument regs.
1815                          */
1816
1817                         /*
1818                          * Assign all registers in call->out_reg_args to the proper
1819                          * argument registers.
1820                          */
1821
1822                         list = call->out_ireg_args;
1823                         if (list) {
1824                                 while (list) {
1825                                         guint32 regpair;
1826                                         int reg, hreg;
1827
1828                                         regpair = (guint32)(gssize)(list->data);
1829                                         hreg = regpair >> 24;
1830                                         reg = regpair & 0xffffff;
1831
1832                                         assign_reg (cfg, rs, reg, hreg, 0);
1833
1834                                         sreg_masks [0] &= ~(regmask (hreg));
1835
1836                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1837
1838                                         list = g_slist_next (list);
1839                                 }
1840                         }
1841
1842                         list = call->out_freg_args;
1843                         if (list) {
1844                                 while (list) {
1845                                         guint32 regpair;
1846                                         int reg, hreg;
1847
1848                                         regpair = (guint32)(gssize)(list->data);
1849                                         hreg = regpair >> 24;
1850                                         reg = regpair & 0xffffff;
1851
1852                                         assign_reg (cfg, rs, reg, hreg, 1);
1853
1854                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1855
1856                                         list = g_slist_next (list);
1857                                 }
1858                         }
1859                 }
1860
1861                 /*
1862                  * TRACK SREG1
1863                  */
1864                 bank = sreg1_bank (spec);
1865                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1866                         int sreg1 = sregs [0];
1867                         int dest_sreg1 = dest_sregs [0];
1868
1869                         g_assert (is_soft_reg (sreg1, bank));
1870
1871                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1872                         if (dest_sreg1 != -1)
1873                                 g_assert (dest_sreg1 == ins->dreg);
1874                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1875                         g_assert (val >= 0);
1876
1877                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1878                                 // FIXME:
1879                                 g_assert_not_reached ();
1880
1881                         assign_reg (cfg, rs, sreg1, val, bank);
1882
1883                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1884
1885                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1886                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1887                         g_assert (val >= 0);
1888
1889                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1890                                 // FIXME:
1891                                 g_assert_not_reached ();
1892
1893                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1894
1895                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1896
1897                         /* Skip rest of this section */
1898                         dest_sregs [0] = -1;
1899                 }
1900
1901                 if (sreg_fixed_masks [0]) {
1902                         g_assert (!bank);
1903                         if (is_global_ireg (sregs [0])) {
1904                                 /*
1905                                  * The argument is already in a hard reg, but that reg is
1906                                  * not usable by this instruction, so allocate a new one.
1907                                  */
1908                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1909                                 if (val < 0)
1910                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1911                                 mono_regstate_free_int (rs, val);
1912                                 dest_sregs [0] = val;
1913
1914                                 /* Fall through to the dest_sreg1 != -1 case */
1915                         }
1916                         else
1917                                 sreg_masks [0] &= sreg_fixed_masks [0];
1918                 }
1919
1920                 if (dest_sregs [0] != -1) {
1921                         sreg_masks [0] = regmask (dest_sregs [0]);
1922
1923                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1924                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1925                         }
1926                         if (is_global_ireg (sregs [0])) {
1927                                 /* The argument is already in a hard reg, need to copy */
1928                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1929                                 insert_before_ins (bb, ins, copy);
1930                                 sregs [0] = dest_sregs [0];
1931                         }
1932                 }
1933
1934                 if (is_soft_reg (sregs [0], bank)) {
1935                         val = rs->vassign [sregs [0]];
1936                         prev_sregs [0] = sregs [0];
1937                         if (val < 0) {
1938                                 int spill = 0;
1939                                 if (val < -1) {
1940                                         /* the register gets spilled after this inst */
1941                                         spill = -val -1;
1942                                 }
1943
1944                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1945                                         /*
1946                                          * Allocate the same hreg to sreg1 as well so the
1947                                          * peephole can get rid of the move.
1948                                          */
1949                                         sreg_masks [0] = regmask (ins->dreg);
1950                                 }
1951
1952                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1953                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1954                                         sreg_masks [0] = regmask (ins->dreg);
1955
1956                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1957                                 assign_reg (cfg, rs, sregs [0], val, bank);
1958                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1959
1960                                 if (spill) {
1961                                         /*
1962                                          * Need to insert before the instruction since it can
1963                                          * overwrite sreg1.
1964                                          */
1965                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1966                                 }
1967                         }
1968                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1969                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1970                                 insert_before_ins (bb, ins, copy);
1971                                 for (j = 1; j < num_sregs; ++j)
1972                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1973                                 val = dest_sregs [0];
1974                         }
1975
1976                         sregs [0] = val;
1977                 }
1978                 else {
1979                         prev_sregs [0] = -1;
1980                 }
1981                 mono_inst_set_src_registers (ins, sregs);
1982
1983                 for (j = 1; j < num_sregs; ++j)
1984                         sreg_masks [j] &= ~(regmask (sregs [0]));
1985
1986                 /* Handle the case when sreg1 is a regpair but dreg is not */
1987                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1988                         int reg2 = prev_sregs [0] + 1;
1989
1990                         g_assert (!bank);
1991                         g_assert (prev_sregs [0] > -1);
1992                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1993                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1994                         val = rs->vassign [reg2];
1995                         if (val < 0) {
1996                                 int spill = 0;
1997                                 if (val < -1) {
1998                                         /* the register gets spilled after this inst */
1999                                         spill = -val -1;
2000                                 }
2001                                 val = mono_regstate_alloc_int (rs, mask);
2002                                 if (val < 0)
2003                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2004                                 if (spill)
2005                                         g_assert_not_reached ();
2006                         }
2007                         else {
2008                                 if (! (mask & (regmask (val)))) {
2009                                         /* The vreg is already allocated to a wrong hreg */
2010                                         /* FIXME: */
2011                                         g_assert_not_reached ();
2012 #if 0
2013                                         val = mono_regstate_alloc_int (rs, mask);
2014                                         if (val < 0)
2015                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2016
2017                                         /* Reallocate hreg to the correct register */
2018                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2019
2020                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2021 #endif
2022                                 }
2023                         }
2024
2025                         sreg1_high = val;
2026                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2027                         assign_reg (cfg, rs, reg2, val, bank);
2028                 }
2029
2030                 /* Handle dreg==sreg1 */
2031                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2032                         MonoInst *sreg2_copy = NULL;
2033                         MonoInst *copy;
2034                         int bank = reg_bank (spec_src1);
2035
2036                         if (ins->dreg == sregs [1]) {
2037                                 /*
2038                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2039                                  * register for it.
2040                                  */
2041                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2042
2043                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2044                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2045                                 prev_sregs [1] = sregs [1] = reg2;
2046
2047                                 if (G_UNLIKELY (bank))
2048                                         mono_regstate_free_general (rs, reg2, bank);
2049                                 else
2050                                         mono_regstate_free_int (rs, reg2);
2051                         }
2052
2053                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2054                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2055                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2056                                         /* FIXME: */
2057                                         g_assert_not_reached ();
2058
2059                                 /*
2060                                  * sreg1 and dest are already allocated to the same regpair by the
2061                                  * SREG1 allocation code.
2062                                  */
2063                                 g_assert (sregs [0] == ins->dreg);
2064                                 g_assert (dreg_high == sreg1_high);
2065                         }
2066
2067                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2068                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2069                         insert_before_ins (bb, ins, copy);
2070
2071                         if (sreg2_copy)
2072                                 insert_before_ins (bb, copy, sreg2_copy);
2073
2074                         /*
2075                          * Need to prevent sreg2 to be allocated to sreg1, since that
2076                          * would screw up the previous copy.
2077                          */
2078                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2079                         /* we set sreg1 to dest as well */
2080                         prev_sregs [0] = sregs [0] = ins->dreg;
2081                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2082                 }
2083                 mono_inst_set_src_registers (ins, sregs);
2084
2085                 /*
2086                  * TRACK SREG2, 3, ...
2087                  */
2088                 for (j = 1; j < num_sregs; ++j) {
2089                         int k;
2090
2091                         bank = sreg_bank (j, spec);
2092                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2093                                 g_assert_not_reached ();
2094
2095                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2096                                 /*
2097                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2098                                  * allocating it to the fixed reg.
2099                                  */
2100                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2101                                 insert_before_ins (bb, ins, copy);
2102                                 sregs [j] = dest_sregs [j];
2103                         } else if (is_soft_reg (sregs [j], bank)) {
2104                                 val = rs->vassign [sregs [j]];
2105
2106                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2107                                         /*
2108                                          * The sreg is already allocated to a hreg, but not to the fixed
2109                                          * reg required by the instruction. Spill the sreg, so it can be
2110                                          * allocated to the fixed reg by the code below.
2111                                          */
2112                                         /* Currently, this code should only be hit for CAS */
2113                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2114                                         val = rs->vassign [sregs [j]];
2115                                 }
2116
2117                                 if (val < 0) {
2118                                         int spill = 0;
2119                                         if (val < -1) {
2120                                                 /* the register gets spilled after this inst */
2121                                                 spill = -val -1;
2122                                         }
2123                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2124                                         assign_reg (cfg, rs, sregs [j], val, bank);
2125                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2126                                         if (spill) {
2127                                                 /*
2128                                                  * Need to insert before the instruction since it can
2129                                                  * overwrite sreg2.
2130                                                  */
2131                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2132                                         }
2133                                 }
2134                                 sregs [j] = val;
2135                                 for (k = j + 1; k < num_sregs; ++k)
2136                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2137                         }
2138                         else {
2139                                 prev_sregs [j] = -1;
2140                         }
2141                 }
2142                 mono_inst_set_src_registers (ins, sregs);
2143
2144                 /* Sanity check */
2145                 /* Do this only for CAS for now */
2146                 for (j = 1; j < num_sregs; ++j) {
2147                         int sreg = sregs [j];
2148                         int dest_sreg = dest_sregs [j];
2149
2150                         if (j == 2 && dest_sreg != -1) {
2151                                 int k;
2152
2153                                 g_assert (sreg == dest_sreg);
2154
2155                                 for (k = 0; k < num_sregs; ++k) {
2156                                         if (k != j)
2157                                                 g_assert (sregs [k] != dest_sreg);
2158                                 }
2159                         }
2160                 }
2161
2162                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2163                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2164                         mono_regstate_free_int (rs, ins->sreg1);
2165                 }
2166                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2167                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2168                         mono_regstate_free_int (rs, ins->sreg2);
2169                 }*/
2170
2171                 DEBUG (mono_print_ins_index (i, ins));
2172         }
2173
2174         // FIXME: Set MAX_FREGS to 8
2175         // FIXME: Optimize generated code
2176 #if MONO_ARCH_USE_FPSTACK
2177         /*
2178          * Make a forward pass over the code, simulating the fp stack, making sure the
2179          * arguments required by the fp opcodes are at the top of the stack.
2180          */
2181         if (has_fp) {
2182                 MonoInst *prev = NULL;
2183                 MonoInst *fxch;
2184                 int tmp;
2185
2186                 g_assert (num_sregs <= 2);
2187
2188                 for (ins = bb->code; ins; ins = ins->next) {
2189                         spec = ins_get_spec (ins->opcode);
2190
2191                         DEBUG (printf ("processing:"));
2192                         DEBUG (mono_print_ins_index (0, ins));
2193
2194                         if (ins->opcode == OP_FMOVE) {
2195                                 /* Do it by renaming the source to the destination on the stack */
2196                                 // FIXME: Is this correct ?
2197                                 for (i = 0; i < sp; ++i)
2198                                         if (fpstack [i] == ins->sreg1)
2199                                                 fpstack [i] = ins->dreg;
2200                                 prev = ins;
2201                                 continue;
2202                         }
2203
2204                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2205                                 /* Arg1 must be in %st(1) */
2206                                 g_assert (prev);
2207
2208                                 i = 0;
2209                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2210                                         i ++;
2211                                 g_assert (i < sp);
2212
2213                                 if (sp - 1 - i > 0) {
2214                                         /* First move it to %st(0) */
2215                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2216
2217                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2218                                         fxch->inst_imm = sp - 1 - i;
2219
2220                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2221                                         prev = fxch;
2222
2223                                         tmp = fpstack [sp - 1];
2224                                         fpstack [sp - 1] = fpstack [i];
2225                                         fpstack [i] = tmp;
2226                                 }
2227
2228                                 /* Then move it to %st(1) */
2229                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2230
2231                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2232                                 fxch->inst_imm = 1;
2233
2234                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2235                                 prev = fxch;
2236
2237                                 tmp = fpstack [sp - 1];
2238                                 fpstack [sp - 1] = fpstack [sp - 2];
2239                                 fpstack [sp - 2] = tmp;
2240                         }
2241
2242                         if (sreg2_is_fp (spec)) {
2243                                 g_assert (sp > 0);
2244
2245                                 if (fpstack [sp - 1] != ins->sreg2) {
2246                                         g_assert (prev);
2247
2248                                         i = 0;
2249                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2250                                                 i ++;
2251                                         g_assert (i < sp);
2252
2253                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2254
2255                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2256                                         fxch->inst_imm = sp - 1 - i;
2257
2258                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2259                                         prev = fxch;
2260
2261                                         tmp = fpstack [sp - 1];
2262                                         fpstack [sp - 1] = fpstack [i];
2263                                         fpstack [i] = tmp;
2264                                 }
2265
2266                                 sp --;
2267                         }
2268
2269                         if (sreg1_is_fp (spec)) {
2270                                 g_assert (sp > 0);
2271
2272                                 if (fpstack [sp - 1] != ins->sreg1) {
2273                                         g_assert (prev);
2274
2275                                         i = 0;
2276                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2277                                                 i ++;
2278                                         g_assert (i < sp);
2279
2280                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2281
2282                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2283                                         fxch->inst_imm = sp - 1 - i;
2284
2285                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2286                                         prev = fxch;
2287
2288                                         tmp = fpstack [sp - 1];
2289                                         fpstack [sp - 1] = fpstack [i];
2290                                         fpstack [i] = tmp;
2291                                 }
2292
2293                                 sp --;
2294                         }
2295
2296                         if (dreg_is_fp (spec)) {
2297                                 g_assert (sp < 8);
2298                                 fpstack [sp ++] = ins->dreg;
2299                         }
2300
2301                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2302                                 printf ("\t[");
2303                                 for (i = 0; i < sp; ++i)
2304                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2305                                 printf ("]\n");
2306                         }
2307
2308                         prev = ins;
2309                 }
2310
2311                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2312                         /* Remove remaining items from the fp stack */
2313                         /*
2314                          * These can remain for example as a result of a dead fmove like in
2315                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2316                          */
2317                         while (sp) {
2318                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2319                                 mono_add_ins_to_end (bb, ins);
2320                                 sp --;
2321                         }
2322                 }
2323         }
2324 #endif
2325 }
2326
2327 CompRelation
2328 mono_opcode_to_cond (int opcode)
2329 {
2330         switch (opcode) {
2331         case OP_CEQ:
2332         case OP_IBEQ:
2333         case OP_ICEQ:
2334         case OP_LBEQ:
2335         case OP_LCEQ:
2336         case OP_FBEQ:
2337         case OP_FCEQ:
2338         case OP_COND_EXC_EQ:
2339         case OP_COND_EXC_IEQ:
2340         case OP_CMOV_IEQ:
2341         case OP_CMOV_LEQ:
2342                 return CMP_EQ;
2343         case OP_IBNE_UN:
2344         case OP_LBNE_UN:
2345         case OP_FBNE_UN:
2346         case OP_COND_EXC_NE_UN:
2347         case OP_COND_EXC_INE_UN:
2348         case OP_CMOV_INE_UN:
2349         case OP_CMOV_LNE_UN:
2350                 return CMP_NE;
2351         case OP_IBLE:
2352         case OP_LBLE:
2353         case OP_FBLE:
2354         case OP_CMOV_ILE:
2355         case OP_CMOV_LLE:
2356                 return CMP_LE;
2357         case OP_IBGE:
2358         case OP_LBGE:
2359         case OP_FBGE:
2360         case OP_CMOV_IGE:
2361         case OP_CMOV_LGE:
2362                 return CMP_GE;
2363         case OP_CLT:
2364         case OP_IBLT:
2365         case OP_ICLT:
2366         case OP_LBLT:
2367         case OP_LCLT:
2368         case OP_FBLT:
2369         case OP_FCLT:
2370         case OP_COND_EXC_LT:
2371         case OP_COND_EXC_ILT:
2372         case OP_CMOV_ILT:
2373         case OP_CMOV_LLT:
2374                 return CMP_LT;
2375         case OP_CGT:
2376         case OP_IBGT:
2377         case OP_ICGT:
2378         case OP_LBGT:
2379         case OP_LCGT:
2380         case OP_FBGT:
2381         case OP_FCGT:
2382         case OP_COND_EXC_GT:
2383         case OP_COND_EXC_IGT:
2384         case OP_CMOV_IGT:
2385         case OP_CMOV_LGT:
2386                 return CMP_GT;
2387
2388         case OP_IBLE_UN:
2389         case OP_LBLE_UN:
2390         case OP_FBLE_UN:
2391         case OP_COND_EXC_LE_UN:
2392         case OP_COND_EXC_ILE_UN:
2393         case OP_CMOV_ILE_UN:
2394         case OP_CMOV_LLE_UN:
2395                 return CMP_LE_UN;
2396         case OP_IBGE_UN:
2397         case OP_LBGE_UN:
2398         case OP_FBGE_UN:
2399         case OP_CMOV_IGE_UN:
2400         case OP_CMOV_LGE_UN:
2401                 return CMP_GE_UN;
2402         case OP_CLT_UN:
2403         case OP_IBLT_UN:
2404         case OP_ICLT_UN:
2405         case OP_LBLT_UN:
2406         case OP_LCLT_UN:
2407         case OP_FBLT_UN:
2408         case OP_FCLT_UN:
2409         case OP_COND_EXC_LT_UN:
2410         case OP_COND_EXC_ILT_UN:
2411         case OP_CMOV_ILT_UN:
2412         case OP_CMOV_LLT_UN:
2413                 return CMP_LT_UN;
2414         case OP_CGT_UN:
2415         case OP_IBGT_UN:
2416         case OP_ICGT_UN:
2417         case OP_LBGT_UN:
2418         case OP_LCGT_UN:
2419         case OP_FCGT_UN:
2420         case OP_FBGT_UN:
2421         case OP_COND_EXC_GT_UN:
2422         case OP_COND_EXC_IGT_UN:
2423         case OP_CMOV_IGT_UN:
2424         case OP_CMOV_LGT_UN:
2425                 return CMP_GT_UN;
2426         default:
2427                 printf ("%s\n", mono_inst_name (opcode));
2428                 g_assert_not_reached ();
2429                 return 0;
2430         }
2431 }
2432
2433 CompRelation
2434 mono_negate_cond (CompRelation cond)
2435 {
2436         switch (cond) {
2437         case CMP_EQ:
2438                 return CMP_NE;
2439         case CMP_NE:
2440                 return CMP_EQ;
2441         case CMP_LE:
2442                 return CMP_GT;
2443         case CMP_GE:
2444                 return CMP_LT;
2445         case CMP_LT:
2446                 return CMP_GE;
2447         case CMP_GT:
2448                 return CMP_LE;
2449         case CMP_LE_UN:
2450                 return CMP_GT_UN;
2451         case CMP_GE_UN:
2452                 return CMP_LT_UN;
2453         case CMP_LT_UN:
2454                 return CMP_GE_UN;
2455         case CMP_GT_UN:
2456                 return CMP_LE_UN;
2457         default:
2458                 g_assert_not_reached ();
2459         }
2460 }
2461
2462 CompType
2463 mono_opcode_to_type (int opcode, int cmp_opcode)
2464 {
2465         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2466                 return CMP_TYPE_L;
2467         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2468                 return CMP_TYPE_I;
2469         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2470                 return CMP_TYPE_I;
2471         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2472                 return CMP_TYPE_L;
2473         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2474                 return CMP_TYPE_L;
2475         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2476                 return CMP_TYPE_F;
2477         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2478                 return CMP_TYPE_F;
2479         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2480                 return CMP_TYPE_I;
2481         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2482                 switch (cmp_opcode) {
2483                 case OP_ICOMPARE:
2484                 case OP_ICOMPARE_IMM:
2485                         return CMP_TYPE_I;
2486                 default:
2487                         return CMP_TYPE_L;
2488                 }
2489         } else {
2490                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2491                 return 0;
2492         }
2493 }
2494
2495 #endif /* DISABLE_JIT */
2496
2497 gboolean
2498 mono_is_regsize_var (MonoType *t)
2499 {
2500         if (t->byref)
2501                 return TRUE;
2502         t = mono_type_get_underlying_type (t);
2503         switch (t->type) {
2504         case MONO_TYPE_BOOLEAN:
2505         case MONO_TYPE_CHAR:
2506         case MONO_TYPE_I1:
2507         case MONO_TYPE_U1:
2508         case MONO_TYPE_I2:
2509         case MONO_TYPE_U2:
2510         case MONO_TYPE_I4:
2511         case MONO_TYPE_U4:
2512         case MONO_TYPE_I:
2513         case MONO_TYPE_U:
2514         case MONO_TYPE_PTR:
2515         case MONO_TYPE_FNPTR:
2516 #if SIZEOF_REGISTER == 8
2517         case MONO_TYPE_I8:
2518         case MONO_TYPE_U8:
2519 #endif
2520                 return TRUE;
2521         case MONO_TYPE_OBJECT:
2522         case MONO_TYPE_STRING:
2523         case MONO_TYPE_CLASS:
2524         case MONO_TYPE_SZARRAY:
2525         case MONO_TYPE_ARRAY:
2526                 return TRUE;
2527         case MONO_TYPE_GENERICINST:
2528                 if (!mono_type_generic_inst_is_valuetype (t))
2529                         return TRUE;
2530                 return FALSE;
2531         case MONO_TYPE_VALUETYPE:
2532                 return FALSE;
2533         default:
2534                 return FALSE;
2535         }
2536 }
2537
2538 #ifndef DISABLE_JIT
2539
2540 /*
2541  * mono_peephole_ins:
2542  *
2543  *   Perform some architecture independent peephole optimizations.
2544  */
2545 void
2546 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2547 {
2548         MonoInst *last_ins = ins->prev;
2549
2550         switch (ins->opcode) {
2551         case OP_MUL_IMM:
2552                 /* remove unnecessary multiplication with 1 */
2553                 if (ins->inst_imm == 1) {
2554                         if (ins->dreg != ins->sreg1)
2555                                 ins->opcode = OP_MOVE;
2556                         else
2557                                 MONO_DELETE_INS (bb, ins);
2558                 }
2559                 break;
2560         case OP_LOAD_MEMBASE:
2561         case OP_LOADI4_MEMBASE:
2562                 /*
2563                  * Note: if reg1 = reg2 the load op is removed
2564                  *
2565                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2566                  * OP_LOAD_MEMBASE offset(basereg), reg2
2567                  * -->
2568                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2569                  * OP_MOVE reg1, reg2
2570                  */
2571                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2572                         last_ins = last_ins->prev;
2573                 if (last_ins &&
2574                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2575                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2576                         ins->inst_basereg == last_ins->inst_destbasereg &&
2577                         ins->inst_offset == last_ins->inst_offset) {
2578                         if (ins->dreg == last_ins->sreg1) {
2579                                 MONO_DELETE_INS (bb, ins);
2580                                 break;
2581                         } else {
2582                                 ins->opcode = OP_MOVE;
2583                                 ins->sreg1 = last_ins->sreg1;
2584                         }
2585
2586                         /*
2587                          * Note: reg1 must be different from the basereg in the second load
2588                          * Note: if reg1 = reg2 is equal then second load is removed
2589                          *
2590                          * OP_LOAD_MEMBASE offset(basereg), reg1
2591                          * OP_LOAD_MEMBASE offset(basereg), reg2
2592                          * -->
2593                          * OP_LOAD_MEMBASE offset(basereg), reg1
2594                          * OP_MOVE reg1, reg2
2595                          */
2596                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2597                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2598                           ins->inst_basereg != last_ins->dreg &&
2599                           ins->inst_basereg == last_ins->inst_basereg &&
2600                           ins->inst_offset == last_ins->inst_offset) {
2601
2602                         if (ins->dreg == last_ins->dreg) {
2603                                 MONO_DELETE_INS (bb, ins);
2604                         } else {
2605                                 ins->opcode = OP_MOVE;
2606                                 ins->sreg1 = last_ins->dreg;
2607                         }
2608
2609                         //g_assert_not_reached ();
2610
2611 #if 0
2612                         /*
2613                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2614                          * OP_LOAD_MEMBASE offset(basereg), reg
2615                          * -->
2616                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2617                          * OP_ICONST reg, imm
2618                          */
2619                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2620                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2621                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2622                                    ins->inst_offset == last_ins->inst_offset) {
2623                         ins->opcode = OP_ICONST;
2624                         ins->inst_c0 = last_ins->inst_imm;
2625                         g_assert_not_reached (); // check this rule
2626 #endif
2627                 }
2628                 break;
2629         case OP_LOADI1_MEMBASE:
2630         case OP_LOADU1_MEMBASE:
2631                 /*
2632                  * Note: if reg1 = reg2 the load op is removed
2633                  *
2634                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2635                  * OP_LOAD_MEMBASE offset(basereg), reg2
2636                  * -->
2637                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2638                  * OP_MOVE reg1, reg2
2639                  */
2640                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2641                         ins->inst_basereg == last_ins->inst_destbasereg &&
2642                         ins->inst_offset == last_ins->inst_offset) {
2643                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2644                         ins->sreg1 = last_ins->sreg1;
2645                 }
2646                 break;
2647         case OP_LOADI2_MEMBASE:
2648         case OP_LOADU2_MEMBASE:
2649                 /*
2650                  * Note: if reg1 = reg2 the load op is removed
2651                  *
2652                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2653                  * OP_LOAD_MEMBASE offset(basereg), reg2
2654                  * -->
2655                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2656                  * OP_MOVE reg1, reg2
2657                  */
2658                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2659                         ins->inst_basereg == last_ins->inst_destbasereg &&
2660                         ins->inst_offset == last_ins->inst_offset) {
2661 #if SIZEOF_REGISTER == 8
2662                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2663 #else
2664                         /* The definition of OP_PCONV_TO_U2 is wrong */
2665                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2666 #endif
2667                         ins->sreg1 = last_ins->sreg1;
2668                 }
2669                 break;
2670         case OP_MOVE:
2671         case OP_FMOVE:
2672                 /*
2673                  * Removes:
2674                  *
2675                  * OP_MOVE reg, reg
2676                  */
2677                 if (ins->dreg == ins->sreg1) {
2678                         MONO_DELETE_INS (bb, ins);
2679                         break;
2680                 }
2681                 /*
2682                  * Removes:
2683                  *
2684                  * OP_MOVE sreg, dreg
2685                  * OP_MOVE dreg, sreg
2686                  */
2687                 if (last_ins && last_ins->opcode == ins->opcode &&
2688                         ins->sreg1 == last_ins->dreg &&
2689                         ins->dreg == last_ins->sreg1) {
2690                         MONO_DELETE_INS (bb, ins);
2691                 }
2692                 break;
2693         case OP_NOP:
2694                 MONO_DELETE_INS (bb, ins);
2695                 break;
2696         }
2697 }
2698
2699 #endif /* DISABLE_JIT */