mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 const char*
 423 mono_ji_type_to_string (MonoJumpInfoType type)
 424 {
 425         return patch_info_str [type];
 426 }
 427
 428 void
 429 mono_print_ji (const MonoJumpInfo *ji)
 430 {
 431         switch (ji->type) {
 432         case MONO_PATCH_INFO_RGCTX_FETCH: {
 433                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 434
 435                 printf ("[RGCTX_FETCH ");
 436                 mono_print_ji (entry->data);
 437                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 438                 break;
 439         }
 440         case MONO_PATCH_INFO_METHODCONST: {
 441                 char *s = mono_method_full_name (ji->data.method, TRUE);
 442                 printf ("[METHODCONST - %s]", s);
 443                 g_free (s);
 444                 break;
 445         }
 446         case MONO_PATCH_INFO_INTERNAL_METHOD: {
 447                 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
 448                 break;
 449         }
 450         default:
 451                 printf ("[%s]", patch_info_str [ji->type]);
 452                 break;
 453         }
 454 }
 455
 456 void
 457 mono_print_ins_index (int i, MonoInst *ins)
 458 {
 459         GString *buf = mono_print_ins_index_strbuf (i, ins);
 460         printf ("%s\n", buf->str);
 461         g_string_free (buf, TRUE);
 462 }
 463
 464 GString *
 465 mono_print_ins_index_strbuf (int i, MonoInst *ins)
 466 {
 467         const char *spec = ins_get_spec (ins->opcode);
 468         GString *sbuf = g_string_new (NULL);
 469         int num_sregs, j;
 470         int sregs [MONO_MAX_SRC_REGS];
 471
 472         if (i != -1)
 473                 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
 474         else
 475                 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
 476         if (spec == MONO_ARCH_CPU_SPEC) {
 477                 gboolean dest_base = FALSE;
 478                 switch (ins->opcode) {
 479                 case OP_STOREV_MEMBASE:
 480                         dest_base = TRUE;
 481                         break;
 482                 default:
 483                         break;
 484                 }
 485
 486                 /* This is a lowered opcode */
 487                 if (ins->dreg != -1) {
 488                         if (dest_base)
 489                                 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 490                         else
 491                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 492                 }
 493                 if (ins->sreg1 != -1)
 494                         g_string_append_printf (sbuf, " R%d", ins->sreg1);
 495                 if (ins->sreg2 != -1)
 496                         g_string_append_printf (sbuf, " R%d", ins->sreg2);
 497                 if (ins->sreg3 != -1)
 498                         g_string_append_printf (sbuf, " R%d", ins->sreg3);
 499
 500                 switch (ins->opcode) {
 501                 case OP_LBNE_UN:
 502                 case OP_LBEQ:
 503                 case OP_LBLT:
 504                 case OP_LBLT_UN:
 505                 case OP_LBGT:
 506                 case OP_LBGT_UN:
 507                 case OP_LBGE:
 508                 case OP_LBGE_UN:
 509                 case OP_LBLE:
 510                 case OP_LBLE_UN:
 511                         if (!ins->inst_false_bb)
 512                                 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 513                         else
 514                                 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 515                         break;
 516                 case OP_PHI:
 517                 case OP_VPHI:
 518                 case OP_XPHI:
 519                 case OP_FPHI: {
 520                         int i;
 521                         g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
 522                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 523                                 if (i)
 524                                         g_string_append_printf (sbuf, ", ");
 525                                 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
 526                         }
 527                         g_string_append_printf (sbuf, ")]");
 528                         break;
 529                 }
 530                 case OP_LDADDR:
 531                 case OP_OUTARG_VTRETADDR:
 532                         g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
 533                         break;
 534                 case OP_REGOFFSET:
 535                 case OP_GSHAREDVT_ARG_REGOFFSET:
 536                         g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
 537                         break;
 538                 default:
 539                         break;
 540                 }
 541
 542                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 543                 return sbuf;
 544         }
 545
 546         if (spec [MONO_INST_DEST]) {
 547                 int bank = dreg_bank (spec);
 548                 if (is_soft_reg (ins->dreg, bank)) {
 549                         if (spec [MONO_INST_DEST] == 'b') {
 550                                 if (ins->inst_offset == 0)
 551                                         g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
 552                                 else
 553                                         g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 554                         }
 555                         else
 556                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 557                 } else if (spec [MONO_INST_DEST] == 'b') {
 558                         if (ins->inst_offset == 0)
 559                                 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
 560                         else
 561                                 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 562                 } else
 563                         g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
 564         }
 565         if (spec [MONO_INST_SRC1]) {
 566                 int bank = sreg1_bank (spec);
 567                 if (is_soft_reg (ins->sreg1, bank)) {
 568                         if (spec [MONO_INST_SRC1] == 'b')
 569                                 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 570                         else
 571                                 g_string_append_printf (sbuf, " R%d", ins->sreg1);
 572                 } else if (spec [MONO_INST_SRC1] == 'b')
 573                         g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 574                 else
 575                         g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
 576         }
 577         num_sregs = mono_inst_get_src_registers (ins, sregs);
 578         for (j = 1; j < num_sregs; ++j) {
 579                 int bank = sreg_bank (j, spec);
 580                 if (is_soft_reg (sregs [j], bank))
 581                         g_string_append_printf (sbuf, " R%d", sregs [j]);
 582                 else
 583                         g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
 584         }
 585
 586         switch (ins->opcode) {
 587         case OP_ICONST:
 588                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
 589                 break;
 590 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 591         case OP_X86_PUSH_IMM:
 592 #endif
 593         case OP_ICOMPARE_IMM:
 594         case OP_COMPARE_IMM:
 595         case OP_IADD_IMM:
 596         case OP_ISUB_IMM:
 597         case OP_IAND_IMM:
 598         case OP_IOR_IMM:
 599         case OP_IXOR_IMM:
 600         case OP_SUB_IMM:
 601         case OP_STORE_MEMBASE_IMM:
 602                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
 603                 break;
 604         case OP_ADD_IMM:
 605         case OP_LADD_IMM:
 606                 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
 607                 break;
 608         case OP_I8CONST:
 609                 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
 610                 break;
 611         case OP_R8CONST:
 612                 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
 613                 break;
 614         case OP_R4CONST:
 615                 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
 616                 break;
 617         case OP_CALL:
 618         case OP_CALL_MEMBASE:
 619         case OP_CALL_REG:
 620         case OP_FCALL:
 621         case OP_LCALL:
 622         case OP_VCALL:
 623         case OP_VCALL_REG:
 624         case OP_VCALL_MEMBASE:
 625         case OP_VCALL2:
 626         case OP_VCALL2_REG:
 627         case OP_VCALL2_MEMBASE:
 628         case OP_VOIDCALL:
 629         case OP_VOIDCALL_MEMBASE:
 630         case OP_TAILCALL: {
 631                 MonoCallInst *call = (MonoCallInst*)ins;
 632                 GSList *list;
 633
 634                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 635                         /*
 636                          * These are lowered opcodes, but they are in the .md files since the old
 637                          * JIT passes them to backends.
 638                          */
 639                         if (ins->dreg != -1)
 640                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 641                 }
 642
 643                 if (call->method) {
 644                         char *full_name = mono_method_full_name (call->method, TRUE);
 645                         g_string_append_printf (sbuf, " [%s]", full_name);
 646                         g_free (full_name);
 647                 } else if (call->fptr_is_patch) {
 648                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 649
 650                         g_string_append_printf (sbuf, " ");
 651                         mono_print_ji (ji);
 652                 } else if (call->fptr) {
 653                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 654                         if (info)
 655                                 g_string_append_printf (sbuf, " [%s]", info->name);
 656                 }
 657
 658                 list = call->out_ireg_args;
 659                 while (list) {
 660                         guint32 regpair;
 661                         int reg, hreg;
 662
 663                         regpair = (guint32)(gssize)(list->data);
 664                         hreg = regpair >> 24;
 665                         reg = regpair & 0xffffff;
 666
 667                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
 668
 669                         list = g_slist_next (list);
 670                 }
 671                 list = call->out_freg_args;
 672                 while (list) {
 673                         guint32 regpair;
 674                         int reg, hreg;
 675
 676                         regpair = (guint32)(gssize)(list->data);
 677                         hreg = regpair >> 24;
 678                         reg = regpair & 0xffffff;
 679
 680                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
 681
 682                         list = g_slist_next (list);
 683                 }
 684                 break;
 685         }
 686         case OP_BR:
 687         case OP_CALL_HANDLER:
 688                 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
 689                 break;
 690         case OP_IBNE_UN:
 691         case OP_IBEQ:
 692         case OP_IBLT:
 693         case OP_IBLT_UN:
 694         case OP_IBGT:
 695         case OP_IBGT_UN:
 696         case OP_IBGE:
 697         case OP_IBGE_UN:
 698         case OP_IBLE:
 699         case OP_IBLE_UN:
 700         case OP_LBNE_UN:
 701         case OP_LBEQ:
 702         case OP_LBLT:
 703         case OP_LBLT_UN:
 704         case OP_LBGT:
 705         case OP_LBGT_UN:
 706         case OP_LBGE:
 707         case OP_LBGE_UN:
 708         case OP_LBLE:
 709         case OP_LBLE_UN:
 710                 if (!ins->inst_false_bb)
 711                         g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 712                 else
 713                         g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 714                 break;
 715         case OP_LIVERANGE_START:
 716         case OP_LIVERANGE_END:
 717         case OP_GC_LIVENESS_DEF:
 718         case OP_GC_LIVENESS_USE:
 719                 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
 720                 break;
 721         case OP_IL_SEQ_POINT:
 722         case OP_SEQ_POINT:
 723                 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 724                 break;
 725         case OP_COND_EXC_EQ:
 726         case OP_COND_EXC_GE:
 727         case OP_COND_EXC_GT:
 728         case OP_COND_EXC_LE:
 729         case OP_COND_EXC_LT:
 730         case OP_COND_EXC_NE_UN:
 731         case OP_COND_EXC_GE_UN:
 732         case OP_COND_EXC_GT_UN:
 733         case OP_COND_EXC_LE_UN:
 734         case OP_COND_EXC_LT_UN:
 735         case OP_COND_EXC_OV:
 736         case OP_COND_EXC_NO:
 737         case OP_COND_EXC_C:
 738         case OP_COND_EXC_NC:
 739         case OP_COND_EXC_IEQ:
 740         case OP_COND_EXC_IGE:
 741         case OP_COND_EXC_IGT:
 742         case OP_COND_EXC_ILE:
 743         case OP_COND_EXC_ILT:
 744         case OP_COND_EXC_INE_UN:
 745         case OP_COND_EXC_IGE_UN:
 746         case OP_COND_EXC_IGT_UN:
 747         case OP_COND_EXC_ILE_UN:
 748         case OP_COND_EXC_ILT_UN:
 749         case OP_COND_EXC_IOV:
 750         case OP_COND_EXC_INO:
 751         case OP_COND_EXC_IC:
 752         case OP_COND_EXC_INC:
 753                 g_string_append_printf (sbuf, " %s", ins->inst_p1);
 754                 break;
 755         default:
 756                 break;
 757         }
 758
 759         if (spec [MONO_INST_CLOB])
 760                 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
 761         return sbuf;
 762 }
 763
 764 static void
 765 print_regtrack (RegTrack *t, int num)
 766 {
 767         int i;
 768         char buf [32];
 769         const char *r;
 770
 771         for (i = 0; i < num; ++i) {
 772                 if (!t [i].born_in)
 773                         continue;
 774                 if (i >= MONO_MAX_IREGS) {
 775                         g_snprintf (buf, sizeof(buf), "R%d", i);
 776                         r = buf;
 777                 } else
 778                         r = mono_arch_regname (i);
 779                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 780         }
 781 }
 782 #else
 783
 784 const char*
 785 mono_ji_type_to_string (MonoJumpInfoType type)
 786 {
 787         return "";
 788 }
 789
 790 void
 791 mono_print_ji (const MonoJumpInfo *ji)
 792 {
 793 }
 794
 795 void
 796 mono_print_ins_index (int i, MonoInst *ins)
 797 {
 798 }
 799 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 800
 801 void
 802 mono_print_ins (MonoInst *ins)
 803 {
 804         mono_print_ins_index (-1, ins);
 805 }
 806
 807 static inline void
 808 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 809 {
 810         /*
 811          * If this function is called multiple times, the new instructions are inserted
 812          * in the proper order.
 813          */
 814         mono_bblock_insert_before_ins (bb, ins, to_insert);
 815 }
 816
 817 static inline void
 818 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 819 {
 820         /*
 821          * If this function is called multiple times, the new instructions are inserted in
 822          * proper order.
 823          */
 824         mono_bblock_insert_after_ins (bb, *last, to_insert);
 825
 826         *last = to_insert;
 827 }
 828
 829 static inline int
 830 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 831 {
 832         if (vreg_is_ref (cfg, reg))
 833                 return MONO_REG_INT_REF;
 834         else if (vreg_is_mp (cfg, reg))
 835                 return MONO_REG_INT_MP;
 836         else
 837                 return bank;
 838 }
 839
 840 /*
 841  * Force the spilling of the variable in the symbolic register 'reg', and free
 842  * the hreg it was assigned to.
 843  */
 844 static void
 845 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 846 {
 847         MonoInst *load;
 848         int i, sel, spill;
 849         MonoRegState *rs = cfg->rs;
 850
 851         sel = rs->vassign [reg];
 852
 853         /* the vreg we need to spill lives in another logical reg bank */
 854         bank = translate_bank (cfg->rs, bank, sel);
 855
 856         /*i = rs->isymbolic [sel];
 857         g_assert (i == reg);*/
 858         i = reg;
 859         spill = ++cfg->spill_count;
 860         rs->vassign [i] = -spill - 1;
 861         if (G_UNLIKELY (bank))
 862                 mono_regstate_free_general (rs, sel, bank);
 863         else
 864                 mono_regstate_free_int (rs, sel);
 865         /* we need to create a spill var and insert a load to sel after the current instruction */
 866         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 867         load->dreg = sel;
 868         load->inst_basereg = cfg->frame_reg;
 869         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 870         insert_after_ins (bb, ins, last, load);
 871         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 872         if (G_UNLIKELY (bank))
 873                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 874         else
 875                 i = mono_regstate_alloc_int (rs, regmask (sel));
 876         g_assert (i == sel);
 877
 878         if (G_UNLIKELY (bank))
 879                 mono_regstate_free_general (rs, sel, bank);
 880         else
 881                 mono_regstate_free_int (rs, sel);
 882 }
 883
 884 static int
 885 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 886 {
 887         MonoInst *load;
 888         int i, sel, spill, num_sregs;
 889         int sregs [MONO_MAX_SRC_REGS];
 890         MonoRegState *rs = cfg->rs;
 891
 892         g_assert (bank < MONO_NUM_REGBANKS);
 893
 894         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 895         /* exclude the registers in the current instruction */
 896         num_sregs = mono_inst_get_src_registers (ins, sregs);
 897         for (i = 0; i < num_sregs; ++i) {
 898                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 899                         if (is_soft_reg (sregs [i], bank))
 900                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 901                         else
 902                                 regmask &= ~ (regmask (sregs [i]));
 903                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 904                 }
 905         }
 906         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 907                 regmask &= ~ (regmask (ins->dreg));
 908                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 909         }
 910
 911         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 912         g_assert (regmask); /* need at least a register we can free */
 913         sel = 0;
 914         /* we should track prev_use and spill the register that's farther */
 915         if (G_UNLIKELY (bank)) {
 916                 for (i = 0; i < regbank_size [bank]; ++i) {
 917                         if (regmask & (regmask (i))) {
 918                                 sel = i;
 919
 920                                 /* the vreg we need to load lives in another logical bank */
 921                                 bank = translate_bank (cfg->rs, bank, sel);
 922
 923                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 924                                 break;
 925                         }
 926                 }
 927
 928                 i = rs->symbolic [bank] [sel];
 929                 spill = ++cfg->spill_count;
 930                 rs->vassign [i] = -spill - 1;
 931                 mono_regstate_free_general (rs, sel, bank);
 932         }
 933         else {
 934                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 935                         if (regmask & (regmask (i))) {
 936                                 sel = i;
 937                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 938                                 break;
 939                         }
 940                 }
 941
 942                 i = rs->isymbolic [sel];
 943                 spill = ++cfg->spill_count;
 944                 rs->vassign [i] = -spill - 1;
 945                 mono_regstate_free_int (rs, sel);
 946         }
 947
 948         /* we need to create a spill var and insert a load to sel after the current instruction */
 949         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 950         load->dreg = sel;
 951         load->inst_basereg = cfg->frame_reg;
 952         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 953         insert_after_ins (bb, ins, last, load);
 954         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 955         if (G_UNLIKELY (bank))
 956                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 957         else
 958                 i = mono_regstate_alloc_int (rs, regmask (sel));
 959         g_assert (i == sel);
 960
 961         return sel;
 962 }
 963
 964 /*
 965  * free_up_hreg:
 966  *
 967  *   Free up the hreg HREG by spilling the vreg allocated to it.
 968  */
 969 static void
 970 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 971 {
 972         if (G_UNLIKELY (bank)) {
 973                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 974                         bank = translate_bank (cfg->rs, bank, hreg);
 975                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 976                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 977                 }
 978         }
 979         else {
 980                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 981                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 982                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 983                 }
 984         }
 985 }
 986
 987 static MonoInst*
 988 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 989 {
 990         MonoInst *copy;
 991
 992         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 993
 994         copy->dreg = dest;
 995         copy->sreg1 = src;
 996         copy->cil_code = ip;
 997         if (ins) {
 998                 mono_bblock_insert_after_ins (bb, ins, copy);
 999                 *last = copy;
1000         }
1001         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
1002         return copy;
1003 }
1004
1005 static inline const char*
1006 regbank_to_string (int bank)
1007 {
1008         if (bank == MONO_REG_INT_REF)
1009                 return "REF ";
1010         else if (bank == MONO_REG_INT_MP)
1011                 return "MP ";
1012         else
1013                 return "";
1014 }
1015
1016 static void
1017 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
1018 {
1019         MonoInst *store, *def;
1020
1021         bank = get_vreg_bank (cfg, prev_reg, bank);
1022
1023         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
1024         store->sreg1 = reg;
1025         store->inst_destbasereg = cfg->frame_reg;
1026         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
1027         if (ins) {
1028                 mono_bblock_insert_after_ins (bb, ins, store);
1029                 *last = store;
1030         } else if (insert_before) {
1031                 insert_before_ins (bb, insert_before, store);
1032         } else {
1033                 g_assert_not_reached ();
1034         }
1035         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
1036
1037         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1038                 g_assert (prev_reg != -1);
1039                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1040                 def->inst_c0 = spill;
1041                 def->inst_c1 = bank;
1042                 mono_bblock_insert_after_ins (bb, store, def);
1043         }
1044 }
1045
1046 /* flags used in reginfo->flags */
1047 enum {
1048         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1049         MONO_FP_NEEDS_SPILL                     = regmask (1),
1050         MONO_FP_NEEDS_LOAD                      = regmask (2)
1051 };
1052
1053 static inline int
1054 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1055 {
1056         int val;
1057
1058         if (info && info->preferred_mask) {
1059                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1060                 if (val >= 0) {
1061                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1062                         return val;
1063                 }
1064         }
1065
1066         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1067         if (val < 0)
1068                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1069
1070         return val;
1071 }
1072
1073 static inline int
1074 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1075 {
1076         int val;
1077
1078         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1079
1080         if (val < 0)
1081                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1082
1083         return val;
1084 }
1085
1086 static inline int
1087 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1088 {
1089         if (G_UNLIKELY (bank))
1090                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1091         else
1092                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1093 }
1094
1095 static inline void
1096 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1097 {
1098         if (G_UNLIKELY (bank)) {
1099                 int mirrored_bank;
1100
1101                 g_assert (reg >= regbank_size [bank]);
1102                 g_assert (hreg < regbank_size [bank]);
1103                 g_assert (! is_global_freg (hreg));
1104
1105                 rs->vassign [reg] = hreg;
1106                 rs->symbolic [bank] [hreg] = reg;
1107                 rs->free_mask [bank] &= ~ (regmask (hreg));
1108
1109                 mirrored_bank = get_mirrored_bank (bank);
1110                 if (mirrored_bank == -1)
1111                         return;
1112
1113                 /* Make sure the other logical reg bank that this bank shares
1114                  * a single hard reg bank knows that this hard reg is not free.
1115                  */
1116                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1117
1118                 /* Mark the other logical bank that the this bank shares
1119                  * a single hard reg bank with as mirrored.
1120                  */
1121                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1122
1123         }
1124         else {
1125                 g_assert (reg >= MONO_MAX_IREGS);
1126                 g_assert (hreg < MONO_MAX_IREGS);
1127 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1128                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1129                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1130                 g_assert (! is_global_ireg (hreg));
1131 #endif
1132
1133                 rs->vassign [reg] = hreg;
1134                 rs->isymbolic [hreg] = reg;
1135                 rs->ifree_mask &= ~ (regmask (hreg));
1136         }
1137 }
1138
1139 static inline regmask_t
1140 get_callee_mask (const char spec)
1141 {
1142         if (G_UNLIKELY (reg_bank (spec)))
1143                 return regbank_callee_regs [reg_bank (spec)];
1144         return MONO_ARCH_CALLEE_REGS;
1145 }
1146
1147 static gint8 desc_to_fixed_reg [256];
1148 static gboolean desc_to_fixed_reg_inited = FALSE;
1149
1150 #ifndef DISABLE_JIT
1151
1152 /*
1153  * Local register allocation.
1154  * We first scan the list of instructions and we save the liveness info of
1155  * each register (when the register is first used, when it's value is set etc.).
1156  * We also reverse the list of instructions because assigning registers backwards allows
1157  * for more tricks to be used.
1158  */
1159 void
1160 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1161 {
1162         MonoInst *ins, *prev, *last;
1163         MonoInst **tmp;
1164         MonoRegState *rs = cfg->rs;
1165         int i, j, val, max;
1166         RegTrack *reginfo;
1167         const char *spec;
1168         unsigned char spec_src1, spec_dest;
1169         int bank = 0;
1170 #if MONO_ARCH_USE_FPSTACK
1171         gboolean has_fp = FALSE;
1172         int fpstack [8];
1173         int sp = 0;
1174 #endif
1175         int num_sregs = 0;
1176         int sregs [MONO_MAX_SRC_REGS];
1177
1178         if (!bb->code)
1179                 return;
1180
1181         if (!desc_to_fixed_reg_inited) {
1182                 for (i = 0; i < 256; ++i)
1183                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1184                 desc_to_fixed_reg_inited = TRUE;
1185
1186                 /* Validate the cpu description against the info in mini-ops.h */
1187 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1188                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1189                         const char *ispec;
1190
1191                         spec = ins_get_spec (i);
1192                         ispec = INS_INFO (i);
1193
1194                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1195                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1196                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1197                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1198                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1199                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1200                 }
1201 #endif
1202         }
1203
1204         rs->next_vreg = bb->max_vreg;
1205         mono_regstate_assign (rs);
1206
1207         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1208         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1209                 rs->free_mask [i] = regbank_callee_regs [i];
1210
1211         max = rs->next_vreg;
1212
1213         if (cfg->reginfo && cfg->reginfo_len < max)
1214                 cfg->reginfo = NULL;
1215
1216         reginfo = (RegTrack *)cfg->reginfo;
1217         if (!reginfo) {
1218                 cfg->reginfo_len = MAX (1024, max * 2);
1219                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1220                 cfg->reginfo = reginfo;
1221         }
1222         else
1223                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1224
1225         if (cfg->verbose_level > 1) {
1226                 /* print_regtrack reads the info of all variables */
1227                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1228         }
1229
1230         /*
1231          * For large methods, next_vreg can be very large, so g_malloc0 time can
1232          * be prohibitive. So we manually init the reginfo entries used by the
1233          * bblock.
1234          */
1235         for (ins = bb->code; ins; ins = ins->next) {
1236                 gboolean modify = FALSE;
1237
1238                 spec = ins_get_spec (ins->opcode);
1239
1240                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1241                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1242 #if SIZEOF_REGISTER == 4
1243                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1244                                 /**
1245                                  * In the new IR, the two vregs of the regpair do not alias the
1246                                  * original long vreg. shift the vreg here so the rest of the
1247                                  * allocator doesn't have to care about it.
1248                                  */
1249                                 ins->dreg ++;
1250                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1251                         }
1252 #endif
1253                 }
1254
1255                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1256                 for (j = 0; j < num_sregs; ++j) {
1257                         g_assert (sregs [j] != -1);
1258                         if (sregs [j] < max) {
1259                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1260 #if SIZEOF_REGISTER == 4
1261                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1262                                         sregs [j]++;
1263                                         modify = TRUE;
1264                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1265                                 }
1266 #endif
1267                         }
1268                 }
1269                 if (modify)
1270                         mono_inst_set_src_registers (ins, sregs);
1271         }
1272
1273         /*if (cfg->opt & MONO_OPT_COPYPROP)
1274                 local_copy_prop (cfg, ins);*/
1275
1276         i = 1;
1277         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1278         /* forward pass on the instructions to collect register liveness info */
1279         MONO_BB_FOR_EACH_INS (bb, ins) {
1280                 spec = ins_get_spec (ins->opcode);
1281                 spec_dest = spec [MONO_INST_DEST];
1282
1283                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1284                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1285                 }
1286
1287                 DEBUG (mono_print_ins_index (i, ins));
1288
1289                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1290
1291 #if MONO_ARCH_USE_FPSTACK
1292                 if (dreg_is_fp (spec)) {
1293                         has_fp = TRUE;
1294                 } else {
1295                         for (j = 0; j < num_sregs; ++j) {
1296                                 if (sreg_is_fp (j, spec))
1297                                         has_fp = TRUE;
1298                         }
1299                 }
1300 #endif
1301
1302                 for (j = 0; j < num_sregs; ++j) {
1303                         int sreg = sregs [j];
1304                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1305                         if (sreg_spec) {
1306                                 bank = sreg_bank (j, spec);
1307                                 g_assert (sreg != -1);
1308                                 if (is_soft_reg (sreg, bank))
1309                                         /* This means the vreg is not local to this bb */
1310                                         g_assert (reginfo [sreg].born_in > 0);
1311                                 rs->vassign [sreg] = -1;
1312                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1313                                 //reginfo [ins->sreg2].last_use = i;
1314                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1315                                         /* The virtual register is allocated sequentially */
1316                                         rs->vassign [sreg + 1] = -1;
1317                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1318                                         //reginfo [ins->sreg2 + 1].last_use = i;
1319                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1320                                                 reginfo [sreg + 1].born_in = i;
1321                                 }
1322                         } else {
1323                                 sregs [j] = -1;
1324                         }
1325                 }
1326                 mono_inst_set_src_registers (ins, sregs);
1327
1328                 if (spec_dest) {
1329                         int dest_dreg;
1330
1331                         bank = dreg_bank (spec);
1332                         if (spec_dest != 'b') /* it's not just a base register */
1333                                 reginfo [ins->dreg].killed_in = i;
1334                         g_assert (ins->dreg != -1);
1335                         rs->vassign [ins->dreg] = -1;
1336                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1337                         //reginfo [ins->dreg].last_use = i;
1338                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1339                                 reginfo [ins->dreg].born_in = i;
1340
1341                         dest_dreg = desc_to_fixed_reg [spec_dest];
1342                         if (dest_dreg != -1)
1343                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1344
1345 #ifdef MONO_ARCH_INST_FIXED_MASK
1346                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1347 #endif
1348
1349                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1350                                 /* The virtual register is allocated sequentially */
1351                                 rs->vassign [ins->dreg + 1] = -1;
1352                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1353                                 //reginfo [ins->dreg + 1].last_use = i;
1354                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1355                                         reginfo [ins->dreg + 1].born_in = i;
1356                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1357                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1358                         }
1359                 } else {
1360                         ins->dreg = -1;
1361                 }
1362
1363                 ++i;
1364         }
1365
1366         tmp = &last;
1367
1368         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1369         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1370                 int prev_dreg;
1371                 int dest_dreg, clob_reg;
1372                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1373                 int dreg_high, sreg1_high;
1374                 regmask_t dreg_mask, mask;
1375                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1376                 regmask_t dreg_fixed_mask;
1377                 const unsigned char *ip;
1378                 --i;
1379                 spec = ins_get_spec (ins->opcode);
1380                 spec_src1 = spec [MONO_INST_SRC1];
1381                 spec_dest = spec [MONO_INST_DEST];
1382                 prev_dreg = -1;
1383                 clob_reg = -1;
1384                 dest_dreg = -1;
1385                 dreg_high = -1;
1386                 sreg1_high = -1;
1387                 dreg_mask = get_callee_mask (spec_dest);
1388                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1389                         prev_sregs [j] = -1;
1390                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1391                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1392 #ifdef MONO_ARCH_INST_FIXED_MASK
1393                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1394 #else
1395                         sreg_fixed_masks [j] = 0;
1396 #endif
1397                 }
1398
1399                 DEBUG (printf ("processing:"));
1400                 DEBUG (mono_print_ins_index (i, ins));
1401
1402                 ip = ins->cil_code;
1403
1404                 last = ins;
1405
1406                 /*
1407                  * FIXED REGS
1408                  */
1409                 dest_dreg = desc_to_fixed_reg [spec_dest];
1410                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1411                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1412
1413 #ifdef MONO_ARCH_INST_FIXED_MASK
1414                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1415 #else
1416                 dreg_fixed_mask = 0;
1417 #endif
1418
1419                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1420
1421                 /*
1422                  * TRACK FIXED SREG2, 3, ...
1423                  */
1424                 for (j = 1; j < num_sregs; ++j) {
1425                         int sreg = sregs [j];
1426                         int dest_sreg = dest_sregs [j];
1427
1428                         if (dest_sreg == -1)
1429                                 continue;
1430
1431                         if (j == 2) {
1432                                 int k;
1433
1434                                 /*
1435                                  * CAS.
1436                                  * We need to special case this, since on x86, there are only 3
1437                                  * free registers, and the code below assigns one of them to
1438                                  * sreg, so we can run out of registers when trying to assign
1439                                  * dreg. Instead, we just set up the register masks, and let the
1440                                  * normal sreg2 assignment code handle this. It would be nice to
1441                                  * do this for all the fixed reg cases too, but there is too much
1442                                  * risk of breakage.
1443                                  */
1444
1445                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1446                                 sreg_masks [j] = regmask (dest_sreg);
1447                                 for (k = 0; k < num_sregs; ++k) {
1448                                         if (k != j)
1449                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1450                                 }
1451
1452                                 /*
1453                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1454                                  */
1455                                 for (k = 0; k < num_sregs; ++k) {
1456                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1457                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1458                                 }
1459
1460                                 /*
1461                                  * We can also run out of registers while processing sreg2 if sreg3 is
1462                                  * assigned to another hreg, so spill sreg3 now.
1463                                  */
1464                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1465                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1466                                 }
1467                                 continue;
1468                         }
1469
1470                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1471                                 if (is_global_ireg (sreg)) {
1472                                         int k;
1473                                         /* Argument already in hard reg, need to copy */
1474                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1475                                         insert_before_ins (bb, ins, copy);
1476                                         for (k = 0; k < num_sregs; ++k) {
1477                                                 if (k != j)
1478                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1479                                         }
1480                                         /* See below */
1481                                         dreg_mask &= ~ (regmask (dest_sreg));
1482                                 } else {
1483                                         val = rs->vassign [sreg];
1484                                         if (val == -1) {
1485                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1486                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1487                                         } else if (val < -1) {
1488                                                 /* FIXME: */
1489                                                 g_assert_not_reached ();
1490                                         } else {
1491                                                 /* Argument already in hard reg, need to copy */
1492                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1493                                                 int k;
1494
1495                                                 insert_before_ins (bb, ins, copy);
1496                                                 for (k = 0; k < num_sregs; ++k) {
1497                                                         if (k != j)
1498                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1499                                                 }
1500                                                 /*
1501                                                  * Prevent the dreg from being allocated to dest_sreg
1502                                                  * too, since it could force sreg1 to be allocated to
1503                                                  * the same reg on x86.
1504                                                  */
1505                                                 dreg_mask &= ~ (regmask (dest_sreg));
1506                                         }
1507                                 }
1508                         } else {
1509                                 gboolean need_spill = TRUE;
1510                                 gboolean need_assign = TRUE;
1511                                 int k;
1512
1513                                 dreg_mask &= ~ (regmask (dest_sreg));
1514                                 for (k = 0; k < num_sregs; ++k) {
1515                                         if (k != j)
1516                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1517                                 }
1518
1519                                 /*
1520                                  * First check if dreg is assigned to dest_sreg2, since we
1521                                  * can't spill a dreg.
1522                                  */
1523                                 if (spec [MONO_INST_DEST])
1524                                         val = rs->vassign [ins->dreg];
1525                                 else
1526                                         val = -1;
1527                                 if (val == dest_sreg && ins->dreg != sreg) {
1528                                         /*
1529                                          * the destination register is already assigned to
1530                                          * dest_sreg2: we need to allocate another register for it
1531                                          * and then copy from this to dest_sreg2.
1532                                          */
1533                                         int new_dest;
1534                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1535                                         g_assert (new_dest >= 0);
1536                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1537
1538                                         prev_dreg = ins->dreg;
1539                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1540                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1541                                         mono_regstate_free_int (rs, dest_sreg);
1542                                         need_spill = FALSE;
1543                                 }
1544
1545                                 if (is_global_ireg (sreg)) {
1546                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1547                                         insert_before_ins (bb, ins, copy);
1548                                         need_assign = FALSE;
1549                                 }
1550                                 else {
1551                                         val = rs->vassign [sreg];
1552                                         if (val == dest_sreg) {
1553                                                 /* sreg2 is already assigned to the correct register */
1554                                                 need_spill = FALSE;
1555                                         } else if (val < -1) {
1556                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1557                                         } else if (val >= 0) {
1558                                                 /* sreg2 already assigned to another register */
1559                                                 /*
1560                                                  * We couldn't emit a copy from val to dest_sreg2, because
1561                                                  * val might be spilled later while processing this
1562                                                  * instruction. So we spill sreg2 so it can be allocated to
1563                                                  * dest_sreg2.
1564                                                  */
1565                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1566                                         }
1567                                 }
1568
1569                                 if (need_spill) {
1570                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1571                                 }
1572
1573                                 if (need_assign) {
1574                                         if (rs->vassign [sreg] < -1) {
1575                                                 int spill;
1576
1577                                                 /* Need to emit a spill store */
1578                                                 spill = - rs->vassign [sreg] - 1;
1579                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1580                                         }
1581                                         /* force-set sreg2 */
1582                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1583                                 }
1584                         }
1585                         sregs [j] = dest_sreg;
1586                 }
1587                 mono_inst_set_src_registers (ins, sregs);
1588
1589                 /*
1590                  * TRACK DREG
1591                  */
1592                 bank = dreg_bank (spec);
1593                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1594                         prev_dreg = ins->dreg;
1595                 }
1596
1597                 if (spec_dest == 'b') {
1598                         /*
1599                          * The dest reg is read by the instruction, not written, so
1600                          * avoid allocating sreg1/sreg2 to the same reg.
1601                          */
1602                         if (dest_sregs [0] != -1)
1603                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1604                         for (j = 1; j < num_sregs; ++j) {
1605                                 if (dest_sregs [j] != -1)
1606                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1607                         }
1608
1609                         val = rs->vassign [ins->dreg];
1610                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1611                                 /* DREG is already allocated to a register needed for sreg1 */
1612                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1613                         }
1614                 }
1615
1616                 /*
1617                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1618                  * various complex situations.
1619                  */
1620                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1621                         guint32 dreg2, dest_dreg2;
1622
1623                         g_assert (is_soft_reg (ins->dreg, bank));
1624
1625                         if (dest_dreg != -1) {
1626                                 if (rs->vassign [ins->dreg] != dest_dreg)
1627                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1628
1629                                 dreg2 = ins->dreg + 1;
1630                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1631                                 if (dest_dreg2 != -1) {
1632                                         if (rs->vassign [dreg2] != dest_dreg2)
1633                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1634                                 }
1635                         }
1636                 }
1637
1638                 if (dreg_fixed_mask) {
1639                         g_assert (!bank);
1640                         if (is_global_ireg (ins->dreg)) {
1641                                 /*
1642                                  * The argument is already in a hard reg, but that reg is
1643                                  * not usable by this instruction, so allocate a new one.
1644                                  */
1645                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1646                                 if (val < 0)
1647                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1648                                 mono_regstate_free_int (rs, val);
1649                                 dest_dreg = val;
1650
1651                                 /* Fall through */
1652                         }
1653                         else
1654                                 dreg_mask &= dreg_fixed_mask;
1655                 }
1656
1657                 if (is_soft_reg (ins->dreg, bank)) {
1658                         val = rs->vassign [ins->dreg];
1659
1660                         if (val < 0) {
1661                                 int spill = 0;
1662                                 if (val < -1) {
1663                                         /* the register gets spilled after this inst */
1664                                         spill = -val -1;
1665                                 }
1666                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1667                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1668                                 if (spill)
1669                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1670                         }
1671
1672                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1673                         ins->dreg = val;
1674                 }
1675
1676                 /* Handle regpairs */
1677                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1678                         int reg2 = prev_dreg + 1;
1679
1680                         g_assert (!bank);
1681                         g_assert (prev_dreg > -1);
1682                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1683                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1684 #ifdef TARGET_X86
1685                         /* bug #80489 */
1686                         mask &= ~regmask (X86_ECX);
1687 #endif
1688                         val = rs->vassign [reg2];
1689                         if (val < 0) {
1690                                 int spill = 0;
1691                                 if (val < -1) {
1692                                         /* the register gets spilled after this inst */
1693                                         spill = -val -1;
1694                                 }
1695                                 val = mono_regstate_alloc_int (rs, mask);
1696                                 if (val < 0)
1697                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1698                                 if (spill)
1699                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1700                         }
1701                         else {
1702                                 if (! (mask & (regmask (val)))) {
1703                                         val = mono_regstate_alloc_int (rs, mask);
1704                                         if (val < 0)
1705                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1706
1707                                         /* Reallocate hreg to the correct register */
1708                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1709
1710                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1711                                 }
1712                         }
1713
1714                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1715                         assign_reg (cfg, rs, reg2, val, bank);
1716
1717                         dreg_high = val;
1718                         ins->backend.reg3 = val;
1719
1720                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1721                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1722                                 mono_regstate_free_int (rs, val);
1723                         }
1724                 }
1725
1726                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1727                         /*
1728                          * In theory, we could free up the hreg even if the vreg is alive,
1729                          * but branches inside bblocks force us to assign the same hreg
1730                          * to a vreg every time it is encountered.
1731                          */
1732                         int dreg = rs->vassign [prev_dreg];
1733                         g_assert (dreg >= 0);
1734                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1735                         if (G_UNLIKELY (bank))
1736                                 mono_regstate_free_general (rs, dreg, bank);
1737                         else
1738                                 mono_regstate_free_int (rs, dreg);
1739                         rs->vassign [prev_dreg] = -1;
1740                 }
1741
1742                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1743                         /* this instruction only outputs to dest_dreg, need to copy */
1744                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1745                         ins->dreg = dest_dreg;
1746
1747                         if (G_UNLIKELY (bank)) {
1748                                 /* the register we need to free up may be used in another logical regbank
1749                                  * so do a translate just in case.
1750                                  */
1751                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1752                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1753                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1754                         }
1755                         else {
1756                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1757                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1758                         }
1759                 }
1760
1761                 if (spec_dest == 'b') {
1762                         /*
1763                          * The dest reg is read by the instruction, not written, so
1764                          * avoid allocating sreg1/sreg2 to the same reg.
1765                          */
1766                         for (j = 0; j < num_sregs; ++j)
1767                                 if (!sreg_bank (j, spec))
1768                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1769                 }
1770
1771                 /*
1772                  * TRACK CLOBBERING
1773                  */
1774                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1775                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1776                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1777                 }
1778
1779                 if (spec [MONO_INST_CLOB] == 'c') {
1780                         int j, s, dreg, dreg2, cur_bank;
1781                         guint64 clob_mask;
1782
1783                         clob_mask = MONO_ARCH_CALLEE_REGS;
1784
1785                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1786                                 /*
1787                                  * Need to avoid spilling the dreg since the dreg is not really
1788                                  * clobbered by the call.
1789                                  */
1790                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1791                                         dreg = rs->vassign [prev_dreg];
1792                                 else
1793                                         dreg = -1;
1794
1795                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1796                                         dreg2 = rs->vassign [prev_dreg + 1];
1797                                 else
1798                                         dreg2 = -1;
1799
1800                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1801                                         s = regmask (j);
1802                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1803                                                 if ((j != dreg) && (j != dreg2))
1804                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1805                                                 else if (rs->isymbolic [j])
1806                                                         /* The hreg is assigned to the dreg of this instruction */
1807                                                         rs->vassign [rs->isymbolic [j]] = -1;
1808                                                 mono_regstate_free_int (rs, j);
1809                                         }
1810                                 }
1811                         }
1812
1813                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1814                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1815                                         clob_mask = regbank_callee_regs [cur_bank];
1816                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1817                                                 dreg = rs->vassign [prev_dreg];
1818                                         else
1819                                                 dreg = -1;
1820
1821                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1822
1823                                                 /* we are looping though the banks in the outer loop
1824                                                  * so, we don't need to deal with mirrored hregs
1825                                                  * because we will get them in one of the other bank passes.
1826                                                  */
1827                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1828                                                         continue;
1829
1830                                                 s = regmask (j);
1831                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1832                                                         if (j != dreg)
1833                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1834                                                         else if (rs->symbolic [cur_bank] [j])
1835                                                                 /* The hreg is assigned to the dreg of this instruction */
1836                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1837                                                         mono_regstate_free_general (rs, j, cur_bank);
1838                                                 }
1839                                         }
1840                                 }
1841                         }
1842                 }
1843
1844                 /*
1845                  * TRACK ARGUMENT REGS
1846                  */
1847                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1848                         MonoCallInst *call = (MonoCallInst*)ins;
1849                         GSList *list;
1850
1851                         /*
1852                          * This needs to be done before assigning sreg1, so sreg1 will
1853                          * not be assigned one of the argument regs.
1854                          */
1855
1856                         /*
1857                          * Assign all registers in call->out_reg_args to the proper
1858                          * argument registers.
1859                          */
1860
1861                         list = call->out_ireg_args;
1862                         if (list) {
1863                                 while (list) {
1864                                         guint32 regpair;
1865                                         int reg, hreg;
1866
1867                                         regpair = (guint32)(gssize)(list->data);
1868                                         hreg = regpair >> 24;
1869                                         reg = regpair & 0xffffff;
1870
1871                                         assign_reg (cfg, rs, reg, hreg, 0);
1872
1873                                         sreg_masks [0] &= ~(regmask (hreg));
1874
1875                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1876
1877                                         list = g_slist_next (list);
1878                                 }
1879                         }
1880
1881                         list = call->out_freg_args;
1882                         if (list) {
1883                                 while (list) {
1884                                         guint32 regpair;
1885                                         int reg, hreg;
1886
1887                                         regpair = (guint32)(gssize)(list->data);
1888                                         hreg = regpair >> 24;
1889                                         reg = regpair & 0xffffff;
1890
1891                                         assign_reg (cfg, rs, reg, hreg, 1);
1892
1893                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1894
1895                                         list = g_slist_next (list);
1896                                 }
1897                         }
1898                 }
1899
1900                 /*
1901                  * TRACK SREG1
1902                  */
1903                 bank = sreg1_bank (spec);
1904                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1905                         int sreg1 = sregs [0];
1906                         int dest_sreg1 = dest_sregs [0];
1907
1908                         g_assert (is_soft_reg (sreg1, bank));
1909
1910                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1911                         if (dest_sreg1 != -1)
1912                                 g_assert (dest_sreg1 == ins->dreg);
1913                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1914                         g_assert (val >= 0);
1915
1916                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1917                                 // FIXME:
1918                                 g_assert_not_reached ();
1919
1920                         assign_reg (cfg, rs, sreg1, val, bank);
1921
1922                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1923
1924                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1925                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1926                         g_assert (val >= 0);
1927
1928                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1929                                 // FIXME:
1930                                 g_assert_not_reached ();
1931
1932                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1933
1934                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1935
1936                         /* Skip rest of this section */
1937                         dest_sregs [0] = -1;
1938                 }
1939
1940                 if (sreg_fixed_masks [0]) {
1941                         g_assert (!bank);
1942                         if (is_global_ireg (sregs [0])) {
1943                                 /*
1944                                  * The argument is already in a hard reg, but that reg is
1945                                  * not usable by this instruction, so allocate a new one.
1946                                  */
1947                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1948                                 if (val < 0)
1949                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1950                                 mono_regstate_free_int (rs, val);
1951                                 dest_sregs [0] = val;
1952
1953                                 /* Fall through to the dest_sreg1 != -1 case */
1954                         }
1955                         else
1956                                 sreg_masks [0] &= sreg_fixed_masks [0];
1957                 }
1958
1959                 if (dest_sregs [0] != -1) {
1960                         sreg_masks [0] = regmask (dest_sregs [0]);
1961
1962                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1963                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1964                         }
1965                         if (is_global_ireg (sregs [0])) {
1966                                 /* The argument is already in a hard reg, need to copy */
1967                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1968                                 insert_before_ins (bb, ins, copy);
1969                                 sregs [0] = dest_sregs [0];
1970                         }
1971                 }
1972
1973                 if (is_soft_reg (sregs [0], bank)) {
1974                         val = rs->vassign [sregs [0]];
1975                         prev_sregs [0] = sregs [0];
1976                         if (val < 0) {
1977                                 int spill = 0;
1978                                 if (val < -1) {
1979                                         /* the register gets spilled after this inst */
1980                                         spill = -val -1;
1981                                 }
1982
1983                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1984                                         /*
1985                                          * Allocate the same hreg to sreg1 as well so the
1986                                          * peephole can get rid of the move.
1987                                          */
1988                                         sreg_masks [0] = regmask (ins->dreg);
1989                                 }
1990
1991                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1992                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1993                                         sreg_masks [0] = regmask (ins->dreg);
1994
1995                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1996                                 assign_reg (cfg, rs, sregs [0], val, bank);
1997                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1998
1999                                 if (spill) {
2000                                         /*
2001                                          * Need to insert before the instruction since it can
2002                                          * overwrite sreg1.
2003                                          */
2004                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
2005                                 }
2006                         }
2007                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
2008                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
2009                                 insert_before_ins (bb, ins, copy);
2010                                 for (j = 1; j < num_sregs; ++j)
2011                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
2012                                 val = dest_sregs [0];
2013                         }
2014
2015                         sregs [0] = val;
2016                 }
2017                 else {
2018                         prev_sregs [0] = -1;
2019                 }
2020                 mono_inst_set_src_registers (ins, sregs);
2021
2022                 for (j = 1; j < num_sregs; ++j)
2023                         sreg_masks [j] &= ~(regmask (sregs [0]));
2024
2025                 /* Handle the case when sreg1 is a regpair but dreg is not */
2026                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2027                         int reg2 = prev_sregs [0] + 1;
2028
2029                         g_assert (!bank);
2030                         g_assert (prev_sregs [0] > -1);
2031                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2032                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2033                         val = rs->vassign [reg2];
2034                         if (val < 0) {
2035                                 int spill = 0;
2036                                 if (val < -1) {
2037                                         /* the register gets spilled after this inst */
2038                                         spill = -val -1;
2039                                 }
2040                                 val = mono_regstate_alloc_int (rs, mask);
2041                                 if (val < 0)
2042                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2043                                 if (spill)
2044                                         g_assert_not_reached ();
2045                         }
2046                         else {
2047                                 if (! (mask & (regmask (val)))) {
2048                                         /* The vreg is already allocated to a wrong hreg */
2049                                         /* FIXME: */
2050                                         g_assert_not_reached ();
2051 #if 0
2052                                         val = mono_regstate_alloc_int (rs, mask);
2053                                         if (val < 0)
2054                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2055
2056                                         /* Reallocate hreg to the correct register */
2057                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2058
2059                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2060 #endif
2061                                 }
2062                         }
2063
2064                         sreg1_high = val;
2065                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2066                         assign_reg (cfg, rs, reg2, val, bank);
2067                 }
2068
2069                 /* Handle dreg==sreg1 */
2070                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2071                         MonoInst *sreg2_copy = NULL;
2072                         MonoInst *copy;
2073                         int bank = reg_bank (spec_src1);
2074
2075                         if (ins->dreg == sregs [1]) {
2076                                 /*
2077                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2078                                  * register for it.
2079                                  */
2080                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2081
2082                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2083                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2084                                 prev_sregs [1] = sregs [1] = reg2;
2085
2086                                 if (G_UNLIKELY (bank))
2087                                         mono_regstate_free_general (rs, reg2, bank);
2088                                 else
2089                                         mono_regstate_free_int (rs, reg2);
2090                         }
2091
2092                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2093                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2094                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2095                                         /* FIXME: */
2096                                         g_assert_not_reached ();
2097
2098                                 /*
2099                                  * sreg1 and dest are already allocated to the same regpair by the
2100                                  * SREG1 allocation code.
2101                                  */
2102                                 g_assert (sregs [0] == ins->dreg);
2103                                 g_assert (dreg_high == sreg1_high);
2104                         }
2105
2106                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2107                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2108                         insert_before_ins (bb, ins, copy);
2109
2110                         if (sreg2_copy)
2111                                 insert_before_ins (bb, copy, sreg2_copy);
2112
2113                         /*
2114                          * Need to prevent sreg2 to be allocated to sreg1, since that
2115                          * would screw up the previous copy.
2116                          */
2117                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2118                         /* we set sreg1 to dest as well */
2119                         prev_sregs [0] = sregs [0] = ins->dreg;
2120                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2121                 }
2122                 mono_inst_set_src_registers (ins, sregs);
2123
2124                 /*
2125                  * TRACK SREG2, 3, ...
2126                  */
2127                 for (j = 1; j < num_sregs; ++j) {
2128                         int k;
2129
2130                         bank = sreg_bank (j, spec);
2131                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2132                                 g_assert_not_reached ();
2133
2134                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2135                                 /*
2136                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2137                                  * allocating it to the fixed reg.
2138                                  */
2139                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2140                                 insert_before_ins (bb, ins, copy);
2141                                 sregs [j] = dest_sregs [j];
2142                         } else if (is_soft_reg (sregs [j], bank)) {
2143                                 val = rs->vassign [sregs [j]];
2144
2145                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2146                                         /*
2147                                          * The sreg is already allocated to a hreg, but not to the fixed
2148                                          * reg required by the instruction. Spill the sreg, so it can be
2149                                          * allocated to the fixed reg by the code below.
2150                                          */
2151                                         /* Currently, this code should only be hit for CAS */
2152                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2153                                         val = rs->vassign [sregs [j]];
2154                                 }
2155
2156                                 if (val < 0) {
2157                                         int spill = 0;
2158                                         if (val < -1) {
2159                                                 /* the register gets spilled after this inst */
2160                                                 spill = -val -1;
2161                                         }
2162                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2163                                         assign_reg (cfg, rs, sregs [j], val, bank);
2164                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2165                                         if (spill) {
2166                                                 /*
2167                                                  * Need to insert before the instruction since it can
2168                                                  * overwrite sreg2.
2169                                                  */
2170                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2171                                         }
2172                                 }
2173                                 sregs [j] = val;
2174                                 for (k = j + 1; k < num_sregs; ++k)
2175                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2176                         }
2177                         else {
2178                                 prev_sregs [j] = -1;
2179                         }
2180                 }
2181                 mono_inst_set_src_registers (ins, sregs);
2182
2183                 /* Sanity check */
2184                 /* Do this only for CAS for now */
2185                 for (j = 1; j < num_sregs; ++j) {
2186                         int sreg = sregs [j];
2187                         int dest_sreg = dest_sregs [j];
2188
2189                         if (j == 2 && dest_sreg != -1) {
2190                                 int k;
2191
2192                                 g_assert (sreg == dest_sreg);
2193
2194                                 for (k = 0; k < num_sregs; ++k) {
2195                                         if (k != j)
2196                                                 g_assert (sregs [k] != dest_sreg);
2197                                 }
2198                         }
2199                 }
2200
2201                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2202                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2203                         mono_regstate_free_int (rs, ins->sreg1);
2204                 }
2205                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2206                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2207                         mono_regstate_free_int (rs, ins->sreg2);
2208                 }*/
2209
2210                 DEBUG (mono_print_ins_index (i, ins));
2211         }
2212
2213         // FIXME: Set MAX_FREGS to 8
2214         // FIXME: Optimize generated code
2215 #if MONO_ARCH_USE_FPSTACK
2216         /*
2217          * Make a forward pass over the code, simulating the fp stack, making sure the
2218          * arguments required by the fp opcodes are at the top of the stack.
2219          */
2220         if (has_fp) {
2221                 MonoInst *prev = NULL;
2222                 MonoInst *fxch;
2223                 int tmp;
2224
2225                 g_assert (num_sregs <= 2);
2226
2227                 for (ins = bb->code; ins; ins = ins->next) {
2228                         spec = ins_get_spec (ins->opcode);
2229
2230                         DEBUG (printf ("processing:"));
2231                         DEBUG (mono_print_ins_index (0, ins));
2232
2233                         if (ins->opcode == OP_FMOVE) {
2234                                 /* Do it by renaming the source to the destination on the stack */
2235                                 // FIXME: Is this correct ?
2236                                 for (i = 0; i < sp; ++i)
2237                                         if (fpstack [i] == ins->sreg1)
2238                                                 fpstack [i] = ins->dreg;
2239                                 prev = ins;
2240                                 continue;
2241                         }
2242
2243                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2244                                 /* Arg1 must be in %st(1) */
2245                                 g_assert (prev);
2246
2247                                 i = 0;
2248                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2249                                         i ++;
2250                                 g_assert (i < sp);
2251
2252                                 if (sp - 1 - i > 0) {
2253                                         /* First move it to %st(0) */
2254                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2255
2256                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2257                                         fxch->inst_imm = sp - 1 - i;
2258
2259                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2260                                         prev = fxch;
2261
2262                                         tmp = fpstack [sp - 1];
2263                                         fpstack [sp - 1] = fpstack [i];
2264                                         fpstack [i] = tmp;
2265                                 }
2266
2267                                 /* Then move it to %st(1) */
2268                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2269
2270                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2271                                 fxch->inst_imm = 1;
2272
2273                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2274                                 prev = fxch;
2275
2276                                 tmp = fpstack [sp - 1];
2277                                 fpstack [sp - 1] = fpstack [sp - 2];
2278                                 fpstack [sp - 2] = tmp;
2279                         }
2280
2281                         if (sreg2_is_fp (spec)) {
2282                                 g_assert (sp > 0);
2283
2284                                 if (fpstack [sp - 1] != ins->sreg2) {
2285                                         g_assert (prev);
2286
2287                                         i = 0;
2288                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2289                                                 i ++;
2290                                         g_assert (i < sp);
2291
2292                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2293
2294                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2295                                         fxch->inst_imm = sp - 1 - i;
2296
2297                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2298                                         prev = fxch;
2299
2300                                         tmp = fpstack [sp - 1];
2301                                         fpstack [sp - 1] = fpstack [i];
2302                                         fpstack [i] = tmp;
2303                                 }
2304
2305                                 sp --;
2306                         }
2307
2308                         if (sreg1_is_fp (spec)) {
2309                                 g_assert (sp > 0);
2310
2311                                 if (fpstack [sp - 1] != ins->sreg1) {
2312                                         g_assert (prev);
2313
2314                                         i = 0;
2315                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2316                                                 i ++;
2317                                         g_assert (i < sp);
2318
2319                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2320
2321                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2322                                         fxch->inst_imm = sp - 1 - i;
2323
2324                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2325                                         prev = fxch;
2326
2327                                         tmp = fpstack [sp - 1];
2328                                         fpstack [sp - 1] = fpstack [i];
2329                                         fpstack [i] = tmp;
2330                                 }
2331
2332                                 sp --;
2333                         }
2334
2335                         if (dreg_is_fp (spec)) {
2336                                 g_assert (sp < 8);
2337                                 fpstack [sp ++] = ins->dreg;
2338                         }
2339
2340                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2341                                 printf ("\t[");
2342                                 for (i = 0; i < sp; ++i)
2343                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2344                                 printf ("]\n");
2345                         }
2346
2347                         prev = ins;
2348                 }
2349
2350                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2351                         /* Remove remaining items from the fp stack */
2352                         /*
2353                          * These can remain for example as a result of a dead fmove like in
2354                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2355                          */
2356                         while (sp) {
2357                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2358                                 mono_add_ins_to_end (bb, ins);
2359                                 sp --;
2360                         }
2361                 }
2362         }
2363 #endif
2364 }
2365
2366 CompRelation
2367 mono_opcode_to_cond (int opcode)
2368 {
2369         switch (opcode) {
2370         case OP_CEQ:
2371         case OP_IBEQ:
2372         case OP_ICEQ:
2373         case OP_LBEQ:
2374         case OP_LCEQ:
2375         case OP_FBEQ:
2376         case OP_FCEQ:
2377         case OP_RBEQ:
2378         case OP_RCEQ:
2379         case OP_COND_EXC_EQ:
2380         case OP_COND_EXC_IEQ:
2381         case OP_CMOV_IEQ:
2382         case OP_CMOV_LEQ:
2383                 return CMP_EQ;
2384         case OP_FCNEQ:
2385         case OP_ICNEQ:
2386         case OP_IBNE_UN:
2387         case OP_LBNE_UN:
2388         case OP_FBNE_UN:
2389         case OP_COND_EXC_NE_UN:
2390         case OP_COND_EXC_INE_UN:
2391         case OP_CMOV_INE_UN:
2392         case OP_CMOV_LNE_UN:
2393                 return CMP_NE;
2394         case OP_FCLE:
2395         case OP_ICLE:
2396         case OP_IBLE:
2397         case OP_LBLE:
2398         case OP_FBLE:
2399         case OP_CMOV_ILE:
2400         case OP_CMOV_LLE:
2401                 return CMP_LE;
2402         case OP_FCGE:
2403         case OP_ICGE:
2404         case OP_IBGE:
2405         case OP_LBGE:
2406         case OP_FBGE:
2407         case OP_CMOV_IGE:
2408         case OP_CMOV_LGE:
2409                 return CMP_GE;
2410         case OP_CLT:
2411         case OP_IBLT:
2412         case OP_ICLT:
2413         case OP_LBLT:
2414         case OP_LCLT:
2415         case OP_FBLT:
2416         case OP_FCLT:
2417         case OP_RBLT:
2418         case OP_RCLT:
2419         case OP_COND_EXC_LT:
2420         case OP_COND_EXC_ILT:
2421         case OP_CMOV_ILT:
2422         case OP_CMOV_LLT:
2423                 return CMP_LT;
2424         case OP_CGT:
2425         case OP_IBGT:
2426         case OP_ICGT:
2427         case OP_LBGT:
2428         case OP_LCGT:
2429         case OP_FBGT:
2430         case OP_FCGT:
2431         case OP_RBGT:
2432         case OP_RCGT:
2433         case OP_COND_EXC_GT:
2434         case OP_COND_EXC_IGT:
2435         case OP_CMOV_IGT:
2436         case OP_CMOV_LGT:
2437                 return CMP_GT;
2438
2439         case OP_ICLE_UN:
2440         case OP_IBLE_UN:
2441         case OP_LBLE_UN:
2442         case OP_FBLE_UN:
2443         case OP_COND_EXC_LE_UN:
2444         case OP_COND_EXC_ILE_UN:
2445         case OP_CMOV_ILE_UN:
2446         case OP_CMOV_LLE_UN:
2447                 return CMP_LE_UN;
2448
2449         case OP_ICGE_UN:
2450         case OP_IBGE_UN:
2451         case OP_LBGE_UN:
2452         case OP_FBGE_UN:
2453         case OP_CMOV_IGE_UN:
2454         case OP_CMOV_LGE_UN:
2455                 return CMP_GE_UN;
2456         case OP_CLT_UN:
2457         case OP_IBLT_UN:
2458         case OP_ICLT_UN:
2459         case OP_LBLT_UN:
2460         case OP_LCLT_UN:
2461         case OP_FBLT_UN:
2462         case OP_FCLT_UN:
2463         case OP_RBLT_UN:
2464         case OP_RCLT_UN:
2465         case OP_COND_EXC_LT_UN:
2466         case OP_COND_EXC_ILT_UN:
2467         case OP_CMOV_ILT_UN:
2468         case OP_CMOV_LLT_UN:
2469                 return CMP_LT_UN;
2470         case OP_CGT_UN:
2471         case OP_IBGT_UN:
2472         case OP_ICGT_UN:
2473         case OP_LBGT_UN:
2474         case OP_LCGT_UN:
2475         case OP_FCGT_UN:
2476         case OP_FBGT_UN:
2477         case OP_RCGT_UN:
2478         case OP_RBGT_UN:
2479         case OP_COND_EXC_GT_UN:
2480         case OP_COND_EXC_IGT_UN:
2481         case OP_CMOV_IGT_UN:
2482         case OP_CMOV_LGT_UN:
2483                 return CMP_GT_UN;
2484         default:
2485                 printf ("%s\n", mono_inst_name (opcode));
2486                 g_assert_not_reached ();
2487                 return (CompRelation)0;
2488         }
2489 }
2490
2491 CompRelation
2492 mono_negate_cond (CompRelation cond)
2493 {
2494         switch (cond) {
2495         case CMP_EQ:
2496                 return CMP_NE;
2497         case CMP_NE:
2498                 return CMP_EQ;
2499         case CMP_LE:
2500                 return CMP_GT;
2501         case CMP_GE:
2502                 return CMP_LT;
2503         case CMP_LT:
2504                 return CMP_GE;
2505         case CMP_GT:
2506                 return CMP_LE;
2507         case CMP_LE_UN:
2508                 return CMP_GT_UN;
2509         case CMP_GE_UN:
2510                 return CMP_LT_UN;
2511         case CMP_LT_UN:
2512                 return CMP_GE_UN;
2513         case CMP_GT_UN:
2514                 return CMP_LE_UN;
2515         default:
2516                 g_assert_not_reached ();
2517         }
2518 }
2519
2520 CompType
2521 mono_opcode_to_type (int opcode, int cmp_opcode)
2522 {
2523         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2524                 return CMP_TYPE_L;
2525         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2526                 return CMP_TYPE_I;
2527         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2528                 return CMP_TYPE_I;
2529         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2530                 return CMP_TYPE_L;
2531         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2532                 return CMP_TYPE_L;
2533         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2534                 return CMP_TYPE_F;
2535         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2536                 return CMP_TYPE_F;
2537         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2538                 return CMP_TYPE_I;
2539         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2540                 switch (cmp_opcode) {
2541                 case OP_ICOMPARE:
2542                 case OP_ICOMPARE_IMM:
2543                         return CMP_TYPE_I;
2544                 default:
2545                         return CMP_TYPE_L;
2546                 }
2547         } else {
2548                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2549                 return (CompType)0;
2550         }
2551 }
2552
2553 #endif /* DISABLE_JIT */
2554
2555 gboolean
2556 mono_is_regsize_var (MonoType *t)
2557 {
2558         t = mini_get_underlying_type (t);
2559         switch (t->type) {
2560         case MONO_TYPE_I1:
2561         case MONO_TYPE_U1:
2562         case MONO_TYPE_I2:
2563         case MONO_TYPE_U2:
2564         case MONO_TYPE_I4:
2565         case MONO_TYPE_U4:
2566         case MONO_TYPE_I:
2567         case MONO_TYPE_U:
2568         case MONO_TYPE_PTR:
2569         case MONO_TYPE_FNPTR:
2570 #if SIZEOF_REGISTER == 8
2571         case MONO_TYPE_I8:
2572         case MONO_TYPE_U8:
2573 #endif
2574                 return TRUE;
2575         case MONO_TYPE_OBJECT:
2576         case MONO_TYPE_STRING:
2577         case MONO_TYPE_CLASS:
2578         case MONO_TYPE_SZARRAY:
2579         case MONO_TYPE_ARRAY:
2580                 return TRUE;
2581         case MONO_TYPE_GENERICINST:
2582                 if (!mono_type_generic_inst_is_valuetype (t))
2583                         return TRUE;
2584                 return FALSE;
2585         case MONO_TYPE_VALUETYPE:
2586                 return FALSE;
2587         default:
2588                 return FALSE;
2589         }
2590 }
2591
2592 #ifndef DISABLE_JIT
2593
2594 /*
2595  * mono_peephole_ins:
2596  *
2597  *   Perform some architecture independent peephole optimizations.
2598  */
2599 void
2600 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2601 {
2602         int filter = FILTER_IL_SEQ_POINT;
2603         MonoInst *last_ins = mono_inst_prev (ins, filter);
2604
2605         switch (ins->opcode) {
2606         case OP_MUL_IMM:
2607                 /* remove unnecessary multiplication with 1 */
2608                 if (ins->inst_imm == 1) {
2609                         if (ins->dreg != ins->sreg1)
2610                                 ins->opcode = OP_MOVE;
2611                         else
2612                                 MONO_DELETE_INS (bb, ins);
2613                 }
2614                 break;
2615         case OP_LOAD_MEMBASE:
2616         case OP_LOADI4_MEMBASE:
2617                 /*
2618                  * Note: if reg1 = reg2 the load op is removed
2619                  *
2620                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2621                  * OP_LOAD_MEMBASE offset(basereg), reg2
2622                  * -->
2623                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2624                  * OP_MOVE reg1, reg2
2625                  */
2626                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2627                         last_ins = mono_inst_prev (ins, filter);
2628                 if (last_ins &&
2629                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2630                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2631                         ins->inst_basereg == last_ins->inst_destbasereg &&
2632                         ins->inst_offset == last_ins->inst_offset) {
2633                         if (ins->dreg == last_ins->sreg1) {
2634                                 MONO_DELETE_INS (bb, ins);
2635                                 break;
2636                         } else {
2637                                 ins->opcode = OP_MOVE;
2638                                 ins->sreg1 = last_ins->sreg1;
2639                         }
2640
2641                         /*
2642                          * Note: reg1 must be different from the basereg in the second load
2643                          * Note: if reg1 = reg2 is equal then second load is removed
2644                          *
2645                          * OP_LOAD_MEMBASE offset(basereg), reg1
2646                          * OP_LOAD_MEMBASE offset(basereg), reg2
2647                          * -->
2648                          * OP_LOAD_MEMBASE offset(basereg), reg1
2649                          * OP_MOVE reg1, reg2
2650                          */
2651                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2652                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2653                           ins->inst_basereg != last_ins->dreg &&
2654                           ins->inst_basereg == last_ins->inst_basereg &&
2655                           ins->inst_offset == last_ins->inst_offset) {
2656
2657                         if (ins->dreg == last_ins->dreg) {
2658                                 MONO_DELETE_INS (bb, ins);
2659                         } else {
2660                                 ins->opcode = OP_MOVE;
2661                                 ins->sreg1 = last_ins->dreg;
2662                         }
2663
2664                         //g_assert_not_reached ();
2665
2666 #if 0
2667                         /*
2668                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2669                          * OP_LOAD_MEMBASE offset(basereg), reg
2670                          * -->
2671                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2672                          * OP_ICONST reg, imm
2673                          */
2674                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2675                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2676                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2677                                    ins->inst_offset == last_ins->inst_offset) {
2678                         ins->opcode = OP_ICONST;
2679                         ins->inst_c0 = last_ins->inst_imm;
2680                         g_assert_not_reached (); // check this rule
2681 #endif
2682                 }
2683                 break;
2684         case OP_LOADI1_MEMBASE:
2685         case OP_LOADU1_MEMBASE:
2686                 /*
2687                  * Note: if reg1 = reg2 the load op is removed
2688                  *
2689                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2690                  * OP_LOAD_MEMBASE offset(basereg), reg2
2691                  * -->
2692                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2693                  * OP_MOVE reg1, reg2
2694                  */
2695                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2696                         ins->inst_basereg == last_ins->inst_destbasereg &&
2697                         ins->inst_offset == last_ins->inst_offset) {
2698                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2699                         ins->sreg1 = last_ins->sreg1;
2700                 }
2701                 break;
2702         case OP_LOADI2_MEMBASE:
2703         case OP_LOADU2_MEMBASE:
2704                 /*
2705                  * Note: if reg1 = reg2 the load op is removed
2706                  *
2707                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2708                  * OP_LOAD_MEMBASE offset(basereg), reg2
2709                  * -->
2710                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2711                  * OP_MOVE reg1, reg2
2712                  */
2713                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2714                         ins->inst_basereg == last_ins->inst_destbasereg &&
2715                         ins->inst_offset == last_ins->inst_offset) {
2716 #if SIZEOF_REGISTER == 8
2717                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2718 #else
2719                         /* The definition of OP_PCONV_TO_U2 is wrong */
2720                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2721 #endif
2722                         ins->sreg1 = last_ins->sreg1;
2723                 }
2724                 break;
2725         case OP_MOVE:
2726         case OP_FMOVE:
2727                 /*
2728                  * Removes:
2729                  *
2730                  * OP_MOVE reg, reg
2731                  */
2732                 if (ins->dreg == ins->sreg1) {
2733                         MONO_DELETE_INS (bb, ins);
2734                         break;
2735                 }
2736                 /*
2737                  * Removes:
2738                  *
2739                  * OP_MOVE sreg, dreg
2740                  * OP_MOVE dreg, sreg
2741                  */
2742                 if (last_ins && last_ins->opcode == ins->opcode &&
2743                         ins->sreg1 == last_ins->dreg &&
2744                         ins->dreg == last_ins->sreg1) {
2745                         MONO_DELETE_INS (bb, ins);
2746                 }
2747                 break;
2748         case OP_NOP:
2749                 MONO_DELETE_INS (bb, ins);
2750                 break;
2751         }
2752 }
2753
2754 int
2755 mini_exception_id_by_name (const char *name)
2756 {
2757         if (strcmp (name, "IndexOutOfRangeException") == 0)
2758                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2759         if (strcmp (name, "OverflowException") == 0)
2760                 return MONO_EXC_OVERFLOW;
2761         if (strcmp (name, "ArithmeticException") == 0)
2762                 return MONO_EXC_ARITHMETIC;
2763         if (strcmp (name, "DivideByZeroException") == 0)
2764                 return MONO_EXC_DIVIDE_BY_ZERO;
2765         if (strcmp (name, "InvalidCastException") == 0)
2766                 return MONO_EXC_INVALID_CAST;
2767         if (strcmp (name, "NullReferenceException") == 0)
2768                 return MONO_EXC_NULL_REF;
2769         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2770                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2771         if (strcmp (name, "ArgumentException") == 0)
2772                 return MONO_EXC_ARGUMENT;
2773         g_error ("Unknown intrinsic exception %s\n", name);
2774         return -1;
2775 }
2776
2777 gboolean
2778 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2779 {
2780         MonoClass *klass;
2781         gpointer iter;
2782         MonoClassField *field;
2783         MonoType *ftype, *prev_ftype = NULL;
2784         int nfields = 0;
2785
2786         klass = mono_class_from_mono_type (t);
2787         iter = NULL;
2788         while ((field = mono_class_get_fields (klass, &iter))) {
2789                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2790                         continue;
2791                 ftype = mono_field_get_type (field);
2792                 ftype = mini_native_type_replace_type (ftype);
2793
2794                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2795                         int nested_nfields, nested_esize;
2796
2797                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2798                                 return FALSE;
2799                         if (nested_esize == 4)
2800                                 ftype = &mono_defaults.single_class->byval_arg;
2801                         else
2802                                 ftype = &mono_defaults.double_class->byval_arg;
2803                         if (prev_ftype && prev_ftype->type != ftype->type)
2804                                 return FALSE;
2805                         prev_ftype = ftype;
2806                         nfields += nested_nfields;
2807                 } else {
2808                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2809                                 return FALSE;
2810                         if (prev_ftype && prev_ftype->type != ftype->type)
2811                                 return FALSE;
2812                         prev_ftype = ftype;
2813                         nfields ++;
2814                 }
2815         }
2816         if (nfields == 0)
2817                 return FALSE;
2818         *out_nfields = nfields;
2819         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2820         return TRUE;
2821 }
2822
2823 MonoRegState*
2824 mono_regstate_new (void)
2825 {
2826         MonoRegState* rs = g_new0 (MonoRegState, 1);
2827
2828         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2829 #ifdef MONO_ARCH_NEED_SIMD_BANK
2830         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2831 #endif
2832
2833         return rs;
2834 }
2835
2836 void
2837 mono_regstate_free (MonoRegState *rs) {
2838         g_free (rs->vassign);
2839         g_free (rs);
2840 }
2841
2842 #endif /* DISABLE_JIT */