mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 413
 414 static const char* const patch_info_str[] = {
 415 #define PATCH_INFO(a,b) "" #a,
 416 #include "patch-info.h"
 417 #undef PATCH_INFO
 418 };
 419
 420 void
 421 mono_print_ji (const MonoJumpInfo *ji)
 422 {
 423         switch (ji->type) {
 424         case MONO_PATCH_INFO_RGCTX_FETCH: {
 425                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 426
 427                 printf ("[RGCTX_FETCH ");
 428                 mono_print_ji (entry->data);
 429                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 430                 break;
 431         }
 432         case MONO_PATCH_INFO_METHODCONST: {
 433                 char *s = mono_method_full_name (ji->data.method, TRUE);
 434                 printf ("[METHODCONST - %s]", s);
 435                 g_free (s);
 436                 break;
 437         }
 438         default:
 439                 printf ("[%s]", patch_info_str [ji->type]);
 440                 break;
 441         }
 442 }
 443
 444 void
 445 mono_print_ins_index (int i, MonoInst *ins)
 446 {
 447         const char *spec = ins_get_spec (ins->opcode);
 448         int num_sregs, j;
 449         int sregs [MONO_MAX_SRC_REGS];
 450
 451         if (i != -1)
 452                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 453         else
 454                 printf (" %s", mono_inst_name (ins->opcode));
 455         if (spec == MONO_ARCH_CPU_SPEC) {
 456                 /* This is a lowered opcode */
 457                 if (ins->dreg != -1)
 458                         printf (" R%d <-", ins->dreg);
 459                 if (ins->sreg1 != -1)
 460                         printf (" R%d", ins->sreg1);
 461                 if (ins->sreg2 != -1)
 462                         printf (" R%d", ins->sreg2);
 463                 if (ins->sreg3 != -1)
 464                         printf (" R%d", ins->sreg3);
 465
 466                 switch (ins->opcode) {
 467                 case OP_LBNE_UN:
 468                 case OP_LBEQ:
 469                 case OP_LBLT:
 470                 case OP_LBLT_UN:
 471                 case OP_LBGT:
 472                 case OP_LBGT_UN:
 473                 case OP_LBGE:
 474                 case OP_LBGE_UN:
 475                 case OP_LBLE:
 476                 case OP_LBLE_UN:
 477                         if (!ins->inst_false_bb)
 478                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 479                         else
 480                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 481                         break;
 482                 case OP_PHI:
 483                 case OP_VPHI:
 484                 case OP_XPHI:
 485                 case OP_FPHI: {
 486                         int i;
 487                         printf (" [%d (", (int)ins->inst_c0);
 488                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 489                                 if (i)
 490                                         printf (", ");
 491                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 492                         }
 493                         printf (")]");
 494                         break;
 495                 }
 496                 case OP_LDADDR:
 497                 case OP_OUTARG_VTRETADDR:
 498                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 499                         break;
 500                 case OP_REGOFFSET:
 501                 case OP_GSHAREDVT_ARG_REGOFFSET:
 502                         printf (" + 0x%lx", (long)ins->inst_offset);
 503                         break;
 504                 default:
 505                         break;
 506                 }
 507
 508                 printf ("\n");
 509                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 510                 return;
 511         }
 512
 513         if (spec [MONO_INST_DEST]) {
 514                 int bank = dreg_bank (spec);
 515                 if (is_soft_reg (ins->dreg, bank)) {
 516                         if (spec [MONO_INST_DEST] == 'b') {
 517                                 if (ins->inst_offset == 0)
 518                                         printf (" [R%d] <-", ins->dreg);
 519                                 else
 520                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 521                         }
 522                         else
 523                                 printf (" R%d <-", ins->dreg);
 524                 } else if (spec [MONO_INST_DEST] == 'b') {
 525                         if (ins->inst_offset == 0)
 526                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 527                         else
 528                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 529                 } else
 530                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 531         }
 532         if (spec [MONO_INST_SRC1]) {
 533                 int bank = sreg1_bank (spec);
 534                 if (is_soft_reg (ins->sreg1, bank)) {
 535                         if (spec [MONO_INST_SRC1] == 'b')
 536                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 537                         else
 538                                 printf (" R%d", ins->sreg1);
 539                 } else if (spec [MONO_INST_SRC1] == 'b')
 540                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 541                 else
 542                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 543         }
 544         num_sregs = mono_inst_get_src_registers (ins, sregs);
 545         for (j = 1; j < num_sregs; ++j) {
 546                 int bank = sreg_bank (j, spec);
 547                 if (is_soft_reg (sregs [j], bank))
 548                         printf (" R%d", sregs [j]);
 549                 else
 550                         printf (" %s", mono_regname_full (sregs [j], bank));
 551         }
 552
 553         switch (ins->opcode) {
 554         case OP_ICONST:
 555                 printf (" [%d]", (int)ins->inst_c0);
 556                 break;
 557 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 558         case OP_X86_PUSH_IMM:
 559 #endif
 560         case OP_ICOMPARE_IMM:
 561         case OP_COMPARE_IMM:
 562         case OP_IADD_IMM:
 563         case OP_ISUB_IMM:
 564         case OP_IAND_IMM:
 565         case OP_IOR_IMM:
 566         case OP_IXOR_IMM:
 567         case OP_SUB_IMM:
 568                 printf (" [%d]", (int)ins->inst_imm);
 569                 break;
 570         case OP_ADD_IMM:
 571         case OP_LADD_IMM:
 572                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 573                 break;
 574         case OP_I8CONST:
 575                 printf (" [%lld]", (long long)ins->inst_l);
 576                 break;
 577         case OP_R8CONST:
 578                 printf (" [%f]", *(double*)ins->inst_p0);
 579                 break;
 580         case OP_R4CONST:
 581                 printf (" [%f]", *(float*)ins->inst_p0);
 582                 break;
 583         case OP_CALL:
 584         case OP_CALL_MEMBASE:
 585         case OP_CALL_REG:
 586         case OP_FCALL:
 587         case OP_LCALL:
 588         case OP_VCALL:
 589         case OP_VCALL_REG:
 590         case OP_VCALL_MEMBASE:
 591         case OP_VCALL2:
 592         case OP_VCALL2_REG:
 593         case OP_VCALL2_MEMBASE:
 594         case OP_VOIDCALL:
 595         case OP_VOIDCALL_MEMBASE:
 596         case OP_TAILCALL: {
 597                 MonoCallInst *call = (MonoCallInst*)ins;
 598                 GSList *list;
 599
 600                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 601                         /*
 602                          * These are lowered opcodes, but they are in the .md files since the old
 603                          * JIT passes them to backends.
 604                          */
 605                         if (ins->dreg != -1)
 606                                 printf (" R%d <-", ins->dreg);
 607                 }
 608
 609                 if (call->method) {
 610                         char *full_name = mono_method_full_name (call->method, TRUE);
 611                         printf (" [%s]", full_name);
 612                         g_free (full_name);
 613                 } else if (call->fptr_is_patch) {
 614                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 615
 616                         printf (" ");
 617                         mono_print_ji (ji);
 618                 } else if (call->fptr) {
 619                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 620                         if (info)
 621                                 printf (" [%s]", info->name);
 622                 }
 623
 624                 list = call->out_ireg_args;
 625                 while (list) {
 626                         guint32 regpair;
 627                         int reg, hreg;
 628
 629                         regpair = (guint32)(gssize)(list->data);
 630                         hreg = regpair >> 24;
 631                         reg = regpair & 0xffffff;
 632
 633                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 634
 635                         list = g_slist_next (list);
 636                 }
 637                 break;
 638         }
 639         case OP_BR:
 640         case OP_CALL_HANDLER:
 641                 printf (" [B%d]", ins->inst_target_bb->block_num);
 642                 break;
 643         case OP_IBNE_UN:
 644         case OP_IBEQ:
 645         case OP_IBLT:
 646         case OP_IBLT_UN:
 647         case OP_IBGT:
 648         case OP_IBGT_UN:
 649         case OP_IBGE:
 650         case OP_IBGE_UN:
 651         case OP_IBLE:
 652         case OP_IBLE_UN:
 653         case OP_LBNE_UN:
 654         case OP_LBEQ:
 655         case OP_LBLT:
 656         case OP_LBLT_UN:
 657         case OP_LBGT:
 658         case OP_LBGT_UN:
 659         case OP_LBGE:
 660         case OP_LBGE_UN:
 661         case OP_LBLE:
 662         case OP_LBLE_UN:
 663                 if (!ins->inst_false_bb)
 664                         printf (" [B%d]", ins->inst_true_bb->block_num);
 665                 else
 666                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 667                 break;
 668         case OP_LIVERANGE_START:
 669         case OP_LIVERANGE_END:
 670         case OP_GC_LIVENESS_DEF:
 671         case OP_GC_LIVENESS_USE:
 672                 printf (" R%d", (int)ins->inst_c1);
 673                 break;
 674         case OP_SEQ_POINT:
 675                 printf (" il: %x", (int)ins->inst_imm);
 676                 break;
 677         default:
 678                 break;
 679         }
 680
 681         if (spec [MONO_INST_CLOB])
 682                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 683         printf ("\n");
 684 }
 685
 686 static void
 687 print_regtrack (RegTrack *t, int num)
 688 {
 689         int i;
 690         char buf [32];
 691         const char *r;
 692
 693         for (i = 0; i < num; ++i) {
 694                 if (!t [i].born_in)
 695                         continue;
 696                 if (i >= MONO_MAX_IREGS) {
 697                         g_snprintf (buf, sizeof(buf), "R%d", i);
 698                         r = buf;
 699                 } else
 700                         r = mono_arch_regname (i);
 701                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 702         }
 703 }
 704 #else
 705
 706 void
 707 mono_print_ji (const MonoJumpInfo *ji)
 708 {
 709 }
 710
 711 void
 712 mono_print_ins_index (int i, MonoInst *ins)
 713 {
 714 }
 715 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 716
 717 void
 718 mono_print_ins (MonoInst *ins)
 719 {
 720         mono_print_ins_index (-1, ins);
 721 }
 722
 723 static inline void
 724 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 725 {
 726         /*
 727          * If this function is called multiple times, the new instructions are inserted
 728          * in the proper order.
 729          */
 730         mono_bblock_insert_before_ins (bb, ins, to_insert);
 731 }
 732
 733 static inline void
 734 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 735 {
 736         /*
 737          * If this function is called multiple times, the new instructions are inserted in
 738          * proper order.
 739          */
 740         mono_bblock_insert_after_ins (bb, *last, to_insert);
 741
 742         *last = to_insert;
 743 }
 744
 745 static inline int
 746 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 747 {
 748         if (vreg_is_ref (cfg, reg))
 749                 return MONO_REG_INT_REF;
 750         else if (vreg_is_mp (cfg, reg))
 751                 return MONO_REG_INT_MP;
 752         else
 753                 return bank;
 754 }
 755
 756 /*
 757  * Force the spilling of the variable in the symbolic register 'reg', and free
 758  * the hreg it was assigned to.
 759  */
 760 static void
 761 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 762 {
 763         MonoInst *load;
 764         int i, sel, spill;
 765         int *symbolic;
 766         MonoRegState *rs = cfg->rs;
 767
 768         symbolic = rs->symbolic [bank];
 769         sel = rs->vassign [reg];
 770
 771         /* the vreg we need to spill lives in another logical reg bank */
 772         bank = translate_bank (cfg->rs, bank, sel);
 773
 774         /*i = rs->isymbolic [sel];
 775         g_assert (i == reg);*/
 776         i = reg;
 777         spill = ++cfg->spill_count;
 778         rs->vassign [i] = -spill - 1;
 779         if (G_UNLIKELY (bank))
 780                 mono_regstate_free_general (rs, sel, bank);
 781         else
 782                 mono_regstate_free_int (rs, sel);
 783         /* we need to create a spill var and insert a load to sel after the current instruction */
 784         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 785         load->dreg = sel;
 786         load->inst_basereg = cfg->frame_reg;
 787         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 788         insert_after_ins (bb, ins, last, load);
 789         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 790         if (G_UNLIKELY (bank))
 791                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 792         else
 793                 i = mono_regstate_alloc_int (rs, regmask (sel));
 794         g_assert (i == sel);
 795
 796         if (G_UNLIKELY (bank))
 797                 mono_regstate_free_general (rs, sel, bank);
 798         else
 799                 mono_regstate_free_int (rs, sel);
 800 }
 801
 802 /* This isn't defined on older glib versions and on some platforms */
 803 #ifndef G_GUINT64_FORMAT
 804 #define G_GUINT64_FORMAT "ul"
 805 #endif
 806
 807 static int
 808 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 809 {
 810         MonoInst *load;
 811         int i, sel, spill, num_sregs;
 812         int sregs [MONO_MAX_SRC_REGS];
 813         int *symbolic;
 814         MonoRegState *rs = cfg->rs;
 815
 816         symbolic = rs->symbolic [bank];
 817
 818         g_assert (bank < MONO_NUM_REGBANKS);
 819
 820         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 821         /* exclude the registers in the current instruction */
 822         num_sregs = mono_inst_get_src_registers (ins, sregs);
 823         for (i = 0; i < num_sregs; ++i) {
 824                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 825                         if (is_soft_reg (sregs [i], bank))
 826                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 827                         else
 828                                 regmask &= ~ (regmask (sregs [i]));
 829                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 830                 }
 831         }
 832         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 833                 regmask &= ~ (regmask (ins->dreg));
 834                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 835         }
 836
 837         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 838         g_assert (regmask); /* need at least a register we can free */
 839         sel = 0;
 840         /* we should track prev_use and spill the register that's farther */
 841         if (G_UNLIKELY (bank)) {
 842                 for (i = 0; i < regbank_size [bank]; ++i) {
 843                         if (regmask & (regmask (i))) {
 844                                 sel = i;
 845
 846                                 /* the vreg we need to load lives in another logical bank */
 847                                 bank = translate_bank (cfg->rs, bank, sel);
 848
 849                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 850                                 break;
 851                         }
 852                 }
 853
 854                 i = rs->symbolic [bank] [sel];
 855                 spill = ++cfg->spill_count;
 856                 rs->vassign [i] = -spill - 1;
 857                 mono_regstate_free_general (rs, sel, bank);
 858         }
 859         else {
 860                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 861                         if (regmask & (regmask (i))) {
 862                                 sel = i;
 863                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 864                                 break;
 865                         }
 866                 }
 867
 868                 i = rs->isymbolic [sel];
 869                 spill = ++cfg->spill_count;
 870                 rs->vassign [i] = -spill - 1;
 871                 mono_regstate_free_int (rs, sel);
 872         }
 873
 874         /* we need to create a spill var and insert a load to sel after the current instruction */
 875         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 876         load->dreg = sel;
 877         load->inst_basereg = cfg->frame_reg;
 878         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 879         insert_after_ins (bb, ins, last, load);
 880         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 881         if (G_UNLIKELY (bank))
 882                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 883         else
 884                 i = mono_regstate_alloc_int (rs, regmask (sel));
 885         g_assert (i == sel);
 886
 887         return sel;
 888 }
 889
 890 /*
 891  * free_up_hreg:
 892  *
 893  *   Free up the hreg HREG by spilling the vreg allocated to it.
 894  */
 895 static void
 896 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 897 {
 898         if (G_UNLIKELY (bank)) {
 899                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 900                         bank = translate_bank (cfg->rs, bank, hreg);
 901                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 902                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 903                 }
 904         }
 905         else {
 906                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 907                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 908                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 909                 }
 910         }
 911 }
 912
 913 static MonoInst*
 914 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 915 {
 916         MonoInst *copy;
 917
 918         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 919
 920         copy->dreg = dest;
 921         copy->sreg1 = src;
 922         copy->cil_code = ip;
 923         if (ins) {
 924                 mono_bblock_insert_after_ins (bb, ins, copy);
 925                 *last = copy;
 926         }
 927         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 928         return copy;
 929 }
 930
 931 static inline const char*
 932 regbank_to_string (int bank)
 933 {
 934         if (bank == MONO_REG_INT_REF)
 935                 return "REF ";
 936         else if (bank == MONO_REG_INT_MP)
 937                 return "MP ";
 938         else
 939                 return "";
 940 }
 941
 942 static void
 943 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 944 {
 945         MonoInst *store, *def;
 946
 947         bank = get_vreg_bank (cfg, prev_reg, bank);
 948
 949         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 950         store->sreg1 = reg;
 951         store->inst_destbasereg = cfg->frame_reg;
 952         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 953         if (ins) {
 954                 mono_bblock_insert_after_ins (bb, ins, store);
 955                 *last = store;
 956         } else if (insert_before) {
 957                 insert_before_ins (bb, insert_before, store);
 958         } else {
 959                 g_assert_not_reached ();
 960         }
 961         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 962
 963         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 964                 g_assert (prev_reg != -1);
 965                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 966                 def->inst_c0 = spill;
 967                 def->inst_c1 = bank;
 968                 mono_bblock_insert_after_ins (bb, store, def);
 969         }
 970 }
 971
 972 /* flags used in reginfo->flags */
 973 enum {
 974         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 975         MONO_FP_NEEDS_SPILL                     = regmask (1),
 976         MONO_FP_NEEDS_LOAD                      = regmask (2)
 977 };
 978
 979 static inline int
 980 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 981 {
 982         int val;
 983
 984         if (info && info->preferred_mask) {
 985                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 986                 if (val >= 0) {
 987                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 988                         return val;
 989                 }
 990         }
 991
 992         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 993         if (val < 0)
 994                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 995
 996         return val;
 997 }
 998
 999 static inline int
1000 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1001 {
1002         int val;
1003
1004         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1005
1006         if (val < 0)
1007                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1008
1009         return val;
1010 }
1011
1012 static inline int
1013 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1014 {
1015         if (G_UNLIKELY (bank))
1016                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1017         else
1018                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1019 }
1020
1021 static inline void
1022 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1023 {
1024         if (G_UNLIKELY (bank)) {
1025                 int mirrored_bank;
1026
1027                 g_assert (reg >= regbank_size [bank]);
1028                 g_assert (hreg < regbank_size [bank]);
1029                 g_assert (! is_global_freg (hreg));
1030
1031                 rs->vassign [reg] = hreg;
1032                 rs->symbolic [bank] [hreg] = reg;
1033                 rs->free_mask [bank] &= ~ (regmask (hreg));
1034
1035                 mirrored_bank = get_mirrored_bank (bank);
1036                 if (mirrored_bank == -1)
1037                         return;
1038
1039                 /* Make sure the other logical reg bank that this bank shares
1040                  * a single hard reg bank knows that this hard reg is not free.
1041                  */
1042                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1043
1044                 /* Mark the other logical bank that the this bank shares
1045                  * a single hard reg bank with as mirrored.
1046                  */
1047                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1048
1049         }
1050         else {
1051                 g_assert (reg >= MONO_MAX_IREGS);
1052                 g_assert (hreg < MONO_MAX_IREGS);
1053 #ifndef TARGET_ARM
1054                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1055                 g_assert (! is_global_ireg (hreg));
1056 #endif
1057
1058                 rs->vassign [reg] = hreg;
1059                 rs->isymbolic [hreg] = reg;
1060                 rs->ifree_mask &= ~ (regmask (hreg));
1061         }
1062 }
1063
1064 static inline regmask_t
1065 get_callee_mask (const char spec)
1066 {
1067         if (G_UNLIKELY (reg_bank (spec)))
1068                 return regbank_callee_regs [reg_bank (spec)];
1069         return MONO_ARCH_CALLEE_REGS;
1070 }
1071
1072 static gint8 desc_to_fixed_reg [256];
1073 static gboolean desc_to_fixed_reg_inited = FALSE;
1074
1075 #ifndef DISABLE_JIT
1076
1077 /*
1078  * Local register allocation.
1079  * We first scan the list of instructions and we save the liveness info of
1080  * each register (when the register is first used, when it's value is set etc.).
1081  * We also reverse the list of instructions because assigning registers backwards allows
1082  * for more tricks to be used.
1083  */
1084 void
1085 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1086 {
1087         MonoInst *ins, *prev, *last;
1088         MonoInst **tmp;
1089         MonoRegState *rs = cfg->rs;
1090         int i, j, val, max;
1091         RegTrack *reginfo;
1092         const char *spec;
1093         unsigned char spec_src1, spec_dest;
1094         int bank = 0;
1095 #if MONO_ARCH_USE_FPSTACK
1096         gboolean has_fp = FALSE;
1097         int fpstack [8];
1098         int sp = 0;
1099 #endif
1100         int num_sregs = 0;
1101         int sregs [MONO_MAX_SRC_REGS];
1102
1103         if (!bb->code)
1104                 return;
1105
1106         if (!desc_to_fixed_reg_inited) {
1107                 for (i = 0; i < 256; ++i)
1108                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1109                 desc_to_fixed_reg_inited = TRUE;
1110
1111                 /* Validate the cpu description against the info in mini-ops.h */
1112 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1113                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1114                         const char *ispec;
1115
1116                         spec = ins_get_spec (i);
1117                         ispec = INS_INFO (i);
1118
1119                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1120                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1121                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1122                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1123                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1124                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1125                 }
1126 #endif
1127         }
1128
1129         rs->next_vreg = bb->max_vreg;
1130         mono_regstate_assign (rs);
1131
1132         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1133         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1134                 rs->free_mask [i] = regbank_callee_regs [i];
1135
1136         max = rs->next_vreg;
1137
1138         if (cfg->reginfo && cfg->reginfo_len < max)
1139                 cfg->reginfo = NULL;
1140
1141         reginfo = cfg->reginfo;
1142         if (!reginfo) {
1143                 cfg->reginfo_len = MAX (1024, max * 2);
1144                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1145         }
1146         else
1147                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1148
1149         if (cfg->verbose_level > 1) {
1150                 /* print_regtrack reads the info of all variables */
1151                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1152         }
1153
1154         /*
1155          * For large methods, next_vreg can be very large, so g_malloc0 time can
1156          * be prohibitive. So we manually init the reginfo entries used by the
1157          * bblock.
1158          */
1159         for (ins = bb->code; ins; ins = ins->next) {
1160                 spec = ins_get_spec (ins->opcode);
1161
1162                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1163                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1164 #if SIZEOF_REGISTER == 4
1165                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1166                                 /**
1167                                  * In the new IR, the two vregs of the regpair do not alias the
1168                                  * original long vreg. shift the vreg here so the rest of the
1169                                  * allocator doesn't have to care about it.
1170                                  */
1171                                 ins->dreg ++;
1172                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1173                         }
1174 #endif
1175                 }
1176
1177                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1178                 for (j = 0; j < num_sregs; ++j) {
1179                         g_assert (sregs [j] != -1);
1180                         if (sregs [j] < max) {
1181                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1182 #if SIZEOF_REGISTER == 4
1183                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1184                                         sregs [j]++;
1185                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1186                                 }
1187 #endif
1188                         }
1189                 }
1190                 mono_inst_set_src_registers (ins, sregs);
1191         }
1192
1193         /*if (cfg->opt & MONO_OPT_COPYPROP)
1194                 local_copy_prop (cfg, ins);*/
1195
1196         i = 1;
1197         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1198         /* forward pass on the instructions to collect register liveness info */
1199         MONO_BB_FOR_EACH_INS (bb, ins) {
1200                 spec = ins_get_spec (ins->opcode);
1201                 spec_dest = spec [MONO_INST_DEST];
1202
1203                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1204                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1205                 }
1206
1207                 DEBUG (mono_print_ins_index (i, ins));
1208
1209                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1210
1211 #if MONO_ARCH_USE_FPSTACK
1212                 if (dreg_is_fp (spec)) {
1213                         has_fp = TRUE;
1214                 } else {
1215                         for (j = 0; j < num_sregs; ++j) {
1216                                 if (sreg_is_fp (j, spec))
1217                                         has_fp = TRUE;
1218                         }
1219                 }
1220 #endif
1221
1222                 for (j = 0; j < num_sregs; ++j) {
1223                         int sreg = sregs [j];
1224                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1225                         if (sreg_spec) {
1226                                 bank = sreg_bank (j, spec);
1227                                 g_assert (sreg != -1);
1228                                 if (is_soft_reg (sreg, bank))
1229                                         /* This means the vreg is not local to this bb */
1230                                         g_assert (reginfo [sreg].born_in > 0);
1231                                 rs->vassign [sreg] = -1;
1232                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1233                                 //reginfo [ins->sreg2].last_use = i;
1234                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1235                                         /* The virtual register is allocated sequentially */
1236                                         rs->vassign [sreg + 1] = -1;
1237                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1238                                         //reginfo [ins->sreg2 + 1].last_use = i;
1239                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1240                                                 reginfo [sreg + 1].born_in = i;
1241                                 }
1242                         } else {
1243                                 sregs [j] = -1;
1244                         }
1245                 }
1246                 mono_inst_set_src_registers (ins, sregs);
1247
1248                 if (spec_dest) {
1249                         int dest_dreg;
1250
1251                         bank = dreg_bank (spec);
1252                         if (spec_dest != 'b') /* it's not just a base register */
1253                                 reginfo [ins->dreg].killed_in = i;
1254                         g_assert (ins->dreg != -1);
1255                         rs->vassign [ins->dreg] = -1;
1256                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1257                         //reginfo [ins->dreg].last_use = i;
1258                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1259                                 reginfo [ins->dreg].born_in = i;
1260
1261                         dest_dreg = desc_to_fixed_reg [spec_dest];
1262                         if (dest_dreg != -1)
1263                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1264
1265 #ifdef MONO_ARCH_INST_FIXED_MASK
1266                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1267 #endif
1268
1269                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1270                                 /* The virtual register is allocated sequentially */
1271                                 rs->vassign [ins->dreg + 1] = -1;
1272                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1273                                 //reginfo [ins->dreg + 1].last_use = i;
1274                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1275                                         reginfo [ins->dreg + 1].born_in = i;
1276                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1277                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1278                         }
1279                 } else {
1280                         ins->dreg = -1;
1281                 }
1282
1283                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1284                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1285
1286                         MonoCallInst *call = (MonoCallInst*)ins;
1287                         GSList *list;
1288
1289                         list = call->out_ireg_args;
1290                         if (list) {
1291                                 while (list) {
1292                                         guint32 regpair;
1293                                         int reg, hreg;
1294
1295                                         regpair = (guint32)(gssize)(list->data);
1296                                         hreg = regpair >> 24;
1297                                         reg = regpair & 0xffffff;
1298
1299                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1300                                         //reginfo [reg].last_use = i;
1301
1302                                         list = g_slist_next (list);
1303                                 }
1304                         }
1305
1306                         list = call->out_freg_args;
1307                         if (list) {
1308                                 while (list) {
1309                                         guint32 regpair;
1310                                         int reg, hreg;
1311
1312                                         regpair = (guint32)(gssize)(list->data);
1313                                         hreg = regpair >> 24;
1314                                         reg = regpair & 0xffffff;
1315
1316                                         list = g_slist_next (list);
1317                                 }
1318                         }
1319                 }
1320
1321                 ++i;
1322         }
1323
1324         tmp = &last;
1325
1326         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1327         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1328                 int prev_dreg, clob_dreg;
1329                 int dest_dreg, clob_reg;
1330                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1331                 int dreg_high, sreg1_high;
1332                 regmask_t dreg_mask, mask;
1333                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1334                 regmask_t dreg_fixed_mask;
1335                 const unsigned char *ip;
1336                 --i;
1337                 spec = ins_get_spec (ins->opcode);
1338                 spec_src1 = spec [MONO_INST_SRC1];
1339                 spec_dest = spec [MONO_INST_DEST];
1340                 prev_dreg = -1;
1341                 clob_dreg = -1;
1342                 clob_reg = -1;
1343                 dest_dreg = -1;
1344                 dreg_high = -1;
1345                 sreg1_high = -1;
1346                 dreg_mask = get_callee_mask (spec_dest);
1347                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1348                         prev_sregs [j] = -1;
1349                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1350                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1351 #ifdef MONO_ARCH_INST_FIXED_MASK
1352                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1353 #else
1354                         sreg_fixed_masks [j] = 0;
1355 #endif
1356                 }
1357
1358                 DEBUG (printf ("processing:"));
1359                 DEBUG (mono_print_ins_index (i, ins));
1360
1361                 ip = ins->cil_code;
1362
1363                 last = ins;
1364
1365                 /*
1366                  * FIXED REGS
1367                  */
1368                 dest_dreg = desc_to_fixed_reg [spec_dest];
1369                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1370                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1371
1372 #ifdef MONO_ARCH_INST_FIXED_MASK
1373                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1374 #else
1375                 dreg_fixed_mask = 0;
1376 #endif
1377
1378                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1379
1380                 /*
1381                  * TRACK FIXED SREG2, 3, ...
1382                  */
1383                 for (j = 1; j < num_sregs; ++j) {
1384                         int sreg = sregs [j];
1385                         int dest_sreg = dest_sregs [j];
1386
1387                         if (dest_sreg == -1)
1388                                 continue;
1389
1390                         if (j == 2) {
1391                                 int k;
1392
1393                                 /*
1394                                  * CAS.
1395                                  * We need to special case this, since on x86, there are only 3
1396                                  * free registers, and the code below assigns one of them to
1397                                  * sreg, so we can run out of registers when trying to assign
1398                                  * dreg. Instead, we just set up the register masks, and let the
1399                                  * normal sreg2 assignment code handle this. It would be nice to
1400                                  * do this for all the fixed reg cases too, but there is too much
1401                                  * risk of breakage.
1402                                  */
1403
1404                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1405                                 sreg_masks [j] = regmask (dest_sreg);
1406                                 for (k = 0; k < num_sregs; ++k) {
1407                                         if (k != j)
1408                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1409                                 }
1410
1411                                 /*
1412                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1413                                  */
1414                                 for (k = 0; k < num_sregs; ++k) {
1415                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1416                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1417                                 }
1418
1419                                 /*
1420                                  * We can also run out of registers while processing sreg2 if sreg3 is
1421                                  * assigned to another hreg, so spill sreg3 now.
1422                                  */
1423                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1424                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1425                                 }
1426                                 continue;
1427                         }
1428
1429                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1430                                 if (is_global_ireg (sreg)) {
1431                                         int k;
1432                                         /* Argument already in hard reg, need to copy */
1433                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1434                                         insert_before_ins (bb, ins, copy);
1435                                         for (k = 0; k < num_sregs; ++k) {
1436                                                 if (k != j)
1437                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1438                                         }
1439                                 } else {
1440                                         val = rs->vassign [sreg];
1441                                         if (val == -1) {
1442                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1443                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1444                                         } else if (val < -1) {
1445                                                 /* FIXME: */
1446                                                 g_assert_not_reached ();
1447                                         } else {
1448                                                 /* Argument already in hard reg, need to copy */
1449                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1450                                                 int k;
1451
1452                                                 insert_before_ins (bb, ins, copy);
1453                                                 for (k = 0; k < num_sregs; ++k) {
1454                                                         if (k != j)
1455                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1456                                                 }
1457                                                 /*
1458                                                  * Prevent the dreg from being allocate to dest_sreg
1459                                                  * too, since it could force sreg1 to be allocated to
1460                                                  * the same reg on x86.
1461                                                  */
1462                                                 dreg_mask &= ~ (regmask (dest_sreg));
1463                                         }
1464                                 }
1465                         } else {
1466                                 gboolean need_spill = TRUE;
1467                                 gboolean need_assign = TRUE;
1468                                 int k;
1469
1470                                 dreg_mask &= ~ (regmask (dest_sreg));
1471                                 for (k = 0; k < num_sregs; ++k) {
1472                                         if (k != j)
1473                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1474                                 }
1475
1476                                 /*
1477                                  * First check if dreg is assigned to dest_sreg2, since we
1478                                  * can't spill a dreg.
1479                                  */
1480                                 if (spec [MONO_INST_DEST])
1481                                         val = rs->vassign [ins->dreg];
1482                                 else
1483                                         val = -1;
1484                                 if (val == dest_sreg && ins->dreg != sreg) {
1485                                         /*
1486                                          * the destination register is already assigned to
1487                                          * dest_sreg2: we need to allocate another register for it
1488                                          * and then copy from this to dest_sreg2.
1489                                          */
1490                                         int new_dest;
1491                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1492                                         g_assert (new_dest >= 0);
1493                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1494
1495                                         prev_dreg = ins->dreg;
1496                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1497                                         clob_dreg = ins->dreg;
1498                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1499                                         mono_regstate_free_int (rs, dest_sreg);
1500                                         need_spill = FALSE;
1501                                 }
1502
1503                                 if (is_global_ireg (sreg)) {
1504                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1505                                         insert_before_ins (bb, ins, copy);
1506                                         need_assign = FALSE;
1507                                 }
1508                                 else {
1509                                         val = rs->vassign [sreg];
1510                                         if (val == dest_sreg) {
1511                                                 /* sreg2 is already assigned to the correct register */
1512                                                 need_spill = FALSE;
1513                                         } else if (val < -1) {
1514                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1515                                         } else if (val >= 0) {
1516                                                 /* sreg2 already assigned to another register */
1517                                                 /*
1518                                                  * We couldn't emit a copy from val to dest_sreg2, because
1519                                                  * val might be spilled later while processing this
1520                                                  * instruction. So we spill sreg2 so it can be allocated to
1521                                                  * dest_sreg2.
1522                                                  */
1523                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1524                                         }
1525                                 }
1526
1527                                 if (need_spill) {
1528                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1529                                 }
1530
1531                                 if (need_assign) {
1532                                         if (rs->vassign [sreg] < -1) {
1533                                                 int spill;
1534
1535                                                 /* Need to emit a spill store */
1536                                                 spill = - rs->vassign [sreg] - 1;
1537                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1538                                         }
1539                                         /* force-set sreg2 */
1540                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1541                                 }
1542                         }
1543                         sregs [j] = dest_sreg;
1544                 }
1545                 mono_inst_set_src_registers (ins, sregs);
1546
1547                 /*
1548                  * TRACK DREG
1549                  */
1550                 bank = dreg_bank (spec);
1551                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1552                         prev_dreg = ins->dreg;
1553                 }
1554
1555                 if (spec_dest == 'b') {
1556                         /*
1557                          * The dest reg is read by the instruction, not written, so
1558                          * avoid allocating sreg1/sreg2 to the same reg.
1559                          */
1560                         if (dest_sregs [0] != -1)
1561                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1562                         for (j = 1; j < num_sregs; ++j) {
1563                                 if (dest_sregs [j] != -1)
1564                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1565                         }
1566
1567                         val = rs->vassign [ins->dreg];
1568                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1569                                 /* DREG is already allocated to a register needed for sreg1 */
1570                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1571                         }
1572                 }
1573
1574                 /*
1575                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1576                  * various complex situations.
1577                  */
1578                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1579                         guint32 dreg2, dest_dreg2;
1580
1581                         g_assert (is_soft_reg (ins->dreg, bank));
1582
1583                         if (dest_dreg != -1) {
1584                                 if (rs->vassign [ins->dreg] != dest_dreg)
1585                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1586
1587                                 dreg2 = ins->dreg + 1;
1588                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1589                                 if (dest_dreg2 != -1) {
1590                                         if (rs->vassign [dreg2] != dest_dreg2)
1591                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1592                                 }
1593                         }
1594                 }
1595
1596                 if (dreg_fixed_mask) {
1597                         g_assert (!bank);
1598                         if (is_global_ireg (ins->dreg)) {
1599                                 /*
1600                                  * The argument is already in a hard reg, but that reg is
1601                                  * not usable by this instruction, so allocate a new one.
1602                                  */
1603                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1604                                 if (val < 0)
1605                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1606                                 mono_regstate_free_int (rs, val);
1607                                 dest_dreg = val;
1608
1609                                 /* Fall through */
1610                         }
1611                         else
1612                                 dreg_mask &= dreg_fixed_mask;
1613                 }
1614
1615                 if (is_soft_reg (ins->dreg, bank)) {
1616                         val = rs->vassign [ins->dreg];
1617
1618                         if (val < 0) {
1619                                 int spill = 0;
1620                                 if (val < -1) {
1621                                         /* the register gets spilled after this inst */
1622                                         spill = -val -1;
1623                                 }
1624                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1625                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1626                                 if (spill)
1627                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1628                         }
1629
1630                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1631                         ins->dreg = val;
1632                 }
1633
1634                 /* Handle regpairs */
1635                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1636                         int reg2 = prev_dreg + 1;
1637
1638                         g_assert (!bank);
1639                         g_assert (prev_dreg > -1);
1640                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1641                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1642 #ifdef TARGET_X86
1643                         /* bug #80489 */
1644                         mask &= ~regmask (X86_ECX);
1645 #endif
1646                         val = rs->vassign [reg2];
1647                         if (val < 0) {
1648                                 int spill = 0;
1649                                 if (val < -1) {
1650                                         /* the register gets spilled after this inst */
1651                                         spill = -val -1;
1652                                 }
1653                                 val = mono_regstate_alloc_int (rs, mask);
1654                                 if (val < 0)
1655                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1656                                 if (spill)
1657                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1658                         }
1659                         else {
1660                                 if (! (mask & (regmask (val)))) {
1661                                         val = mono_regstate_alloc_int (rs, mask);
1662                                         if (val < 0)
1663                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1664
1665                                         /* Reallocate hreg to the correct register */
1666                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1667
1668                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1669                                 }
1670                         }
1671
1672                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1673                         assign_reg (cfg, rs, reg2, val, bank);
1674
1675                         dreg_high = val;
1676                         ins->backend.reg3 = val;
1677
1678                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1679                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1680                                 mono_regstate_free_int (rs, val);
1681                         }
1682                 }
1683
1684                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1685                         /*
1686                          * In theory, we could free up the hreg even if the vreg is alive,
1687                          * but branches inside bblocks force us to assign the same hreg
1688                          * to a vreg every time it is encountered.
1689                          */
1690                         int dreg = rs->vassign [prev_dreg];
1691                         g_assert (dreg >= 0);
1692                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1693                         if (G_UNLIKELY (bank))
1694                                 mono_regstate_free_general (rs, dreg, bank);
1695                         else
1696                                 mono_regstate_free_int (rs, dreg);
1697                         rs->vassign [prev_dreg] = -1;
1698                 }
1699
1700                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1701                         /* this instruction only outputs to dest_dreg, need to copy */
1702                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1703                         ins->dreg = dest_dreg;
1704
1705                         if (G_UNLIKELY (bank)) {
1706                                 /* the register we need to free up may be used in another logical regbank
1707                                  * so do a translate just in case.
1708                                  */
1709                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1710                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1711                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1712                         }
1713                         else {
1714                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1715                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1716                         }
1717                 }
1718
1719                 if (spec_dest == 'b') {
1720                         /*
1721                          * The dest reg is read by the instruction, not written, so
1722                          * avoid allocating sreg1/sreg2 to the same reg.
1723                          */
1724                         for (j = 0; j < num_sregs; ++j)
1725                                 if (!sreg_bank (j, spec))
1726                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1727                 }
1728
1729                 /*
1730                  * TRACK CLOBBERING
1731                  */
1732                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1733                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1734                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1735                 }
1736
1737                 if (spec [MONO_INST_CLOB] == 'c') {
1738                         int j, s, dreg, dreg2, cur_bank;
1739                         guint64 clob_mask;
1740
1741                         clob_mask = MONO_ARCH_CALLEE_REGS;
1742
1743                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1744                                 /*
1745                                  * Need to avoid spilling the dreg since the dreg is not really
1746                                  * clobbered by the call.
1747                                  */
1748                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1749                                         dreg = rs->vassign [prev_dreg];
1750                                 else
1751                                         dreg = -1;
1752
1753                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1754                                         dreg2 = rs->vassign [prev_dreg + 1];
1755                                 else
1756                                         dreg2 = -1;
1757
1758                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1759                                         s = regmask (j);
1760                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1761                                                 if ((j != dreg) && (j != dreg2))
1762                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1763                                                 else if (rs->isymbolic [j])
1764                                                         /* The hreg is assigned to the dreg of this instruction */
1765                                                         rs->vassign [rs->isymbolic [j]] = -1;
1766                                                 mono_regstate_free_int (rs, j);
1767                                         }
1768                                 }
1769                         }
1770
1771                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1772                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1773                                         clob_mask = regbank_callee_regs [cur_bank];
1774                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1775                                                 dreg = rs->vassign [prev_dreg];
1776                                         else
1777                                                 dreg = -1;
1778
1779                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1780
1781                                                 /* we are looping though the banks in the outer loop
1782                                                  * so, we don't need to deal with mirrored hregs
1783                                                  * because we will get them in one of the other bank passes.
1784                                                  */
1785                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1786                                                         continue;
1787
1788                                                 s = regmask (j);
1789                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1790                                                         if (j != dreg)
1791                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1792                                                         else if (rs->symbolic [cur_bank] [j])
1793                                                                 /* The hreg is assigned to the dreg of this instruction */
1794                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1795                                                         mono_regstate_free_general (rs, j, cur_bank);
1796                                                 }
1797                                         }
1798                                 }
1799                         }
1800                 }
1801
1802                 /*
1803                  * TRACK ARGUMENT REGS
1804                  */
1805                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1806                         MonoCallInst *call = (MonoCallInst*)ins;
1807                         GSList *list;
1808
1809                         /*
1810                          * This needs to be done before assigning sreg1, so sreg1 will
1811                          * not be assigned one of the argument regs.
1812                          */
1813
1814                         /*
1815                          * Assign all registers in call->out_reg_args to the proper
1816                          * argument registers.
1817                          */
1818
1819                         list = call->out_ireg_args;
1820                         if (list) {
1821                                 while (list) {
1822                                         guint32 regpair;
1823                                         int reg, hreg;
1824
1825                                         regpair = (guint32)(gssize)(list->data);
1826                                         hreg = regpair >> 24;
1827                                         reg = regpair & 0xffffff;
1828
1829                                         assign_reg (cfg, rs, reg, hreg, 0);
1830
1831                                         sreg_masks [0] &= ~(regmask (hreg));
1832
1833                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1834
1835                                         list = g_slist_next (list);
1836                                 }
1837                         }
1838
1839                         list = call->out_freg_args;
1840                         if (list) {
1841                                 while (list) {
1842                                         guint32 regpair;
1843                                         int reg, hreg;
1844
1845                                         regpair = (guint32)(gssize)(list->data);
1846                                         hreg = regpair >> 24;
1847                                         reg = regpair & 0xffffff;
1848
1849                                         assign_reg (cfg, rs, reg, hreg, 1);
1850
1851                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1852
1853                                         list = g_slist_next (list);
1854                                 }
1855                         }
1856                 }
1857
1858                 /*
1859                  * TRACK SREG1
1860                  */
1861                 bank = sreg1_bank (spec);
1862                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1863                         int sreg1 = sregs [0];
1864                         int dest_sreg1 = dest_sregs [0];
1865
1866                         g_assert (is_soft_reg (sreg1, bank));
1867
1868                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1869                         if (dest_sreg1 != -1)
1870                                 g_assert (dest_sreg1 == ins->dreg);
1871                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1872                         g_assert (val >= 0);
1873
1874                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1875                                 // FIXME:
1876                                 g_assert_not_reached ();
1877
1878                         assign_reg (cfg, rs, sreg1, val, bank);
1879
1880                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1881
1882                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1883                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1884                         g_assert (val >= 0);
1885
1886                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1887                                 // FIXME:
1888                                 g_assert_not_reached ();
1889
1890                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1891
1892                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1893
1894                         /* Skip rest of this section */
1895                         dest_sregs [0] = -1;
1896                 }
1897
1898                 if (sreg_fixed_masks [0]) {
1899                         g_assert (!bank);
1900                         if (is_global_ireg (sregs [0])) {
1901                                 /*
1902                                  * The argument is already in a hard reg, but that reg is
1903                                  * not usable by this instruction, so allocate a new one.
1904                                  */
1905                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1906                                 if (val < 0)
1907                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1908                                 mono_regstate_free_int (rs, val);
1909                                 dest_sregs [0] = val;
1910
1911                                 /* Fall through to the dest_sreg1 != -1 case */
1912                         }
1913                         else
1914                                 sreg_masks [0] &= sreg_fixed_masks [0];
1915                 }
1916
1917                 if (dest_sregs [0] != -1) {
1918                         sreg_masks [0] = regmask (dest_sregs [0]);
1919
1920                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1921                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1922                         }
1923                         if (is_global_ireg (sregs [0])) {
1924                                 /* The argument is already in a hard reg, need to copy */
1925                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1926                                 insert_before_ins (bb, ins, copy);
1927                                 sregs [0] = dest_sregs [0];
1928                         }
1929                 }
1930
1931                 if (is_soft_reg (sregs [0], bank)) {
1932                         val = rs->vassign [sregs [0]];
1933                         prev_sregs [0] = sregs [0];
1934                         if (val < 0) {
1935                                 int spill = 0;
1936                                 if (val < -1) {
1937                                         /* the register gets spilled after this inst */
1938                                         spill = -val -1;
1939                                 }
1940
1941                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1942                                         /*
1943                                          * Allocate the same hreg to sreg1 as well so the
1944                                          * peephole can get rid of the move.
1945                                          */
1946                                         sreg_masks [0] = regmask (ins->dreg);
1947                                 }
1948
1949                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1950                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1951                                         sreg_masks [0] = regmask (ins->dreg);
1952
1953                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1954                                 assign_reg (cfg, rs, sregs [0], val, bank);
1955                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1956
1957                                 if (spill) {
1958                                         /*
1959                                          * Need to insert before the instruction since it can
1960                                          * overwrite sreg1.
1961                                          */
1962                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1963                                 }
1964                         }
1965                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1966                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1967                                 insert_before_ins (bb, ins, copy);
1968                                 for (j = 1; j < num_sregs; ++j)
1969                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1970                                 val = dest_sregs [0];
1971                         }
1972
1973                         sregs [0] = val;
1974                 }
1975                 else {
1976                         prev_sregs [0] = -1;
1977                 }
1978                 mono_inst_set_src_registers (ins, sregs);
1979
1980                 for (j = 1; j < num_sregs; ++j)
1981                         sreg_masks [j] &= ~(regmask (sregs [0]));
1982
1983                 /* Handle the case when sreg1 is a regpair but dreg is not */
1984                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1985                         int reg2 = prev_sregs [0] + 1;
1986
1987                         g_assert (!bank);
1988                         g_assert (prev_sregs [0] > -1);
1989                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1990                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1991                         val = rs->vassign [reg2];
1992                         if (val < 0) {
1993                                 int spill = 0;
1994                                 if (val < -1) {
1995                                         /* the register gets spilled after this inst */
1996                                         spill = -val -1;
1997                                 }
1998                                 val = mono_regstate_alloc_int (rs, mask);
1999                                 if (val < 0)
2000                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2001                                 if (spill)
2002                                         g_assert_not_reached ();
2003                         }
2004                         else {
2005                                 if (! (mask & (regmask (val)))) {
2006                                         /* The vreg is already allocated to a wrong hreg */
2007                                         /* FIXME: */
2008                                         g_assert_not_reached ();
2009 #if 0
2010                                         val = mono_regstate_alloc_int (rs, mask);
2011                                         if (val < 0)
2012                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2013
2014                                         /* Reallocate hreg to the correct register */
2015                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2016
2017                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2018 #endif
2019                                 }
2020                         }
2021
2022                         sreg1_high = val;
2023                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2024                         assign_reg (cfg, rs, reg2, val, bank);
2025                 }
2026
2027                 /* Handle dreg==sreg1 */
2028                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2029                         MonoInst *sreg2_copy = NULL;
2030                         MonoInst *copy;
2031                         int bank = reg_bank (spec_src1);
2032
2033                         if (ins->dreg == sregs [1]) {
2034                                 /*
2035                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2036                                  * register for it.
2037                                  */
2038                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2039
2040                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2041                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2042                                 prev_sregs [1] = sregs [1] = reg2;
2043
2044                                 if (G_UNLIKELY (bank))
2045                                         mono_regstate_free_general (rs, reg2, bank);
2046                                 else
2047                                         mono_regstate_free_int (rs, reg2);
2048                         }
2049
2050                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2051                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2052                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2053                                         /* FIXME: */
2054                                         g_assert_not_reached ();
2055
2056                                 /*
2057                                  * sreg1 and dest are already allocated to the same regpair by the
2058                                  * SREG1 allocation code.
2059                                  */
2060                                 g_assert (sregs [0] == ins->dreg);
2061                                 g_assert (dreg_high == sreg1_high);
2062                         }
2063
2064                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2065                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2066                         insert_before_ins (bb, ins, copy);
2067
2068                         if (sreg2_copy)
2069                                 insert_before_ins (bb, copy, sreg2_copy);
2070
2071                         /*
2072                          * Need to prevent sreg2 to be allocated to sreg1, since that
2073                          * would screw up the previous copy.
2074                          */
2075                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2076                         /* we set sreg1 to dest as well */
2077                         prev_sregs [0] = sregs [0] = ins->dreg;
2078                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2079                 }
2080                 mono_inst_set_src_registers (ins, sregs);
2081
2082                 /*
2083                  * TRACK SREG2, 3, ...
2084                  */
2085                 for (j = 1; j < num_sregs; ++j) {
2086                         int k;
2087
2088                         bank = sreg_bank (j, spec);
2089                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2090                                 g_assert_not_reached ();
2091
2092                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2093                                 /*
2094                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2095                                  * allocating it to the fixed reg.
2096                                  */
2097                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2098                                 insert_before_ins (bb, ins, copy);
2099                                 sregs [j] = dest_sregs [j];
2100                         } else if (is_soft_reg (sregs [j], bank)) {
2101                                 val = rs->vassign [sregs [j]];
2102
2103                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2104                                         /*
2105                                          * The sreg is already allocated to a hreg, but not to the fixed
2106                                          * reg required by the instruction. Spill the sreg, so it can be
2107                                          * allocated to the fixed reg by the code below.
2108                                          */
2109                                         /* Currently, this code should only be hit for CAS */
2110                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2111                                         val = rs->vassign [sregs [j]];
2112                                 }
2113
2114                                 if (val < 0) {
2115                                         int spill = 0;
2116                                         if (val < -1) {
2117                                                 /* the register gets spilled after this inst */
2118                                                 spill = -val -1;
2119                                         }
2120                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2121                                         assign_reg (cfg, rs, sregs [j], val, bank);
2122                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2123                                         if (spill) {
2124                                                 /*
2125                                                  * Need to insert before the instruction since it can
2126                                                  * overwrite sreg2.
2127                                                  */
2128                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2129                                         }
2130                                 }
2131                                 sregs [j] = val;
2132                                 for (k = j + 1; k < num_sregs; ++k)
2133                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2134                         }
2135                         else {
2136                                 prev_sregs [j] = -1;
2137                         }
2138                 }
2139                 mono_inst_set_src_registers (ins, sregs);
2140
2141                 /* Sanity check */
2142                 /* Do this only for CAS for now */
2143                 for (j = 1; j < num_sregs; ++j) {
2144                         int sreg = sregs [j];
2145                         int dest_sreg = dest_sregs [j];
2146
2147                         if (j == 2 && dest_sreg != -1) {
2148                                 int k;
2149
2150                                 g_assert (sreg == dest_sreg);
2151
2152                                 for (k = 0; k < num_sregs; ++k) {
2153                                         if (k != j)
2154                                                 g_assert (sregs [k] != dest_sreg);
2155                                 }
2156                         }
2157                 }
2158
2159                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2160                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2161                         mono_regstate_free_int (rs, ins->sreg1);
2162                 }
2163                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2164                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2165                         mono_regstate_free_int (rs, ins->sreg2);
2166                 }*/
2167
2168                 DEBUG (mono_print_ins_index (i, ins));
2169         }
2170
2171         // FIXME: Set MAX_FREGS to 8
2172         // FIXME: Optimize generated code
2173 #if MONO_ARCH_USE_FPSTACK
2174         /*
2175          * Make a forward pass over the code, simulating the fp stack, making sure the
2176          * arguments required by the fp opcodes are at the top of the stack.
2177          */
2178         if (has_fp) {
2179                 MonoInst *prev = NULL;
2180                 MonoInst *fxch;
2181                 int tmp;
2182
2183                 g_assert (num_sregs <= 2);
2184
2185                 for (ins = bb->code; ins; ins = ins->next) {
2186                         spec = ins_get_spec (ins->opcode);
2187
2188                         DEBUG (printf ("processing:"));
2189                         DEBUG (mono_print_ins_index (0, ins));
2190
2191                         if (ins->opcode == OP_FMOVE) {
2192                                 /* Do it by renaming the source to the destination on the stack */
2193                                 // FIXME: Is this correct ?
2194                                 for (i = 0; i < sp; ++i)
2195                                         if (fpstack [i] == ins->sreg1)
2196                                                 fpstack [i] = ins->dreg;
2197                                 prev = ins;
2198                                 continue;
2199                         }
2200
2201                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2202                                 /* Arg1 must be in %st(1) */
2203                                 g_assert (prev);
2204
2205                                 i = 0;
2206                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2207                                         i ++;
2208                                 g_assert (i < sp);
2209
2210                                 if (sp - 1 - i > 0) {
2211                                         /* First move it to %st(0) */
2212                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2213
2214                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2215                                         fxch->inst_imm = sp - 1 - i;
2216
2217                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2218                                         prev = fxch;
2219
2220                                         tmp = fpstack [sp - 1];
2221                                         fpstack [sp - 1] = fpstack [i];
2222                                         fpstack [i] = tmp;
2223                                 }
2224
2225                                 /* Then move it to %st(1) */
2226                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2227
2228                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2229                                 fxch->inst_imm = 1;
2230
2231                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2232                                 prev = fxch;
2233
2234                                 tmp = fpstack [sp - 1];
2235                                 fpstack [sp - 1] = fpstack [sp - 2];
2236                                 fpstack [sp - 2] = tmp;
2237                         }
2238
2239                         if (sreg2_is_fp (spec)) {
2240                                 g_assert (sp > 0);
2241
2242                                 if (fpstack [sp - 1] != ins->sreg2) {
2243                                         g_assert (prev);
2244
2245                                         i = 0;
2246                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2247                                                 i ++;
2248                                         g_assert (i < sp);
2249
2250                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2251
2252                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2253                                         fxch->inst_imm = sp - 1 - i;
2254
2255                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2256                                         prev = fxch;
2257
2258                                         tmp = fpstack [sp - 1];
2259                                         fpstack [sp - 1] = fpstack [i];
2260                                         fpstack [i] = tmp;
2261                                 }
2262
2263                                 sp --;
2264                         }
2265
2266                         if (sreg1_is_fp (spec)) {
2267                                 g_assert (sp > 0);
2268
2269                                 if (fpstack [sp - 1] != ins->sreg1) {
2270                                         g_assert (prev);
2271
2272                                         i = 0;
2273                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2274                                                 i ++;
2275                                         g_assert (i < sp);
2276
2277                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2278
2279                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2280                                         fxch->inst_imm = sp - 1 - i;
2281
2282                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2283                                         prev = fxch;
2284
2285                                         tmp = fpstack [sp - 1];
2286                                         fpstack [sp - 1] = fpstack [i];
2287                                         fpstack [i] = tmp;
2288                                 }
2289
2290                                 sp --;
2291                         }
2292
2293                         if (dreg_is_fp (spec)) {
2294                                 g_assert (sp < 8);
2295                                 fpstack [sp ++] = ins->dreg;
2296                         }
2297
2298                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2299                                 printf ("\t[");
2300                                 for (i = 0; i < sp; ++i)
2301                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2302                                 printf ("]\n");
2303                         }
2304
2305                         prev = ins;
2306                 }
2307
2308                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2309                         /* Remove remaining items from the fp stack */
2310                         /*
2311                          * These can remain for example as a result of a dead fmove like in
2312                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2313                          */
2314                         while (sp) {
2315                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2316                                 mono_add_ins_to_end (bb, ins);
2317                                 sp --;
2318                         }
2319                 }
2320         }
2321 #endif
2322 }
2323
2324 CompRelation
2325 mono_opcode_to_cond (int opcode)
2326 {
2327         switch (opcode) {
2328         case OP_CEQ:
2329         case OP_IBEQ:
2330         case OP_ICEQ:
2331         case OP_LBEQ:
2332         case OP_LCEQ:
2333         case OP_FBEQ:
2334         case OP_FCEQ:
2335         case OP_COND_EXC_EQ:
2336         case OP_COND_EXC_IEQ:
2337         case OP_CMOV_IEQ:
2338         case OP_CMOV_LEQ:
2339                 return CMP_EQ;
2340         case OP_FCNEQ:
2341         case OP_ICNEQ:
2342         case OP_IBNE_UN:
2343         case OP_LBNE_UN:
2344         case OP_FBNE_UN:
2345         case OP_COND_EXC_NE_UN:
2346         case OP_COND_EXC_INE_UN:
2347         case OP_CMOV_INE_UN:
2348         case OP_CMOV_LNE_UN:
2349                 return CMP_NE;
2350         case OP_FCLE:
2351         case OP_ICLE:
2352         case OP_IBLE:
2353         case OP_LBLE:
2354         case OP_FBLE:
2355         case OP_CMOV_ILE:
2356         case OP_CMOV_LLE:
2357                 return CMP_LE;
2358         case OP_FCGE:
2359         case OP_ICGE:
2360         case OP_IBGE:
2361         case OP_LBGE:
2362         case OP_FBGE:
2363         case OP_CMOV_IGE:
2364         case OP_CMOV_LGE:
2365                 return CMP_GE;
2366         case OP_CLT:
2367         case OP_IBLT:
2368         case OP_ICLT:
2369         case OP_LBLT:
2370         case OP_LCLT:
2371         case OP_FBLT:
2372         case OP_FCLT:
2373         case OP_COND_EXC_LT:
2374         case OP_COND_EXC_ILT:
2375         case OP_CMOV_ILT:
2376         case OP_CMOV_LLT:
2377                 return CMP_LT;
2378         case OP_CGT:
2379         case OP_IBGT:
2380         case OP_ICGT:
2381         case OP_LBGT:
2382         case OP_LCGT:
2383         case OP_FBGT:
2384         case OP_FCGT:
2385         case OP_COND_EXC_GT:
2386         case OP_COND_EXC_IGT:
2387         case OP_CMOV_IGT:
2388         case OP_CMOV_LGT:
2389                 return CMP_GT;
2390
2391         case OP_ICLE_UN:
2392         case OP_IBLE_UN:
2393         case OP_LBLE_UN:
2394         case OP_FBLE_UN:
2395         case OP_COND_EXC_LE_UN:
2396         case OP_COND_EXC_ILE_UN:
2397         case OP_CMOV_ILE_UN:
2398         case OP_CMOV_LLE_UN:
2399                 return CMP_LE_UN;
2400
2401         case OP_ICGE_UN:
2402         case OP_IBGE_UN:
2403         case OP_LBGE_UN:
2404         case OP_FBGE_UN:
2405         case OP_CMOV_IGE_UN:
2406         case OP_CMOV_LGE_UN:
2407                 return CMP_GE_UN;
2408         case OP_CLT_UN:
2409         case OP_IBLT_UN:
2410         case OP_ICLT_UN:
2411         case OP_LBLT_UN:
2412         case OP_LCLT_UN:
2413         case OP_FBLT_UN:
2414         case OP_FCLT_UN:
2415         case OP_COND_EXC_LT_UN:
2416         case OP_COND_EXC_ILT_UN:
2417         case OP_CMOV_ILT_UN:
2418         case OP_CMOV_LLT_UN:
2419                 return CMP_LT_UN;
2420         case OP_CGT_UN:
2421         case OP_IBGT_UN:
2422         case OP_ICGT_UN:
2423         case OP_LBGT_UN:
2424         case OP_LCGT_UN:
2425         case OP_FCGT_UN:
2426         case OP_FBGT_UN:
2427         case OP_COND_EXC_GT_UN:
2428         case OP_COND_EXC_IGT_UN:
2429         case OP_CMOV_IGT_UN:
2430         case OP_CMOV_LGT_UN:
2431                 return CMP_GT_UN;
2432         default:
2433                 printf ("%s\n", mono_inst_name (opcode));
2434                 g_assert_not_reached ();
2435                 return 0;
2436         }
2437 }
2438
2439 CompRelation
2440 mono_negate_cond (CompRelation cond)
2441 {
2442         switch (cond) {
2443         case CMP_EQ:
2444                 return CMP_NE;
2445         case CMP_NE:
2446                 return CMP_EQ;
2447         case CMP_LE:
2448                 return CMP_GT;
2449         case CMP_GE:
2450                 return CMP_LT;
2451         case CMP_LT:
2452                 return CMP_GE;
2453         case CMP_GT:
2454                 return CMP_LE;
2455         case CMP_LE_UN:
2456                 return CMP_GT_UN;
2457         case CMP_GE_UN:
2458                 return CMP_LT_UN;
2459         case CMP_LT_UN:
2460                 return CMP_GE_UN;
2461         case CMP_GT_UN:
2462                 return CMP_LE_UN;
2463         default:
2464                 g_assert_not_reached ();
2465         }
2466 }
2467
2468 CompType
2469 mono_opcode_to_type (int opcode, int cmp_opcode)
2470 {
2471         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2472                 return CMP_TYPE_L;
2473         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2474                 return CMP_TYPE_I;
2475         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2476                 return CMP_TYPE_I;
2477         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2478                 return CMP_TYPE_L;
2479         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2480                 return CMP_TYPE_L;
2481         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2482                 return CMP_TYPE_F;
2483         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2484                 return CMP_TYPE_F;
2485         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2486                 return CMP_TYPE_I;
2487         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2488                 switch (cmp_opcode) {
2489                 case OP_ICOMPARE:
2490                 case OP_ICOMPARE_IMM:
2491                         return CMP_TYPE_I;
2492                 default:
2493                         return CMP_TYPE_L;
2494                 }
2495         } else {
2496                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2497                 return 0;
2498         }
2499 }
2500
2501 #endif /* DISABLE_JIT */
2502
2503 gboolean
2504 mono_is_regsize_var (MonoType *t)
2505 {
2506         if (t->byref)
2507                 return TRUE;
2508         t = mono_type_get_underlying_type (t);
2509         switch (t->type) {
2510         case MONO_TYPE_BOOLEAN:
2511         case MONO_TYPE_CHAR:
2512         case MONO_TYPE_I1:
2513         case MONO_TYPE_U1:
2514         case MONO_TYPE_I2:
2515         case MONO_TYPE_U2:
2516         case MONO_TYPE_I4:
2517         case MONO_TYPE_U4:
2518         case MONO_TYPE_I:
2519         case MONO_TYPE_U:
2520         case MONO_TYPE_PTR:
2521         case MONO_TYPE_FNPTR:
2522 #if SIZEOF_REGISTER == 8
2523         case MONO_TYPE_I8:
2524         case MONO_TYPE_U8:
2525 #endif
2526                 return TRUE;
2527         case MONO_TYPE_OBJECT:
2528         case MONO_TYPE_STRING:
2529         case MONO_TYPE_CLASS:
2530         case MONO_TYPE_SZARRAY:
2531         case MONO_TYPE_ARRAY:
2532                 return TRUE;
2533         case MONO_TYPE_GENERICINST:
2534                 if (!mono_type_generic_inst_is_valuetype (t))
2535                         return TRUE;
2536                 return FALSE;
2537         case MONO_TYPE_VALUETYPE:
2538                 return FALSE;
2539         default:
2540                 return FALSE;
2541         }
2542 }
2543
2544 #ifndef DISABLE_JIT
2545
2546 /*
2547  * mono_peephole_ins:
2548  *
2549  *   Perform some architecture independent peephole optimizations.
2550  */
2551 void
2552 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2553 {
2554         MonoInst *last_ins = ins->prev;
2555
2556         switch (ins->opcode) {
2557         case OP_MUL_IMM:
2558                 /* remove unnecessary multiplication with 1 */
2559                 if (ins->inst_imm == 1) {
2560                         if (ins->dreg != ins->sreg1)
2561                                 ins->opcode = OP_MOVE;
2562                         else
2563                                 MONO_DELETE_INS (bb, ins);
2564                 }
2565                 break;
2566         case OP_LOAD_MEMBASE:
2567         case OP_LOADI4_MEMBASE:
2568                 /*
2569                  * Note: if reg1 = reg2 the load op is removed
2570                  *
2571                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2572                  * OP_LOAD_MEMBASE offset(basereg), reg2
2573                  * -->
2574                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2575                  * OP_MOVE reg1, reg2
2576                  */
2577                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2578                         last_ins = last_ins->prev;
2579                 if (last_ins &&
2580                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2581                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2582                         ins->inst_basereg == last_ins->inst_destbasereg &&
2583                         ins->inst_offset == last_ins->inst_offset) {
2584                         if (ins->dreg == last_ins->sreg1) {
2585                                 MONO_DELETE_INS (bb, ins);
2586                                 break;
2587                         } else {
2588                                 ins->opcode = OP_MOVE;
2589                                 ins->sreg1 = last_ins->sreg1;
2590                         }
2591
2592                         /*
2593                          * Note: reg1 must be different from the basereg in the second load
2594                          * Note: if reg1 = reg2 is equal then second load is removed
2595                          *
2596                          * OP_LOAD_MEMBASE offset(basereg), reg1
2597                          * OP_LOAD_MEMBASE offset(basereg), reg2
2598                          * -->
2599                          * OP_LOAD_MEMBASE offset(basereg), reg1
2600                          * OP_MOVE reg1, reg2
2601                          */
2602                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2603                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2604                           ins->inst_basereg != last_ins->dreg &&
2605                           ins->inst_basereg == last_ins->inst_basereg &&
2606                           ins->inst_offset == last_ins->inst_offset) {
2607
2608                         if (ins->dreg == last_ins->dreg) {
2609                                 MONO_DELETE_INS (bb, ins);
2610                         } else {
2611                                 ins->opcode = OP_MOVE;
2612                                 ins->sreg1 = last_ins->dreg;
2613                         }
2614
2615                         //g_assert_not_reached ();
2616
2617 #if 0
2618                         /*
2619                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2620                          * OP_LOAD_MEMBASE offset(basereg), reg
2621                          * -->
2622                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2623                          * OP_ICONST reg, imm
2624                          */
2625                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2626                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2627                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2628                                    ins->inst_offset == last_ins->inst_offset) {
2629                         ins->opcode = OP_ICONST;
2630                         ins->inst_c0 = last_ins->inst_imm;
2631                         g_assert_not_reached (); // check this rule
2632 #endif
2633                 }
2634                 break;
2635         case OP_LOADI1_MEMBASE:
2636         case OP_LOADU1_MEMBASE:
2637                 /*
2638                  * Note: if reg1 = reg2 the load op is removed
2639                  *
2640                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2641                  * OP_LOAD_MEMBASE offset(basereg), reg2
2642                  * -->
2643                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2644                  * OP_MOVE reg1, reg2
2645                  */
2646                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2647                         ins->inst_basereg == last_ins->inst_destbasereg &&
2648                         ins->inst_offset == last_ins->inst_offset) {
2649                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2650                         ins->sreg1 = last_ins->sreg1;
2651                 }
2652                 break;
2653         case OP_LOADI2_MEMBASE:
2654         case OP_LOADU2_MEMBASE:
2655                 /*
2656                  * Note: if reg1 = reg2 the load op is removed
2657                  *
2658                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2659                  * OP_LOAD_MEMBASE offset(basereg), reg2
2660                  * -->
2661                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2662                  * OP_MOVE reg1, reg2
2663                  */
2664                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2665                         ins->inst_basereg == last_ins->inst_destbasereg &&
2666                         ins->inst_offset == last_ins->inst_offset) {
2667 #if SIZEOF_REGISTER == 8
2668                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2669 #else
2670                         /* The definition of OP_PCONV_TO_U2 is wrong */
2671                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2672 #endif
2673                         ins->sreg1 = last_ins->sreg1;
2674                 }
2675                 break;
2676         case OP_MOVE:
2677         case OP_FMOVE:
2678                 /*
2679                  * Removes:
2680                  *
2681                  * OP_MOVE reg, reg
2682                  */
2683                 if (ins->dreg == ins->sreg1) {
2684                         MONO_DELETE_INS (bb, ins);
2685                         break;
2686                 }
2687                 /*
2688                  * Removes:
2689                  *
2690                  * OP_MOVE sreg, dreg
2691                  * OP_MOVE dreg, sreg
2692                  */
2693                 if (last_ins && last_ins->opcode == ins->opcode &&
2694                         ins->sreg1 == last_ins->dreg &&
2695                         ins->dreg == last_ins->sreg1) {
2696                         MONO_DELETE_INS (bb, ins);
2697                 }
2698                 break;
2699         case OP_NOP:
2700                 MONO_DELETE_INS (bb, ins);
2701                 break;
2702         }
2703 }
2704
2705 int
2706 mini_exception_id_by_name (const char *name)
2707 {
2708         if (strcmp (name, "IndexOutOfRangeException") == 0)
2709                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2710         if (strcmp (name, "OverflowException") == 0)
2711                 return MONO_EXC_OVERFLOW;
2712         if (strcmp (name, "ArithmeticException") == 0)
2713                 return MONO_EXC_ARITHMETIC;
2714         if (strcmp (name, "DivideByZeroException") == 0)
2715                 return MONO_EXC_DIVIDE_BY_ZERO;
2716         if (strcmp (name, "InvalidCastException") == 0)
2717                 return MONO_EXC_INVALID_CAST;
2718         if (strcmp (name, "NullReferenceException") == 0)
2719                 return MONO_EXC_NULL_REF;
2720         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2721                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2722         if (strcmp (name, "ArgumentException") == 0)
2723                 return MONO_EXC_ARGUMENT;
2724         g_error ("Unknown intrinsic exception %s\n", name);
2725         return -1;
2726 }
2727
2728 #endif /* DISABLE_JIT */