mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30
  31
  32 #define MONO_ARCH_BANK_MIRRORED -2
  33
  34 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  35
  36 #ifndef MONO_ARCH_NEED_SIMD_BANK
  37 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  38 #endif
  39
  40 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  41
  42 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  43
  44
  45 #else
  46
  47
  48 #define get_mirrored_bank(bank) (-1)
  49
  50 #define is_hreg_mirrored(rs, bank, hreg) (0)
  51
  52 #endif
  53
  54
  55 /* If the bank is mirrored return the true logical bank that the register in the
  56  * physical register bank is allocated to.
  57  */
  58 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  59         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  60 }
  61
  62 /*
  63  * Every hardware register belongs to a register type or register bank. bank 0
  64  * contains the int registers, bank 1 contains the fp registers.
  65  * int registers are used 99% of the time, so they are special cased in a lot of
  66  * places.
  67  */
  68
  69 static const int regbank_size [] = {
  70         MONO_MAX_IREGS,
  71         MONO_MAX_FREGS,
  72         MONO_MAX_XREGS
  73 };
  74
  75 static const int regbank_load_ops [] = {
  76         OP_LOADR_MEMBASE,
  77         OP_LOADR8_MEMBASE,
  78         OP_LOADX_MEMBASE
  79 };
  80
  81 static const int regbank_store_ops [] = {
  82         OP_STORER_MEMBASE_REG,
  83         OP_STORER8_MEMBASE_REG,
  84         OP_STOREX_MEMBASE
  85 };
  86
  87 static const int regbank_move_ops [] = {
  88         OP_MOVE,
  89         OP_FMOVE,
  90         OP_XMOVE
  91 };
  92
  93 #define regmask(reg) (((regmask_t)1) << (reg))
  94
  95 static const regmask_t regbank_callee_saved_regs [] = {
  96         MONO_ARCH_CALLEE_SAVED_REGS,
  97         MONO_ARCH_CALLEE_SAVED_FREGS,
  98         MONO_ARCH_CALLEE_SAVED_XREGS,
  99 };
 100
 101 static const regmask_t regbank_callee_regs [] = {
 102         MONO_ARCH_CALLEE_REGS,
 103         MONO_ARCH_CALLEE_FREGS,
 104         MONO_ARCH_CALLEE_XREGS,
 105 };
 106
 107 static const int regbank_spill_var_size[] = {
 108         sizeof (mgreg_t),
 109         sizeof (double),
 110         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 111 };
 112
 113 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 114
 115 static inline GSList*
 116 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
 117 {
 118         GSList *new_list;
 119         GSList *last;
 120
 121         new_list = mono_mempool_alloc (mp, sizeof (GSList));
 122         new_list->data = data;
 123         new_list->next = NULL;
 124
 125         if (list) {
 126                 last = list;
 127                 while (last->next)
 128                         last = last->next;
 129                 last->next = new_list;
 130
 131                 return list;
 132         } else
 133                 return new_list;
 134 }
 135
 136 static inline void
 137 mono_regstate_assign (MonoRegState *rs)
 138 {
 139 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 140         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 141          * if the values here are not the same.
 142          */
 143         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 144         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 145         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 146 #endif
 147
 148         if (rs->next_vreg > rs->vassign_size) {
 149                 g_free (rs->vassign);
 150                 rs->vassign_size = MAX (rs->next_vreg, 256);
 151                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 152         }
 153
 154         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 155         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 156
 157         rs->symbolic [0] = rs->isymbolic;
 158         rs->symbolic [1] = rs->fsymbolic;
 159
 160 #ifdef MONO_ARCH_NEED_SIMD_BANK
 161         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 162         rs->symbolic [2] = rs->xsymbolic;
 163 #endif
 164 }
 165
 166 static inline int
 167 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 168 {
 169         regmask_t mask = allow & rs->ifree_mask;
 170
 171 #if defined(__x86_64__) && defined(__GNUC__)
 172  {
 173         guint64 i;
 174
 175         if (mask == 0)
 176                 return -1;
 177
 178         __asm__("bsfq %1,%0\n\t"
 179                         : "=r" (i) : "rm" (mask));
 180
 181         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 182         return i;
 183  }
 184 #else
 185         int i;
 186
 187         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 188                 if (mask & ((regmask_t)1 << i)) {
 189                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 190                         return i;
 191                 }
 192         }
 193         return -1;
 194 #endif
 195 }
 196
 197 static inline void
 198 mono_regstate_free_int (MonoRegState *rs, int reg)
 199 {
 200         if (reg >= 0) {
 201                 rs->ifree_mask |= (regmask_t)1 << reg;
 202                 rs->isymbolic [reg] = 0;
 203         }
 204 }
 205
 206 static inline int
 207 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 208 {
 209         int i;
 210         int mirrored_bank;
 211         regmask_t mask = allow & rs->free_mask [bank];
 212         for (i = 0; i < regbank_size [bank]; ++i) {
 213                 if (mask & ((regmask_t)1 << i)) {
 214                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 215
 216                         mirrored_bank = get_mirrored_bank (bank);
 217                         if (mirrored_bank == -1)
 218                                 return i;
 219
 220                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 221                         return i;
 222                 }
 223         }
 224         return -1;
 225 }
 226
 227 static inline void
 228 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 229 {
 230         int mirrored_bank;
 231
 232         if (reg >= 0) {
 233                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 234                 rs->symbolic [bank][reg] = 0;
 235
 236                 mirrored_bank = get_mirrored_bank (bank);
 237                 if (mirrored_bank == -1)
 238                         return;
 239                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 240                 rs->symbolic [mirrored_bank][reg] = 0;
 241         }
 242 }
 243
 244 const char*
 245 mono_regname_full (int reg, int bank)
 246 {
 247         if (G_UNLIKELY (bank)) {
 248 #if MONO_ARCH_NEED_SIMD_BANK
 249                 if (bank == 2)
 250                         return mono_arch_xregname (reg);
 251 #endif
 252                 g_assert (bank == 1);
 253                 return mono_arch_fregname (reg);
 254         } else {
 255                 return mono_arch_regname (reg);
 256         }
 257 }
 258
 259 void
 260 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 261 {
 262         guint32 regpair;
 263
 264         regpair = (((guint32)hreg) << 24) + vreg;
 265         if (G_UNLIKELY (bank)) {
 266                 g_assert (vreg >= regbank_size [bank]);
 267                 g_assert (hreg < regbank_size [bank]);
 268                 call->used_fregs |= 1 << hreg;
 269                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 270         } else {
 271                 g_assert (vreg >= MONO_MAX_IREGS);
 272                 g_assert (hreg < MONO_MAX_IREGS);
 273                 call->used_iregs |= 1 << hreg;
 274                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 275         }
 276 }
 277
 278 static void
 279 resize_spill_info (MonoCompile *cfg, int bank)
 280 {
 281         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 282         int orig_len = cfg->spill_info_len [bank];
 283         int new_len = orig_len ? orig_len * 2 : 16;
 284         MonoSpillInfo *new_info;
 285         int i;
 286
 287         g_assert (bank < MONO_NUM_REGBANKS);
 288
 289         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 290         if (orig_info)
 291                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 292         for (i = orig_len; i < new_len; ++i)
 293                 new_info [i].offset = -1;
 294
 295         cfg->spill_info [bank] = new_info;
 296         cfg->spill_info_len [bank] = new_len;
 297 }
 298
 299 /*
 300  * returns the offset used by spillvar. It allocates a new
 301  * spill variable if necessary.
 302  */
 303 static inline int
 304 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 305 {
 306         MonoSpillInfo *info;
 307         int size;
 308
 309         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 310                 while (spillvar >= cfg->spill_info_len [bank])
 311                         resize_spill_info (cfg, bank);
 312         }
 313
 314         /*
 315          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 316          */
 317         info = &cfg->spill_info [bank][spillvar];
 318         if (info->offset == -1) {
 319                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 320                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 321
 322                 g_assert (bank < MONO_NUM_REGBANKS);
 323                 if (G_UNLIKELY (bank))
 324                         size = regbank_spill_var_size [bank];
 325                 else
 326                         size = sizeof (mgreg_t);
 327
 328                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 329                         cfg->stack_offset += size - 1;
 330                         cfg->stack_offset &= ~(size - 1);
 331                         info->offset = cfg->stack_offset;
 332                         cfg->stack_offset += size;
 333                 } else {
 334                         cfg->stack_offset += size - 1;
 335                         cfg->stack_offset &= ~(size - 1);
 336                         cfg->stack_offset += size;
 337                         info->offset = - cfg->stack_offset;
 338                 }
 339         }
 340
 341         return info->offset;
 342 }
 343
 344 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 345 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 346 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 347 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 348 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 349 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 350
 351 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 352 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 353 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 354 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 355 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 356
 357 #ifndef MONO_ARCH_INST_IS_FLOAT
 358 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 359 #endif
 360
 361 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 362 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 363 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 364 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 365 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 366
 367 #define reg_is_simd(desc) ((desc) == 'x')
 368
 369 #ifdef MONO_ARCH_NEED_SIMD_BANK
 370
 371 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 372
 373 #else
 374
 375 #define reg_bank(desc) reg_is_fp ((desc))
 376
 377 #endif
 378
 379 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 380 #define sreg1_bank(spec) sreg_bank (0, (spec))
 381 #define sreg2_bank(spec) sreg_bank (1, (spec))
 382 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 383
 384 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 385 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 386 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 387 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 388
 389 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 390
 391 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 392 #undef is_global_ireg
 393 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 394 #endif
 395
 396 typedef struct {
 397         int born_in;
 398         int killed_in;
 399         /* Not (yet) used */
 400         //int last_use;
 401         //int prev_use;
 402         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 403 } RegTrack;
 404
 405 #ifndef DISABLE_LOGGING
 406 void
 407 mono_print_ins_index (int i, MonoInst *ins)
 408 {
 409         const char *spec = ins_get_spec (ins->opcode);
 410         int num_sregs, j;
 411         int sregs [MONO_MAX_SRC_REGS];
 412
 413         if (i != -1)
 414                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 415         else
 416                 printf (" %s", mono_inst_name (ins->opcode));
 417         if (spec == MONO_ARCH_CPU_SPEC) {
 418                 /* This is a lowered opcode */
 419                 if (ins->dreg != -1)
 420                         printf (" R%d <-", ins->dreg);
 421                 if (ins->sreg1 != -1)
 422                         printf (" R%d", ins->sreg1);
 423                 if (ins->sreg2 != -1)
 424                         printf (" R%d", ins->sreg2);
 425                 if (ins->sreg3 != -1)
 426                         printf (" R%d", ins->sreg3);
 427
 428                 switch (ins->opcode) {
 429                 case OP_LBNE_UN:
 430                 case OP_LBEQ:
 431                 case OP_LBLT:
 432                 case OP_LBLT_UN:
 433                 case OP_LBGT:
 434                 case OP_LBGT_UN:
 435                 case OP_LBGE:
 436                 case OP_LBGE_UN:
 437                 case OP_LBLE:
 438                 case OP_LBLE_UN:
 439                         if (!ins->inst_false_bb)
 440                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 441                         else
 442                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 443                         break;
 444                 case OP_PHI:
 445                 case OP_VPHI:
 446                 case OP_XPHI:
 447                 case OP_FPHI: {
 448                         int i;
 449                         printf (" [%d (", (int)ins->inst_c0);
 450                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 451                                 if (i)
 452                                         printf (", ");
 453                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 454                         }
 455                         printf (")]");
 456                         break;
 457                 }
 458                 case OP_LDADDR:
 459                 case OP_OUTARG_VTRETADDR:
 460                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 461                         break;
 462                 case OP_REGOFFSET:
 463                         printf (" + 0x%lx", (long)ins->inst_offset);
 464                         break;
 465                 default:
 466                         break;
 467                 }
 468
 469                 printf ("\n");
 470                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 471                 return;
 472         }
 473
 474         if (spec [MONO_INST_DEST]) {
 475                 int bank = dreg_bank (spec);
 476                 if (is_soft_reg (ins->dreg, bank)) {
 477                         if (spec [MONO_INST_DEST] == 'b') {
 478                                 if (ins->inst_offset == 0)
 479                                         printf (" [R%d] <-", ins->dreg);
 480                                 else
 481                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 482                         }
 483                         else
 484                                 printf (" R%d <-", ins->dreg);
 485                 } else if (spec [MONO_INST_DEST] == 'b') {
 486                         if (ins->inst_offset == 0)
 487                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 488                         else
 489                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 490                 } else
 491                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 492         }
 493         if (spec [MONO_INST_SRC1]) {
 494                 int bank = sreg1_bank (spec);
 495                 if (is_soft_reg (ins->sreg1, bank)) {
 496                         if (spec [MONO_INST_SRC1] == 'b')
 497                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 498                         else
 499                                 printf (" R%d", ins->sreg1);
 500                 } else if (spec [MONO_INST_SRC1] == 'b')
 501                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 502                 else
 503                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 504         }
 505         num_sregs = mono_inst_get_src_registers (ins, sregs);
 506         for (j = 1; j < num_sregs; ++j) {
 507                 int bank = sreg_bank (j, spec);
 508                 if (is_soft_reg (sregs [j], bank))
 509                         printf (" R%d", sregs [j]);
 510                 else
 511                         printf (" %s", mono_regname_full (sregs [j], bank));
 512         }
 513
 514         switch (ins->opcode) {
 515         case OP_ICONST:
 516                 printf (" [%d]", (int)ins->inst_c0);
 517                 break;
 518 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 519         case OP_X86_PUSH_IMM:
 520 #endif
 521         case OP_ICOMPARE_IMM:
 522         case OP_COMPARE_IMM:
 523         case OP_IADD_IMM:
 524         case OP_ISUB_IMM:
 525         case OP_IAND_IMM:
 526         case OP_IOR_IMM:
 527         case OP_IXOR_IMM:
 528                 printf (" [%d]", (int)ins->inst_imm);
 529                 break;
 530         case OP_ADD_IMM:
 531         case OP_LADD_IMM:
 532                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 533                 break;
 534         case OP_I8CONST:
 535                 printf (" [%lld]", (long long)ins->inst_l);
 536                 break;
 537         case OP_R8CONST:
 538                 printf (" [%f]", *(double*)ins->inst_p0);
 539                 break;
 540         case OP_R4CONST:
 541                 printf (" [%f]", *(float*)ins->inst_p0);
 542                 break;
 543         case CEE_CALL:
 544         case CEE_CALLVIRT:
 545         case OP_CALL:
 546         case OP_CALL_MEMBASE:
 547         case OP_CALL_REG:
 548         case OP_FCALL:
 549         case OP_FCALLVIRT:
 550         case OP_LCALL:
 551         case OP_LCALLVIRT:
 552         case OP_VCALL:
 553         case OP_VCALLVIRT:
 554         case OP_VCALL_REG:
 555         case OP_VCALL_MEMBASE:
 556         case OP_VCALL2:
 557         case OP_VCALL2_REG:
 558         case OP_VCALL2_MEMBASE:
 559         case OP_VOIDCALL:
 560         case OP_VOIDCALL_MEMBASE:
 561         case OP_VOIDCALLVIRT: {
 562                 MonoCallInst *call = (MonoCallInst*)ins;
 563                 GSList *list;
 564
 565                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 566                         /*
 567                          * These are lowered opcodes, but they are in the .md files since the old
 568                          * JIT passes them to backends.
 569                          */
 570                         if (ins->dreg != -1)
 571                                 printf (" R%d <-", ins->dreg);
 572                 }
 573
 574                 if (call->method) {
 575                         char *full_name = mono_method_full_name (call->method, TRUE);
 576                         printf (" [%s]", full_name);
 577                         g_free (full_name);
 578                 } else if (call->fptr) {
 579                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 580                         if (info)
 581                                 printf (" [%s]", info->name);
 582                 }
 583
 584                 list = call->out_ireg_args;
 585                 while (list) {
 586                         guint32 regpair;
 587                         int reg, hreg;
 588
 589                         regpair = (guint32)(gssize)(list->data);
 590                         hreg = regpair >> 24;
 591                         reg = regpair & 0xffffff;
 592
 593                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 594
 595                         list = g_slist_next (list);
 596                 }
 597                 break;
 598         }
 599         case OP_BR:
 600         case OP_CALL_HANDLER:
 601                 printf (" [B%d]", ins->inst_target_bb->block_num);
 602                 break;
 603         case CEE_BNE_UN:
 604         case CEE_BEQ:
 605         case CEE_BLT:
 606         case CEE_BLT_UN:
 607         case CEE_BGT:
 608         case CEE_BGT_UN:
 609         case CEE_BGE:
 610         case CEE_BGE_UN:
 611         case CEE_BLE:
 612         case CEE_BLE_UN:
 613         case OP_IBNE_UN:
 614         case OP_IBEQ:
 615         case OP_IBLT:
 616         case OP_IBLT_UN:
 617         case OP_IBGT:
 618         case OP_IBGT_UN:
 619         case OP_IBGE:
 620         case OP_IBGE_UN:
 621         case OP_IBLE:
 622         case OP_IBLE_UN:
 623         case OP_LBNE_UN:
 624         case OP_LBEQ:
 625         case OP_LBLT:
 626         case OP_LBLT_UN:
 627         case OP_LBGT:
 628         case OP_LBGT_UN:
 629         case OP_LBGE:
 630         case OP_LBGE_UN:
 631         case OP_LBLE:
 632         case OP_LBLE_UN:
 633                 if (!ins->inst_false_bb)
 634                         printf (" [B%d]", ins->inst_true_bb->block_num);
 635                 else
 636                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 637                 break;
 638         case OP_LIVERANGE_START:
 639         case OP_LIVERANGE_END:
 640                 printf (" R%d", (int)ins->inst_c1);
 641                 break;
 642         default:
 643                 break;
 644         }
 645
 646         if (spec [MONO_INST_CLOB])
 647                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 648         printf ("\n");
 649 }
 650
 651 static void
 652 print_regtrack (RegTrack *t, int num)
 653 {
 654         int i;
 655         char buf [32];
 656         const char *r;
 657
 658         for (i = 0; i < num; ++i) {
 659                 if (!t [i].born_in)
 660                         continue;
 661                 if (i >= MONO_MAX_IREGS) {
 662                         g_snprintf (buf, sizeof(buf), "R%d", i);
 663                         r = buf;
 664                 } else
 665                         r = mono_arch_regname (i);
 666                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 667         }
 668 }
 669 #else
 670 void
 671 mono_print_ins_index (int i, MonoInst *ins)
 672 {
 673 }
 674 #endif /* DISABLE_LOGGING */
 675
 676 void
 677 mono_print_ins (MonoInst *ins)
 678 {
 679         mono_print_ins_index (-1, ins);
 680 }
 681
 682 static inline void
 683 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 684 {
 685         /*
 686          * If this function is called multiple times, the new instructions are inserted
 687          * in the proper order.
 688          */
 689         mono_bblock_insert_before_ins (bb, ins, to_insert);
 690 }
 691
 692 static inline void
 693 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 694 {
 695         /*
 696          * If this function is called multiple times, the new instructions are inserted in
 697          * proper order.
 698          */
 699         mono_bblock_insert_after_ins (bb, *last, to_insert);
 700
 701         *last = to_insert;
 702 }
 703
 704 /*
 705  * Force the spilling of the variable in the symbolic register 'reg'.
 706  */
 707 static int
 708 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 709 {
 710         MonoInst *load;
 711         int i, sel, spill;
 712         int *symbolic;
 713         MonoRegState *rs = cfg->rs;
 714
 715         symbolic = rs->symbolic [bank];
 716         sel = rs->vassign [reg];
 717
 718         /* the vreg we need to spill lives in another logical reg bank */
 719         bank = translate_bank (cfg->rs, bank, sel);
 720
 721         /*i = rs->isymbolic [sel];
 722         g_assert (i == reg);*/
 723         i = reg;
 724         spill = ++cfg->spill_count;
 725         rs->vassign [i] = -spill - 1;
 726         if (G_UNLIKELY (bank))
 727                 mono_regstate_free_general (rs, sel, bank);
 728         else
 729                 mono_regstate_free_int (rs, sel);
 730         /* we need to create a spill var and insert a load to sel after the current instruction */
 731         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 732         load->dreg = sel;
 733         load->inst_basereg = cfg->frame_reg;
 734         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 735         insert_after_ins (bb, ins, last, load);
 736         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 737         if (G_UNLIKELY (bank))
 738                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 739         else
 740                 i = mono_regstate_alloc_int (rs, regmask (sel));
 741         g_assert (i == sel);
 742
 743         return sel;
 744 }
 745
 746 /* This isn't defined on older glib versions and on some platforms */
 747 #ifndef G_GUINT64_FORMAT
 748 #define G_GUINT64_FORMAT "ul"
 749 #endif
 750
 751 static int
 752 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 753 {
 754         MonoInst *load;
 755         int i, sel, spill, num_sregs;
 756         int sregs [MONO_MAX_SRC_REGS];
 757         int *symbolic;
 758         MonoRegState *rs = cfg->rs;
 759
 760         symbolic = rs->symbolic [bank];
 761
 762         g_assert (bank < MONO_NUM_REGBANKS);
 763
 764         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 765         /* exclude the registers in the current instruction */
 766         num_sregs = mono_inst_get_src_registers (ins, sregs);
 767         for (i = 0; i < num_sregs; ++i) {
 768                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 769                         if (is_soft_reg (sregs [i], bank))
 770                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 771                         else
 772                                 regmask &= ~ (regmask (sregs [i]));
 773                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 774                 }
 775         }
 776         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 777                 regmask &= ~ (regmask (ins->dreg));
 778                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 779         }
 780
 781         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 782         g_assert (regmask); /* need at least a register we can free */
 783         sel = 0;
 784         /* we should track prev_use and spill the register that's farther */
 785         if (G_UNLIKELY (bank)) {
 786                 for (i = 0; i < regbank_size [bank]; ++i) {
 787                         if (regmask & (regmask (i))) {
 788                                 sel = i;
 789
 790                                 /* the vreg we need to load lives in another logical bank */
 791                                 bank = translate_bank (cfg->rs, bank, sel);
 792
 793                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 794                                 break;
 795                         }
 796                 }
 797
 798                 i = rs->symbolic [bank] [sel];
 799                 spill = ++cfg->spill_count;
 800                 rs->vassign [i] = -spill - 1;
 801                 mono_regstate_free_general (rs, sel, bank);
 802         }
 803         else {
 804                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 805                         if (regmask & (regmask (i))) {
 806                                 sel = i;
 807                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 808                                 break;
 809                         }
 810                 }
 811
 812                 i = rs->isymbolic [sel];
 813                 spill = ++cfg->spill_count;
 814                 rs->vassign [i] = -spill - 1;
 815                 mono_regstate_free_int (rs, sel);
 816         }
 817
 818         /* we need to create a spill var and insert a load to sel after the current instruction */
 819         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 820         load->dreg = sel;
 821         load->inst_basereg = cfg->frame_reg;
 822         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 823         insert_after_ins (bb, ins, last, load);
 824         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 825         if (G_UNLIKELY (bank))
 826                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 827         else
 828                 i = mono_regstate_alloc_int (rs, regmask (sel));
 829         g_assert (i == sel);
 830
 831         return sel;
 832 }
 833
 834 static void
 835 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 836 {
 837         if (G_UNLIKELY (bank)) {
 838                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 839                         bank = translate_bank (cfg->rs, bank, hreg);
 840                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 841                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 842                         mono_regstate_free_general (cfg->rs, hreg, bank);
 843                 }
 844         }
 845         else {
 846                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 847                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 848                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 849                         mono_regstate_free_int (cfg->rs, hreg);
 850                 }
 851         }
 852 }
 853
 854 static MonoInst*
 855 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 856 {
 857         MonoInst *copy;
 858
 859         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 860
 861         copy->dreg = dest;
 862         copy->sreg1 = src;
 863         copy->cil_code = ip;
 864         if (ins) {
 865                 mono_bblock_insert_after_ins (bb, ins, copy);
 866                 *last = copy;
 867         }
 868         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 869         return copy;
 870 }
 871
 872 static MonoInst*
 873 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 874 {
 875         MonoInst *store;
 876         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 877         store->sreg1 = reg;
 878         store->inst_destbasereg = cfg->frame_reg;
 879         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 880         if (ins) {
 881                 mono_bblock_insert_after_ins (bb, ins, store);
 882                 *last = store;
 883         }
 884         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 885         return store;
 886 }
 887
 888 /* flags used in reginfo->flags */
 889 enum {
 890         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 891         MONO_FP_NEEDS_SPILL                     = regmask (1),
 892         MONO_FP_NEEDS_LOAD                      = regmask (2)
 893 };
 894
 895 static inline int
 896 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 897 {
 898         int val;
 899
 900         if (info && info->preferred_mask) {
 901                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 902                 if (val >= 0) {
 903                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 904                         return val;
 905                 }
 906         }
 907
 908         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 909         if (val < 0)
 910                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 911
 912         return val;
 913 }
 914
 915 static inline int
 916 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 917 {
 918         int val;
 919
 920         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 921
 922         if (val < 0)
 923                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 924
 925         return val;
 926 }
 927
 928 static inline int
 929 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 930 {
 931         if (G_UNLIKELY (bank))
 932                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 933         else
 934                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 935 }
 936
 937 static inline void
 938 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 939 {
 940         if (G_UNLIKELY (bank)) {
 941                 int mirrored_bank;
 942
 943                 g_assert (reg >= regbank_size [bank]);
 944                 g_assert (hreg < regbank_size [bank]);
 945                 g_assert (! is_global_freg (hreg));
 946
 947                 rs->vassign [reg] = hreg;
 948                 rs->symbolic [bank] [hreg] = reg;
 949                 rs->free_mask [bank] &= ~ (regmask (hreg));
 950
 951                 mirrored_bank = get_mirrored_bank (bank);
 952                 if (mirrored_bank == -1)
 953                         return;
 954
 955                 /* Make sure the other logical reg bank that this bank shares
 956                  * a single hard reg bank knows that this hard reg is not free.
 957                  */
 958                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 959
 960                 /* Mark the other logical bank that the this bank shares
 961                  * a single hard reg bank with as mirrored.
 962                  */
 963                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
 964
 965         }
 966         else {
 967                 g_assert (reg >= MONO_MAX_IREGS);
 968                 g_assert (hreg < MONO_MAX_IREGS);
 969 #ifndef TARGET_ARM
 970                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 971                 g_assert (! is_global_ireg (hreg));
 972 #endif
 973
 974                 rs->vassign [reg] = hreg;
 975                 rs->isymbolic [hreg] = reg;
 976                 rs->ifree_mask &= ~ (regmask (hreg));
 977         }
 978 }
 979
 980 static inline regmask_t
 981 get_callee_mask (const char spec)
 982 {
 983         if (G_UNLIKELY (reg_bank (spec)))
 984                 return regbank_callee_regs [reg_bank (spec)];
 985         return MONO_ARCH_CALLEE_REGS;
 986 }
 987
 988 static gint8 desc_to_fixed_reg [256];
 989 static gboolean desc_to_fixed_reg_inited = FALSE;
 990
 991 /*
 992  * Local register allocation.
 993  * We first scan the list of instructions and we save the liveness info of
 994  * each register (when the register is first used, when it's value is set etc.).
 995  * We also reverse the list of instructions because assigning registers backwards allows
 996  * for more tricks to be used.
 997  */
 998 void
 999 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1000 {
1001         MonoInst *ins, *prev, *last;
1002         MonoInst **tmp;
1003         MonoRegState *rs = cfg->rs;
1004         int i, j, val, max;
1005         RegTrack *reginfo;
1006         const char *spec;
1007         unsigned char spec_src1, spec_dest;
1008         int bank = 0;
1009 #if MONO_ARCH_USE_FPSTACK
1010         gboolean has_fp = FALSE;
1011         int fpstack [8];
1012         int sp = 0;
1013 #endif
1014         int num_sregs;
1015         int sregs [MONO_MAX_SRC_REGS];
1016
1017         if (!bb->code)
1018                 return;
1019
1020         if (!desc_to_fixed_reg_inited) {
1021                 for (i = 0; i < 256; ++i)
1022                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1023                 desc_to_fixed_reg_inited = TRUE;
1024
1025                 /* Validate the cpu description against the info in mini-ops.h */
1026 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1027                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1028                         const char *ispec;
1029
1030                         spec = ins_get_spec (i);
1031                         ispec = INS_INFO (i);
1032
1033                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1034                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1035                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1036                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1037                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1038                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1039                 }
1040 #endif
1041         }
1042
1043         rs->next_vreg = bb->max_vreg;
1044         mono_regstate_assign (rs);
1045
1046         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1047         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1048                 rs->free_mask [i] = regbank_callee_regs [i];
1049
1050         max = rs->next_vreg;
1051
1052         if (cfg->reginfo && cfg->reginfo_len < max)
1053                 cfg->reginfo = NULL;
1054
1055         reginfo = cfg->reginfo;
1056         if (!reginfo) {
1057                 cfg->reginfo_len = MAX (1024, max * 2);
1058                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1059         }
1060         else
1061                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1062
1063         if (cfg->verbose_level > 1) {
1064                 /* print_regtrack reads the info of all variables */
1065                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1066         }
1067
1068         /*
1069          * For large methods, next_vreg can be very large, so g_malloc0 time can
1070          * be prohibitive. So we manually init the reginfo entries used by the
1071          * bblock.
1072          */
1073         for (ins = bb->code; ins; ins = ins->next) {
1074                 spec = ins_get_spec (ins->opcode);
1075
1076                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1077                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1078 #if SIZEOF_REGISTER == 4
1079                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1080                                 /**
1081                                  * In the new IR, the two vregs of the regpair do not alias the
1082                                  * original long vreg. shift the vreg here so the rest of the
1083                                  * allocator doesn't have to care about it.
1084                                  */
1085                                 ins->dreg ++;
1086                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1087                         }
1088 #endif
1089                 }
1090
1091                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1092                 for (j = 0; j < num_sregs; ++j) {
1093                         g_assert (sregs [j] != -1);
1094                         if (sregs [j] < max) {
1095                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1096 #if SIZEOF_REGISTER == 4
1097                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1098                                         sregs [j]++;
1099                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1100                                 }
1101 #endif
1102                         }
1103                 }
1104                 mono_inst_set_src_registers (ins, sregs);
1105         }
1106
1107         /*if (cfg->opt & MONO_OPT_COPYPROP)
1108                 local_copy_prop (cfg, ins);*/
1109
1110         i = 1;
1111         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1112         /* forward pass on the instructions to collect register liveness info */
1113         MONO_BB_FOR_EACH_INS (bb, ins) {
1114                 spec = ins_get_spec (ins->opcode);
1115                 spec_dest = spec [MONO_INST_DEST];
1116
1117                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1118                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1119                 }
1120
1121                 DEBUG (mono_print_ins_index (i, ins));
1122
1123                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1124
1125 #if MONO_ARCH_USE_FPSTACK
1126                 if (dreg_is_fp (spec)) {
1127                         has_fp = TRUE;
1128                 } else {
1129                         for (j = 0; j < num_sregs; ++j) {
1130                                 if (sreg_is_fp (j, spec))
1131                                         has_fp = TRUE;
1132                         }
1133                 }
1134 #endif
1135
1136                 for (j = 0; j < num_sregs; ++j) {
1137                         int sreg = sregs [j];
1138                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1139                         if (sreg_spec) {
1140                                 bank = sreg_bank (j, spec);
1141                                 g_assert (sreg != -1);
1142                                 if (is_soft_reg (sreg, bank))
1143                                         /* This means the vreg is not local to this bb */
1144                                         g_assert (reginfo [sreg].born_in > 0);
1145                                 rs->vassign [sreg] = -1;
1146                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1147                                 //reginfo [ins->sreg2].last_use = i;
1148                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1149                                         /* The virtual register is allocated sequentially */
1150                                         rs->vassign [sreg + 1] = -1;
1151                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1152                                         //reginfo [ins->sreg2 + 1].last_use = i;
1153                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1154                                                 reginfo [sreg + 1].born_in = i;
1155                                 }
1156                         } else {
1157                                 sregs [j] = -1;
1158                         }
1159                 }
1160                 mono_inst_set_src_registers (ins, sregs);
1161
1162                 if (spec_dest) {
1163                         int dest_dreg;
1164
1165                         bank = dreg_bank (spec);
1166                         if (spec_dest != 'b') /* it's not just a base register */
1167                                 reginfo [ins->dreg].killed_in = i;
1168                         g_assert (ins->dreg != -1);
1169                         rs->vassign [ins->dreg] = -1;
1170                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1171                         //reginfo [ins->dreg].last_use = i;
1172                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1173                                 reginfo [ins->dreg].born_in = i;
1174
1175                         dest_dreg = desc_to_fixed_reg [spec_dest];
1176                         if (dest_dreg != -1)
1177                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1178
1179 #ifdef MONO_ARCH_INST_FIXED_MASK
1180                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1181 #endif
1182
1183                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1184                                 /* The virtual register is allocated sequentially */
1185                                 rs->vassign [ins->dreg + 1] = -1;
1186                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1187                                 //reginfo [ins->dreg + 1].last_use = i;
1188                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1189                                         reginfo [ins->dreg + 1].born_in = i;
1190                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1191                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1192                         }
1193                 } else {
1194                         ins->dreg = -1;
1195                 }
1196
1197                 if (spec [MONO_INST_CLOB] == 'c') {
1198                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1199
1200                         MonoCallInst *call = (MonoCallInst*)ins;
1201                         GSList *list;
1202
1203                         list = call->out_ireg_args;
1204                         if (list) {
1205                                 while (list) {
1206                                         guint32 regpair;
1207                                         int reg, hreg;
1208
1209                                         regpair = (guint32)(gssize)(list->data);
1210                                         hreg = regpair >> 24;
1211                                         reg = regpair & 0xffffff;
1212
1213                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1214                                         //reginfo [reg].last_use = i;
1215
1216                                         list = g_slist_next (list);
1217                                 }
1218                         }
1219
1220                         list = call->out_freg_args;
1221                         if (list) {
1222                                 while (list) {
1223                                         guint32 regpair;
1224                                         int reg, hreg;
1225
1226                                         regpair = (guint32)(gssize)(list->data);
1227                                         hreg = regpair >> 24;
1228                                         reg = regpair & 0xffffff;
1229
1230                                         list = g_slist_next (list);
1231                                 }
1232                         }
1233                 }
1234
1235                 ++i;
1236         }
1237
1238         tmp = &last;
1239
1240         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1241         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1242                 int prev_dreg, clob_dreg;
1243                 int dest_dreg, clob_reg;
1244                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1245                 int dreg_high, sreg1_high;
1246                 regmask_t dreg_mask, mask;
1247                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1248                 regmask_t dreg_fixed_mask;
1249                 const unsigned char *ip;
1250                 --i;
1251                 spec = ins_get_spec (ins->opcode);
1252                 spec_src1 = spec [MONO_INST_SRC1];
1253                 spec_dest = spec [MONO_INST_DEST];
1254                 prev_dreg = -1;
1255                 clob_dreg = -1;
1256                 clob_reg = -1;
1257                 dest_dreg = -1;
1258                 dreg_high = -1;
1259                 sreg1_high = -1;
1260                 dreg_mask = get_callee_mask (spec_dest);
1261                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1262                         prev_sregs [j] = -1;
1263                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1264                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1265 #ifdef MONO_ARCH_INST_FIXED_MASK
1266                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1267 #else
1268                         sreg_fixed_masks [j] = 0;
1269 #endif
1270                 }
1271
1272                 DEBUG (printf ("processing:"));
1273                 DEBUG (mono_print_ins_index (i, ins));
1274
1275                 ip = ins->cil_code;
1276
1277                 last = ins;
1278
1279                 /*
1280                  * FIXED REGS
1281                  */
1282                 dest_dreg = desc_to_fixed_reg [spec_dest];
1283                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1284                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1285
1286 #ifdef MONO_ARCH_INST_FIXED_MASK
1287                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1288 #else
1289                 dreg_fixed_mask = 0;
1290 #endif
1291
1292                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1293
1294                 /*
1295                  * TRACK FIXED SREG2, 3, ...
1296                  */
1297                 for (j = 1; j < num_sregs; ++j) {
1298                         int sreg = sregs [j];
1299                         int dest_sreg = dest_sregs [j];
1300                         if (dest_sreg != -1) {
1301                                 if (rs->ifree_mask & (regmask (dest_sreg))) {
1302                                         if (is_global_ireg (sreg)) {
1303                                                 int k;
1304                                                 /* Argument already in hard reg, need to copy */
1305                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1306                                                 insert_before_ins (bb, ins, copy);
1307                                                 for (k = 0; k < num_sregs; ++k) {
1308                                                         if (k != j)
1309                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1310                                                 }
1311                                         }
1312                                         else {
1313                                                 val = rs->vassign [sreg];
1314                                                 if (val == -1) {
1315                                                         DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1316                                                         assign_reg (cfg, rs, sreg, dest_sreg, 0);
1317                                                 } else if (val < -1) {
1318                                                         /* FIXME: */
1319                                                         g_assert_not_reached ();
1320                                                 } else {
1321                                                         /* Argument already in hard reg, need to copy */
1322                                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1323                                                         int k;
1324
1325                                                         insert_before_ins (bb, ins, copy);
1326                                                         for (k = 0; k < num_sregs; ++k) {
1327                                                                 if (k != j)
1328                                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1329                                                         }
1330                                                         /*
1331                                                          * Prevent the dreg from being allocate to dest_sreg
1332                                                          * too, since it could force sreg1 to be allocated to
1333                                                          * the same reg on x86.
1334                                                          */
1335                                                         dreg_mask &= ~ (regmask (dest_sreg));
1336                                                 }
1337                                         }
1338                                 } else {
1339                                         gboolean need_spill = TRUE;
1340                                         gboolean need_assign = TRUE;
1341                                         int k;
1342
1343                                         dreg_mask &= ~ (regmask (dest_sreg));
1344                                         for (k = 0; k < num_sregs; ++k) {
1345                                                 if (k != j)
1346                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1347                                         }
1348
1349                                         /*
1350                                          * First check if dreg is assigned to dest_sreg2, since we
1351                                          * can't spill a dreg.
1352                                          */
1353                                         val = rs->vassign [ins->dreg];
1354                                         if (val == dest_sreg && ins->dreg != sreg) {
1355                                                 /*
1356                                                  * the destination register is already assigned to
1357                                                  * dest_sreg2: we need to allocate another register for it
1358                                                  * and then copy from this to dest_sreg2.
1359                                                  */
1360                                                 int new_dest;
1361                                                 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1362                                                 g_assert (new_dest >= 0);
1363                                                 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1364
1365                                                 prev_dreg = ins->dreg;
1366                                                 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1367                                                 clob_dreg = ins->dreg;
1368                                                 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1369                                                 mono_regstate_free_int (rs, dest_sreg);
1370                                                 need_spill = FALSE;
1371                                         }
1372
1373                                         if (is_global_ireg (sreg)) {
1374                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1375                                                 insert_before_ins (bb, ins, copy);
1376                                                 need_assign = FALSE;
1377                                         }
1378                                         else {
1379                                                 val = rs->vassign [sreg];
1380                                                 if (val == dest_sreg) {
1381                                                         /* sreg2 is already assigned to the correct register */
1382                                                         need_spill = FALSE;
1383                                                 } else if (val < -1) {
1384                                                         /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1385                                                 } else if (val >= 0) {
1386                                                         /* sreg2 already assigned to another register */
1387                                                         /*
1388                                                          * We couldn't emit a copy from val to dest_sreg2, because
1389                                                          * val might be spilled later while processing this
1390                                                          * instruction. So we spill sreg2 so it can be allocated to
1391                                                          * dest_sreg2.
1392                                                          */
1393                                                         DEBUG (printf ("\tforced spill of R%d\n", sreg));
1394                                                         free_up_reg (cfg, bb, tmp, ins, val, 0);
1395                                                 }
1396                                         }
1397
1398                                         if (need_spill) {
1399                                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg]));
1400                                                 free_up_reg (cfg, bb, tmp, ins, dest_sreg, 0);
1401                                         }
1402
1403                                         if (need_assign) {
1404                                                 if (rs->vassign [sreg] < -1) {
1405                                                         MonoInst *store;
1406                                                         int spill;
1407
1408                                                         /* Need to emit a spill store */
1409                                                         spill = - rs->vassign [sreg] - 1;
1410                                                         store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
1411                                                         insert_before_ins (bb, ins, store);
1412                                                 }
1413                                                 /* force-set sreg2 */
1414                                                 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1415                                         }
1416                                 }
1417                                 sregs [j] = dest_sreg;
1418                         }
1419                 }
1420                 mono_inst_set_src_registers (ins, sregs);
1421
1422                 /*
1423                  * TRACK DREG
1424                  */
1425                 bank = dreg_bank (spec);
1426                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1427                         prev_dreg = ins->dreg;
1428                 }
1429
1430                 if (spec_dest == 'b') {
1431                         /*
1432                          * The dest reg is read by the instruction, not written, so
1433                          * avoid allocating sreg1/sreg2 to the same reg.
1434                          */
1435                         if (dest_sregs [0] != -1)
1436                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1437                         for (j = 1; j < num_sregs; ++j) {
1438                                 if (dest_sregs [j] != -1)
1439                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1440                         }
1441
1442                         val = rs->vassign [ins->dreg];
1443                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1444                                 /* DREG is already allocated to a register needed for sreg1 */
1445                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1446                                 mono_regstate_free_int (rs, val);
1447                         }
1448                 }
1449
1450                 /*
1451                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1452                  * various complex situations.
1453                  */
1454                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1455                         guint32 dreg2, dest_dreg2;
1456
1457                         g_assert (is_soft_reg (ins->dreg, bank));
1458
1459                         if (dest_dreg != -1) {
1460                                 if (rs->vassign [ins->dreg] != dest_dreg)
1461                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1462
1463                                 dreg2 = ins->dreg + 1;
1464                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1465                                 if (dest_dreg2 != -1) {
1466                                         if (rs->vassign [dreg2] != dest_dreg2)
1467                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1468                                 }
1469                         }
1470                 }
1471
1472                 if (dreg_fixed_mask) {
1473                         g_assert (!bank);
1474                         if (is_global_ireg (ins->dreg)) {
1475                                 /*
1476                                  * The argument is already in a hard reg, but that reg is
1477                                  * not usable by this instruction, so allocate a new one.
1478                                  */
1479                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1480                                 if (val < 0)
1481                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1482                                 mono_regstate_free_int (rs, val);
1483                                 dest_dreg = val;
1484
1485                                 /* Fall through */
1486                         }
1487                         else
1488                                 dreg_mask &= dreg_fixed_mask;
1489                 }
1490
1491                 if (is_soft_reg (ins->dreg, bank)) {
1492                         val = rs->vassign [ins->dreg];
1493
1494                         if (val < 0) {
1495                                 int spill = 0;
1496                                 if (val < -1) {
1497                                         /* the register gets spilled after this inst */
1498                                         spill = -val -1;
1499                                 }
1500                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1501                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1502                                 if (spill)
1503                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1504                         }
1505
1506                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1507                         ins->dreg = val;
1508                 }
1509
1510                 /* Handle regpairs */
1511                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1512                         int reg2 = prev_dreg + 1;
1513
1514                         g_assert (!bank);
1515                         g_assert (prev_dreg > -1);
1516                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1517                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1518 #ifdef TARGET_X86
1519                         /* bug #80489 */
1520                         mask &= ~regmask (X86_ECX);
1521 #endif
1522                         val = rs->vassign [reg2];
1523                         if (val < 0) {
1524                                 int spill = 0;
1525                                 if (val < -1) {
1526                                         /* the register gets spilled after this inst */
1527                                         spill = -val -1;
1528                                 }
1529                                 val = mono_regstate_alloc_int (rs, mask);
1530                                 if (val < 0)
1531                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1532                                 if (spill)
1533                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1534                         }
1535                         else {
1536                                 if (! (mask & (regmask (val)))) {
1537                                         val = mono_regstate_alloc_int (rs, mask);
1538                                         if (val < 0)
1539                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1540
1541                                         /* Reallocate hreg to the correct register */
1542                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1543
1544                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1545                                 }
1546                         }
1547
1548                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1549                         assign_reg (cfg, rs, reg2, val, bank);
1550
1551                         dreg_high = val;
1552                         ins->backend.reg3 = val;
1553
1554                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1555                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1556                                 mono_regstate_free_int (rs, val);
1557                         }
1558                 }
1559
1560                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1561                         /*
1562                          * In theory, we could free up the hreg even if the vreg is alive,
1563                          * but branches inside bblocks force us to assign the same hreg
1564                          * to a vreg every time it is encountered.
1565                          */
1566                         int dreg = rs->vassign [prev_dreg];
1567                         g_assert (dreg >= 0);
1568                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1569                         if (G_UNLIKELY (bank))
1570                                 mono_regstate_free_general (rs, dreg, bank);
1571                         else
1572                                 mono_regstate_free_int (rs, dreg);
1573                         rs->vassign [prev_dreg] = -1;
1574                 }
1575
1576                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1577                         /* this instruction only outputs to dest_dreg, need to copy */
1578                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1579                         ins->dreg = dest_dreg;
1580
1581                         if (G_UNLIKELY (bank)) {
1582                                 /* the register we need to free up may be used in another logical regbank
1583                                  * so do a translate just in case.
1584                                  */
1585                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1586                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1587                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1588                         }
1589                         else {
1590                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1591                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1592                         }
1593                 }
1594
1595                 if (spec_dest == 'b') {
1596                         /*
1597                          * The dest reg is read by the instruction, not written, so
1598                          * avoid allocating sreg1/sreg2 to the same reg.
1599                          */
1600                         for (j = 0; j < num_sregs; ++j)
1601                                 if (!sreg_bank (j, spec))
1602                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1603                 }
1604
1605                 /*
1606                  * TRACK CLOBBERING
1607                  */
1608                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1609                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1610                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1611                         mono_regstate_free_int (rs, clob_reg);
1612                 }
1613
1614                 if (spec [MONO_INST_CLOB] == 'c') {
1615                         int j, s, dreg, dreg2, cur_bank;
1616                         guint64 clob_mask;
1617
1618                         clob_mask = MONO_ARCH_CALLEE_REGS;
1619
1620                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1621                                 /*
1622                                  * Need to avoid spilling the dreg since the dreg is not really
1623                                  * clobbered by the call.
1624                                  */
1625                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1626                                         dreg = rs->vassign [prev_dreg];
1627                                 else
1628                                         dreg = -1;
1629
1630                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1631                                         dreg2 = rs->vassign [prev_dreg + 1];
1632                                 else
1633                                         dreg2 = -1;
1634
1635                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1636                                         s = regmask (j);
1637                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1638                                                 if ((j != dreg) && (j != dreg2))
1639                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1640                                                 else if (rs->isymbolic [j])
1641                                                         /* The hreg is assigned to the dreg of this instruction */
1642                                                         rs->vassign [rs->isymbolic [j]] = -1;
1643                                                 mono_regstate_free_int (rs, j);
1644                                         }
1645                                 }
1646                         }
1647
1648                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1649                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1650                                         clob_mask = regbank_callee_regs [cur_bank];
1651                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1652                                                 dreg = rs->vassign [prev_dreg];
1653                                         else
1654                                                 dreg = -1;
1655
1656                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1657
1658                                                 /* we are looping though the banks in the outer loop
1659                                                  * so, we don't need to deal with mirrored hregs
1660                                                  * because we will get them in one of the other bank passes.
1661                                                  */
1662                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1663                                                         continue;
1664
1665                                                 s = regmask (j);
1666                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1667                                                         if (j != dreg)
1668                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1669                                                         else if (rs->symbolic [cur_bank] [j])
1670                                                                 /* The hreg is assigned to the dreg of this instruction */
1671                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1672                                                         mono_regstate_free_general (rs, j, cur_bank);
1673                                                 }
1674                                         }
1675                                 }
1676                         }
1677                 }
1678
1679                 /*
1680                  * TRACK ARGUMENT REGS
1681                  */
1682                 if (spec [MONO_INST_CLOB] == 'c') {
1683                         MonoCallInst *call = (MonoCallInst*)ins;
1684                         GSList *list;
1685
1686                         /*
1687                          * This needs to be done before assigning sreg1, so sreg1 will
1688                          * not be assigned one of the argument regs.
1689                          */
1690
1691                         /*
1692                          * Assign all registers in call->out_reg_args to the proper
1693                          * argument registers.
1694                          */
1695
1696                         list = call->out_ireg_args;
1697                         if (list) {
1698                                 while (list) {
1699                                         guint32 regpair;
1700                                         int reg, hreg;
1701
1702                                         regpair = (guint32)(gssize)(list->data);
1703                                         hreg = regpair >> 24;
1704                                         reg = regpair & 0xffffff;
1705
1706                                         assign_reg (cfg, rs, reg, hreg, 0);
1707
1708                                         sreg_masks [0] &= ~(regmask (hreg));
1709
1710                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1711
1712                                         list = g_slist_next (list);
1713                                 }
1714                         }
1715
1716                         list = call->out_freg_args;
1717                         if (list) {
1718                                 while (list) {
1719                                         guint32 regpair;
1720                                         int reg, hreg;
1721
1722                                         regpair = (guint32)(gssize)(list->data);
1723                                         hreg = regpair >> 24;
1724                                         reg = regpair & 0xffffff;
1725
1726                                         assign_reg (cfg, rs, reg, hreg, 1);
1727
1728                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1729
1730                                         list = g_slist_next (list);
1731                                 }
1732                         }
1733                 }
1734
1735                 /*
1736                  * TRACK SREG1
1737                  */
1738                 bank = sreg1_bank (spec);
1739                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1740                         int sreg1 = sregs [0];
1741                         int dest_sreg1 = dest_sregs [0];
1742
1743                         g_assert (is_soft_reg (sreg1, bank));
1744
1745                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1746                         if (dest_sreg1 != -1)
1747                                 g_assert (dest_sreg1 == ins->dreg);
1748                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1749                         g_assert (val >= 0);
1750
1751                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1752                                 // FIXME:
1753                                 g_assert_not_reached ();
1754
1755                         assign_reg (cfg, rs, sreg1, val, bank);
1756
1757                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1758
1759                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1760                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1761                         g_assert (val >= 0);
1762
1763                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1764                                 // FIXME:
1765                                 g_assert_not_reached ();
1766
1767                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1768
1769                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1770
1771                         /* Skip rest of this section */
1772                         dest_sregs [0] = -1;
1773                 }
1774
1775                 if (sreg_fixed_masks [0]) {
1776                         g_assert (!bank);
1777                         if (is_global_ireg (sregs [0])) {
1778                                 /*
1779                                  * The argument is already in a hard reg, but that reg is
1780                                  * not usable by this instruction, so allocate a new one.
1781                                  */
1782                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1783                                 if (val < 0)
1784                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1785                                 mono_regstate_free_int (rs, val);
1786                                 dest_sregs [0] = val;
1787
1788                                 /* Fall through to the dest_sreg1 != -1 case */
1789                         }
1790                         else
1791                                 sreg_masks [0] &= sreg_fixed_masks [0];
1792                 }
1793
1794                 if (dest_sregs [0] != -1) {
1795                         sreg_masks [0] = regmask (dest_sregs [0]);
1796
1797                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1798                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sregs [0]]));
1799                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sregs [0]], 0);
1800                                 mono_regstate_free_int (rs, dest_sregs [0]);
1801                         }
1802                         if (is_global_ireg (sregs [0])) {
1803                                 /* The argument is already in a hard reg, need to copy */
1804                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1805                                 insert_before_ins (bb, ins, copy);
1806                                 sregs [0] = dest_sregs [0];
1807                         }
1808                 }
1809
1810                 if (is_soft_reg (sregs [0], bank)) {
1811                         val = rs->vassign [sregs [0]];
1812                         prev_sregs [0] = sregs [0];
1813                         if (val < 0) {
1814                                 int spill = 0;
1815                                 if (val < -1) {
1816                                         /* the register gets spilled after this inst */
1817                                         spill = -val -1;
1818                                 }
1819
1820                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1821                                         /*
1822                                          * Allocate the same hreg to sreg1 as well so the
1823                                          * peephole can get rid of the move.
1824                                          */
1825                                         sreg_masks [0] = regmask (ins->dreg);
1826                                 }
1827
1828                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1829                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1830                                         sreg_masks [0] = regmask (ins->dreg);
1831
1832                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1833                                 assign_reg (cfg, rs, sregs [0], val, bank);
1834                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1835
1836                                 if (spill) {
1837                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
1838                                         /*
1839                                          * Need to insert before the instruction since it can
1840                                          * overwrite sreg1.
1841                                          */
1842                                         insert_before_ins (bb, ins, store);
1843                                 }
1844                         }
1845                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1846                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1847                                 insert_before_ins (bb, ins, copy);
1848                                 for (j = 1; j < num_sregs; ++j)
1849                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1850                                 val = dest_sregs [0];
1851                         }
1852
1853                         sregs [0] = val;
1854                 }
1855                 else {
1856                         prev_sregs [0] = -1;
1857                 }
1858                 mono_inst_set_src_registers (ins, sregs);
1859
1860                 for (j = 1; j < num_sregs; ++j)
1861                         sreg_masks [j] &= ~(regmask (sregs [0]));
1862
1863                 /* Handle the case when sreg1 is a regpair but dreg is not */
1864                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1865                         int reg2 = prev_sregs [0] + 1;
1866
1867                         g_assert (!bank);
1868                         g_assert (prev_sregs [0] > -1);
1869                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1870                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1871                         val = rs->vassign [reg2];
1872                         if (val < 0) {
1873                                 int spill = 0;
1874                                 if (val < -1) {
1875                                         /* the register gets spilled after this inst */
1876                                         spill = -val -1;
1877                                 }
1878                                 val = mono_regstate_alloc_int (rs, mask);
1879                                 if (val < 0)
1880                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1881                                 if (spill)
1882                                         g_assert_not_reached ();
1883                         }
1884                         else {
1885                                 if (! (mask & (regmask (val)))) {
1886                                         /* The vreg is already allocated to a wrong hreg */
1887                                         /* FIXME: */
1888                                         g_assert_not_reached ();
1889 #if 0
1890                                         val = mono_regstate_alloc_int (rs, mask);
1891                                         if (val < 0)
1892                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1893
1894                                         /* Reallocate hreg to the correct register */
1895                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1896
1897                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1898 #endif
1899                                 }
1900                         }
1901
1902                         sreg1_high = val;
1903                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1904                         assign_reg (cfg, rs, reg2, val, bank);
1905                 }
1906
1907                 /* Handle dreg==sreg1 */
1908                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1909                         MonoInst *sreg2_copy = NULL;
1910                         MonoInst *copy;
1911                         int bank = reg_bank (spec_src1);
1912
1913                         if (ins->dreg == sregs [1]) {
1914                                 /*
1915                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1916                                  * register for it.
1917                                  */
1918                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1919
1920                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1921                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1922                                 prev_sregs [1] = sregs [1] = reg2;
1923
1924                                 if (G_UNLIKELY (bank))
1925                                         mono_regstate_free_general (rs, reg2, bank);
1926                                 else
1927                                         mono_regstate_free_int (rs, reg2);
1928                         }
1929
1930                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1931                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1932                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1933                                         /* FIXME: */
1934                                         g_assert_not_reached ();
1935
1936                                 /*
1937                                  * sreg1 and dest are already allocated to the same regpair by the
1938                                  * SREG1 allocation code.
1939                                  */
1940                                 g_assert (sregs [0] == ins->dreg);
1941                                 g_assert (dreg_high == sreg1_high);
1942                         }
1943
1944                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
1945                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
1946                         insert_before_ins (bb, ins, copy);
1947
1948                         if (sreg2_copy)
1949                                 insert_before_ins (bb, copy, sreg2_copy);
1950
1951                         /*
1952                          * Need to prevent sreg2 to be allocated to sreg1, since that
1953                          * would screw up the previous copy.
1954                          */
1955                         sreg_masks [1] &= ~ (regmask (sregs [0]));
1956                         /* we set sreg1 to dest as well */
1957                         prev_sregs [0] = sregs [0] = ins->dreg;
1958                         sreg_masks [1] &= ~ (regmask (ins->dreg));
1959                 }
1960                 mono_inst_set_src_registers (ins, sregs);
1961
1962                 /*
1963                  * TRACK SREG2, 3, ...
1964                  */
1965                 for (j = 1; j < num_sregs; ++j) {
1966                         int k;
1967
1968                         bank = sreg_bank (j, spec);
1969                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
1970                                 g_assert_not_reached ();
1971                         if (is_soft_reg (sregs [j], bank)) {
1972                                 val = rs->vassign [sregs [j]];
1973
1974                                 if (val < 0) {
1975                                         int spill = 0;
1976                                         if (val < -1) {
1977                                                 /* the register gets spilled after this inst */
1978                                                 spill = -val -1;
1979                                         }
1980                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
1981                                         assign_reg (cfg, rs, sregs [j], val, bank);
1982                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
1983                                         if (spill) {
1984                                                 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
1985                                                 /*
1986                                                  * Need to insert before the instruction since it can
1987                                                  * overwrite sreg2.
1988                                                  */
1989                                                 insert_before_ins (bb, ins, store);
1990                                         }
1991                                 }
1992                                 sregs [j] = val;
1993                                 for (k = j + 1; k < num_sregs; ++k)
1994                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
1995                         }
1996                         else {
1997                                 prev_sregs [j] = -1;
1998                         }
1999                 }
2000                 mono_inst_set_src_registers (ins, sregs);
2001
2002                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2003                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2004                         mono_regstate_free_int (rs, ins->sreg1);
2005                 }
2006                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2007                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2008                         mono_regstate_free_int (rs, ins->sreg2);
2009                 }*/
2010
2011                 DEBUG (mono_print_ins_index (i, ins));
2012         }
2013
2014         // FIXME: Set MAX_FREGS to 8
2015         // FIXME: Optimize generated code
2016 #if MONO_ARCH_USE_FPSTACK
2017         /*
2018          * Make a forward pass over the code, simulating the fp stack, making sure the
2019          * arguments required by the fp opcodes are at the top of the stack.
2020          */
2021         if (has_fp) {
2022                 MonoInst *prev = NULL;
2023                 MonoInst *fxch;
2024                 int tmp;
2025
2026                 g_assert (num_sregs <= 2);
2027
2028                 for (ins = bb->code; ins; ins = ins->next) {
2029                         spec = ins_get_spec (ins->opcode);
2030
2031                         DEBUG (printf ("processing:"));
2032                         DEBUG (mono_print_ins_index (0, ins));
2033
2034                         if (ins->opcode == OP_FMOVE) {
2035                                 /* Do it by renaming the source to the destination on the stack */
2036                                 // FIXME: Is this correct ?
2037                                 for (i = 0; i < sp; ++i)
2038                                         if (fpstack [i] == ins->sreg1)
2039                                                 fpstack [i] = ins->dreg;
2040                                 prev = ins;
2041                                 continue;
2042                         }
2043
2044                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2045                                 /* Arg1 must be in %st(1) */
2046                                 g_assert (prev);
2047
2048                                 i = 0;
2049                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2050                                         i ++;
2051                                 g_assert (i < sp);
2052
2053                                 if (sp - 1 - i > 0) {
2054                                         /* First move it to %st(0) */
2055                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2056
2057                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2058                                         fxch->inst_imm = sp - 1 - i;
2059
2060                                         prev->next = fxch;
2061                                         fxch->next = ins;
2062                                         prev = fxch;
2063
2064                                         tmp = fpstack [sp - 1];
2065                                         fpstack [sp - 1] = fpstack [i];
2066                                         fpstack [i] = tmp;
2067                                 }
2068
2069                                 /* Then move it to %st(1) */
2070                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2071
2072                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2073                                 fxch->inst_imm = 1;
2074
2075                                 prev->next = fxch;
2076                                 fxch->next = ins;
2077                                 prev = fxch;
2078
2079                                 tmp = fpstack [sp - 1];
2080                                 fpstack [sp - 1] = fpstack [sp - 2];
2081                                 fpstack [sp - 2] = tmp;
2082                         }
2083
2084                         if (sreg2_is_fp (spec)) {
2085                                 g_assert (sp > 0);
2086
2087                                 if (fpstack [sp - 1] != ins->sreg2) {
2088                                         g_assert (prev);
2089
2090                                         i = 0;
2091                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2092                                                 i ++;
2093                                         g_assert (i < sp);
2094
2095                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2096
2097                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2098                                         fxch->inst_imm = sp - 1 - i;
2099
2100                                         prev->next = fxch;
2101                                         fxch->next = ins;
2102                                         prev = fxch;
2103
2104                                         tmp = fpstack [sp - 1];
2105                                         fpstack [sp - 1] = fpstack [i];
2106                                         fpstack [i] = tmp;
2107                                 }
2108
2109                                 sp --;
2110                         }
2111
2112                         if (sreg1_is_fp (spec)) {
2113                                 g_assert (sp > 0);
2114
2115                                 if (fpstack [sp - 1] != ins->sreg1) {
2116                                         g_assert (prev);
2117
2118                                         i = 0;
2119                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2120                                                 i ++;
2121                                         g_assert (i < sp);
2122
2123                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2124
2125                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2126                                         fxch->inst_imm = sp - 1 - i;
2127
2128                                         prev->next = fxch;
2129                                         fxch->next = ins;
2130                                         prev = fxch;
2131
2132                                         tmp = fpstack [sp - 1];
2133                                         fpstack [sp - 1] = fpstack [i];
2134                                         fpstack [i] = tmp;
2135                                 }
2136
2137                                 sp --;
2138                         }
2139
2140                         if (dreg_is_fp (spec)) {
2141                                 g_assert (sp < 8);
2142                                 fpstack [sp ++] = ins->dreg;
2143                         }
2144
2145                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2146                                 printf ("\t[");
2147                                 for (i = 0; i < sp; ++i)
2148                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2149                                 printf ("]\n");
2150                         }
2151
2152                         prev = ins;
2153                 }
2154
2155                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2156                         /* Remove remaining items from the fp stack */
2157                         /*
2158                          * These can remain for example as a result of a dead fmove like in
2159                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2160                          */
2161                         while (sp) {
2162                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2163                                 mono_add_ins_to_end (bb, ins);
2164                                 sp --;
2165                         }
2166                 }
2167         }
2168 #endif
2169 }
2170
2171 CompRelation
2172 mono_opcode_to_cond (int opcode)
2173 {
2174         switch (opcode) {
2175         case CEE_BEQ:
2176         case OP_CEQ:
2177         case OP_IBEQ:
2178         case OP_ICEQ:
2179         case OP_LBEQ:
2180         case OP_LCEQ:
2181         case OP_FBEQ:
2182         case OP_FCEQ:
2183         case OP_COND_EXC_EQ:
2184         case OP_COND_EXC_IEQ:
2185         case OP_CMOV_IEQ:
2186         case OP_CMOV_LEQ:
2187                 return CMP_EQ;
2188         case CEE_BNE_UN:
2189         case OP_IBNE_UN:
2190         case OP_LBNE_UN:
2191         case OP_FBNE_UN:
2192         case OP_COND_EXC_NE_UN:
2193         case OP_COND_EXC_INE_UN:
2194         case OP_CMOV_INE_UN:
2195         case OP_CMOV_LNE_UN:
2196                 return CMP_NE;
2197         case CEE_BLE:
2198         case OP_IBLE:
2199         case OP_LBLE:
2200         case OP_FBLE:
2201         case OP_CMOV_ILE:
2202         case OP_CMOV_LLE:
2203                 return CMP_LE;
2204         case CEE_BGE:
2205         case OP_IBGE:
2206         case OP_LBGE:
2207         case OP_FBGE:
2208         case OP_CMOV_IGE:
2209         case OP_CMOV_LGE:
2210                 return CMP_GE;
2211         case CEE_BLT:
2212         case OP_CLT:
2213         case OP_IBLT:
2214         case OP_ICLT:
2215         case OP_LBLT:
2216         case OP_LCLT:
2217         case OP_FBLT:
2218         case OP_FCLT:
2219         case OP_COND_EXC_LT:
2220         case OP_COND_EXC_ILT:
2221         case OP_CMOV_ILT:
2222         case OP_CMOV_LLT:
2223                 return CMP_LT;
2224         case CEE_BGT:
2225         case OP_CGT:
2226         case OP_IBGT:
2227         case OP_ICGT:
2228         case OP_LBGT:
2229         case OP_LCGT:
2230         case OP_FBGT:
2231         case OP_FCGT:
2232         case OP_COND_EXC_GT:
2233         case OP_COND_EXC_IGT:
2234         case OP_CMOV_IGT:
2235         case OP_CMOV_LGT:
2236                 return CMP_GT;
2237
2238         case CEE_BLE_UN:
2239         case OP_IBLE_UN:
2240         case OP_LBLE_UN:
2241         case OP_FBLE_UN:
2242         case OP_COND_EXC_LE_UN:
2243         case OP_COND_EXC_ILE_UN:
2244         case OP_CMOV_ILE_UN:
2245         case OP_CMOV_LLE_UN:
2246                 return CMP_LE_UN;
2247         case CEE_BGE_UN:
2248         case OP_IBGE_UN:
2249         case OP_LBGE_UN:
2250         case OP_FBGE_UN:
2251         case OP_CMOV_IGE_UN:
2252         case OP_CMOV_LGE_UN:
2253                 return CMP_GE_UN;
2254         case CEE_BLT_UN:
2255         case OP_CLT_UN:
2256         case OP_IBLT_UN:
2257         case OP_ICLT_UN:
2258         case OP_LBLT_UN:
2259         case OP_LCLT_UN:
2260         case OP_FBLT_UN:
2261         case OP_FCLT_UN:
2262         case OP_COND_EXC_LT_UN:
2263         case OP_COND_EXC_ILT_UN:
2264         case OP_CMOV_ILT_UN:
2265         case OP_CMOV_LLT_UN:
2266                 return CMP_LT_UN;
2267         case CEE_BGT_UN:
2268         case OP_CGT_UN:
2269         case OP_IBGT_UN:
2270         case OP_ICGT_UN:
2271         case OP_LBGT_UN:
2272         case OP_LCGT_UN:
2273         case OP_FCGT_UN:
2274         case OP_FBGT_UN:
2275         case OP_COND_EXC_GT_UN:
2276         case OP_COND_EXC_IGT_UN:
2277         case OP_CMOV_IGT_UN:
2278         case OP_CMOV_LGT_UN:
2279                 return CMP_GT_UN;
2280         default:
2281                 printf ("%s\n", mono_inst_name (opcode));
2282                 g_assert_not_reached ();
2283                 return 0;
2284         }
2285 }
2286
2287 CompRelation
2288 mono_negate_cond (CompRelation cond)
2289 {
2290         switch (cond) {
2291         case CMP_EQ:
2292                 return CMP_NE;
2293         case CMP_NE:
2294                 return CMP_EQ;
2295         case CMP_LE:
2296                 return CMP_GT;
2297         case CMP_GE:
2298                 return CMP_LT;
2299         case CMP_LT:
2300                 return CMP_GE;
2301         case CMP_GT:
2302                 return CMP_LE;
2303         case CMP_LE_UN:
2304                 return CMP_GT_UN;
2305         case CMP_GE_UN:
2306                 return CMP_LT_UN;
2307         case CMP_LT_UN:
2308                 return CMP_GE_UN;
2309         case CMP_GT_UN:
2310                 return CMP_LE_UN;
2311         default:
2312                 g_assert_not_reached ();
2313         }
2314 }
2315
2316 CompType
2317 mono_opcode_to_type (int opcode, int cmp_opcode)
2318 {
2319         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2320                 return CMP_TYPE_L;
2321         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2322                 return CMP_TYPE_L;
2323         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2324                 return CMP_TYPE_I;
2325         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2326                 return CMP_TYPE_I;
2327         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2328                 return CMP_TYPE_L;
2329         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2330                 return CMP_TYPE_L;
2331         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2332                 return CMP_TYPE_F;
2333         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2334                 return CMP_TYPE_F;
2335         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2336                 return CMP_TYPE_I;
2337         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2338                 switch (cmp_opcode) {
2339                 case OP_ICOMPARE:
2340                 case OP_ICOMPARE_IMM:
2341                 case OP_LCOMPARE_IMM:
2342                         return CMP_TYPE_I;
2343                 default:
2344                         return CMP_TYPE_L;
2345                 }
2346         } else {
2347                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2348                 return 0;
2349         }
2350 }
2351
2352 gboolean
2353 mono_is_regsize_var (MonoType *t)
2354 {
2355         if (t->byref)
2356                 return TRUE;
2357         t = mono_type_get_underlying_type (t);
2358         switch (t->type) {
2359         case MONO_TYPE_BOOLEAN:
2360         case MONO_TYPE_CHAR:
2361         case MONO_TYPE_I1:
2362         case MONO_TYPE_U1:
2363         case MONO_TYPE_I2:
2364         case MONO_TYPE_U2:
2365         case MONO_TYPE_I4:
2366         case MONO_TYPE_U4:
2367         case MONO_TYPE_I:
2368         case MONO_TYPE_U:
2369         case MONO_TYPE_PTR:
2370         case MONO_TYPE_FNPTR:
2371 #if SIZEOF_REGISTER == 8
2372         case MONO_TYPE_I8:
2373         case MONO_TYPE_U8:
2374 #endif
2375                 return TRUE;
2376         case MONO_TYPE_OBJECT:
2377         case MONO_TYPE_STRING:
2378         case MONO_TYPE_CLASS:
2379         case MONO_TYPE_SZARRAY:
2380         case MONO_TYPE_ARRAY:
2381                 return TRUE;
2382         case MONO_TYPE_GENERICINST:
2383                 if (!mono_type_generic_inst_is_valuetype (t))
2384                         return TRUE;
2385                 return FALSE;
2386         case MONO_TYPE_VALUETYPE:
2387                 return FALSE;
2388         }
2389         return FALSE;
2390 }
2391
2392 /*
2393  * mono_peephole_ins:
2394  *
2395  *   Perform some architecture independent peephole optimizations.
2396  */
2397 void
2398 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2399 {
2400         MonoInst *last_ins = ins->prev;
2401
2402         switch (ins->opcode) {
2403         case OP_MUL_IMM:
2404                 /* remove unnecessary multiplication with 1 */
2405                 if (ins->inst_imm == 1) {
2406                         if (ins->dreg != ins->sreg1)
2407                                 ins->opcode = OP_MOVE;
2408                         else
2409                                 MONO_DELETE_INS (bb, ins);
2410                 }
2411                 break;
2412         case OP_LOAD_MEMBASE:
2413         case OP_LOADI4_MEMBASE:
2414                 /*
2415                  * Note: if reg1 = reg2 the load op is removed
2416                  *
2417                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2418                  * OP_LOAD_MEMBASE offset(basereg), reg2
2419                  * -->
2420                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2421                  * OP_MOVE reg1, reg2
2422                  */
2423                 if (last_ins &&
2424                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2425                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2426                         ins->inst_basereg == last_ins->inst_destbasereg &&
2427                         ins->inst_offset == last_ins->inst_offset) {
2428                         if (ins->dreg == last_ins->sreg1) {
2429                                 MONO_DELETE_INS (bb, ins);
2430                                 break;
2431                         } else {
2432                                 ins->opcode = OP_MOVE;
2433                                 ins->sreg1 = last_ins->sreg1;
2434                         }
2435
2436                         /*
2437                          * Note: reg1 must be different from the basereg in the second load
2438                          * Note: if reg1 = reg2 is equal then second load is removed
2439                          *
2440                          * OP_LOAD_MEMBASE offset(basereg), reg1
2441                          * OP_LOAD_MEMBASE offset(basereg), reg2
2442                          * -->
2443                          * OP_LOAD_MEMBASE offset(basereg), reg1
2444                          * OP_MOVE reg1, reg2
2445                          */
2446                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2447                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2448                           ins->inst_basereg != last_ins->dreg &&
2449                           ins->inst_basereg == last_ins->inst_basereg &&
2450                           ins->inst_offset == last_ins->inst_offset) {
2451
2452                         if (ins->dreg == last_ins->dreg) {
2453                                 MONO_DELETE_INS (bb, ins);
2454                         } else {
2455                                 ins->opcode = OP_MOVE;
2456                                 ins->sreg1 = last_ins->dreg;
2457                         }
2458
2459                         //g_assert_not_reached ();
2460
2461 #if 0
2462                         /*
2463                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2464                          * OP_LOAD_MEMBASE offset(basereg), reg
2465                          * -->
2466                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2467                          * OP_ICONST reg, imm
2468                          */
2469                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2470                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2471                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2472                                    ins->inst_offset == last_ins->inst_offset) {
2473                         ins->opcode = OP_ICONST;
2474                         ins->inst_c0 = last_ins->inst_imm;
2475                         g_assert_not_reached (); // check this rule
2476 #endif
2477                 }
2478                 break;
2479         case OP_LOADI1_MEMBASE:
2480         case OP_LOADU1_MEMBASE:
2481                 /*
2482                  * Note: if reg1 = reg2 the load op is removed
2483                  *
2484                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2485                  * OP_LOAD_MEMBASE offset(basereg), reg2
2486                  * -->
2487                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2488                  * OP_MOVE reg1, reg2
2489                  */
2490                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2491                         ins->inst_basereg == last_ins->inst_destbasereg &&
2492                         ins->inst_offset == last_ins->inst_offset) {
2493                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2494                         ins->sreg1 = last_ins->sreg1;
2495                 }
2496                 break;
2497         case OP_LOADI2_MEMBASE:
2498         case OP_LOADU2_MEMBASE:
2499                 /*
2500                  * Note: if reg1 = reg2 the load op is removed
2501                  *
2502                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2503                  * OP_LOAD_MEMBASE offset(basereg), reg2
2504                  * -->
2505                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2506                  * OP_MOVE reg1, reg2
2507                  */
2508                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2509                         ins->inst_basereg == last_ins->inst_destbasereg &&
2510                         ins->inst_offset == last_ins->inst_offset) {
2511 #if SIZEOF_REGISTER == 8
2512                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2513 #else
2514                         /* The definition of OP_PCONV_TO_U2 is wrong */
2515                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2516 #endif
2517                         ins->sreg1 = last_ins->sreg1;
2518                 }
2519                 break;
2520         case OP_MOVE:
2521         case OP_FMOVE:
2522                 /*
2523                  * Removes:
2524                  *
2525                  * OP_MOVE reg, reg
2526                  */
2527                 if (ins->dreg == ins->sreg1) {
2528                         MONO_DELETE_INS (bb, ins);
2529                         break;
2530                 }
2531                 /*
2532                  * Removes:
2533                  *
2534                  * OP_MOVE sreg, dreg
2535                  * OP_MOVE dreg, sreg
2536                  */
2537                 if (last_ins && last_ins->opcode == OP_MOVE &&
2538                         ins->sreg1 == last_ins->dreg &&
2539                         ins->dreg == last_ins->sreg1) {
2540                         MONO_DELETE_INS (bb, ins);
2541                 }
2542                 break;
2543         case OP_NOP:
2544                 MONO_DELETE_INS (bb, ins);
2545                 break;
2546         }
2547 }
2548