mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 const char*
 423 mono_ji_type_to_string (MonoJumpInfoType type)
 424 {
 425         return patch_info_str [type];
 426 }
 427
 428 void
 429 mono_print_ji (const MonoJumpInfo *ji)
 430 {
 431         switch (ji->type) {
 432         case MONO_PATCH_INFO_RGCTX_FETCH: {
 433                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 434
 435                 printf ("[RGCTX_FETCH ");
 436                 mono_print_ji (entry->data);
 437                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 438                 break;
 439         }
 440         case MONO_PATCH_INFO_METHODCONST: {
 441                 char *s = mono_method_full_name (ji->data.method, TRUE);
 442                 printf ("[METHODCONST - %s]", s);
 443                 g_free (s);
 444                 break;
 445         }
 446         case MONO_PATCH_INFO_INTERNAL_METHOD: {
 447                 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
 448                 break;
 449         }
 450         default:
 451                 printf ("[%s]", patch_info_str [ji->type]);
 452                 break;
 453         }
 454 }
 455
 456 void
 457 mono_print_ins_index (int i, MonoInst *ins)
 458 {
 459         GString *buf = mono_print_ins_index_strbuf (i, ins);
 460         printf ("%s\n", buf->str);
 461         g_string_free (buf, TRUE);
 462 }
 463
 464 GString *
 465 mono_print_ins_index_strbuf (int i, MonoInst *ins)
 466 {
 467         const char *spec = ins_get_spec (ins->opcode);
 468         GString *sbuf = g_string_new (NULL);
 469         int num_sregs, j;
 470         int sregs [MONO_MAX_SRC_REGS];
 471
 472         if (i != -1)
 473                 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
 474         else
 475                 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
 476         if (spec == MONO_ARCH_CPU_SPEC) {
 477                 gboolean dest_base = FALSE;
 478                 switch (ins->opcode) {
 479                 case OP_STOREV_MEMBASE:
 480                         dest_base = TRUE;
 481                         break;
 482                 default:
 483                         break;
 484                 }
 485
 486                 /* This is a lowered opcode */
 487                 if (ins->dreg != -1) {
 488                         if (dest_base)
 489                                 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 490                         else
 491                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 492                 }
 493                 if (ins->sreg1 != -1)
 494                         g_string_append_printf (sbuf, " R%d", ins->sreg1);
 495                 if (ins->sreg2 != -1)
 496                         g_string_append_printf (sbuf, " R%d", ins->sreg2);
 497                 if (ins->sreg3 != -1)
 498                         g_string_append_printf (sbuf, " R%d", ins->sreg3);
 499
 500                 switch (ins->opcode) {
 501                 case OP_LBNE_UN:
 502                 case OP_LBEQ:
 503                 case OP_LBLT:
 504                 case OP_LBLT_UN:
 505                 case OP_LBGT:
 506                 case OP_LBGT_UN:
 507                 case OP_LBGE:
 508                 case OP_LBGE_UN:
 509                 case OP_LBLE:
 510                 case OP_LBLE_UN:
 511                         if (!ins->inst_false_bb)
 512                                 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 513                         else
 514                                 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 515                         break;
 516                 case OP_PHI:
 517                 case OP_VPHI:
 518                 case OP_XPHI:
 519                 case OP_FPHI: {
 520                         int i;
 521                         g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
 522                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 523                                 if (i)
 524                                         g_string_append_printf (sbuf, ", ");
 525                                 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
 526                         }
 527                         g_string_append_printf (sbuf, ")]");
 528                         break;
 529                 }
 530                 case OP_LDADDR:
 531                 case OP_OUTARG_VTRETADDR:
 532                         g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
 533                         break;
 534                 case OP_REGOFFSET:
 535                 case OP_GSHAREDVT_ARG_REGOFFSET:
 536                         g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
 537                         break;
 538                 case OP_ISINST:
 539                 case OP_CASTCLASS:
 540                         g_string_append_printf (sbuf, " %s", ins->klass->name);
 541                         break;
 542                 default:
 543                         break;
 544                 }
 545
 546                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 547                 return sbuf;
 548         }
 549
 550         if (spec [MONO_INST_DEST]) {
 551                 int bank = dreg_bank (spec);
 552                 if (is_soft_reg (ins->dreg, bank)) {
 553                         if (spec [MONO_INST_DEST] == 'b') {
 554                                 if (ins->inst_offset == 0)
 555                                         g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
 556                                 else
 557                                         g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 558                         }
 559                         else
 560                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 561                 } else if (spec [MONO_INST_DEST] == 'b') {
 562                         if (ins->inst_offset == 0)
 563                                 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
 564                         else
 565                                 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 566                 } else
 567                         g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
 568         }
 569         if (spec [MONO_INST_SRC1]) {
 570                 int bank = sreg1_bank (spec);
 571                 if (is_soft_reg (ins->sreg1, bank)) {
 572                         if (spec [MONO_INST_SRC1] == 'b')
 573                                 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 574                         else
 575                                 g_string_append_printf (sbuf, " R%d", ins->sreg1);
 576                 } else if (spec [MONO_INST_SRC1] == 'b')
 577                         g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 578                 else
 579                         g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
 580         }
 581         num_sregs = mono_inst_get_src_registers (ins, sregs);
 582         for (j = 1; j < num_sregs; ++j) {
 583                 int bank = sreg_bank (j, spec);
 584                 if (is_soft_reg (sregs [j], bank))
 585                         g_string_append_printf (sbuf, " R%d", sregs [j]);
 586                 else
 587                         g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
 588         }
 589
 590         switch (ins->opcode) {
 591         case OP_ICONST:
 592                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
 593                 break;
 594 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 595         case OP_X86_PUSH_IMM:
 596 #endif
 597         case OP_ICOMPARE_IMM:
 598         case OP_COMPARE_IMM:
 599         case OP_IADD_IMM:
 600         case OP_ISUB_IMM:
 601         case OP_IAND_IMM:
 602         case OP_IOR_IMM:
 603         case OP_IXOR_IMM:
 604         case OP_SUB_IMM:
 605         case OP_STORE_MEMBASE_IMM:
 606                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
 607                 break;
 608         case OP_ADD_IMM:
 609         case OP_LADD_IMM:
 610                 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
 611                 break;
 612         case OP_I8CONST:
 613                 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
 614                 break;
 615         case OP_R8CONST:
 616                 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
 617                 break;
 618         case OP_R4CONST:
 619                 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
 620                 break;
 621         case OP_CALL:
 622         case OP_CALL_MEMBASE:
 623         case OP_CALL_REG:
 624         case OP_FCALL:
 625         case OP_LCALL:
 626         case OP_VCALL:
 627         case OP_VCALL_REG:
 628         case OP_VCALL_MEMBASE:
 629         case OP_VCALL2:
 630         case OP_VCALL2_REG:
 631         case OP_VCALL2_MEMBASE:
 632         case OP_VOIDCALL:
 633         case OP_VOIDCALL_MEMBASE:
 634         case OP_TAILCALL: {
 635                 MonoCallInst *call = (MonoCallInst*)ins;
 636                 GSList *list;
 637
 638                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 639                         /*
 640                          * These are lowered opcodes, but they are in the .md files since the old
 641                          * JIT passes them to backends.
 642                          */
 643                         if (ins->dreg != -1)
 644                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 645                 }
 646
 647                 if (call->method) {
 648                         char *full_name = mono_method_full_name (call->method, TRUE);
 649                         g_string_append_printf (sbuf, " [%s]", full_name);
 650                         g_free (full_name);
 651                 } else if (call->fptr_is_patch) {
 652                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 653
 654                         g_string_append_printf (sbuf, " ");
 655                         mono_print_ji (ji);
 656                 } else if (call->fptr) {
 657                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 658                         if (info)
 659                                 g_string_append_printf (sbuf, " [%s]", info->name);
 660                 }
 661
 662                 list = call->out_ireg_args;
 663                 while (list) {
 664                         guint32 regpair;
 665                         int reg, hreg;
 666
 667                         regpair = (guint32)(gssize)(list->data);
 668                         hreg = regpair >> 24;
 669                         reg = regpair & 0xffffff;
 670
 671                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
 672
 673                         list = g_slist_next (list);
 674                 }
 675                 list = call->out_freg_args;
 676                 while (list) {
 677                         guint32 regpair;
 678                         int reg, hreg;
 679
 680                         regpair = (guint32)(gssize)(list->data);
 681                         hreg = regpair >> 24;
 682                         reg = regpair & 0xffffff;
 683
 684                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
 685
 686                         list = g_slist_next (list);
 687                 }
 688                 break;
 689         }
 690         case OP_BR:
 691         case OP_CALL_HANDLER:
 692                 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
 693                 break;
 694         case OP_IBNE_UN:
 695         case OP_IBEQ:
 696         case OP_IBLT:
 697         case OP_IBLT_UN:
 698         case OP_IBGT:
 699         case OP_IBGT_UN:
 700         case OP_IBGE:
 701         case OP_IBGE_UN:
 702         case OP_IBLE:
 703         case OP_IBLE_UN:
 704         case OP_LBNE_UN:
 705         case OP_LBEQ:
 706         case OP_LBLT:
 707         case OP_LBLT_UN:
 708         case OP_LBGT:
 709         case OP_LBGT_UN:
 710         case OP_LBGE:
 711         case OP_LBGE_UN:
 712         case OP_LBLE:
 713         case OP_LBLE_UN:
 714                 if (!ins->inst_false_bb)
 715                         g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 716                 else
 717                         g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 718                 break;
 719         case OP_LIVERANGE_START:
 720         case OP_LIVERANGE_END:
 721         case OP_GC_LIVENESS_DEF:
 722         case OP_GC_LIVENESS_USE:
 723                 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
 724                 break;
 725         case OP_IL_SEQ_POINT:
 726         case OP_SEQ_POINT:
 727                 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 728                 break;
 729         case OP_COND_EXC_EQ:
 730         case OP_COND_EXC_GE:
 731         case OP_COND_EXC_GT:
 732         case OP_COND_EXC_LE:
 733         case OP_COND_EXC_LT:
 734         case OP_COND_EXC_NE_UN:
 735         case OP_COND_EXC_GE_UN:
 736         case OP_COND_EXC_GT_UN:
 737         case OP_COND_EXC_LE_UN:
 738         case OP_COND_EXC_LT_UN:
 739         case OP_COND_EXC_OV:
 740         case OP_COND_EXC_NO:
 741         case OP_COND_EXC_C:
 742         case OP_COND_EXC_NC:
 743         case OP_COND_EXC_IEQ:
 744         case OP_COND_EXC_IGE:
 745         case OP_COND_EXC_IGT:
 746         case OP_COND_EXC_ILE:
 747         case OP_COND_EXC_ILT:
 748         case OP_COND_EXC_INE_UN:
 749         case OP_COND_EXC_IGE_UN:
 750         case OP_COND_EXC_IGT_UN:
 751         case OP_COND_EXC_ILE_UN:
 752         case OP_COND_EXC_ILT_UN:
 753         case OP_COND_EXC_IOV:
 754         case OP_COND_EXC_INO:
 755         case OP_COND_EXC_IC:
 756         case OP_COND_EXC_INC:
 757                 g_string_append_printf (sbuf, " %s", ins->inst_p1);
 758                 break;
 759         default:
 760                 break;
 761         }
 762
 763         if (spec [MONO_INST_CLOB])
 764                 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
 765         return sbuf;
 766 }
 767
 768 static void
 769 print_regtrack (RegTrack *t, int num)
 770 {
 771         int i;
 772         char buf [32];
 773         const char *r;
 774
 775         for (i = 0; i < num; ++i) {
 776                 if (!t [i].born_in)
 777                         continue;
 778                 if (i >= MONO_MAX_IREGS) {
 779                         g_snprintf (buf, sizeof(buf), "R%d", i);
 780                         r = buf;
 781                 } else
 782                         r = mono_arch_regname (i);
 783                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 784         }
 785 }
 786 #else
 787
 788 const char*
 789 mono_ji_type_to_string (MonoJumpInfoType type)
 790 {
 791         return "";
 792 }
 793
 794 void
 795 mono_print_ji (const MonoJumpInfo *ji)
 796 {
 797 }
 798
 799 void
 800 mono_print_ins_index (int i, MonoInst *ins)
 801 {
 802 }
 803 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 804
 805 void
 806 mono_print_ins (MonoInst *ins)
 807 {
 808         mono_print_ins_index (-1, ins);
 809 }
 810
 811 static inline void
 812 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 813 {
 814         /*
 815          * If this function is called multiple times, the new instructions are inserted
 816          * in the proper order.
 817          */
 818         mono_bblock_insert_before_ins (bb, ins, to_insert);
 819 }
 820
 821 static inline void
 822 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 823 {
 824         /*
 825          * If this function is called multiple times, the new instructions are inserted in
 826          * proper order.
 827          */
 828         mono_bblock_insert_after_ins (bb, *last, to_insert);
 829
 830         *last = to_insert;
 831 }
 832
 833 static inline int
 834 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 835 {
 836         if (vreg_is_ref (cfg, reg))
 837                 return MONO_REG_INT_REF;
 838         else if (vreg_is_mp (cfg, reg))
 839                 return MONO_REG_INT_MP;
 840         else
 841                 return bank;
 842 }
 843
 844 /*
 845  * Force the spilling of the variable in the symbolic register 'reg', and free
 846  * the hreg it was assigned to.
 847  */
 848 static void
 849 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 850 {
 851         MonoInst *load;
 852         int i, sel, spill;
 853         MonoRegState *rs = cfg->rs;
 854
 855         sel = rs->vassign [reg];
 856
 857         /* the vreg we need to spill lives in another logical reg bank */
 858         bank = translate_bank (cfg->rs, bank, sel);
 859
 860         /*i = rs->isymbolic [sel];
 861         g_assert (i == reg);*/
 862         i = reg;
 863         spill = ++cfg->spill_count;
 864         rs->vassign [i] = -spill - 1;
 865         if (G_UNLIKELY (bank))
 866                 mono_regstate_free_general (rs, sel, bank);
 867         else
 868                 mono_regstate_free_int (rs, sel);
 869         /* we need to create a spill var and insert a load to sel after the current instruction */
 870         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 871         load->dreg = sel;
 872         load->inst_basereg = cfg->frame_reg;
 873         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 874         insert_after_ins (bb, ins, last, load);
 875         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 876         if (G_UNLIKELY (bank))
 877                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 878         else
 879                 i = mono_regstate_alloc_int (rs, regmask (sel));
 880         g_assert (i == sel);
 881
 882         if (G_UNLIKELY (bank))
 883                 mono_regstate_free_general (rs, sel, bank);
 884         else
 885                 mono_regstate_free_int (rs, sel);
 886 }
 887
 888 static int
 889 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 890 {
 891         MonoInst *load;
 892         int i, sel, spill, num_sregs;
 893         int sregs [MONO_MAX_SRC_REGS];
 894         MonoRegState *rs = cfg->rs;
 895
 896         g_assert (bank < MONO_NUM_REGBANKS);
 897
 898         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 899         /* exclude the registers in the current instruction */
 900         num_sregs = mono_inst_get_src_registers (ins, sregs);
 901         for (i = 0; i < num_sregs; ++i) {
 902                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 903                         if (is_soft_reg (sregs [i], bank))
 904                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 905                         else
 906                                 regmask &= ~ (regmask (sregs [i]));
 907                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 908                 }
 909         }
 910         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 911                 regmask &= ~ (regmask (ins->dreg));
 912                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 913         }
 914
 915         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 916         g_assert (regmask); /* need at least a register we can free */
 917         sel = 0;
 918         /* we should track prev_use and spill the register that's farther */
 919         if (G_UNLIKELY (bank)) {
 920                 for (i = 0; i < regbank_size [bank]; ++i) {
 921                         if (regmask & (regmask (i))) {
 922                                 sel = i;
 923
 924                                 /* the vreg we need to load lives in another logical bank */
 925                                 bank = translate_bank (cfg->rs, bank, sel);
 926
 927                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 928                                 break;
 929                         }
 930                 }
 931
 932                 i = rs->symbolic [bank] [sel];
 933                 spill = ++cfg->spill_count;
 934                 rs->vassign [i] = -spill - 1;
 935                 mono_regstate_free_general (rs, sel, bank);
 936         }
 937         else {
 938                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 939                         if (regmask & (regmask (i))) {
 940                                 sel = i;
 941                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 942                                 break;
 943                         }
 944                 }
 945
 946                 i = rs->isymbolic [sel];
 947                 spill = ++cfg->spill_count;
 948                 rs->vassign [i] = -spill - 1;
 949                 mono_regstate_free_int (rs, sel);
 950         }
 951
 952         /* we need to create a spill var and insert a load to sel after the current instruction */
 953         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 954         load->dreg = sel;
 955         load->inst_basereg = cfg->frame_reg;
 956         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 957         insert_after_ins (bb, ins, last, load);
 958         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 959         if (G_UNLIKELY (bank))
 960                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 961         else
 962                 i = mono_regstate_alloc_int (rs, regmask (sel));
 963         g_assert (i == sel);
 964
 965         return sel;
 966 }
 967
 968 /*
 969  * free_up_hreg:
 970  *
 971  *   Free up the hreg HREG by spilling the vreg allocated to it.
 972  */
 973 static void
 974 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 975 {
 976         if (G_UNLIKELY (bank)) {
 977                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 978                         bank = translate_bank (cfg->rs, bank, hreg);
 979                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 980                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 981                 }
 982         }
 983         else {
 984                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 985                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 986                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 987                 }
 988         }
 989 }
 990
 991 static MonoInst*
 992 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 993 {
 994         MonoInst *copy;
 995
 996         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 997
 998         copy->dreg = dest;
 999         copy->sreg1 = src;
1000         copy->cil_code = ip;
1001         if (ins) {
1002                 mono_bblock_insert_after_ins (bb, ins, copy);
1003                 *last = copy;
1004         }
1005         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
1006         return copy;
1007 }
1008
1009 static inline const char*
1010 regbank_to_string (int bank)
1011 {
1012         if (bank == MONO_REG_INT_REF)
1013                 return "REF ";
1014         else if (bank == MONO_REG_INT_MP)
1015                 return "MP ";
1016         else
1017                 return "";
1018 }
1019
1020 static void
1021 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
1022 {
1023         MonoInst *store, *def;
1024
1025         bank = get_vreg_bank (cfg, prev_reg, bank);
1026
1027         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
1028         store->sreg1 = reg;
1029         store->inst_destbasereg = cfg->frame_reg;
1030         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
1031         if (ins) {
1032                 mono_bblock_insert_after_ins (bb, ins, store);
1033                 *last = store;
1034         } else if (insert_before) {
1035                 insert_before_ins (bb, insert_before, store);
1036         } else {
1037                 g_assert_not_reached ();
1038         }
1039         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
1040
1041         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1042                 g_assert (prev_reg != -1);
1043                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1044                 def->inst_c0 = spill;
1045                 def->inst_c1 = bank;
1046                 mono_bblock_insert_after_ins (bb, store, def);
1047         }
1048 }
1049
1050 /* flags used in reginfo->flags */
1051 enum {
1052         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1053         MONO_FP_NEEDS_SPILL                     = regmask (1),
1054         MONO_FP_NEEDS_LOAD                      = regmask (2)
1055 };
1056
1057 static inline int
1058 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1059 {
1060         int val;
1061
1062         if (info && info->preferred_mask) {
1063                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1064                 if (val >= 0) {
1065                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1066                         return val;
1067                 }
1068         }
1069
1070         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1071         if (val < 0)
1072                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1073
1074         return val;
1075 }
1076
1077 static inline int
1078 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1079 {
1080         int val;
1081
1082         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1083
1084         if (val < 0)
1085                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1086
1087         return val;
1088 }
1089
1090 static inline int
1091 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1092 {
1093         if (G_UNLIKELY (bank))
1094                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1095         else
1096                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1097 }
1098
1099 static inline void
1100 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1101 {
1102         if (G_UNLIKELY (bank)) {
1103                 int mirrored_bank;
1104
1105                 g_assert (reg >= regbank_size [bank]);
1106                 g_assert (hreg < regbank_size [bank]);
1107                 g_assert (! is_global_freg (hreg));
1108
1109                 rs->vassign [reg] = hreg;
1110                 rs->symbolic [bank] [hreg] = reg;
1111                 rs->free_mask [bank] &= ~ (regmask (hreg));
1112
1113                 mirrored_bank = get_mirrored_bank (bank);
1114                 if (mirrored_bank == -1)
1115                         return;
1116
1117                 /* Make sure the other logical reg bank that this bank shares
1118                  * a single hard reg bank knows that this hard reg is not free.
1119                  */
1120                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1121
1122                 /* Mark the other logical bank that the this bank shares
1123                  * a single hard reg bank with as mirrored.
1124                  */
1125                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1126
1127         }
1128         else {
1129                 g_assert (reg >= MONO_MAX_IREGS);
1130                 g_assert (hreg < MONO_MAX_IREGS);
1131 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1132                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1133                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1134                 g_assert (! is_global_ireg (hreg));
1135 #endif
1136
1137                 rs->vassign [reg] = hreg;
1138                 rs->isymbolic [hreg] = reg;
1139                 rs->ifree_mask &= ~ (regmask (hreg));
1140         }
1141 }
1142
1143 static inline regmask_t
1144 get_callee_mask (const char spec)
1145 {
1146         if (G_UNLIKELY (reg_bank (spec)))
1147                 return regbank_callee_regs [reg_bank (spec)];
1148         return MONO_ARCH_CALLEE_REGS;
1149 }
1150
1151 static gint8 desc_to_fixed_reg [256];
1152 static gboolean desc_to_fixed_reg_inited = FALSE;
1153
1154 #ifndef DISABLE_JIT
1155
1156 /*
1157  * Local register allocation.
1158  * We first scan the list of instructions and we save the liveness info of
1159  * each register (when the register is first used, when it's value is set etc.).
1160  * We also reverse the list of instructions because assigning registers backwards allows
1161  * for more tricks to be used.
1162  */
1163 void
1164 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1165 {
1166         MonoInst *ins, *prev, *last;
1167         MonoInst **tmp;
1168         MonoRegState *rs = cfg->rs;
1169         int i, j, val, max;
1170         RegTrack *reginfo;
1171         const char *spec;
1172         unsigned char spec_src1, spec_dest;
1173         int bank = 0;
1174 #if MONO_ARCH_USE_FPSTACK
1175         gboolean has_fp = FALSE;
1176         int fpstack [8];
1177         int sp = 0;
1178 #endif
1179         int num_sregs = 0;
1180         int sregs [MONO_MAX_SRC_REGS];
1181
1182         if (!bb->code)
1183                 return;
1184
1185         if (!desc_to_fixed_reg_inited) {
1186                 for (i = 0; i < 256; ++i)
1187                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1188                 desc_to_fixed_reg_inited = TRUE;
1189
1190                 /* Validate the cpu description against the info in mini-ops.h */
1191 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1192                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1193                         const char *ispec;
1194
1195                         spec = ins_get_spec (i);
1196                         ispec = INS_INFO (i);
1197
1198                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1199                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1200                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1201                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1202                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1203                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1204                 }
1205 #endif
1206         }
1207
1208         rs->next_vreg = bb->max_vreg;
1209         mono_regstate_assign (rs);
1210
1211         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1212         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1213                 rs->free_mask [i] = regbank_callee_regs [i];
1214
1215         max = rs->next_vreg;
1216
1217         if (cfg->reginfo && cfg->reginfo_len < max)
1218                 cfg->reginfo = NULL;
1219
1220         reginfo = (RegTrack *)cfg->reginfo;
1221         if (!reginfo) {
1222                 cfg->reginfo_len = MAX (1024, max * 2);
1223                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1224                 cfg->reginfo = reginfo;
1225         }
1226         else
1227                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1228
1229         if (cfg->verbose_level > 1) {
1230                 /* print_regtrack reads the info of all variables */
1231                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1232         }
1233
1234         /*
1235          * For large methods, next_vreg can be very large, so g_malloc0 time can
1236          * be prohibitive. So we manually init the reginfo entries used by the
1237          * bblock.
1238          */
1239         for (ins = bb->code; ins; ins = ins->next) {
1240                 gboolean modify = FALSE;
1241
1242                 spec = ins_get_spec (ins->opcode);
1243
1244                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1245                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1246 #if SIZEOF_REGISTER == 4
1247                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1248                                 /**
1249                                  * In the new IR, the two vregs of the regpair do not alias the
1250                                  * original long vreg. shift the vreg here so the rest of the
1251                                  * allocator doesn't have to care about it.
1252                                  */
1253                                 ins->dreg ++;
1254                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1255                         }
1256 #endif
1257                 }
1258
1259                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1260                 for (j = 0; j < num_sregs; ++j) {
1261                         g_assert (sregs [j] != -1);
1262                         if (sregs [j] < max) {
1263                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1264 #if SIZEOF_REGISTER == 4
1265                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1266                                         sregs [j]++;
1267                                         modify = TRUE;
1268                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1269                                 }
1270 #endif
1271                         }
1272                 }
1273                 if (modify)
1274                         mono_inst_set_src_registers (ins, sregs);
1275         }
1276
1277         /*if (cfg->opt & MONO_OPT_COPYPROP)
1278                 local_copy_prop (cfg, ins);*/
1279
1280         i = 1;
1281         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1282         /* forward pass on the instructions to collect register liveness info */
1283         MONO_BB_FOR_EACH_INS (bb, ins) {
1284                 spec = ins_get_spec (ins->opcode);
1285                 spec_dest = spec [MONO_INST_DEST];
1286
1287                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1288                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1289                 }
1290
1291                 DEBUG (mono_print_ins_index (i, ins));
1292
1293                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1294
1295 #if MONO_ARCH_USE_FPSTACK
1296                 if (dreg_is_fp (spec)) {
1297                         has_fp = TRUE;
1298                 } else {
1299                         for (j = 0; j < num_sregs; ++j) {
1300                                 if (sreg_is_fp (j, spec))
1301                                         has_fp = TRUE;
1302                         }
1303                 }
1304 #endif
1305
1306                 for (j = 0; j < num_sregs; ++j) {
1307                         int sreg = sregs [j];
1308                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1309                         if (sreg_spec) {
1310                                 bank = sreg_bank (j, spec);
1311                                 g_assert (sreg != -1);
1312                                 if (is_soft_reg (sreg, bank))
1313                                         /* This means the vreg is not local to this bb */
1314                                         g_assert (reginfo [sreg].born_in > 0);
1315                                 rs->vassign [sreg] = -1;
1316                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1317                                 //reginfo [ins->sreg2].last_use = i;
1318                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1319                                         /* The virtual register is allocated sequentially */
1320                                         rs->vassign [sreg + 1] = -1;
1321                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1322                                         //reginfo [ins->sreg2 + 1].last_use = i;
1323                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1324                                                 reginfo [sreg + 1].born_in = i;
1325                                 }
1326                         } else {
1327                                 sregs [j] = -1;
1328                         }
1329                 }
1330                 mono_inst_set_src_registers (ins, sregs);
1331
1332                 if (spec_dest) {
1333                         int dest_dreg;
1334
1335                         bank = dreg_bank (spec);
1336                         if (spec_dest != 'b') /* it's not just a base register */
1337                                 reginfo [ins->dreg].killed_in = i;
1338                         g_assert (ins->dreg != -1);
1339                         rs->vassign [ins->dreg] = -1;
1340                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1341                         //reginfo [ins->dreg].last_use = i;
1342                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1343                                 reginfo [ins->dreg].born_in = i;
1344
1345                         dest_dreg = desc_to_fixed_reg [spec_dest];
1346                         if (dest_dreg != -1)
1347                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1348
1349 #ifdef MONO_ARCH_INST_FIXED_MASK
1350                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1351 #endif
1352
1353                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1354                                 /* The virtual register is allocated sequentially */
1355                                 rs->vassign [ins->dreg + 1] = -1;
1356                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1357                                 //reginfo [ins->dreg + 1].last_use = i;
1358                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1359                                         reginfo [ins->dreg + 1].born_in = i;
1360                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1361                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1362                         }
1363                 } else {
1364                         ins->dreg = -1;
1365                 }
1366
1367                 ++i;
1368         }
1369
1370         tmp = &last;
1371
1372         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1373         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1374                 int prev_dreg;
1375                 int dest_dreg, clob_reg;
1376                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1377                 int dreg_high, sreg1_high;
1378                 regmask_t dreg_mask, mask;
1379                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1380                 regmask_t dreg_fixed_mask;
1381                 const unsigned char *ip;
1382                 --i;
1383                 spec = ins_get_spec (ins->opcode);
1384                 spec_src1 = spec [MONO_INST_SRC1];
1385                 spec_dest = spec [MONO_INST_DEST];
1386                 prev_dreg = -1;
1387                 clob_reg = -1;
1388                 dest_dreg = -1;
1389                 dreg_high = -1;
1390                 sreg1_high = -1;
1391                 dreg_mask = get_callee_mask (spec_dest);
1392                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1393                         prev_sregs [j] = -1;
1394                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1395                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1396 #ifdef MONO_ARCH_INST_FIXED_MASK
1397                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1398 #else
1399                         sreg_fixed_masks [j] = 0;
1400 #endif
1401                 }
1402
1403                 DEBUG (printf ("processing:"));
1404                 DEBUG (mono_print_ins_index (i, ins));
1405
1406                 ip = ins->cil_code;
1407
1408                 last = ins;
1409
1410                 /*
1411                  * FIXED REGS
1412                  */
1413                 dest_dreg = desc_to_fixed_reg [spec_dest];
1414                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1415                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1416
1417 #ifdef MONO_ARCH_INST_FIXED_MASK
1418                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1419 #else
1420                 dreg_fixed_mask = 0;
1421 #endif
1422
1423                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1424
1425                 /*
1426                  * TRACK FIXED SREG2, 3, ...
1427                  */
1428                 for (j = 1; j < num_sregs; ++j) {
1429                         int sreg = sregs [j];
1430                         int dest_sreg = dest_sregs [j];
1431
1432                         if (dest_sreg == -1)
1433                                 continue;
1434
1435                         if (j == 2) {
1436                                 int k;
1437
1438                                 /*
1439                                  * CAS.
1440                                  * We need to special case this, since on x86, there are only 3
1441                                  * free registers, and the code below assigns one of them to
1442                                  * sreg, so we can run out of registers when trying to assign
1443                                  * dreg. Instead, we just set up the register masks, and let the
1444                                  * normal sreg2 assignment code handle this. It would be nice to
1445                                  * do this for all the fixed reg cases too, but there is too much
1446                                  * risk of breakage.
1447                                  */
1448
1449                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1450                                 sreg_masks [j] = regmask (dest_sreg);
1451                                 for (k = 0; k < num_sregs; ++k) {
1452                                         if (k != j)
1453                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1454                                 }
1455
1456                                 /*
1457                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1458                                  */
1459                                 for (k = 0; k < num_sregs; ++k) {
1460                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1461                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1462                                 }
1463
1464                                 /*
1465                                  * We can also run out of registers while processing sreg2 if sreg3 is
1466                                  * assigned to another hreg, so spill sreg3 now.
1467                                  */
1468                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1469                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1470                                 }
1471                                 continue;
1472                         }
1473
1474                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1475                                 if (is_global_ireg (sreg)) {
1476                                         int k;
1477                                         /* Argument already in hard reg, need to copy */
1478                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1479                                         insert_before_ins (bb, ins, copy);
1480                                         for (k = 0; k < num_sregs; ++k) {
1481                                                 if (k != j)
1482                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1483                                         }
1484                                         /* See below */
1485                                         dreg_mask &= ~ (regmask (dest_sreg));
1486                                 } else {
1487                                         val = rs->vassign [sreg];
1488                                         if (val == -1) {
1489                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1490                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1491                                         } else if (val < -1) {
1492                                                 /* FIXME: */
1493                                                 g_assert_not_reached ();
1494                                         } else {
1495                                                 /* Argument already in hard reg, need to copy */
1496                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1497                                                 int k;
1498
1499                                                 insert_before_ins (bb, ins, copy);
1500                                                 for (k = 0; k < num_sregs; ++k) {
1501                                                         if (k != j)
1502                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1503                                                 }
1504                                                 /*
1505                                                  * Prevent the dreg from being allocated to dest_sreg
1506                                                  * too, since it could force sreg1 to be allocated to
1507                                                  * the same reg on x86.
1508                                                  */
1509                                                 dreg_mask &= ~ (regmask (dest_sreg));
1510                                         }
1511                                 }
1512                         } else {
1513                                 gboolean need_spill = TRUE;
1514                                 gboolean need_assign = TRUE;
1515                                 int k;
1516
1517                                 dreg_mask &= ~ (regmask (dest_sreg));
1518                                 for (k = 0; k < num_sregs; ++k) {
1519                                         if (k != j)
1520                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1521                                 }
1522
1523                                 /*
1524                                  * First check if dreg is assigned to dest_sreg2, since we
1525                                  * can't spill a dreg.
1526                                  */
1527                                 if (spec [MONO_INST_DEST])
1528                                         val = rs->vassign [ins->dreg];
1529                                 else
1530                                         val = -1;
1531                                 if (val == dest_sreg && ins->dreg != sreg) {
1532                                         /*
1533                                          * the destination register is already assigned to
1534                                          * dest_sreg2: we need to allocate another register for it
1535                                          * and then copy from this to dest_sreg2.
1536                                          */
1537                                         int new_dest;
1538                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1539                                         g_assert (new_dest >= 0);
1540                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1541
1542                                         prev_dreg = ins->dreg;
1543                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1544                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1545                                         mono_regstate_free_int (rs, dest_sreg);
1546                                         need_spill = FALSE;
1547                                 }
1548
1549                                 if (is_global_ireg (sreg)) {
1550                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1551                                         insert_before_ins (bb, ins, copy);
1552                                         need_assign = FALSE;
1553                                 }
1554                                 else {
1555                                         val = rs->vassign [sreg];
1556                                         if (val == dest_sreg) {
1557                                                 /* sreg2 is already assigned to the correct register */
1558                                                 need_spill = FALSE;
1559                                         } else if (val < -1) {
1560                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1561                                         } else if (val >= 0) {
1562                                                 /* sreg2 already assigned to another register */
1563                                                 /*
1564                                                  * We couldn't emit a copy from val to dest_sreg2, because
1565                                                  * val might be spilled later while processing this
1566                                                  * instruction. So we spill sreg2 so it can be allocated to
1567                                                  * dest_sreg2.
1568                                                  */
1569                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1570                                         }
1571                                 }
1572
1573                                 if (need_spill) {
1574                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1575                                 }
1576
1577                                 if (need_assign) {
1578                                         if (rs->vassign [sreg] < -1) {
1579                                                 int spill;
1580
1581                                                 /* Need to emit a spill store */
1582                                                 spill = - rs->vassign [sreg] - 1;
1583                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1584                                         }
1585                                         /* force-set sreg2 */
1586                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1587                                 }
1588                         }
1589                         sregs [j] = dest_sreg;
1590                 }
1591                 mono_inst_set_src_registers (ins, sregs);
1592
1593                 /*
1594                  * TRACK DREG
1595                  */
1596                 bank = dreg_bank (spec);
1597                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1598                         prev_dreg = ins->dreg;
1599                 }
1600
1601                 if (spec_dest == 'b') {
1602                         /*
1603                          * The dest reg is read by the instruction, not written, so
1604                          * avoid allocating sreg1/sreg2 to the same reg.
1605                          */
1606                         if (dest_sregs [0] != -1)
1607                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1608                         for (j = 1; j < num_sregs; ++j) {
1609                                 if (dest_sregs [j] != -1)
1610                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1611                         }
1612
1613                         val = rs->vassign [ins->dreg];
1614                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1615                                 /* DREG is already allocated to a register needed for sreg1 */
1616                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1617                         }
1618                 }
1619
1620                 /*
1621                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1622                  * various complex situations.
1623                  */
1624                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1625                         guint32 dreg2, dest_dreg2;
1626
1627                         g_assert (is_soft_reg (ins->dreg, bank));
1628
1629                         if (dest_dreg != -1) {
1630                                 if (rs->vassign [ins->dreg] != dest_dreg)
1631                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1632
1633                                 dreg2 = ins->dreg + 1;
1634                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1635                                 if (dest_dreg2 != -1) {
1636                                         if (rs->vassign [dreg2] != dest_dreg2)
1637                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1638                                 }
1639                         }
1640                 }
1641
1642                 if (dreg_fixed_mask) {
1643                         g_assert (!bank);
1644                         if (is_global_ireg (ins->dreg)) {
1645                                 /*
1646                                  * The argument is already in a hard reg, but that reg is
1647                                  * not usable by this instruction, so allocate a new one.
1648                                  */
1649                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1650                                 if (val < 0)
1651                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1652                                 mono_regstate_free_int (rs, val);
1653                                 dest_dreg = val;
1654
1655                                 /* Fall through */
1656                         }
1657                         else
1658                                 dreg_mask &= dreg_fixed_mask;
1659                 }
1660
1661                 if (is_soft_reg (ins->dreg, bank)) {
1662                         val = rs->vassign [ins->dreg];
1663
1664                         if (val < 0) {
1665                                 int spill = 0;
1666                                 if (val < -1) {
1667                                         /* the register gets spilled after this inst */
1668                                         spill = -val -1;
1669                                 }
1670                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1671                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1672                                 if (spill)
1673                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1674                         }
1675
1676                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1677                         ins->dreg = val;
1678                 }
1679
1680                 /* Handle regpairs */
1681                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1682                         int reg2 = prev_dreg + 1;
1683
1684                         g_assert (!bank);
1685                         g_assert (prev_dreg > -1);
1686                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1687                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1688 #ifdef TARGET_X86
1689                         /* bug #80489 */
1690                         mask &= ~regmask (X86_ECX);
1691 #endif
1692                         val = rs->vassign [reg2];
1693                         if (val < 0) {
1694                                 int spill = 0;
1695                                 if (val < -1) {
1696                                         /* the register gets spilled after this inst */
1697                                         spill = -val -1;
1698                                 }
1699                                 val = mono_regstate_alloc_int (rs, mask);
1700                                 if (val < 0)
1701                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1702                                 if (spill)
1703                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1704                         }
1705                         else {
1706                                 if (! (mask & (regmask (val)))) {
1707                                         val = mono_regstate_alloc_int (rs, mask);
1708                                         if (val < 0)
1709                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1710
1711                                         /* Reallocate hreg to the correct register */
1712                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1713
1714                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1715                                 }
1716                         }
1717
1718                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1719                         assign_reg (cfg, rs, reg2, val, bank);
1720
1721                         dreg_high = val;
1722                         ins->backend.reg3 = val;
1723
1724                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1725                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1726                                 mono_regstate_free_int (rs, val);
1727                         }
1728                 }
1729
1730                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1731                         /*
1732                          * In theory, we could free up the hreg even if the vreg is alive,
1733                          * but branches inside bblocks force us to assign the same hreg
1734                          * to a vreg every time it is encountered.
1735                          */
1736                         int dreg = rs->vassign [prev_dreg];
1737                         g_assert (dreg >= 0);
1738                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1739                         if (G_UNLIKELY (bank))
1740                                 mono_regstate_free_general (rs, dreg, bank);
1741                         else
1742                                 mono_regstate_free_int (rs, dreg);
1743                         rs->vassign [prev_dreg] = -1;
1744                 }
1745
1746                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1747                         /* this instruction only outputs to dest_dreg, need to copy */
1748                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1749                         ins->dreg = dest_dreg;
1750
1751                         if (G_UNLIKELY (bank)) {
1752                                 /* the register we need to free up may be used in another logical regbank
1753                                  * so do a translate just in case.
1754                                  */
1755                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1756                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1757                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1758                         }
1759                         else {
1760                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1761                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1762                         }
1763                 }
1764
1765                 if (spec_dest == 'b') {
1766                         /*
1767                          * The dest reg is read by the instruction, not written, so
1768                          * avoid allocating sreg1/sreg2 to the same reg.
1769                          */
1770                         for (j = 0; j < num_sregs; ++j)
1771                                 if (!sreg_bank (j, spec))
1772                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1773                 }
1774
1775                 /*
1776                  * TRACK CLOBBERING
1777                  */
1778                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1779                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1780                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1781                 }
1782
1783                 if (spec [MONO_INST_CLOB] == 'c') {
1784                         int j, s, dreg, dreg2, cur_bank;
1785                         guint64 clob_mask;
1786
1787                         clob_mask = MONO_ARCH_CALLEE_REGS;
1788
1789                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1790                                 /*
1791                                  * Need to avoid spilling the dreg since the dreg is not really
1792                                  * clobbered by the call.
1793                                  */
1794                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1795                                         dreg = rs->vassign [prev_dreg];
1796                                 else
1797                                         dreg = -1;
1798
1799                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1800                                         dreg2 = rs->vassign [prev_dreg + 1];
1801                                 else
1802                                         dreg2 = -1;
1803
1804                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1805                                         s = regmask (j);
1806                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1807                                                 if ((j != dreg) && (j != dreg2))
1808                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1809                                                 else if (rs->isymbolic [j])
1810                                                         /* The hreg is assigned to the dreg of this instruction */
1811                                                         rs->vassign [rs->isymbolic [j]] = -1;
1812                                                 mono_regstate_free_int (rs, j);
1813                                         }
1814                                 }
1815                         }
1816
1817                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1818                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1819                                         clob_mask = regbank_callee_regs [cur_bank];
1820                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1821                                                 dreg = rs->vassign [prev_dreg];
1822                                         else
1823                                                 dreg = -1;
1824
1825                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1826
1827                                                 /* we are looping though the banks in the outer loop
1828                                                  * so, we don't need to deal with mirrored hregs
1829                                                  * because we will get them in one of the other bank passes.
1830                                                  */
1831                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1832                                                         continue;
1833
1834                                                 s = regmask (j);
1835                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1836                                                         if (j != dreg)
1837                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1838                                                         else if (rs->symbolic [cur_bank] [j])
1839                                                                 /* The hreg is assigned to the dreg of this instruction */
1840                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1841                                                         mono_regstate_free_general (rs, j, cur_bank);
1842                                                 }
1843                                         }
1844                                 }
1845                         }
1846                 }
1847
1848                 /*
1849                  * TRACK ARGUMENT REGS
1850                  */
1851                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1852                         MonoCallInst *call = (MonoCallInst*)ins;
1853                         GSList *list;
1854
1855                         /*
1856                          * This needs to be done before assigning sreg1, so sreg1 will
1857                          * not be assigned one of the argument regs.
1858                          */
1859
1860                         /*
1861                          * Assign all registers in call->out_reg_args to the proper
1862                          * argument registers.
1863                          */
1864
1865                         list = call->out_ireg_args;
1866                         if (list) {
1867                                 while (list) {
1868                                         guint32 regpair;
1869                                         int reg, hreg;
1870
1871                                         regpair = (guint32)(gssize)(list->data);
1872                                         hreg = regpair >> 24;
1873                                         reg = regpair & 0xffffff;
1874
1875                                         assign_reg (cfg, rs, reg, hreg, 0);
1876
1877                                         sreg_masks [0] &= ~(regmask (hreg));
1878
1879                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1880
1881                                         list = g_slist_next (list);
1882                                 }
1883                         }
1884
1885                         list = call->out_freg_args;
1886                         if (list) {
1887                                 while (list) {
1888                                         guint32 regpair;
1889                                         int reg, hreg;
1890
1891                                         regpair = (guint32)(gssize)(list->data);
1892                                         hreg = regpair >> 24;
1893                                         reg = regpair & 0xffffff;
1894
1895                                         assign_reg (cfg, rs, reg, hreg, 1);
1896
1897                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1898
1899                                         list = g_slist_next (list);
1900                                 }
1901                         }
1902                 }
1903
1904                 /*
1905                  * TRACK SREG1
1906                  */
1907                 bank = sreg1_bank (spec);
1908                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1909                         int sreg1 = sregs [0];
1910                         int dest_sreg1 = dest_sregs [0];
1911
1912                         g_assert (is_soft_reg (sreg1, bank));
1913
1914                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1915                         if (dest_sreg1 != -1)
1916                                 g_assert (dest_sreg1 == ins->dreg);
1917                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1918                         g_assert (val >= 0);
1919
1920                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1921                                 // FIXME:
1922                                 g_assert_not_reached ();
1923
1924                         assign_reg (cfg, rs, sreg1, val, bank);
1925
1926                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1927
1928                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1929                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1930                         g_assert (val >= 0);
1931
1932                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1933                                 // FIXME:
1934                                 g_assert_not_reached ();
1935
1936                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1937
1938                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1939
1940                         /* Skip rest of this section */
1941                         dest_sregs [0] = -1;
1942                 }
1943
1944                 if (sreg_fixed_masks [0]) {
1945                         g_assert (!bank);
1946                         if (is_global_ireg (sregs [0])) {
1947                                 /*
1948                                  * The argument is already in a hard reg, but that reg is
1949                                  * not usable by this instruction, so allocate a new one.
1950                                  */
1951                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1952                                 if (val < 0)
1953                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1954                                 mono_regstate_free_int (rs, val);
1955                                 dest_sregs [0] = val;
1956
1957                                 /* Fall through to the dest_sreg1 != -1 case */
1958                         }
1959                         else
1960                                 sreg_masks [0] &= sreg_fixed_masks [0];
1961                 }
1962
1963                 if (dest_sregs [0] != -1) {
1964                         sreg_masks [0] = regmask (dest_sregs [0]);
1965
1966                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1967                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1968                         }
1969                         if (is_global_ireg (sregs [0])) {
1970                                 /* The argument is already in a hard reg, need to copy */
1971                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1972                                 insert_before_ins (bb, ins, copy);
1973                                 sregs [0] = dest_sregs [0];
1974                         }
1975                 }
1976
1977                 if (is_soft_reg (sregs [0], bank)) {
1978                         val = rs->vassign [sregs [0]];
1979                         prev_sregs [0] = sregs [0];
1980                         if (val < 0) {
1981                                 int spill = 0;
1982                                 if (val < -1) {
1983                                         /* the register gets spilled after this inst */
1984                                         spill = -val -1;
1985                                 }
1986
1987                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1988                                         /*
1989                                          * Allocate the same hreg to sreg1 as well so the
1990                                          * peephole can get rid of the move.
1991                                          */
1992                                         sreg_masks [0] = regmask (ins->dreg);
1993                                 }
1994
1995                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1996                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1997                                         sreg_masks [0] = regmask (ins->dreg);
1998
1999                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
2000                                 assign_reg (cfg, rs, sregs [0], val, bank);
2001                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
2002
2003                                 if (spill) {
2004                                         /*
2005                                          * Need to insert before the instruction since it can
2006                                          * overwrite sreg1.
2007                                          */
2008                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
2009                                 }
2010                         }
2011                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
2012                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
2013                                 insert_before_ins (bb, ins, copy);
2014                                 for (j = 1; j < num_sregs; ++j)
2015                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
2016                                 val = dest_sregs [0];
2017                         }
2018
2019                         sregs [0] = val;
2020                 }
2021                 else {
2022                         prev_sregs [0] = -1;
2023                 }
2024                 mono_inst_set_src_registers (ins, sregs);
2025
2026                 for (j = 1; j < num_sregs; ++j)
2027                         sreg_masks [j] &= ~(regmask (sregs [0]));
2028
2029                 /* Handle the case when sreg1 is a regpair but dreg is not */
2030                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2031                         int reg2 = prev_sregs [0] + 1;
2032
2033                         g_assert (!bank);
2034                         g_assert (prev_sregs [0] > -1);
2035                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2036                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2037                         val = rs->vassign [reg2];
2038                         if (val < 0) {
2039                                 int spill = 0;
2040                                 if (val < -1) {
2041                                         /* the register gets spilled after this inst */
2042                                         spill = -val -1;
2043                                 }
2044                                 val = mono_regstate_alloc_int (rs, mask);
2045                                 if (val < 0)
2046                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2047                                 if (spill)
2048                                         g_assert_not_reached ();
2049                         }
2050                         else {
2051                                 if (! (mask & (regmask (val)))) {
2052                                         /* The vreg is already allocated to a wrong hreg */
2053                                         /* FIXME: */
2054                                         g_assert_not_reached ();
2055 #if 0
2056                                         val = mono_regstate_alloc_int (rs, mask);
2057                                         if (val < 0)
2058                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2059
2060                                         /* Reallocate hreg to the correct register */
2061                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2062
2063                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2064 #endif
2065                                 }
2066                         }
2067
2068                         sreg1_high = val;
2069                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2070                         assign_reg (cfg, rs, reg2, val, bank);
2071                 }
2072
2073                 /* Handle dreg==sreg1 */
2074                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2075                         MonoInst *sreg2_copy = NULL;
2076                         MonoInst *copy;
2077                         int bank = reg_bank (spec_src1);
2078
2079                         if (ins->dreg == sregs [1]) {
2080                                 /*
2081                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2082                                  * register for it.
2083                                  */
2084                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2085
2086                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2087                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2088                                 prev_sregs [1] = sregs [1] = reg2;
2089
2090                                 if (G_UNLIKELY (bank))
2091                                         mono_regstate_free_general (rs, reg2, bank);
2092                                 else
2093                                         mono_regstate_free_int (rs, reg2);
2094                         }
2095
2096                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2097                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2098                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2099                                         /* FIXME: */
2100                                         g_assert_not_reached ();
2101
2102                                 /*
2103                                  * sreg1 and dest are already allocated to the same regpair by the
2104                                  * SREG1 allocation code.
2105                                  */
2106                                 g_assert (sregs [0] == ins->dreg);
2107                                 g_assert (dreg_high == sreg1_high);
2108                         }
2109
2110                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2111                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2112                         insert_before_ins (bb, ins, copy);
2113
2114                         if (sreg2_copy)
2115                                 insert_before_ins (bb, copy, sreg2_copy);
2116
2117                         /*
2118                          * Need to prevent sreg2 to be allocated to sreg1, since that
2119                          * would screw up the previous copy.
2120                          */
2121                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2122                         /* we set sreg1 to dest as well */
2123                         prev_sregs [0] = sregs [0] = ins->dreg;
2124                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2125                 }
2126                 mono_inst_set_src_registers (ins, sregs);
2127
2128                 /*
2129                  * TRACK SREG2, 3, ...
2130                  */
2131                 for (j = 1; j < num_sregs; ++j) {
2132                         int k;
2133
2134                         bank = sreg_bank (j, spec);
2135                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2136                                 g_assert_not_reached ();
2137
2138                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2139                                 /*
2140                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2141                                  * allocating it to the fixed reg.
2142                                  */
2143                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2144                                 insert_before_ins (bb, ins, copy);
2145                                 sregs [j] = dest_sregs [j];
2146                         } else if (is_soft_reg (sregs [j], bank)) {
2147                                 val = rs->vassign [sregs [j]];
2148
2149                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2150                                         /*
2151                                          * The sreg is already allocated to a hreg, but not to the fixed
2152                                          * reg required by the instruction. Spill the sreg, so it can be
2153                                          * allocated to the fixed reg by the code below.
2154                                          */
2155                                         /* Currently, this code should only be hit for CAS */
2156                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2157                                         val = rs->vassign [sregs [j]];
2158                                 }
2159
2160                                 if (val < 0) {
2161                                         int spill = 0;
2162                                         if (val < -1) {
2163                                                 /* the register gets spilled after this inst */
2164                                                 spill = -val -1;
2165                                         }
2166                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2167                                         assign_reg (cfg, rs, sregs [j], val, bank);
2168                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2169                                         if (spill) {
2170                                                 /*
2171                                                  * Need to insert before the instruction since it can
2172                                                  * overwrite sreg2.
2173                                                  */
2174                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2175                                         }
2176                                 }
2177                                 sregs [j] = val;
2178                                 for (k = j + 1; k < num_sregs; ++k)
2179                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2180                         }
2181                         else {
2182                                 prev_sregs [j] = -1;
2183                         }
2184                 }
2185                 mono_inst_set_src_registers (ins, sregs);
2186
2187                 /* Sanity check */
2188                 /* Do this only for CAS for now */
2189                 for (j = 1; j < num_sregs; ++j) {
2190                         int sreg = sregs [j];
2191                         int dest_sreg = dest_sregs [j];
2192
2193                         if (j == 2 && dest_sreg != -1) {
2194                                 int k;
2195
2196                                 g_assert (sreg == dest_sreg);
2197
2198                                 for (k = 0; k < num_sregs; ++k) {
2199                                         if (k != j)
2200                                                 g_assert (sregs [k] != dest_sreg);
2201                                 }
2202                         }
2203                 }
2204
2205                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2206                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2207                         mono_regstate_free_int (rs, ins->sreg1);
2208                 }
2209                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2210                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2211                         mono_regstate_free_int (rs, ins->sreg2);
2212                 }*/
2213
2214                 DEBUG (mono_print_ins_index (i, ins));
2215         }
2216
2217         // FIXME: Set MAX_FREGS to 8
2218         // FIXME: Optimize generated code
2219 #if MONO_ARCH_USE_FPSTACK
2220         /*
2221          * Make a forward pass over the code, simulating the fp stack, making sure the
2222          * arguments required by the fp opcodes are at the top of the stack.
2223          */
2224         if (has_fp) {
2225                 MonoInst *prev = NULL;
2226                 MonoInst *fxch;
2227                 int tmp;
2228
2229                 g_assert (num_sregs <= 2);
2230
2231                 for (ins = bb->code; ins; ins = ins->next) {
2232                         spec = ins_get_spec (ins->opcode);
2233
2234                         DEBUG (printf ("processing:"));
2235                         DEBUG (mono_print_ins_index (0, ins));
2236
2237                         if (ins->opcode == OP_FMOVE) {
2238                                 /* Do it by renaming the source to the destination on the stack */
2239                                 // FIXME: Is this correct ?
2240                                 for (i = 0; i < sp; ++i)
2241                                         if (fpstack [i] == ins->sreg1)
2242                                                 fpstack [i] = ins->dreg;
2243                                 prev = ins;
2244                                 continue;
2245                         }
2246
2247                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2248                                 /* Arg1 must be in %st(1) */
2249                                 g_assert (prev);
2250
2251                                 i = 0;
2252                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2253                                         i ++;
2254                                 g_assert (i < sp);
2255
2256                                 if (sp - 1 - i > 0) {
2257                                         /* First move it to %st(0) */
2258                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2259
2260                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2261                                         fxch->inst_imm = sp - 1 - i;
2262
2263                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2264                                         prev = fxch;
2265
2266                                         tmp = fpstack [sp - 1];
2267                                         fpstack [sp - 1] = fpstack [i];
2268                                         fpstack [i] = tmp;
2269                                 }
2270
2271                                 /* Then move it to %st(1) */
2272                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2273
2274                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2275                                 fxch->inst_imm = 1;
2276
2277                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2278                                 prev = fxch;
2279
2280                                 tmp = fpstack [sp - 1];
2281                                 fpstack [sp - 1] = fpstack [sp - 2];
2282                                 fpstack [sp - 2] = tmp;
2283                         }
2284
2285                         if (sreg2_is_fp (spec)) {
2286                                 g_assert (sp > 0);
2287
2288                                 if (fpstack [sp - 1] != ins->sreg2) {
2289                                         g_assert (prev);
2290
2291                                         i = 0;
2292                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2293                                                 i ++;
2294                                         g_assert (i < sp);
2295
2296                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2297
2298                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2299                                         fxch->inst_imm = sp - 1 - i;
2300
2301                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2302                                         prev = fxch;
2303
2304                                         tmp = fpstack [sp - 1];
2305                                         fpstack [sp - 1] = fpstack [i];
2306                                         fpstack [i] = tmp;
2307                                 }
2308
2309                                 sp --;
2310                         }
2311
2312                         if (sreg1_is_fp (spec)) {
2313                                 g_assert (sp > 0);
2314
2315                                 if (fpstack [sp - 1] != ins->sreg1) {
2316                                         g_assert (prev);
2317
2318                                         i = 0;
2319                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2320                                                 i ++;
2321                                         g_assert (i < sp);
2322
2323                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2324
2325                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2326                                         fxch->inst_imm = sp - 1 - i;
2327
2328                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2329                                         prev = fxch;
2330
2331                                         tmp = fpstack [sp - 1];
2332                                         fpstack [sp - 1] = fpstack [i];
2333                                         fpstack [i] = tmp;
2334                                 }
2335
2336                                 sp --;
2337                         }
2338
2339                         if (dreg_is_fp (spec)) {
2340                                 g_assert (sp < 8);
2341                                 fpstack [sp ++] = ins->dreg;
2342                         }
2343
2344                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2345                                 printf ("\t[");
2346                                 for (i = 0; i < sp; ++i)
2347                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2348                                 printf ("]\n");
2349                         }
2350
2351                         prev = ins;
2352                 }
2353
2354                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2355                         /* Remove remaining items from the fp stack */
2356                         /*
2357                          * These can remain for example as a result of a dead fmove like in
2358                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2359                          */
2360                         while (sp) {
2361                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2362                                 mono_add_ins_to_end (bb, ins);
2363                                 sp --;
2364                         }
2365                 }
2366         }
2367 #endif
2368 }
2369
2370 CompRelation
2371 mono_opcode_to_cond (int opcode)
2372 {
2373         switch (opcode) {
2374         case OP_CEQ:
2375         case OP_IBEQ:
2376         case OP_ICEQ:
2377         case OP_LBEQ:
2378         case OP_LCEQ:
2379         case OP_FBEQ:
2380         case OP_FCEQ:
2381         case OP_RBEQ:
2382         case OP_RCEQ:
2383         case OP_COND_EXC_EQ:
2384         case OP_COND_EXC_IEQ:
2385         case OP_CMOV_IEQ:
2386         case OP_CMOV_LEQ:
2387                 return CMP_EQ;
2388         case OP_FCNEQ:
2389         case OP_ICNEQ:
2390         case OP_IBNE_UN:
2391         case OP_LBNE_UN:
2392         case OP_FBNE_UN:
2393         case OP_COND_EXC_NE_UN:
2394         case OP_COND_EXC_INE_UN:
2395         case OP_CMOV_INE_UN:
2396         case OP_CMOV_LNE_UN:
2397                 return CMP_NE;
2398         case OP_FCLE:
2399         case OP_ICLE:
2400         case OP_IBLE:
2401         case OP_LBLE:
2402         case OP_FBLE:
2403         case OP_CMOV_ILE:
2404         case OP_CMOV_LLE:
2405                 return CMP_LE;
2406         case OP_FCGE:
2407         case OP_ICGE:
2408         case OP_IBGE:
2409         case OP_LBGE:
2410         case OP_FBGE:
2411         case OP_CMOV_IGE:
2412         case OP_CMOV_LGE:
2413                 return CMP_GE;
2414         case OP_CLT:
2415         case OP_IBLT:
2416         case OP_ICLT:
2417         case OP_LBLT:
2418         case OP_LCLT:
2419         case OP_FBLT:
2420         case OP_FCLT:
2421         case OP_RBLT:
2422         case OP_RCLT:
2423         case OP_COND_EXC_LT:
2424         case OP_COND_EXC_ILT:
2425         case OP_CMOV_ILT:
2426         case OP_CMOV_LLT:
2427                 return CMP_LT;
2428         case OP_CGT:
2429         case OP_IBGT:
2430         case OP_ICGT:
2431         case OP_LBGT:
2432         case OP_LCGT:
2433         case OP_FBGT:
2434         case OP_FCGT:
2435         case OP_RBGT:
2436         case OP_RCGT:
2437         case OP_COND_EXC_GT:
2438         case OP_COND_EXC_IGT:
2439         case OP_CMOV_IGT:
2440         case OP_CMOV_LGT:
2441                 return CMP_GT;
2442
2443         case OP_ICLE_UN:
2444         case OP_IBLE_UN:
2445         case OP_LBLE_UN:
2446         case OP_FBLE_UN:
2447         case OP_COND_EXC_LE_UN:
2448         case OP_COND_EXC_ILE_UN:
2449         case OP_CMOV_ILE_UN:
2450         case OP_CMOV_LLE_UN:
2451                 return CMP_LE_UN;
2452
2453         case OP_ICGE_UN:
2454         case OP_IBGE_UN:
2455         case OP_LBGE_UN:
2456         case OP_FBGE_UN:
2457         case OP_CMOV_IGE_UN:
2458         case OP_CMOV_LGE_UN:
2459                 return CMP_GE_UN;
2460         case OP_CLT_UN:
2461         case OP_IBLT_UN:
2462         case OP_ICLT_UN:
2463         case OP_LBLT_UN:
2464         case OP_LCLT_UN:
2465         case OP_FBLT_UN:
2466         case OP_FCLT_UN:
2467         case OP_RBLT_UN:
2468         case OP_RCLT_UN:
2469         case OP_COND_EXC_LT_UN:
2470         case OP_COND_EXC_ILT_UN:
2471         case OP_CMOV_ILT_UN:
2472         case OP_CMOV_LLT_UN:
2473                 return CMP_LT_UN;
2474         case OP_CGT_UN:
2475         case OP_IBGT_UN:
2476         case OP_ICGT_UN:
2477         case OP_LBGT_UN:
2478         case OP_LCGT_UN:
2479         case OP_FCGT_UN:
2480         case OP_FBGT_UN:
2481         case OP_RCGT_UN:
2482         case OP_RBGT_UN:
2483         case OP_COND_EXC_GT_UN:
2484         case OP_COND_EXC_IGT_UN:
2485         case OP_CMOV_IGT_UN:
2486         case OP_CMOV_LGT_UN:
2487                 return CMP_GT_UN;
2488         default:
2489                 printf ("%s\n", mono_inst_name (opcode));
2490                 g_assert_not_reached ();
2491                 return (CompRelation)0;
2492         }
2493 }
2494
2495 CompRelation
2496 mono_negate_cond (CompRelation cond)
2497 {
2498         switch (cond) {
2499         case CMP_EQ:
2500                 return CMP_NE;
2501         case CMP_NE:
2502                 return CMP_EQ;
2503         case CMP_LE:
2504                 return CMP_GT;
2505         case CMP_GE:
2506                 return CMP_LT;
2507         case CMP_LT:
2508                 return CMP_GE;
2509         case CMP_GT:
2510                 return CMP_LE;
2511         case CMP_LE_UN:
2512                 return CMP_GT_UN;
2513         case CMP_GE_UN:
2514                 return CMP_LT_UN;
2515         case CMP_LT_UN:
2516                 return CMP_GE_UN;
2517         case CMP_GT_UN:
2518                 return CMP_LE_UN;
2519         default:
2520                 g_assert_not_reached ();
2521         }
2522 }
2523
2524 CompType
2525 mono_opcode_to_type (int opcode, int cmp_opcode)
2526 {
2527         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2528                 return CMP_TYPE_L;
2529         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2530                 return CMP_TYPE_I;
2531         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2532                 return CMP_TYPE_I;
2533         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2534                 return CMP_TYPE_L;
2535         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2536                 return CMP_TYPE_L;
2537         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2538                 return CMP_TYPE_F;
2539         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2540                 return CMP_TYPE_F;
2541         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2542                 return CMP_TYPE_I;
2543         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2544                 switch (cmp_opcode) {
2545                 case OP_ICOMPARE:
2546                 case OP_ICOMPARE_IMM:
2547                         return CMP_TYPE_I;
2548                 default:
2549                         return CMP_TYPE_L;
2550                 }
2551         } else {
2552                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2553                 return (CompType)0;
2554         }
2555 }
2556
2557 #endif /* DISABLE_JIT */
2558
2559 gboolean
2560 mono_is_regsize_var (MonoType *t)
2561 {
2562         t = mini_get_underlying_type (t);
2563         switch (t->type) {
2564         case MONO_TYPE_I1:
2565         case MONO_TYPE_U1:
2566         case MONO_TYPE_I2:
2567         case MONO_TYPE_U2:
2568         case MONO_TYPE_I4:
2569         case MONO_TYPE_U4:
2570         case MONO_TYPE_I:
2571         case MONO_TYPE_U:
2572         case MONO_TYPE_PTR:
2573         case MONO_TYPE_FNPTR:
2574 #if SIZEOF_REGISTER == 8
2575         case MONO_TYPE_I8:
2576         case MONO_TYPE_U8:
2577 #endif
2578                 return TRUE;
2579         case MONO_TYPE_OBJECT:
2580         case MONO_TYPE_STRING:
2581         case MONO_TYPE_CLASS:
2582         case MONO_TYPE_SZARRAY:
2583         case MONO_TYPE_ARRAY:
2584                 return TRUE;
2585         case MONO_TYPE_GENERICINST:
2586                 if (!mono_type_generic_inst_is_valuetype (t))
2587                         return TRUE;
2588                 return FALSE;
2589         case MONO_TYPE_VALUETYPE:
2590                 return FALSE;
2591         default:
2592                 return FALSE;
2593         }
2594 }
2595
2596 #ifndef DISABLE_JIT
2597
2598 /*
2599  * mono_peephole_ins:
2600  *
2601  *   Perform some architecture independent peephole optimizations.
2602  */
2603 void
2604 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2605 {
2606         int filter = FILTER_IL_SEQ_POINT;
2607         MonoInst *last_ins = mono_inst_prev (ins, filter);
2608
2609         switch (ins->opcode) {
2610         case OP_MUL_IMM:
2611                 /* remove unnecessary multiplication with 1 */
2612                 if (ins->inst_imm == 1) {
2613                         if (ins->dreg != ins->sreg1)
2614                                 ins->opcode = OP_MOVE;
2615                         else
2616                                 MONO_DELETE_INS (bb, ins);
2617                 }
2618                 break;
2619         case OP_LOAD_MEMBASE:
2620         case OP_LOADI4_MEMBASE:
2621                 /*
2622                  * Note: if reg1 = reg2 the load op is removed
2623                  *
2624                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2625                  * OP_LOAD_MEMBASE offset(basereg), reg2
2626                  * -->
2627                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2628                  * OP_MOVE reg1, reg2
2629                  */
2630                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2631                         last_ins = mono_inst_prev (ins, filter);
2632                 if (last_ins &&
2633                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2634                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2635                         ins->inst_basereg == last_ins->inst_destbasereg &&
2636                         ins->inst_offset == last_ins->inst_offset) {
2637                         if (ins->dreg == last_ins->sreg1) {
2638                                 MONO_DELETE_INS (bb, ins);
2639                                 break;
2640                         } else {
2641                                 ins->opcode = OP_MOVE;
2642                                 ins->sreg1 = last_ins->sreg1;
2643                         }
2644
2645                         /*
2646                          * Note: reg1 must be different from the basereg in the second load
2647                          * Note: if reg1 = reg2 is equal then second load is removed
2648                          *
2649                          * OP_LOAD_MEMBASE offset(basereg), reg1
2650                          * OP_LOAD_MEMBASE offset(basereg), reg2
2651                          * -->
2652                          * OP_LOAD_MEMBASE offset(basereg), reg1
2653                          * OP_MOVE reg1, reg2
2654                          */
2655                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2656                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2657                           ins->inst_basereg != last_ins->dreg &&
2658                           ins->inst_basereg == last_ins->inst_basereg &&
2659                           ins->inst_offset == last_ins->inst_offset) {
2660
2661                         if (ins->dreg == last_ins->dreg) {
2662                                 MONO_DELETE_INS (bb, ins);
2663                         } else {
2664                                 ins->opcode = OP_MOVE;
2665                                 ins->sreg1 = last_ins->dreg;
2666                         }
2667
2668                         //g_assert_not_reached ();
2669
2670 #if 0
2671                         /*
2672                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2673                          * OP_LOAD_MEMBASE offset(basereg), reg
2674                          * -->
2675                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2676                          * OP_ICONST reg, imm
2677                          */
2678                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2679                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2680                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2681                                    ins->inst_offset == last_ins->inst_offset) {
2682                         ins->opcode = OP_ICONST;
2683                         ins->inst_c0 = last_ins->inst_imm;
2684                         g_assert_not_reached (); // check this rule
2685 #endif
2686                 }
2687                 break;
2688         case OP_LOADI1_MEMBASE:
2689         case OP_LOADU1_MEMBASE:
2690                 /*
2691                  * Note: if reg1 = reg2 the load op is removed
2692                  *
2693                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2694                  * OP_LOAD_MEMBASE offset(basereg), reg2
2695                  * -->
2696                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2697                  * OP_MOVE reg1, reg2
2698                  */
2699                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2700                         ins->inst_basereg == last_ins->inst_destbasereg &&
2701                         ins->inst_offset == last_ins->inst_offset) {
2702                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2703                         ins->sreg1 = last_ins->sreg1;
2704                 }
2705                 break;
2706         case OP_LOADI2_MEMBASE:
2707         case OP_LOADU2_MEMBASE:
2708                 /*
2709                  * Note: if reg1 = reg2 the load op is removed
2710                  *
2711                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2712                  * OP_LOAD_MEMBASE offset(basereg), reg2
2713                  * -->
2714                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2715                  * OP_MOVE reg1, reg2
2716                  */
2717                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2718                         ins->inst_basereg == last_ins->inst_destbasereg &&
2719                         ins->inst_offset == last_ins->inst_offset) {
2720 #if SIZEOF_REGISTER == 8
2721                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2722 #else
2723                         /* The definition of OP_PCONV_TO_U2 is wrong */
2724                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2725 #endif
2726                         ins->sreg1 = last_ins->sreg1;
2727                 }
2728                 break;
2729         case OP_MOVE:
2730         case OP_FMOVE:
2731                 /*
2732                  * Removes:
2733                  *
2734                  * OP_MOVE reg, reg
2735                  */
2736                 if (ins->dreg == ins->sreg1) {
2737                         MONO_DELETE_INS (bb, ins);
2738                         break;
2739                 }
2740                 /*
2741                  * Removes:
2742                  *
2743                  * OP_MOVE sreg, dreg
2744                  * OP_MOVE dreg, sreg
2745                  */
2746                 if (last_ins && last_ins->opcode == ins->opcode &&
2747                         ins->sreg1 == last_ins->dreg &&
2748                         ins->dreg == last_ins->sreg1) {
2749                         MONO_DELETE_INS (bb, ins);
2750                 }
2751                 break;
2752         case OP_NOP:
2753                 MONO_DELETE_INS (bb, ins);
2754                 break;
2755         }
2756 }
2757
2758 int
2759 mini_exception_id_by_name (const char *name)
2760 {
2761         if (strcmp (name, "IndexOutOfRangeException") == 0)
2762                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2763         if (strcmp (name, "OverflowException") == 0)
2764                 return MONO_EXC_OVERFLOW;
2765         if (strcmp (name, "ArithmeticException") == 0)
2766                 return MONO_EXC_ARITHMETIC;
2767         if (strcmp (name, "DivideByZeroException") == 0)
2768                 return MONO_EXC_DIVIDE_BY_ZERO;
2769         if (strcmp (name, "InvalidCastException") == 0)
2770                 return MONO_EXC_INVALID_CAST;
2771         if (strcmp (name, "NullReferenceException") == 0)
2772                 return MONO_EXC_NULL_REF;
2773         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2774                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2775         if (strcmp (name, "ArgumentException") == 0)
2776                 return MONO_EXC_ARGUMENT;
2777         g_error ("Unknown intrinsic exception %s\n", name);
2778         return -1;
2779 }
2780
2781 gboolean
2782 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2783 {
2784         MonoClass *klass;
2785         gpointer iter;
2786         MonoClassField *field;
2787         MonoType *ftype, *prev_ftype = NULL;
2788         int nfields = 0;
2789
2790         klass = mono_class_from_mono_type (t);
2791         iter = NULL;
2792         while ((field = mono_class_get_fields (klass, &iter))) {
2793                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2794                         continue;
2795                 ftype = mono_field_get_type (field);
2796                 ftype = mini_native_type_replace_type (ftype);
2797
2798                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2799                         int nested_nfields, nested_esize;
2800
2801                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2802                                 return FALSE;
2803                         if (nested_esize == 4)
2804                                 ftype = &mono_defaults.single_class->byval_arg;
2805                         else
2806                                 ftype = &mono_defaults.double_class->byval_arg;
2807                         if (prev_ftype && prev_ftype->type != ftype->type)
2808                                 return FALSE;
2809                         prev_ftype = ftype;
2810                         nfields += nested_nfields;
2811                 } else {
2812                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2813                                 return FALSE;
2814                         if (prev_ftype && prev_ftype->type != ftype->type)
2815                                 return FALSE;
2816                         prev_ftype = ftype;
2817                         nfields ++;
2818                 }
2819         }
2820         if (nfields == 0)
2821                 return FALSE;
2822         *out_nfields = nfields;
2823         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2824         return TRUE;
2825 }
2826
2827 MonoRegState*
2828 mono_regstate_new (void)
2829 {
2830         MonoRegState* rs = g_new0 (MonoRegState, 1);
2831
2832         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2833 #ifdef MONO_ARCH_NEED_SIMD_BANK
2834         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2835 #endif
2836
2837         return rs;
2838 }
2839
2840 void
2841 mono_regstate_free (MonoRegState *rs) {
2842         g_free (rs->vassign);
2843         g_free (rs);
2844 }
2845
2846 #endif /* DISABLE_JIT */