mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include "config.h"
   8 #ifndef DISABLE_JIT
   9
  10 #include <string.h>
  11 #include <math.h>
  12 #ifdef HAVE_UNISTD_H
  13 #include <unistd.h>
  14 #endif
  15
  16 #include <mono/metadata/appdomain.h>
  17 #include <mono/metadata/debug-helpers.h>
  18 #include <mono/metadata/threads.h>
  19 #include <mono/metadata/profiler-private.h>
  20 #include <mono/metadata/mempool-internals.h>
  21 #include <mono/utils/mono-math.h>
  22
  23 #include "mini.h"
  24 #include "trace.h"
  25 #include "mini-arch.h"
  26
  27 #ifndef MONO_MAX_XREGS
  28
  29 #define MONO_MAX_XREGS 0
  30 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  31 #define MONO_ARCH_CALLEE_XREGS 0
  32
  33 #endif
  34
  35 #define MONO_ARCH_BANK_MIRRORED -2
  36
  37 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  38
  39 #ifndef MONO_ARCH_NEED_SIMD_BANK
  40 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  41 #endif
  42
  43 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  44
  45 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  46
  47
  48 #else
  49
  50
  51 #define get_mirrored_bank(bank) (-1)
  52
  53 #define is_hreg_mirrored(rs, bank, hreg) (0)
  54
  55 #endif
  56
  57
  58 /* If the bank is mirrored return the true logical bank that the register in the
  59  * physical register bank is allocated to.
  60  */
  61 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  62         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  63 }
  64
  65 /*
  66  * Every hardware register belongs to a register type or register bank. bank 0
  67  * contains the int registers, bank 1 contains the fp registers.
  68  * int registers are used 99% of the time, so they are special cased in a lot of
  69  * places.
  70  */
  71
  72 static const int regbank_size [] = {
  73         MONO_MAX_IREGS,
  74         MONO_MAX_FREGS,
  75         MONO_MAX_IREGS,
  76         MONO_MAX_IREGS,
  77         MONO_MAX_XREGS
  78 };
  79
  80 static const int regbank_load_ops [] = {
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR8_MEMBASE,
  83         OP_LOADR_MEMBASE,
  84         OP_LOADR_MEMBASE,
  85         OP_LOADX_MEMBASE
  86 };
  87
  88 static const int regbank_store_ops [] = {
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER8_MEMBASE_REG,
  91         OP_STORER_MEMBASE_REG,
  92         OP_STORER_MEMBASE_REG,
  93         OP_STOREX_MEMBASE
  94 };
  95
  96 static const int regbank_move_ops [] = {
  97         OP_MOVE,
  98         OP_FMOVE,
  99         OP_MOVE,
 100         OP_MOVE,
 101         OP_XMOVE
 102 };
 103
 104 #define regmask(reg) (((regmask_t)1) << (reg))
 105
 106 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 107 static const regmask_t regbank_callee_saved_regs [] = {
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_FREGS,
 110         MONO_ARCH_CALLEE_SAVED_REGS,
 111         MONO_ARCH_CALLEE_SAVED_REGS,
 112         MONO_ARCH_CALLEE_SAVED_XREGS,
 113 };
 114 #endif
 115
 116 static const regmask_t regbank_callee_regs [] = {
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_FREGS,
 119         MONO_ARCH_CALLEE_REGS,
 120         MONO_ARCH_CALLEE_REGS,
 121         MONO_ARCH_CALLEE_XREGS,
 122 };
 123
 124 static const int regbank_spill_var_size[] = {
 125         sizeof (mgreg_t),
 126         sizeof (double),
 127         sizeof (mgreg_t),
 128         sizeof (mgreg_t),
 129         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 130 };
 131
 132 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 133
 134 static inline void
 135 mono_regstate_assign (MonoRegState *rs)
 136 {
 137 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 138         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 139          * if the values here are not the same.
 140          */
 141         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 142         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 143         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 144 #endif
 145
 146         if (rs->next_vreg > rs->vassign_size) {
 147                 g_free (rs->vassign);
 148                 rs->vassign_size = MAX (rs->next_vreg, 256);
 149                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 150         }
 151
 152         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 153         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 154
 155         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 156         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 157
 158 #ifdef MONO_ARCH_NEED_SIMD_BANK
 159         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 160         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 161 #endif
 162 }
 163
 164 static inline int
 165 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 166 {
 167         regmask_t mask = allow & rs->ifree_mask;
 168
 169 #if defined(__x86_64__) && defined(__GNUC__)
 170  {
 171         guint64 i;
 172
 173         if (mask == 0)
 174                 return -1;
 175
 176         __asm__("bsfq %1,%0\n\t"
 177                         : "=r" (i) : "rm" (mask));
 178
 179         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 180         return i;
 181  }
 182 #else
 183         int i;
 184
 185         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 186                 if (mask & ((regmask_t)1 << i)) {
 187                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 188                         return i;
 189                 }
 190         }
 191         return -1;
 192 #endif
 193 }
 194
 195 static inline void
 196 mono_regstate_free_int (MonoRegState *rs, int reg)
 197 {
 198         if (reg >= 0) {
 199                 rs->ifree_mask |= (regmask_t)1 << reg;
 200                 rs->isymbolic [reg] = 0;
 201         }
 202 }
 203
 204 static inline int
 205 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 206 {
 207         int i;
 208         int mirrored_bank;
 209         regmask_t mask = allow & rs->free_mask [bank];
 210         for (i = 0; i < regbank_size [bank]; ++i) {
 211                 if (mask & ((regmask_t)1 << i)) {
 212                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 213
 214                         mirrored_bank = get_mirrored_bank (bank);
 215                         if (mirrored_bank == -1)
 216                                 return i;
 217
 218                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 219                         return i;
 220                 }
 221         }
 222         return -1;
 223 }
 224
 225 static inline void
 226 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 227 {
 228         int mirrored_bank;
 229
 230         if (reg >= 0) {
 231                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 232                 rs->symbolic [bank][reg] = 0;
 233
 234                 mirrored_bank = get_mirrored_bank (bank);
 235                 if (mirrored_bank == -1)
 236                         return;
 237                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 238                 rs->symbolic [mirrored_bank][reg] = 0;
 239         }
 240 }
 241
 242 const char*
 243 mono_regname_full (int reg, int bank)
 244 {
 245         if (G_UNLIKELY (bank)) {
 246 #if MONO_ARCH_NEED_SIMD_BANK
 247                 if (bank == MONO_REG_SIMD)
 248                         return mono_arch_xregname (reg);
 249 #endif
 250                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 251                         return mono_arch_regname (reg);
 252                 g_assert (bank == MONO_REG_DOUBLE);
 253                 return mono_arch_fregname (reg);
 254         } else {
 255                 return mono_arch_regname (reg);
 256         }
 257 }
 258
 259 void
 260 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 261 {
 262         guint32 regpair;
 263
 264         regpair = (((guint32)hreg) << 24) + vreg;
 265         if (G_UNLIKELY (bank)) {
 266                 g_assert (vreg >= regbank_size [bank]);
 267                 g_assert (hreg < regbank_size [bank]);
 268                 call->used_fregs |= 1 << hreg;
 269                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 270         } else {
 271                 g_assert (vreg >= MONO_MAX_IREGS);
 272                 g_assert (hreg < MONO_MAX_IREGS);
 273                 call->used_iregs |= 1 << hreg;
 274                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 275         }
 276 }
 277
 278 /*
 279  * mono_call_inst_add_outarg_vt:
 280  *
 281  *   Register OUTARG_VT as belonging to CALL.
 282  */
 283 void
 284 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 285 {
 286         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 287 }
 288
 289 static void
 290 resize_spill_info (MonoCompile *cfg, int bank)
 291 {
 292         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 293         int orig_len = cfg->spill_info_len [bank];
 294         int new_len = orig_len ? orig_len * 2 : 16;
 295         MonoSpillInfo *new_info;
 296         int i;
 297
 298         g_assert (bank < MONO_NUM_REGBANKS);
 299
 300         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 301         if (orig_info)
 302                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 303         for (i = orig_len; i < new_len; ++i)
 304                 new_info [i].offset = -1;
 305
 306         cfg->spill_info [bank] = new_info;
 307         cfg->spill_info_len [bank] = new_len;
 308 }
 309
 310 /*
 311  * returns the offset used by spillvar. It allocates a new
 312  * spill variable if necessary.
 313  */
 314 static inline int
 315 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 316 {
 317         MonoSpillInfo *info;
 318         int size;
 319
 320         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 321                 while (spillvar >= cfg->spill_info_len [bank])
 322                         resize_spill_info (cfg, bank);
 323         }
 324
 325         /*
 326          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 327          */
 328         info = &cfg->spill_info [bank][spillvar];
 329         if (info->offset == -1) {
 330                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 331                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 332
 333                 g_assert (bank < MONO_NUM_REGBANKS);
 334                 if (G_UNLIKELY (bank))
 335                         size = regbank_spill_var_size [bank];
 336                 else
 337                         size = sizeof (mgreg_t);
 338
 339                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 340                         cfg->stack_offset += size - 1;
 341                         cfg->stack_offset &= ~(size - 1);
 342                         info->offset = cfg->stack_offset;
 343                         cfg->stack_offset += size;
 344                 } else {
 345                         cfg->stack_offset += size - 1;
 346                         cfg->stack_offset &= ~(size - 1);
 347                         cfg->stack_offset += size;
 348                         info->offset = - cfg->stack_offset;
 349                 }
 350         }
 351
 352         return info->offset;
 353 }
 354
 355 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 356 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 357 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 358 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 359 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 360 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 361
 362 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 363 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 364 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 365 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 366 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 367
 368 #ifndef MONO_ARCH_INST_IS_FLOAT
 369 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 370 #endif
 371
 372 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 373 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 374 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 375 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 376 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 377
 378 #define reg_is_simd(desc) ((desc) == 'x')
 379
 380 #ifdef MONO_ARCH_NEED_SIMD_BANK
 381
 382 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 383
 384 #else
 385
 386 #define reg_bank(desc) reg_is_fp ((desc))
 387
 388 #endif
 389
 390 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 391 #define sreg1_bank(spec) sreg_bank (0, (spec))
 392 #define sreg2_bank(spec) sreg_bank (1, (spec))
 393 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 394
 395 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 396 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 397 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 398 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 399
 400 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 401
 402 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 403 #undef is_global_ireg
 404 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 405 #endif
 406
 407 typedef struct {
 408         int born_in;
 409         int killed_in;
 410         /* Not (yet) used */
 411         //int last_use;
 412         //int prev_use;
 413         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 414 } RegTrack;
 415
 416 #if !defined(DISABLE_LOGGING)
 417
 418 void
 419 mono_print_ins_index (int i, MonoInst *ins)
 420 {
 421         GString *buf = mono_print_ins_index_strbuf (i, ins);
 422         printf ("%s\n", buf->str);
 423         g_string_free (buf, TRUE);
 424 }
 425
 426 GString *
 427 mono_print_ins_index_strbuf (int i, MonoInst *ins)
 428 {
 429         const char *spec = ins_get_spec (ins->opcode);
 430         GString *sbuf = g_string_new (NULL);
 431         int num_sregs, j;
 432         int sregs [MONO_MAX_SRC_REGS];
 433
 434         if (i != -1)
 435                 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
 436         else
 437                 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
 438         if (spec == MONO_ARCH_CPU_SPEC) {
 439                 gboolean dest_base = FALSE;
 440                 switch (ins->opcode) {
 441                 case OP_STOREV_MEMBASE:
 442                         dest_base = TRUE;
 443                         break;
 444                 default:
 445                         break;
 446                 }
 447
 448                 /* This is a lowered opcode */
 449                 if (ins->dreg != -1) {
 450                         if (dest_base)
 451                                 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 452                         else
 453                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 454                 }
 455                 if (ins->sreg1 != -1)
 456                         g_string_append_printf (sbuf, " R%d", ins->sreg1);
 457                 if (ins->sreg2 != -1)
 458                         g_string_append_printf (sbuf, " R%d", ins->sreg2);
 459                 if (ins->sreg3 != -1)
 460                         g_string_append_printf (sbuf, " R%d", ins->sreg3);
 461
 462                 switch (ins->opcode) {
 463                 case OP_LBNE_UN:
 464                 case OP_LBEQ:
 465                 case OP_LBLT:
 466                 case OP_LBLT_UN:
 467                 case OP_LBGT:
 468                 case OP_LBGT_UN:
 469                 case OP_LBGE:
 470                 case OP_LBGE_UN:
 471                 case OP_LBLE:
 472                 case OP_LBLE_UN:
 473                         if (!ins->inst_false_bb)
 474                                 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 475                         else
 476                                 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 477                         break;
 478                 case OP_PHI:
 479                 case OP_VPHI:
 480                 case OP_XPHI:
 481                 case OP_FPHI: {
 482                         int i;
 483                         g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
 484                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 485                                 if (i)
 486                                         g_string_append_printf (sbuf, ", ");
 487                                 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
 488                         }
 489                         g_string_append_printf (sbuf, ")]");
 490                         break;
 491                 }
 492                 case OP_LDADDR:
 493                 case OP_OUTARG_VTRETADDR:
 494                         g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
 495                         break;
 496                 case OP_REGOFFSET:
 497                 case OP_GSHAREDVT_ARG_REGOFFSET:
 498                         g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
 499                         break;
 500                 case OP_ISINST:
 501                 case OP_CASTCLASS:
 502                         g_string_append_printf (sbuf, " %s", ins->klass->name);
 503                         break;
 504                 default:
 505                         break;
 506                 }
 507
 508                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 509                 return sbuf;
 510         }
 511
 512         if (spec [MONO_INST_DEST]) {
 513                 int bank = dreg_bank (spec);
 514                 if (is_soft_reg (ins->dreg, bank)) {
 515                         if (spec [MONO_INST_DEST] == 'b') {
 516                                 if (ins->inst_offset == 0)
 517                                         g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
 518                                 else
 519                                         g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 520                         }
 521                         else
 522                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 523                 } else if (spec [MONO_INST_DEST] == 'b') {
 524                         if (ins->inst_offset == 0)
 525                                 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
 526                         else
 527                                 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 528                 } else
 529                         g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
 530         }
 531         if (spec [MONO_INST_SRC1]) {
 532                 int bank = sreg1_bank (spec);
 533                 if (is_soft_reg (ins->sreg1, bank)) {
 534                         if (spec [MONO_INST_SRC1] == 'b')
 535                                 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 536                         else
 537                                 g_string_append_printf (sbuf, " R%d", ins->sreg1);
 538                 } else if (spec [MONO_INST_SRC1] == 'b')
 539                         g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 540                 else
 541                         g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
 542         }
 543         num_sregs = mono_inst_get_src_registers (ins, sregs);
 544         for (j = 1; j < num_sregs; ++j) {
 545                 int bank = sreg_bank (j, spec);
 546                 if (is_soft_reg (sregs [j], bank))
 547                         g_string_append_printf (sbuf, " R%d", sregs [j]);
 548                 else
 549                         g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
 550         }
 551
 552         switch (ins->opcode) {
 553         case OP_ICONST:
 554                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
 555                 break;
 556 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 557         case OP_X86_PUSH_IMM:
 558 #endif
 559         case OP_ICOMPARE_IMM:
 560         case OP_COMPARE_IMM:
 561         case OP_IADD_IMM:
 562         case OP_ISUB_IMM:
 563         case OP_IAND_IMM:
 564         case OP_IOR_IMM:
 565         case OP_IXOR_IMM:
 566         case OP_SUB_IMM:
 567         case OP_STORE_MEMBASE_IMM:
 568                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
 569                 break;
 570         case OP_ADD_IMM:
 571         case OP_LADD_IMM:
 572                 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
 573                 break;
 574         case OP_I8CONST:
 575                 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
 576                 break;
 577         case OP_R8CONST:
 578                 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
 579                 break;
 580         case OP_R4CONST:
 581                 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
 582                 break;
 583         case OP_CALL:
 584         case OP_CALL_MEMBASE:
 585         case OP_CALL_REG:
 586         case OP_FCALL:
 587         case OP_LCALL:
 588         case OP_VCALL:
 589         case OP_VCALL_REG:
 590         case OP_VCALL_MEMBASE:
 591         case OP_VCALL2:
 592         case OP_VCALL2_REG:
 593         case OP_VCALL2_MEMBASE:
 594         case OP_VOIDCALL:
 595         case OP_VOIDCALL_MEMBASE:
 596         case OP_TAILCALL: {
 597                 MonoCallInst *call = (MonoCallInst*)ins;
 598                 GSList *list;
 599
 600                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 601                         /*
 602                          * These are lowered opcodes, but they are in the .md files since the old
 603                          * JIT passes them to backends.
 604                          */
 605                         if (ins->dreg != -1)
 606                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 607                 }
 608
 609                 if (call->method) {
 610                         char *full_name = mono_method_full_name (call->method, TRUE);
 611                         g_string_append_printf (sbuf, " [%s]", full_name);
 612                         g_free (full_name);
 613                 } else if (call->fptr_is_patch) {
 614                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 615
 616                         g_string_append_printf (sbuf, " ");
 617                         mono_print_ji (ji);
 618                 } else if (call->fptr) {
 619                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 620                         if (info)
 621                                 g_string_append_printf (sbuf, " [%s]", info->name);
 622                 }
 623
 624                 list = call->out_ireg_args;
 625                 while (list) {
 626                         guint32 regpair;
 627                         int reg, hreg;
 628
 629                         regpair = (guint32)(gssize)(list->data);
 630                         hreg = regpair >> 24;
 631                         reg = regpair & 0xffffff;
 632
 633                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
 634
 635                         list = g_slist_next (list);
 636                 }
 637                 list = call->out_freg_args;
 638                 while (list) {
 639                         guint32 regpair;
 640                         int reg, hreg;
 641
 642                         regpair = (guint32)(gssize)(list->data);
 643                         hreg = regpair >> 24;
 644                         reg = regpair & 0xffffff;
 645
 646                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
 647
 648                         list = g_slist_next (list);
 649                 }
 650                 break;
 651         }
 652         case OP_BR:
 653         case OP_CALL_HANDLER:
 654                 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
 655                 break;
 656         case OP_IBNE_UN:
 657         case OP_IBEQ:
 658         case OP_IBLT:
 659         case OP_IBLT_UN:
 660         case OP_IBGT:
 661         case OP_IBGT_UN:
 662         case OP_IBGE:
 663         case OP_IBGE_UN:
 664         case OP_IBLE:
 665         case OP_IBLE_UN:
 666         case OP_LBNE_UN:
 667         case OP_LBEQ:
 668         case OP_LBLT:
 669         case OP_LBLT_UN:
 670         case OP_LBGT:
 671         case OP_LBGT_UN:
 672         case OP_LBGE:
 673         case OP_LBGE_UN:
 674         case OP_LBLE:
 675         case OP_LBLE_UN:
 676                 if (!ins->inst_false_bb)
 677                         g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 678                 else
 679                         g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 680                 break;
 681         case OP_LIVERANGE_START:
 682         case OP_LIVERANGE_END:
 683         case OP_GC_LIVENESS_DEF:
 684         case OP_GC_LIVENESS_USE:
 685                 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
 686                 break;
 687         case OP_IL_SEQ_POINT:
 688         case OP_SEQ_POINT:
 689                 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 690                 break;
 691         case OP_COND_EXC_EQ:
 692         case OP_COND_EXC_GE:
 693         case OP_COND_EXC_GT:
 694         case OP_COND_EXC_LE:
 695         case OP_COND_EXC_LT:
 696         case OP_COND_EXC_NE_UN:
 697         case OP_COND_EXC_GE_UN:
 698         case OP_COND_EXC_GT_UN:
 699         case OP_COND_EXC_LE_UN:
 700         case OP_COND_EXC_LT_UN:
 701         case OP_COND_EXC_OV:
 702         case OP_COND_EXC_NO:
 703         case OP_COND_EXC_C:
 704         case OP_COND_EXC_NC:
 705         case OP_COND_EXC_IEQ:
 706         case OP_COND_EXC_IGE:
 707         case OP_COND_EXC_IGT:
 708         case OP_COND_EXC_ILE:
 709         case OP_COND_EXC_ILT:
 710         case OP_COND_EXC_INE_UN:
 711         case OP_COND_EXC_IGE_UN:
 712         case OP_COND_EXC_IGT_UN:
 713         case OP_COND_EXC_ILE_UN:
 714         case OP_COND_EXC_ILT_UN:
 715         case OP_COND_EXC_IOV:
 716         case OP_COND_EXC_INO:
 717         case OP_COND_EXC_IC:
 718         case OP_COND_EXC_INC:
 719                 g_string_append_printf (sbuf, " %s", ins->inst_p1);
 720                 break;
 721         default:
 722                 break;
 723         }
 724
 725         if (spec [MONO_INST_CLOB])
 726                 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
 727         return sbuf;
 728 }
 729
 730 static void
 731 print_regtrack (RegTrack *t, int num)
 732 {
 733         int i;
 734         char buf [32];
 735         const char *r;
 736
 737         for (i = 0; i < num; ++i) {
 738                 if (!t [i].born_in)
 739                         continue;
 740                 if (i >= MONO_MAX_IREGS) {
 741                         g_snprintf (buf, sizeof(buf), "R%d", i);
 742                         r = buf;
 743                 } else
 744                         r = mono_arch_regname (i);
 745                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 746         }
 747 }
 748 #else
 749
 750 void
 751 mono_print_ins_index (int i, MonoInst *ins)
 752 {
 753 }
 754 #endif /* !defined(DISABLE_LOGGING) */
 755
 756 void
 757 mono_print_ins (MonoInst *ins)
 758 {
 759         mono_print_ins_index (-1, ins);
 760 }
 761
 762 static inline void
 763 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 764 {
 765         /*
 766          * If this function is called multiple times, the new instructions are inserted
 767          * in the proper order.
 768          */
 769         mono_bblock_insert_before_ins (bb, ins, to_insert);
 770 }
 771
 772 static inline void
 773 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 774 {
 775         /*
 776          * If this function is called multiple times, the new instructions are inserted in
 777          * proper order.
 778          */
 779         mono_bblock_insert_after_ins (bb, *last, to_insert);
 780
 781         *last = to_insert;
 782 }
 783
 784 static inline int
 785 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 786 {
 787         if (vreg_is_ref (cfg, reg))
 788                 return MONO_REG_INT_REF;
 789         else if (vreg_is_mp (cfg, reg))
 790                 return MONO_REG_INT_MP;
 791         else
 792                 return bank;
 793 }
 794
 795 /*
 796  * Force the spilling of the variable in the symbolic register 'reg', and free
 797  * the hreg it was assigned to.
 798  */
 799 static void
 800 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 801 {
 802         MonoInst *load;
 803         int i, sel, spill;
 804         MonoRegState *rs = cfg->rs;
 805
 806         sel = rs->vassign [reg];
 807
 808         /* the vreg we need to spill lives in another logical reg bank */
 809         bank = translate_bank (cfg->rs, bank, sel);
 810
 811         /*i = rs->isymbolic [sel];
 812         g_assert (i == reg);*/
 813         i = reg;
 814         spill = ++cfg->spill_count;
 815         rs->vassign [i] = -spill - 1;
 816         if (G_UNLIKELY (bank))
 817                 mono_regstate_free_general (rs, sel, bank);
 818         else
 819                 mono_regstate_free_int (rs, sel);
 820         /* we need to create a spill var and insert a load to sel after the current instruction */
 821         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 822         load->dreg = sel;
 823         load->inst_basereg = cfg->frame_reg;
 824         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 825         insert_after_ins (bb, ins, last, load);
 826         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 827         if (G_UNLIKELY (bank))
 828                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 829         else
 830                 i = mono_regstate_alloc_int (rs, regmask (sel));
 831         g_assert (i == sel);
 832
 833         if (G_UNLIKELY (bank))
 834                 mono_regstate_free_general (rs, sel, bank);
 835         else
 836                 mono_regstate_free_int (rs, sel);
 837 }
 838
 839 static int
 840 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 841 {
 842         MonoInst *load;
 843         int i, sel, spill, num_sregs;
 844         int sregs [MONO_MAX_SRC_REGS];
 845         MonoRegState *rs = cfg->rs;
 846
 847         g_assert (bank < MONO_NUM_REGBANKS);
 848
 849         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 850         /* exclude the registers in the current instruction */
 851         num_sregs = mono_inst_get_src_registers (ins, sregs);
 852         for (i = 0; i < num_sregs; ++i) {
 853                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 854                         if (is_soft_reg (sregs [i], bank))
 855                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 856                         else
 857                                 regmask &= ~ (regmask (sregs [i]));
 858                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 859                 }
 860         }
 861         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 862                 regmask &= ~ (regmask (ins->dreg));
 863                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 864         }
 865
 866         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 867         g_assert (regmask); /* need at least a register we can free */
 868         sel = 0;
 869         /* we should track prev_use and spill the register that's farther */
 870         if (G_UNLIKELY (bank)) {
 871                 for (i = 0; i < regbank_size [bank]; ++i) {
 872                         if (regmask & (regmask (i))) {
 873                                 sel = i;
 874
 875                                 /* the vreg we need to load lives in another logical bank */
 876                                 bank = translate_bank (cfg->rs, bank, sel);
 877
 878                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 879                                 break;
 880                         }
 881                 }
 882
 883                 i = rs->symbolic [bank] [sel];
 884                 spill = ++cfg->spill_count;
 885                 rs->vassign [i] = -spill - 1;
 886                 mono_regstate_free_general (rs, sel, bank);
 887         }
 888         else {
 889                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 890                         if (regmask & (regmask (i))) {
 891                                 sel = i;
 892                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 893                                 break;
 894                         }
 895                 }
 896
 897                 i = rs->isymbolic [sel];
 898                 spill = ++cfg->spill_count;
 899                 rs->vassign [i] = -spill - 1;
 900                 mono_regstate_free_int (rs, sel);
 901         }
 902
 903         /* we need to create a spill var and insert a load to sel after the current instruction */
 904         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 905         load->dreg = sel;
 906         load->inst_basereg = cfg->frame_reg;
 907         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 908         insert_after_ins (bb, ins, last, load);
 909         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 910         if (G_UNLIKELY (bank))
 911                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 912         else
 913                 i = mono_regstate_alloc_int (rs, regmask (sel));
 914         g_assert (i == sel);
 915
 916         return sel;
 917 }
 918
 919 /*
 920  * free_up_hreg:
 921  *
 922  *   Free up the hreg HREG by spilling the vreg allocated to it.
 923  */
 924 static void
 925 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 926 {
 927         if (G_UNLIKELY (bank)) {
 928                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 929                         bank = translate_bank (cfg->rs, bank, hreg);
 930                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 931                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 932                 }
 933         }
 934         else {
 935                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 936                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 937                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 938                 }
 939         }
 940 }
 941
 942 static MonoInst*
 943 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 944 {
 945         MonoInst *copy;
 946
 947         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 948
 949         copy->dreg = dest;
 950         copy->sreg1 = src;
 951         copy->cil_code = ip;
 952         if (ins) {
 953                 mono_bblock_insert_after_ins (bb, ins, copy);
 954                 *last = copy;
 955         }
 956         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 957         return copy;
 958 }
 959
 960 static inline const char*
 961 regbank_to_string (int bank)
 962 {
 963         if (bank == MONO_REG_INT_REF)
 964                 return "REF ";
 965         else if (bank == MONO_REG_INT_MP)
 966                 return "MP ";
 967         else
 968                 return "";
 969 }
 970
 971 static void
 972 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 973 {
 974         MonoInst *store, *def;
 975
 976         bank = get_vreg_bank (cfg, prev_reg, bank);
 977
 978         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 979         store->sreg1 = reg;
 980         store->inst_destbasereg = cfg->frame_reg;
 981         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 982         if (ins) {
 983                 mono_bblock_insert_after_ins (bb, ins, store);
 984                 *last = store;
 985         } else if (insert_before) {
 986                 insert_before_ins (bb, insert_before, store);
 987         } else {
 988                 g_assert_not_reached ();
 989         }
 990         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 991
 992         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 993                 g_assert (prev_reg != -1);
 994                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 995                 def->inst_c0 = spill;
 996                 def->inst_c1 = bank;
 997                 mono_bblock_insert_after_ins (bb, store, def);
 998         }
 999 }
1000
1001 /* flags used in reginfo->flags */
1002 enum {
1003         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1004         MONO_FP_NEEDS_SPILL                     = regmask (1),
1005         MONO_FP_NEEDS_LOAD                      = regmask (2)
1006 };
1007
1008 static inline int
1009 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1010 {
1011         int val;
1012
1013         if (info && info->preferred_mask) {
1014                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1015                 if (val >= 0) {
1016                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1017                         return val;
1018                 }
1019         }
1020
1021         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1022         if (val < 0)
1023                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1024
1025         return val;
1026 }
1027
1028 static inline int
1029 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1030 {
1031         int val;
1032
1033         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1034
1035         if (val < 0)
1036                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1037
1038         return val;
1039 }
1040
1041 static inline int
1042 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1043 {
1044         if (G_UNLIKELY (bank))
1045                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1046         else
1047                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1048 }
1049
1050 static inline void
1051 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1052 {
1053         if (G_UNLIKELY (bank)) {
1054                 int mirrored_bank;
1055
1056                 g_assert (reg >= regbank_size [bank]);
1057                 g_assert (hreg < regbank_size [bank]);
1058                 g_assert (! is_global_freg (hreg));
1059
1060                 rs->vassign [reg] = hreg;
1061                 rs->symbolic [bank] [hreg] = reg;
1062                 rs->free_mask [bank] &= ~ (regmask (hreg));
1063
1064                 mirrored_bank = get_mirrored_bank (bank);
1065                 if (mirrored_bank == -1)
1066                         return;
1067
1068                 /* Make sure the other logical reg bank that this bank shares
1069                  * a single hard reg bank knows that this hard reg is not free.
1070                  */
1071                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1072
1073                 /* Mark the other logical bank that the this bank shares
1074                  * a single hard reg bank with as mirrored.
1075                  */
1076                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1077
1078         }
1079         else {
1080                 g_assert (reg >= MONO_MAX_IREGS);
1081                 g_assert (hreg < MONO_MAX_IREGS);
1082 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1083                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1084                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1085                 g_assert (! is_global_ireg (hreg));
1086 #endif
1087
1088                 rs->vassign [reg] = hreg;
1089                 rs->isymbolic [hreg] = reg;
1090                 rs->ifree_mask &= ~ (regmask (hreg));
1091         }
1092 }
1093
1094 static inline regmask_t
1095 get_callee_mask (const char spec)
1096 {
1097         if (G_UNLIKELY (reg_bank (spec)))
1098                 return regbank_callee_regs [reg_bank (spec)];
1099         return MONO_ARCH_CALLEE_REGS;
1100 }
1101
1102 static gint8 desc_to_fixed_reg [256];
1103 static gboolean desc_to_fixed_reg_inited = FALSE;
1104
1105 /*
1106  * Local register allocation.
1107  * We first scan the list of instructions and we save the liveness info of
1108  * each register (when the register is first used, when it's value is set etc.).
1109  * We also reverse the list of instructions because assigning registers backwards allows
1110  * for more tricks to be used.
1111  */
1112 void
1113 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1114 {
1115         MonoInst *ins, *prev, *last;
1116         MonoInst **tmp;
1117         MonoRegState *rs = cfg->rs;
1118         int i, j, val, max;
1119         RegTrack *reginfo;
1120         const char *spec;
1121         unsigned char spec_src1, spec_dest;
1122         int bank = 0;
1123 #if MONO_ARCH_USE_FPSTACK
1124         gboolean has_fp = FALSE;
1125         int fpstack [8];
1126         int sp = 0;
1127 #endif
1128         int num_sregs = 0;
1129         int sregs [MONO_MAX_SRC_REGS];
1130
1131         if (!bb->code)
1132                 return;
1133
1134         if (!desc_to_fixed_reg_inited) {
1135                 for (i = 0; i < 256; ++i)
1136                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1137                 desc_to_fixed_reg_inited = TRUE;
1138
1139                 /* Validate the cpu description against the info in mini-ops.h */
1140 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1141                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1142                         const char *ispec;
1143
1144                         spec = ins_get_spec (i);
1145                         ispec = INS_INFO (i);
1146
1147                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1148                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1149                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1150                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1151                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1152                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1153                 }
1154 #endif
1155         }
1156
1157         rs->next_vreg = bb->max_vreg;
1158         mono_regstate_assign (rs);
1159
1160         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1161         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1162                 rs->free_mask [i] = regbank_callee_regs [i];
1163
1164         max = rs->next_vreg;
1165
1166         if (cfg->reginfo && cfg->reginfo_len < max)
1167                 cfg->reginfo = NULL;
1168
1169         reginfo = (RegTrack *)cfg->reginfo;
1170         if (!reginfo) {
1171                 cfg->reginfo_len = MAX (1024, max * 2);
1172                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1173                 cfg->reginfo = reginfo;
1174         }
1175         else
1176                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1177
1178         if (cfg->verbose_level > 1) {
1179                 /* print_regtrack reads the info of all variables */
1180                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1181         }
1182
1183         /*
1184          * For large methods, next_vreg can be very large, so g_malloc0 time can
1185          * be prohibitive. So we manually init the reginfo entries used by the
1186          * bblock.
1187          */
1188         for (ins = bb->code; ins; ins = ins->next) {
1189                 gboolean modify = FALSE;
1190
1191                 spec = ins_get_spec (ins->opcode);
1192
1193                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1194                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1195 #if SIZEOF_REGISTER == 4
1196                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1197                                 /**
1198                                  * In the new IR, the two vregs of the regpair do not alias the
1199                                  * original long vreg. shift the vreg here so the rest of the
1200                                  * allocator doesn't have to care about it.
1201                                  */
1202                                 ins->dreg ++;
1203                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1204                         }
1205 #endif
1206                 }
1207
1208                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1209                 for (j = 0; j < num_sregs; ++j) {
1210                         g_assert (sregs [j] != -1);
1211                         if (sregs [j] < max) {
1212                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1213 #if SIZEOF_REGISTER == 4
1214                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1215                                         sregs [j]++;
1216                                         modify = TRUE;
1217                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1218                                 }
1219 #endif
1220                         }
1221                 }
1222                 if (modify)
1223                         mono_inst_set_src_registers (ins, sregs);
1224         }
1225
1226         /*if (cfg->opt & MONO_OPT_COPYPROP)
1227                 local_copy_prop (cfg, ins);*/
1228
1229         i = 1;
1230         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1231         /* forward pass on the instructions to collect register liveness info */
1232         MONO_BB_FOR_EACH_INS (bb, ins) {
1233                 spec = ins_get_spec (ins->opcode);
1234                 spec_dest = spec [MONO_INST_DEST];
1235
1236                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1237                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1238                 }
1239
1240                 DEBUG (mono_print_ins_index (i, ins));
1241
1242                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1243
1244 #if MONO_ARCH_USE_FPSTACK
1245                 if (dreg_is_fp (spec)) {
1246                         has_fp = TRUE;
1247                 } else {
1248                         for (j = 0; j < num_sregs; ++j) {
1249                                 if (sreg_is_fp (j, spec))
1250                                         has_fp = TRUE;
1251                         }
1252                 }
1253 #endif
1254
1255                 for (j = 0; j < num_sregs; ++j) {
1256                         int sreg = sregs [j];
1257                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1258                         if (sreg_spec) {
1259                                 bank = sreg_bank (j, spec);
1260                                 g_assert (sreg != -1);
1261                                 if (is_soft_reg (sreg, bank))
1262                                         /* This means the vreg is not local to this bb */
1263                                         g_assert (reginfo [sreg].born_in > 0);
1264                                 rs->vassign [sreg] = -1;
1265                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1266                                 //reginfo [ins->sreg2].last_use = i;
1267                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1268                                         /* The virtual register is allocated sequentially */
1269                                         rs->vassign [sreg + 1] = -1;
1270                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1271                                         //reginfo [ins->sreg2 + 1].last_use = i;
1272                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1273                                                 reginfo [sreg + 1].born_in = i;
1274                                 }
1275                         } else {
1276                                 sregs [j] = -1;
1277                         }
1278                 }
1279                 mono_inst_set_src_registers (ins, sregs);
1280
1281                 if (spec_dest) {
1282                         int dest_dreg;
1283
1284                         bank = dreg_bank (spec);
1285                         if (spec_dest != 'b') /* it's not just a base register */
1286                                 reginfo [ins->dreg].killed_in = i;
1287                         g_assert (ins->dreg != -1);
1288                         rs->vassign [ins->dreg] = -1;
1289                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1290                         //reginfo [ins->dreg].last_use = i;
1291                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1292                                 reginfo [ins->dreg].born_in = i;
1293
1294                         dest_dreg = desc_to_fixed_reg [spec_dest];
1295                         if (dest_dreg != -1)
1296                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1297
1298 #ifdef MONO_ARCH_INST_FIXED_MASK
1299                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1300 #endif
1301
1302                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1303                                 /* The virtual register is allocated sequentially */
1304                                 rs->vassign [ins->dreg + 1] = -1;
1305                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1306                                 //reginfo [ins->dreg + 1].last_use = i;
1307                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1308                                         reginfo [ins->dreg + 1].born_in = i;
1309                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1310                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1311                         }
1312                 } else {
1313                         ins->dreg = -1;
1314                 }
1315
1316                 ++i;
1317         }
1318
1319         tmp = &last;
1320
1321         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1322         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1323                 int prev_dreg;
1324                 int dest_dreg, clob_reg;
1325                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1326                 int dreg_high, sreg1_high;
1327                 regmask_t dreg_mask, mask;
1328                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1329                 regmask_t dreg_fixed_mask;
1330                 const unsigned char *ip;
1331                 --i;
1332                 spec = ins_get_spec (ins->opcode);
1333                 spec_src1 = spec [MONO_INST_SRC1];
1334                 spec_dest = spec [MONO_INST_DEST];
1335                 prev_dreg = -1;
1336                 clob_reg = -1;
1337                 dest_dreg = -1;
1338                 dreg_high = -1;
1339                 sreg1_high = -1;
1340                 dreg_mask = get_callee_mask (spec_dest);
1341                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1342                         prev_sregs [j] = -1;
1343                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1344                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1345 #ifdef MONO_ARCH_INST_FIXED_MASK
1346                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1347 #else
1348                         sreg_fixed_masks [j] = 0;
1349 #endif
1350                 }
1351
1352                 DEBUG (printf ("processing:"));
1353                 DEBUG (mono_print_ins_index (i, ins));
1354
1355                 ip = ins->cil_code;
1356
1357                 last = ins;
1358
1359                 /*
1360                  * FIXED REGS
1361                  */
1362                 dest_dreg = desc_to_fixed_reg [spec_dest];
1363                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1364                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1365
1366 #ifdef MONO_ARCH_INST_FIXED_MASK
1367                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1368 #else
1369                 dreg_fixed_mask = 0;
1370 #endif
1371
1372                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1373
1374                 /*
1375                  * TRACK FIXED SREG2, 3, ...
1376                  */
1377                 for (j = 1; j < num_sregs; ++j) {
1378                         int sreg = sregs [j];
1379                         int dest_sreg = dest_sregs [j];
1380
1381                         if (dest_sreg == -1)
1382                                 continue;
1383
1384                         if (j == 2) {
1385                                 int k;
1386
1387                                 /*
1388                                  * CAS.
1389                                  * We need to special case this, since on x86, there are only 3
1390                                  * free registers, and the code below assigns one of them to
1391                                  * sreg, so we can run out of registers when trying to assign
1392                                  * dreg. Instead, we just set up the register masks, and let the
1393                                  * normal sreg2 assignment code handle this. It would be nice to
1394                                  * do this for all the fixed reg cases too, but there is too much
1395                                  * risk of breakage.
1396                                  */
1397
1398                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1399                                 sreg_masks [j] = regmask (dest_sreg);
1400                                 for (k = 0; k < num_sregs; ++k) {
1401                                         if (k != j)
1402                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1403                                 }
1404
1405                                 /*
1406                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1407                                  */
1408                                 for (k = 0; k < num_sregs; ++k) {
1409                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1410                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1411                                 }
1412
1413                                 /*
1414                                  * We can also run out of registers while processing sreg2 if sreg3 is
1415                                  * assigned to another hreg, so spill sreg3 now.
1416                                  */
1417                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1418                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1419                                 }
1420                                 continue;
1421                         }
1422
1423                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1424                                 if (is_global_ireg (sreg)) {
1425                                         int k;
1426                                         /* Argument already in hard reg, need to copy */
1427                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1428                                         insert_before_ins (bb, ins, copy);
1429                                         for (k = 0; k < num_sregs; ++k) {
1430                                                 if (k != j)
1431                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1432                                         }
1433                                         /* See below */
1434                                         dreg_mask &= ~ (regmask (dest_sreg));
1435                                 } else {
1436                                         val = rs->vassign [sreg];
1437                                         if (val == -1) {
1438                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1439                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1440                                         } else if (val < -1) {
1441                                                 /* FIXME: */
1442                                                 g_assert_not_reached ();
1443                                         } else {
1444                                                 /* Argument already in hard reg, need to copy */
1445                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1446                                                 int k;
1447
1448                                                 insert_before_ins (bb, ins, copy);
1449                                                 for (k = 0; k < num_sregs; ++k) {
1450                                                         if (k != j)
1451                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1452                                                 }
1453                                                 /*
1454                                                  * Prevent the dreg from being allocated to dest_sreg
1455                                                  * too, since it could force sreg1 to be allocated to
1456                                                  * the same reg on x86.
1457                                                  */
1458                                                 dreg_mask &= ~ (regmask (dest_sreg));
1459                                         }
1460                                 }
1461                         } else {
1462                                 gboolean need_spill = TRUE;
1463                                 gboolean need_assign = TRUE;
1464                                 int k;
1465
1466                                 dreg_mask &= ~ (regmask (dest_sreg));
1467                                 for (k = 0; k < num_sregs; ++k) {
1468                                         if (k != j)
1469                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1470                                 }
1471
1472                                 /*
1473                                  * First check if dreg is assigned to dest_sreg2, since we
1474                                  * can't spill a dreg.
1475                                  */
1476                                 if (spec [MONO_INST_DEST])
1477                                         val = rs->vassign [ins->dreg];
1478                                 else
1479                                         val = -1;
1480                                 if (val == dest_sreg && ins->dreg != sreg) {
1481                                         /*
1482                                          * the destination register is already assigned to
1483                                          * dest_sreg2: we need to allocate another register for it
1484                                          * and then copy from this to dest_sreg2.
1485                                          */
1486                                         int new_dest;
1487                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1488                                         g_assert (new_dest >= 0);
1489                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1490
1491                                         prev_dreg = ins->dreg;
1492                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1493                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1494                                         mono_regstate_free_int (rs, dest_sreg);
1495                                         need_spill = FALSE;
1496                                 }
1497
1498                                 if (is_global_ireg (sreg)) {
1499                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1500                                         insert_before_ins (bb, ins, copy);
1501                                         need_assign = FALSE;
1502                                 }
1503                                 else {
1504                                         val = rs->vassign [sreg];
1505                                         if (val == dest_sreg) {
1506                                                 /* sreg2 is already assigned to the correct register */
1507                                                 need_spill = FALSE;
1508                                         } else if (val < -1) {
1509                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1510                                         } else if (val >= 0) {
1511                                                 /* sreg2 already assigned to another register */
1512                                                 /*
1513                                                  * We couldn't emit a copy from val to dest_sreg2, because
1514                                                  * val might be spilled later while processing this
1515                                                  * instruction. So we spill sreg2 so it can be allocated to
1516                                                  * dest_sreg2.
1517                                                  */
1518                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1519                                         }
1520                                 }
1521
1522                                 if (need_spill) {
1523                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1524                                 }
1525
1526                                 if (need_assign) {
1527                                         if (rs->vassign [sreg] < -1) {
1528                                                 int spill;
1529
1530                                                 /* Need to emit a spill store */
1531                                                 spill = - rs->vassign [sreg] - 1;
1532                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1533                                         }
1534                                         /* force-set sreg2 */
1535                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1536                                 }
1537                         }
1538                         sregs [j] = dest_sreg;
1539                 }
1540                 mono_inst_set_src_registers (ins, sregs);
1541
1542                 /*
1543                  * TRACK DREG
1544                  */
1545                 bank = dreg_bank (spec);
1546                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1547                         prev_dreg = ins->dreg;
1548                 }
1549
1550                 if (spec_dest == 'b') {
1551                         /*
1552                          * The dest reg is read by the instruction, not written, so
1553                          * avoid allocating sreg1/sreg2 to the same reg.
1554                          */
1555                         if (dest_sregs [0] != -1)
1556                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1557                         for (j = 1; j < num_sregs; ++j) {
1558                                 if (dest_sregs [j] != -1)
1559                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1560                         }
1561
1562                         val = rs->vassign [ins->dreg];
1563                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1564                                 /* DREG is already allocated to a register needed for sreg1 */
1565                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1566                         }
1567                 }
1568
1569                 /*
1570                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1571                  * various complex situations.
1572                  */
1573                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1574                         guint32 dreg2, dest_dreg2;
1575
1576                         g_assert (is_soft_reg (ins->dreg, bank));
1577
1578                         if (dest_dreg != -1) {
1579                                 if (rs->vassign [ins->dreg] != dest_dreg)
1580                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1581
1582                                 dreg2 = ins->dreg + 1;
1583                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1584                                 if (dest_dreg2 != -1) {
1585                                         if (rs->vassign [dreg2] != dest_dreg2)
1586                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1587                                 }
1588                         }
1589                 }
1590
1591                 if (dreg_fixed_mask) {
1592                         g_assert (!bank);
1593                         if (is_global_ireg (ins->dreg)) {
1594                                 /*
1595                                  * The argument is already in a hard reg, but that reg is
1596                                  * not usable by this instruction, so allocate a new one.
1597                                  */
1598                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1599                                 if (val < 0)
1600                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1601                                 mono_regstate_free_int (rs, val);
1602                                 dest_dreg = val;
1603
1604                                 /* Fall through */
1605                         }
1606                         else
1607                                 dreg_mask &= dreg_fixed_mask;
1608                 }
1609
1610                 if (is_soft_reg (ins->dreg, bank)) {
1611                         val = rs->vassign [ins->dreg];
1612
1613                         if (val < 0) {
1614                                 int spill = 0;
1615                                 if (val < -1) {
1616                                         /* the register gets spilled after this inst */
1617                                         spill = -val -1;
1618                                 }
1619                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1620                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1621                                 if (spill)
1622                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1623                         }
1624
1625                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1626                         ins->dreg = val;
1627                 }
1628
1629                 /* Handle regpairs */
1630                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1631                         int reg2 = prev_dreg + 1;
1632
1633                         g_assert (!bank);
1634                         g_assert (prev_dreg > -1);
1635                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1636                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1637 #ifdef TARGET_X86
1638                         /* bug #80489 */
1639                         mask &= ~regmask (X86_ECX);
1640 #endif
1641                         val = rs->vassign [reg2];
1642                         if (val < 0) {
1643                                 int spill = 0;
1644                                 if (val < -1) {
1645                                         /* the register gets spilled after this inst */
1646                                         spill = -val -1;
1647                                 }
1648                                 val = mono_regstate_alloc_int (rs, mask);
1649                                 if (val < 0)
1650                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1651                                 if (spill)
1652                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1653                         }
1654                         else {
1655                                 if (! (mask & (regmask (val)))) {
1656                                         val = mono_regstate_alloc_int (rs, mask);
1657                                         if (val < 0)
1658                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1659
1660                                         /* Reallocate hreg to the correct register */
1661                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1662
1663                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1664                                 }
1665                         }
1666
1667                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1668                         assign_reg (cfg, rs, reg2, val, bank);
1669
1670                         dreg_high = val;
1671                         ins->backend.reg3 = val;
1672
1673                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1674                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1675                                 mono_regstate_free_int (rs, val);
1676                         }
1677                 }
1678
1679                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1680                         /*
1681                          * In theory, we could free up the hreg even if the vreg is alive,
1682                          * but branches inside bblocks force us to assign the same hreg
1683                          * to a vreg every time it is encountered.
1684                          */
1685                         int dreg = rs->vassign [prev_dreg];
1686                         g_assert (dreg >= 0);
1687                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1688                         if (G_UNLIKELY (bank))
1689                                 mono_regstate_free_general (rs, dreg, bank);
1690                         else
1691                                 mono_regstate_free_int (rs, dreg);
1692                         rs->vassign [prev_dreg] = -1;
1693                 }
1694
1695                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1696                         /* this instruction only outputs to dest_dreg, need to copy */
1697                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1698                         ins->dreg = dest_dreg;
1699
1700                         if (G_UNLIKELY (bank)) {
1701                                 /* the register we need to free up may be used in another logical regbank
1702                                  * so do a translate just in case.
1703                                  */
1704                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1705                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1706                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1707                         }
1708                         else {
1709                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1710                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1711                         }
1712                 }
1713
1714                 if (spec_dest == 'b') {
1715                         /*
1716                          * The dest reg is read by the instruction, not written, so
1717                          * avoid allocating sreg1/sreg2 to the same reg.
1718                          */
1719                         for (j = 0; j < num_sregs; ++j)
1720                                 if (!sreg_bank (j, spec))
1721                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1722                 }
1723
1724                 /*
1725                  * TRACK CLOBBERING
1726                  */
1727                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1728                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1729                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1730                 }
1731
1732                 if (spec [MONO_INST_CLOB] == 'c') {
1733                         int j, s, dreg, dreg2, cur_bank;
1734                         guint64 clob_mask;
1735
1736                         clob_mask = MONO_ARCH_CALLEE_REGS;
1737
1738                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1739                                 /*
1740                                  * Need to avoid spilling the dreg since the dreg is not really
1741                                  * clobbered by the call.
1742                                  */
1743                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1744                                         dreg = rs->vassign [prev_dreg];
1745                                 else
1746                                         dreg = -1;
1747
1748                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1749                                         dreg2 = rs->vassign [prev_dreg + 1];
1750                                 else
1751                                         dreg2 = -1;
1752
1753                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1754                                         s = regmask (j);
1755                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1756                                                 if ((j != dreg) && (j != dreg2))
1757                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1758                                                 else if (rs->isymbolic [j])
1759                                                         /* The hreg is assigned to the dreg of this instruction */
1760                                                         rs->vassign [rs->isymbolic [j]] = -1;
1761                                                 mono_regstate_free_int (rs, j);
1762                                         }
1763                                 }
1764                         }
1765
1766                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1767                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1768                                         clob_mask = regbank_callee_regs [cur_bank];
1769                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1770                                                 dreg = rs->vassign [prev_dreg];
1771                                         else
1772                                                 dreg = -1;
1773
1774                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1775
1776                                                 /* we are looping though the banks in the outer loop
1777                                                  * so, we don't need to deal with mirrored hregs
1778                                                  * because we will get them in one of the other bank passes.
1779                                                  */
1780                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1781                                                         continue;
1782
1783                                                 s = regmask (j);
1784                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1785                                                         if (j != dreg)
1786                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1787                                                         else if (rs->symbolic [cur_bank] [j])
1788                                                                 /* The hreg is assigned to the dreg of this instruction */
1789                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1790                                                         mono_regstate_free_general (rs, j, cur_bank);
1791                                                 }
1792                                         }
1793                                 }
1794                         }
1795                 }
1796
1797                 /*
1798                  * TRACK ARGUMENT REGS
1799                  */
1800                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1801                         MonoCallInst *call = (MonoCallInst*)ins;
1802                         GSList *list;
1803
1804                         /*
1805                          * This needs to be done before assigning sreg1, so sreg1 will
1806                          * not be assigned one of the argument regs.
1807                          */
1808
1809                         /*
1810                          * Assign all registers in call->out_reg_args to the proper
1811                          * argument registers.
1812                          */
1813
1814                         list = call->out_ireg_args;
1815                         if (list) {
1816                                 while (list) {
1817                                         guint32 regpair;
1818                                         int reg, hreg;
1819
1820                                         regpair = (guint32)(gssize)(list->data);
1821                                         hreg = regpair >> 24;
1822                                         reg = regpair & 0xffffff;
1823
1824                                         assign_reg (cfg, rs, reg, hreg, 0);
1825
1826                                         sreg_masks [0] &= ~(regmask (hreg));
1827
1828                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1829
1830                                         list = g_slist_next (list);
1831                                 }
1832                         }
1833
1834                         list = call->out_freg_args;
1835                         if (list) {
1836                                 while (list) {
1837                                         guint32 regpair;
1838                                         int reg, hreg;
1839
1840                                         regpair = (guint32)(gssize)(list->data);
1841                                         hreg = regpair >> 24;
1842                                         reg = regpair & 0xffffff;
1843
1844                                         assign_reg (cfg, rs, reg, hreg, 1);
1845
1846                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1847
1848                                         list = g_slist_next (list);
1849                                 }
1850                         }
1851                 }
1852
1853                 /*
1854                  * TRACK SREG1
1855                  */
1856                 bank = sreg1_bank (spec);
1857                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1858                         int sreg1 = sregs [0];
1859                         int dest_sreg1 = dest_sregs [0];
1860
1861                         g_assert (is_soft_reg (sreg1, bank));
1862
1863                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1864                         if (dest_sreg1 != -1)
1865                                 g_assert (dest_sreg1 == ins->dreg);
1866                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1867                         g_assert (val >= 0);
1868
1869                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1870                                 // FIXME:
1871                                 g_assert_not_reached ();
1872
1873                         assign_reg (cfg, rs, sreg1, val, bank);
1874
1875                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1876
1877                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1878                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1879                         g_assert (val >= 0);
1880
1881                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1882                                 // FIXME:
1883                                 g_assert_not_reached ();
1884
1885                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1886
1887                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1888
1889                         /* Skip rest of this section */
1890                         dest_sregs [0] = -1;
1891                 }
1892
1893                 if (sreg_fixed_masks [0]) {
1894                         g_assert (!bank);
1895                         if (is_global_ireg (sregs [0])) {
1896                                 /*
1897                                  * The argument is already in a hard reg, but that reg is
1898                                  * not usable by this instruction, so allocate a new one.
1899                                  */
1900                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1901                                 if (val < 0)
1902                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1903                                 mono_regstate_free_int (rs, val);
1904                                 dest_sregs [0] = val;
1905
1906                                 /* Fall through to the dest_sreg1 != -1 case */
1907                         }
1908                         else
1909                                 sreg_masks [0] &= sreg_fixed_masks [0];
1910                 }
1911
1912                 if (dest_sregs [0] != -1) {
1913                         sreg_masks [0] = regmask (dest_sregs [0]);
1914
1915                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1916                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1917                         }
1918                         if (is_global_ireg (sregs [0])) {
1919                                 /* The argument is already in a hard reg, need to copy */
1920                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1921                                 insert_before_ins (bb, ins, copy);
1922                                 sregs [0] = dest_sregs [0];
1923                         }
1924                 }
1925
1926                 if (is_soft_reg (sregs [0], bank)) {
1927                         val = rs->vassign [sregs [0]];
1928                         prev_sregs [0] = sregs [0];
1929                         if (val < 0) {
1930                                 int spill = 0;
1931                                 if (val < -1) {
1932                                         /* the register gets spilled after this inst */
1933                                         spill = -val -1;
1934                                 }
1935
1936                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1937                                         /*
1938                                          * Allocate the same hreg to sreg1 as well so the
1939                                          * peephole can get rid of the move.
1940                                          */
1941                                         sreg_masks [0] = regmask (ins->dreg);
1942                                 }
1943
1944                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1945                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1946                                         sreg_masks [0] = regmask (ins->dreg);
1947
1948                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1949                                 assign_reg (cfg, rs, sregs [0], val, bank);
1950                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1951
1952                                 if (spill) {
1953                                         /*
1954                                          * Need to insert before the instruction since it can
1955                                          * overwrite sreg1.
1956                                          */
1957                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1958                                 }
1959                         }
1960                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1961                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1962                                 insert_before_ins (bb, ins, copy);
1963                                 for (j = 1; j < num_sregs; ++j)
1964                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1965                                 val = dest_sregs [0];
1966                         }
1967
1968                         sregs [0] = val;
1969                 }
1970                 else {
1971                         prev_sregs [0] = -1;
1972                 }
1973                 mono_inst_set_src_registers (ins, sregs);
1974
1975                 for (j = 1; j < num_sregs; ++j)
1976                         sreg_masks [j] &= ~(regmask (sregs [0]));
1977
1978                 /* Handle the case when sreg1 is a regpair but dreg is not */
1979                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1980                         int reg2 = prev_sregs [0] + 1;
1981
1982                         g_assert (!bank);
1983                         g_assert (prev_sregs [0] > -1);
1984                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1985                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1986                         val = rs->vassign [reg2];
1987                         if (val < 0) {
1988                                 int spill = 0;
1989                                 if (val < -1) {
1990                                         /* the register gets spilled after this inst */
1991                                         spill = -val -1;
1992                                 }
1993                                 val = mono_regstate_alloc_int (rs, mask);
1994                                 if (val < 0)
1995                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1996                                 if (spill)
1997                                         g_assert_not_reached ();
1998                         }
1999                         else {
2000                                 if (! (mask & (regmask (val)))) {
2001                                         /* The vreg is already allocated to a wrong hreg */
2002                                         /* FIXME: */
2003                                         g_assert_not_reached ();
2004 #if 0
2005                                         val = mono_regstate_alloc_int (rs, mask);
2006                                         if (val < 0)
2007                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2008
2009                                         /* Reallocate hreg to the correct register */
2010                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2011
2012                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2013 #endif
2014                                 }
2015                         }
2016
2017                         sreg1_high = val;
2018                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2019                         assign_reg (cfg, rs, reg2, val, bank);
2020                 }
2021
2022                 /* Handle dreg==sreg1 */
2023                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2024                         MonoInst *sreg2_copy = NULL;
2025                         MonoInst *copy;
2026                         int bank = reg_bank (spec_src1);
2027
2028                         if (ins->dreg == sregs [1]) {
2029                                 /*
2030                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2031                                  * register for it.
2032                                  */
2033                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2034
2035                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2036                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2037                                 prev_sregs [1] = sregs [1] = reg2;
2038
2039                                 if (G_UNLIKELY (bank))
2040                                         mono_regstate_free_general (rs, reg2, bank);
2041                                 else
2042                                         mono_regstate_free_int (rs, reg2);
2043                         }
2044
2045                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2046                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2047                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2048                                         /* FIXME: */
2049                                         g_assert_not_reached ();
2050
2051                                 /*
2052                                  * sreg1 and dest are already allocated to the same regpair by the
2053                                  * SREG1 allocation code.
2054                                  */
2055                                 g_assert (sregs [0] == ins->dreg);
2056                                 g_assert (dreg_high == sreg1_high);
2057                         }
2058
2059                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2060                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2061                         insert_before_ins (bb, ins, copy);
2062
2063                         if (sreg2_copy)
2064                                 insert_before_ins (bb, copy, sreg2_copy);
2065
2066                         /*
2067                          * Need to prevent sreg2 to be allocated to sreg1, since that
2068                          * would screw up the previous copy.
2069                          */
2070                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2071                         /* we set sreg1 to dest as well */
2072                         prev_sregs [0] = sregs [0] = ins->dreg;
2073                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2074                 }
2075                 mono_inst_set_src_registers (ins, sregs);
2076
2077                 /*
2078                  * TRACK SREG2, 3, ...
2079                  */
2080                 for (j = 1; j < num_sregs; ++j) {
2081                         int k;
2082
2083                         bank = sreg_bank (j, spec);
2084                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2085                                 g_assert_not_reached ();
2086
2087                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2088                                 /*
2089                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2090                                  * allocating it to the fixed reg.
2091                                  */
2092                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2093                                 insert_before_ins (bb, ins, copy);
2094                                 sregs [j] = dest_sregs [j];
2095                         } else if (is_soft_reg (sregs [j], bank)) {
2096                                 val = rs->vassign [sregs [j]];
2097
2098                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2099                                         /*
2100                                          * The sreg is already allocated to a hreg, but not to the fixed
2101                                          * reg required by the instruction. Spill the sreg, so it can be
2102                                          * allocated to the fixed reg by the code below.
2103                                          */
2104                                         /* Currently, this code should only be hit for CAS */
2105                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2106                                         val = rs->vassign [sregs [j]];
2107                                 }
2108
2109                                 if (val < 0) {
2110                                         int spill = 0;
2111                                         if (val < -1) {
2112                                                 /* the register gets spilled after this inst */
2113                                                 spill = -val -1;
2114                                         }
2115                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2116                                         assign_reg (cfg, rs, sregs [j], val, bank);
2117                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2118                                         if (spill) {
2119                                                 /*
2120                                                  * Need to insert before the instruction since it can
2121                                                  * overwrite sreg2.
2122                                                  */
2123                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2124                                         }
2125                                 }
2126                                 sregs [j] = val;
2127                                 for (k = j + 1; k < num_sregs; ++k)
2128                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2129                         }
2130                         else {
2131                                 prev_sregs [j] = -1;
2132                         }
2133                 }
2134                 mono_inst_set_src_registers (ins, sregs);
2135
2136                 /* Sanity check */
2137                 /* Do this only for CAS for now */
2138                 for (j = 1; j < num_sregs; ++j) {
2139                         int sreg = sregs [j];
2140                         int dest_sreg = dest_sregs [j];
2141
2142                         if (j == 2 && dest_sreg != -1) {
2143                                 int k;
2144
2145                                 g_assert (sreg == dest_sreg);
2146
2147                                 for (k = 0; k < num_sregs; ++k) {
2148                                         if (k != j)
2149                                                 g_assert (sregs [k] != dest_sreg);
2150                                 }
2151                         }
2152                 }
2153
2154                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2155                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2156                         mono_regstate_free_int (rs, ins->sreg1);
2157                 }
2158                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2159                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2160                         mono_regstate_free_int (rs, ins->sreg2);
2161                 }*/
2162
2163                 DEBUG (mono_print_ins_index (i, ins));
2164         }
2165
2166         // FIXME: Set MAX_FREGS to 8
2167         // FIXME: Optimize generated code
2168 #if MONO_ARCH_USE_FPSTACK
2169         /*
2170          * Make a forward pass over the code, simulating the fp stack, making sure the
2171          * arguments required by the fp opcodes are at the top of the stack.
2172          */
2173         if (has_fp) {
2174                 MonoInst *prev = NULL;
2175                 MonoInst *fxch;
2176                 int tmp;
2177
2178                 g_assert (num_sregs <= 2);
2179
2180                 for (ins = bb->code; ins; ins = ins->next) {
2181                         spec = ins_get_spec (ins->opcode);
2182
2183                         DEBUG (printf ("processing:"));
2184                         DEBUG (mono_print_ins_index (0, ins));
2185
2186                         if (ins->opcode == OP_FMOVE) {
2187                                 /* Do it by renaming the source to the destination on the stack */
2188                                 // FIXME: Is this correct ?
2189                                 for (i = 0; i < sp; ++i)
2190                                         if (fpstack [i] == ins->sreg1)
2191                                                 fpstack [i] = ins->dreg;
2192                                 prev = ins;
2193                                 continue;
2194                         }
2195
2196                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2197                                 /* Arg1 must be in %st(1) */
2198                                 g_assert (prev);
2199
2200                                 i = 0;
2201                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2202                                         i ++;
2203                                 g_assert (i < sp);
2204
2205                                 if (sp - 1 - i > 0) {
2206                                         /* First move it to %st(0) */
2207                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2208
2209                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2210                                         fxch->inst_imm = sp - 1 - i;
2211
2212                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2213                                         prev = fxch;
2214
2215                                         tmp = fpstack [sp - 1];
2216                                         fpstack [sp - 1] = fpstack [i];
2217                                         fpstack [i] = tmp;
2218                                 }
2219
2220                                 /* Then move it to %st(1) */
2221                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2222
2223                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2224                                 fxch->inst_imm = 1;
2225
2226                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2227                                 prev = fxch;
2228
2229                                 tmp = fpstack [sp - 1];
2230                                 fpstack [sp - 1] = fpstack [sp - 2];
2231                                 fpstack [sp - 2] = tmp;
2232                         }
2233
2234                         if (sreg2_is_fp (spec)) {
2235                                 g_assert (sp > 0);
2236
2237                                 if (fpstack [sp - 1] != ins->sreg2) {
2238                                         g_assert (prev);
2239
2240                                         i = 0;
2241                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2242                                                 i ++;
2243                                         g_assert (i < sp);
2244
2245                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2246
2247                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2248                                         fxch->inst_imm = sp - 1 - i;
2249
2250                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2251                                         prev = fxch;
2252
2253                                         tmp = fpstack [sp - 1];
2254                                         fpstack [sp - 1] = fpstack [i];
2255                                         fpstack [i] = tmp;
2256                                 }
2257
2258                                 sp --;
2259                         }
2260
2261                         if (sreg1_is_fp (spec)) {
2262                                 g_assert (sp > 0);
2263
2264                                 if (fpstack [sp - 1] != ins->sreg1) {
2265                                         g_assert (prev);
2266
2267                                         i = 0;
2268                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2269                                                 i ++;
2270                                         g_assert (i < sp);
2271
2272                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2273
2274                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2275                                         fxch->inst_imm = sp - 1 - i;
2276
2277                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2278                                         prev = fxch;
2279
2280                                         tmp = fpstack [sp - 1];
2281                                         fpstack [sp - 1] = fpstack [i];
2282                                         fpstack [i] = tmp;
2283                                 }
2284
2285                                 sp --;
2286                         }
2287
2288                         if (dreg_is_fp (spec)) {
2289                                 g_assert (sp < 8);
2290                                 fpstack [sp ++] = ins->dreg;
2291                         }
2292
2293                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2294                                 printf ("\t[");
2295                                 for (i = 0; i < sp; ++i)
2296                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2297                                 printf ("]\n");
2298                         }
2299
2300                         prev = ins;
2301                 }
2302
2303                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2304                         /* Remove remaining items from the fp stack */
2305                         /*
2306                          * These can remain for example as a result of a dead fmove like in
2307                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2308                          */
2309                         while (sp) {
2310                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2311                                 mono_add_ins_to_end (bb, ins);
2312                                 sp --;
2313                         }
2314                 }
2315         }
2316 #endif
2317 }
2318
2319 CompRelation
2320 mono_opcode_to_cond (int opcode)
2321 {
2322         switch (opcode) {
2323         case OP_CEQ:
2324         case OP_IBEQ:
2325         case OP_ICEQ:
2326         case OP_LBEQ:
2327         case OP_LCEQ:
2328         case OP_FBEQ:
2329         case OP_FCEQ:
2330         case OP_RBEQ:
2331         case OP_RCEQ:
2332         case OP_COND_EXC_EQ:
2333         case OP_COND_EXC_IEQ:
2334         case OP_CMOV_IEQ:
2335         case OP_CMOV_LEQ:
2336                 return CMP_EQ;
2337         case OP_FCNEQ:
2338         case OP_ICNEQ:
2339         case OP_IBNE_UN:
2340         case OP_LBNE_UN:
2341         case OP_FBNE_UN:
2342         case OP_COND_EXC_NE_UN:
2343         case OP_COND_EXC_INE_UN:
2344         case OP_CMOV_INE_UN:
2345         case OP_CMOV_LNE_UN:
2346                 return CMP_NE;
2347         case OP_FCLE:
2348         case OP_ICLE:
2349         case OP_IBLE:
2350         case OP_LBLE:
2351         case OP_FBLE:
2352         case OP_CMOV_ILE:
2353         case OP_CMOV_LLE:
2354                 return CMP_LE;
2355         case OP_FCGE:
2356         case OP_ICGE:
2357         case OP_IBGE:
2358         case OP_LBGE:
2359         case OP_FBGE:
2360         case OP_CMOV_IGE:
2361         case OP_CMOV_LGE:
2362                 return CMP_GE;
2363         case OP_CLT:
2364         case OP_IBLT:
2365         case OP_ICLT:
2366         case OP_LBLT:
2367         case OP_LCLT:
2368         case OP_FBLT:
2369         case OP_FCLT:
2370         case OP_RBLT:
2371         case OP_RCLT:
2372         case OP_COND_EXC_LT:
2373         case OP_COND_EXC_ILT:
2374         case OP_CMOV_ILT:
2375         case OP_CMOV_LLT:
2376                 return CMP_LT;
2377         case OP_CGT:
2378         case OP_IBGT:
2379         case OP_ICGT:
2380         case OP_LBGT:
2381         case OP_LCGT:
2382         case OP_FBGT:
2383         case OP_FCGT:
2384         case OP_RBGT:
2385         case OP_RCGT:
2386         case OP_COND_EXC_GT:
2387         case OP_COND_EXC_IGT:
2388         case OP_CMOV_IGT:
2389         case OP_CMOV_LGT:
2390                 return CMP_GT;
2391
2392         case OP_ICLE_UN:
2393         case OP_IBLE_UN:
2394         case OP_LBLE_UN:
2395         case OP_FBLE_UN:
2396         case OP_COND_EXC_LE_UN:
2397         case OP_COND_EXC_ILE_UN:
2398         case OP_CMOV_ILE_UN:
2399         case OP_CMOV_LLE_UN:
2400                 return CMP_LE_UN;
2401
2402         case OP_ICGE_UN:
2403         case OP_IBGE_UN:
2404         case OP_LBGE_UN:
2405         case OP_FBGE_UN:
2406         case OP_CMOV_IGE_UN:
2407         case OP_CMOV_LGE_UN:
2408                 return CMP_GE_UN;
2409         case OP_CLT_UN:
2410         case OP_IBLT_UN:
2411         case OP_ICLT_UN:
2412         case OP_LBLT_UN:
2413         case OP_LCLT_UN:
2414         case OP_FBLT_UN:
2415         case OP_FCLT_UN:
2416         case OP_RBLT_UN:
2417         case OP_RCLT_UN:
2418         case OP_COND_EXC_LT_UN:
2419         case OP_COND_EXC_ILT_UN:
2420         case OP_CMOV_ILT_UN:
2421         case OP_CMOV_LLT_UN:
2422                 return CMP_LT_UN;
2423         case OP_CGT_UN:
2424         case OP_IBGT_UN:
2425         case OP_ICGT_UN:
2426         case OP_LBGT_UN:
2427         case OP_LCGT_UN:
2428         case OP_FCGT_UN:
2429         case OP_FBGT_UN:
2430         case OP_RCGT_UN:
2431         case OP_RBGT_UN:
2432         case OP_COND_EXC_GT_UN:
2433         case OP_COND_EXC_IGT_UN:
2434         case OP_CMOV_IGT_UN:
2435         case OP_CMOV_LGT_UN:
2436                 return CMP_GT_UN;
2437         default:
2438                 printf ("%s\n", mono_inst_name (opcode));
2439                 g_assert_not_reached ();
2440                 return (CompRelation)0;
2441         }
2442 }
2443
2444 CompRelation
2445 mono_negate_cond (CompRelation cond)
2446 {
2447         switch (cond) {
2448         case CMP_EQ:
2449                 return CMP_NE;
2450         case CMP_NE:
2451                 return CMP_EQ;
2452         case CMP_LE:
2453                 return CMP_GT;
2454         case CMP_GE:
2455                 return CMP_LT;
2456         case CMP_LT:
2457                 return CMP_GE;
2458         case CMP_GT:
2459                 return CMP_LE;
2460         case CMP_LE_UN:
2461                 return CMP_GT_UN;
2462         case CMP_GE_UN:
2463                 return CMP_LT_UN;
2464         case CMP_LT_UN:
2465                 return CMP_GE_UN;
2466         case CMP_GT_UN:
2467                 return CMP_LE_UN;
2468         default:
2469                 g_assert_not_reached ();
2470         }
2471 }
2472
2473 CompType
2474 mono_opcode_to_type (int opcode, int cmp_opcode)
2475 {
2476         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2477                 return CMP_TYPE_L;
2478         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2479                 return CMP_TYPE_I;
2480         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2481                 return CMP_TYPE_I;
2482         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2483                 return CMP_TYPE_L;
2484         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2485                 return CMP_TYPE_L;
2486         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2487                 return CMP_TYPE_F;
2488         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2489                 return CMP_TYPE_F;
2490         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2491                 return CMP_TYPE_I;
2492         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2493                 switch (cmp_opcode) {
2494                 case OP_ICOMPARE:
2495                 case OP_ICOMPARE_IMM:
2496                         return CMP_TYPE_I;
2497                 default:
2498                         return CMP_TYPE_L;
2499                 }
2500         } else {
2501                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2502                 return (CompType)0;
2503         }
2504 }
2505
2506 #endif /* DISABLE_JIT */
2507
2508 gboolean
2509 mono_is_regsize_var (MonoType *t)
2510 {
2511         t = mini_get_underlying_type (t);
2512         switch (t->type) {
2513         case MONO_TYPE_I1:
2514         case MONO_TYPE_U1:
2515         case MONO_TYPE_I2:
2516         case MONO_TYPE_U2:
2517         case MONO_TYPE_I4:
2518         case MONO_TYPE_U4:
2519         case MONO_TYPE_I:
2520         case MONO_TYPE_U:
2521         case MONO_TYPE_PTR:
2522         case MONO_TYPE_FNPTR:
2523 #if SIZEOF_REGISTER == 8
2524         case MONO_TYPE_I8:
2525         case MONO_TYPE_U8:
2526 #endif
2527                 return TRUE;
2528         case MONO_TYPE_OBJECT:
2529         case MONO_TYPE_STRING:
2530         case MONO_TYPE_CLASS:
2531         case MONO_TYPE_SZARRAY:
2532         case MONO_TYPE_ARRAY:
2533                 return TRUE;
2534         case MONO_TYPE_GENERICINST:
2535                 if (!mono_type_generic_inst_is_valuetype (t))
2536                         return TRUE;
2537                 return FALSE;
2538         case MONO_TYPE_VALUETYPE:
2539                 return FALSE;
2540         default:
2541                 return FALSE;
2542         }
2543 }
2544
2545 #ifndef DISABLE_JIT
2546
2547 /*
2548  * mono_peephole_ins:
2549  *
2550  *   Perform some architecture independent peephole optimizations.
2551  */
2552 void
2553 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2554 {
2555         int filter = FILTER_IL_SEQ_POINT;
2556         MonoInst *last_ins = mono_inst_prev (ins, filter);
2557
2558         switch (ins->opcode) {
2559         case OP_MUL_IMM:
2560                 /* remove unnecessary multiplication with 1 */
2561                 if (ins->inst_imm == 1) {
2562                         if (ins->dreg != ins->sreg1)
2563                                 ins->opcode = OP_MOVE;
2564                         else
2565                                 MONO_DELETE_INS (bb, ins);
2566                 }
2567                 break;
2568         case OP_LOAD_MEMBASE:
2569         case OP_LOADI4_MEMBASE:
2570                 /*
2571                  * Note: if reg1 = reg2 the load op is removed
2572                  *
2573                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2574                  * OP_LOAD_MEMBASE offset(basereg), reg2
2575                  * -->
2576                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2577                  * OP_MOVE reg1, reg2
2578                  */
2579                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2580                         last_ins = mono_inst_prev (ins, filter);
2581                 if (last_ins &&
2582                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2583                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2584                         ins->inst_basereg == last_ins->inst_destbasereg &&
2585                         ins->inst_offset == last_ins->inst_offset) {
2586                         if (ins->dreg == last_ins->sreg1) {
2587                                 MONO_DELETE_INS (bb, ins);
2588                                 break;
2589                         } else {
2590                                 ins->opcode = OP_MOVE;
2591                                 ins->sreg1 = last_ins->sreg1;
2592                         }
2593
2594                         /*
2595                          * Note: reg1 must be different from the basereg in the second load
2596                          * Note: if reg1 = reg2 is equal then second load is removed
2597                          *
2598                          * OP_LOAD_MEMBASE offset(basereg), reg1
2599                          * OP_LOAD_MEMBASE offset(basereg), reg2
2600                          * -->
2601                          * OP_LOAD_MEMBASE offset(basereg), reg1
2602                          * OP_MOVE reg1, reg2
2603                          */
2604                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2605                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2606                           ins->inst_basereg != last_ins->dreg &&
2607                           ins->inst_basereg == last_ins->inst_basereg &&
2608                           ins->inst_offset == last_ins->inst_offset) {
2609
2610                         if (ins->dreg == last_ins->dreg) {
2611                                 MONO_DELETE_INS (bb, ins);
2612                         } else {
2613                                 ins->opcode = OP_MOVE;
2614                                 ins->sreg1 = last_ins->dreg;
2615                         }
2616
2617                         //g_assert_not_reached ();
2618
2619 #if 0
2620                         /*
2621                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2622                          * OP_LOAD_MEMBASE offset(basereg), reg
2623                          * -->
2624                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2625                          * OP_ICONST reg, imm
2626                          */
2627                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2628                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2629                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2630                                    ins->inst_offset == last_ins->inst_offset) {
2631                         ins->opcode = OP_ICONST;
2632                         ins->inst_c0 = last_ins->inst_imm;
2633                         g_assert_not_reached (); // check this rule
2634 #endif
2635                 }
2636                 break;
2637         case OP_LOADI1_MEMBASE:
2638         case OP_LOADU1_MEMBASE:
2639                 /*
2640                  * Note: if reg1 = reg2 the load op is removed
2641                  *
2642                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2643                  * OP_LOAD_MEMBASE offset(basereg), reg2
2644                  * -->
2645                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2646                  * OP_MOVE reg1, reg2
2647                  */
2648                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2649                         ins->inst_basereg == last_ins->inst_destbasereg &&
2650                         ins->inst_offset == last_ins->inst_offset) {
2651                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2652                         ins->sreg1 = last_ins->sreg1;
2653                 }
2654                 break;
2655         case OP_LOADI2_MEMBASE:
2656         case OP_LOADU2_MEMBASE:
2657                 /*
2658                  * Note: if reg1 = reg2 the load op is removed
2659                  *
2660                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2661                  * OP_LOAD_MEMBASE offset(basereg), reg2
2662                  * -->
2663                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2664                  * OP_MOVE reg1, reg2
2665                  */
2666                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2667                         ins->inst_basereg == last_ins->inst_destbasereg &&
2668                         ins->inst_offset == last_ins->inst_offset) {
2669 #if SIZEOF_REGISTER == 8
2670                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2671 #else
2672                         /* The definition of OP_PCONV_TO_U2 is wrong */
2673                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2674 #endif
2675                         ins->sreg1 = last_ins->sreg1;
2676                 }
2677                 break;
2678         case OP_MOVE:
2679         case OP_FMOVE:
2680                 /*
2681                  * Removes:
2682                  *
2683                  * OP_MOVE reg, reg
2684                  */
2685                 if (ins->dreg == ins->sreg1) {
2686                         MONO_DELETE_INS (bb, ins);
2687                         break;
2688                 }
2689                 /*
2690                  * Removes:
2691                  *
2692                  * OP_MOVE sreg, dreg
2693                  * OP_MOVE dreg, sreg
2694                  */
2695                 if (last_ins && last_ins->opcode == ins->opcode &&
2696                         ins->sreg1 == last_ins->dreg &&
2697                         ins->dreg == last_ins->sreg1) {
2698                         MONO_DELETE_INS (bb, ins);
2699                 }
2700                 break;
2701         case OP_NOP:
2702                 MONO_DELETE_INS (bb, ins);
2703                 break;
2704         }
2705 }
2706
2707 int
2708 mini_exception_id_by_name (const char *name)
2709 {
2710         if (strcmp (name, "IndexOutOfRangeException") == 0)
2711                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2712         if (strcmp (name, "OverflowException") == 0)
2713                 return MONO_EXC_OVERFLOW;
2714         if (strcmp (name, "ArithmeticException") == 0)
2715                 return MONO_EXC_ARITHMETIC;
2716         if (strcmp (name, "DivideByZeroException") == 0)
2717                 return MONO_EXC_DIVIDE_BY_ZERO;
2718         if (strcmp (name, "InvalidCastException") == 0)
2719                 return MONO_EXC_INVALID_CAST;
2720         if (strcmp (name, "NullReferenceException") == 0)
2721                 return MONO_EXC_NULL_REF;
2722         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2723                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2724         if (strcmp (name, "ArgumentException") == 0)
2725                 return MONO_EXC_ARGUMENT;
2726         g_error ("Unknown intrinsic exception %s\n", name);
2727         return -1;
2728 }
2729
2730 gboolean
2731 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2732 {
2733         MonoClass *klass;
2734         gpointer iter;
2735         MonoClassField *field;
2736         MonoType *ftype, *prev_ftype = NULL;
2737         int nfields = 0;
2738
2739         klass = mono_class_from_mono_type (t);
2740         iter = NULL;
2741         while ((field = mono_class_get_fields (klass, &iter))) {
2742                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2743                         continue;
2744                 ftype = mono_field_get_type (field);
2745                 ftype = mini_native_type_replace_type (ftype);
2746
2747                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2748                         int nested_nfields, nested_esize;
2749
2750                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2751                                 return FALSE;
2752                         if (nested_esize == 4)
2753                                 ftype = &mono_defaults.single_class->byval_arg;
2754                         else
2755                                 ftype = &mono_defaults.double_class->byval_arg;
2756                         if (prev_ftype && prev_ftype->type != ftype->type)
2757                                 return FALSE;
2758                         prev_ftype = ftype;
2759                         nfields += nested_nfields;
2760                 } else {
2761                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2762                                 return FALSE;
2763                         if (prev_ftype && prev_ftype->type != ftype->type)
2764                                 return FALSE;
2765                         prev_ftype = ftype;
2766                         nfields ++;
2767                 }
2768         }
2769         if (nfields == 0)
2770                 return FALSE;
2771         *out_nfields = nfields;
2772         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2773         return TRUE;
2774 }
2775
2776 MonoRegState*
2777 mono_regstate_new (void)
2778 {
2779         MonoRegState* rs = g_new0 (MonoRegState, 1);
2780
2781         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2782 #ifdef MONO_ARCH_NEED_SIMD_BANK
2783         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2784 #endif
2785
2786         return rs;
2787 }
2788
2789 void
2790 mono_regstate_free (MonoRegState *rs) {
2791         g_free (rs->vassign);
2792         g_free (rs);
2793 }
2794
2795 #endif /* DISABLE_JIT */
2796