mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30 /*
  31  * Every hardware register belongs to a register type or register bank. bank 0
  32  * contains the int registers, bank 1 contains the fp registers.
  33  * int registers are used 99% of the time, so they are special cased in a lot of
  34  * places.
  35  */
  36
  37 static const int regbank_size [] = {
  38         MONO_MAX_IREGS,
  39         MONO_MAX_FREGS,
  40         MONO_MAX_XREGS
  41 };
  42
  43 static const int regbank_load_ops [] = {
  44         OP_LOAD_MEMBASE,
  45         OP_LOADR8_MEMBASE,
  46         OP_LOADX_MEMBASE
  47 };
  48
  49 static const int regbank_store_ops [] = {
  50         OP_STORE_MEMBASE_REG,
  51         OP_STORER8_MEMBASE_REG,
  52         OP_STOREX_MEMBASE
  53 };
  54
  55 static const int regbank_move_ops [] = {
  56         OP_MOVE,
  57         OP_FMOVE,
  58         OP_XMOVE
  59 };
  60
  61 #define regmask(reg) (((regmask_t)1) << (reg))
  62
  63 static const regmask_t regbank_callee_saved_regs [] = {
  64         MONO_ARCH_CALLEE_SAVED_REGS,
  65         MONO_ARCH_CALLEE_SAVED_FREGS,
  66         MONO_ARCH_CALLEE_SAVED_XREGS,
  67 };
  68
  69 static const regmask_t regbank_callee_regs [] = {
  70         MONO_ARCH_CALLEE_REGS,
  71         MONO_ARCH_CALLEE_FREGS,
  72         MONO_ARCH_CALLEE_XREGS,
  73 };
  74
  75 static const int regbank_spill_var_size[] = {
  76         sizeof (gpointer),
  77         sizeof (double),
  78         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
  79 };
  80
  81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
  82
  83 static inline GSList*
  84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
  85 {
  86         GSList *new_list;
  87         GSList *last;
  88
  89         new_list = mono_mempool_alloc (mp, sizeof (GSList));
  90         new_list->data = data;
  91         new_list->next = NULL;
  92
  93         if (list) {
  94                 last = list;
  95                 while (last->next)
  96                         last = last->next;
  97                 last->next = new_list;
  98
  99                 return list;
 100         } else
 101                 return new_list;
 102 }
 103
 104 static inline void
 105 mono_regstate_assign (MonoRegState *rs)
 106 {
 107         if (rs->next_vreg > rs->vassign_size) {
 108                 g_free (rs->vassign);
 109                 rs->vassign_size = MAX (rs->next_vreg, 256);
 110                 rs->vassign = g_malloc (rs->vassign_size * sizeof (int));
 111         }
 112
 113         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 114         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 115
 116         rs->symbolic [0] = rs->isymbolic;
 117         rs->symbolic [1] = rs->fsymbolic;
 118
 119 #ifdef MONO_ARCH_NEED_SIMD_BANK
 120         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 121         rs->symbolic [2] = rs->xsymbolic;
 122 #endif
 123 }
 124
 125 static inline int
 126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 127 {
 128         regmask_t mask = allow & rs->ifree_mask;
 129
 130 #if defined(__x86_64__) && defined(__GNUC__)
 131  {
 132         guint64 i;
 133
 134         if (mask == 0)
 135                 return -1;
 136
 137         __asm__("bsfq %1,%0\n\t"
 138                         : "=r" (i) : "rm" (mask));
 139
 140         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 141         return i;
 142  }
 143 #else
 144         int i;
 145
 146         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 147                 if (mask & ((regmask_t)1 << i)) {
 148                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 149                         return i;
 150                 }
 151         }
 152         return -1;
 153 #endif
 154 }
 155
 156 static inline void
 157 mono_regstate_free_int (MonoRegState *rs, int reg)
 158 {
 159         if (reg >= 0) {
 160                 rs->ifree_mask |= (regmask_t)1 << reg;
 161                 rs->isymbolic [reg] = 0;
 162         }
 163 }
 164
 165 static inline int
 166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 167 {
 168         int i;
 169         regmask_t mask = allow & rs->free_mask [bank];
 170         for (i = 0; i < regbank_size [bank]; ++i) {
 171                 if (mask & ((regmask_t)1 << i)) {
 172                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 173                         return i;
 174                 }
 175         }
 176         return -1;
 177 }
 178
 179 static inline void
 180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 181 {
 182         if (reg >= 0) {
 183                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 184                 rs->symbolic [bank][reg] = 0;
 185         }
 186 }
 187
 188 const char*
 189 mono_regname_full (int reg, int bank)
 190 {
 191         if (G_UNLIKELY (bank)) {
 192 #if MONO_ARCH_NEED_SIMD_BANK
 193                 if (bank == 2)
 194                         return mono_arch_xregname (reg);
 195 #endif
 196                 g_assert (bank == 1);
 197                 return mono_arch_fregname (reg);
 198         } else {
 199                 return mono_arch_regname (reg);
 200         }
 201 }
 202
 203 void
 204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 205 {
 206         guint32 regpair;
 207
 208         regpair = (((guint32)hreg) << 24) + vreg;
 209         if (G_UNLIKELY (bank)) {
 210                 g_assert (vreg >= regbank_size [bank]);
 211                 g_assert (hreg < regbank_size [bank]);
 212                 call->used_fregs |= 1 << hreg;
 213                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 214         } else {
 215                 g_assert (vreg >= MONO_MAX_IREGS);
 216                 g_assert (hreg < MONO_MAX_IREGS);
 217                 call->used_iregs |= 1 << hreg;
 218                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 219         }
 220 }
 221
 222 static void
 223 resize_spill_info (MonoCompile *cfg, int bank)
 224 {
 225         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 226         int orig_len = cfg->spill_info_len [bank];
 227         int new_len = orig_len ? orig_len * 2 : 16;
 228         MonoSpillInfo *new_info;
 229         int i;
 230
 231         g_assert (bank < MONO_NUM_REGBANKS);
 232
 233         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 234         if (orig_info)
 235                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 236         for (i = orig_len; i < new_len; ++i)
 237                 new_info [i].offset = -1;
 238
 239         cfg->spill_info [bank] = new_info;
 240         cfg->spill_info_len [bank] = new_len;
 241 }
 242
 243 /*
 244  * returns the offset used by spillvar. It allocates a new
 245  * spill variable if necessary.
 246  */
 247 static inline int
 248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 249 {
 250         MonoSpillInfo *info;
 251         int size;
 252
 253         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 254                 while (spillvar >= cfg->spill_info_len [bank])
 255                         resize_spill_info (cfg, bank);
 256         }
 257
 258         /*
 259          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 260          */
 261         info = &cfg->spill_info [bank][spillvar];
 262         if (info->offset == -1) {
 263                 cfg->stack_offset += sizeof (gpointer) - 1;
 264                 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
 265
 266                 g_assert (bank < MONO_NUM_REGBANKS);
 267                 if (G_UNLIKELY (bank))
 268                         size = regbank_spill_var_size [bank];
 269                 else
 270                         size = sizeof (gpointer);
 271
 272                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 273                         cfg->stack_offset += size - 1;
 274                         cfg->stack_offset &= ~(size - 1);
 275                         info->offset = cfg->stack_offset;
 276                         cfg->stack_offset += size;
 277                 } else {
 278                         cfg->stack_offset += size - 1;
 279                         cfg->stack_offset &= ~(size - 1);
 280                         cfg->stack_offset += size;
 281                         info->offset = - cfg->stack_offset;
 282                 }
 283         }
 284
 285         return info->offset;
 286 }
 287
 288 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 289 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 290 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 291 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 292 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 293 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 294
 295 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 296 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 297 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 298 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 299 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 300
 301 #ifndef MONO_ARCH_INST_IS_FLOAT
 302 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 303 #endif
 304
 305 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 306 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 307 #define sreg1_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1]))
 308 #define sreg2_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC2]))
 309
 310 #define reg_is_simd(desc) ((desc) == 'x')
 311
 312 #ifdef MONO_ARCH_NEED_SIMD_BANK
 313
 314 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 315
 316 #else
 317
 318 #define reg_bank(desc) reg_is_fp ((desc))
 319
 320 #endif
 321
 322 #define sreg1_bank(spec) reg_bank ((spec)[MONO_INST_SRC1])
 323 #define sreg2_bank(spec) reg_bank ((spec)[MONO_INST_SRC2])
 324 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 325
 326 #define sreg1_bank_ins(ins) sreg1_bank (ins_get_spec ((ins)->opcode))
 327 #define sreg2_bank_ins(ins) sreg2_bank (ins_get_spec ((ins)->opcode))
 328 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 329
 330 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 331
 332 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 333 #undef is_global_ireg
 334 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 335 #endif
 336
 337 typedef struct {
 338         int born_in;
 339         int killed_in;
 340         /* Not (yet) used */
 341         //int last_use;
 342         //int prev_use;
 343         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 344 } RegTrack;
 345
 346 #ifndef DISABLE_LOGGING
 347 void
 348 mono_print_ins_index (int i, MonoInst *ins)
 349 {
 350         const char *spec = ins_get_spec (ins->opcode);
 351
 352         if (i != -1)
 353                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 354         else
 355                 printf (" %s", mono_inst_name (ins->opcode));
 356         if (spec == MONO_ARCH_CPU_SPEC) {
 357                 /* This is a lowered opcode */
 358                 if (ins->dreg != -1)
 359                         printf (" R%d <-", ins->dreg);
 360                 if (ins->sreg1 != -1)
 361                         printf (" R%d", ins->sreg1);
 362                 if (ins->sreg2 != -1)
 363                         printf (" R%d", ins->sreg2);
 364
 365                 switch (ins->opcode) {
 366                 case OP_LBNE_UN:
 367                 case OP_LBEQ:
 368                 case OP_LBLT:
 369                 case OP_LBLT_UN:
 370                 case OP_LBGT:
 371                 case OP_LBGT_UN:
 372                 case OP_LBGE:
 373                 case OP_LBGE_UN:
 374                 case OP_LBLE:
 375                 case OP_LBLE_UN:
 376                         if (!(ins->flags & MONO_INST_BRLABEL)) {
 377                                 if (!ins->inst_false_bb)
 378                                         printf (" [B%d]", ins->inst_true_bb->block_num);
 379                                 else
 380                                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 381                         }
 382                         break;
 383                 case OP_PHI:
 384                 case OP_FPHI: {
 385                         int i;
 386                         printf (" [%d (", (int)ins->inst_c0);
 387                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 388                                 if (i)
 389                                         printf (", ");
 390                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 391                         }
 392                         printf (")]");
 393                         break;
 394                 }
 395                 case OP_LDADDR:
 396                 case OP_OUTARG_VTRETADDR:
 397                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 398                         break;
 399                 case OP_REGOFFSET:
 400                         printf (" + 0x%lx", (long)ins->inst_offset);
 401                 default:
 402                         break;
 403                 }
 404
 405                 printf ("\n");
 406                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 407                 return;
 408         }
 409
 410         if (spec [MONO_INST_DEST]) {
 411                 int bank = dreg_bank (spec);
 412                 if (is_soft_reg (ins->dreg, bank)) {
 413                         if (spec [MONO_INST_DEST] == 'b') {
 414                                 if (ins->inst_offset == 0)
 415                                         printf (" [R%d] <-", ins->dreg);
 416                                 else
 417                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 418                         }
 419                         else
 420                                 printf (" R%d <-", ins->dreg);
 421                 } else if (spec [MONO_INST_DEST] == 'b') {
 422                         if (ins->inst_offset == 0)
 423                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 424                         else
 425                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 426                 } else
 427                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 428         }
 429         if (spec [MONO_INST_SRC1]) {
 430                 int bank = sreg1_bank (spec);
 431                 if (is_soft_reg (ins->sreg1, bank)) {
 432                         if (spec [MONO_INST_SRC1] == 'b')
 433                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 434                         else
 435                                 printf (" R%d", ins->sreg1);
 436                 } else if (spec [MONO_INST_SRC1] == 'b')
 437                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 438                 else
 439                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 440         }
 441         if (spec [MONO_INST_SRC2]) {
 442                 int bank = sreg2_bank (spec);
 443                 if (is_soft_reg (ins->sreg2, bank))
 444                         printf (" R%d", ins->sreg2);
 445                 else
 446                         printf (" %s", mono_regname_full (ins->sreg2, bank));
 447         }
 448
 449         switch (ins->opcode) {
 450         case OP_ICONST:
 451                 printf (" [%d]", (int)ins->inst_c0);
 452                 break;
 453 #if defined(__i386__) || defined(__x86_64__)
 454         case OP_X86_PUSH_IMM:
 455 #endif
 456         case OP_ICOMPARE_IMM:
 457         case OP_COMPARE_IMM:
 458         case OP_IADD_IMM:
 459         case OP_ISUB_IMM:
 460         case OP_IAND_IMM:
 461         case OP_IOR_IMM:
 462         case OP_IXOR_IMM:
 463                 printf (" [%d]", (int)ins->inst_imm);
 464                 break;
 465         case OP_ADD_IMM:
 466         case OP_LADD_IMM:
 467                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 468                 break;
 469         case OP_I8CONST:
 470                 printf (" [%lld]", (long long)ins->inst_l);
 471                 break;
 472         case OP_R8CONST:
 473                 printf (" [%f]", *(double*)ins->inst_p0);
 474                 break;
 475         case OP_R4CONST:
 476                 printf (" [%f]", *(float*)ins->inst_p0);
 477                 break;
 478         case CEE_CALL:
 479         case CEE_CALLVIRT:
 480         case OP_CALL:
 481         case OP_CALL_MEMBASE:
 482         case OP_CALL_REG:
 483         case OP_FCALL:
 484         case OP_FCALLVIRT:
 485         case OP_LCALL:
 486         case OP_LCALLVIRT:
 487         case OP_VCALL:
 488         case OP_VCALLVIRT:
 489         case OP_VCALL_REG:
 490         case OP_VCALL_MEMBASE:
 491         case OP_VCALL2:
 492         case OP_VCALL2_REG:
 493         case OP_VCALL2_MEMBASE:
 494         case OP_VOIDCALL:
 495         case OP_VOIDCALL_MEMBASE:
 496         case OP_VOIDCALLVIRT: {
 497                 MonoCallInst *call = (MonoCallInst*)ins;
 498                 GSList *list;
 499
 500                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 501                         /*
 502                          * These are lowered opcodes, but they are in the .md files since the old
 503                          * JIT passes them to backends.
 504                          */
 505                         if (ins->dreg != -1)
 506                                 printf (" R%d <-", ins->dreg);
 507                 }
 508
 509                 if (call->method) {
 510                         char *full_name = mono_method_full_name (call->method, TRUE);
 511                         printf (" [%s]", full_name);
 512                         g_free (full_name);
 513                 } else if (call->fptr) {
 514                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 515                         if (info)
 516                                 printf (" [%s]", info->name);
 517                 }
 518
 519                 list = call->out_ireg_args;
 520                 while (list) {
 521                         guint32 regpair;
 522                         int reg, hreg;
 523
 524                         regpair = (guint32)(gssize)(list->data);
 525                         hreg = regpair >> 24;
 526                         reg = regpair & 0xffffff;
 527
 528                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 529
 530                         list = g_slist_next (list);
 531                 }
 532                 break;
 533         }
 534         case OP_BR:
 535         case OP_CALL_HANDLER:
 536                 printf (" [B%d]", ins->inst_target_bb->block_num);
 537                 break;
 538         case CEE_BNE_UN:
 539         case CEE_BEQ:
 540         case CEE_BLT:
 541         case CEE_BLT_UN:
 542         case CEE_BGT:
 543         case CEE_BGT_UN:
 544         case CEE_BGE:
 545         case CEE_BGE_UN:
 546         case CEE_BLE:
 547         case CEE_BLE_UN:
 548         case OP_IBNE_UN:
 549         case OP_IBEQ:
 550         case OP_IBLT:
 551         case OP_IBLT_UN:
 552         case OP_IBGT:
 553         case OP_IBGT_UN:
 554         case OP_IBGE:
 555         case OP_IBGE_UN:
 556         case OP_IBLE:
 557         case OP_IBLE_UN:
 558         case OP_LBNE_UN:
 559         case OP_LBEQ:
 560         case OP_LBLT:
 561         case OP_LBLT_UN:
 562         case OP_LBGT:
 563         case OP_LBGT_UN:
 564         case OP_LBGE:
 565         case OP_LBGE_UN:
 566         case OP_LBLE:
 567         case OP_LBLE_UN:
 568                 if (!(ins->flags & MONO_INST_BRLABEL)) {
 569                         if (!ins->inst_false_bb)
 570                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 571                         else
 572                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 573                 }
 574                 break;
 575         default:
 576                 break;
 577         }
 578
 579         if (spec [MONO_INST_CLOB])
 580                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 581         printf ("\n");
 582 }
 583
 584 static void
 585 print_regtrack (RegTrack *t, int num)
 586 {
 587         int i;
 588         char buf [32];
 589         const char *r;
 590
 591         for (i = 0; i < num; ++i) {
 592                 if (!t [i].born_in)
 593                         continue;
 594                 if (i >= MONO_MAX_IREGS) {
 595                         g_snprintf (buf, sizeof(buf), "R%d", i);
 596                         r = buf;
 597                 } else
 598                         r = mono_arch_regname (i);
 599                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 600         }
 601 }
 602 #else
 603 void
 604 mono_print_ins_index (int i, MonoInst *ins)
 605 {
 606 }
 607 #endif /* DISABLE_LOGGING */
 608
 609 void
 610 mono_print_ins (MonoInst *ins)
 611 {
 612         mono_print_ins_index (-1, ins);
 613 }
 614
 615 static inline void
 616 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 617 {
 618         /*
 619          * If this function is called multiple times, the new instructions are inserted
 620          * in the proper order.
 621          */
 622         mono_bblock_insert_before_ins (bb, ins, to_insert);
 623 }
 624
 625 static inline void
 626 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 627 {
 628         /*
 629          * If this function is called multiple times, the new instructions are inserted in
 630          * proper order.
 631          */
 632         mono_bblock_insert_after_ins (bb, *last, to_insert);
 633
 634         *last = to_insert;
 635 }
 636
 637 /*
 638  * Force the spilling of the variable in the symbolic register 'reg'.
 639  */
 640 static int
 641 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 642 {
 643         MonoInst *load;
 644         int i, sel, spill;
 645         int *symbolic;
 646         MonoRegState *rs = cfg->rs;
 647
 648         symbolic = rs->symbolic [bank];
 649         sel = rs->vassign [reg];
 650
 651         /*i = rs->isymbolic [sel];
 652         g_assert (i == reg);*/
 653         i = reg;
 654         spill = ++cfg->spill_count;
 655         rs->vassign [i] = -spill - 1;
 656         if (G_UNLIKELY (bank))
 657                 mono_regstate_free_general (rs, sel, bank);
 658         else
 659                 mono_regstate_free_int (rs, sel);
 660         /* we need to create a spill var and insert a load to sel after the current instruction */
 661         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 662         load->dreg = sel;
 663         load->inst_basereg = cfg->frame_reg;
 664         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 665         insert_after_ins (bb, ins, last, load);
 666         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 667         if (G_UNLIKELY (bank))
 668                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 669         else
 670                 i = mono_regstate_alloc_int (rs, regmask (sel));
 671         g_assert (i == sel);
 672
 673         return sel;
 674 }
 675
 676 /* This isn't defined on older glib versions and on some platforms */
 677 #ifndef G_GUINT64_FORMAT
 678 #define G_GUINT64_FORMAT "ul"
 679 #endif
 680
 681 static int
 682 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 683 {
 684         MonoInst *load;
 685         int i, sel, spill;
 686         int *symbolic;
 687         MonoRegState *rs = cfg->rs;
 688
 689         symbolic = rs->symbolic [bank];
 690
 691         g_assert (bank < MONO_NUM_REGBANKS);
 692
 693         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2));
 694         /* exclude the registers in the current instruction */
 695         if ((sreg1_bank_ins (ins) == bank) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, bank) || (is_soft_reg (ins->sreg1, bank) && rs->vassign [ins->sreg1] >= 0))) {
 696                 if (is_soft_reg (ins->sreg1, bank))
 697                         regmask &= ~ (regmask (rs->vassign [ins->sreg1]));
 698                 else
 699                         regmask &= ~ (regmask (ins->sreg1));
 700                 DEBUG (printf ("\t\texcluding sreg1 %s\n", mono_regname_full (ins->sreg1, bank)));
 701         }
 702         if ((sreg2_bank_ins (ins) == bank) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, bank) || (is_soft_reg (ins->sreg2, bank) && rs->vassign [ins->sreg2] >= 0))) {
 703                 if (is_soft_reg (ins->sreg2, bank))
 704                         regmask &= ~ (regmask (rs->vassign [ins->sreg2]));
 705                 else
 706                         regmask &= ~ (regmask (ins->sreg2));
 707                 DEBUG (printf ("\t\texcluding sreg2 %s %d\n", mono_regname_full (ins->sreg2, bank), ins->sreg2));
 708         }
 709         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 710                 regmask &= ~ (regmask (ins->dreg));
 711                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 712         }
 713
 714         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 715         g_assert (regmask); /* need at least a register we can free */
 716         sel = 0;
 717         /* we should track prev_use and spill the register that's farther */
 718         if (G_UNLIKELY (bank)) {
 719                 for (i = 0; i < regbank_size [bank]; ++i) {
 720                         if (regmask & (regmask (i))) {
 721                                 sel = i;
 722                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 723                                 break;
 724                         }
 725                 }
 726
 727                 i = rs->symbolic [bank] [sel];
 728                 spill = ++cfg->spill_count;
 729                 rs->vassign [i] = -spill - 1;
 730                 mono_regstate_free_general (rs, sel, bank);
 731         }
 732         else {
 733                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 734                         if (regmask & (regmask (i))) {
 735                                 sel = i;
 736                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 737                                 break;
 738                         }
 739                 }
 740
 741                 i = rs->isymbolic [sel];
 742                 spill = ++cfg->spill_count;
 743                 rs->vassign [i] = -spill - 1;
 744                 mono_regstate_free_int (rs, sel);
 745         }
 746
 747         /* we need to create a spill var and insert a load to sel after the current instruction */
 748         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 749         load->dreg = sel;
 750         load->inst_basereg = cfg->frame_reg;
 751         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 752         insert_after_ins (bb, ins, last, load);
 753         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 754         if (G_UNLIKELY (bank))
 755                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 756         else
 757                 i = mono_regstate_alloc_int (rs, regmask (sel));
 758         g_assert (i == sel);
 759
 760         return sel;
 761 }
 762
 763 static void
 764 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 765 {
 766         if (G_UNLIKELY (bank)) {
 767                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 768                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 769                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 770                         mono_regstate_free_general (cfg->rs, hreg, bank);
 771                 }
 772         }
 773         else {
 774                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 775                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 776                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 777                         mono_regstate_free_int (cfg->rs, hreg);
 778                 }
 779         }
 780 }
 781
 782 static MonoInst*
 783 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 784 {
 785         MonoInst *copy;
 786
 787         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 788
 789         copy->dreg = dest;
 790         copy->sreg1 = src;
 791         copy->cil_code = ip;
 792         if (ins) {
 793                 mono_bblock_insert_after_ins (bb, ins, copy);
 794                 *last = copy;
 795         }
 796         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 797         return copy;
 798 }
 799
 800 static MonoInst*
 801 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 802 {
 803         MonoInst *store;
 804         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 805         store->sreg1 = reg;
 806         store->inst_destbasereg = cfg->frame_reg;
 807         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 808         if (ins) {
 809                 mono_bblock_insert_after_ins (bb, ins, store);
 810                 *last = store;
 811         }
 812         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 813         return store;
 814 }
 815
 816 /* flags used in reginfo->flags */
 817 enum {
 818         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 819         MONO_FP_NEEDS_SPILL                     = regmask (1),
 820         MONO_FP_NEEDS_LOAD                      = regmask (2)
 821 };
 822
 823 static inline int
 824 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 825 {
 826         int val;
 827
 828         if (info && info->preferred_mask) {
 829                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 830                 if (val >= 0) {
 831                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 832                         return val;
 833                 }
 834         }
 835
 836         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 837         if (val < 0)
 838                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 839
 840         return val;
 841 }
 842
 843 static inline int
 844 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 845 {
 846         int val;
 847
 848         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 849
 850         if (val < 0)
 851                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 852
 853         return val;
 854 }
 855
 856 static inline int
 857 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 858 {
 859         if (G_UNLIKELY (bank))
 860                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 861         else
 862                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 863 }
 864
 865 static inline void
 866 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 867 {
 868         if (G_UNLIKELY (bank)) {
 869                 g_assert (reg >= regbank_size [bank]);
 870                 g_assert (hreg < regbank_size [bank]);
 871                 g_assert (! is_global_freg (hreg));
 872
 873                 rs->vassign [reg] = hreg;
 874                 rs->symbolic [bank] [hreg] = reg;
 875                 rs->free_mask [bank] &= ~ (regmask (hreg));
 876         }
 877         else {
 878                 g_assert (reg >= MONO_MAX_IREGS);
 879                 g_assert (hreg < MONO_MAX_IREGS);
 880 #ifndef __arm__
 881                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 882                 g_assert (! is_global_ireg (hreg));
 883 #endif
 884
 885                 rs->vassign [reg] = hreg;
 886                 rs->isymbolic [hreg] = reg;
 887                 rs->ifree_mask &= ~ (regmask (hreg));
 888         }
 889 }
 890
 891 static inline regmask_t
 892 get_callee_mask (const char spec)
 893 {
 894         if (G_UNLIKELY (reg_bank (spec)))
 895                 return regbank_callee_regs [reg_bank (spec)];
 896         return MONO_ARCH_CALLEE_REGS;
 897 }
 898
 899 static gint8 desc_to_fixed_reg [256];
 900 static gboolean desc_to_fixed_reg_inited = FALSE;
 901
 902 /*
 903  * Local register allocation.
 904  * We first scan the list of instructions and we save the liveness info of
 905  * each register (when the register is first used, when it's value is set etc.).
 906  * We also reverse the list of instructions because assigning registers backwards allows
 907  * for more tricks to be used.
 908  */
 909 void
 910 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 911 {
 912         MonoInst *ins, *prev, *last;
 913         MonoInst **tmp;
 914         MonoRegState *rs = cfg->rs;
 915         int i, val, max;
 916         RegTrack *reginfo;
 917         const char *spec;
 918         unsigned char spec_src1, spec_src2, spec_dest;
 919         int bank = 0;
 920 #if MONO_ARCH_USE_FPSTACK
 921         gboolean has_fp = FALSE;
 922         int fpstack [8];
 923         int sp = 0;
 924 #endif
 925
 926         if (!bb->code)
 927                 return;
 928
 929         if (!desc_to_fixed_reg_inited) {
 930                 for (i = 0; i < 256; ++i)
 931                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
 932                 desc_to_fixed_reg_inited = TRUE;
 933         }
 934
 935         rs->next_vreg = bb->max_vreg;
 936         mono_regstate_assign (rs);
 937
 938         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
 939         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
 940                 rs->free_mask [i] = regbank_callee_regs [i];
 941
 942         max = rs->next_vreg;
 943
 944         if (cfg->reginfo && cfg->reginfo_len < max)
 945                 cfg->reginfo = NULL;
 946
 947         reginfo = cfg->reginfo;
 948         if (!reginfo) {
 949                 cfg->reginfo_len = MAX (1024, max * 2);
 950                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
 951         }
 952         else
 953                 g_assert (cfg->reginfo_len >= rs->next_vreg);
 954
 955         if (cfg->verbose_level > 1) {
 956                 /* print_regtrack reads the info of all variables */
 957                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
 958         }
 959
 960         /*
 961          * For large methods, next_vreg can be very large, so g_malloc0 time can
 962          * be prohibitive. So we manually init the reginfo entries used by the
 963          * bblock.
 964          */
 965         for (ins = bb->code; ins; ins = ins->next) {
 966                 spec = ins_get_spec (ins->opcode);
 967
 968                 if ((ins->dreg != -1) && (ins->dreg < max)) {
 969                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
 970 #if SIZEOF_VOID_P == 4
 971                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
 972                                 /**
 973                                  * In the new IR, the two vregs of the regpair do not alias the
 974                                  * original long vreg. shift the vreg here so the rest of the
 975                                  * allocator doesn't have to care about it.
 976                                  */
 977                                 ins->dreg ++;
 978                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
 979                         }
 980 #endif
 981                 }
 982                 if ((ins->sreg1 != -1) && (ins->sreg1 < max)) {
 983                         memset (&reginfo [ins->sreg1], 0, sizeof (RegTrack));
 984 #if SIZEOF_VOID_P == 4
 985                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1])) {
 986                                 ins->sreg1 ++;
 987                                 memset (&reginfo [ins->sreg1 + 1], 0, sizeof (RegTrack));
 988                         }
 989 #endif
 990                 }
 991                 if ((ins->sreg2 != -1) && (ins->sreg2 < max)) {
 992                         memset (&reginfo [ins->sreg2], 0, sizeof (RegTrack));
 993 #if SIZEOF_VOID_P == 4
 994                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
 995                                 ins->sreg2 ++;
 996                                 memset (&reginfo [ins->sreg2 + 1], 0, sizeof (RegTrack));
 997                         }
 998 #endif
 999                 }
1000         }
1001
1002         /*if (cfg->opt & MONO_OPT_COPYPROP)
1003                 local_copy_prop (cfg, ins);*/
1004
1005         i = 1;
1006         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1007         /* forward pass on the instructions to collect register liveness info */
1008         MONO_BB_FOR_EACH_INS (bb, ins) {
1009                 spec = ins_get_spec (ins->opcode);
1010                 spec_src1 = spec [MONO_INST_SRC1];
1011                 spec_src2 = spec [MONO_INST_SRC2];
1012                 spec_dest = spec [MONO_INST_DEST];
1013
1014                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1015                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1016                 }
1017
1018                 DEBUG (mono_print_ins_index (i, ins));
1019
1020 #if MONO_ARCH_USE_FPSTACK
1021                 if (sreg1_is_fp (spec) || sreg2_is_fp (spec) || dreg_is_fp (spec))
1022                         has_fp = TRUE;
1023 #endif
1024
1025                 if (spec_src1) {
1026                         bank = sreg1_bank (spec);
1027                         g_assert (ins->sreg1 != -1);
1028                         if (is_soft_reg (ins->sreg1, bank))
1029                                 /* This means the vreg is not local to this bb */
1030                                 g_assert (reginfo [ins->sreg1].born_in > 0);
1031                         rs->vassign [ins->sreg1] = -1;
1032                         //reginfo [ins->sreg1].prev_use = reginfo [ins->sreg1].last_use;
1033                         //reginfo [ins->sreg1].last_use = i;
1034                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1035                                 /* The virtual register is allocated sequentially */
1036                                 rs->vassign [ins->sreg1 + 1] = -1;
1037                                 //reginfo [ins->sreg1 + 1].prev_use = reginfo [ins->sreg1 + 1].last_use;
1038                                 //reginfo [ins->sreg1 + 1].last_use = i;
1039                                 if (reginfo [ins->sreg1 + 1].born_in == 0 || reginfo [ins->sreg1 + 1].born_in > i)
1040                                         reginfo [ins->sreg1 + 1].born_in = i;
1041                         }
1042                 } else {
1043                         ins->sreg1 = -1;
1044                 }
1045                 if (spec_src2) {
1046                         bank = sreg2_bank (spec);
1047                         g_assert (ins->sreg2 != -1);
1048                         if (is_soft_reg (ins->sreg2, bank))
1049                                 /* This means the vreg is not local to this bb */
1050                                 g_assert (reginfo [ins->sreg2].born_in > 0);
1051                         rs->vassign [ins->sreg2] = -1;
1052                         //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1053                         //reginfo [ins->sreg2].last_use = i;
1054                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1055                                 /* The virtual register is allocated sequentially */
1056                                 rs->vassign [ins->sreg2 + 1] = -1;
1057                                 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1058                                 //reginfo [ins->sreg2 + 1].last_use = i;
1059                                 if (reginfo [ins->sreg2 + 1].born_in == 0 || reginfo [ins->sreg2 + 1].born_in > i)
1060                                         reginfo [ins->sreg2 + 1].born_in = i;
1061                         }
1062                 } else {
1063                         ins->sreg2 = -1;
1064                 }
1065                 if (spec_dest) {
1066                         int dest_dreg;
1067
1068                         bank = dreg_bank (spec);
1069                         if (spec_dest != 'b') /* it's not just a base register */
1070                                 reginfo [ins->dreg].killed_in = i;
1071                         g_assert (ins->dreg != -1);
1072                         rs->vassign [ins->dreg] = -1;
1073                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1074                         //reginfo [ins->dreg].last_use = i;
1075                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1076                                 reginfo [ins->dreg].born_in = i;
1077
1078                         dest_dreg = desc_to_fixed_reg [spec_dest];
1079                         if (dest_dreg != -1)
1080                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1081
1082 #ifdef MONO_ARCH_INST_FIXED_MASK
1083                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1084 #endif
1085
1086                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1087                                 /* The virtual register is allocated sequentially */
1088                                 rs->vassign [ins->dreg + 1] = -1;
1089                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1090                                 //reginfo [ins->dreg + 1].last_use = i;
1091                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1092                                         reginfo [ins->dreg + 1].born_in = i;
1093                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1094                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1095                         }
1096                 } else {
1097                         ins->dreg = -1;
1098                 }
1099
1100                 if (spec [MONO_INST_CLOB] == 'c') {
1101                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1102
1103                         MonoCallInst *call = (MonoCallInst*)ins;
1104                         GSList *list;
1105
1106                         list = call->out_ireg_args;
1107                         if (list) {
1108                                 while (list) {
1109                                         guint32 regpair;
1110                                         int reg, hreg;
1111
1112                                         regpair = (guint32)(gssize)(list->data);
1113                                         hreg = regpair >> 24;
1114                                         reg = regpair & 0xffffff;
1115
1116                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1117                                         //reginfo [reg].last_use = i;
1118
1119                                         list = g_slist_next (list);
1120                                 }
1121                         }
1122
1123                         list = call->out_freg_args;
1124                         if (list) {
1125                                 while (list) {
1126                                         guint32 regpair;
1127                                         int reg, hreg;
1128
1129                                         regpair = (guint32)(gssize)(list->data);
1130                                         hreg = regpair >> 24;
1131                                         reg = regpair & 0xffffff;
1132
1133                                         list = g_slist_next (list);
1134                                 }
1135                         }
1136                 }
1137
1138                 ++i;
1139         }
1140
1141         tmp = &last;
1142
1143         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1144         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1145                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1146                 int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
1147                 int dreg_high, sreg1_high;
1148                 regmask_t dreg_mask, sreg1_mask, sreg2_mask, mask;
1149                 regmask_t dreg_fixed_mask, sreg1_fixed_mask, sreg2_fixed_mask;
1150                 const unsigned char *ip;
1151                 --i;
1152                 spec = ins_get_spec (ins->opcode);
1153                 spec_src1 = spec [MONO_INST_SRC1];
1154                 spec_src2 = spec [MONO_INST_SRC2];
1155                 spec_dest = spec [MONO_INST_DEST];
1156                 prev_dreg = -1;
1157                 prev_sreg2 = -1;
1158                 clob_dreg = -1;
1159                 clob_reg = -1;
1160                 dest_dreg = -1;
1161                 dest_sreg1 = -1;
1162                 dest_sreg2 = -1;
1163                 prev_sreg1 = -1;
1164                 dreg_high = -1;
1165                 sreg1_high = -1;
1166                 dreg_mask = get_callee_mask (spec_dest);
1167                 sreg1_mask = get_callee_mask (spec_src1);
1168                 sreg2_mask = get_callee_mask (spec_src2);
1169
1170                 DEBUG (printf ("processing:"));
1171                 DEBUG (mono_print_ins_index (i, ins));
1172
1173                 ip = ins->cil_code;
1174
1175                 last = ins;
1176
1177                 /*
1178                  * FIXED REGS
1179                  */
1180                 dest_sreg1 = desc_to_fixed_reg [spec_src1];
1181                 dest_sreg2 = desc_to_fixed_reg [spec_src2];
1182                 dest_dreg = desc_to_fixed_reg [spec_dest];
1183                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1184                 sreg2_mask &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1185
1186 #ifdef MONO_ARCH_INST_FIXED_MASK
1187                 sreg1_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src1);
1188                 sreg2_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src2);
1189                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1190 #else
1191                 sreg1_fixed_mask = sreg2_fixed_mask = dreg_fixed_mask = 0;
1192 #endif
1193
1194                 /*
1195                  * TRACK FIXED SREG2
1196                  */
1197                 if (dest_sreg2 != -1) {
1198                         if (rs->ifree_mask & (regmask (dest_sreg2))) {
1199                                 if (is_global_ireg (ins->sreg2)) {
1200                                         /* Argument already in hard reg, need to copy */
1201                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1202                                         insert_before_ins (bb, ins, copy);
1203                                 }
1204                                 else {
1205                                         val = rs->vassign [ins->sreg2];
1206                                         if (val == -1) {
1207                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
1208                                                 assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1209                                         } else if (val < -1) {
1210                                                 /* FIXME: */
1211                                                 g_assert_not_reached ();
1212                                         } else {
1213                                                 /* Argument already in hard reg, need to copy */
1214                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, val, NULL, ip, 0);
1215                                                 insert_before_ins (bb, ins, copy);
1216                                         }
1217                                 }
1218                         } else {
1219                                 gboolean need_spill = TRUE;
1220                                 gboolean need_assign = TRUE;
1221
1222                                 dreg_mask &= ~ (regmask (dest_sreg2));
1223                                 sreg1_mask &= ~ (regmask (dest_sreg2));
1224
1225                                 /*
1226                                  * First check if dreg is assigned to dest_sreg2, since we
1227                                  * can't spill a dreg.
1228                                  */
1229                                 val = rs->vassign [ins->dreg];
1230                                 if (val == dest_sreg2 && ins->dreg != ins->sreg2) {
1231                                         /*
1232                                          * the destination register is already assigned to
1233                                          * dest_sreg2: we need to allocate another register for it
1234                                          * and then copy from this to dest_sreg2.
1235                                          */
1236                                         int new_dest;
1237                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1238                                         g_assert (new_dest >= 0);
1239                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg2)));
1240
1241                                         prev_dreg = ins->dreg;
1242                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1243                                         clob_dreg = ins->dreg;
1244                                         create_copy_ins (cfg, bb, tmp, dest_sreg2, new_dest, ins, ip, 0);
1245                                         mono_regstate_free_int (rs, dest_sreg2);
1246                                         need_spill = FALSE;
1247                                 }
1248
1249                                 if (is_global_ireg (ins->sreg2)) {
1250                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1251                                         insert_before_ins (bb, ins, copy);
1252                                         need_assign = FALSE;
1253                                 }
1254                                 else {
1255                                         val = rs->vassign [ins->sreg2];
1256                                         if (val == dest_sreg2) {
1257                                                 /* sreg2 is already assigned to the correct register */
1258                                                 need_spill = FALSE;
1259                                         } else if (val < -1) {
1260                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1261                                         } else if (val >= 0) {
1262                                                 /* sreg2 already assigned to another register */
1263                                                 /*
1264                                                  * We couldn't emit a copy from val to dest_sreg2, because
1265                                                  * val might be spilled later while processing this
1266                                                  * instruction. So we spill sreg2 so it can be allocated to
1267                                                  * dest_sreg2.
1268                                                  */
1269                                                 DEBUG (printf ("\tforced spill of R%d\n", ins->sreg2));
1270                                                 free_up_reg (cfg, bb, tmp, ins, val, 0);
1271                                         }
1272                                 }
1273
1274                                 if (need_spill) {
1275                                         DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg2]));
1276                                         free_up_reg (cfg, bb, tmp, ins, dest_sreg2, 0);
1277                                 }
1278
1279                                 if (need_assign) {
1280                                         if (rs->vassign [ins->sreg2] < -1) {
1281                                                 MonoInst *store;
1282                                                 int spill;
1283
1284                                                 /* Need to emit a spill store */
1285                                                 spill = - rs->vassign [ins->sreg2] - 1;
1286                                                 store = create_spilled_store (cfg, bb, spill, dest_sreg2, ins->sreg2, tmp, NULL, bank);
1287                                                 insert_before_ins (bb, ins, store);
1288                                         }
1289                                         /* force-set sreg2 */
1290                                         assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1291                                 }
1292                         }
1293                         ins->sreg2 = dest_sreg2;
1294                 }
1295
1296                 /*
1297                  * TRACK DREG
1298                  */
1299                 bank = dreg_bank (spec);
1300                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1301                         prev_dreg = ins->dreg;
1302                 }
1303
1304                 if (spec_dest == 'b') {
1305                         /*
1306                          * The dest reg is read by the instruction, not written, so
1307                          * avoid allocating sreg1/sreg2 to the same reg.
1308                          */
1309                         if (!dest_sreg1 != -1)
1310                                 dreg_mask &= ~ (regmask (dest_sreg1));
1311                         if (dest_sreg2 != -1)
1312                                 dreg_mask &= ~ (regmask (dest_sreg2));
1313
1314                         val = rs->vassign [ins->dreg];
1315                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1316                                 /* DREG is already allocated to a register needed for sreg1 */
1317                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1318                                 mono_regstate_free_int (rs, val);
1319                         }
1320                 }
1321
1322                 /*
1323                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1324                  * various complex situations.
1325                  */
1326                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1327                         guint32 dreg2, dest_dreg2;
1328
1329                         g_assert (is_soft_reg (ins->dreg, bank));
1330
1331                         if (dest_dreg != -1) {
1332                                 if (rs->vassign [ins->dreg] != dest_dreg)
1333                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1334
1335                                 dreg2 = ins->dreg + 1;
1336                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1337                                 if (dest_dreg2 != -1) {
1338                                         if (rs->vassign [dreg2] != dest_dreg2)
1339                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1340                                 }
1341                         }
1342                 }
1343
1344                 if (dreg_fixed_mask) {
1345                         g_assert (!bank);
1346                         if (is_global_ireg (ins->dreg)) {
1347                                 /*
1348                                  * The argument is already in a hard reg, but that reg is
1349                                  * not usable by this instruction, so allocate a new one.
1350                                  */
1351                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1352                                 if (val < 0)
1353                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1354                                 mono_regstate_free_int (rs, val);
1355                                 dest_dreg = val;
1356
1357                                 /* Fall through */
1358                         }
1359                         else
1360                                 dreg_mask &= dreg_fixed_mask;
1361                 }
1362
1363                 if (is_soft_reg (ins->dreg, bank)) {
1364                         val = rs->vassign [ins->dreg];
1365
1366                         if (val < 0) {
1367                                 int spill = 0;
1368                                 if (val < -1) {
1369                                         /* the register gets spilled after this inst */
1370                                         spill = -val -1;
1371                                 }
1372                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1373                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1374                                 if (spill)
1375                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1376                         }
1377
1378                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1379                         ins->dreg = val;
1380                 }
1381
1382                 /* Handle regpairs */
1383                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1384                         int reg2 = prev_dreg + 1;
1385
1386                         g_assert (!bank);
1387                         g_assert (prev_dreg > -1);
1388                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1389                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1390 #ifdef __i386__
1391                         /* bug #80489 */
1392                         mask &= ~regmask (X86_ECX);
1393 #endif
1394                         val = rs->vassign [reg2];
1395                         if (val < 0) {
1396                                 int spill = 0;
1397                                 if (val < -1) {
1398                                         /* the register gets spilled after this inst */
1399                                         spill = -val -1;
1400                                 }
1401                                 val = mono_regstate_alloc_int (rs, mask);
1402                                 if (val < 0)
1403                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1404                                 if (spill)
1405                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1406                         }
1407                         else {
1408                                 if (! (mask & (regmask (val)))) {
1409                                         val = mono_regstate_alloc_int (rs, mask);
1410                                         if (val < 0)
1411                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1412
1413                                         /* Reallocate hreg to the correct register */
1414                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1415
1416                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1417                                 }
1418                         }
1419
1420                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1421                         assign_reg (cfg, rs, reg2, val, bank);
1422
1423                         dreg_high = val;
1424                         ins->backend.reg3 = val;
1425
1426                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1427                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1428                                 mono_regstate_free_int (rs, val);
1429                         }
1430                 }
1431
1432                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1433                         /*
1434                          * In theory, we could free up the hreg even if the vreg is alive,
1435                          * but branches inside bblocks force us to assign the same hreg
1436                          * to a vreg every time it is encountered.
1437                          */
1438                         int dreg = rs->vassign [prev_dreg];
1439                         g_assert (dreg >= 0);
1440                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1441                         if (G_UNLIKELY (bank))
1442                                 mono_regstate_free_general (rs, dreg, bank);
1443                         else
1444                                 mono_regstate_free_int (rs, dreg);
1445                         rs->vassign [prev_dreg] = -1;
1446                 }
1447
1448                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1449                         /* this instruction only outputs to dest_dreg, need to copy */
1450                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1451                         ins->dreg = dest_dreg;
1452
1453                         if (G_UNLIKELY (bank)) {
1454                                 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1455                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1456                         }
1457                         else {
1458                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1459                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1460                         }
1461                 }
1462
1463                 if (spec_dest == 'b') {
1464                         /*
1465                          * The dest reg is read by the instruction, not written, so
1466                          * avoid allocating sreg1/sreg2 to the same reg.
1467                          */
1468                         if (!sreg1_bank (spec))
1469                                 sreg1_mask &= ~ (regmask (ins->dreg));
1470                         if (!sreg2_bank (spec))
1471                                 sreg2_mask &= ~ (regmask (ins->dreg));
1472                 }
1473
1474                 /*
1475                  * TRACK CLOBBERING
1476                  */
1477                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1478                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1479                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1480                         mono_regstate_free_int (rs, clob_reg);
1481                 }
1482
1483                 if (spec [MONO_INST_CLOB] == 'c') {
1484                         int j, s, dreg, dreg2, cur_bank;
1485                         guint64 clob_mask;
1486
1487                         clob_mask = MONO_ARCH_CALLEE_REGS;
1488
1489                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1490                                 /*
1491                                  * Need to avoid spilling the dreg since the dreg is not really
1492                                  * clobbered by the call.
1493                                  */
1494                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1495                                         dreg = rs->vassign [prev_dreg];
1496                                 else
1497                                         dreg = -1;
1498
1499                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1500                                         dreg2 = rs->vassign [prev_dreg + 1];
1501                                 else
1502                                         dreg2 = -1;
1503
1504                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1505                                         s = regmask (j);
1506                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1507                                                 if ((j != dreg) && (j != dreg2))
1508                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1509                                                 else if (rs->isymbolic [j])
1510                                                         /* The hreg is assigned to the dreg of this instruction */
1511                                                         rs->vassign [rs->isymbolic [j]] = -1;
1512                                                 mono_regstate_free_int (rs, j);
1513                                         }
1514                                 }
1515                         }
1516
1517                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1518                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1519                                         clob_mask = regbank_callee_regs [cur_bank];
1520                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1521                                                 dreg = rs->vassign [prev_dreg];
1522                                         else
1523                                                 dreg = -1;
1524
1525                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1526                                                 s = regmask (j);
1527                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1528                                                         if (j != dreg)
1529                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1530                                                         else if (rs->symbolic [cur_bank] [j])
1531                                                                 /* The hreg is assigned to the dreg of this instruction */
1532                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1533                                                         mono_regstate_free_general (rs, j, cur_bank);
1534                                                 }
1535                                         }
1536                                 }
1537                         }
1538                 }
1539
1540                 /*
1541                  * TRACK ARGUMENT REGS
1542                  */
1543                 if (spec [MONO_INST_CLOB] == 'c') {
1544                         MonoCallInst *call = (MonoCallInst*)ins;
1545                         GSList *list;
1546
1547                         /*
1548                          * This needs to be done before assigning sreg1, so sreg1 will
1549                          * not be assigned one of the argument regs.
1550                          */
1551
1552                         /*
1553                          * Assign all registers in call->out_reg_args to the proper
1554                          * argument registers.
1555                          */
1556
1557                         list = call->out_ireg_args;
1558                         if (list) {
1559                                 while (list) {
1560                                         guint32 regpair;
1561                                         int reg, hreg;
1562
1563                                         regpair = (guint32)(gssize)(list->data);
1564                                         hreg = regpair >> 24;
1565                                         reg = regpair & 0xffffff;
1566
1567                                         assign_reg (cfg, rs, reg, hreg, 0);
1568
1569                                         sreg1_mask &= ~(regmask (hreg));
1570
1571                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1572
1573                                         list = g_slist_next (list);
1574                                 }
1575                         }
1576
1577                         list = call->out_freg_args;
1578                         if (list) {
1579                                 while (list) {
1580                                         guint32 regpair;
1581                                         int reg, hreg;
1582
1583                                         regpair = (guint32)(gssize)(list->data);
1584                                         hreg = regpair >> 24;
1585                                         reg = regpair & 0xffffff;
1586
1587                                         assign_reg (cfg, rs, reg, hreg, 1);
1588
1589                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1590
1591                                         list = g_slist_next (list);
1592                                 }
1593                         }
1594                 }
1595
1596                 /*
1597                  * TRACK SREG1
1598                  */
1599                 bank = sreg1_bank (spec);
1600                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1601                         g_assert (is_soft_reg (ins->sreg1, bank));
1602
1603                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1604                         if (dest_sreg1 != -1)
1605                                 g_assert (dest_sreg1 == ins->dreg);
1606                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1607                         g_assert (val >= 0);
1608
1609                         if (rs->vassign [ins->sreg1] >= 0 && rs->vassign [ins->sreg1] != val)
1610                                 // FIXME:
1611                                 g_assert_not_reached ();
1612
1613                         assign_reg (cfg, rs, ins->sreg1, val, bank);
1614
1615                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1616
1617                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1618                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1619                         g_assert (val >= 0);
1620
1621                         if (rs->vassign [ins->sreg1 + 1] >= 0 && rs->vassign [ins->sreg1 + 1] != val)
1622                                 // FIXME:
1623                                 g_assert_not_reached ();
1624
1625                         assign_reg (cfg, rs, ins->sreg1 + 1, val, bank);
1626
1627                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), ins->sreg1 + 1));
1628
1629                         /* Skip rest of this section */
1630                         dest_sreg1 = -1;
1631                 }
1632
1633                 if (sreg1_fixed_mask) {
1634                         g_assert (!bank);
1635                         if (is_global_ireg (ins->sreg1)) {
1636                                 /*
1637                                  * The argument is already in a hard reg, but that reg is
1638                                  * not usable by this instruction, so allocate a new one.
1639                                  */
1640                                 val = mono_regstate_alloc_int (rs, sreg1_fixed_mask);
1641                                 if (val < 0)
1642                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg1_fixed_mask, -1, bank);
1643                                 mono_regstate_free_int (rs, val);
1644                                 dest_sreg1 = val;
1645
1646                                 /* Fall through to the dest_sreg1 != -1 case */
1647                         }
1648                         else
1649                                 sreg1_mask &= sreg1_fixed_mask;
1650                 }
1651
1652                 if (dest_sreg1 != -1) {
1653                         sreg1_mask = regmask (dest_sreg1);
1654
1655                         if ((rs->vassign [ins->sreg1] != dest_sreg1) && !(rs->ifree_mask & (regmask (dest_sreg1)))) {
1656                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg1]));
1657                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sreg1], 0);
1658                                 mono_regstate_free_int (rs, dest_sreg1);
1659                         }
1660                         if (is_global_ireg (ins->sreg1)) {
1661                                 /* The argument is already in a hard reg, need to copy */
1662                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, ins->sreg1, NULL, ip, 0);
1663                                 insert_before_ins (bb, ins, copy);
1664                                 ins->sreg1 = dest_sreg1;
1665                         }
1666                 }
1667
1668                 if (is_soft_reg (ins->sreg1, bank)) {
1669                         val = rs->vassign [ins->sreg1];
1670                         prev_sreg1 = ins->sreg1;
1671                         if (val < 0) {
1672                                 int spill = 0;
1673                                 if (val < -1) {
1674                                         /* the register gets spilled after this inst */
1675                                         spill = -val -1;
1676                                 }
1677
1678                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1679                                         /*
1680                                          * Allocate the same hreg to sreg1 as well so the
1681                                          * peephole can get rid of the move.
1682                                          */
1683                                         sreg1_mask = regmask (ins->dreg);
1684                                 }
1685
1686                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1687                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1688                                         sreg1_mask = regmask (ins->dreg);
1689
1690                                 val = alloc_reg (cfg, bb, tmp, ins, sreg1_mask, ins->sreg1, &reginfo [ins->sreg1], bank);
1691                                 assign_reg (cfg, rs, ins->sreg1, val, bank);
1692                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1693
1694                                 if (spill) {
1695                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg1, tmp, NULL, bank);
1696                                         /*
1697                                          * Need to insert before the instruction since it can
1698                                          * overwrite sreg1.
1699                                          */
1700                                         insert_before_ins (bb, ins, store);
1701                                 }
1702                         }
1703                         else if ((dest_sreg1 != -1) && (dest_sreg1 != val)) {
1704                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, val, NULL, ip, bank);
1705                                 insert_before_ins (bb, ins, copy);
1706                                 sreg2_mask &= ~(regmask (dest_sreg1));
1707                                 val = dest_sreg1;
1708                         }
1709
1710                         ins->sreg1 = val;
1711                 }
1712                 else {
1713                         prev_sreg1 = -1;
1714                 }
1715                 sreg2_mask &= ~(regmask (ins->sreg1));
1716
1717                 /* Handle the case when sreg1 is a regpair but dreg is not */
1718                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1719                         int reg2 = prev_sreg1 + 1;
1720
1721                         g_assert (!bank);
1722                         g_assert (prev_sreg1 > -1);
1723                         g_assert (!is_global_ireg (rs->vassign [prev_sreg1]));
1724                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sreg1]);
1725                         val = rs->vassign [reg2];
1726                         if (val < 0) {
1727                                 int spill = 0;
1728                                 if (val < -1) {
1729                                         /* the register gets spilled after this inst */
1730                                         spill = -val -1;
1731                                 }
1732                                 val = mono_regstate_alloc_int (rs, mask);
1733                                 if (val < 0)
1734                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1735                                 if (spill)
1736                                         g_assert_not_reached ();
1737                         }
1738                         else {
1739                                 if (! (mask & (regmask (val)))) {
1740                                         /* The vreg is already allocated to a wrong hreg */
1741                                         /* FIXME: */
1742                                         g_assert_not_reached ();
1743 #if 0
1744                                         val = mono_regstate_alloc_int (rs, mask);
1745                                         if (val < 0)
1746                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1747
1748                                         /* Reallocate hreg to the correct register */
1749                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1750
1751                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1752 #endif
1753                                 }
1754                         }
1755
1756                         sreg1_high = val;
1757                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1758                         assign_reg (cfg, rs, reg2, val, bank);
1759                 }
1760
1761                 /* Handle dreg==sreg1 */
1762                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != ins->sreg1) {
1763                         MonoInst *sreg2_copy = NULL;
1764                         MonoInst *copy;
1765                         int bank = reg_bank (spec_src1);
1766
1767                         if (ins->dreg == ins->sreg2) {
1768                                 /*
1769                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1770                                  * register for it.
1771                                  */
1772                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->sreg2, NULL, bank);
1773
1774                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (ins->sreg2, bank), mono_regname_full (reg2, bank)));
1775                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, ins->sreg2, NULL, ip, bank);
1776                                 prev_sreg2 = ins->sreg2 = reg2;
1777
1778                                 if (G_UNLIKELY (bank))
1779                                         mono_regstate_free_general (rs, reg2, bank);
1780                                 else
1781                                         mono_regstate_free_int (rs, reg2);
1782                         }
1783
1784                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1785                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1786                                 if (rs->vassign [prev_sreg1 + 1] == ins->sreg2)
1787                                         /* FIXME: */
1788                                         g_assert_not_reached ();
1789
1790                                 /*
1791                                  * sreg1 and dest are already allocated to the same regpair by the
1792                                  * SREG1 allocation code.
1793                                  */
1794                                 g_assert (ins->sreg1 == ins->dreg);
1795                                 g_assert (dreg_high == sreg1_high);
1796                         }
1797
1798                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (ins->sreg1, bank), mono_regname_full (ins->dreg, bank)));
1799                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, ins->sreg1, NULL, ip, bank);
1800                         insert_before_ins (bb, ins, copy);
1801
1802                         if (sreg2_copy)
1803                                 insert_before_ins (bb, copy, sreg2_copy);
1804
1805                         /*
1806                          * Need to prevent sreg2 to be allocated to sreg1, since that
1807                          * would screw up the previous copy.
1808                          */
1809                         sreg2_mask &= ~ (regmask (ins->sreg1));
1810                         /* we set sreg1 to dest as well */
1811                         prev_sreg1 = ins->sreg1 = ins->dreg;
1812                         sreg2_mask &= ~ (regmask (ins->dreg));
1813                 }
1814
1815                 /*
1816                  * TRACK SREG2
1817                  */
1818                 bank = sreg2_bank (spec);
1819                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src2))
1820                         g_assert_not_reached ();
1821                 if (is_soft_reg (ins->sreg2, bank)) {
1822                         val = rs->vassign [ins->sreg2];
1823
1824                         if (val < 0) {
1825                                 int spill = 0;
1826                                 if (val < -1) {
1827                                         /* the register gets spilled after this inst */
1828                                         spill = -val -1;
1829                                 }
1830                                 val = alloc_reg (cfg, bb, tmp, ins, sreg2_mask, ins->sreg2, &reginfo [ins->sreg2], bank);
1831                                 assign_reg (cfg, rs, ins->sreg2, val, bank);
1832                                 DEBUG (printf ("\tassigned sreg2 %s to R%d\n", mono_regname_full (val, bank), ins->sreg2));
1833                                 if (spill) {
1834                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg2, tmp, NULL, bank);
1835                                         /*
1836                                          * Need to insert before the instruction since it can
1837                                          * overwrite sreg2.
1838                                          */
1839                                         insert_before_ins (bb, ins, store);
1840                                 }
1841                         }
1842                         ins->sreg2 = val;
1843                 }
1844                 else {
1845                         prev_sreg2 = -1;
1846                 }
1847
1848                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1849                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1850                         mono_regstate_free_int (rs, ins->sreg1);
1851                 }
1852                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1853                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1854                         mono_regstate_free_int (rs, ins->sreg2);
1855                 }*/
1856
1857                 DEBUG (mono_print_ins_index (i, ins));
1858         }
1859
1860         // FIXME: Set MAX_FREGS to 8
1861         // FIXME: Optimize generated code
1862 #if MONO_ARCH_USE_FPSTACK
1863         /*
1864          * Make a forward pass over the code, simulating the fp stack, making sure the
1865          * arguments required by the fp opcodes are at the top of the stack.
1866          */
1867         if (has_fp) {
1868                 MonoInst *prev = NULL;
1869                 MonoInst *fxch;
1870                 int tmp;
1871
1872                 for (ins = bb->code; ins; ins = ins->next) {
1873                         spec = ins_get_spec (ins->opcode);
1874
1875                         DEBUG (printf ("processing:"));
1876                         DEBUG (mono_print_ins_index (0, ins));
1877
1878                         if (ins->opcode == OP_FMOVE) {
1879                                 /* Do it by renaming the source to the destination on the stack */
1880                                 // FIXME: Is this correct ?
1881                                 for (i = 0; i < sp; ++i)
1882                                         if (fpstack [i] == ins->sreg1)
1883                                                 fpstack [i] = ins->dreg;
1884                                 prev = ins;
1885                                 continue;
1886                         }
1887
1888                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1889                                 /* Arg1 must be in %st(1) */
1890                                 g_assert (prev);
1891
1892                                 i = 0;
1893                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
1894                                         i ++;
1895                                 g_assert (i < sp);
1896
1897                                 if (sp - 1 - i > 0) {
1898                                         /* First move it to %st(0) */
1899                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1900
1901                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1902                                         fxch->inst_imm = sp - 1 - i;
1903
1904                                         prev->next = fxch;
1905                                         fxch->next = ins;
1906                                         prev = fxch;
1907
1908                                         tmp = fpstack [sp - 1];
1909                                         fpstack [sp - 1] = fpstack [i];
1910                                         fpstack [i] = tmp;
1911                                 }
1912
1913                                 /* Then move it to %st(1) */
1914                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1915
1916                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1917                                 fxch->inst_imm = 1;
1918
1919                                 prev->next = fxch;
1920                                 fxch->next = ins;
1921                                 prev = fxch;
1922
1923                                 tmp = fpstack [sp - 1];
1924                                 fpstack [sp - 1] = fpstack [sp - 2];
1925                                 fpstack [sp - 2] = tmp;
1926                         }
1927
1928                         if (sreg2_is_fp (spec)) {
1929                                 g_assert (sp > 0);
1930
1931                                 if (fpstack [sp - 1] != ins->sreg2) {
1932                                         g_assert (prev);
1933
1934                                         i = 0;
1935                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
1936                                                 i ++;
1937                                         g_assert (i < sp);
1938
1939                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1940
1941                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1942                                         fxch->inst_imm = sp - 1 - i;
1943
1944                                         prev->next = fxch;
1945                                         fxch->next = ins;
1946                                         prev = fxch;
1947
1948                                         tmp = fpstack [sp - 1];
1949                                         fpstack [sp - 1] = fpstack [i];
1950                                         fpstack [i] = tmp;
1951                                 }
1952
1953                                 sp --;
1954                         }
1955
1956                         if (sreg1_is_fp (spec)) {
1957                                 g_assert (sp > 0);
1958
1959                                 if (fpstack [sp - 1] != ins->sreg1) {
1960                                         g_assert (prev);
1961
1962                                         i = 0;
1963                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
1964                                                 i ++;
1965                                         g_assert (i < sp);
1966
1967                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1968
1969                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1970                                         fxch->inst_imm = sp - 1 - i;
1971
1972                                         prev->next = fxch;
1973                                         fxch->next = ins;
1974                                         prev = fxch;
1975
1976                                         tmp = fpstack [sp - 1];
1977                                         fpstack [sp - 1] = fpstack [i];
1978                                         fpstack [i] = tmp;
1979                                 }
1980
1981                                 sp --;
1982                         }
1983
1984                         if (dreg_is_fp (spec)) {
1985                                 g_assert (sp < 8);
1986                                 fpstack [sp ++] = ins->dreg;
1987                         }
1988
1989                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
1990                                 printf ("\t[");
1991                                 for (i = 0; i < sp; ++i)
1992                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
1993                                 printf ("]\n");
1994                         }
1995
1996                         prev = ins;
1997                 }
1998
1999                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2000                         /* Remove remaining items from the fp stack */
2001                         /*
2002                          * These can remain for example as a result of a dead fmove like in
2003                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2004                          */
2005                         while (sp) {
2006                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2007                                 mono_add_ins_to_end (bb, ins);
2008                                 sp --;
2009                         }
2010                 }
2011         }
2012 #endif
2013 }
2014
2015 CompRelation
2016 mono_opcode_to_cond (int opcode)
2017 {
2018         switch (opcode) {
2019         case CEE_BEQ:
2020         case OP_CEQ:
2021         case OP_IBEQ:
2022         case OP_ICEQ:
2023         case OP_LBEQ:
2024         case OP_LCEQ:
2025         case OP_FBEQ:
2026         case OP_FCEQ:
2027         case OP_COND_EXC_EQ:
2028         case OP_COND_EXC_IEQ:
2029         case OP_CMOV_IEQ:
2030         case OP_CMOV_LEQ:
2031                 return CMP_EQ;
2032         case CEE_BNE_UN:
2033         case OP_IBNE_UN:
2034         case OP_LBNE_UN:
2035         case OP_FBNE_UN:
2036         case OP_COND_EXC_NE_UN:
2037         case OP_COND_EXC_INE_UN:
2038         case OP_CMOV_INE_UN:
2039         case OP_CMOV_LNE_UN:
2040                 return CMP_NE;
2041         case CEE_BLE:
2042         case OP_IBLE:
2043         case OP_LBLE:
2044         case OP_FBLE:
2045         case OP_CMOV_ILE:
2046         case OP_CMOV_LLE:
2047                 return CMP_LE;
2048         case CEE_BGE:
2049         case OP_IBGE:
2050         case OP_LBGE:
2051         case OP_FBGE:
2052         case OP_CMOV_IGE:
2053         case OP_CMOV_LGE:
2054                 return CMP_GE;
2055         case CEE_BLT:
2056         case OP_CLT:
2057         case OP_IBLT:
2058         case OP_ICLT:
2059         case OP_LBLT:
2060         case OP_LCLT:
2061         case OP_FBLT:
2062         case OP_FCLT:
2063         case OP_COND_EXC_LT:
2064         case OP_COND_EXC_ILT:
2065         case OP_CMOV_ILT:
2066         case OP_CMOV_LLT:
2067                 return CMP_LT;
2068         case CEE_BGT:
2069         case OP_CGT:
2070         case OP_IBGT:
2071         case OP_ICGT:
2072         case OP_LBGT:
2073         case OP_LCGT:
2074         case OP_FBGT:
2075         case OP_FCGT:
2076         case OP_COND_EXC_GT:
2077         case OP_COND_EXC_IGT:
2078         case OP_CMOV_IGT:
2079         case OP_CMOV_LGT:
2080                 return CMP_GT;
2081
2082         case CEE_BLE_UN:
2083         case OP_IBLE_UN:
2084         case OP_LBLE_UN:
2085         case OP_FBLE_UN:
2086         case OP_COND_EXC_LE_UN:
2087         case OP_COND_EXC_ILE_UN:
2088         case OP_CMOV_ILE_UN:
2089         case OP_CMOV_LLE_UN:
2090                 return CMP_LE_UN;
2091         case CEE_BGE_UN:
2092         case OP_IBGE_UN:
2093         case OP_LBGE_UN:
2094         case OP_FBGE_UN:
2095         case OP_CMOV_IGE_UN:
2096         case OP_CMOV_LGE_UN:
2097                 return CMP_GE_UN;
2098         case CEE_BLT_UN:
2099         case OP_CLT_UN:
2100         case OP_IBLT_UN:
2101         case OP_ICLT_UN:
2102         case OP_LBLT_UN:
2103         case OP_LCLT_UN:
2104         case OP_FBLT_UN:
2105         case OP_FCLT_UN:
2106         case OP_COND_EXC_LT_UN:
2107         case OP_COND_EXC_ILT_UN:
2108         case OP_CMOV_ILT_UN:
2109         case OP_CMOV_LLT_UN:
2110                 return CMP_LT_UN;
2111         case CEE_BGT_UN:
2112         case OP_CGT_UN:
2113         case OP_IBGT_UN:
2114         case OP_ICGT_UN:
2115         case OP_LBGT_UN:
2116         case OP_LCGT_UN:
2117         case OP_FCGT_UN:
2118         case OP_FBGT_UN:
2119         case OP_COND_EXC_GT_UN:
2120         case OP_COND_EXC_IGT_UN:
2121         case OP_CMOV_IGT_UN:
2122         case OP_CMOV_LGT_UN:
2123                 return CMP_GT_UN;
2124         default:
2125                 printf ("%s\n", mono_inst_name (opcode));
2126                 g_assert_not_reached ();
2127                 return 0;
2128         }
2129 }
2130
2131 CompRelation
2132 mono_negate_cond (CompRelation cond)
2133 {
2134         switch (cond) {
2135         case CMP_EQ:
2136                 return CMP_NE;
2137         case CMP_NE:
2138                 return CMP_EQ;
2139         case CMP_LE:
2140                 return CMP_GT;
2141         case CMP_GE:
2142                 return CMP_LT;
2143         case CMP_LT:
2144                 return CMP_GE;
2145         case CMP_GT:
2146                 return CMP_LE;
2147         case CMP_LE_UN:
2148                 return CMP_GT_UN;
2149         case CMP_GE_UN:
2150                 return CMP_LT_UN;
2151         case CMP_LT_UN:
2152                 return CMP_GE_UN;
2153         case CMP_GT_UN:
2154                 return CMP_LE_UN;
2155         default:
2156                 g_assert_not_reached ();
2157         }
2158 }
2159
2160 CompType
2161 mono_opcode_to_type (int opcode, int cmp_opcode)
2162 {
2163         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2164                 return CMP_TYPE_L;
2165         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2166                 return CMP_TYPE_L;
2167         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2168                 return CMP_TYPE_I;
2169         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2170                 return CMP_TYPE_I;
2171         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2172                 return CMP_TYPE_L;
2173         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2174                 return CMP_TYPE_L;
2175         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2176                 return CMP_TYPE_F;
2177         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2178                 return CMP_TYPE_F;
2179         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2180                 return CMP_TYPE_I;
2181         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2182                 switch (cmp_opcode) {
2183                 case OP_ICOMPARE:
2184                 case OP_ICOMPARE_IMM:
2185                 case OP_LCOMPARE_IMM:
2186                         return CMP_TYPE_I;
2187                 default:
2188                         return CMP_TYPE_L;
2189                 }
2190         } else {
2191                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2192                 return 0;
2193         }
2194 }
2195
2196 gboolean
2197 mono_is_regsize_var (MonoType *t)
2198 {
2199         if (t->byref)
2200                 return TRUE;
2201         t = mono_type_get_underlying_type (t);
2202         switch (t->type) {
2203         case MONO_TYPE_BOOLEAN:
2204         case MONO_TYPE_CHAR:
2205         case MONO_TYPE_I1:
2206         case MONO_TYPE_U1:
2207         case MONO_TYPE_I2:
2208         case MONO_TYPE_U2:
2209         case MONO_TYPE_I4:
2210         case MONO_TYPE_U4:
2211         case MONO_TYPE_I:
2212         case MONO_TYPE_U:
2213         case MONO_TYPE_PTR:
2214         case MONO_TYPE_FNPTR:
2215 #if SIZEOF_VOID_P == 8
2216         case MONO_TYPE_I8:
2217         case MONO_TYPE_U8:
2218 #endif
2219                 return TRUE;
2220         case MONO_TYPE_OBJECT:
2221         case MONO_TYPE_STRING:
2222         case MONO_TYPE_CLASS:
2223         case MONO_TYPE_SZARRAY:
2224         case MONO_TYPE_ARRAY:
2225                 return TRUE;
2226         case MONO_TYPE_GENERICINST:
2227                 if (!mono_type_generic_inst_is_valuetype (t))
2228                         return TRUE;
2229                 return FALSE;
2230         case MONO_TYPE_VALUETYPE:
2231                 return FALSE;
2232         }
2233         return FALSE;
2234 }
2235
2236 /*
2237  * mono_peephole_ins:
2238  *
2239  *   Perform some architecture independent peephole optimizations.
2240  */
2241 void
2242 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2243 {
2244         MonoInst *last_ins = ins->prev;
2245
2246         switch (ins->opcode) {
2247         case OP_MUL_IMM:
2248                 /* remove unnecessary multiplication with 1 */
2249                 if (ins->inst_imm == 1) {
2250                         if (ins->dreg != ins->sreg1)
2251                                 ins->opcode = OP_MOVE;
2252                         else
2253                                 MONO_DELETE_INS (bb, ins);
2254                 }
2255                 break;
2256         case OP_LOAD_MEMBASE:
2257         case OP_LOADI4_MEMBASE:
2258                 /*
2259                  * Note: if reg1 = reg2 the load op is removed
2260                  *
2261                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2262                  * OP_LOAD_MEMBASE offset(basereg), reg2
2263                  * -->
2264                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2265                  * OP_MOVE reg1, reg2
2266                  */
2267                 if (last_ins &&
2268                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2269                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2270                         ins->inst_basereg == last_ins->inst_destbasereg &&
2271                         ins->inst_offset == last_ins->inst_offset) {
2272                         if (ins->dreg == last_ins->sreg1) {
2273                                 MONO_DELETE_INS (bb, ins);
2274                                 break;
2275                         } else {
2276                                 ins->opcode = OP_MOVE;
2277                                 ins->sreg1 = last_ins->sreg1;
2278                         }
2279
2280                         /*
2281                          * Note: reg1 must be different from the basereg in the second load
2282                          * Note: if reg1 = reg2 is equal then second load is removed
2283                          *
2284                          * OP_LOAD_MEMBASE offset(basereg), reg1
2285                          * OP_LOAD_MEMBASE offset(basereg), reg2
2286                          * -->
2287                          * OP_LOAD_MEMBASE offset(basereg), reg1
2288                          * OP_MOVE reg1, reg2
2289                          */
2290                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2291                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2292                           ins->inst_basereg != last_ins->dreg &&
2293                           ins->inst_basereg == last_ins->inst_basereg &&
2294                           ins->inst_offset == last_ins->inst_offset) {
2295
2296                         if (ins->dreg == last_ins->dreg) {
2297                                 MONO_DELETE_INS (bb, ins);
2298                         } else {
2299                                 ins->opcode = OP_MOVE;
2300                                 ins->sreg1 = last_ins->dreg;
2301                         }
2302
2303                         //g_assert_not_reached ();
2304
2305 #if 0
2306                         /*
2307                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2308                          * OP_LOAD_MEMBASE offset(basereg), reg
2309                          * -->
2310                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2311                          * OP_ICONST reg, imm
2312                          */
2313                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2314                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2315                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2316                                    ins->inst_offset == last_ins->inst_offset) {
2317                         ins->opcode = OP_ICONST;
2318                         ins->inst_c0 = last_ins->inst_imm;
2319                         g_assert_not_reached (); // check this rule
2320 #endif
2321                 }
2322                 break;
2323         case OP_LOADI1_MEMBASE:
2324         case OP_LOADU1_MEMBASE:
2325                 /*
2326                  * Note: if reg1 = reg2 the load op is removed
2327                  *
2328                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2329                  * OP_LOAD_MEMBASE offset(basereg), reg2
2330                  * -->
2331                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2332                  * OP_MOVE reg1, reg2
2333                  */
2334                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2335                         ins->inst_basereg == last_ins->inst_destbasereg &&
2336                         ins->inst_offset == last_ins->inst_offset) {
2337                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2338                         ins->sreg1 = last_ins->sreg1;
2339                 }
2340                 break;
2341         case OP_LOADI2_MEMBASE:
2342         case OP_LOADU2_MEMBASE:
2343                 /*
2344                  * Note: if reg1 = reg2 the load op is removed
2345                  *
2346                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2347                  * OP_LOAD_MEMBASE offset(basereg), reg2
2348                  * -->
2349                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2350                  * OP_MOVE reg1, reg2
2351                  */
2352                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2353                         ins->inst_basereg == last_ins->inst_destbasereg &&
2354                         ins->inst_offset == last_ins->inst_offset) {
2355 #if SIZEOF_VOID_P == 8
2356                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2357 #else
2358                         /* The definition of OP_PCONV_TO_U2 is wrong */
2359                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2360 #endif
2361                         ins->sreg1 = last_ins->sreg1;
2362                 }
2363                 break;
2364         case OP_MOVE:
2365         case OP_FMOVE:
2366                 /*
2367                  * Removes:
2368                  *
2369                  * OP_MOVE reg, reg
2370                  */
2371                 if (ins->dreg == ins->sreg1) {
2372                         MONO_DELETE_INS (bb, ins);
2373                         break;
2374                 }
2375                 /*
2376                  * Removes:
2377                  *
2378                  * OP_MOVE sreg, dreg
2379                  * OP_MOVE dreg, sreg
2380                  */
2381                 if (last_ins && last_ins->opcode == OP_MOVE &&
2382                         ins->sreg1 == last_ins->dreg &&
2383                         ins->dreg == last_ins->sreg1) {
2384                         MONO_DELETE_INS (bb, ins);
2385                 }
2386                 break;
2387         case OP_NOP:
2388                 MONO_DELETE_INS (bb, ins);
2389                 break;
2390         }
2391 }
2392