mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 const char*
 423 mono_ji_type_to_string (MonoJumpInfoType type)
 424 {
 425         return patch_info_str [type];
 426 }
 427
 428 void
 429 mono_print_ji (const MonoJumpInfo *ji)
 430 {
 431         switch (ji->type) {
 432         case MONO_PATCH_INFO_RGCTX_FETCH: {
 433                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 434
 435                 printf ("[RGCTX_FETCH ");
 436                 mono_print_ji (entry->data);
 437                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 438                 break;
 439         }
 440         case MONO_PATCH_INFO_METHODCONST: {
 441                 char *s = mono_method_full_name (ji->data.method, TRUE);
 442                 printf ("[METHODCONST - %s]", s);
 443                 g_free (s);
 444                 break;
 445         }
 446         case MONO_PATCH_INFO_INTERNAL_METHOD: {
 447                 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
 448                 break;
 449         }
 450         default:
 451                 printf ("[%s]", patch_info_str [ji->type]);
 452                 break;
 453         }
 454 }
 455
 456 void
 457 mono_print_ins_index (int i, MonoInst *ins)
 458 {
 459         GString *buf = mono_print_ins_index_strbuf (i, ins);
 460         printf ("%s\n", buf->str);
 461         g_string_free (buf, TRUE);
 462 }
 463
 464 GString *
 465 mono_print_ins_index_strbuf (int i, MonoInst *ins)
 466 {
 467         const char *spec = ins_get_spec (ins->opcode);
 468         GString *sbuf = g_string_new (NULL);
 469         int num_sregs, j;
 470         int sregs [MONO_MAX_SRC_REGS];
 471
 472         if (i != -1)
 473                 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
 474         else
 475                 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
 476         if (spec == MONO_ARCH_CPU_SPEC) {
 477                 gboolean dest_base = FALSE;
 478                 switch (ins->opcode) {
 479                 case OP_STOREV_MEMBASE:
 480                         dest_base = TRUE;
 481                         break;
 482                 default:
 483                         break;
 484                 }
 485
 486                 /* This is a lowered opcode */
 487                 if (ins->dreg != -1) {
 488                         if (dest_base)
 489                                 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 490                         else
 491                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 492                 }
 493                 if (ins->sreg1 != -1)
 494                         g_string_append_printf (sbuf, " R%d", ins->sreg1);
 495                 if (ins->sreg2 != -1)
 496                         g_string_append_printf (sbuf, " R%d", ins->sreg2);
 497                 if (ins->sreg3 != -1)
 498                         g_string_append_printf (sbuf, " R%d", ins->sreg3);
 499
 500                 switch (ins->opcode) {
 501                 case OP_LBNE_UN:
 502                 case OP_LBEQ:
 503                 case OP_LBLT:
 504                 case OP_LBLT_UN:
 505                 case OP_LBGT:
 506                 case OP_LBGT_UN:
 507                 case OP_LBGE:
 508                 case OP_LBGE_UN:
 509                 case OP_LBLE:
 510                 case OP_LBLE_UN:
 511                         if (!ins->inst_false_bb)
 512                                 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 513                         else
 514                                 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 515                         break;
 516                 case OP_PHI:
 517                 case OP_VPHI:
 518                 case OP_XPHI:
 519                 case OP_FPHI: {
 520                         int i;
 521                         g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
 522                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 523                                 if (i)
 524                                         g_string_append_printf (sbuf, ", ");
 525                                 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
 526                         }
 527                         g_string_append_printf (sbuf, ")]");
 528                         break;
 529                 }
 530                 case OP_LDADDR:
 531                 case OP_OUTARG_VTRETADDR:
 532                         g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
 533                         break;
 534                 case OP_REGOFFSET:
 535                 case OP_GSHAREDVT_ARG_REGOFFSET:
 536                         g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
 537                         break;
 538                 default:
 539                         break;
 540                 }
 541
 542                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 543                 return sbuf;
 544         }
 545
 546         if (spec [MONO_INST_DEST]) {
 547                 int bank = dreg_bank (spec);
 548                 if (is_soft_reg (ins->dreg, bank)) {
 549                         if (spec [MONO_INST_DEST] == 'b') {
 550                                 if (ins->inst_offset == 0)
 551                                         g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
 552                                 else
 553                                         g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 554                         }
 555                         else
 556                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 557                 } else if (spec [MONO_INST_DEST] == 'b') {
 558                         if (ins->inst_offset == 0)
 559                                 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
 560                         else
 561                                 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 562                 } else
 563                         g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
 564         }
 565         if (spec [MONO_INST_SRC1]) {
 566                 int bank = sreg1_bank (spec);
 567                 if (is_soft_reg (ins->sreg1, bank)) {
 568                         if (spec [MONO_INST_SRC1] == 'b')
 569                                 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 570                         else
 571                                 g_string_append_printf (sbuf, " R%d", ins->sreg1);
 572                 } else if (spec [MONO_INST_SRC1] == 'b')
 573                         g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 574                 else
 575                         g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
 576         }
 577         num_sregs = mono_inst_get_src_registers (ins, sregs);
 578         for (j = 1; j < num_sregs; ++j) {
 579                 int bank = sreg_bank (j, spec);
 580                 if (is_soft_reg (sregs [j], bank))
 581                         g_string_append_printf (sbuf, " R%d", sregs [j]);
 582                 else
 583                         g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
 584         }
 585
 586         switch (ins->opcode) {
 587         case OP_ICONST:
 588                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
 589                 break;
 590 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 591         case OP_X86_PUSH_IMM:
 592 #endif
 593         case OP_ICOMPARE_IMM:
 594         case OP_COMPARE_IMM:
 595         case OP_IADD_IMM:
 596         case OP_ISUB_IMM:
 597         case OP_IAND_IMM:
 598         case OP_IOR_IMM:
 599         case OP_IXOR_IMM:
 600         case OP_SUB_IMM:
 601         case OP_STORE_MEMBASE_IMM:
 602                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
 603                 break;
 604         case OP_ADD_IMM:
 605         case OP_LADD_IMM:
 606                 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
 607                 break;
 608         case OP_I8CONST:
 609                 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
 610                 break;
 611         case OP_R8CONST:
 612                 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
 613                 break;
 614         case OP_R4CONST:
 615                 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
 616                 break;
 617         case OP_CALL:
 618         case OP_CALL_MEMBASE:
 619         case OP_CALL_REG:
 620         case OP_FCALL:
 621         case OP_LCALL:
 622         case OP_VCALL:
 623         case OP_VCALL_REG:
 624         case OP_VCALL_MEMBASE:
 625         case OP_VCALL2:
 626         case OP_VCALL2_REG:
 627         case OP_VCALL2_MEMBASE:
 628         case OP_VOIDCALL:
 629         case OP_VOIDCALL_MEMBASE:
 630         case OP_TAILCALL: {
 631                 MonoCallInst *call = (MonoCallInst*)ins;
 632                 GSList *list;
 633
 634                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 635                         /*
 636                          * These are lowered opcodes, but they are in the .md files since the old
 637                          * JIT passes them to backends.
 638                          */
 639                         if (ins->dreg != -1)
 640                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 641                 }
 642
 643                 if (call->method) {
 644                         char *full_name = mono_method_full_name (call->method, TRUE);
 645                         g_string_append_printf (sbuf, " [%s]", full_name);
 646                         g_free (full_name);
 647                 } else if (call->fptr_is_patch) {
 648                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 649
 650                         g_string_append_printf (sbuf, " ");
 651                         mono_print_ji (ji);
 652                 } else if (call->fptr) {
 653                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 654                         if (info)
 655                                 g_string_append_printf (sbuf, " [%s]", info->name);
 656                 }
 657
 658                 list = call->out_ireg_args;
 659                 while (list) {
 660                         guint32 regpair;
 661                         int reg, hreg;
 662
 663                         regpair = (guint32)(gssize)(list->data);
 664                         hreg = regpair >> 24;
 665                         reg = regpair & 0xffffff;
 666
 667                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
 668
 669                         list = g_slist_next (list);
 670                 }
 671                 list = call->out_freg_args;
 672                 while (list) {
 673                         guint32 regpair;
 674                         int reg, hreg;
 675
 676                         regpair = (guint32)(gssize)(list->data);
 677                         hreg = regpair >> 24;
 678                         reg = regpair & 0xffffff;
 679
 680                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
 681
 682                         list = g_slist_next (list);
 683                 }
 684                 break;
 685         }
 686         case OP_BR:
 687         case OP_CALL_HANDLER:
 688                 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
 689                 break;
 690         case OP_IBNE_UN:
 691         case OP_IBEQ:
 692         case OP_IBLT:
 693         case OP_IBLT_UN:
 694         case OP_IBGT:
 695         case OP_IBGT_UN:
 696         case OP_IBGE:
 697         case OP_IBGE_UN:
 698         case OP_IBLE:
 699         case OP_IBLE_UN:
 700         case OP_LBNE_UN:
 701         case OP_LBEQ:
 702         case OP_LBLT:
 703         case OP_LBLT_UN:
 704         case OP_LBGT:
 705         case OP_LBGT_UN:
 706         case OP_LBGE:
 707         case OP_LBGE_UN:
 708         case OP_LBLE:
 709         case OP_LBLE_UN:
 710                 if (!ins->inst_false_bb)
 711                         g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 712                 else
 713                         g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 714                 break;
 715         case OP_LIVERANGE_START:
 716         case OP_LIVERANGE_END:
 717         case OP_GC_LIVENESS_DEF:
 718         case OP_GC_LIVENESS_USE:
 719                 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
 720                 break;
 721         case OP_IL_SEQ_POINT:
 722         case OP_SEQ_POINT:
 723                 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 724                 break;
 725         default:
 726                 break;
 727         }
 728
 729         if (spec [MONO_INST_CLOB])
 730                 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
 731         return sbuf;
 732 }
 733
 734 static void
 735 print_regtrack (RegTrack *t, int num)
 736 {
 737         int i;
 738         char buf [32];
 739         const char *r;
 740
 741         for (i = 0; i < num; ++i) {
 742                 if (!t [i].born_in)
 743                         continue;
 744                 if (i >= MONO_MAX_IREGS) {
 745                         g_snprintf (buf, sizeof(buf), "R%d", i);
 746                         r = buf;
 747                 } else
 748                         r = mono_arch_regname (i);
 749                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 750         }
 751 }
 752 #else
 753
 754 const char*
 755 mono_ji_type_to_string (MonoJumpInfoType type)
 756 {
 757         return "";
 758 }
 759
 760 void
 761 mono_print_ji (const MonoJumpInfo *ji)
 762 {
 763 }
 764
 765 void
 766 mono_print_ins_index (int i, MonoInst *ins)
 767 {
 768 }
 769 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 770
 771 void
 772 mono_print_ins (MonoInst *ins)
 773 {
 774         mono_print_ins_index (-1, ins);
 775 }
 776
 777 static inline void
 778 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 779 {
 780         /*
 781          * If this function is called multiple times, the new instructions are inserted
 782          * in the proper order.
 783          */
 784         mono_bblock_insert_before_ins (bb, ins, to_insert);
 785 }
 786
 787 static inline void
 788 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 789 {
 790         /*
 791          * If this function is called multiple times, the new instructions are inserted in
 792          * proper order.
 793          */
 794         mono_bblock_insert_after_ins (bb, *last, to_insert);
 795
 796         *last = to_insert;
 797 }
 798
 799 static inline int
 800 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 801 {
 802         if (vreg_is_ref (cfg, reg))
 803                 return MONO_REG_INT_REF;
 804         else if (vreg_is_mp (cfg, reg))
 805                 return MONO_REG_INT_MP;
 806         else
 807                 return bank;
 808 }
 809
 810 /*
 811  * Force the spilling of the variable in the symbolic register 'reg', and free
 812  * the hreg it was assigned to.
 813  */
 814 static void
 815 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 816 {
 817         MonoInst *load;
 818         int i, sel, spill;
 819         MonoRegState *rs = cfg->rs;
 820
 821         sel = rs->vassign [reg];
 822
 823         /* the vreg we need to spill lives in another logical reg bank */
 824         bank = translate_bank (cfg->rs, bank, sel);
 825
 826         /*i = rs->isymbolic [sel];
 827         g_assert (i == reg);*/
 828         i = reg;
 829         spill = ++cfg->spill_count;
 830         rs->vassign [i] = -spill - 1;
 831         if (G_UNLIKELY (bank))
 832                 mono_regstate_free_general (rs, sel, bank);
 833         else
 834                 mono_regstate_free_int (rs, sel);
 835         /* we need to create a spill var and insert a load to sel after the current instruction */
 836         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 837         load->dreg = sel;
 838         load->inst_basereg = cfg->frame_reg;
 839         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 840         insert_after_ins (bb, ins, last, load);
 841         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 842         if (G_UNLIKELY (bank))
 843                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 844         else
 845                 i = mono_regstate_alloc_int (rs, regmask (sel));
 846         g_assert (i == sel);
 847
 848         if (G_UNLIKELY (bank))
 849                 mono_regstate_free_general (rs, sel, bank);
 850         else
 851                 mono_regstate_free_int (rs, sel);
 852 }
 853
 854 /* This isn't defined on older glib versions and on some platforms */
 855 #ifndef G_GUINT64_FORMAT
 856 #define G_GUINT64_FORMAT "ul"
 857 #endif
 858
 859 static int
 860 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 861 {
 862         MonoInst *load;
 863         int i, sel, spill, num_sregs;
 864         int sregs [MONO_MAX_SRC_REGS];
 865         MonoRegState *rs = cfg->rs;
 866
 867         g_assert (bank < MONO_NUM_REGBANKS);
 868
 869         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 870         /* exclude the registers in the current instruction */
 871         num_sregs = mono_inst_get_src_registers (ins, sregs);
 872         for (i = 0; i < num_sregs; ++i) {
 873                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 874                         if (is_soft_reg (sregs [i], bank))
 875                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 876                         else
 877                                 regmask &= ~ (regmask (sregs [i]));
 878                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 879                 }
 880         }
 881         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 882                 regmask &= ~ (regmask (ins->dreg));
 883                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 884         }
 885
 886         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 887         g_assert (regmask); /* need at least a register we can free */
 888         sel = 0;
 889         /* we should track prev_use and spill the register that's farther */
 890         if (G_UNLIKELY (bank)) {
 891                 for (i = 0; i < regbank_size [bank]; ++i) {
 892                         if (regmask & (regmask (i))) {
 893                                 sel = i;
 894
 895                                 /* the vreg we need to load lives in another logical bank */
 896                                 bank = translate_bank (cfg->rs, bank, sel);
 897
 898                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 899                                 break;
 900                         }
 901                 }
 902
 903                 i = rs->symbolic [bank] [sel];
 904                 spill = ++cfg->spill_count;
 905                 rs->vassign [i] = -spill - 1;
 906                 mono_regstate_free_general (rs, sel, bank);
 907         }
 908         else {
 909                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 910                         if (regmask & (regmask (i))) {
 911                                 sel = i;
 912                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 913                                 break;
 914                         }
 915                 }
 916
 917                 i = rs->isymbolic [sel];
 918                 spill = ++cfg->spill_count;
 919                 rs->vassign [i] = -spill - 1;
 920                 mono_regstate_free_int (rs, sel);
 921         }
 922
 923         /* we need to create a spill var and insert a load to sel after the current instruction */
 924         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 925         load->dreg = sel;
 926         load->inst_basereg = cfg->frame_reg;
 927         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 928         insert_after_ins (bb, ins, last, load);
 929         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 930         if (G_UNLIKELY (bank))
 931                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 932         else
 933                 i = mono_regstate_alloc_int (rs, regmask (sel));
 934         g_assert (i == sel);
 935
 936         return sel;
 937 }
 938
 939 /*
 940  * free_up_hreg:
 941  *
 942  *   Free up the hreg HREG by spilling the vreg allocated to it.
 943  */
 944 static void
 945 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 946 {
 947         if (G_UNLIKELY (bank)) {
 948                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 949                         bank = translate_bank (cfg->rs, bank, hreg);
 950                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 951                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 952                 }
 953         }
 954         else {
 955                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 956                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 957                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 958                 }
 959         }
 960 }
 961
 962 static MonoInst*
 963 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 964 {
 965         MonoInst *copy;
 966
 967         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 968
 969         copy->dreg = dest;
 970         copy->sreg1 = src;
 971         copy->cil_code = ip;
 972         if (ins) {
 973                 mono_bblock_insert_after_ins (bb, ins, copy);
 974                 *last = copy;
 975         }
 976         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 977         return copy;
 978 }
 979
 980 static inline const char*
 981 regbank_to_string (int bank)
 982 {
 983         if (bank == MONO_REG_INT_REF)
 984                 return "REF ";
 985         else if (bank == MONO_REG_INT_MP)
 986                 return "MP ";
 987         else
 988                 return "";
 989 }
 990
 991 static void
 992 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 993 {
 994         MonoInst *store, *def;
 995
 996         bank = get_vreg_bank (cfg, prev_reg, bank);
 997
 998         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 999         store->sreg1 = reg;
1000         store->inst_destbasereg = cfg->frame_reg;
1001         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
1002         if (ins) {
1003                 mono_bblock_insert_after_ins (bb, ins, store);
1004                 *last = store;
1005         } else if (insert_before) {
1006                 insert_before_ins (bb, insert_before, store);
1007         } else {
1008                 g_assert_not_reached ();
1009         }
1010         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
1011
1012         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1013                 g_assert (prev_reg != -1);
1014                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1015                 def->inst_c0 = spill;
1016                 def->inst_c1 = bank;
1017                 mono_bblock_insert_after_ins (bb, store, def);
1018         }
1019 }
1020
1021 /* flags used in reginfo->flags */
1022 enum {
1023         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1024         MONO_FP_NEEDS_SPILL                     = regmask (1),
1025         MONO_FP_NEEDS_LOAD                      = regmask (2)
1026 };
1027
1028 static inline int
1029 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1030 {
1031         int val;
1032
1033         if (info && info->preferred_mask) {
1034                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1035                 if (val >= 0) {
1036                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1037                         return val;
1038                 }
1039         }
1040
1041         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1042         if (val < 0)
1043                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1044
1045         return val;
1046 }
1047
1048 static inline int
1049 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1050 {
1051         int val;
1052
1053         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1054
1055         if (val < 0)
1056                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1057
1058         return val;
1059 }
1060
1061 static inline int
1062 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1063 {
1064         if (G_UNLIKELY (bank))
1065                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1066         else
1067                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1068 }
1069
1070 static inline void
1071 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1072 {
1073         if (G_UNLIKELY (bank)) {
1074                 int mirrored_bank;
1075
1076                 g_assert (reg >= regbank_size [bank]);
1077                 g_assert (hreg < regbank_size [bank]);
1078                 g_assert (! is_global_freg (hreg));
1079
1080                 rs->vassign [reg] = hreg;
1081                 rs->symbolic [bank] [hreg] = reg;
1082                 rs->free_mask [bank] &= ~ (regmask (hreg));
1083
1084                 mirrored_bank = get_mirrored_bank (bank);
1085                 if (mirrored_bank == -1)
1086                         return;
1087
1088                 /* Make sure the other logical reg bank that this bank shares
1089                  * a single hard reg bank knows that this hard reg is not free.
1090                  */
1091                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1092
1093                 /* Mark the other logical bank that the this bank shares
1094                  * a single hard reg bank with as mirrored.
1095                  */
1096                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1097
1098         }
1099         else {
1100                 g_assert (reg >= MONO_MAX_IREGS);
1101                 g_assert (hreg < MONO_MAX_IREGS);
1102 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1103                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1104                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1105                 g_assert (! is_global_ireg (hreg));
1106 #endif
1107
1108                 rs->vassign [reg] = hreg;
1109                 rs->isymbolic [hreg] = reg;
1110                 rs->ifree_mask &= ~ (regmask (hreg));
1111         }
1112 }
1113
1114 static inline regmask_t
1115 get_callee_mask (const char spec)
1116 {
1117         if (G_UNLIKELY (reg_bank (spec)))
1118                 return regbank_callee_regs [reg_bank (spec)];
1119         return MONO_ARCH_CALLEE_REGS;
1120 }
1121
1122 static gint8 desc_to_fixed_reg [256];
1123 static gboolean desc_to_fixed_reg_inited = FALSE;
1124
1125 #ifndef DISABLE_JIT
1126
1127 /*
1128  * Local register allocation.
1129  * We first scan the list of instructions and we save the liveness info of
1130  * each register (when the register is first used, when it's value is set etc.).
1131  * We also reverse the list of instructions because assigning registers backwards allows
1132  * for more tricks to be used.
1133  */
1134 void
1135 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1136 {
1137         MonoInst *ins, *prev, *last;
1138         MonoInst **tmp;
1139         MonoRegState *rs = cfg->rs;
1140         int i, j, val, max;
1141         RegTrack *reginfo;
1142         const char *spec;
1143         unsigned char spec_src1, spec_dest;
1144         int bank = 0;
1145 #if MONO_ARCH_USE_FPSTACK
1146         gboolean has_fp = FALSE;
1147         int fpstack [8];
1148         int sp = 0;
1149 #endif
1150         int num_sregs = 0;
1151         int sregs [MONO_MAX_SRC_REGS];
1152
1153         if (!bb->code)
1154                 return;
1155
1156         if (!desc_to_fixed_reg_inited) {
1157                 for (i = 0; i < 256; ++i)
1158                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1159                 desc_to_fixed_reg_inited = TRUE;
1160
1161                 /* Validate the cpu description against the info in mini-ops.h */
1162 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1163                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1164                         const char *ispec;
1165
1166                         spec = ins_get_spec (i);
1167                         ispec = INS_INFO (i);
1168
1169                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1170                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1171                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1172                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1173                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1174                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1175                 }
1176 #endif
1177         }
1178
1179         rs->next_vreg = bb->max_vreg;
1180         mono_regstate_assign (rs);
1181
1182         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1183         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1184                 rs->free_mask [i] = regbank_callee_regs [i];
1185
1186         max = rs->next_vreg;
1187
1188         if (cfg->reginfo && cfg->reginfo_len < max)
1189                 cfg->reginfo = NULL;
1190
1191         reginfo = (RegTrack *)cfg->reginfo;
1192         if (!reginfo) {
1193                 cfg->reginfo_len = MAX (1024, max * 2);
1194                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1195                 cfg->reginfo = reginfo;
1196         }
1197         else
1198                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1199
1200         if (cfg->verbose_level > 1) {
1201                 /* print_regtrack reads the info of all variables */
1202                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1203         }
1204
1205         /*
1206          * For large methods, next_vreg can be very large, so g_malloc0 time can
1207          * be prohibitive. So we manually init the reginfo entries used by the
1208          * bblock.
1209          */
1210         for (ins = bb->code; ins; ins = ins->next) {
1211                 gboolean modify = FALSE;
1212
1213                 spec = ins_get_spec (ins->opcode);
1214
1215                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1216                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1217 #if SIZEOF_REGISTER == 4
1218                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1219                                 /**
1220                                  * In the new IR, the two vregs of the regpair do not alias the
1221                                  * original long vreg. shift the vreg here so the rest of the
1222                                  * allocator doesn't have to care about it.
1223                                  */
1224                                 ins->dreg ++;
1225                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1226                         }
1227 #endif
1228                 }
1229
1230                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1231                 for (j = 0; j < num_sregs; ++j) {
1232                         g_assert (sregs [j] != -1);
1233                         if (sregs [j] < max) {
1234                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1235 #if SIZEOF_REGISTER == 4
1236                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1237                                         sregs [j]++;
1238                                         modify = TRUE;
1239                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1240                                 }
1241 #endif
1242                         }
1243                 }
1244                 if (modify)
1245                         mono_inst_set_src_registers (ins, sregs);
1246         }
1247
1248         /*if (cfg->opt & MONO_OPT_COPYPROP)
1249                 local_copy_prop (cfg, ins);*/
1250
1251         i = 1;
1252         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1253         /* forward pass on the instructions to collect register liveness info */
1254         MONO_BB_FOR_EACH_INS (bb, ins) {
1255                 spec = ins_get_spec (ins->opcode);
1256                 spec_dest = spec [MONO_INST_DEST];
1257
1258                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1259                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1260                 }
1261
1262                 DEBUG (mono_print_ins_index (i, ins));
1263
1264                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1265
1266 #if MONO_ARCH_USE_FPSTACK
1267                 if (dreg_is_fp (spec)) {
1268                         has_fp = TRUE;
1269                 } else {
1270                         for (j = 0; j < num_sregs; ++j) {
1271                                 if (sreg_is_fp (j, spec))
1272                                         has_fp = TRUE;
1273                         }
1274                 }
1275 #endif
1276
1277                 for (j = 0; j < num_sregs; ++j) {
1278                         int sreg = sregs [j];
1279                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1280                         if (sreg_spec) {
1281                                 bank = sreg_bank (j, spec);
1282                                 g_assert (sreg != -1);
1283                                 if (is_soft_reg (sreg, bank))
1284                                         /* This means the vreg is not local to this bb */
1285                                         g_assert (reginfo [sreg].born_in > 0);
1286                                 rs->vassign [sreg] = -1;
1287                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1288                                 //reginfo [ins->sreg2].last_use = i;
1289                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1290                                         /* The virtual register is allocated sequentially */
1291                                         rs->vassign [sreg + 1] = -1;
1292                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1293                                         //reginfo [ins->sreg2 + 1].last_use = i;
1294                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1295                                                 reginfo [sreg + 1].born_in = i;
1296                                 }
1297                         } else {
1298                                 sregs [j] = -1;
1299                         }
1300                 }
1301                 mono_inst_set_src_registers (ins, sregs);
1302
1303                 if (spec_dest) {
1304                         int dest_dreg;
1305
1306                         bank = dreg_bank (spec);
1307                         if (spec_dest != 'b') /* it's not just a base register */
1308                                 reginfo [ins->dreg].killed_in = i;
1309                         g_assert (ins->dreg != -1);
1310                         rs->vassign [ins->dreg] = -1;
1311                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1312                         //reginfo [ins->dreg].last_use = i;
1313                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1314                                 reginfo [ins->dreg].born_in = i;
1315
1316                         dest_dreg = desc_to_fixed_reg [spec_dest];
1317                         if (dest_dreg != -1)
1318                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1319
1320 #ifdef MONO_ARCH_INST_FIXED_MASK
1321                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1322 #endif
1323
1324                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1325                                 /* The virtual register is allocated sequentially */
1326                                 rs->vassign [ins->dreg + 1] = -1;
1327                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1328                                 //reginfo [ins->dreg + 1].last_use = i;
1329                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1330                                         reginfo [ins->dreg + 1].born_in = i;
1331                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1332                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1333                         }
1334                 } else {
1335                         ins->dreg = -1;
1336                 }
1337
1338                 ++i;
1339         }
1340
1341         tmp = &last;
1342
1343         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1344         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1345                 int prev_dreg;
1346                 int dest_dreg, clob_reg;
1347                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1348                 int dreg_high, sreg1_high;
1349                 regmask_t dreg_mask, mask;
1350                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1351                 regmask_t dreg_fixed_mask;
1352                 const unsigned char *ip;
1353                 --i;
1354                 spec = ins_get_spec (ins->opcode);
1355                 spec_src1 = spec [MONO_INST_SRC1];
1356                 spec_dest = spec [MONO_INST_DEST];
1357                 prev_dreg = -1;
1358                 clob_reg = -1;
1359                 dest_dreg = -1;
1360                 dreg_high = -1;
1361                 sreg1_high = -1;
1362                 dreg_mask = get_callee_mask (spec_dest);
1363                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1364                         prev_sregs [j] = -1;
1365                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1366                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1367 #ifdef MONO_ARCH_INST_FIXED_MASK
1368                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1369 #else
1370                         sreg_fixed_masks [j] = 0;
1371 #endif
1372                 }
1373
1374                 DEBUG (printf ("processing:"));
1375                 DEBUG (mono_print_ins_index (i, ins));
1376
1377                 ip = ins->cil_code;
1378
1379                 last = ins;
1380
1381                 /*
1382                  * FIXED REGS
1383                  */
1384                 dest_dreg = desc_to_fixed_reg [spec_dest];
1385                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1386                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1387
1388 #ifdef MONO_ARCH_INST_FIXED_MASK
1389                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1390 #else
1391                 dreg_fixed_mask = 0;
1392 #endif
1393
1394                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1395
1396                 /*
1397                  * TRACK FIXED SREG2, 3, ...
1398                  */
1399                 for (j = 1; j < num_sregs; ++j) {
1400                         int sreg = sregs [j];
1401                         int dest_sreg = dest_sregs [j];
1402
1403                         if (dest_sreg == -1)
1404                                 continue;
1405
1406                         if (j == 2) {
1407                                 int k;
1408
1409                                 /*
1410                                  * CAS.
1411                                  * We need to special case this, since on x86, there are only 3
1412                                  * free registers, and the code below assigns one of them to
1413                                  * sreg, so we can run out of registers when trying to assign
1414                                  * dreg. Instead, we just set up the register masks, and let the
1415                                  * normal sreg2 assignment code handle this. It would be nice to
1416                                  * do this for all the fixed reg cases too, but there is too much
1417                                  * risk of breakage.
1418                                  */
1419
1420                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1421                                 sreg_masks [j] = regmask (dest_sreg);
1422                                 for (k = 0; k < num_sregs; ++k) {
1423                                         if (k != j)
1424                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1425                                 }
1426
1427                                 /*
1428                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1429                                  */
1430                                 for (k = 0; k < num_sregs; ++k) {
1431                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1432                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1433                                 }
1434
1435                                 /*
1436                                  * We can also run out of registers while processing sreg2 if sreg3 is
1437                                  * assigned to another hreg, so spill sreg3 now.
1438                                  */
1439                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1440                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1441                                 }
1442                                 continue;
1443                         }
1444
1445                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1446                                 if (is_global_ireg (sreg)) {
1447                                         int k;
1448                                         /* Argument already in hard reg, need to copy */
1449                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1450                                         insert_before_ins (bb, ins, copy);
1451                                         for (k = 0; k < num_sregs; ++k) {
1452                                                 if (k != j)
1453                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1454                                         }
1455                                         /* See below */
1456                                         dreg_mask &= ~ (regmask (dest_sreg));
1457                                 } else {
1458                                         val = rs->vassign [sreg];
1459                                         if (val == -1) {
1460                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1461                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1462                                         } else if (val < -1) {
1463                                                 /* FIXME: */
1464                                                 g_assert_not_reached ();
1465                                         } else {
1466                                                 /* Argument already in hard reg, need to copy */
1467                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1468                                                 int k;
1469
1470                                                 insert_before_ins (bb, ins, copy);
1471                                                 for (k = 0; k < num_sregs; ++k) {
1472                                                         if (k != j)
1473                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1474                                                 }
1475                                                 /*
1476                                                  * Prevent the dreg from being allocated to dest_sreg
1477                                                  * too, since it could force sreg1 to be allocated to
1478                                                  * the same reg on x86.
1479                                                  */
1480                                                 dreg_mask &= ~ (regmask (dest_sreg));
1481                                         }
1482                                 }
1483                         } else {
1484                                 gboolean need_spill = TRUE;
1485                                 gboolean need_assign = TRUE;
1486                                 int k;
1487
1488                                 dreg_mask &= ~ (regmask (dest_sreg));
1489                                 for (k = 0; k < num_sregs; ++k) {
1490                                         if (k != j)
1491                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1492                                 }
1493
1494                                 /*
1495                                  * First check if dreg is assigned to dest_sreg2, since we
1496                                  * can't spill a dreg.
1497                                  */
1498                                 if (spec [MONO_INST_DEST])
1499                                         val = rs->vassign [ins->dreg];
1500                                 else
1501                                         val = -1;
1502                                 if (val == dest_sreg && ins->dreg != sreg) {
1503                                         /*
1504                                          * the destination register is already assigned to
1505                                          * dest_sreg2: we need to allocate another register for it
1506                                          * and then copy from this to dest_sreg2.
1507                                          */
1508                                         int new_dest;
1509                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1510                                         g_assert (new_dest >= 0);
1511                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1512
1513                                         prev_dreg = ins->dreg;
1514                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1515                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1516                                         mono_regstate_free_int (rs, dest_sreg);
1517                                         need_spill = FALSE;
1518                                 }
1519
1520                                 if (is_global_ireg (sreg)) {
1521                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1522                                         insert_before_ins (bb, ins, copy);
1523                                         need_assign = FALSE;
1524                                 }
1525                                 else {
1526                                         val = rs->vassign [sreg];
1527                                         if (val == dest_sreg) {
1528                                                 /* sreg2 is already assigned to the correct register */
1529                                                 need_spill = FALSE;
1530                                         } else if (val < -1) {
1531                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1532                                         } else if (val >= 0) {
1533                                                 /* sreg2 already assigned to another register */
1534                                                 /*
1535                                                  * We couldn't emit a copy from val to dest_sreg2, because
1536                                                  * val might be spilled later while processing this
1537                                                  * instruction. So we spill sreg2 so it can be allocated to
1538                                                  * dest_sreg2.
1539                                                  */
1540                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1541                                         }
1542                                 }
1543
1544                                 if (need_spill) {
1545                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1546                                 }
1547
1548                                 if (need_assign) {
1549                                         if (rs->vassign [sreg] < -1) {
1550                                                 int spill;
1551
1552                                                 /* Need to emit a spill store */
1553                                                 spill = - rs->vassign [sreg] - 1;
1554                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1555                                         }
1556                                         /* force-set sreg2 */
1557                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1558                                 }
1559                         }
1560                         sregs [j] = dest_sreg;
1561                 }
1562                 mono_inst_set_src_registers (ins, sregs);
1563
1564                 /*
1565                  * TRACK DREG
1566                  */
1567                 bank = dreg_bank (spec);
1568                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1569                         prev_dreg = ins->dreg;
1570                 }
1571
1572                 if (spec_dest == 'b') {
1573                         /*
1574                          * The dest reg is read by the instruction, not written, so
1575                          * avoid allocating sreg1/sreg2 to the same reg.
1576                          */
1577                         if (dest_sregs [0] != -1)
1578                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1579                         for (j = 1; j < num_sregs; ++j) {
1580                                 if (dest_sregs [j] != -1)
1581                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1582                         }
1583
1584                         val = rs->vassign [ins->dreg];
1585                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1586                                 /* DREG is already allocated to a register needed for sreg1 */
1587                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1588                         }
1589                 }
1590
1591                 /*
1592                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1593                  * various complex situations.
1594                  */
1595                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1596                         guint32 dreg2, dest_dreg2;
1597
1598                         g_assert (is_soft_reg (ins->dreg, bank));
1599
1600                         if (dest_dreg != -1) {
1601                                 if (rs->vassign [ins->dreg] != dest_dreg)
1602                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1603
1604                                 dreg2 = ins->dreg + 1;
1605                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1606                                 if (dest_dreg2 != -1) {
1607                                         if (rs->vassign [dreg2] != dest_dreg2)
1608                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1609                                 }
1610                         }
1611                 }
1612
1613                 if (dreg_fixed_mask) {
1614                         g_assert (!bank);
1615                         if (is_global_ireg (ins->dreg)) {
1616                                 /*
1617                                  * The argument is already in a hard reg, but that reg is
1618                                  * not usable by this instruction, so allocate a new one.
1619                                  */
1620                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1621                                 if (val < 0)
1622                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1623                                 mono_regstate_free_int (rs, val);
1624                                 dest_dreg = val;
1625
1626                                 /* Fall through */
1627                         }
1628                         else
1629                                 dreg_mask &= dreg_fixed_mask;
1630                 }
1631
1632                 if (is_soft_reg (ins->dreg, bank)) {
1633                         val = rs->vassign [ins->dreg];
1634
1635                         if (val < 0) {
1636                                 int spill = 0;
1637                                 if (val < -1) {
1638                                         /* the register gets spilled after this inst */
1639                                         spill = -val -1;
1640                                 }
1641                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1642                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1643                                 if (spill)
1644                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1645                         }
1646
1647                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1648                         ins->dreg = val;
1649                 }
1650
1651                 /* Handle regpairs */
1652                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1653                         int reg2 = prev_dreg + 1;
1654
1655                         g_assert (!bank);
1656                         g_assert (prev_dreg > -1);
1657                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1658                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1659 #ifdef TARGET_X86
1660                         /* bug #80489 */
1661                         mask &= ~regmask (X86_ECX);
1662 #endif
1663                         val = rs->vassign [reg2];
1664                         if (val < 0) {
1665                                 int spill = 0;
1666                                 if (val < -1) {
1667                                         /* the register gets spilled after this inst */
1668                                         spill = -val -1;
1669                                 }
1670                                 val = mono_regstate_alloc_int (rs, mask);
1671                                 if (val < 0)
1672                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1673                                 if (spill)
1674                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1675                         }
1676                         else {
1677                                 if (! (mask & (regmask (val)))) {
1678                                         val = mono_regstate_alloc_int (rs, mask);
1679                                         if (val < 0)
1680                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1681
1682                                         /* Reallocate hreg to the correct register */
1683                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1684
1685                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1686                                 }
1687                         }
1688
1689                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1690                         assign_reg (cfg, rs, reg2, val, bank);
1691
1692                         dreg_high = val;
1693                         ins->backend.reg3 = val;
1694
1695                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1696                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1697                                 mono_regstate_free_int (rs, val);
1698                         }
1699                 }
1700
1701                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1702                         /*
1703                          * In theory, we could free up the hreg even if the vreg is alive,
1704                          * but branches inside bblocks force us to assign the same hreg
1705                          * to a vreg every time it is encountered.
1706                          */
1707                         int dreg = rs->vassign [prev_dreg];
1708                         g_assert (dreg >= 0);
1709                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1710                         if (G_UNLIKELY (bank))
1711                                 mono_regstate_free_general (rs, dreg, bank);
1712                         else
1713                                 mono_regstate_free_int (rs, dreg);
1714                         rs->vassign [prev_dreg] = -1;
1715                 }
1716
1717                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1718                         /* this instruction only outputs to dest_dreg, need to copy */
1719                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1720                         ins->dreg = dest_dreg;
1721
1722                         if (G_UNLIKELY (bank)) {
1723                                 /* the register we need to free up may be used in another logical regbank
1724                                  * so do a translate just in case.
1725                                  */
1726                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1727                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1728                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1729                         }
1730                         else {
1731                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1732                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1733                         }
1734                 }
1735
1736                 if (spec_dest == 'b') {
1737                         /*
1738                          * The dest reg is read by the instruction, not written, so
1739                          * avoid allocating sreg1/sreg2 to the same reg.
1740                          */
1741                         for (j = 0; j < num_sregs; ++j)
1742                                 if (!sreg_bank (j, spec))
1743                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1744                 }
1745
1746                 /*
1747                  * TRACK CLOBBERING
1748                  */
1749                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1750                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1751                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1752                 }
1753
1754                 if (spec [MONO_INST_CLOB] == 'c') {
1755                         int j, s, dreg, dreg2, cur_bank;
1756                         guint64 clob_mask;
1757
1758                         clob_mask = MONO_ARCH_CALLEE_REGS;
1759
1760                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1761                                 /*
1762                                  * Need to avoid spilling the dreg since the dreg is not really
1763                                  * clobbered by the call.
1764                                  */
1765                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1766                                         dreg = rs->vassign [prev_dreg];
1767                                 else
1768                                         dreg = -1;
1769
1770                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1771                                         dreg2 = rs->vassign [prev_dreg + 1];
1772                                 else
1773                                         dreg2 = -1;
1774
1775                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1776                                         s = regmask (j);
1777                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1778                                                 if ((j != dreg) && (j != dreg2))
1779                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1780                                                 else if (rs->isymbolic [j])
1781                                                         /* The hreg is assigned to the dreg of this instruction */
1782                                                         rs->vassign [rs->isymbolic [j]] = -1;
1783                                                 mono_regstate_free_int (rs, j);
1784                                         }
1785                                 }
1786                         }
1787
1788                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1789                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1790                                         clob_mask = regbank_callee_regs [cur_bank];
1791                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1792                                                 dreg = rs->vassign [prev_dreg];
1793                                         else
1794                                                 dreg = -1;
1795
1796                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1797
1798                                                 /* we are looping though the banks in the outer loop
1799                                                  * so, we don't need to deal with mirrored hregs
1800                                                  * because we will get them in one of the other bank passes.
1801                                                  */
1802                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1803                                                         continue;
1804
1805                                                 s = regmask (j);
1806                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1807                                                         if (j != dreg)
1808                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1809                                                         else if (rs->symbolic [cur_bank] [j])
1810                                                                 /* The hreg is assigned to the dreg of this instruction */
1811                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1812                                                         mono_regstate_free_general (rs, j, cur_bank);
1813                                                 }
1814                                         }
1815                                 }
1816                         }
1817                 }
1818
1819                 /*
1820                  * TRACK ARGUMENT REGS
1821                  */
1822                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1823                         MonoCallInst *call = (MonoCallInst*)ins;
1824                         GSList *list;
1825
1826                         /*
1827                          * This needs to be done before assigning sreg1, so sreg1 will
1828                          * not be assigned one of the argument regs.
1829                          */
1830
1831                         /*
1832                          * Assign all registers in call->out_reg_args to the proper
1833                          * argument registers.
1834                          */
1835
1836                         list = call->out_ireg_args;
1837                         if (list) {
1838                                 while (list) {
1839                                         guint32 regpair;
1840                                         int reg, hreg;
1841
1842                                         regpair = (guint32)(gssize)(list->data);
1843                                         hreg = regpair >> 24;
1844                                         reg = regpair & 0xffffff;
1845
1846                                         assign_reg (cfg, rs, reg, hreg, 0);
1847
1848                                         sreg_masks [0] &= ~(regmask (hreg));
1849
1850                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1851
1852                                         list = g_slist_next (list);
1853                                 }
1854                         }
1855
1856                         list = call->out_freg_args;
1857                         if (list) {
1858                                 while (list) {
1859                                         guint32 regpair;
1860                                         int reg, hreg;
1861
1862                                         regpair = (guint32)(gssize)(list->data);
1863                                         hreg = regpair >> 24;
1864                                         reg = regpair & 0xffffff;
1865
1866                                         assign_reg (cfg, rs, reg, hreg, 1);
1867
1868                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1869
1870                                         list = g_slist_next (list);
1871                                 }
1872                         }
1873                 }
1874
1875                 /*
1876                  * TRACK SREG1
1877                  */
1878                 bank = sreg1_bank (spec);
1879                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1880                         int sreg1 = sregs [0];
1881                         int dest_sreg1 = dest_sregs [0];
1882
1883                         g_assert (is_soft_reg (sreg1, bank));
1884
1885                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1886                         if (dest_sreg1 != -1)
1887                                 g_assert (dest_sreg1 == ins->dreg);
1888                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1889                         g_assert (val >= 0);
1890
1891                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1892                                 // FIXME:
1893                                 g_assert_not_reached ();
1894
1895                         assign_reg (cfg, rs, sreg1, val, bank);
1896
1897                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1898
1899                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1900                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1901                         g_assert (val >= 0);
1902
1903                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1904                                 // FIXME:
1905                                 g_assert_not_reached ();
1906
1907                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1908
1909                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1910
1911                         /* Skip rest of this section */
1912                         dest_sregs [0] = -1;
1913                 }
1914
1915                 if (sreg_fixed_masks [0]) {
1916                         g_assert (!bank);
1917                         if (is_global_ireg (sregs [0])) {
1918                                 /*
1919                                  * The argument is already in a hard reg, but that reg is
1920                                  * not usable by this instruction, so allocate a new one.
1921                                  */
1922                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1923                                 if (val < 0)
1924                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1925                                 mono_regstate_free_int (rs, val);
1926                                 dest_sregs [0] = val;
1927
1928                                 /* Fall through to the dest_sreg1 != -1 case */
1929                         }
1930                         else
1931                                 sreg_masks [0] &= sreg_fixed_masks [0];
1932                 }
1933
1934                 if (dest_sregs [0] != -1) {
1935                         sreg_masks [0] = regmask (dest_sregs [0]);
1936
1937                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1938                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1939                         }
1940                         if (is_global_ireg (sregs [0])) {
1941                                 /* The argument is already in a hard reg, need to copy */
1942                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1943                                 insert_before_ins (bb, ins, copy);
1944                                 sregs [0] = dest_sregs [0];
1945                         }
1946                 }
1947
1948                 if (is_soft_reg (sregs [0], bank)) {
1949                         val = rs->vassign [sregs [0]];
1950                         prev_sregs [0] = sregs [0];
1951                         if (val < 0) {
1952                                 int spill = 0;
1953                                 if (val < -1) {
1954                                         /* the register gets spilled after this inst */
1955                                         spill = -val -1;
1956                                 }
1957
1958                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1959                                         /*
1960                                          * Allocate the same hreg to sreg1 as well so the
1961                                          * peephole can get rid of the move.
1962                                          */
1963                                         sreg_masks [0] = regmask (ins->dreg);
1964                                 }
1965
1966                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1967                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1968                                         sreg_masks [0] = regmask (ins->dreg);
1969
1970                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1971                                 assign_reg (cfg, rs, sregs [0], val, bank);
1972                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1973
1974                                 if (spill) {
1975                                         /*
1976                                          * Need to insert before the instruction since it can
1977                                          * overwrite sreg1.
1978                                          */
1979                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1980                                 }
1981                         }
1982                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1983                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1984                                 insert_before_ins (bb, ins, copy);
1985                                 for (j = 1; j < num_sregs; ++j)
1986                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1987                                 val = dest_sregs [0];
1988                         }
1989
1990                         sregs [0] = val;
1991                 }
1992                 else {
1993                         prev_sregs [0] = -1;
1994                 }
1995                 mono_inst_set_src_registers (ins, sregs);
1996
1997                 for (j = 1; j < num_sregs; ++j)
1998                         sreg_masks [j] &= ~(regmask (sregs [0]));
1999
2000                 /* Handle the case when sreg1 is a regpair but dreg is not */
2001                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2002                         int reg2 = prev_sregs [0] + 1;
2003
2004                         g_assert (!bank);
2005                         g_assert (prev_sregs [0] > -1);
2006                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2007                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2008                         val = rs->vassign [reg2];
2009                         if (val < 0) {
2010                                 int spill = 0;
2011                                 if (val < -1) {
2012                                         /* the register gets spilled after this inst */
2013                                         spill = -val -1;
2014                                 }
2015                                 val = mono_regstate_alloc_int (rs, mask);
2016                                 if (val < 0)
2017                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2018                                 if (spill)
2019                                         g_assert_not_reached ();
2020                         }
2021                         else {
2022                                 if (! (mask & (regmask (val)))) {
2023                                         /* The vreg is already allocated to a wrong hreg */
2024                                         /* FIXME: */
2025                                         g_assert_not_reached ();
2026 #if 0
2027                                         val = mono_regstate_alloc_int (rs, mask);
2028                                         if (val < 0)
2029                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2030
2031                                         /* Reallocate hreg to the correct register */
2032                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2033
2034                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2035 #endif
2036                                 }
2037                         }
2038
2039                         sreg1_high = val;
2040                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2041                         assign_reg (cfg, rs, reg2, val, bank);
2042                 }
2043
2044                 /* Handle dreg==sreg1 */
2045                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2046                         MonoInst *sreg2_copy = NULL;
2047                         MonoInst *copy;
2048                         int bank = reg_bank (spec_src1);
2049
2050                         if (ins->dreg == sregs [1]) {
2051                                 /*
2052                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2053                                  * register for it.
2054                                  */
2055                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2056
2057                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2058                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2059                                 prev_sregs [1] = sregs [1] = reg2;
2060
2061                                 if (G_UNLIKELY (bank))
2062                                         mono_regstate_free_general (rs, reg2, bank);
2063                                 else
2064                                         mono_regstate_free_int (rs, reg2);
2065                         }
2066
2067                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2068                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2069                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2070                                         /* FIXME: */
2071                                         g_assert_not_reached ();
2072
2073                                 /*
2074                                  * sreg1 and dest are already allocated to the same regpair by the
2075                                  * SREG1 allocation code.
2076                                  */
2077                                 g_assert (sregs [0] == ins->dreg);
2078                                 g_assert (dreg_high == sreg1_high);
2079                         }
2080
2081                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2082                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2083                         insert_before_ins (bb, ins, copy);
2084
2085                         if (sreg2_copy)
2086                                 insert_before_ins (bb, copy, sreg2_copy);
2087
2088                         /*
2089                          * Need to prevent sreg2 to be allocated to sreg1, since that
2090                          * would screw up the previous copy.
2091                          */
2092                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2093                         /* we set sreg1 to dest as well */
2094                         prev_sregs [0] = sregs [0] = ins->dreg;
2095                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2096                 }
2097                 mono_inst_set_src_registers (ins, sregs);
2098
2099                 /*
2100                  * TRACK SREG2, 3, ...
2101                  */
2102                 for (j = 1; j < num_sregs; ++j) {
2103                         int k;
2104
2105                         bank = sreg_bank (j, spec);
2106                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2107                                 g_assert_not_reached ();
2108
2109                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2110                                 /*
2111                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2112                                  * allocating it to the fixed reg.
2113                                  */
2114                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2115                                 insert_before_ins (bb, ins, copy);
2116                                 sregs [j] = dest_sregs [j];
2117                         } else if (is_soft_reg (sregs [j], bank)) {
2118                                 val = rs->vassign [sregs [j]];
2119
2120                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2121                                         /*
2122                                          * The sreg is already allocated to a hreg, but not to the fixed
2123                                          * reg required by the instruction. Spill the sreg, so it can be
2124                                          * allocated to the fixed reg by the code below.
2125                                          */
2126                                         /* Currently, this code should only be hit for CAS */
2127                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2128                                         val = rs->vassign [sregs [j]];
2129                                 }
2130
2131                                 if (val < 0) {
2132                                         int spill = 0;
2133                                         if (val < -1) {
2134                                                 /* the register gets spilled after this inst */
2135                                                 spill = -val -1;
2136                                         }
2137                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2138                                         assign_reg (cfg, rs, sregs [j], val, bank);
2139                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2140                                         if (spill) {
2141                                                 /*
2142                                                  * Need to insert before the instruction since it can
2143                                                  * overwrite sreg2.
2144                                                  */
2145                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2146                                         }
2147                                 }
2148                                 sregs [j] = val;
2149                                 for (k = j + 1; k < num_sregs; ++k)
2150                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2151                         }
2152                         else {
2153                                 prev_sregs [j] = -1;
2154                         }
2155                 }
2156                 mono_inst_set_src_registers (ins, sregs);
2157
2158                 /* Sanity check */
2159                 /* Do this only for CAS for now */
2160                 for (j = 1; j < num_sregs; ++j) {
2161                         int sreg = sregs [j];
2162                         int dest_sreg = dest_sregs [j];
2163
2164                         if (j == 2 && dest_sreg != -1) {
2165                                 int k;
2166
2167                                 g_assert (sreg == dest_sreg);
2168
2169                                 for (k = 0; k < num_sregs; ++k) {
2170                                         if (k != j)
2171                                                 g_assert (sregs [k] != dest_sreg);
2172                                 }
2173                         }
2174                 }
2175
2176                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2177                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2178                         mono_regstate_free_int (rs, ins->sreg1);
2179                 }
2180                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2181                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2182                         mono_regstate_free_int (rs, ins->sreg2);
2183                 }*/
2184
2185                 DEBUG (mono_print_ins_index (i, ins));
2186         }
2187
2188         // FIXME: Set MAX_FREGS to 8
2189         // FIXME: Optimize generated code
2190 #if MONO_ARCH_USE_FPSTACK
2191         /*
2192          * Make a forward pass over the code, simulating the fp stack, making sure the
2193          * arguments required by the fp opcodes are at the top of the stack.
2194          */
2195         if (has_fp) {
2196                 MonoInst *prev = NULL;
2197                 MonoInst *fxch;
2198                 int tmp;
2199
2200                 g_assert (num_sregs <= 2);
2201
2202                 for (ins = bb->code; ins; ins = ins->next) {
2203                         spec = ins_get_spec (ins->opcode);
2204
2205                         DEBUG (printf ("processing:"));
2206                         DEBUG (mono_print_ins_index (0, ins));
2207
2208                         if (ins->opcode == OP_FMOVE) {
2209                                 /* Do it by renaming the source to the destination on the stack */
2210                                 // FIXME: Is this correct ?
2211                                 for (i = 0; i < sp; ++i)
2212                                         if (fpstack [i] == ins->sreg1)
2213                                                 fpstack [i] = ins->dreg;
2214                                 prev = ins;
2215                                 continue;
2216                         }
2217
2218                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2219                                 /* Arg1 must be in %st(1) */
2220                                 g_assert (prev);
2221
2222                                 i = 0;
2223                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2224                                         i ++;
2225                                 g_assert (i < sp);
2226
2227                                 if (sp - 1 - i > 0) {
2228                                         /* First move it to %st(0) */
2229                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2230
2231                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2232                                         fxch->inst_imm = sp - 1 - i;
2233
2234                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2235                                         prev = fxch;
2236
2237                                         tmp = fpstack [sp - 1];
2238                                         fpstack [sp - 1] = fpstack [i];
2239                                         fpstack [i] = tmp;
2240                                 }
2241
2242                                 /* Then move it to %st(1) */
2243                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2244
2245                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2246                                 fxch->inst_imm = 1;
2247
2248                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2249                                 prev = fxch;
2250
2251                                 tmp = fpstack [sp - 1];
2252                                 fpstack [sp - 1] = fpstack [sp - 2];
2253                                 fpstack [sp - 2] = tmp;
2254                         }
2255
2256                         if (sreg2_is_fp (spec)) {
2257                                 g_assert (sp > 0);
2258
2259                                 if (fpstack [sp - 1] != ins->sreg2) {
2260                                         g_assert (prev);
2261
2262                                         i = 0;
2263                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2264                                                 i ++;
2265                                         g_assert (i < sp);
2266
2267                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2268
2269                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2270                                         fxch->inst_imm = sp - 1 - i;
2271
2272                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2273                                         prev = fxch;
2274
2275                                         tmp = fpstack [sp - 1];
2276                                         fpstack [sp - 1] = fpstack [i];
2277                                         fpstack [i] = tmp;
2278                                 }
2279
2280                                 sp --;
2281                         }
2282
2283                         if (sreg1_is_fp (spec)) {
2284                                 g_assert (sp > 0);
2285
2286                                 if (fpstack [sp - 1] != ins->sreg1) {
2287                                         g_assert (prev);
2288
2289                                         i = 0;
2290                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2291                                                 i ++;
2292                                         g_assert (i < sp);
2293
2294                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2295
2296                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2297                                         fxch->inst_imm = sp - 1 - i;
2298
2299                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2300                                         prev = fxch;
2301
2302                                         tmp = fpstack [sp - 1];
2303                                         fpstack [sp - 1] = fpstack [i];
2304                                         fpstack [i] = tmp;
2305                                 }
2306
2307                                 sp --;
2308                         }
2309
2310                         if (dreg_is_fp (spec)) {
2311                                 g_assert (sp < 8);
2312                                 fpstack [sp ++] = ins->dreg;
2313                         }
2314
2315                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2316                                 printf ("\t[");
2317                                 for (i = 0; i < sp; ++i)
2318                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2319                                 printf ("]\n");
2320                         }
2321
2322                         prev = ins;
2323                 }
2324
2325                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2326                         /* Remove remaining items from the fp stack */
2327                         /*
2328                          * These can remain for example as a result of a dead fmove like in
2329                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2330                          */
2331                         while (sp) {
2332                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2333                                 mono_add_ins_to_end (bb, ins);
2334                                 sp --;
2335                         }
2336                 }
2337         }
2338 #endif
2339 }
2340
2341 CompRelation
2342 mono_opcode_to_cond (int opcode)
2343 {
2344         switch (opcode) {
2345         case OP_CEQ:
2346         case OP_IBEQ:
2347         case OP_ICEQ:
2348         case OP_LBEQ:
2349         case OP_LCEQ:
2350         case OP_FBEQ:
2351         case OP_FCEQ:
2352         case OP_RBEQ:
2353         case OP_RCEQ:
2354         case OP_COND_EXC_EQ:
2355         case OP_COND_EXC_IEQ:
2356         case OP_CMOV_IEQ:
2357         case OP_CMOV_LEQ:
2358                 return CMP_EQ;
2359         case OP_FCNEQ:
2360         case OP_ICNEQ:
2361         case OP_IBNE_UN:
2362         case OP_LBNE_UN:
2363         case OP_FBNE_UN:
2364         case OP_COND_EXC_NE_UN:
2365         case OP_COND_EXC_INE_UN:
2366         case OP_CMOV_INE_UN:
2367         case OP_CMOV_LNE_UN:
2368                 return CMP_NE;
2369         case OP_FCLE:
2370         case OP_ICLE:
2371         case OP_IBLE:
2372         case OP_LBLE:
2373         case OP_FBLE:
2374         case OP_CMOV_ILE:
2375         case OP_CMOV_LLE:
2376                 return CMP_LE;
2377         case OP_FCGE:
2378         case OP_ICGE:
2379         case OP_IBGE:
2380         case OP_LBGE:
2381         case OP_FBGE:
2382         case OP_CMOV_IGE:
2383         case OP_CMOV_LGE:
2384                 return CMP_GE;
2385         case OP_CLT:
2386         case OP_IBLT:
2387         case OP_ICLT:
2388         case OP_LBLT:
2389         case OP_LCLT:
2390         case OP_FBLT:
2391         case OP_FCLT:
2392         case OP_RBLT:
2393         case OP_RCLT:
2394         case OP_COND_EXC_LT:
2395         case OP_COND_EXC_ILT:
2396         case OP_CMOV_ILT:
2397         case OP_CMOV_LLT:
2398                 return CMP_LT;
2399         case OP_CGT:
2400         case OP_IBGT:
2401         case OP_ICGT:
2402         case OP_LBGT:
2403         case OP_LCGT:
2404         case OP_FBGT:
2405         case OP_FCGT:
2406         case OP_RBGT:
2407         case OP_RCGT:
2408         case OP_COND_EXC_GT:
2409         case OP_COND_EXC_IGT:
2410         case OP_CMOV_IGT:
2411         case OP_CMOV_LGT:
2412                 return CMP_GT;
2413
2414         case OP_ICLE_UN:
2415         case OP_IBLE_UN:
2416         case OP_LBLE_UN:
2417         case OP_FBLE_UN:
2418         case OP_COND_EXC_LE_UN:
2419         case OP_COND_EXC_ILE_UN:
2420         case OP_CMOV_ILE_UN:
2421         case OP_CMOV_LLE_UN:
2422                 return CMP_LE_UN;
2423
2424         case OP_ICGE_UN:
2425         case OP_IBGE_UN:
2426         case OP_LBGE_UN:
2427         case OP_FBGE_UN:
2428         case OP_CMOV_IGE_UN:
2429         case OP_CMOV_LGE_UN:
2430                 return CMP_GE_UN;
2431         case OP_CLT_UN:
2432         case OP_IBLT_UN:
2433         case OP_ICLT_UN:
2434         case OP_LBLT_UN:
2435         case OP_LCLT_UN:
2436         case OP_FBLT_UN:
2437         case OP_FCLT_UN:
2438         case OP_RBLT_UN:
2439         case OP_RCLT_UN:
2440         case OP_COND_EXC_LT_UN:
2441         case OP_COND_EXC_ILT_UN:
2442         case OP_CMOV_ILT_UN:
2443         case OP_CMOV_LLT_UN:
2444                 return CMP_LT_UN;
2445         case OP_CGT_UN:
2446         case OP_IBGT_UN:
2447         case OP_ICGT_UN:
2448         case OP_LBGT_UN:
2449         case OP_LCGT_UN:
2450         case OP_FCGT_UN:
2451         case OP_FBGT_UN:
2452         case OP_RCGT_UN:
2453         case OP_RBGT_UN:
2454         case OP_COND_EXC_GT_UN:
2455         case OP_COND_EXC_IGT_UN:
2456         case OP_CMOV_IGT_UN:
2457         case OP_CMOV_LGT_UN:
2458                 return CMP_GT_UN;
2459         default:
2460                 printf ("%s\n", mono_inst_name (opcode));
2461                 g_assert_not_reached ();
2462                 return (CompRelation)0;
2463         }
2464 }
2465
2466 CompRelation
2467 mono_negate_cond (CompRelation cond)
2468 {
2469         switch (cond) {
2470         case CMP_EQ:
2471                 return CMP_NE;
2472         case CMP_NE:
2473                 return CMP_EQ;
2474         case CMP_LE:
2475                 return CMP_GT;
2476         case CMP_GE:
2477                 return CMP_LT;
2478         case CMP_LT:
2479                 return CMP_GE;
2480         case CMP_GT:
2481                 return CMP_LE;
2482         case CMP_LE_UN:
2483                 return CMP_GT_UN;
2484         case CMP_GE_UN:
2485                 return CMP_LT_UN;
2486         case CMP_LT_UN:
2487                 return CMP_GE_UN;
2488         case CMP_GT_UN:
2489                 return CMP_LE_UN;
2490         default:
2491                 g_assert_not_reached ();
2492         }
2493 }
2494
2495 CompType
2496 mono_opcode_to_type (int opcode, int cmp_opcode)
2497 {
2498         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2499                 return CMP_TYPE_L;
2500         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2501                 return CMP_TYPE_I;
2502         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2503                 return CMP_TYPE_I;
2504         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2505                 return CMP_TYPE_L;
2506         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2507                 return CMP_TYPE_L;
2508         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2509                 return CMP_TYPE_F;
2510         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2511                 return CMP_TYPE_F;
2512         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2513                 return CMP_TYPE_I;
2514         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2515                 switch (cmp_opcode) {
2516                 case OP_ICOMPARE:
2517                 case OP_ICOMPARE_IMM:
2518                         return CMP_TYPE_I;
2519                 default:
2520                         return CMP_TYPE_L;
2521                 }
2522         } else {
2523                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2524                 return (CompType)0;
2525         }
2526 }
2527
2528 #endif /* DISABLE_JIT */
2529
2530 gboolean
2531 mono_is_regsize_var (MonoType *t)
2532 {
2533         t = mini_get_underlying_type (t);
2534         switch (t->type) {
2535         case MONO_TYPE_I1:
2536         case MONO_TYPE_U1:
2537         case MONO_TYPE_I2:
2538         case MONO_TYPE_U2:
2539         case MONO_TYPE_I4:
2540         case MONO_TYPE_U4:
2541         case MONO_TYPE_I:
2542         case MONO_TYPE_U:
2543         case MONO_TYPE_PTR:
2544         case MONO_TYPE_FNPTR:
2545 #if SIZEOF_REGISTER == 8
2546         case MONO_TYPE_I8:
2547         case MONO_TYPE_U8:
2548 #endif
2549                 return TRUE;
2550         case MONO_TYPE_OBJECT:
2551         case MONO_TYPE_STRING:
2552         case MONO_TYPE_CLASS:
2553         case MONO_TYPE_SZARRAY:
2554         case MONO_TYPE_ARRAY:
2555                 return TRUE;
2556         case MONO_TYPE_GENERICINST:
2557                 if (!mono_type_generic_inst_is_valuetype (t))
2558                         return TRUE;
2559                 return FALSE;
2560         case MONO_TYPE_VALUETYPE:
2561                 return FALSE;
2562         default:
2563                 return FALSE;
2564         }
2565 }
2566
2567 #ifndef DISABLE_JIT
2568
2569 /*
2570  * mono_peephole_ins:
2571  *
2572  *   Perform some architecture independent peephole optimizations.
2573  */
2574 void
2575 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2576 {
2577         int filter = FILTER_IL_SEQ_POINT;
2578         MonoInst *last_ins = mono_inst_prev (ins, filter);
2579
2580         switch (ins->opcode) {
2581         case OP_MUL_IMM:
2582                 /* remove unnecessary multiplication with 1 */
2583                 if (ins->inst_imm == 1) {
2584                         if (ins->dreg != ins->sreg1)
2585                                 ins->opcode = OP_MOVE;
2586                         else
2587                                 MONO_DELETE_INS (bb, ins);
2588                 }
2589                 break;
2590         case OP_LOAD_MEMBASE:
2591         case OP_LOADI4_MEMBASE:
2592                 /*
2593                  * Note: if reg1 = reg2 the load op is removed
2594                  *
2595                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2596                  * OP_LOAD_MEMBASE offset(basereg), reg2
2597                  * -->
2598                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2599                  * OP_MOVE reg1, reg2
2600                  */
2601                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2602                         last_ins = mono_inst_prev (ins, filter);
2603                 if (last_ins &&
2604                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2605                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2606                         ins->inst_basereg == last_ins->inst_destbasereg &&
2607                         ins->inst_offset == last_ins->inst_offset) {
2608                         if (ins->dreg == last_ins->sreg1) {
2609                                 MONO_DELETE_INS (bb, ins);
2610                                 break;
2611                         } else {
2612                                 ins->opcode = OP_MOVE;
2613                                 ins->sreg1 = last_ins->sreg1;
2614                         }
2615
2616                         /*
2617                          * Note: reg1 must be different from the basereg in the second load
2618                          * Note: if reg1 = reg2 is equal then second load is removed
2619                          *
2620                          * OP_LOAD_MEMBASE offset(basereg), reg1
2621                          * OP_LOAD_MEMBASE offset(basereg), reg2
2622                          * -->
2623                          * OP_LOAD_MEMBASE offset(basereg), reg1
2624                          * OP_MOVE reg1, reg2
2625                          */
2626                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2627                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2628                           ins->inst_basereg != last_ins->dreg &&
2629                           ins->inst_basereg == last_ins->inst_basereg &&
2630                           ins->inst_offset == last_ins->inst_offset) {
2631
2632                         if (ins->dreg == last_ins->dreg) {
2633                                 MONO_DELETE_INS (bb, ins);
2634                         } else {
2635                                 ins->opcode = OP_MOVE;
2636                                 ins->sreg1 = last_ins->dreg;
2637                         }
2638
2639                         //g_assert_not_reached ();
2640
2641 #if 0
2642                         /*
2643                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2644                          * OP_LOAD_MEMBASE offset(basereg), reg
2645                          * -->
2646                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2647                          * OP_ICONST reg, imm
2648                          */
2649                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2650                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2651                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2652                                    ins->inst_offset == last_ins->inst_offset) {
2653                         ins->opcode = OP_ICONST;
2654                         ins->inst_c0 = last_ins->inst_imm;
2655                         g_assert_not_reached (); // check this rule
2656 #endif
2657                 }
2658                 break;
2659         case OP_LOADI1_MEMBASE:
2660         case OP_LOADU1_MEMBASE:
2661                 /*
2662                  * Note: if reg1 = reg2 the load op is removed
2663                  *
2664                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2665                  * OP_LOAD_MEMBASE offset(basereg), reg2
2666                  * -->
2667                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2668                  * OP_MOVE reg1, reg2
2669                  */
2670                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2671                         ins->inst_basereg == last_ins->inst_destbasereg &&
2672                         ins->inst_offset == last_ins->inst_offset) {
2673                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2674                         ins->sreg1 = last_ins->sreg1;
2675                 }
2676                 break;
2677         case OP_LOADI2_MEMBASE:
2678         case OP_LOADU2_MEMBASE:
2679                 /*
2680                  * Note: if reg1 = reg2 the load op is removed
2681                  *
2682                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2683                  * OP_LOAD_MEMBASE offset(basereg), reg2
2684                  * -->
2685                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2686                  * OP_MOVE reg1, reg2
2687                  */
2688                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2689                         ins->inst_basereg == last_ins->inst_destbasereg &&
2690                         ins->inst_offset == last_ins->inst_offset) {
2691 #if SIZEOF_REGISTER == 8
2692                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2693 #else
2694                         /* The definition of OP_PCONV_TO_U2 is wrong */
2695                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2696 #endif
2697                         ins->sreg1 = last_ins->sreg1;
2698                 }
2699                 break;
2700         case OP_MOVE:
2701         case OP_FMOVE:
2702                 /*
2703                  * Removes:
2704                  *
2705                  * OP_MOVE reg, reg
2706                  */
2707                 if (ins->dreg == ins->sreg1) {
2708                         MONO_DELETE_INS (bb, ins);
2709                         break;
2710                 }
2711                 /*
2712                  * Removes:
2713                  *
2714                  * OP_MOVE sreg, dreg
2715                  * OP_MOVE dreg, sreg
2716                  */
2717                 if (last_ins && last_ins->opcode == ins->opcode &&
2718                         ins->sreg1 == last_ins->dreg &&
2719                         ins->dreg == last_ins->sreg1) {
2720                         MONO_DELETE_INS (bb, ins);
2721                 }
2722                 break;
2723         case OP_NOP:
2724                 MONO_DELETE_INS (bb, ins);
2725                 break;
2726         }
2727 }
2728
2729 int
2730 mini_exception_id_by_name (const char *name)
2731 {
2732         if (strcmp (name, "IndexOutOfRangeException") == 0)
2733                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2734         if (strcmp (name, "OverflowException") == 0)
2735                 return MONO_EXC_OVERFLOW;
2736         if (strcmp (name, "ArithmeticException") == 0)
2737                 return MONO_EXC_ARITHMETIC;
2738         if (strcmp (name, "DivideByZeroException") == 0)
2739                 return MONO_EXC_DIVIDE_BY_ZERO;
2740         if (strcmp (name, "InvalidCastException") == 0)
2741                 return MONO_EXC_INVALID_CAST;
2742         if (strcmp (name, "NullReferenceException") == 0)
2743                 return MONO_EXC_NULL_REF;
2744         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2745                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2746         if (strcmp (name, "ArgumentException") == 0)
2747                 return MONO_EXC_ARGUMENT;
2748         g_error ("Unknown intrinsic exception %s\n", name);
2749         return -1;
2750 }
2751
2752 gboolean
2753 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2754 {
2755         MonoClass *klass;
2756         gpointer iter;
2757         MonoClassField *field;
2758         MonoType *ftype, *prev_ftype = NULL;
2759         int nfields = 0;
2760
2761         klass = mono_class_from_mono_type (t);
2762         iter = NULL;
2763         while ((field = mono_class_get_fields (klass, &iter))) {
2764                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2765                         continue;
2766                 ftype = mono_field_get_type (field);
2767                 ftype = mini_native_type_replace_type (ftype);
2768
2769                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2770                         int nested_nfields, nested_esize;
2771
2772                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2773                                 return FALSE;
2774                         if (nested_esize == 4)
2775                                 ftype = &mono_defaults.single_class->byval_arg;
2776                         else
2777                                 ftype = &mono_defaults.double_class->byval_arg;
2778                         if (prev_ftype && prev_ftype->type != ftype->type)
2779                                 return FALSE;
2780                         prev_ftype = ftype;
2781                         nfields += nested_nfields;
2782                 } else {
2783                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2784                                 return FALSE;
2785                         if (prev_ftype && prev_ftype->type != ftype->type)
2786                                 return FALSE;
2787                         prev_ftype = ftype;
2788                         nfields ++;
2789                 }
2790         }
2791         if (nfields == 0)
2792                 return FALSE;
2793         *out_nfields = nfields;
2794         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2795         return TRUE;
2796 }
2797
2798 MonoRegState*
2799 mono_regstate_new (void)
2800 {
2801         MonoRegState* rs = g_new0 (MonoRegState, 1);
2802
2803         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2804 #ifdef MONO_ARCH_NEED_SIMD_BANK
2805         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2806 #endif
2807
2808         return rs;
2809 }
2810
2811 void
2812 mono_regstate_free (MonoRegState *rs) {
2813         g_free (rs->vassign);
2814         g_free (rs);
2815 }
2816
2817 #endif /* DISABLE_JIT */