mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583         case OP_STORE_MEMBASE_IMM:
 584                 printf (" [%d]", (int)ins->inst_imm);
 585                 break;
 586         case OP_ADD_IMM:
 587         case OP_LADD_IMM:
 588                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 589                 break;
 590         case OP_I8CONST:
 591                 printf (" [%lld]", (long long)ins->inst_l);
 592                 break;
 593         case OP_R8CONST:
 594                 printf (" [%f]", *(double*)ins->inst_p0);
 595                 break;
 596         case OP_R4CONST:
 597                 printf (" [%f]", *(float*)ins->inst_p0);
 598                 break;
 599         case OP_CALL:
 600         case OP_CALL_MEMBASE:
 601         case OP_CALL_REG:
 602         case OP_FCALL:
 603         case OP_LCALL:
 604         case OP_VCALL:
 605         case OP_VCALL_REG:
 606         case OP_VCALL_MEMBASE:
 607         case OP_VCALL2:
 608         case OP_VCALL2_REG:
 609         case OP_VCALL2_MEMBASE:
 610         case OP_VOIDCALL:
 611         case OP_VOIDCALL_MEMBASE:
 612         case OP_TAILCALL: {
 613                 MonoCallInst *call = (MonoCallInst*)ins;
 614                 GSList *list;
 615
 616                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 617                         /*
 618                          * These are lowered opcodes, but they are in the .md files since the old
 619                          * JIT passes them to backends.
 620                          */
 621                         if (ins->dreg != -1)
 622                                 printf (" R%d <-", ins->dreg);
 623                 }
 624
 625                 if (call->method) {
 626                         char *full_name = mono_method_full_name (call->method, TRUE);
 627                         printf (" [%s]", full_name);
 628                         g_free (full_name);
 629                 } else if (call->fptr_is_patch) {
 630                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 631
 632                         printf (" ");
 633                         mono_print_ji (ji);
 634                 } else if (call->fptr) {
 635                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 636                         if (info)
 637                                 printf (" [%s]", info->name);
 638                 }
 639
 640                 list = call->out_ireg_args;
 641                 while (list) {
 642                         guint32 regpair;
 643                         int reg, hreg;
 644
 645                         regpair = (guint32)(gssize)(list->data);
 646                         hreg = regpair >> 24;
 647                         reg = regpair & 0xffffff;
 648
 649                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 650
 651                         list = g_slist_next (list);
 652                 }
 653                 break;
 654         }
 655         case OP_BR:
 656         case OP_CALL_HANDLER:
 657                 printf (" [B%d]", ins->inst_target_bb->block_num);
 658                 break;
 659         case OP_IBNE_UN:
 660         case OP_IBEQ:
 661         case OP_IBLT:
 662         case OP_IBLT_UN:
 663         case OP_IBGT:
 664         case OP_IBGT_UN:
 665         case OP_IBGE:
 666         case OP_IBGE_UN:
 667         case OP_IBLE:
 668         case OP_IBLE_UN:
 669         case OP_LBNE_UN:
 670         case OP_LBEQ:
 671         case OP_LBLT:
 672         case OP_LBLT_UN:
 673         case OP_LBGT:
 674         case OP_LBGT_UN:
 675         case OP_LBGE:
 676         case OP_LBGE_UN:
 677         case OP_LBLE:
 678         case OP_LBLE_UN:
 679                 if (!ins->inst_false_bb)
 680                         printf (" [B%d]", ins->inst_true_bb->block_num);
 681                 else
 682                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 683                 break;
 684         case OP_LIVERANGE_START:
 685         case OP_LIVERANGE_END:
 686         case OP_GC_LIVENESS_DEF:
 687         case OP_GC_LIVENESS_USE:
 688                 printf (" R%d", (int)ins->inst_c1);
 689                 break;
 690         case OP_IL_SEQ_POINT:
 691         case OP_SEQ_POINT:
 692                 printf (" il: %x", (int)ins->inst_imm);
 693                 break;
 694         default:
 695                 break;
 696         }
 697
 698         if (spec [MONO_INST_CLOB])
 699                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 700         printf ("\n");
 701 }
 702
 703 static void
 704 print_regtrack (RegTrack *t, int num)
 705 {
 706         int i;
 707         char buf [32];
 708         const char *r;
 709
 710         for (i = 0; i < num; ++i) {
 711                 if (!t [i].born_in)
 712                         continue;
 713                 if (i >= MONO_MAX_IREGS) {
 714                         g_snprintf (buf, sizeof(buf), "R%d", i);
 715                         r = buf;
 716                 } else
 717                         r = mono_arch_regname (i);
 718                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 719         }
 720 }
 721 #else
 722
 723 void
 724 mono_print_ji (const MonoJumpInfo *ji)
 725 {
 726 }
 727
 728 void
 729 mono_print_ins_index (int i, MonoInst *ins)
 730 {
 731 }
 732 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 733
 734 void
 735 mono_print_ins (MonoInst *ins)
 736 {
 737         mono_print_ins_index (-1, ins);
 738 }
 739
 740 static inline void
 741 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 742 {
 743         /*
 744          * If this function is called multiple times, the new instructions are inserted
 745          * in the proper order.
 746          */
 747         mono_bblock_insert_before_ins (bb, ins, to_insert);
 748 }
 749
 750 static inline void
 751 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 752 {
 753         /*
 754          * If this function is called multiple times, the new instructions are inserted in
 755          * proper order.
 756          */
 757         mono_bblock_insert_after_ins (bb, *last, to_insert);
 758
 759         *last = to_insert;
 760 }
 761
 762 static inline int
 763 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 764 {
 765         if (vreg_is_ref (cfg, reg))
 766                 return MONO_REG_INT_REF;
 767         else if (vreg_is_mp (cfg, reg))
 768                 return MONO_REG_INT_MP;
 769         else
 770                 return bank;
 771 }
 772
 773 /*
 774  * Force the spilling of the variable in the symbolic register 'reg', and free
 775  * the hreg it was assigned to.
 776  */
 777 static void
 778 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 779 {
 780         MonoInst *load;
 781         int i, sel, spill;
 782         int *symbolic;
 783         MonoRegState *rs = cfg->rs;
 784
 785         symbolic = rs->symbolic [bank];
 786         sel = rs->vassign [reg];
 787
 788         /* the vreg we need to spill lives in another logical reg bank */
 789         bank = translate_bank (cfg->rs, bank, sel);
 790
 791         /*i = rs->isymbolic [sel];
 792         g_assert (i == reg);*/
 793         i = reg;
 794         spill = ++cfg->spill_count;
 795         rs->vassign [i] = -spill - 1;
 796         if (G_UNLIKELY (bank))
 797                 mono_regstate_free_general (rs, sel, bank);
 798         else
 799                 mono_regstate_free_int (rs, sel);
 800         /* we need to create a spill var and insert a load to sel after the current instruction */
 801         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 802         load->dreg = sel;
 803         load->inst_basereg = cfg->frame_reg;
 804         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 805         insert_after_ins (bb, ins, last, load);
 806         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 807         if (G_UNLIKELY (bank))
 808                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 809         else
 810                 i = mono_regstate_alloc_int (rs, regmask (sel));
 811         g_assert (i == sel);
 812
 813         if (G_UNLIKELY (bank))
 814                 mono_regstate_free_general (rs, sel, bank);
 815         else
 816                 mono_regstate_free_int (rs, sel);
 817 }
 818
 819 /* This isn't defined on older glib versions and on some platforms */
 820 #ifndef G_GUINT64_FORMAT
 821 #define G_GUINT64_FORMAT "ul"
 822 #endif
 823
 824 static int
 825 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 826 {
 827         MonoInst *load;
 828         int i, sel, spill, num_sregs;
 829         int sregs [MONO_MAX_SRC_REGS];
 830         int *symbolic;
 831         MonoRegState *rs = cfg->rs;
 832
 833         symbolic = rs->symbolic [bank];
 834
 835         g_assert (bank < MONO_NUM_REGBANKS);
 836
 837         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 838         /* exclude the registers in the current instruction */
 839         num_sregs = mono_inst_get_src_registers (ins, sregs);
 840         for (i = 0; i < num_sregs; ++i) {
 841                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 842                         if (is_soft_reg (sregs [i], bank))
 843                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 844                         else
 845                                 regmask &= ~ (regmask (sregs [i]));
 846                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 847                 }
 848         }
 849         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 850                 regmask &= ~ (regmask (ins->dreg));
 851                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 852         }
 853
 854         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 855         g_assert (regmask); /* need at least a register we can free */
 856         sel = 0;
 857         /* we should track prev_use and spill the register that's farther */
 858         if (G_UNLIKELY (bank)) {
 859                 for (i = 0; i < regbank_size [bank]; ++i) {
 860                         if (regmask & (regmask (i))) {
 861                                 sel = i;
 862
 863                                 /* the vreg we need to load lives in another logical bank */
 864                                 bank = translate_bank (cfg->rs, bank, sel);
 865
 866                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 867                                 break;
 868                         }
 869                 }
 870
 871                 i = rs->symbolic [bank] [sel];
 872                 spill = ++cfg->spill_count;
 873                 rs->vassign [i] = -spill - 1;
 874                 mono_regstate_free_general (rs, sel, bank);
 875         }
 876         else {
 877                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 878                         if (regmask & (regmask (i))) {
 879                                 sel = i;
 880                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 881                                 break;
 882                         }
 883                 }
 884
 885                 i = rs->isymbolic [sel];
 886                 spill = ++cfg->spill_count;
 887                 rs->vassign [i] = -spill - 1;
 888                 mono_regstate_free_int (rs, sel);
 889         }
 890
 891         /* we need to create a spill var and insert a load to sel after the current instruction */
 892         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 893         load->dreg = sel;
 894         load->inst_basereg = cfg->frame_reg;
 895         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 896         insert_after_ins (bb, ins, last, load);
 897         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 898         if (G_UNLIKELY (bank))
 899                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 900         else
 901                 i = mono_regstate_alloc_int (rs, regmask (sel));
 902         g_assert (i == sel);
 903
 904         return sel;
 905 }
 906
 907 /*
 908  * free_up_hreg:
 909  *
 910  *   Free up the hreg HREG by spilling the vreg allocated to it.
 911  */
 912 static void
 913 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 914 {
 915         if (G_UNLIKELY (bank)) {
 916                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 917                         bank = translate_bank (cfg->rs, bank, hreg);
 918                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 919                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 920                 }
 921         }
 922         else {
 923                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 924                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 925                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 926                 }
 927         }
 928 }
 929
 930 static MonoInst*
 931 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 932 {
 933         MonoInst *copy;
 934
 935         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 936
 937         copy->dreg = dest;
 938         copy->sreg1 = src;
 939         copy->cil_code = ip;
 940         if (ins) {
 941                 mono_bblock_insert_after_ins (bb, ins, copy);
 942                 *last = copy;
 943         }
 944         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 945         return copy;
 946 }
 947
 948 static inline const char*
 949 regbank_to_string (int bank)
 950 {
 951         if (bank == MONO_REG_INT_REF)
 952                 return "REF ";
 953         else if (bank == MONO_REG_INT_MP)
 954                 return "MP ";
 955         else
 956                 return "";
 957 }
 958
 959 static void
 960 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 961 {
 962         MonoInst *store, *def;
 963
 964         bank = get_vreg_bank (cfg, prev_reg, bank);
 965
 966         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 967         store->sreg1 = reg;
 968         store->inst_destbasereg = cfg->frame_reg;
 969         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 970         if (ins) {
 971                 mono_bblock_insert_after_ins (bb, ins, store);
 972                 *last = store;
 973         } else if (insert_before) {
 974                 insert_before_ins (bb, insert_before, store);
 975         } else {
 976                 g_assert_not_reached ();
 977         }
 978         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 979
 980         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 981                 g_assert (prev_reg != -1);
 982                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 983                 def->inst_c0 = spill;
 984                 def->inst_c1 = bank;
 985                 mono_bblock_insert_after_ins (bb, store, def);
 986         }
 987 }
 988
 989 /* flags used in reginfo->flags */
 990 enum {
 991         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 992         MONO_FP_NEEDS_SPILL                     = regmask (1),
 993         MONO_FP_NEEDS_LOAD                      = regmask (2)
 994 };
 995
 996 static inline int
 997 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 998 {
 999         int val;
1000
1001         if (info && info->preferred_mask) {
1002                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1003                 if (val >= 0) {
1004                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1005                         return val;
1006                 }
1007         }
1008
1009         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1010         if (val < 0)
1011                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1012
1013         return val;
1014 }
1015
1016 static inline int
1017 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1018 {
1019         int val;
1020
1021         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1022
1023         if (val < 0)
1024                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1025
1026         return val;
1027 }
1028
1029 static inline int
1030 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1031 {
1032         if (G_UNLIKELY (bank))
1033                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1034         else
1035                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1036 }
1037
1038 static inline void
1039 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1040 {
1041         if (G_UNLIKELY (bank)) {
1042                 int mirrored_bank;
1043
1044                 g_assert (reg >= regbank_size [bank]);
1045                 g_assert (hreg < regbank_size [bank]);
1046                 g_assert (! is_global_freg (hreg));
1047
1048                 rs->vassign [reg] = hreg;
1049                 rs->symbolic [bank] [hreg] = reg;
1050                 rs->free_mask [bank] &= ~ (regmask (hreg));
1051
1052                 mirrored_bank = get_mirrored_bank (bank);
1053                 if (mirrored_bank == -1)
1054                         return;
1055
1056                 /* Make sure the other logical reg bank that this bank shares
1057                  * a single hard reg bank knows that this hard reg is not free.
1058                  */
1059                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1060
1061                 /* Mark the other logical bank that the this bank shares
1062                  * a single hard reg bank with as mirrored.
1063                  */
1064                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1065
1066         }
1067         else {
1068                 g_assert (reg >= MONO_MAX_IREGS);
1069                 g_assert (hreg < MONO_MAX_IREGS);
1070 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1071                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1072                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1073                 g_assert (! is_global_ireg (hreg));
1074 #endif
1075
1076                 rs->vassign [reg] = hreg;
1077                 rs->isymbolic [hreg] = reg;
1078                 rs->ifree_mask &= ~ (regmask (hreg));
1079         }
1080 }
1081
1082 static inline regmask_t
1083 get_callee_mask (const char spec)
1084 {
1085         if (G_UNLIKELY (reg_bank (spec)))
1086                 return regbank_callee_regs [reg_bank (spec)];
1087         return MONO_ARCH_CALLEE_REGS;
1088 }
1089
1090 static gint8 desc_to_fixed_reg [256];
1091 static gboolean desc_to_fixed_reg_inited = FALSE;
1092
1093 #ifndef DISABLE_JIT
1094
1095 /*
1096  * Local register allocation.
1097  * We first scan the list of instructions and we save the liveness info of
1098  * each register (when the register is first used, when it's value is set etc.).
1099  * We also reverse the list of instructions because assigning registers backwards allows
1100  * for more tricks to be used.
1101  */
1102 void
1103 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1104 {
1105         MonoInst *ins, *prev, *last;
1106         MonoInst **tmp;
1107         MonoRegState *rs = cfg->rs;
1108         int i, j, val, max;
1109         RegTrack *reginfo;
1110         const char *spec;
1111         unsigned char spec_src1, spec_dest;
1112         int bank = 0;
1113 #if MONO_ARCH_USE_FPSTACK
1114         gboolean has_fp = FALSE;
1115         int fpstack [8];
1116         int sp = 0;
1117 #endif
1118         int num_sregs = 0;
1119         int sregs [MONO_MAX_SRC_REGS];
1120
1121         if (!bb->code)
1122                 return;
1123
1124         if (!desc_to_fixed_reg_inited) {
1125                 for (i = 0; i < 256; ++i)
1126                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1127                 desc_to_fixed_reg_inited = TRUE;
1128
1129                 /* Validate the cpu description against the info in mini-ops.h */
1130 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1131                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1132                         const char *ispec;
1133
1134                         spec = ins_get_spec (i);
1135                         ispec = INS_INFO (i);
1136
1137                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1138                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1139                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1140                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1141                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1142                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1143                 }
1144 #endif
1145         }
1146
1147         rs->next_vreg = bb->max_vreg;
1148         mono_regstate_assign (rs);
1149
1150         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1151         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1152                 rs->free_mask [i] = regbank_callee_regs [i];
1153
1154         max = rs->next_vreg;
1155
1156         if (cfg->reginfo && cfg->reginfo_len < max)
1157                 cfg->reginfo = NULL;
1158
1159         reginfo = cfg->reginfo;
1160         if (!reginfo) {
1161                 cfg->reginfo_len = MAX (1024, max * 2);
1162                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1163         }
1164         else
1165                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1166
1167         if (cfg->verbose_level > 1) {
1168                 /* print_regtrack reads the info of all variables */
1169                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1170         }
1171
1172         /*
1173          * For large methods, next_vreg can be very large, so g_malloc0 time can
1174          * be prohibitive. So we manually init the reginfo entries used by the
1175          * bblock.
1176          */
1177         for (ins = bb->code; ins; ins = ins->next) {
1178                 gboolean modify = FALSE;
1179
1180                 spec = ins_get_spec (ins->opcode);
1181
1182                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1183                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1184 #if SIZEOF_REGISTER == 4
1185                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1186                                 /**
1187                                  * In the new IR, the two vregs of the regpair do not alias the
1188                                  * original long vreg. shift the vreg here so the rest of the
1189                                  * allocator doesn't have to care about it.
1190                                  */
1191                                 ins->dreg ++;
1192                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1193                         }
1194 #endif
1195                 }
1196
1197                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1198                 for (j = 0; j < num_sregs; ++j) {
1199                         g_assert (sregs [j] != -1);
1200                         if (sregs [j] < max) {
1201                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1202 #if SIZEOF_REGISTER == 4
1203                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1204                                         sregs [j]++;
1205                                         modify = TRUE;
1206                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1207                                 }
1208 #endif
1209                         }
1210                 }
1211                 if (modify)
1212                         mono_inst_set_src_registers (ins, sregs);
1213         }
1214
1215         /*if (cfg->opt & MONO_OPT_COPYPROP)
1216                 local_copy_prop (cfg, ins);*/
1217
1218         i = 1;
1219         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1220         /* forward pass on the instructions to collect register liveness info */
1221         MONO_BB_FOR_EACH_INS (bb, ins) {
1222                 spec = ins_get_spec (ins->opcode);
1223                 spec_dest = spec [MONO_INST_DEST];
1224
1225                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1226                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1227                 }
1228
1229                 DEBUG (mono_print_ins_index (i, ins));
1230
1231                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1232
1233 #if MONO_ARCH_USE_FPSTACK
1234                 if (dreg_is_fp (spec)) {
1235                         has_fp = TRUE;
1236                 } else {
1237                         for (j = 0; j < num_sregs; ++j) {
1238                                 if (sreg_is_fp (j, spec))
1239                                         has_fp = TRUE;
1240                         }
1241                 }
1242 #endif
1243
1244                 for (j = 0; j < num_sregs; ++j) {
1245                         int sreg = sregs [j];
1246                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1247                         if (sreg_spec) {
1248                                 bank = sreg_bank (j, spec);
1249                                 g_assert (sreg != -1);
1250                                 if (is_soft_reg (sreg, bank))
1251                                         /* This means the vreg is not local to this bb */
1252                                         g_assert (reginfo [sreg].born_in > 0);
1253                                 rs->vassign [sreg] = -1;
1254                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1255                                 //reginfo [ins->sreg2].last_use = i;
1256                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1257                                         /* The virtual register is allocated sequentially */
1258                                         rs->vassign [sreg + 1] = -1;
1259                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1260                                         //reginfo [ins->sreg2 + 1].last_use = i;
1261                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1262                                                 reginfo [sreg + 1].born_in = i;
1263                                 }
1264                         } else {
1265                                 sregs [j] = -1;
1266                         }
1267                 }
1268                 mono_inst_set_src_registers (ins, sregs);
1269
1270                 if (spec_dest) {
1271                         int dest_dreg;
1272
1273                         bank = dreg_bank (spec);
1274                         if (spec_dest != 'b') /* it's not just a base register */
1275                                 reginfo [ins->dreg].killed_in = i;
1276                         g_assert (ins->dreg != -1);
1277                         rs->vassign [ins->dreg] = -1;
1278                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1279                         //reginfo [ins->dreg].last_use = i;
1280                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1281                                 reginfo [ins->dreg].born_in = i;
1282
1283                         dest_dreg = desc_to_fixed_reg [spec_dest];
1284                         if (dest_dreg != -1)
1285                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1286
1287 #ifdef MONO_ARCH_INST_FIXED_MASK
1288                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1289 #endif
1290
1291                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1292                                 /* The virtual register is allocated sequentially */
1293                                 rs->vassign [ins->dreg + 1] = -1;
1294                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1295                                 //reginfo [ins->dreg + 1].last_use = i;
1296                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1297                                         reginfo [ins->dreg + 1].born_in = i;
1298                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1299                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1300                         }
1301                 } else {
1302                         ins->dreg = -1;
1303                 }
1304
1305                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1306                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1307
1308                         MonoCallInst *call = (MonoCallInst*)ins;
1309                         GSList *list;
1310
1311                         list = call->out_ireg_args;
1312                         if (list) {
1313                                 while (list) {
1314                                         guint32 regpair;
1315                                         int reg, hreg;
1316
1317                                         regpair = (guint32)(gssize)(list->data);
1318                                         hreg = regpair >> 24;
1319                                         reg = regpair & 0xffffff;
1320
1321                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1322                                         //reginfo [reg].last_use = i;
1323
1324                                         list = g_slist_next (list);
1325                                 }
1326                         }
1327
1328                         list = call->out_freg_args;
1329                         if (list) {
1330                                 while (list) {
1331                                         guint32 regpair;
1332                                         int reg, hreg;
1333
1334                                         regpair = (guint32)(gssize)(list->data);
1335                                         hreg = regpair >> 24;
1336                                         reg = regpair & 0xffffff;
1337
1338                                         list = g_slist_next (list);
1339                                 }
1340                         }
1341                 }
1342
1343                 ++i;
1344         }
1345
1346         tmp = &last;
1347
1348         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1349         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1350                 int prev_dreg, clob_dreg;
1351                 int dest_dreg, clob_reg;
1352                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1353                 int dreg_high, sreg1_high;
1354                 regmask_t dreg_mask, mask;
1355                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1356                 regmask_t dreg_fixed_mask;
1357                 const unsigned char *ip;
1358                 --i;
1359                 spec = ins_get_spec (ins->opcode);
1360                 spec_src1 = spec [MONO_INST_SRC1];
1361                 spec_dest = spec [MONO_INST_DEST];
1362                 prev_dreg = -1;
1363                 clob_dreg = -1;
1364                 clob_reg = -1;
1365                 dest_dreg = -1;
1366                 dreg_high = -1;
1367                 sreg1_high = -1;
1368                 dreg_mask = get_callee_mask (spec_dest);
1369                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1370                         prev_sregs [j] = -1;
1371                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1372                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1373 #ifdef MONO_ARCH_INST_FIXED_MASK
1374                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1375 #else
1376                         sreg_fixed_masks [j] = 0;
1377 #endif
1378                 }
1379
1380                 DEBUG (printf ("processing:"));
1381                 DEBUG (mono_print_ins_index (i, ins));
1382
1383                 ip = ins->cil_code;
1384
1385                 last = ins;
1386
1387                 /*
1388                  * FIXED REGS
1389                  */
1390                 dest_dreg = desc_to_fixed_reg [spec_dest];
1391                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1392                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1393
1394 #ifdef MONO_ARCH_INST_FIXED_MASK
1395                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1396 #else
1397                 dreg_fixed_mask = 0;
1398 #endif
1399
1400                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1401
1402                 /*
1403                  * TRACK FIXED SREG2, 3, ...
1404                  */
1405                 for (j = 1; j < num_sregs; ++j) {
1406                         int sreg = sregs [j];
1407                         int dest_sreg = dest_sregs [j];
1408
1409                         if (dest_sreg == -1)
1410                                 continue;
1411
1412                         if (j == 2) {
1413                                 int k;
1414
1415                                 /*
1416                                  * CAS.
1417                                  * We need to special case this, since on x86, there are only 3
1418                                  * free registers, and the code below assigns one of them to
1419                                  * sreg, so we can run out of registers when trying to assign
1420                                  * dreg. Instead, we just set up the register masks, and let the
1421                                  * normal sreg2 assignment code handle this. It would be nice to
1422                                  * do this for all the fixed reg cases too, but there is too much
1423                                  * risk of breakage.
1424                                  */
1425
1426                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1427                                 sreg_masks [j] = regmask (dest_sreg);
1428                                 for (k = 0; k < num_sregs; ++k) {
1429                                         if (k != j)
1430                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1431                                 }
1432
1433                                 /*
1434                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1435                                  */
1436                                 for (k = 0; k < num_sregs; ++k) {
1437                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1438                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1439                                 }
1440
1441                                 /*
1442                                  * We can also run out of registers while processing sreg2 if sreg3 is
1443                                  * assigned to another hreg, so spill sreg3 now.
1444                                  */
1445                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1446                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1447                                 }
1448                                 continue;
1449                         }
1450
1451                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1452                                 if (is_global_ireg (sreg)) {
1453                                         int k;
1454                                         /* Argument already in hard reg, need to copy */
1455                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1456                                         insert_before_ins (bb, ins, copy);
1457                                         for (k = 0; k < num_sregs; ++k) {
1458                                                 if (k != j)
1459                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1460                                         }
1461                                         /* See below */
1462                                         dreg_mask &= ~ (regmask (dest_sreg));
1463                                 } else {
1464                                         val = rs->vassign [sreg];
1465                                         if (val == -1) {
1466                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1467                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1468                                         } else if (val < -1) {
1469                                                 /* FIXME: */
1470                                                 g_assert_not_reached ();
1471                                         } else {
1472                                                 /* Argument already in hard reg, need to copy */
1473                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1474                                                 int k;
1475
1476                                                 insert_before_ins (bb, ins, copy);
1477                                                 for (k = 0; k < num_sregs; ++k) {
1478                                                         if (k != j)
1479                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1480                                                 }
1481                                                 /*
1482                                                  * Prevent the dreg from being allocated to dest_sreg
1483                                                  * too, since it could force sreg1 to be allocated to
1484                                                  * the same reg on x86.
1485                                                  */
1486                                                 dreg_mask &= ~ (regmask (dest_sreg));
1487                                         }
1488                                 }
1489                         } else {
1490                                 gboolean need_spill = TRUE;
1491                                 gboolean need_assign = TRUE;
1492                                 int k;
1493
1494                                 dreg_mask &= ~ (regmask (dest_sreg));
1495                                 for (k = 0; k < num_sregs; ++k) {
1496                                         if (k != j)
1497                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1498                                 }
1499
1500                                 /*
1501                                  * First check if dreg is assigned to dest_sreg2, since we
1502                                  * can't spill a dreg.
1503                                  */
1504                                 if (spec [MONO_INST_DEST])
1505                                         val = rs->vassign [ins->dreg];
1506                                 else
1507                                         val = -1;
1508                                 if (val == dest_sreg && ins->dreg != sreg) {
1509                                         /*
1510                                          * the destination register is already assigned to
1511                                          * dest_sreg2: we need to allocate another register for it
1512                                          * and then copy from this to dest_sreg2.
1513                                          */
1514                                         int new_dest;
1515                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1516                                         g_assert (new_dest >= 0);
1517                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1518
1519                                         prev_dreg = ins->dreg;
1520                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1521                                         clob_dreg = ins->dreg;
1522                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1523                                         mono_regstate_free_int (rs, dest_sreg);
1524                                         need_spill = FALSE;
1525                                 }
1526
1527                                 if (is_global_ireg (sreg)) {
1528                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1529                                         insert_before_ins (bb, ins, copy);
1530                                         need_assign = FALSE;
1531                                 }
1532                                 else {
1533                                         val = rs->vassign [sreg];
1534                                         if (val == dest_sreg) {
1535                                                 /* sreg2 is already assigned to the correct register */
1536                                                 need_spill = FALSE;
1537                                         } else if (val < -1) {
1538                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1539                                         } else if (val >= 0) {
1540                                                 /* sreg2 already assigned to another register */
1541                                                 /*
1542                                                  * We couldn't emit a copy from val to dest_sreg2, because
1543                                                  * val might be spilled later while processing this
1544                                                  * instruction. So we spill sreg2 so it can be allocated to
1545                                                  * dest_sreg2.
1546                                                  */
1547                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1548                                         }
1549                                 }
1550
1551                                 if (need_spill) {
1552                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1553                                 }
1554
1555                                 if (need_assign) {
1556                                         if (rs->vassign [sreg] < -1) {
1557                                                 int spill;
1558
1559                                                 /* Need to emit a spill store */
1560                                                 spill = - rs->vassign [sreg] - 1;
1561                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1562                                         }
1563                                         /* force-set sreg2 */
1564                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1565                                 }
1566                         }
1567                         sregs [j] = dest_sreg;
1568                 }
1569                 mono_inst_set_src_registers (ins, sregs);
1570
1571                 /*
1572                  * TRACK DREG
1573                  */
1574                 bank = dreg_bank (spec);
1575                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1576                         prev_dreg = ins->dreg;
1577                 }
1578
1579                 if (spec_dest == 'b') {
1580                         /*
1581                          * The dest reg is read by the instruction, not written, so
1582                          * avoid allocating sreg1/sreg2 to the same reg.
1583                          */
1584                         if (dest_sregs [0] != -1)
1585                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1586                         for (j = 1; j < num_sregs; ++j) {
1587                                 if (dest_sregs [j] != -1)
1588                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1589                         }
1590
1591                         val = rs->vassign [ins->dreg];
1592                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1593                                 /* DREG is already allocated to a register needed for sreg1 */
1594                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1595                         }
1596                 }
1597
1598                 /*
1599                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1600                  * various complex situations.
1601                  */
1602                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1603                         guint32 dreg2, dest_dreg2;
1604
1605                         g_assert (is_soft_reg (ins->dreg, bank));
1606
1607                         if (dest_dreg != -1) {
1608                                 if (rs->vassign [ins->dreg] != dest_dreg)
1609                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1610
1611                                 dreg2 = ins->dreg + 1;
1612                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1613                                 if (dest_dreg2 != -1) {
1614                                         if (rs->vassign [dreg2] != dest_dreg2)
1615                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1616                                 }
1617                         }
1618                 }
1619
1620                 if (dreg_fixed_mask) {
1621                         g_assert (!bank);
1622                         if (is_global_ireg (ins->dreg)) {
1623                                 /*
1624                                  * The argument is already in a hard reg, but that reg is
1625                                  * not usable by this instruction, so allocate a new one.
1626                                  */
1627                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1628                                 if (val < 0)
1629                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1630                                 mono_regstate_free_int (rs, val);
1631                                 dest_dreg = val;
1632
1633                                 /* Fall through */
1634                         }
1635                         else
1636                                 dreg_mask &= dreg_fixed_mask;
1637                 }
1638
1639                 if (is_soft_reg (ins->dreg, bank)) {
1640                         val = rs->vassign [ins->dreg];
1641
1642                         if (val < 0) {
1643                                 int spill = 0;
1644                                 if (val < -1) {
1645                                         /* the register gets spilled after this inst */
1646                                         spill = -val -1;
1647                                 }
1648                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1649                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1650                                 if (spill)
1651                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1652                         }
1653
1654                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1655                         ins->dreg = val;
1656                 }
1657
1658                 /* Handle regpairs */
1659                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1660                         int reg2 = prev_dreg + 1;
1661
1662                         g_assert (!bank);
1663                         g_assert (prev_dreg > -1);
1664                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1665                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1666 #ifdef TARGET_X86
1667                         /* bug #80489 */
1668                         mask &= ~regmask (X86_ECX);
1669 #endif
1670                         val = rs->vassign [reg2];
1671                         if (val < 0) {
1672                                 int spill = 0;
1673                                 if (val < -1) {
1674                                         /* the register gets spilled after this inst */
1675                                         spill = -val -1;
1676                                 }
1677                                 val = mono_regstate_alloc_int (rs, mask);
1678                                 if (val < 0)
1679                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1680                                 if (spill)
1681                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1682                         }
1683                         else {
1684                                 if (! (mask & (regmask (val)))) {
1685                                         val = mono_regstate_alloc_int (rs, mask);
1686                                         if (val < 0)
1687                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1688
1689                                         /* Reallocate hreg to the correct register */
1690                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1691
1692                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1693                                 }
1694                         }
1695
1696                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1697                         assign_reg (cfg, rs, reg2, val, bank);
1698
1699                         dreg_high = val;
1700                         ins->backend.reg3 = val;
1701
1702                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1703                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1704                                 mono_regstate_free_int (rs, val);
1705                         }
1706                 }
1707
1708                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1709                         /*
1710                          * In theory, we could free up the hreg even if the vreg is alive,
1711                          * but branches inside bblocks force us to assign the same hreg
1712                          * to a vreg every time it is encountered.
1713                          */
1714                         int dreg = rs->vassign [prev_dreg];
1715                         g_assert (dreg >= 0);
1716                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1717                         if (G_UNLIKELY (bank))
1718                                 mono_regstate_free_general (rs, dreg, bank);
1719                         else
1720                                 mono_regstate_free_int (rs, dreg);
1721                         rs->vassign [prev_dreg] = -1;
1722                 }
1723
1724                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1725                         /* this instruction only outputs to dest_dreg, need to copy */
1726                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1727                         ins->dreg = dest_dreg;
1728
1729                         if (G_UNLIKELY (bank)) {
1730                                 /* the register we need to free up may be used in another logical regbank
1731                                  * so do a translate just in case.
1732                                  */
1733                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1734                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1735                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1736                         }
1737                         else {
1738                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1739                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1740                         }
1741                 }
1742
1743                 if (spec_dest == 'b') {
1744                         /*
1745                          * The dest reg is read by the instruction, not written, so
1746                          * avoid allocating sreg1/sreg2 to the same reg.
1747                          */
1748                         for (j = 0; j < num_sregs; ++j)
1749                                 if (!sreg_bank (j, spec))
1750                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1751                 }
1752
1753                 /*
1754                  * TRACK CLOBBERING
1755                  */
1756                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1757                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1758                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1759                 }
1760
1761                 if (spec [MONO_INST_CLOB] == 'c') {
1762                         int j, s, dreg, dreg2, cur_bank;
1763                         guint64 clob_mask;
1764
1765                         clob_mask = MONO_ARCH_CALLEE_REGS;
1766
1767                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1768                                 /*
1769                                  * Need to avoid spilling the dreg since the dreg is not really
1770                                  * clobbered by the call.
1771                                  */
1772                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1773                                         dreg = rs->vassign [prev_dreg];
1774                                 else
1775                                         dreg = -1;
1776
1777                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1778                                         dreg2 = rs->vassign [prev_dreg + 1];
1779                                 else
1780                                         dreg2 = -1;
1781
1782                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1783                                         s = regmask (j);
1784                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1785                                                 if ((j != dreg) && (j != dreg2))
1786                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1787                                                 else if (rs->isymbolic [j])
1788                                                         /* The hreg is assigned to the dreg of this instruction */
1789                                                         rs->vassign [rs->isymbolic [j]] = -1;
1790                                                 mono_regstate_free_int (rs, j);
1791                                         }
1792                                 }
1793                         }
1794
1795                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1796                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1797                                         clob_mask = regbank_callee_regs [cur_bank];
1798                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1799                                                 dreg = rs->vassign [prev_dreg];
1800                                         else
1801                                                 dreg = -1;
1802
1803                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1804
1805                                                 /* we are looping though the banks in the outer loop
1806                                                  * so, we don't need to deal with mirrored hregs
1807                                                  * because we will get them in one of the other bank passes.
1808                                                  */
1809                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1810                                                         continue;
1811
1812                                                 s = regmask (j);
1813                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1814                                                         if (j != dreg)
1815                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1816                                                         else if (rs->symbolic [cur_bank] [j])
1817                                                                 /* The hreg is assigned to the dreg of this instruction */
1818                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1819                                                         mono_regstate_free_general (rs, j, cur_bank);
1820                                                 }
1821                                         }
1822                                 }
1823                         }
1824                 }
1825
1826                 /*
1827                  * TRACK ARGUMENT REGS
1828                  */
1829                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1830                         MonoCallInst *call = (MonoCallInst*)ins;
1831                         GSList *list;
1832
1833                         /*
1834                          * This needs to be done before assigning sreg1, so sreg1 will
1835                          * not be assigned one of the argument regs.
1836                          */
1837
1838                         /*
1839                          * Assign all registers in call->out_reg_args to the proper
1840                          * argument registers.
1841                          */
1842
1843                         list = call->out_ireg_args;
1844                         if (list) {
1845                                 while (list) {
1846                                         guint32 regpair;
1847                                         int reg, hreg;
1848
1849                                         regpair = (guint32)(gssize)(list->data);
1850                                         hreg = regpair >> 24;
1851                                         reg = regpair & 0xffffff;
1852
1853                                         assign_reg (cfg, rs, reg, hreg, 0);
1854
1855                                         sreg_masks [0] &= ~(regmask (hreg));
1856
1857                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1858
1859                                         list = g_slist_next (list);
1860                                 }
1861                         }
1862
1863                         list = call->out_freg_args;
1864                         if (list) {
1865                                 while (list) {
1866                                         guint32 regpair;
1867                                         int reg, hreg;
1868
1869                                         regpair = (guint32)(gssize)(list->data);
1870                                         hreg = regpair >> 24;
1871                                         reg = regpair & 0xffffff;
1872
1873                                         assign_reg (cfg, rs, reg, hreg, 1);
1874
1875                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1876
1877                                         list = g_slist_next (list);
1878                                 }
1879                         }
1880                 }
1881
1882                 /*
1883                  * TRACK SREG1
1884                  */
1885                 bank = sreg1_bank (spec);
1886                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1887                         int sreg1 = sregs [0];
1888                         int dest_sreg1 = dest_sregs [0];
1889
1890                         g_assert (is_soft_reg (sreg1, bank));
1891
1892                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1893                         if (dest_sreg1 != -1)
1894                                 g_assert (dest_sreg1 == ins->dreg);
1895                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1896                         g_assert (val >= 0);
1897
1898                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1899                                 // FIXME:
1900                                 g_assert_not_reached ();
1901
1902                         assign_reg (cfg, rs, sreg1, val, bank);
1903
1904                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1905
1906                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1907                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1908                         g_assert (val >= 0);
1909
1910                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1911                                 // FIXME:
1912                                 g_assert_not_reached ();
1913
1914                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1915
1916                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1917
1918                         /* Skip rest of this section */
1919                         dest_sregs [0] = -1;
1920                 }
1921
1922                 if (sreg_fixed_masks [0]) {
1923                         g_assert (!bank);
1924                         if (is_global_ireg (sregs [0])) {
1925                                 /*
1926                                  * The argument is already in a hard reg, but that reg is
1927                                  * not usable by this instruction, so allocate a new one.
1928                                  */
1929                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1930                                 if (val < 0)
1931                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1932                                 mono_regstate_free_int (rs, val);
1933                                 dest_sregs [0] = val;
1934
1935                                 /* Fall through to the dest_sreg1 != -1 case */
1936                         }
1937                         else
1938                                 sreg_masks [0] &= sreg_fixed_masks [0];
1939                 }
1940
1941                 if (dest_sregs [0] != -1) {
1942                         sreg_masks [0] = regmask (dest_sregs [0]);
1943
1944                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1945                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1946                         }
1947                         if (is_global_ireg (sregs [0])) {
1948                                 /* The argument is already in a hard reg, need to copy */
1949                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1950                                 insert_before_ins (bb, ins, copy);
1951                                 sregs [0] = dest_sregs [0];
1952                         }
1953                 }
1954
1955                 if (is_soft_reg (sregs [0], bank)) {
1956                         val = rs->vassign [sregs [0]];
1957                         prev_sregs [0] = sregs [0];
1958                         if (val < 0) {
1959                                 int spill = 0;
1960                                 if (val < -1) {
1961                                         /* the register gets spilled after this inst */
1962                                         spill = -val -1;
1963                                 }
1964
1965                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1966                                         /*
1967                                          * Allocate the same hreg to sreg1 as well so the
1968                                          * peephole can get rid of the move.
1969                                          */
1970                                         sreg_masks [0] = regmask (ins->dreg);
1971                                 }
1972
1973                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1974                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1975                                         sreg_masks [0] = regmask (ins->dreg);
1976
1977                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1978                                 assign_reg (cfg, rs, sregs [0], val, bank);
1979                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1980
1981                                 if (spill) {
1982                                         /*
1983                                          * Need to insert before the instruction since it can
1984                                          * overwrite sreg1.
1985                                          */
1986                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1987                                 }
1988                         }
1989                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1990                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1991                                 insert_before_ins (bb, ins, copy);
1992                                 for (j = 1; j < num_sregs; ++j)
1993                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1994                                 val = dest_sregs [0];
1995                         }
1996
1997                         sregs [0] = val;
1998                 }
1999                 else {
2000                         prev_sregs [0] = -1;
2001                 }
2002                 mono_inst_set_src_registers (ins, sregs);
2003
2004                 for (j = 1; j < num_sregs; ++j)
2005                         sreg_masks [j] &= ~(regmask (sregs [0]));
2006
2007                 /* Handle the case when sreg1 is a regpair but dreg is not */
2008                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2009                         int reg2 = prev_sregs [0] + 1;
2010
2011                         g_assert (!bank);
2012                         g_assert (prev_sregs [0] > -1);
2013                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2014                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2015                         val = rs->vassign [reg2];
2016                         if (val < 0) {
2017                                 int spill = 0;
2018                                 if (val < -1) {
2019                                         /* the register gets spilled after this inst */
2020                                         spill = -val -1;
2021                                 }
2022                                 val = mono_regstate_alloc_int (rs, mask);
2023                                 if (val < 0)
2024                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2025                                 if (spill)
2026                                         g_assert_not_reached ();
2027                         }
2028                         else {
2029                                 if (! (mask & (regmask (val)))) {
2030                                         /* The vreg is already allocated to a wrong hreg */
2031                                         /* FIXME: */
2032                                         g_assert_not_reached ();
2033 #if 0
2034                                         val = mono_regstate_alloc_int (rs, mask);
2035                                         if (val < 0)
2036                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2037
2038                                         /* Reallocate hreg to the correct register */
2039                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2040
2041                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2042 #endif
2043                                 }
2044                         }
2045
2046                         sreg1_high = val;
2047                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2048                         assign_reg (cfg, rs, reg2, val, bank);
2049                 }
2050
2051                 /* Handle dreg==sreg1 */
2052                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2053                         MonoInst *sreg2_copy = NULL;
2054                         MonoInst *copy;
2055                         int bank = reg_bank (spec_src1);
2056
2057                         if (ins->dreg == sregs [1]) {
2058                                 /*
2059                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2060                                  * register for it.
2061                                  */
2062                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2063
2064                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2065                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2066                                 prev_sregs [1] = sregs [1] = reg2;
2067
2068                                 if (G_UNLIKELY (bank))
2069                                         mono_regstate_free_general (rs, reg2, bank);
2070                                 else
2071                                         mono_regstate_free_int (rs, reg2);
2072                         }
2073
2074                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2075                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2076                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2077                                         /* FIXME: */
2078                                         g_assert_not_reached ();
2079
2080                                 /*
2081                                  * sreg1 and dest are already allocated to the same regpair by the
2082                                  * SREG1 allocation code.
2083                                  */
2084                                 g_assert (sregs [0] == ins->dreg);
2085                                 g_assert (dreg_high == sreg1_high);
2086                         }
2087
2088                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2089                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2090                         insert_before_ins (bb, ins, copy);
2091
2092                         if (sreg2_copy)
2093                                 insert_before_ins (bb, copy, sreg2_copy);
2094
2095                         /*
2096                          * Need to prevent sreg2 to be allocated to sreg1, since that
2097                          * would screw up the previous copy.
2098                          */
2099                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2100                         /* we set sreg1 to dest as well */
2101                         prev_sregs [0] = sregs [0] = ins->dreg;
2102                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2103                 }
2104                 mono_inst_set_src_registers (ins, sregs);
2105
2106                 /*
2107                  * TRACK SREG2, 3, ...
2108                  */
2109                 for (j = 1; j < num_sregs; ++j) {
2110                         int k;
2111
2112                         bank = sreg_bank (j, spec);
2113                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2114                                 g_assert_not_reached ();
2115
2116                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2117                                 /*
2118                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2119                                  * allocating it to the fixed reg.
2120                                  */
2121                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2122                                 insert_before_ins (bb, ins, copy);
2123                                 sregs [j] = dest_sregs [j];
2124                         } else if (is_soft_reg (sregs [j], bank)) {
2125                                 val = rs->vassign [sregs [j]];
2126
2127                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2128                                         /*
2129                                          * The sreg is already allocated to a hreg, but not to the fixed
2130                                          * reg required by the instruction. Spill the sreg, so it can be
2131                                          * allocated to the fixed reg by the code below.
2132                                          */
2133                                         /* Currently, this code should only be hit for CAS */
2134                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2135                                         val = rs->vassign [sregs [j]];
2136                                 }
2137
2138                                 if (val < 0) {
2139                                         int spill = 0;
2140                                         if (val < -1) {
2141                                                 /* the register gets spilled after this inst */
2142                                                 spill = -val -1;
2143                                         }
2144                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2145                                         assign_reg (cfg, rs, sregs [j], val, bank);
2146                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2147                                         if (spill) {
2148                                                 /*
2149                                                  * Need to insert before the instruction since it can
2150                                                  * overwrite sreg2.
2151                                                  */
2152                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2153                                         }
2154                                 }
2155                                 sregs [j] = val;
2156                                 for (k = j + 1; k < num_sregs; ++k)
2157                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2158                         }
2159                         else {
2160                                 prev_sregs [j] = -1;
2161                         }
2162                 }
2163                 mono_inst_set_src_registers (ins, sregs);
2164
2165                 /* Sanity check */
2166                 /* Do this only for CAS for now */
2167                 for (j = 1; j < num_sregs; ++j) {
2168                         int sreg = sregs [j];
2169                         int dest_sreg = dest_sregs [j];
2170
2171                         if (j == 2 && dest_sreg != -1) {
2172                                 int k;
2173
2174                                 g_assert (sreg == dest_sreg);
2175
2176                                 for (k = 0; k < num_sregs; ++k) {
2177                                         if (k != j)
2178                                                 g_assert (sregs [k] != dest_sreg);
2179                                 }
2180                         }
2181                 }
2182
2183                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2184                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2185                         mono_regstate_free_int (rs, ins->sreg1);
2186                 }
2187                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2188                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2189                         mono_regstate_free_int (rs, ins->sreg2);
2190                 }*/
2191
2192                 DEBUG (mono_print_ins_index (i, ins));
2193         }
2194
2195         // FIXME: Set MAX_FREGS to 8
2196         // FIXME: Optimize generated code
2197 #if MONO_ARCH_USE_FPSTACK
2198         /*
2199          * Make a forward pass over the code, simulating the fp stack, making sure the
2200          * arguments required by the fp opcodes are at the top of the stack.
2201          */
2202         if (has_fp) {
2203                 MonoInst *prev = NULL;
2204                 MonoInst *fxch;
2205                 int tmp;
2206
2207                 g_assert (num_sregs <= 2);
2208
2209                 for (ins = bb->code; ins; ins = ins->next) {
2210                         spec = ins_get_spec (ins->opcode);
2211
2212                         DEBUG (printf ("processing:"));
2213                         DEBUG (mono_print_ins_index (0, ins));
2214
2215                         if (ins->opcode == OP_FMOVE) {
2216                                 /* Do it by renaming the source to the destination on the stack */
2217                                 // FIXME: Is this correct ?
2218                                 for (i = 0; i < sp; ++i)
2219                                         if (fpstack [i] == ins->sreg1)
2220                                                 fpstack [i] = ins->dreg;
2221                                 prev = ins;
2222                                 continue;
2223                         }
2224
2225                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2226                                 /* Arg1 must be in %st(1) */
2227                                 g_assert (prev);
2228
2229                                 i = 0;
2230                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2231                                         i ++;
2232                                 g_assert (i < sp);
2233
2234                                 if (sp - 1 - i > 0) {
2235                                         /* First move it to %st(0) */
2236                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2237
2238                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2239                                         fxch->inst_imm = sp - 1 - i;
2240
2241                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2242                                         prev = fxch;
2243
2244                                         tmp = fpstack [sp - 1];
2245                                         fpstack [sp - 1] = fpstack [i];
2246                                         fpstack [i] = tmp;
2247                                 }
2248
2249                                 /* Then move it to %st(1) */
2250                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2251
2252                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2253                                 fxch->inst_imm = 1;
2254
2255                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2256                                 prev = fxch;
2257
2258                                 tmp = fpstack [sp - 1];
2259                                 fpstack [sp - 1] = fpstack [sp - 2];
2260                                 fpstack [sp - 2] = tmp;
2261                         }
2262
2263                         if (sreg2_is_fp (spec)) {
2264                                 g_assert (sp > 0);
2265
2266                                 if (fpstack [sp - 1] != ins->sreg2) {
2267                                         g_assert (prev);
2268
2269                                         i = 0;
2270                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2271                                                 i ++;
2272                                         g_assert (i < sp);
2273
2274                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2275
2276                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2277                                         fxch->inst_imm = sp - 1 - i;
2278
2279                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2280                                         prev = fxch;
2281
2282                                         tmp = fpstack [sp - 1];
2283                                         fpstack [sp - 1] = fpstack [i];
2284                                         fpstack [i] = tmp;
2285                                 }
2286
2287                                 sp --;
2288                         }
2289
2290                         if (sreg1_is_fp (spec)) {
2291                                 g_assert (sp > 0);
2292
2293                                 if (fpstack [sp - 1] != ins->sreg1) {
2294                                         g_assert (prev);
2295
2296                                         i = 0;
2297                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2298                                                 i ++;
2299                                         g_assert (i < sp);
2300
2301                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2302
2303                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2304                                         fxch->inst_imm = sp - 1 - i;
2305
2306                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2307                                         prev = fxch;
2308
2309                                         tmp = fpstack [sp - 1];
2310                                         fpstack [sp - 1] = fpstack [i];
2311                                         fpstack [i] = tmp;
2312                                 }
2313
2314                                 sp --;
2315                         }
2316
2317                         if (dreg_is_fp (spec)) {
2318                                 g_assert (sp < 8);
2319                                 fpstack [sp ++] = ins->dreg;
2320                         }
2321
2322                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2323                                 printf ("\t[");
2324                                 for (i = 0; i < sp; ++i)
2325                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2326                                 printf ("]\n");
2327                         }
2328
2329                         prev = ins;
2330                 }
2331
2332                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2333                         /* Remove remaining items from the fp stack */
2334                         /*
2335                          * These can remain for example as a result of a dead fmove like in
2336                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2337                          */
2338                         while (sp) {
2339                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2340                                 mono_add_ins_to_end (bb, ins);
2341                                 sp --;
2342                         }
2343                 }
2344         }
2345 #endif
2346 }
2347
2348 CompRelation
2349 mono_opcode_to_cond (int opcode)
2350 {
2351         switch (opcode) {
2352         case OP_CEQ:
2353         case OP_IBEQ:
2354         case OP_ICEQ:
2355         case OP_LBEQ:
2356         case OP_LCEQ:
2357         case OP_FBEQ:
2358         case OP_FCEQ:
2359         case OP_RBEQ:
2360         case OP_RCEQ:
2361         case OP_COND_EXC_EQ:
2362         case OP_COND_EXC_IEQ:
2363         case OP_CMOV_IEQ:
2364         case OP_CMOV_LEQ:
2365                 return CMP_EQ;
2366         case OP_FCNEQ:
2367         case OP_ICNEQ:
2368         case OP_IBNE_UN:
2369         case OP_LBNE_UN:
2370         case OP_FBNE_UN:
2371         case OP_COND_EXC_NE_UN:
2372         case OP_COND_EXC_INE_UN:
2373         case OP_CMOV_INE_UN:
2374         case OP_CMOV_LNE_UN:
2375                 return CMP_NE;
2376         case OP_FCLE:
2377         case OP_ICLE:
2378         case OP_IBLE:
2379         case OP_LBLE:
2380         case OP_FBLE:
2381         case OP_CMOV_ILE:
2382         case OP_CMOV_LLE:
2383                 return CMP_LE;
2384         case OP_FCGE:
2385         case OP_ICGE:
2386         case OP_IBGE:
2387         case OP_LBGE:
2388         case OP_FBGE:
2389         case OP_CMOV_IGE:
2390         case OP_CMOV_LGE:
2391                 return CMP_GE;
2392         case OP_CLT:
2393         case OP_IBLT:
2394         case OP_ICLT:
2395         case OP_LBLT:
2396         case OP_LCLT:
2397         case OP_FBLT:
2398         case OP_FCLT:
2399         case OP_RBLT:
2400         case OP_RCLT:
2401         case OP_COND_EXC_LT:
2402         case OP_COND_EXC_ILT:
2403         case OP_CMOV_ILT:
2404         case OP_CMOV_LLT:
2405                 return CMP_LT;
2406         case OP_CGT:
2407         case OP_IBGT:
2408         case OP_ICGT:
2409         case OP_LBGT:
2410         case OP_LCGT:
2411         case OP_FBGT:
2412         case OP_FCGT:
2413         case OP_RBGT:
2414         case OP_RCGT:
2415         case OP_COND_EXC_GT:
2416         case OP_COND_EXC_IGT:
2417         case OP_CMOV_IGT:
2418         case OP_CMOV_LGT:
2419                 return CMP_GT;
2420
2421         case OP_ICLE_UN:
2422         case OP_IBLE_UN:
2423         case OP_LBLE_UN:
2424         case OP_FBLE_UN:
2425         case OP_COND_EXC_LE_UN:
2426         case OP_COND_EXC_ILE_UN:
2427         case OP_CMOV_ILE_UN:
2428         case OP_CMOV_LLE_UN:
2429                 return CMP_LE_UN;
2430
2431         case OP_ICGE_UN:
2432         case OP_IBGE_UN:
2433         case OP_LBGE_UN:
2434         case OP_FBGE_UN:
2435         case OP_CMOV_IGE_UN:
2436         case OP_CMOV_LGE_UN:
2437                 return CMP_GE_UN;
2438         case OP_CLT_UN:
2439         case OP_IBLT_UN:
2440         case OP_ICLT_UN:
2441         case OP_LBLT_UN:
2442         case OP_LCLT_UN:
2443         case OP_FBLT_UN:
2444         case OP_FCLT_UN:
2445         case OP_RBLT_UN:
2446         case OP_RCLT_UN:
2447         case OP_COND_EXC_LT_UN:
2448         case OP_COND_EXC_ILT_UN:
2449         case OP_CMOV_ILT_UN:
2450         case OP_CMOV_LLT_UN:
2451                 return CMP_LT_UN;
2452         case OP_CGT_UN:
2453         case OP_IBGT_UN:
2454         case OP_ICGT_UN:
2455         case OP_LBGT_UN:
2456         case OP_LCGT_UN:
2457         case OP_FCGT_UN:
2458         case OP_FBGT_UN:
2459         case OP_RCGT_UN:
2460         case OP_RBGT_UN:
2461         case OP_COND_EXC_GT_UN:
2462         case OP_COND_EXC_IGT_UN:
2463         case OP_CMOV_IGT_UN:
2464         case OP_CMOV_LGT_UN:
2465                 return CMP_GT_UN;
2466         default:
2467                 printf ("%s\n", mono_inst_name (opcode));
2468                 g_assert_not_reached ();
2469                 return 0;
2470         }
2471 }
2472
2473 CompRelation
2474 mono_negate_cond (CompRelation cond)
2475 {
2476         switch (cond) {
2477         case CMP_EQ:
2478                 return CMP_NE;
2479         case CMP_NE:
2480                 return CMP_EQ;
2481         case CMP_LE:
2482                 return CMP_GT;
2483         case CMP_GE:
2484                 return CMP_LT;
2485         case CMP_LT:
2486                 return CMP_GE;
2487         case CMP_GT:
2488                 return CMP_LE;
2489         case CMP_LE_UN:
2490                 return CMP_GT_UN;
2491         case CMP_GE_UN:
2492                 return CMP_LT_UN;
2493         case CMP_LT_UN:
2494                 return CMP_GE_UN;
2495         case CMP_GT_UN:
2496                 return CMP_LE_UN;
2497         default:
2498                 g_assert_not_reached ();
2499         }
2500 }
2501
2502 CompType
2503 mono_opcode_to_type (int opcode, int cmp_opcode)
2504 {
2505         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2506                 return CMP_TYPE_L;
2507         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2508                 return CMP_TYPE_I;
2509         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2510                 return CMP_TYPE_I;
2511         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2512                 return CMP_TYPE_L;
2513         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2514                 return CMP_TYPE_L;
2515         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2516                 return CMP_TYPE_F;
2517         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2518                 return CMP_TYPE_F;
2519         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2520                 return CMP_TYPE_I;
2521         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2522                 switch (cmp_opcode) {
2523                 case OP_ICOMPARE:
2524                 case OP_ICOMPARE_IMM:
2525                         return CMP_TYPE_I;
2526                 default:
2527                         return CMP_TYPE_L;
2528                 }
2529         } else {
2530                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2531                 return 0;
2532         }
2533 }
2534
2535 #endif /* DISABLE_JIT */
2536
2537 gboolean
2538 mono_is_regsize_var (MonoType *t)
2539 {
2540         if (t->byref)
2541                 return TRUE;
2542         t = mono_type_get_underlying_type (t);
2543         switch (t->type) {
2544         case MONO_TYPE_BOOLEAN:
2545         case MONO_TYPE_CHAR:
2546         case MONO_TYPE_I1:
2547         case MONO_TYPE_U1:
2548         case MONO_TYPE_I2:
2549         case MONO_TYPE_U2:
2550         case MONO_TYPE_I4:
2551         case MONO_TYPE_U4:
2552         case MONO_TYPE_I:
2553         case MONO_TYPE_U:
2554         case MONO_TYPE_PTR:
2555         case MONO_TYPE_FNPTR:
2556 #if SIZEOF_REGISTER == 8
2557         case MONO_TYPE_I8:
2558         case MONO_TYPE_U8:
2559 #endif
2560                 return TRUE;
2561         case MONO_TYPE_OBJECT:
2562         case MONO_TYPE_STRING:
2563         case MONO_TYPE_CLASS:
2564         case MONO_TYPE_SZARRAY:
2565         case MONO_TYPE_ARRAY:
2566                 return TRUE;
2567         case MONO_TYPE_GENERICINST:
2568                 if (!mono_type_generic_inst_is_valuetype (t))
2569                         return TRUE;
2570                 return FALSE;
2571         case MONO_TYPE_VALUETYPE:
2572                 return FALSE;
2573         default:
2574                 return FALSE;
2575         }
2576 }
2577
2578 #ifndef DISABLE_JIT
2579
2580 /*
2581  * mono_peephole_ins:
2582  *
2583  *   Perform some architecture independent peephole optimizations.
2584  */
2585 void
2586 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2587 {
2588         int filter = FILTER_IL_SEQ_POINT;
2589         MonoInst *last_ins = mono_inst_prev (ins, filter);
2590
2591         switch (ins->opcode) {
2592         case OP_MUL_IMM:
2593                 /* remove unnecessary multiplication with 1 */
2594                 if (ins->inst_imm == 1) {
2595                         if (ins->dreg != ins->sreg1)
2596                                 ins->opcode = OP_MOVE;
2597                         else
2598                                 MONO_DELETE_INS (bb, ins);
2599                 }
2600                 break;
2601         case OP_LOAD_MEMBASE:
2602         case OP_LOADI4_MEMBASE:
2603                 /*
2604                  * Note: if reg1 = reg2 the load op is removed
2605                  *
2606                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2607                  * OP_LOAD_MEMBASE offset(basereg), reg2
2608                  * -->
2609                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2610                  * OP_MOVE reg1, reg2
2611                  */
2612                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2613                         last_ins = mono_inst_prev (ins, filter);
2614                 if (last_ins &&
2615                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2616                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2617                         ins->inst_basereg == last_ins->inst_destbasereg &&
2618                         ins->inst_offset == last_ins->inst_offset) {
2619                         if (ins->dreg == last_ins->sreg1) {
2620                                 MONO_DELETE_INS (bb, ins);
2621                                 break;
2622                         } else {
2623                                 ins->opcode = OP_MOVE;
2624                                 ins->sreg1 = last_ins->sreg1;
2625                         }
2626
2627                         /*
2628                          * Note: reg1 must be different from the basereg in the second load
2629                          * Note: if reg1 = reg2 is equal then second load is removed
2630                          *
2631                          * OP_LOAD_MEMBASE offset(basereg), reg1
2632                          * OP_LOAD_MEMBASE offset(basereg), reg2
2633                          * -->
2634                          * OP_LOAD_MEMBASE offset(basereg), reg1
2635                          * OP_MOVE reg1, reg2
2636                          */
2637                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2638                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2639                           ins->inst_basereg != last_ins->dreg &&
2640                           ins->inst_basereg == last_ins->inst_basereg &&
2641                           ins->inst_offset == last_ins->inst_offset) {
2642
2643                         if (ins->dreg == last_ins->dreg) {
2644                                 MONO_DELETE_INS (bb, ins);
2645                         } else {
2646                                 ins->opcode = OP_MOVE;
2647                                 ins->sreg1 = last_ins->dreg;
2648                         }
2649
2650                         //g_assert_not_reached ();
2651
2652 #if 0
2653                         /*
2654                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2655                          * OP_LOAD_MEMBASE offset(basereg), reg
2656                          * -->
2657                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2658                          * OP_ICONST reg, imm
2659                          */
2660                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2661                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2662                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2663                                    ins->inst_offset == last_ins->inst_offset) {
2664                         ins->opcode = OP_ICONST;
2665                         ins->inst_c0 = last_ins->inst_imm;
2666                         g_assert_not_reached (); // check this rule
2667 #endif
2668                 }
2669                 break;
2670         case OP_LOADI1_MEMBASE:
2671         case OP_LOADU1_MEMBASE:
2672                 /*
2673                  * Note: if reg1 = reg2 the load op is removed
2674                  *
2675                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2676                  * OP_LOAD_MEMBASE offset(basereg), reg2
2677                  * -->
2678                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2679                  * OP_MOVE reg1, reg2
2680                  */
2681                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2682                         ins->inst_basereg == last_ins->inst_destbasereg &&
2683                         ins->inst_offset == last_ins->inst_offset) {
2684                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2685                         ins->sreg1 = last_ins->sreg1;
2686                 }
2687                 break;
2688         case OP_LOADI2_MEMBASE:
2689         case OP_LOADU2_MEMBASE:
2690                 /*
2691                  * Note: if reg1 = reg2 the load op is removed
2692                  *
2693                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2694                  * OP_LOAD_MEMBASE offset(basereg), reg2
2695                  * -->
2696                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2697                  * OP_MOVE reg1, reg2
2698                  */
2699                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2700                         ins->inst_basereg == last_ins->inst_destbasereg &&
2701                         ins->inst_offset == last_ins->inst_offset) {
2702 #if SIZEOF_REGISTER == 8
2703                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2704 #else
2705                         /* The definition of OP_PCONV_TO_U2 is wrong */
2706                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2707 #endif
2708                         ins->sreg1 = last_ins->sreg1;
2709                 }
2710                 break;
2711         case OP_MOVE:
2712         case OP_FMOVE:
2713                 /*
2714                  * Removes:
2715                  *
2716                  * OP_MOVE reg, reg
2717                  */
2718                 if (ins->dreg == ins->sreg1) {
2719                         MONO_DELETE_INS (bb, ins);
2720                         break;
2721                 }
2722                 /*
2723                  * Removes:
2724                  *
2725                  * OP_MOVE sreg, dreg
2726                  * OP_MOVE dreg, sreg
2727                  */
2728                 if (last_ins && last_ins->opcode == ins->opcode &&
2729                         ins->sreg1 == last_ins->dreg &&
2730                         ins->dreg == last_ins->sreg1) {
2731                         MONO_DELETE_INS (bb, ins);
2732                 }
2733                 break;
2734         case OP_NOP:
2735                 MONO_DELETE_INS (bb, ins);
2736                 break;
2737         }
2738 }
2739
2740 int
2741 mini_exception_id_by_name (const char *name)
2742 {
2743         if (strcmp (name, "IndexOutOfRangeException") == 0)
2744                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2745         if (strcmp (name, "OverflowException") == 0)
2746                 return MONO_EXC_OVERFLOW;
2747         if (strcmp (name, "ArithmeticException") == 0)
2748                 return MONO_EXC_ARITHMETIC;
2749         if (strcmp (name, "DivideByZeroException") == 0)
2750                 return MONO_EXC_DIVIDE_BY_ZERO;
2751         if (strcmp (name, "InvalidCastException") == 0)
2752                 return MONO_EXC_INVALID_CAST;
2753         if (strcmp (name, "NullReferenceException") == 0)
2754                 return MONO_EXC_NULL_REF;
2755         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2756                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2757         if (strcmp (name, "ArgumentException") == 0)
2758                 return MONO_EXC_ARGUMENT;
2759         g_error ("Unknown intrinsic exception %s\n", name);
2760         return -1;
2761 }
2762
2763 gboolean
2764 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2765 {
2766         MonoClass *klass;
2767         gpointer iter;
2768         MonoClassField *field;
2769         MonoType *ftype, *prev_ftype = NULL;
2770         int nfields = 0;
2771
2772         klass = mono_class_from_mono_type (t);
2773         iter = NULL;
2774         while ((field = mono_class_get_fields (klass, &iter))) {
2775                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2776                         continue;
2777                 ftype = mono_field_get_type (field);
2778                 ftype = mini_native_type_replace_type (ftype);
2779
2780                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2781                         int nested_nfields, nested_esize;
2782
2783                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2784                                 return FALSE;
2785                         if (nested_esize == 4)
2786                                 ftype = &mono_defaults.single_class->byval_arg;
2787                         else
2788                                 ftype = &mono_defaults.double_class->byval_arg;
2789                         if (prev_ftype && prev_ftype->type != ftype->type)
2790                                 return FALSE;
2791                         prev_ftype = ftype;
2792                         nfields += nested_nfields;
2793                         // FIXME: Nested float structs are aligned to 8 bytes
2794                         if (ftype->type == MONO_TYPE_R4)
2795                                 return FALSE;
2796                 } else {
2797                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2798                                 return FALSE;
2799                         if (prev_ftype && prev_ftype->type != ftype->type)
2800                                 return FALSE;
2801                         prev_ftype = ftype;
2802                         nfields ++;
2803                 }
2804         }
2805         if (nfields == 0 || nfields > 4)
2806                 return FALSE;
2807         *out_nfields = nfields;
2808         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2809         return TRUE;
2810 }
2811
2812 #endif /* DISABLE_JIT */