mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413
 414 static void
 415 print_ji (MonoJumpInfo *ji)
 416 {
 417         switch (ji->type) {
 418         case MONO_PATCH_INFO_RGCTX_FETCH: {
 419                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 420
 421                 printf ("[RGCTX_FETCH ");
 422                 print_ji (entry->data);
 423                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 424                 break;
 425         }
 426         case MONO_PATCH_INFO_METHODCONST: {
 427                 char *s = mono_method_full_name (ji->data.method, TRUE);
 428                 printf ("[METHODCONST - %s]", s);
 429                 g_free (s);
 430                 break;
 431         }
 432         default:
 433                 printf ("[%d]", ji->type);
 434                 break;
 435         }
 436 }
 437
 438 void
 439 mono_print_ins_index (int i, MonoInst *ins)
 440 {
 441         const char *spec = ins_get_spec (ins->opcode);
 442         int num_sregs, j;
 443         int sregs [MONO_MAX_SRC_REGS];
 444
 445         if (i != -1)
 446                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 447         else
 448                 printf (" %s", mono_inst_name (ins->opcode));
 449         if (spec == MONO_ARCH_CPU_SPEC) {
 450                 /* This is a lowered opcode */
 451                 if (ins->dreg != -1)
 452                         printf (" R%d <-", ins->dreg);
 453                 if (ins->sreg1 != -1)
 454                         printf (" R%d", ins->sreg1);
 455                 if (ins->sreg2 != -1)
 456                         printf (" R%d", ins->sreg2);
 457                 if (ins->sreg3 != -1)
 458                         printf (" R%d", ins->sreg3);
 459
 460                 switch (ins->opcode) {
 461                 case OP_LBNE_UN:
 462                 case OP_LBEQ:
 463                 case OP_LBLT:
 464                 case OP_LBLT_UN:
 465                 case OP_LBGT:
 466                 case OP_LBGT_UN:
 467                 case OP_LBGE:
 468                 case OP_LBGE_UN:
 469                 case OP_LBLE:
 470                 case OP_LBLE_UN:
 471                         if (!ins->inst_false_bb)
 472                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 473                         else
 474                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 475                         break;
 476                 case OP_PHI:
 477                 case OP_VPHI:
 478                 case OP_XPHI:
 479                 case OP_FPHI: {
 480                         int i;
 481                         printf (" [%d (", (int)ins->inst_c0);
 482                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 483                                 if (i)
 484                                         printf (", ");
 485                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 486                         }
 487                         printf (")]");
 488                         break;
 489                 }
 490                 case OP_LDADDR:
 491                 case OP_OUTARG_VTRETADDR:
 492                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 493                         break;
 494                 case OP_REGOFFSET:
 495                         printf (" + 0x%lx", (long)ins->inst_offset);
 496                         break;
 497                 default:
 498                         break;
 499                 }
 500
 501                 printf ("\n");
 502                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 503                 return;
 504         }
 505
 506         if (spec [MONO_INST_DEST]) {
 507                 int bank = dreg_bank (spec);
 508                 if (is_soft_reg (ins->dreg, bank)) {
 509                         if (spec [MONO_INST_DEST] == 'b') {
 510                                 if (ins->inst_offset == 0)
 511                                         printf (" [R%d] <-", ins->dreg);
 512                                 else
 513                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 514                         }
 515                         else
 516                                 printf (" R%d <-", ins->dreg);
 517                 } else if (spec [MONO_INST_DEST] == 'b') {
 518                         if (ins->inst_offset == 0)
 519                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 520                         else
 521                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 522                 } else
 523                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 524         }
 525         if (spec [MONO_INST_SRC1]) {
 526                 int bank = sreg1_bank (spec);
 527                 if (is_soft_reg (ins->sreg1, bank)) {
 528                         if (spec [MONO_INST_SRC1] == 'b')
 529                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 530                         else
 531                                 printf (" R%d", ins->sreg1);
 532                 } else if (spec [MONO_INST_SRC1] == 'b')
 533                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 534                 else
 535                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 536         }
 537         num_sregs = mono_inst_get_src_registers (ins, sregs);
 538         for (j = 1; j < num_sregs; ++j) {
 539                 int bank = sreg_bank (j, spec);
 540                 if (is_soft_reg (sregs [j], bank))
 541                         printf (" R%d", sregs [j]);
 542                 else
 543                         printf (" %s", mono_regname_full (sregs [j], bank));
 544         }
 545
 546         switch (ins->opcode) {
 547         case OP_ICONST:
 548                 printf (" [%d]", (int)ins->inst_c0);
 549                 break;
 550 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 551         case OP_X86_PUSH_IMM:
 552 #endif
 553         case OP_ICOMPARE_IMM:
 554         case OP_COMPARE_IMM:
 555         case OP_IADD_IMM:
 556         case OP_ISUB_IMM:
 557         case OP_IAND_IMM:
 558         case OP_IOR_IMM:
 559         case OP_IXOR_IMM:
 560         case OP_SUB_IMM:
 561                 printf (" [%d]", (int)ins->inst_imm);
 562                 break;
 563         case OP_ADD_IMM:
 564         case OP_LADD_IMM:
 565                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 566                 break;
 567         case OP_I8CONST:
 568                 printf (" [%lld]", (long long)ins->inst_l);
 569                 break;
 570         case OP_R8CONST:
 571                 printf (" [%f]", *(double*)ins->inst_p0);
 572                 break;
 573         case OP_R4CONST:
 574                 printf (" [%f]", *(float*)ins->inst_p0);
 575                 break;
 576         case OP_CALL:
 577         case OP_CALL_MEMBASE:
 578         case OP_CALL_REG:
 579         case OP_FCALL:
 580         case OP_FCALLVIRT:
 581         case OP_LCALL:
 582         case OP_LCALLVIRT:
 583         case OP_VCALL:
 584         case OP_VCALLVIRT:
 585         case OP_VCALL_REG:
 586         case OP_VCALL_MEMBASE:
 587         case OP_VCALL2:
 588         case OP_VCALL2_REG:
 589         case OP_VCALL2_MEMBASE:
 590         case OP_VOIDCALL:
 591         case OP_VOIDCALL_MEMBASE:
 592         case OP_VOIDCALLVIRT:
 593         case OP_TAILCALL: {
 594                 MonoCallInst *call = (MonoCallInst*)ins;
 595                 GSList *list;
 596
 597                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 598                         /*
 599                          * These are lowered opcodes, but they are in the .md files since the old
 600                          * JIT passes them to backends.
 601                          */
 602                         if (ins->dreg != -1)
 603                                 printf (" R%d <-", ins->dreg);
 604                 }
 605
 606                 if (call->method) {
 607                         char *full_name = mono_method_full_name (call->method, TRUE);
 608                         printf (" [%s]", full_name);
 609                         g_free (full_name);
 610                 } else if (call->fptr_is_patch) {
 611                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 612
 613                         printf (" ");
 614                         print_ji (ji);
 615                 } else if (call->fptr) {
 616                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 617                         if (info)
 618                                 printf (" [%s]", info->name);
 619                 }
 620
 621                 list = call->out_ireg_args;
 622                 while (list) {
 623                         guint32 regpair;
 624                         int reg, hreg;
 625
 626                         regpair = (guint32)(gssize)(list->data);
 627                         hreg = regpair >> 24;
 628                         reg = regpair & 0xffffff;
 629
 630                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 631
 632                         list = g_slist_next (list);
 633                 }
 634                 break;
 635         }
 636         case OP_BR:
 637         case OP_CALL_HANDLER:
 638                 printf (" [B%d]", ins->inst_target_bb->block_num);
 639                 break;
 640         case OP_IBNE_UN:
 641         case OP_IBEQ:
 642         case OP_IBLT:
 643         case OP_IBLT_UN:
 644         case OP_IBGT:
 645         case OP_IBGT_UN:
 646         case OP_IBGE:
 647         case OP_IBGE_UN:
 648         case OP_IBLE:
 649         case OP_IBLE_UN:
 650         case OP_LBNE_UN:
 651         case OP_LBEQ:
 652         case OP_LBLT:
 653         case OP_LBLT_UN:
 654         case OP_LBGT:
 655         case OP_LBGT_UN:
 656         case OP_LBGE:
 657         case OP_LBGE_UN:
 658         case OP_LBLE:
 659         case OP_LBLE_UN:
 660                 if (!ins->inst_false_bb)
 661                         printf (" [B%d]", ins->inst_true_bb->block_num);
 662                 else
 663                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 664                 break;
 665         case OP_LIVERANGE_START:
 666         case OP_LIVERANGE_END:
 667         case OP_GC_LIVENESS_DEF:
 668         case OP_GC_LIVENESS_USE:
 669                 printf (" R%d", (int)ins->inst_c1);
 670                 break;
 671         case OP_SEQ_POINT:
 672                 printf (" il: %x", (int)ins->inst_imm);
 673                 break;
 674         default:
 675                 break;
 676         }
 677
 678         if (spec [MONO_INST_CLOB])
 679                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 680         printf ("\n");
 681 }
 682
 683 static void
 684 print_regtrack (RegTrack *t, int num)
 685 {
 686         int i;
 687         char buf [32];
 688         const char *r;
 689
 690         for (i = 0; i < num; ++i) {
 691                 if (!t [i].born_in)
 692                         continue;
 693                 if (i >= MONO_MAX_IREGS) {
 694                         g_snprintf (buf, sizeof(buf), "R%d", i);
 695                         r = buf;
 696                 } else
 697                         r = mono_arch_regname (i);
 698                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 699         }
 700 }
 701 #else
 702 void
 703 mono_print_ins_index (int i, MonoInst *ins)
 704 {
 705 }
 706 #endif /* DISABLE_LOGGING */
 707
 708 void
 709 mono_print_ins (MonoInst *ins)
 710 {
 711         mono_print_ins_index (-1, ins);
 712 }
 713
 714 static inline void
 715 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 716 {
 717         /*
 718          * If this function is called multiple times, the new instructions are inserted
 719          * in the proper order.
 720          */
 721         mono_bblock_insert_before_ins (bb, ins, to_insert);
 722 }
 723
 724 static inline void
 725 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 726 {
 727         /*
 728          * If this function is called multiple times, the new instructions are inserted in
 729          * proper order.
 730          */
 731         mono_bblock_insert_after_ins (bb, *last, to_insert);
 732
 733         *last = to_insert;
 734 }
 735
 736 static inline int
 737 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 738 {
 739         if (vreg_is_ref (cfg, reg))
 740                 return MONO_REG_INT_REF;
 741         else if (vreg_is_mp (cfg, reg))
 742                 return MONO_REG_INT_MP;
 743         else
 744                 return bank;
 745 }
 746
 747 /*
 748  * Force the spilling of the variable in the symbolic register 'reg', and free
 749  * the hreg it was assigned to.
 750  */
 751 static void
 752 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 753 {
 754         MonoInst *load;
 755         int i, sel, spill;
 756         int *symbolic;
 757         MonoRegState *rs = cfg->rs;
 758
 759         symbolic = rs->symbolic [bank];
 760         sel = rs->vassign [reg];
 761
 762         /* the vreg we need to spill lives in another logical reg bank */
 763         bank = translate_bank (cfg->rs, bank, sel);
 764
 765         /*i = rs->isymbolic [sel];
 766         g_assert (i == reg);*/
 767         i = reg;
 768         spill = ++cfg->spill_count;
 769         rs->vassign [i] = -spill - 1;
 770         if (G_UNLIKELY (bank))
 771                 mono_regstate_free_general (rs, sel, bank);
 772         else
 773                 mono_regstate_free_int (rs, sel);
 774         /* we need to create a spill var and insert a load to sel after the current instruction */
 775         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 776         load->dreg = sel;
 777         load->inst_basereg = cfg->frame_reg;
 778         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 779         insert_after_ins (bb, ins, last, load);
 780         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 781         if (G_UNLIKELY (bank))
 782                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 783         else
 784                 i = mono_regstate_alloc_int (rs, regmask (sel));
 785         g_assert (i == sel);
 786
 787         if (G_UNLIKELY (bank))
 788                 mono_regstate_free_general (rs, sel, bank);
 789         else
 790                 mono_regstate_free_int (rs, sel);
 791 }
 792
 793 /* This isn't defined on older glib versions and on some platforms */
 794 #ifndef G_GUINT64_FORMAT
 795 #define G_GUINT64_FORMAT "ul"
 796 #endif
 797
 798 static int
 799 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 800 {
 801         MonoInst *load;
 802         int i, sel, spill, num_sregs;
 803         int sregs [MONO_MAX_SRC_REGS];
 804         int *symbolic;
 805         MonoRegState *rs = cfg->rs;
 806
 807         symbolic = rs->symbolic [bank];
 808
 809         g_assert (bank < MONO_NUM_REGBANKS);
 810
 811         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 812         /* exclude the registers in the current instruction */
 813         num_sregs = mono_inst_get_src_registers (ins, sregs);
 814         for (i = 0; i < num_sregs; ++i) {
 815                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 816                         if (is_soft_reg (sregs [i], bank))
 817                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 818                         else
 819                                 regmask &= ~ (regmask (sregs [i]));
 820                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 821                 }
 822         }
 823         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 824                 regmask &= ~ (regmask (ins->dreg));
 825                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 826         }
 827
 828         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 829         g_assert (regmask); /* need at least a register we can free */
 830         sel = 0;
 831         /* we should track prev_use and spill the register that's farther */
 832         if (G_UNLIKELY (bank)) {
 833                 for (i = 0; i < regbank_size [bank]; ++i) {
 834                         if (regmask & (regmask (i))) {
 835                                 sel = i;
 836
 837                                 /* the vreg we need to load lives in another logical bank */
 838                                 bank = translate_bank (cfg->rs, bank, sel);
 839
 840                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 841                                 break;
 842                         }
 843                 }
 844
 845                 i = rs->symbolic [bank] [sel];
 846                 spill = ++cfg->spill_count;
 847                 rs->vassign [i] = -spill - 1;
 848                 mono_regstate_free_general (rs, sel, bank);
 849         }
 850         else {
 851                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 852                         if (regmask & (regmask (i))) {
 853                                 sel = i;
 854                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 855                                 break;
 856                         }
 857                 }
 858
 859                 i = rs->isymbolic [sel];
 860                 spill = ++cfg->spill_count;
 861                 rs->vassign [i] = -spill - 1;
 862                 mono_regstate_free_int (rs, sel);
 863         }
 864
 865         /* we need to create a spill var and insert a load to sel after the current instruction */
 866         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 867         load->dreg = sel;
 868         load->inst_basereg = cfg->frame_reg;
 869         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 870         insert_after_ins (bb, ins, last, load);
 871         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 872         if (G_UNLIKELY (bank))
 873                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 874         else
 875                 i = mono_regstate_alloc_int (rs, regmask (sel));
 876         g_assert (i == sel);
 877
 878         return sel;
 879 }
 880
 881 /*
 882  * free_up_hreg:
 883  *
 884  *   Free up the hreg HREG by spilling the vreg allocated to it.
 885  */
 886 static void
 887 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 888 {
 889         if (G_UNLIKELY (bank)) {
 890                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 891                         bank = translate_bank (cfg->rs, bank, hreg);
 892                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 893                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 894                 }
 895         }
 896         else {
 897                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 898                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 899                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 900                 }
 901         }
 902 }
 903
 904 static MonoInst*
 905 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 906 {
 907         MonoInst *copy;
 908
 909         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 910
 911         copy->dreg = dest;
 912         copy->sreg1 = src;
 913         copy->cil_code = ip;
 914         if (ins) {
 915                 mono_bblock_insert_after_ins (bb, ins, copy);
 916                 *last = copy;
 917         }
 918         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 919         return copy;
 920 }
 921
 922 static inline const char*
 923 regbank_to_string (int bank)
 924 {
 925         if (bank == MONO_REG_INT_REF)
 926                 return "REF ";
 927         else if (bank == MONO_REG_INT_MP)
 928                 return "MP ";
 929         else
 930                 return "";
 931 }
 932
 933 static void
 934 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 935 {
 936         MonoInst *store, *def;
 937
 938         bank = get_vreg_bank (cfg, prev_reg, bank);
 939
 940         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 941         store->sreg1 = reg;
 942         store->inst_destbasereg = cfg->frame_reg;
 943         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 944         if (ins) {
 945                 mono_bblock_insert_after_ins (bb, ins, store);
 946                 *last = store;
 947         } else if (insert_before) {
 948                 insert_before_ins (bb, insert_before, store);
 949         } else {
 950                 g_assert_not_reached ();
 951         }
 952         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 953
 954         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 955                 g_assert (prev_reg != -1);
 956                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 957                 def->inst_c0 = spill;
 958                 def->inst_c1 = bank;
 959                 mono_bblock_insert_after_ins (bb, store, def);
 960         }
 961 }
 962
 963 /* flags used in reginfo->flags */
 964 enum {
 965         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 966         MONO_FP_NEEDS_SPILL                     = regmask (1),
 967         MONO_FP_NEEDS_LOAD                      = regmask (2)
 968 };
 969
 970 static inline int
 971 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 972 {
 973         int val;
 974
 975         if (info && info->preferred_mask) {
 976                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 977                 if (val >= 0) {
 978                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 979                         return val;
 980                 }
 981         }
 982
 983         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 984         if (val < 0)
 985                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 986
 987         return val;
 988 }
 989
 990 static inline int
 991 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 992 {
 993         int val;
 994
 995         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 996
 997         if (val < 0)
 998                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 999
1000         return val;
1001 }
1002
1003 static inline int
1004 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1005 {
1006         if (G_UNLIKELY (bank))
1007                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1008         else
1009                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1010 }
1011
1012 static inline void
1013 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1014 {
1015         if (G_UNLIKELY (bank)) {
1016                 int mirrored_bank;
1017
1018                 g_assert (reg >= regbank_size [bank]);
1019                 g_assert (hreg < regbank_size [bank]);
1020                 g_assert (! is_global_freg (hreg));
1021
1022                 rs->vassign [reg] = hreg;
1023                 rs->symbolic [bank] [hreg] = reg;
1024                 rs->free_mask [bank] &= ~ (regmask (hreg));
1025
1026                 mirrored_bank = get_mirrored_bank (bank);
1027                 if (mirrored_bank == -1)
1028                         return;
1029
1030                 /* Make sure the other logical reg bank that this bank shares
1031                  * a single hard reg bank knows that this hard reg is not free.
1032                  */
1033                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1034
1035                 /* Mark the other logical bank that the this bank shares
1036                  * a single hard reg bank with as mirrored.
1037                  */
1038                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1039
1040         }
1041         else {
1042                 g_assert (reg >= MONO_MAX_IREGS);
1043                 g_assert (hreg < MONO_MAX_IREGS);
1044 #ifndef TARGET_ARM
1045                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1046                 g_assert (! is_global_ireg (hreg));
1047 #endif
1048
1049                 rs->vassign [reg] = hreg;
1050                 rs->isymbolic [hreg] = reg;
1051                 rs->ifree_mask &= ~ (regmask (hreg));
1052         }
1053 }
1054
1055 static inline regmask_t
1056 get_callee_mask (const char spec)
1057 {
1058         if (G_UNLIKELY (reg_bank (spec)))
1059                 return regbank_callee_regs [reg_bank (spec)];
1060         return MONO_ARCH_CALLEE_REGS;
1061 }
1062
1063 static gint8 desc_to_fixed_reg [256];
1064 static gboolean desc_to_fixed_reg_inited = FALSE;
1065
1066 #ifndef DISABLE_JIT
1067
1068 /*
1069  * Local register allocation.
1070  * We first scan the list of instructions and we save the liveness info of
1071  * each register (when the register is first used, when it's value is set etc.).
1072  * We also reverse the list of instructions because assigning registers backwards allows
1073  * for more tricks to be used.
1074  */
1075 void
1076 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1077 {
1078         MonoInst *ins, *prev, *last;
1079         MonoInst **tmp;
1080         MonoRegState *rs = cfg->rs;
1081         int i, j, val, max;
1082         RegTrack *reginfo;
1083         const char *spec;
1084         unsigned char spec_src1, spec_dest;
1085         int bank = 0;
1086 #if MONO_ARCH_USE_FPSTACK
1087         gboolean has_fp = FALSE;
1088         int fpstack [8];
1089         int sp = 0;
1090 #endif
1091         int num_sregs = 0;
1092         int sregs [MONO_MAX_SRC_REGS];
1093
1094         if (!bb->code)
1095                 return;
1096
1097         if (!desc_to_fixed_reg_inited) {
1098                 for (i = 0; i < 256; ++i)
1099                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1100                 desc_to_fixed_reg_inited = TRUE;
1101
1102                 /* Validate the cpu description against the info in mini-ops.h */
1103 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1104                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1105                         const char *ispec;
1106
1107                         spec = ins_get_spec (i);
1108                         ispec = INS_INFO (i);
1109
1110                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1111                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1112                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1113                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1114                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1115                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1116                 }
1117 #endif
1118         }
1119
1120         rs->next_vreg = bb->max_vreg;
1121         mono_regstate_assign (rs);
1122
1123         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1124         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1125                 rs->free_mask [i] = regbank_callee_regs [i];
1126
1127         max = rs->next_vreg;
1128
1129         if (cfg->reginfo && cfg->reginfo_len < max)
1130                 cfg->reginfo = NULL;
1131
1132         reginfo = cfg->reginfo;
1133         if (!reginfo) {
1134                 cfg->reginfo_len = MAX (1024, max * 2);
1135                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1136         }
1137         else
1138                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1139
1140         if (cfg->verbose_level > 1) {
1141                 /* print_regtrack reads the info of all variables */
1142                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1143         }
1144
1145         /*
1146          * For large methods, next_vreg can be very large, so g_malloc0 time can
1147          * be prohibitive. So we manually init the reginfo entries used by the
1148          * bblock.
1149          */
1150         for (ins = bb->code; ins; ins = ins->next) {
1151                 spec = ins_get_spec (ins->opcode);
1152
1153                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1154                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1155 #if SIZEOF_REGISTER == 4
1156                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1157                                 /**
1158                                  * In the new IR, the two vregs of the regpair do not alias the
1159                                  * original long vreg. shift the vreg here so the rest of the
1160                                  * allocator doesn't have to care about it.
1161                                  */
1162                                 ins->dreg ++;
1163                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1164                         }
1165 #endif
1166                 }
1167
1168                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1169                 for (j = 0; j < num_sregs; ++j) {
1170                         g_assert (sregs [j] != -1);
1171                         if (sregs [j] < max) {
1172                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1173 #if SIZEOF_REGISTER == 4
1174                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1175                                         sregs [j]++;
1176                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1177                                 }
1178 #endif
1179                         }
1180                 }
1181                 mono_inst_set_src_registers (ins, sregs);
1182         }
1183
1184         /*if (cfg->opt & MONO_OPT_COPYPROP)
1185                 local_copy_prop (cfg, ins);*/
1186
1187         i = 1;
1188         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1189         /* forward pass on the instructions to collect register liveness info */
1190         MONO_BB_FOR_EACH_INS (bb, ins) {
1191                 spec = ins_get_spec (ins->opcode);
1192                 spec_dest = spec [MONO_INST_DEST];
1193
1194                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1195                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1196                 }
1197
1198                 DEBUG (mono_print_ins_index (i, ins));
1199
1200                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1201
1202 #if MONO_ARCH_USE_FPSTACK
1203                 if (dreg_is_fp (spec)) {
1204                         has_fp = TRUE;
1205                 } else {
1206                         for (j = 0; j < num_sregs; ++j) {
1207                                 if (sreg_is_fp (j, spec))
1208                                         has_fp = TRUE;
1209                         }
1210                 }
1211 #endif
1212
1213                 for (j = 0; j < num_sregs; ++j) {
1214                         int sreg = sregs [j];
1215                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1216                         if (sreg_spec) {
1217                                 bank = sreg_bank (j, spec);
1218                                 g_assert (sreg != -1);
1219                                 if (is_soft_reg (sreg, bank))
1220                                         /* This means the vreg is not local to this bb */
1221                                         g_assert (reginfo [sreg].born_in > 0);
1222                                 rs->vassign [sreg] = -1;
1223                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1224                                 //reginfo [ins->sreg2].last_use = i;
1225                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1226                                         /* The virtual register is allocated sequentially */
1227                                         rs->vassign [sreg + 1] = -1;
1228                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1229                                         //reginfo [ins->sreg2 + 1].last_use = i;
1230                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1231                                                 reginfo [sreg + 1].born_in = i;
1232                                 }
1233                         } else {
1234                                 sregs [j] = -1;
1235                         }
1236                 }
1237                 mono_inst_set_src_registers (ins, sregs);
1238
1239                 if (spec_dest) {
1240                         int dest_dreg;
1241
1242                         bank = dreg_bank (spec);
1243                         if (spec_dest != 'b') /* it's not just a base register */
1244                                 reginfo [ins->dreg].killed_in = i;
1245                         g_assert (ins->dreg != -1);
1246                         rs->vassign [ins->dreg] = -1;
1247                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1248                         //reginfo [ins->dreg].last_use = i;
1249                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1250                                 reginfo [ins->dreg].born_in = i;
1251
1252                         dest_dreg = desc_to_fixed_reg [spec_dest];
1253                         if (dest_dreg != -1)
1254                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1255
1256 #ifdef MONO_ARCH_INST_FIXED_MASK
1257                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1258 #endif
1259
1260                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1261                                 /* The virtual register is allocated sequentially */
1262                                 rs->vassign [ins->dreg + 1] = -1;
1263                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1264                                 //reginfo [ins->dreg + 1].last_use = i;
1265                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1266                                         reginfo [ins->dreg + 1].born_in = i;
1267                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1268                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1269                         }
1270                 } else {
1271                         ins->dreg = -1;
1272                 }
1273
1274                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1275                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1276
1277                         MonoCallInst *call = (MonoCallInst*)ins;
1278                         GSList *list;
1279
1280                         list = call->out_ireg_args;
1281                         if (list) {
1282                                 while (list) {
1283                                         guint32 regpair;
1284                                         int reg, hreg;
1285
1286                                         regpair = (guint32)(gssize)(list->data);
1287                                         hreg = regpair >> 24;
1288                                         reg = regpair & 0xffffff;
1289
1290                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1291                                         //reginfo [reg].last_use = i;
1292
1293                                         list = g_slist_next (list);
1294                                 }
1295                         }
1296
1297                         list = call->out_freg_args;
1298                         if (list) {
1299                                 while (list) {
1300                                         guint32 regpair;
1301                                         int reg, hreg;
1302
1303                                         regpair = (guint32)(gssize)(list->data);
1304                                         hreg = regpair >> 24;
1305                                         reg = regpair & 0xffffff;
1306
1307                                         list = g_slist_next (list);
1308                                 }
1309                         }
1310                 }
1311
1312                 ++i;
1313         }
1314
1315         tmp = &last;
1316
1317         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1318         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1319                 int prev_dreg, clob_dreg;
1320                 int dest_dreg, clob_reg;
1321                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1322                 int dreg_high, sreg1_high;
1323                 regmask_t dreg_mask, mask;
1324                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1325                 regmask_t dreg_fixed_mask;
1326                 const unsigned char *ip;
1327                 --i;
1328                 spec = ins_get_spec (ins->opcode);
1329                 spec_src1 = spec [MONO_INST_SRC1];
1330                 spec_dest = spec [MONO_INST_DEST];
1331                 prev_dreg = -1;
1332                 clob_dreg = -1;
1333                 clob_reg = -1;
1334                 dest_dreg = -1;
1335                 dreg_high = -1;
1336                 sreg1_high = -1;
1337                 dreg_mask = get_callee_mask (spec_dest);
1338                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1339                         prev_sregs [j] = -1;
1340                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1341                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1342 #ifdef MONO_ARCH_INST_FIXED_MASK
1343                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1344 #else
1345                         sreg_fixed_masks [j] = 0;
1346 #endif
1347                 }
1348
1349                 DEBUG (printf ("processing:"));
1350                 DEBUG (mono_print_ins_index (i, ins));
1351
1352                 ip = ins->cil_code;
1353
1354                 last = ins;
1355
1356                 /*
1357                  * FIXED REGS
1358                  */
1359                 dest_dreg = desc_to_fixed_reg [spec_dest];
1360                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1361                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1362
1363 #ifdef MONO_ARCH_INST_FIXED_MASK
1364                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1365 #else
1366                 dreg_fixed_mask = 0;
1367 #endif
1368
1369                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1370
1371                 /*
1372                  * TRACK FIXED SREG2, 3, ...
1373                  */
1374                 for (j = 1; j < num_sregs; ++j) {
1375                         int sreg = sregs [j];
1376                         int dest_sreg = dest_sregs [j];
1377
1378                         if (dest_sreg == -1)
1379                                 continue;
1380
1381                         if (j == 2) {
1382                                 int k;
1383
1384                                 /*
1385                                  * CAS.
1386                                  * We need to special case this, since on x86, there are only 3
1387                                  * free registers, and the code below assigns one of them to
1388                                  * sreg, so we can run out of registers when trying to assign
1389                                  * dreg. Instead, we just set up the register masks, and let the
1390                                  * normal sreg2 assignment code handle this. It would be nice to
1391                                  * do this for all the fixed reg cases too, but there is too much
1392                                  * risk of breakage.
1393                                  */
1394
1395                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1396                                 sreg_masks [j] = regmask (dest_sreg);
1397                                 for (k = 0; k < num_sregs; ++k) {
1398                                         if (k != j)
1399                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1400                                 }
1401
1402                                 /*
1403                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1404                                  */
1405                                 for (k = 0; k < num_sregs; ++k) {
1406                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1407                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1408                                 }
1409
1410                                 /*
1411                                  * We can also run out of registers while processing sreg2 if sreg3 is
1412                                  * assigned to another hreg, so spill sreg3 now.
1413                                  */
1414                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1415                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1416                                 }
1417                                 continue;
1418                         }
1419
1420                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1421                                 if (is_global_ireg (sreg)) {
1422                                         int k;
1423                                         /* Argument already in hard reg, need to copy */
1424                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1425                                         insert_before_ins (bb, ins, copy);
1426                                         for (k = 0; k < num_sregs; ++k) {
1427                                                 if (k != j)
1428                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1429                                         }
1430                                 } else {
1431                                         val = rs->vassign [sreg];
1432                                         if (val == -1) {
1433                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1434                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1435                                         } else if (val < -1) {
1436                                                 /* FIXME: */
1437                                                 g_assert_not_reached ();
1438                                         } else {
1439                                                 /* Argument already in hard reg, need to copy */
1440                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1441                                                 int k;
1442
1443                                                 insert_before_ins (bb, ins, copy);
1444                                                 for (k = 0; k < num_sregs; ++k) {
1445                                                         if (k != j)
1446                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1447                                                 }
1448                                                 /*
1449                                                  * Prevent the dreg from being allocate to dest_sreg
1450                                                  * too, since it could force sreg1 to be allocated to
1451                                                  * the same reg on x86.
1452                                                  */
1453                                                 dreg_mask &= ~ (regmask (dest_sreg));
1454                                         }
1455                                 }
1456                         } else {
1457                                 gboolean need_spill = TRUE;
1458                                 gboolean need_assign = TRUE;
1459                                 int k;
1460
1461                                 dreg_mask &= ~ (regmask (dest_sreg));
1462                                 for (k = 0; k < num_sregs; ++k) {
1463                                         if (k != j)
1464                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1465                                 }
1466
1467                                 /*
1468                                  * First check if dreg is assigned to dest_sreg2, since we
1469                                  * can't spill a dreg.
1470                                  */
1471                                 if (spec [MONO_INST_DEST])
1472                                         val = rs->vassign [ins->dreg];
1473                                 else
1474                                         val = -1;
1475                                 if (val == dest_sreg && ins->dreg != sreg) {
1476                                         /*
1477                                          * the destination register is already assigned to
1478                                          * dest_sreg2: we need to allocate another register for it
1479                                          * and then copy from this to dest_sreg2.
1480                                          */
1481                                         int new_dest;
1482                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1483                                         g_assert (new_dest >= 0);
1484                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1485
1486                                         prev_dreg = ins->dreg;
1487                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1488                                         clob_dreg = ins->dreg;
1489                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1490                                         mono_regstate_free_int (rs, dest_sreg);
1491                                         need_spill = FALSE;
1492                                 }
1493
1494                                 if (is_global_ireg (sreg)) {
1495                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1496                                         insert_before_ins (bb, ins, copy);
1497                                         need_assign = FALSE;
1498                                 }
1499                                 else {
1500                                         val = rs->vassign [sreg];
1501                                         if (val == dest_sreg) {
1502                                                 /* sreg2 is already assigned to the correct register */
1503                                                 need_spill = FALSE;
1504                                         } else if (val < -1) {
1505                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1506                                         } else if (val >= 0) {
1507                                                 /* sreg2 already assigned to another register */
1508                                                 /*
1509                                                  * We couldn't emit a copy from val to dest_sreg2, because
1510                                                  * val might be spilled later while processing this
1511                                                  * instruction. So we spill sreg2 so it can be allocated to
1512                                                  * dest_sreg2.
1513                                                  */
1514                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1515                                         }
1516                                 }
1517
1518                                 if (need_spill) {
1519                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1520                                 }
1521
1522                                 if (need_assign) {
1523                                         if (rs->vassign [sreg] < -1) {
1524                                                 int spill;
1525
1526                                                 /* Need to emit a spill store */
1527                                                 spill = - rs->vassign [sreg] - 1;
1528                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1529                                         }
1530                                         /* force-set sreg2 */
1531                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1532                                 }
1533                         }
1534                         sregs [j] = dest_sreg;
1535                 }
1536                 mono_inst_set_src_registers (ins, sregs);
1537
1538                 /*
1539                  * TRACK DREG
1540                  */
1541                 bank = dreg_bank (spec);
1542                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1543                         prev_dreg = ins->dreg;
1544                 }
1545
1546                 if (spec_dest == 'b') {
1547                         /*
1548                          * The dest reg is read by the instruction, not written, so
1549                          * avoid allocating sreg1/sreg2 to the same reg.
1550                          */
1551                         if (dest_sregs [0] != -1)
1552                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1553                         for (j = 1; j < num_sregs; ++j) {
1554                                 if (dest_sregs [j] != -1)
1555                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1556                         }
1557
1558                         val = rs->vassign [ins->dreg];
1559                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1560                                 /* DREG is already allocated to a register needed for sreg1 */
1561                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1562                         }
1563                 }
1564
1565                 /*
1566                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1567                  * various complex situations.
1568                  */
1569                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1570                         guint32 dreg2, dest_dreg2;
1571
1572                         g_assert (is_soft_reg (ins->dreg, bank));
1573
1574                         if (dest_dreg != -1) {
1575                                 if (rs->vassign [ins->dreg] != dest_dreg)
1576                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1577
1578                                 dreg2 = ins->dreg + 1;
1579                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1580                                 if (dest_dreg2 != -1) {
1581                                         if (rs->vassign [dreg2] != dest_dreg2)
1582                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1583                                 }
1584                         }
1585                 }
1586
1587                 if (dreg_fixed_mask) {
1588                         g_assert (!bank);
1589                         if (is_global_ireg (ins->dreg)) {
1590                                 /*
1591                                  * The argument is already in a hard reg, but that reg is
1592                                  * not usable by this instruction, so allocate a new one.
1593                                  */
1594                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1595                                 if (val < 0)
1596                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1597                                 mono_regstate_free_int (rs, val);
1598                                 dest_dreg = val;
1599
1600                                 /* Fall through */
1601                         }
1602                         else
1603                                 dreg_mask &= dreg_fixed_mask;
1604                 }
1605
1606                 if (is_soft_reg (ins->dreg, bank)) {
1607                         val = rs->vassign [ins->dreg];
1608
1609                         if (val < 0) {
1610                                 int spill = 0;
1611                                 if (val < -1) {
1612                                         /* the register gets spilled after this inst */
1613                                         spill = -val -1;
1614                                 }
1615                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1616                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1617                                 if (spill)
1618                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1619                         }
1620
1621                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1622                         ins->dreg = val;
1623                 }
1624
1625                 /* Handle regpairs */
1626                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1627                         int reg2 = prev_dreg + 1;
1628
1629                         g_assert (!bank);
1630                         g_assert (prev_dreg > -1);
1631                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1632                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1633 #ifdef TARGET_X86
1634                         /* bug #80489 */
1635                         mask &= ~regmask (X86_ECX);
1636 #endif
1637                         val = rs->vassign [reg2];
1638                         if (val < 0) {
1639                                 int spill = 0;
1640                                 if (val < -1) {
1641                                         /* the register gets spilled after this inst */
1642                                         spill = -val -1;
1643                                 }
1644                                 val = mono_regstate_alloc_int (rs, mask);
1645                                 if (val < 0)
1646                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1647                                 if (spill)
1648                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1649                         }
1650                         else {
1651                                 if (! (mask & (regmask (val)))) {
1652                                         val = mono_regstate_alloc_int (rs, mask);
1653                                         if (val < 0)
1654                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1655
1656                                         /* Reallocate hreg to the correct register */
1657                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1658
1659                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1660                                 }
1661                         }
1662
1663                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1664                         assign_reg (cfg, rs, reg2, val, bank);
1665
1666                         dreg_high = val;
1667                         ins->backend.reg3 = val;
1668
1669                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1670                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1671                                 mono_regstate_free_int (rs, val);
1672                         }
1673                 }
1674
1675                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1676                         /*
1677                          * In theory, we could free up the hreg even if the vreg is alive,
1678                          * but branches inside bblocks force us to assign the same hreg
1679                          * to a vreg every time it is encountered.
1680                          */
1681                         int dreg = rs->vassign [prev_dreg];
1682                         g_assert (dreg >= 0);
1683                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1684                         if (G_UNLIKELY (bank))
1685                                 mono_regstate_free_general (rs, dreg, bank);
1686                         else
1687                                 mono_regstate_free_int (rs, dreg);
1688                         rs->vassign [prev_dreg] = -1;
1689                 }
1690
1691                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1692                         /* this instruction only outputs to dest_dreg, need to copy */
1693                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1694                         ins->dreg = dest_dreg;
1695
1696                         if (G_UNLIKELY (bank)) {
1697                                 /* the register we need to free up may be used in another logical regbank
1698                                  * so do a translate just in case.
1699                                  */
1700                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1701                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1702                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1703                         }
1704                         else {
1705                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1706                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1707                         }
1708                 }
1709
1710                 if (spec_dest == 'b') {
1711                         /*
1712                          * The dest reg is read by the instruction, not written, so
1713                          * avoid allocating sreg1/sreg2 to the same reg.
1714                          */
1715                         for (j = 0; j < num_sregs; ++j)
1716                                 if (!sreg_bank (j, spec))
1717                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1718                 }
1719
1720                 /*
1721                  * TRACK CLOBBERING
1722                  */
1723                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1724                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1725                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1726                 }
1727
1728                 if (spec [MONO_INST_CLOB] == 'c') {
1729                         int j, s, dreg, dreg2, cur_bank;
1730                         guint64 clob_mask;
1731
1732                         clob_mask = MONO_ARCH_CALLEE_REGS;
1733
1734                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1735                                 /*
1736                                  * Need to avoid spilling the dreg since the dreg is not really
1737                                  * clobbered by the call.
1738                                  */
1739                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1740                                         dreg = rs->vassign [prev_dreg];
1741                                 else
1742                                         dreg = -1;
1743
1744                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1745                                         dreg2 = rs->vassign [prev_dreg + 1];
1746                                 else
1747                                         dreg2 = -1;
1748
1749                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1750                                         s = regmask (j);
1751                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1752                                                 if ((j != dreg) && (j != dreg2))
1753                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1754                                                 else if (rs->isymbolic [j])
1755                                                         /* The hreg is assigned to the dreg of this instruction */
1756                                                         rs->vassign [rs->isymbolic [j]] = -1;
1757                                                 mono_regstate_free_int (rs, j);
1758                                         }
1759                                 }
1760                         }
1761
1762                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1763                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1764                                         clob_mask = regbank_callee_regs [cur_bank];
1765                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1766                                                 dreg = rs->vassign [prev_dreg];
1767                                         else
1768                                                 dreg = -1;
1769
1770                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1771
1772                                                 /* we are looping though the banks in the outer loop
1773                                                  * so, we don't need to deal with mirrored hregs
1774                                                  * because we will get them in one of the other bank passes.
1775                                                  */
1776                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1777                                                         continue;
1778
1779                                                 s = regmask (j);
1780                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1781                                                         if (j != dreg)
1782                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1783                                                         else if (rs->symbolic [cur_bank] [j])
1784                                                                 /* The hreg is assigned to the dreg of this instruction */
1785                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1786                                                         mono_regstate_free_general (rs, j, cur_bank);
1787                                                 }
1788                                         }
1789                                 }
1790                         }
1791                 }
1792
1793                 /*
1794                  * TRACK ARGUMENT REGS
1795                  */
1796                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1797                         MonoCallInst *call = (MonoCallInst*)ins;
1798                         GSList *list;
1799
1800                         /*
1801                          * This needs to be done before assigning sreg1, so sreg1 will
1802                          * not be assigned one of the argument regs.
1803                          */
1804
1805                         /*
1806                          * Assign all registers in call->out_reg_args to the proper
1807                          * argument registers.
1808                          */
1809
1810                         list = call->out_ireg_args;
1811                         if (list) {
1812                                 while (list) {
1813                                         guint32 regpair;
1814                                         int reg, hreg;
1815
1816                                         regpair = (guint32)(gssize)(list->data);
1817                                         hreg = regpair >> 24;
1818                                         reg = regpair & 0xffffff;
1819
1820                                         assign_reg (cfg, rs, reg, hreg, 0);
1821
1822                                         sreg_masks [0] &= ~(regmask (hreg));
1823
1824                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1825
1826                                         list = g_slist_next (list);
1827                                 }
1828                         }
1829
1830                         list = call->out_freg_args;
1831                         if (list) {
1832                                 while (list) {
1833                                         guint32 regpair;
1834                                         int reg, hreg;
1835
1836                                         regpair = (guint32)(gssize)(list->data);
1837                                         hreg = regpair >> 24;
1838                                         reg = regpair & 0xffffff;
1839
1840                                         assign_reg (cfg, rs, reg, hreg, 1);
1841
1842                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1843
1844                                         list = g_slist_next (list);
1845                                 }
1846                         }
1847                 }
1848
1849                 /*
1850                  * TRACK SREG1
1851                  */
1852                 bank = sreg1_bank (spec);
1853                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1854                         int sreg1 = sregs [0];
1855                         int dest_sreg1 = dest_sregs [0];
1856
1857                         g_assert (is_soft_reg (sreg1, bank));
1858
1859                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1860                         if (dest_sreg1 != -1)
1861                                 g_assert (dest_sreg1 == ins->dreg);
1862                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1863                         g_assert (val >= 0);
1864
1865                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1866                                 // FIXME:
1867                                 g_assert_not_reached ();
1868
1869                         assign_reg (cfg, rs, sreg1, val, bank);
1870
1871                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1872
1873                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1874                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1875                         g_assert (val >= 0);
1876
1877                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1878                                 // FIXME:
1879                                 g_assert_not_reached ();
1880
1881                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1882
1883                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1884
1885                         /* Skip rest of this section */
1886                         dest_sregs [0] = -1;
1887                 }
1888
1889                 if (sreg_fixed_masks [0]) {
1890                         g_assert (!bank);
1891                         if (is_global_ireg (sregs [0])) {
1892                                 /*
1893                                  * The argument is already in a hard reg, but that reg is
1894                                  * not usable by this instruction, so allocate a new one.
1895                                  */
1896                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1897                                 if (val < 0)
1898                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1899                                 mono_regstate_free_int (rs, val);
1900                                 dest_sregs [0] = val;
1901
1902                                 /* Fall through to the dest_sreg1 != -1 case */
1903                         }
1904                         else
1905                                 sreg_masks [0] &= sreg_fixed_masks [0];
1906                 }
1907
1908                 if (dest_sregs [0] != -1) {
1909                         sreg_masks [0] = regmask (dest_sregs [0]);
1910
1911                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1912                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1913                         }
1914                         if (is_global_ireg (sregs [0])) {
1915                                 /* The argument is already in a hard reg, need to copy */
1916                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1917                                 insert_before_ins (bb, ins, copy);
1918                                 sregs [0] = dest_sregs [0];
1919                         }
1920                 }
1921
1922                 if (is_soft_reg (sregs [0], bank)) {
1923                         val = rs->vassign [sregs [0]];
1924                         prev_sregs [0] = sregs [0];
1925                         if (val < 0) {
1926                                 int spill = 0;
1927                                 if (val < -1) {
1928                                         /* the register gets spilled after this inst */
1929                                         spill = -val -1;
1930                                 }
1931
1932                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1933                                         /*
1934                                          * Allocate the same hreg to sreg1 as well so the
1935                                          * peephole can get rid of the move.
1936                                          */
1937                                         sreg_masks [0] = regmask (ins->dreg);
1938                                 }
1939
1940                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1941                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1942                                         sreg_masks [0] = regmask (ins->dreg);
1943
1944                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1945                                 assign_reg (cfg, rs, sregs [0], val, bank);
1946                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1947
1948                                 if (spill) {
1949                                         /*
1950                                          * Need to insert before the instruction since it can
1951                                          * overwrite sreg1.
1952                                          */
1953                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1954                                 }
1955                         }
1956                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1957                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1958                                 insert_before_ins (bb, ins, copy);
1959                                 for (j = 1; j < num_sregs; ++j)
1960                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1961                                 val = dest_sregs [0];
1962                         }
1963
1964                         sregs [0] = val;
1965                 }
1966                 else {
1967                         prev_sregs [0] = -1;
1968                 }
1969                 mono_inst_set_src_registers (ins, sregs);
1970
1971                 for (j = 1; j < num_sregs; ++j)
1972                         sreg_masks [j] &= ~(regmask (sregs [0]));
1973
1974                 /* Handle the case when sreg1 is a regpair but dreg is not */
1975                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1976                         int reg2 = prev_sregs [0] + 1;
1977
1978                         g_assert (!bank);
1979                         g_assert (prev_sregs [0] > -1);
1980                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1981                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1982                         val = rs->vassign [reg2];
1983                         if (val < 0) {
1984                                 int spill = 0;
1985                                 if (val < -1) {
1986                                         /* the register gets spilled after this inst */
1987                                         spill = -val -1;
1988                                 }
1989                                 val = mono_regstate_alloc_int (rs, mask);
1990                                 if (val < 0)
1991                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1992                                 if (spill)
1993                                         g_assert_not_reached ();
1994                         }
1995                         else {
1996                                 if (! (mask & (regmask (val)))) {
1997                                         /* The vreg is already allocated to a wrong hreg */
1998                                         /* FIXME: */
1999                                         g_assert_not_reached ();
2000 #if 0
2001                                         val = mono_regstate_alloc_int (rs, mask);
2002                                         if (val < 0)
2003                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2004
2005                                         /* Reallocate hreg to the correct register */
2006                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2007
2008                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2009 #endif
2010                                 }
2011                         }
2012
2013                         sreg1_high = val;
2014                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2015                         assign_reg (cfg, rs, reg2, val, bank);
2016                 }
2017
2018                 /* Handle dreg==sreg1 */
2019                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2020                         MonoInst *sreg2_copy = NULL;
2021                         MonoInst *copy;
2022                         int bank = reg_bank (spec_src1);
2023
2024                         if (ins->dreg == sregs [1]) {
2025                                 /*
2026                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2027                                  * register for it.
2028                                  */
2029                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2030
2031                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2032                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2033                                 prev_sregs [1] = sregs [1] = reg2;
2034
2035                                 if (G_UNLIKELY (bank))
2036                                         mono_regstate_free_general (rs, reg2, bank);
2037                                 else
2038                                         mono_regstate_free_int (rs, reg2);
2039                         }
2040
2041                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2042                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2043                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2044                                         /* FIXME: */
2045                                         g_assert_not_reached ();
2046
2047                                 /*
2048                                  * sreg1 and dest are already allocated to the same regpair by the
2049                                  * SREG1 allocation code.
2050                                  */
2051                                 g_assert (sregs [0] == ins->dreg);
2052                                 g_assert (dreg_high == sreg1_high);
2053                         }
2054
2055                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2056                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2057                         insert_before_ins (bb, ins, copy);
2058
2059                         if (sreg2_copy)
2060                                 insert_before_ins (bb, copy, sreg2_copy);
2061
2062                         /*
2063                          * Need to prevent sreg2 to be allocated to sreg1, since that
2064                          * would screw up the previous copy.
2065                          */
2066                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2067                         /* we set sreg1 to dest as well */
2068                         prev_sregs [0] = sregs [0] = ins->dreg;
2069                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2070                 }
2071                 mono_inst_set_src_registers (ins, sregs);
2072
2073                 /*
2074                  * TRACK SREG2, 3, ...
2075                  */
2076                 for (j = 1; j < num_sregs; ++j) {
2077                         int k;
2078
2079                         bank = sreg_bank (j, spec);
2080                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2081                                 g_assert_not_reached ();
2082
2083                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2084                                 /*
2085                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2086                                  * allocating it to the fixed reg.
2087                                  */
2088                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2089                                 insert_before_ins (bb, ins, copy);
2090                                 sregs [j] = dest_sregs [j];
2091                         } else if (is_soft_reg (sregs [j], bank)) {
2092                                 val = rs->vassign [sregs [j]];
2093
2094                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2095                                         /*
2096                                          * The sreg is already allocated to a hreg, but not to the fixed
2097                                          * reg required by the instruction. Spill the sreg, so it can be
2098                                          * allocated to the fixed reg by the code below.
2099                                          */
2100                                         /* Currently, this code should only be hit for CAS */
2101                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2102                                         val = rs->vassign [sregs [j]];
2103                                 }
2104
2105                                 if (val < 0) {
2106                                         int spill = 0;
2107                                         if (val < -1) {
2108                                                 /* the register gets spilled after this inst */
2109                                                 spill = -val -1;
2110                                         }
2111                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2112                                         assign_reg (cfg, rs, sregs [j], val, bank);
2113                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2114                                         if (spill) {
2115                                                 /*
2116                                                  * Need to insert before the instruction since it can
2117                                                  * overwrite sreg2.
2118                                                  */
2119                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2120                                         }
2121                                 }
2122                                 sregs [j] = val;
2123                                 for (k = j + 1; k < num_sregs; ++k)
2124                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2125                         }
2126                         else {
2127                                 prev_sregs [j] = -1;
2128                         }
2129                 }
2130                 mono_inst_set_src_registers (ins, sregs);
2131
2132                 /* Sanity check */
2133                 /* Do this only for CAS for now */
2134                 for (j = 1; j < num_sregs; ++j) {
2135                         int sreg = sregs [j];
2136                         int dest_sreg = dest_sregs [j];
2137
2138                         if (j == 2 && dest_sreg != -1) {
2139                                 int k;
2140
2141                                 g_assert (sreg == dest_sreg);
2142
2143                                 for (k = 0; k < num_sregs; ++k) {
2144                                         if (k != j)
2145                                                 g_assert (sregs [k] != dest_sreg);
2146                                 }
2147                         }
2148                 }
2149
2150                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2151                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2152                         mono_regstate_free_int (rs, ins->sreg1);
2153                 }
2154                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2155                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2156                         mono_regstate_free_int (rs, ins->sreg2);
2157                 }*/
2158
2159                 DEBUG (mono_print_ins_index (i, ins));
2160         }
2161
2162         // FIXME: Set MAX_FREGS to 8
2163         // FIXME: Optimize generated code
2164 #if MONO_ARCH_USE_FPSTACK
2165         /*
2166          * Make a forward pass over the code, simulating the fp stack, making sure the
2167          * arguments required by the fp opcodes are at the top of the stack.
2168          */
2169         if (has_fp) {
2170                 MonoInst *prev = NULL;
2171                 MonoInst *fxch;
2172                 int tmp;
2173
2174                 g_assert (num_sregs <= 2);
2175
2176                 for (ins = bb->code; ins; ins = ins->next) {
2177                         spec = ins_get_spec (ins->opcode);
2178
2179                         DEBUG (printf ("processing:"));
2180                         DEBUG (mono_print_ins_index (0, ins));
2181
2182                         if (ins->opcode == OP_FMOVE) {
2183                                 /* Do it by renaming the source to the destination on the stack */
2184                                 // FIXME: Is this correct ?
2185                                 for (i = 0; i < sp; ++i)
2186                                         if (fpstack [i] == ins->sreg1)
2187                                                 fpstack [i] = ins->dreg;
2188                                 prev = ins;
2189                                 continue;
2190                         }
2191
2192                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2193                                 /* Arg1 must be in %st(1) */
2194                                 g_assert (prev);
2195
2196                                 i = 0;
2197                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2198                                         i ++;
2199                                 g_assert (i < sp);
2200
2201                                 if (sp - 1 - i > 0) {
2202                                         /* First move it to %st(0) */
2203                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2204
2205                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2206                                         fxch->inst_imm = sp - 1 - i;
2207
2208                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2209                                         prev = fxch;
2210
2211                                         tmp = fpstack [sp - 1];
2212                                         fpstack [sp - 1] = fpstack [i];
2213                                         fpstack [i] = tmp;
2214                                 }
2215
2216                                 /* Then move it to %st(1) */
2217                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2218
2219                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2220                                 fxch->inst_imm = 1;
2221
2222                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2223                                 prev = fxch;
2224
2225                                 tmp = fpstack [sp - 1];
2226                                 fpstack [sp - 1] = fpstack [sp - 2];
2227                                 fpstack [sp - 2] = tmp;
2228                         }
2229
2230                         if (sreg2_is_fp (spec)) {
2231                                 g_assert (sp > 0);
2232
2233                                 if (fpstack [sp - 1] != ins->sreg2) {
2234                                         g_assert (prev);
2235
2236                                         i = 0;
2237                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2238                                                 i ++;
2239                                         g_assert (i < sp);
2240
2241                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2242
2243                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2244                                         fxch->inst_imm = sp - 1 - i;
2245
2246                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2247                                         prev = fxch;
2248
2249                                         tmp = fpstack [sp - 1];
2250                                         fpstack [sp - 1] = fpstack [i];
2251                                         fpstack [i] = tmp;
2252                                 }
2253
2254                                 sp --;
2255                         }
2256
2257                         if (sreg1_is_fp (spec)) {
2258                                 g_assert (sp > 0);
2259
2260                                 if (fpstack [sp - 1] != ins->sreg1) {
2261                                         g_assert (prev);
2262
2263                                         i = 0;
2264                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2265                                                 i ++;
2266                                         g_assert (i < sp);
2267
2268                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2269
2270                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2271                                         fxch->inst_imm = sp - 1 - i;
2272
2273                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2274                                         prev = fxch;
2275
2276                                         tmp = fpstack [sp - 1];
2277                                         fpstack [sp - 1] = fpstack [i];
2278                                         fpstack [i] = tmp;
2279                                 }
2280
2281                                 sp --;
2282                         }
2283
2284                         if (dreg_is_fp (spec)) {
2285                                 g_assert (sp < 8);
2286                                 fpstack [sp ++] = ins->dreg;
2287                         }
2288
2289                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2290                                 printf ("\t[");
2291                                 for (i = 0; i < sp; ++i)
2292                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2293                                 printf ("]\n");
2294                         }
2295
2296                         prev = ins;
2297                 }
2298
2299                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2300                         /* Remove remaining items from the fp stack */
2301                         /*
2302                          * These can remain for example as a result of a dead fmove like in
2303                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2304                          */
2305                         while (sp) {
2306                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2307                                 mono_add_ins_to_end (bb, ins);
2308                                 sp --;
2309                         }
2310                 }
2311         }
2312 #endif
2313 }
2314
2315 CompRelation
2316 mono_opcode_to_cond (int opcode)
2317 {
2318         switch (opcode) {
2319         case OP_CEQ:
2320         case OP_IBEQ:
2321         case OP_ICEQ:
2322         case OP_LBEQ:
2323         case OP_LCEQ:
2324         case OP_FBEQ:
2325         case OP_FCEQ:
2326         case OP_COND_EXC_EQ:
2327         case OP_COND_EXC_IEQ:
2328         case OP_CMOV_IEQ:
2329         case OP_CMOV_LEQ:
2330                 return CMP_EQ;
2331         case OP_IBNE_UN:
2332         case OP_LBNE_UN:
2333         case OP_FBNE_UN:
2334         case OP_COND_EXC_NE_UN:
2335         case OP_COND_EXC_INE_UN:
2336         case OP_CMOV_INE_UN:
2337         case OP_CMOV_LNE_UN:
2338                 return CMP_NE;
2339         case OP_IBLE:
2340         case OP_LBLE:
2341         case OP_FBLE:
2342         case OP_CMOV_ILE:
2343         case OP_CMOV_LLE:
2344                 return CMP_LE;
2345         case OP_IBGE:
2346         case OP_LBGE:
2347         case OP_FBGE:
2348         case OP_CMOV_IGE:
2349         case OP_CMOV_LGE:
2350                 return CMP_GE;
2351         case OP_CLT:
2352         case OP_IBLT:
2353         case OP_ICLT:
2354         case OP_LBLT:
2355         case OP_LCLT:
2356         case OP_FBLT:
2357         case OP_FCLT:
2358         case OP_COND_EXC_LT:
2359         case OP_COND_EXC_ILT:
2360         case OP_CMOV_ILT:
2361         case OP_CMOV_LLT:
2362                 return CMP_LT;
2363         case OP_CGT:
2364         case OP_IBGT:
2365         case OP_ICGT:
2366         case OP_LBGT:
2367         case OP_LCGT:
2368         case OP_FBGT:
2369         case OP_FCGT:
2370         case OP_COND_EXC_GT:
2371         case OP_COND_EXC_IGT:
2372         case OP_CMOV_IGT:
2373         case OP_CMOV_LGT:
2374                 return CMP_GT;
2375
2376         case OP_IBLE_UN:
2377         case OP_LBLE_UN:
2378         case OP_FBLE_UN:
2379         case OP_COND_EXC_LE_UN:
2380         case OP_COND_EXC_ILE_UN:
2381         case OP_CMOV_ILE_UN:
2382         case OP_CMOV_LLE_UN:
2383                 return CMP_LE_UN;
2384         case OP_IBGE_UN:
2385         case OP_LBGE_UN:
2386         case OP_FBGE_UN:
2387         case OP_CMOV_IGE_UN:
2388         case OP_CMOV_LGE_UN:
2389                 return CMP_GE_UN;
2390         case OP_CLT_UN:
2391         case OP_IBLT_UN:
2392         case OP_ICLT_UN:
2393         case OP_LBLT_UN:
2394         case OP_LCLT_UN:
2395         case OP_FBLT_UN:
2396         case OP_FCLT_UN:
2397         case OP_COND_EXC_LT_UN:
2398         case OP_COND_EXC_ILT_UN:
2399         case OP_CMOV_ILT_UN:
2400         case OP_CMOV_LLT_UN:
2401                 return CMP_LT_UN;
2402         case OP_CGT_UN:
2403         case OP_IBGT_UN:
2404         case OP_ICGT_UN:
2405         case OP_LBGT_UN:
2406         case OP_LCGT_UN:
2407         case OP_FCGT_UN:
2408         case OP_FBGT_UN:
2409         case OP_COND_EXC_GT_UN:
2410         case OP_COND_EXC_IGT_UN:
2411         case OP_CMOV_IGT_UN:
2412         case OP_CMOV_LGT_UN:
2413                 return CMP_GT_UN;
2414         default:
2415                 printf ("%s\n", mono_inst_name (opcode));
2416                 g_assert_not_reached ();
2417                 return 0;
2418         }
2419 }
2420
2421 CompRelation
2422 mono_negate_cond (CompRelation cond)
2423 {
2424         switch (cond) {
2425         case CMP_EQ:
2426                 return CMP_NE;
2427         case CMP_NE:
2428                 return CMP_EQ;
2429         case CMP_LE:
2430                 return CMP_GT;
2431         case CMP_GE:
2432                 return CMP_LT;
2433         case CMP_LT:
2434                 return CMP_GE;
2435         case CMP_GT:
2436                 return CMP_LE;
2437         case CMP_LE_UN:
2438                 return CMP_GT_UN;
2439         case CMP_GE_UN:
2440                 return CMP_LT_UN;
2441         case CMP_LT_UN:
2442                 return CMP_GE_UN;
2443         case CMP_GT_UN:
2444                 return CMP_LE_UN;
2445         default:
2446                 g_assert_not_reached ();
2447         }
2448 }
2449
2450 CompType
2451 mono_opcode_to_type (int opcode, int cmp_opcode)
2452 {
2453         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2454                 return CMP_TYPE_L;
2455         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2456                 return CMP_TYPE_I;
2457         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2458                 return CMP_TYPE_I;
2459         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2460                 return CMP_TYPE_L;
2461         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2462                 return CMP_TYPE_L;
2463         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2464                 return CMP_TYPE_F;
2465         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2466                 return CMP_TYPE_F;
2467         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2468                 return CMP_TYPE_I;
2469         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2470                 switch (cmp_opcode) {
2471                 case OP_ICOMPARE:
2472                 case OP_ICOMPARE_IMM:
2473                         return CMP_TYPE_I;
2474                 default:
2475                         return CMP_TYPE_L;
2476                 }
2477         } else {
2478                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2479                 return 0;
2480         }
2481 }
2482
2483 #endif /* DISABLE_JIT */
2484
2485 gboolean
2486 mono_is_regsize_var (MonoType *t)
2487 {
2488         if (t->byref)
2489                 return TRUE;
2490         t = mono_type_get_underlying_type (t);
2491         switch (t->type) {
2492         case MONO_TYPE_BOOLEAN:
2493         case MONO_TYPE_CHAR:
2494         case MONO_TYPE_I1:
2495         case MONO_TYPE_U1:
2496         case MONO_TYPE_I2:
2497         case MONO_TYPE_U2:
2498         case MONO_TYPE_I4:
2499         case MONO_TYPE_U4:
2500         case MONO_TYPE_I:
2501         case MONO_TYPE_U:
2502         case MONO_TYPE_PTR:
2503         case MONO_TYPE_FNPTR:
2504 #if SIZEOF_REGISTER == 8
2505         case MONO_TYPE_I8:
2506         case MONO_TYPE_U8:
2507 #endif
2508                 return TRUE;
2509         case MONO_TYPE_OBJECT:
2510         case MONO_TYPE_STRING:
2511         case MONO_TYPE_CLASS:
2512         case MONO_TYPE_SZARRAY:
2513         case MONO_TYPE_ARRAY:
2514                 return TRUE;
2515         case MONO_TYPE_GENERICINST:
2516                 if (!mono_type_generic_inst_is_valuetype (t))
2517                         return TRUE;
2518                 return FALSE;
2519         case MONO_TYPE_VALUETYPE:
2520                 return FALSE;
2521         default:
2522                 return FALSE;
2523         }
2524 }
2525
2526 #ifndef DISABLE_JIT
2527
2528 /*
2529  * mono_peephole_ins:
2530  *
2531  *   Perform some architecture independent peephole optimizations.
2532  */
2533 void
2534 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2535 {
2536         MonoInst *last_ins = ins->prev;
2537
2538         switch (ins->opcode) {
2539         case OP_MUL_IMM:
2540                 /* remove unnecessary multiplication with 1 */
2541                 if (ins->inst_imm == 1) {
2542                         if (ins->dreg != ins->sreg1)
2543                                 ins->opcode = OP_MOVE;
2544                         else
2545                                 MONO_DELETE_INS (bb, ins);
2546                 }
2547                 break;
2548         case OP_LOAD_MEMBASE:
2549         case OP_LOADI4_MEMBASE:
2550                 /*
2551                  * Note: if reg1 = reg2 the load op is removed
2552                  *
2553                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2554                  * OP_LOAD_MEMBASE offset(basereg), reg2
2555                  * -->
2556                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2557                  * OP_MOVE reg1, reg2
2558                  */
2559                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2560                         last_ins = last_ins->prev;
2561                 if (last_ins &&
2562                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2563                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2564                         ins->inst_basereg == last_ins->inst_destbasereg &&
2565                         ins->inst_offset == last_ins->inst_offset) {
2566                         if (ins->dreg == last_ins->sreg1) {
2567                                 MONO_DELETE_INS (bb, ins);
2568                                 break;
2569                         } else {
2570                                 ins->opcode = OP_MOVE;
2571                                 ins->sreg1 = last_ins->sreg1;
2572                         }
2573
2574                         /*
2575                          * Note: reg1 must be different from the basereg in the second load
2576                          * Note: if reg1 = reg2 is equal then second load is removed
2577                          *
2578                          * OP_LOAD_MEMBASE offset(basereg), reg1
2579                          * OP_LOAD_MEMBASE offset(basereg), reg2
2580                          * -->
2581                          * OP_LOAD_MEMBASE offset(basereg), reg1
2582                          * OP_MOVE reg1, reg2
2583                          */
2584                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2585                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2586                           ins->inst_basereg != last_ins->dreg &&
2587                           ins->inst_basereg == last_ins->inst_basereg &&
2588                           ins->inst_offset == last_ins->inst_offset) {
2589
2590                         if (ins->dreg == last_ins->dreg) {
2591                                 MONO_DELETE_INS (bb, ins);
2592                         } else {
2593                                 ins->opcode = OP_MOVE;
2594                                 ins->sreg1 = last_ins->dreg;
2595                         }
2596
2597                         //g_assert_not_reached ();
2598
2599 #if 0
2600                         /*
2601                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2602                          * OP_LOAD_MEMBASE offset(basereg), reg
2603                          * -->
2604                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2605                          * OP_ICONST reg, imm
2606                          */
2607                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2608                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2609                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2610                                    ins->inst_offset == last_ins->inst_offset) {
2611                         ins->opcode = OP_ICONST;
2612                         ins->inst_c0 = last_ins->inst_imm;
2613                         g_assert_not_reached (); // check this rule
2614 #endif
2615                 }
2616                 break;
2617         case OP_LOADI1_MEMBASE:
2618         case OP_LOADU1_MEMBASE:
2619                 /*
2620                  * Note: if reg1 = reg2 the load op is removed
2621                  *
2622                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2623                  * OP_LOAD_MEMBASE offset(basereg), reg2
2624                  * -->
2625                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2626                  * OP_MOVE reg1, reg2
2627                  */
2628                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2629                         ins->inst_basereg == last_ins->inst_destbasereg &&
2630                         ins->inst_offset == last_ins->inst_offset) {
2631                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2632                         ins->sreg1 = last_ins->sreg1;
2633                 }
2634                 break;
2635         case OP_LOADI2_MEMBASE:
2636         case OP_LOADU2_MEMBASE:
2637                 /*
2638                  * Note: if reg1 = reg2 the load op is removed
2639                  *
2640                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2641                  * OP_LOAD_MEMBASE offset(basereg), reg2
2642                  * -->
2643                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2644                  * OP_MOVE reg1, reg2
2645                  */
2646                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2647                         ins->inst_basereg == last_ins->inst_destbasereg &&
2648                         ins->inst_offset == last_ins->inst_offset) {
2649 #if SIZEOF_REGISTER == 8
2650                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2651 #else
2652                         /* The definition of OP_PCONV_TO_U2 is wrong */
2653                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2654 #endif
2655                         ins->sreg1 = last_ins->sreg1;
2656                 }
2657                 break;
2658         case OP_MOVE:
2659         case OP_FMOVE:
2660                 /*
2661                  * Removes:
2662                  *
2663                  * OP_MOVE reg, reg
2664                  */
2665                 if (ins->dreg == ins->sreg1) {
2666                         MONO_DELETE_INS (bb, ins);
2667                         break;
2668                 }
2669                 /*
2670                  * Removes:
2671                  *
2672                  * OP_MOVE sreg, dreg
2673                  * OP_MOVE dreg, sreg
2674                  */
2675                 if (last_ins && last_ins->opcode == ins->opcode &&
2676                         ins->sreg1 == last_ins->dreg &&
2677                         ins->dreg == last_ins->sreg1) {
2678                         MONO_DELETE_INS (bb, ins);
2679                 }
2680                 break;
2681         case OP_NOP:
2682                 MONO_DELETE_INS (bb, ins);
2683                 break;
2684         }
2685 }
2686
2687 #endif /* DISABLE_JIT */