2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
13 #include <mono/metadata/appdomain.h>
14 #include <mono/metadata/debug-helpers.h>
15 #include <mono/metadata/threads.h>
16 #include <mono/metadata/profiler-private.h>
17 #include <mono/metadata/mempool-internals.h>
18 #include <mono/utils/mono-math.h>
22 #include "mini-arch.h"
24 #ifndef MONO_MAX_XREGS
26 #define MONO_MAX_XREGS 0
27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
28 #define MONO_ARCH_CALLEE_XREGS 0
33 #define MONO_ARCH_BANK_MIRRORED -2
35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
37 #ifndef MONO_ARCH_NEED_SIMD_BANK
38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
49 #define get_mirrored_bank(bank) (-1)
51 #define is_hreg_mirrored(rs, bank, hreg) (0)
56 /* If the bank is mirrored return the true logical bank that the register in the
57 * physical register bank is allocated to.
59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
60 return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
64 * Every hardware register belongs to a register type or register bank. bank 0
65 * contains the int registers, bank 1 contains the fp registers.
66 * int registers are used 99% of the time, so they are special cased in a lot of
70 static const int regbank_size [] = {
78 static const int regbank_load_ops [] = {
86 static const int regbank_store_ops [] = {
87 OP_STORER_MEMBASE_REG,
88 OP_STORER8_MEMBASE_REG,
89 OP_STORER_MEMBASE_REG,
90 OP_STORER_MEMBASE_REG,
94 static const int regbank_move_ops [] = {
102 #define regmask(reg) (((regmask_t)1) << (reg))
104 static const regmask_t regbank_callee_saved_regs [] = {
105 MONO_ARCH_CALLEE_SAVED_REGS,
106 MONO_ARCH_CALLEE_SAVED_FREGS,
107 MONO_ARCH_CALLEE_SAVED_REGS,
108 MONO_ARCH_CALLEE_SAVED_REGS,
109 MONO_ARCH_CALLEE_SAVED_XREGS,
112 static const regmask_t regbank_callee_regs [] = {
113 MONO_ARCH_CALLEE_REGS,
114 MONO_ARCH_CALLEE_FREGS,
115 MONO_ARCH_CALLEE_REGS,
116 MONO_ARCH_CALLEE_REGS,
117 MONO_ARCH_CALLEE_XREGS,
120 static const int regbank_spill_var_size[] = {
125 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
131 mono_regstate_assign (MonoRegState *rs)
133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
134 /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
135 * if the values here are not the same.
137 g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
138 g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
139 g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
142 if (rs->next_vreg > rs->vassign_size) {
143 g_free (rs->vassign);
144 rs->vassign_size = MAX (rs->next_vreg, 256);
145 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
148 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
149 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
151 rs->symbolic [MONO_REG_INT] = rs->isymbolic;
152 rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
154 #ifdef MONO_ARCH_NEED_SIMD_BANK
155 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
156 rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
163 regmask_t mask = allow & rs->ifree_mask;
165 #if defined(__x86_64__) && defined(__GNUC__)
172 __asm__("bsfq %1,%0\n\t"
173 : "=r" (i) : "rm" (mask));
175 rs->ifree_mask &= ~ ((regmask_t)1 << i);
181 for (i = 0; i < MONO_MAX_IREGS; ++i) {
182 if (mask & ((regmask_t)1 << i)) {
183 rs->ifree_mask &= ~ ((regmask_t)1 << i);
192 mono_regstate_free_int (MonoRegState *rs, int reg)
195 rs->ifree_mask |= (regmask_t)1 << reg;
196 rs->isymbolic [reg] = 0;
201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
205 regmask_t mask = allow & rs->free_mask [bank];
206 for (i = 0; i < regbank_size [bank]; ++i) {
207 if (mask & ((regmask_t)1 << i)) {
208 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
210 mirrored_bank = get_mirrored_bank (bank);
211 if (mirrored_bank == -1)
214 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
227 rs->free_mask [bank] |= (regmask_t)1 << reg;
228 rs->symbolic [bank][reg] = 0;
230 mirrored_bank = get_mirrored_bank (bank);
231 if (mirrored_bank == -1)
233 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
234 rs->symbolic [mirrored_bank][reg] = 0;
239 mono_regname_full (int reg, int bank)
241 if (G_UNLIKELY (bank)) {
242 #if MONO_ARCH_NEED_SIMD_BANK
243 if (bank == MONO_REG_SIMD)
244 return mono_arch_xregname (reg);
246 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
247 return mono_arch_regname (reg);
248 g_assert (bank == MONO_REG_DOUBLE);
249 return mono_arch_fregname (reg);
251 return mono_arch_regname (reg);
256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
260 regpair = (((guint32)hreg) << 24) + vreg;
261 if (G_UNLIKELY (bank)) {
262 g_assert (vreg >= regbank_size [bank]);
263 g_assert (hreg < regbank_size [bank]);
264 call->used_fregs |= 1 << hreg;
265 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
267 g_assert (vreg >= MONO_MAX_IREGS);
268 g_assert (hreg < MONO_MAX_IREGS);
269 call->used_iregs |= 1 << hreg;
270 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
275 * mono_call_inst_add_outarg_vt:
277 * Register OUTARG_VT as belonging to CALL.
280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
282 call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
286 resize_spill_info (MonoCompile *cfg, int bank)
288 MonoSpillInfo *orig_info = cfg->spill_info [bank];
289 int orig_len = cfg->spill_info_len [bank];
290 int new_len = orig_len ? orig_len * 2 : 16;
291 MonoSpillInfo *new_info;
294 g_assert (bank < MONO_NUM_REGBANKS);
296 new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
298 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
299 for (i = orig_len; i < new_len; ++i)
300 new_info [i].offset = -1;
302 cfg->spill_info [bank] = new_info;
303 cfg->spill_info_len [bank] = new_len;
307 * returns the offset used by spillvar. It allocates a new
308 * spill variable if necessary.
311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
316 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
317 while (spillvar >= cfg->spill_info_len [bank])
318 resize_spill_info (cfg, bank);
322 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
324 info = &cfg->spill_info [bank][spillvar];
325 if (info->offset == -1) {
326 cfg->stack_offset += sizeof (mgreg_t) - 1;
327 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
329 g_assert (bank < MONO_NUM_REGBANKS);
330 if (G_UNLIKELY (bank))
331 size = regbank_spill_var_size [bank];
333 size = sizeof (mgreg_t);
335 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
336 cfg->stack_offset += size - 1;
337 cfg->stack_offset &= ~(size - 1);
338 info->offset = cfg->stack_offset;
339 cfg->stack_offset += size;
341 cfg->stack_offset += size - 1;
342 cfg->stack_offset &= ~(size - 1);
343 cfg->stack_offset += size;
344 info->offset = - cfg->stack_offset;
351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
364 #ifndef MONO_ARCH_INST_IS_FLOAT
365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
369 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
374 #define reg_is_simd(desc) ((desc) == 'x')
376 #ifdef MONO_ARCH_NEED_SIMD_BANK
378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
382 #define reg_bank(desc) reg_is_fp ((desc))
386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
387 #define sreg1_bank(spec) sreg_bank (0, (spec))
388 #define sreg2_bank(spec) sreg_bank (1, (spec))
389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
399 #undef is_global_ireg
400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
409 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
412 #ifndef DISABLE_LOGGING
415 print_ji (MonoJumpInfo *ji)
418 case MONO_PATCH_INFO_RGCTX_FETCH: {
419 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
421 printf ("[RGCTX_FETCH ");
422 print_ji (entry->data);
423 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
426 case MONO_PATCH_INFO_METHODCONST: {
427 char *s = mono_method_full_name (ji->data.method, TRUE);
428 printf ("[METHODCONST - %s]", s);
433 printf ("[%d]", ji->type);
439 mono_print_ins_index (int i, MonoInst *ins)
441 const char *spec = ins_get_spec (ins->opcode);
443 int sregs [MONO_MAX_SRC_REGS];
446 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
448 printf (" %s", mono_inst_name (ins->opcode));
449 if (spec == MONO_ARCH_CPU_SPEC) {
450 /* This is a lowered opcode */
452 printf (" R%d <-", ins->dreg);
453 if (ins->sreg1 != -1)
454 printf (" R%d", ins->sreg1);
455 if (ins->sreg2 != -1)
456 printf (" R%d", ins->sreg2);
457 if (ins->sreg3 != -1)
458 printf (" R%d", ins->sreg3);
460 switch (ins->opcode) {
471 if (!ins->inst_false_bb)
472 printf (" [B%d]", ins->inst_true_bb->block_num);
474 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
481 printf (" [%d (", (int)ins->inst_c0);
482 for (i = 0; i < ins->inst_phi_args [0]; i++) {
485 printf ("R%d", ins->inst_phi_args [i + 1]);
491 case OP_OUTARG_VTRETADDR:
492 printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
495 printf (" + 0x%lx", (long)ins->inst_offset);
502 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
506 if (spec [MONO_INST_DEST]) {
507 int bank = dreg_bank (spec);
508 if (is_soft_reg (ins->dreg, bank)) {
509 if (spec [MONO_INST_DEST] == 'b') {
510 if (ins->inst_offset == 0)
511 printf (" [R%d] <-", ins->dreg);
513 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
516 printf (" R%d <-", ins->dreg);
517 } else if (spec [MONO_INST_DEST] == 'b') {
518 if (ins->inst_offset == 0)
519 printf (" [%s] <-", mono_arch_regname (ins->dreg));
521 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
523 printf (" %s <-", mono_regname_full (ins->dreg, bank));
525 if (spec [MONO_INST_SRC1]) {
526 int bank = sreg1_bank (spec);
527 if (is_soft_reg (ins->sreg1, bank)) {
528 if (spec [MONO_INST_SRC1] == 'b')
529 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
531 printf (" R%d", ins->sreg1);
532 } else if (spec [MONO_INST_SRC1] == 'b')
533 printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
535 printf (" %s", mono_regname_full (ins->sreg1, bank));
537 num_sregs = mono_inst_get_src_registers (ins, sregs);
538 for (j = 1; j < num_sregs; ++j) {
539 int bank = sreg_bank (j, spec);
540 if (is_soft_reg (sregs [j], bank))
541 printf (" R%d", sregs [j]);
543 printf (" %s", mono_regname_full (sregs [j], bank));
546 switch (ins->opcode) {
548 printf (" [%d]", (int)ins->inst_c0);
550 #if defined(TARGET_X86) || defined(TARGET_AMD64)
551 case OP_X86_PUSH_IMM:
553 case OP_ICOMPARE_IMM:
561 printf (" [%d]", (int)ins->inst_imm);
565 printf (" [%d]", (int)(gssize)ins->inst_p1);
568 printf (" [%lld]", (long long)ins->inst_l);
571 printf (" [%f]", *(double*)ins->inst_p0);
574 printf (" [%f]", *(float*)ins->inst_p0);
577 case OP_CALL_MEMBASE:
586 case OP_VCALL_MEMBASE:
589 case OP_VCALL2_MEMBASE:
591 case OP_VOIDCALL_MEMBASE:
592 case OP_VOIDCALLVIRT:
594 MonoCallInst *call = (MonoCallInst*)ins;
597 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
599 * These are lowered opcodes, but they are in the .md files since the old
600 * JIT passes them to backends.
603 printf (" R%d <-", ins->dreg);
607 char *full_name = mono_method_full_name (call->method, TRUE);
608 printf (" [%s]", full_name);
610 } else if (call->fptr_is_patch) {
611 MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
615 } else if (call->fptr) {
616 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
618 printf (" [%s]", info->name);
621 list = call->out_ireg_args;
626 regpair = (guint32)(gssize)(list->data);
627 hreg = regpair >> 24;
628 reg = regpair & 0xffffff;
630 printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
632 list = g_slist_next (list);
637 case OP_CALL_HANDLER:
638 printf (" [B%d]", ins->inst_target_bb->block_num);
660 if (!ins->inst_false_bb)
661 printf (" [B%d]", ins->inst_true_bb->block_num);
663 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
665 case OP_LIVERANGE_START:
666 case OP_LIVERANGE_END:
667 case OP_GC_LIVENESS_DEF:
668 case OP_GC_LIVENESS_USE:
669 printf (" R%d", (int)ins->inst_c1);
672 printf (" il: %x", (int)ins->inst_imm);
678 if (spec [MONO_INST_CLOB])
679 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
684 print_regtrack (RegTrack *t, int num)
690 for (i = 0; i < num; ++i) {
693 if (i >= MONO_MAX_IREGS) {
694 g_snprintf (buf, sizeof(buf), "R%d", i);
697 r = mono_arch_regname (i);
698 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
703 mono_print_ins_index (int i, MonoInst *ins)
706 #endif /* DISABLE_LOGGING */
709 mono_print_ins (MonoInst *ins)
711 mono_print_ins_index (-1, ins);
715 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
718 * If this function is called multiple times, the new instructions are inserted
719 * in the proper order.
721 mono_bblock_insert_before_ins (bb, ins, to_insert);
725 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
728 * If this function is called multiple times, the new instructions are inserted in
731 mono_bblock_insert_after_ins (bb, *last, to_insert);
737 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
739 if (vreg_is_ref (cfg, reg))
740 return MONO_REG_INT_REF;
741 else if (vreg_is_mp (cfg, reg))
742 return MONO_REG_INT_MP;
748 * Force the spilling of the variable in the symbolic register 'reg', and free
749 * the hreg it was assigned to.
752 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
757 MonoRegState *rs = cfg->rs;
759 symbolic = rs->symbolic [bank];
760 sel = rs->vassign [reg];
762 /* the vreg we need to spill lives in another logical reg bank */
763 bank = translate_bank (cfg->rs, bank, sel);
765 /*i = rs->isymbolic [sel];
766 g_assert (i == reg);*/
768 spill = ++cfg->spill_count;
769 rs->vassign [i] = -spill - 1;
770 if (G_UNLIKELY (bank))
771 mono_regstate_free_general (rs, sel, bank);
773 mono_regstate_free_int (rs, sel);
774 /* we need to create a spill var and insert a load to sel after the current instruction */
775 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
777 load->inst_basereg = cfg->frame_reg;
778 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
779 insert_after_ins (bb, ins, last, load);
780 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
781 if (G_UNLIKELY (bank))
782 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
784 i = mono_regstate_alloc_int (rs, regmask (sel));
787 if (G_UNLIKELY (bank))
788 mono_regstate_free_general (rs, sel, bank);
790 mono_regstate_free_int (rs, sel);
793 /* This isn't defined on older glib versions and on some platforms */
794 #ifndef G_GUINT64_FORMAT
795 #define G_GUINT64_FORMAT "ul"
799 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
802 int i, sel, spill, num_sregs;
803 int sregs [MONO_MAX_SRC_REGS];
805 MonoRegState *rs = cfg->rs;
807 symbolic = rs->symbolic [bank];
809 g_assert (bank < MONO_NUM_REGBANKS);
811 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
812 /* exclude the registers in the current instruction */
813 num_sregs = mono_inst_get_src_registers (ins, sregs);
814 for (i = 0; i < num_sregs; ++i) {
815 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
816 if (is_soft_reg (sregs [i], bank))
817 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
819 regmask &= ~ (regmask (sregs [i]));
820 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
823 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
824 regmask &= ~ (regmask (ins->dreg));
825 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
828 DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
829 g_assert (regmask); /* need at least a register we can free */
831 /* we should track prev_use and spill the register that's farther */
832 if (G_UNLIKELY (bank)) {
833 for (i = 0; i < regbank_size [bank]; ++i) {
834 if (regmask & (regmask (i))) {
837 /* the vreg we need to load lives in another logical bank */
838 bank = translate_bank (cfg->rs, bank, sel);
840 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
845 i = rs->symbolic [bank] [sel];
846 spill = ++cfg->spill_count;
847 rs->vassign [i] = -spill - 1;
848 mono_regstate_free_general (rs, sel, bank);
851 for (i = 0; i < MONO_MAX_IREGS; ++i) {
852 if (regmask & (regmask (i))) {
854 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
859 i = rs->isymbolic [sel];
860 spill = ++cfg->spill_count;
861 rs->vassign [i] = -spill - 1;
862 mono_regstate_free_int (rs, sel);
865 /* we need to create a spill var and insert a load to sel after the current instruction */
866 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
868 load->inst_basereg = cfg->frame_reg;
869 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
870 insert_after_ins (bb, ins, last, load);
871 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
872 if (G_UNLIKELY (bank))
873 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
875 i = mono_regstate_alloc_int (rs, regmask (sel));
884 * Free up the hreg HREG by spilling the vreg allocated to it.
887 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
889 if (G_UNLIKELY (bank)) {
890 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
891 bank = translate_bank (cfg->rs, bank, hreg);
892 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
893 spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
897 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
898 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
899 spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
905 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
909 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
915 mono_bblock_insert_after_ins (bb, ins, copy);
918 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
922 static inline const char*
923 regbank_to_string (int bank)
925 if (bank == MONO_REG_INT_REF)
927 else if (bank == MONO_REG_INT_MP)
934 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
936 MonoInst *store, *def;
938 bank = get_vreg_bank (cfg, prev_reg, bank);
940 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
942 store->inst_destbasereg = cfg->frame_reg;
943 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
945 mono_bblock_insert_after_ins (bb, ins, store);
947 } else if (insert_before) {
948 insert_before_ins (bb, insert_before, store);
950 g_assert_not_reached ();
952 DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
954 if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
955 g_assert (prev_reg != -1);
956 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
957 def->inst_c0 = spill;
959 mono_bblock_insert_after_ins (bb, store, def);
963 /* flags used in reginfo->flags */
965 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
966 MONO_FP_NEEDS_SPILL = regmask (1),
967 MONO_FP_NEEDS_LOAD = regmask (2)
971 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
975 if (info && info->preferred_mask) {
976 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
978 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
983 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
985 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
991 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
995 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
998 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1004 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1006 if (G_UNLIKELY (bank))
1007 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1009 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1013 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1015 if (G_UNLIKELY (bank)) {
1018 g_assert (reg >= regbank_size [bank]);
1019 g_assert (hreg < regbank_size [bank]);
1020 g_assert (! is_global_freg (hreg));
1022 rs->vassign [reg] = hreg;
1023 rs->symbolic [bank] [hreg] = reg;
1024 rs->free_mask [bank] &= ~ (regmask (hreg));
1026 mirrored_bank = get_mirrored_bank (bank);
1027 if (mirrored_bank == -1)
1030 /* Make sure the other logical reg bank that this bank shares
1031 * a single hard reg bank knows that this hard reg is not free.
1033 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1035 /* Mark the other logical bank that the this bank shares
1036 * a single hard reg bank with as mirrored.
1038 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1042 g_assert (reg >= MONO_MAX_IREGS);
1043 g_assert (hreg < MONO_MAX_IREGS);
1045 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1046 g_assert (! is_global_ireg (hreg));
1049 rs->vassign [reg] = hreg;
1050 rs->isymbolic [hreg] = reg;
1051 rs->ifree_mask &= ~ (regmask (hreg));
1055 static inline regmask_t
1056 get_callee_mask (const char spec)
1058 if (G_UNLIKELY (reg_bank (spec)))
1059 return regbank_callee_regs [reg_bank (spec)];
1060 return MONO_ARCH_CALLEE_REGS;
1063 static gint8 desc_to_fixed_reg [256];
1064 static gboolean desc_to_fixed_reg_inited = FALSE;
1069 * Local register allocation.
1070 * We first scan the list of instructions and we save the liveness info of
1071 * each register (when the register is first used, when it's value is set etc.).
1072 * We also reverse the list of instructions because assigning registers backwards allows
1073 * for more tricks to be used.
1076 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1078 MonoInst *ins, *prev, *last;
1080 MonoRegState *rs = cfg->rs;
1084 unsigned char spec_src1, spec_dest;
1086 #if MONO_ARCH_USE_FPSTACK
1087 gboolean has_fp = FALSE;
1092 int sregs [MONO_MAX_SRC_REGS];
1097 if (!desc_to_fixed_reg_inited) {
1098 for (i = 0; i < 256; ++i)
1099 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1100 desc_to_fixed_reg_inited = TRUE;
1102 /* Validate the cpu description against the info in mini-ops.h */
1103 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1104 for (i = OP_LOAD; i < OP_LAST; ++i) {
1107 spec = ins_get_spec (i);
1108 ispec = INS_INFO (i);
1110 if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1111 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1112 if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1113 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1114 if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1115 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1120 rs->next_vreg = bb->max_vreg;
1121 mono_regstate_assign (rs);
1123 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1124 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1125 rs->free_mask [i] = regbank_callee_regs [i];
1127 max = rs->next_vreg;
1129 if (cfg->reginfo && cfg->reginfo_len < max)
1130 cfg->reginfo = NULL;
1132 reginfo = cfg->reginfo;
1134 cfg->reginfo_len = MAX (1024, max * 2);
1135 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1138 g_assert (cfg->reginfo_len >= rs->next_vreg);
1140 if (cfg->verbose_level > 1) {
1141 /* print_regtrack reads the info of all variables */
1142 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1146 * For large methods, next_vreg can be very large, so g_malloc0 time can
1147 * be prohibitive. So we manually init the reginfo entries used by the
1150 for (ins = bb->code; ins; ins = ins->next) {
1151 spec = ins_get_spec (ins->opcode);
1153 if ((ins->dreg != -1) && (ins->dreg < max)) {
1154 memset (®info [ins->dreg], 0, sizeof (RegTrack));
1155 #if SIZEOF_REGISTER == 4
1156 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1158 * In the new IR, the two vregs of the regpair do not alias the
1159 * original long vreg. shift the vreg here so the rest of the
1160 * allocator doesn't have to care about it.
1163 memset (®info [ins->dreg + 1], 0, sizeof (RegTrack));
1168 num_sregs = mono_inst_get_src_registers (ins, sregs);
1169 for (j = 0; j < num_sregs; ++j) {
1170 g_assert (sregs [j] != -1);
1171 if (sregs [j] < max) {
1172 memset (®info [sregs [j]], 0, sizeof (RegTrack));
1173 #if SIZEOF_REGISTER == 4
1174 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1176 memset (®info [sregs [j] + 1], 0, sizeof (RegTrack));
1181 mono_inst_set_src_registers (ins, sregs);
1184 /*if (cfg->opt & MONO_OPT_COPYPROP)
1185 local_copy_prop (cfg, ins);*/
1188 DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1189 /* forward pass on the instructions to collect register liveness info */
1190 MONO_BB_FOR_EACH_INS (bb, ins) {
1191 spec = ins_get_spec (ins->opcode);
1192 spec_dest = spec [MONO_INST_DEST];
1194 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1195 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1198 DEBUG (mono_print_ins_index (i, ins));
1200 num_sregs = mono_inst_get_src_registers (ins, sregs);
1202 #if MONO_ARCH_USE_FPSTACK
1203 if (dreg_is_fp (spec)) {
1206 for (j = 0; j < num_sregs; ++j) {
1207 if (sreg_is_fp (j, spec))
1213 for (j = 0; j < num_sregs; ++j) {
1214 int sreg = sregs [j];
1215 int sreg_spec = spec [MONO_INST_SRC1 + j];
1217 bank = sreg_bank (j, spec);
1218 g_assert (sreg != -1);
1219 if (is_soft_reg (sreg, bank))
1220 /* This means the vreg is not local to this bb */
1221 g_assert (reginfo [sreg].born_in > 0);
1222 rs->vassign [sreg] = -1;
1223 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1224 //reginfo [ins->sreg2].last_use = i;
1225 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1226 /* The virtual register is allocated sequentially */
1227 rs->vassign [sreg + 1] = -1;
1228 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1229 //reginfo [ins->sreg2 + 1].last_use = i;
1230 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1231 reginfo [sreg + 1].born_in = i;
1237 mono_inst_set_src_registers (ins, sregs);
1242 bank = dreg_bank (spec);
1243 if (spec_dest != 'b') /* it's not just a base register */
1244 reginfo [ins->dreg].killed_in = i;
1245 g_assert (ins->dreg != -1);
1246 rs->vassign [ins->dreg] = -1;
1247 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1248 //reginfo [ins->dreg].last_use = i;
1249 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1250 reginfo [ins->dreg].born_in = i;
1252 dest_dreg = desc_to_fixed_reg [spec_dest];
1253 if (dest_dreg != -1)
1254 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1256 #ifdef MONO_ARCH_INST_FIXED_MASK
1257 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1260 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1261 /* The virtual register is allocated sequentially */
1262 rs->vassign [ins->dreg + 1] = -1;
1263 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1264 //reginfo [ins->dreg + 1].last_use = i;
1265 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1266 reginfo [ins->dreg + 1].born_in = i;
1267 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1268 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1274 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1275 /* A call instruction implicitly uses all registers in call->out_ireg_args */
1277 MonoCallInst *call = (MonoCallInst*)ins;
1280 list = call->out_ireg_args;
1286 regpair = (guint32)(gssize)(list->data);
1287 hreg = regpair >> 24;
1288 reg = regpair & 0xffffff;
1290 //reginfo [reg].prev_use = reginfo [reg].last_use;
1291 //reginfo [reg].last_use = i;
1293 list = g_slist_next (list);
1297 list = call->out_freg_args;
1303 regpair = (guint32)(gssize)(list->data);
1304 hreg = regpair >> 24;
1305 reg = regpair & 0xffffff;
1307 list = g_slist_next (list);
1317 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1318 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1319 int prev_dreg, clob_dreg;
1320 int dest_dreg, clob_reg;
1321 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1322 int dreg_high, sreg1_high;
1323 regmask_t dreg_mask, mask;
1324 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1325 regmask_t dreg_fixed_mask;
1326 const unsigned char *ip;
1328 spec = ins_get_spec (ins->opcode);
1329 spec_src1 = spec [MONO_INST_SRC1];
1330 spec_dest = spec [MONO_INST_DEST];
1337 dreg_mask = get_callee_mask (spec_dest);
1338 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1339 prev_sregs [j] = -1;
1340 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1341 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1342 #ifdef MONO_ARCH_INST_FIXED_MASK
1343 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1345 sreg_fixed_masks [j] = 0;
1349 DEBUG (printf ("processing:"));
1350 DEBUG (mono_print_ins_index (i, ins));
1359 dest_dreg = desc_to_fixed_reg [spec_dest];
1360 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1361 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1363 #ifdef MONO_ARCH_INST_FIXED_MASK
1364 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1366 dreg_fixed_mask = 0;
1369 num_sregs = mono_inst_get_src_registers (ins, sregs);
1372 * TRACK FIXED SREG2, 3, ...
1374 for (j = 1; j < num_sregs; ++j) {
1375 int sreg = sregs [j];
1376 int dest_sreg = dest_sregs [j];
1378 if (dest_sreg == -1)
1386 * We need to special case this, since on x86, there are only 3
1387 * free registers, and the code below assigns one of them to
1388 * sreg, so we can run out of registers when trying to assign
1389 * dreg. Instead, we just set up the register masks, and let the
1390 * normal sreg2 assignment code handle this. It would be nice to
1391 * do this for all the fixed reg cases too, but there is too much
1395 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1396 sreg_masks [j] = regmask (dest_sreg);
1397 for (k = 0; k < num_sregs; ++k) {
1399 sreg_masks [k] &= ~ (regmask (dest_sreg));
1403 * Spill sreg1/2 if they are assigned to dest_sreg.
1405 for (k = 0; k < num_sregs; ++k) {
1406 if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1407 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1411 * We can also run out of registers while processing sreg2 if sreg3 is
1412 * assigned to another hreg, so spill sreg3 now.
1414 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1415 spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1420 if (rs->ifree_mask & (regmask (dest_sreg))) {
1421 if (is_global_ireg (sreg)) {
1423 /* Argument already in hard reg, need to copy */
1424 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1425 insert_before_ins (bb, ins, copy);
1426 for (k = 0; k < num_sregs; ++k) {
1428 sreg_masks [k] &= ~ (regmask (dest_sreg));
1431 val = rs->vassign [sreg];
1433 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1434 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1435 } else if (val < -1) {
1437 g_assert_not_reached ();
1439 /* Argument already in hard reg, need to copy */
1440 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1443 insert_before_ins (bb, ins, copy);
1444 for (k = 0; k < num_sregs; ++k) {
1446 sreg_masks [k] &= ~ (regmask (dest_sreg));
1449 * Prevent the dreg from being allocate to dest_sreg
1450 * too, since it could force sreg1 to be allocated to
1451 * the same reg on x86.
1453 dreg_mask &= ~ (regmask (dest_sreg));
1457 gboolean need_spill = TRUE;
1458 gboolean need_assign = TRUE;
1461 dreg_mask &= ~ (regmask (dest_sreg));
1462 for (k = 0; k < num_sregs; ++k) {
1464 sreg_masks [k] &= ~ (regmask (dest_sreg));
1468 * First check if dreg is assigned to dest_sreg2, since we
1469 * can't spill a dreg.
1471 if (spec [MONO_INST_DEST])
1472 val = rs->vassign [ins->dreg];
1475 if (val == dest_sreg && ins->dreg != sreg) {
1477 * the destination register is already assigned to
1478 * dest_sreg2: we need to allocate another register for it
1479 * and then copy from this to dest_sreg2.
1482 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
1483 g_assert (new_dest >= 0);
1484 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1486 prev_dreg = ins->dreg;
1487 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1488 clob_dreg = ins->dreg;
1489 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1490 mono_regstate_free_int (rs, dest_sreg);
1494 if (is_global_ireg (sreg)) {
1495 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1496 insert_before_ins (bb, ins, copy);
1497 need_assign = FALSE;
1500 val = rs->vassign [sreg];
1501 if (val == dest_sreg) {
1502 /* sreg2 is already assigned to the correct register */
1504 } else if (val < -1) {
1505 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1506 } else if (val >= 0) {
1507 /* sreg2 already assigned to another register */
1509 * We couldn't emit a copy from val to dest_sreg2, because
1510 * val might be spilled later while processing this
1511 * instruction. So we spill sreg2 so it can be allocated to
1514 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1519 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1523 if (rs->vassign [sreg] < -1) {
1526 /* Need to emit a spill store */
1527 spill = - rs->vassign [sreg] - 1;
1528 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1530 /* force-set sreg2 */
1531 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1534 sregs [j] = dest_sreg;
1536 mono_inst_set_src_registers (ins, sregs);
1541 bank = dreg_bank (spec);
1542 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1543 prev_dreg = ins->dreg;
1546 if (spec_dest == 'b') {
1548 * The dest reg is read by the instruction, not written, so
1549 * avoid allocating sreg1/sreg2 to the same reg.
1551 if (dest_sregs [0] != -1)
1552 dreg_mask &= ~ (regmask (dest_sregs [0]));
1553 for (j = 1; j < num_sregs; ++j) {
1554 if (dest_sregs [j] != -1)
1555 dreg_mask &= ~ (regmask (dest_sregs [j]));
1558 val = rs->vassign [ins->dreg];
1559 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1560 /* DREG is already allocated to a register needed for sreg1 */
1561 spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1566 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1567 * various complex situations.
1569 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1570 guint32 dreg2, dest_dreg2;
1572 g_assert (is_soft_reg (ins->dreg, bank));
1574 if (dest_dreg != -1) {
1575 if (rs->vassign [ins->dreg] != dest_dreg)
1576 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1578 dreg2 = ins->dreg + 1;
1579 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1580 if (dest_dreg2 != -1) {
1581 if (rs->vassign [dreg2] != dest_dreg2)
1582 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1587 if (dreg_fixed_mask) {
1589 if (is_global_ireg (ins->dreg)) {
1591 * The argument is already in a hard reg, but that reg is
1592 * not usable by this instruction, so allocate a new one.
1594 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1596 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1597 mono_regstate_free_int (rs, val);
1603 dreg_mask &= dreg_fixed_mask;
1606 if (is_soft_reg (ins->dreg, bank)) {
1607 val = rs->vassign [ins->dreg];
1612 /* the register gets spilled after this inst */
1615 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
1616 assign_reg (cfg, rs, ins->dreg, val, bank);
1618 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1621 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1625 /* Handle regpairs */
1626 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1627 int reg2 = prev_dreg + 1;
1630 g_assert (prev_dreg > -1);
1631 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1632 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1635 mask &= ~regmask (X86_ECX);
1637 val = rs->vassign [reg2];
1641 /* the register gets spilled after this inst */
1644 val = mono_regstate_alloc_int (rs, mask);
1646 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1648 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1651 if (! (mask & (regmask (val)))) {
1652 val = mono_regstate_alloc_int (rs, mask);
1654 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1656 /* Reallocate hreg to the correct register */
1657 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1659 mono_regstate_free_int (rs, rs->vassign [reg2]);
1663 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1664 assign_reg (cfg, rs, reg2, val, bank);
1667 ins->backend.reg3 = val;
1669 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1670 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1671 mono_regstate_free_int (rs, val);
1675 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1677 * In theory, we could free up the hreg even if the vreg is alive,
1678 * but branches inside bblocks force us to assign the same hreg
1679 * to a vreg every time it is encountered.
1681 int dreg = rs->vassign [prev_dreg];
1682 g_assert (dreg >= 0);
1683 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1684 if (G_UNLIKELY (bank))
1685 mono_regstate_free_general (rs, dreg, bank);
1687 mono_regstate_free_int (rs, dreg);
1688 rs->vassign [prev_dreg] = -1;
1691 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1692 /* this instruction only outputs to dest_dreg, need to copy */
1693 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1694 ins->dreg = dest_dreg;
1696 if (G_UNLIKELY (bank)) {
1697 /* the register we need to free up may be used in another logical regbank
1698 * so do a translate just in case.
1700 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1701 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1702 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1705 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1706 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1710 if (spec_dest == 'b') {
1712 * The dest reg is read by the instruction, not written, so
1713 * avoid allocating sreg1/sreg2 to the same reg.
1715 for (j = 0; j < num_sregs; ++j)
1716 if (!sreg_bank (j, spec))
1717 sreg_masks [j] &= ~ (regmask (ins->dreg));
1723 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1724 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1725 free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1728 if (spec [MONO_INST_CLOB] == 'c') {
1729 int j, s, dreg, dreg2, cur_bank;
1732 clob_mask = MONO_ARCH_CALLEE_REGS;
1734 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1736 * Need to avoid spilling the dreg since the dreg is not really
1737 * clobbered by the call.
1739 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1740 dreg = rs->vassign [prev_dreg];
1744 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1745 dreg2 = rs->vassign [prev_dreg + 1];
1749 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1751 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1752 if ((j != dreg) && (j != dreg2))
1753 free_up_hreg (cfg, bb, tmp, ins, j, 0);
1754 else if (rs->isymbolic [j])
1755 /* The hreg is assigned to the dreg of this instruction */
1756 rs->vassign [rs->isymbolic [j]] = -1;
1757 mono_regstate_free_int (rs, j);
1762 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1763 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1764 clob_mask = regbank_callee_regs [cur_bank];
1765 if ((prev_dreg != -1) && reg_bank (spec_dest))
1766 dreg = rs->vassign [prev_dreg];
1770 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1772 /* we are looping though the banks in the outer loop
1773 * so, we don't need to deal with mirrored hregs
1774 * because we will get them in one of the other bank passes.
1776 if (is_hreg_mirrored (rs, cur_bank, j))
1780 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1782 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1783 else if (rs->symbolic [cur_bank] [j])
1784 /* The hreg is assigned to the dreg of this instruction */
1785 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1786 mono_regstate_free_general (rs, j, cur_bank);
1794 * TRACK ARGUMENT REGS
1796 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1797 MonoCallInst *call = (MonoCallInst*)ins;
1801 * This needs to be done before assigning sreg1, so sreg1 will
1802 * not be assigned one of the argument regs.
1806 * Assign all registers in call->out_reg_args to the proper
1807 * argument registers.
1810 list = call->out_ireg_args;
1816 regpair = (guint32)(gssize)(list->data);
1817 hreg = regpair >> 24;
1818 reg = regpair & 0xffffff;
1820 assign_reg (cfg, rs, reg, hreg, 0);
1822 sreg_masks [0] &= ~(regmask (hreg));
1824 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1826 list = g_slist_next (list);
1830 list = call->out_freg_args;
1836 regpair = (guint32)(gssize)(list->data);
1837 hreg = regpair >> 24;
1838 reg = regpair & 0xffffff;
1840 assign_reg (cfg, rs, reg, hreg, 1);
1842 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1844 list = g_slist_next (list);
1852 bank = sreg1_bank (spec);
1853 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1854 int sreg1 = sregs [0];
1855 int dest_sreg1 = dest_sregs [0];
1857 g_assert (is_soft_reg (sreg1, bank));
1859 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1860 if (dest_sreg1 != -1)
1861 g_assert (dest_sreg1 == ins->dreg);
1862 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1863 g_assert (val >= 0);
1865 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1867 g_assert_not_reached ();
1869 assign_reg (cfg, rs, sreg1, val, bank);
1871 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1873 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1874 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1875 g_assert (val >= 0);
1877 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1879 g_assert_not_reached ();
1881 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1883 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1885 /* Skip rest of this section */
1886 dest_sregs [0] = -1;
1889 if (sreg_fixed_masks [0]) {
1891 if (is_global_ireg (sregs [0])) {
1893 * The argument is already in a hard reg, but that reg is
1894 * not usable by this instruction, so allocate a new one.
1896 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1898 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1899 mono_regstate_free_int (rs, val);
1900 dest_sregs [0] = val;
1902 /* Fall through to the dest_sreg1 != -1 case */
1905 sreg_masks [0] &= sreg_fixed_masks [0];
1908 if (dest_sregs [0] != -1) {
1909 sreg_masks [0] = regmask (dest_sregs [0]);
1911 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1912 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1914 if (is_global_ireg (sregs [0])) {
1915 /* The argument is already in a hard reg, need to copy */
1916 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1917 insert_before_ins (bb, ins, copy);
1918 sregs [0] = dest_sregs [0];
1922 if (is_soft_reg (sregs [0], bank)) {
1923 val = rs->vassign [sregs [0]];
1924 prev_sregs [0] = sregs [0];
1928 /* the register gets spilled after this inst */
1932 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1934 * Allocate the same hreg to sreg1 as well so the
1935 * peephole can get rid of the move.
1937 sreg_masks [0] = regmask (ins->dreg);
1940 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1941 /* Allocate the same reg to sreg1 to avoid a copy later */
1942 sreg_masks [0] = regmask (ins->dreg);
1944 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], ®info [sregs [0]], bank);
1945 assign_reg (cfg, rs, sregs [0], val, bank);
1946 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1950 * Need to insert before the instruction since it can
1953 create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1956 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1957 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1958 insert_before_ins (bb, ins, copy);
1959 for (j = 1; j < num_sregs; ++j)
1960 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1961 val = dest_sregs [0];
1967 prev_sregs [0] = -1;
1969 mono_inst_set_src_registers (ins, sregs);
1971 for (j = 1; j < num_sregs; ++j)
1972 sreg_masks [j] &= ~(regmask (sregs [0]));
1974 /* Handle the case when sreg1 is a regpair but dreg is not */
1975 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1976 int reg2 = prev_sregs [0] + 1;
1979 g_assert (prev_sregs [0] > -1);
1980 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1981 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1982 val = rs->vassign [reg2];
1986 /* the register gets spilled after this inst */
1989 val = mono_regstate_alloc_int (rs, mask);
1991 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1993 g_assert_not_reached ();
1996 if (! (mask & (regmask (val)))) {
1997 /* The vreg is already allocated to a wrong hreg */
1999 g_assert_not_reached ();
2001 val = mono_regstate_alloc_int (rs, mask);
2003 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2005 /* Reallocate hreg to the correct register */
2006 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2008 mono_regstate_free_int (rs, rs->vassign [reg2]);
2014 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2015 assign_reg (cfg, rs, reg2, val, bank);
2018 /* Handle dreg==sreg1 */
2019 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2020 MonoInst *sreg2_copy = NULL;
2022 int bank = reg_bank (spec_src1);
2024 if (ins->dreg == sregs [1]) {
2026 * copying sreg1 to dreg could clobber sreg2, so allocate a new
2029 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2031 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2032 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2033 prev_sregs [1] = sregs [1] = reg2;
2035 if (G_UNLIKELY (bank))
2036 mono_regstate_free_general (rs, reg2, bank);
2038 mono_regstate_free_int (rs, reg2);
2041 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2042 /* Copying sreg1_high to dreg could also clobber sreg2 */
2043 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2045 g_assert_not_reached ();
2048 * sreg1 and dest are already allocated to the same regpair by the
2049 * SREG1 allocation code.
2051 g_assert (sregs [0] == ins->dreg);
2052 g_assert (dreg_high == sreg1_high);
2055 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2056 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2057 insert_before_ins (bb, ins, copy);
2060 insert_before_ins (bb, copy, sreg2_copy);
2063 * Need to prevent sreg2 to be allocated to sreg1, since that
2064 * would screw up the previous copy.
2066 sreg_masks [1] &= ~ (regmask (sregs [0]));
2067 /* we set sreg1 to dest as well */
2068 prev_sregs [0] = sregs [0] = ins->dreg;
2069 sreg_masks [1] &= ~ (regmask (ins->dreg));
2071 mono_inst_set_src_registers (ins, sregs);
2074 * TRACK SREG2, 3, ...
2076 for (j = 1; j < num_sregs; ++j) {
2079 bank = sreg_bank (j, spec);
2080 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2081 g_assert_not_reached ();
2083 if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2085 * Argument already in a global hard reg, copy it to the fixed reg, without
2086 * allocating it to the fixed reg.
2088 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2089 insert_before_ins (bb, ins, copy);
2090 sregs [j] = dest_sregs [j];
2091 } else if (is_soft_reg (sregs [j], bank)) {
2092 val = rs->vassign [sregs [j]];
2094 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2096 * The sreg is already allocated to a hreg, but not to the fixed
2097 * reg required by the instruction. Spill the sreg, so it can be
2098 * allocated to the fixed reg by the code below.
2100 /* Currently, this code should only be hit for CAS */
2101 spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2102 val = rs->vassign [sregs [j]];
2108 /* the register gets spilled after this inst */
2111 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], ®info [sregs [j]], bank);
2112 assign_reg (cfg, rs, sregs [j], val, bank);
2113 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2116 * Need to insert before the instruction since it can
2119 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2123 for (k = j + 1; k < num_sregs; ++k)
2124 sreg_masks [k] &= ~ (regmask (sregs [j]));
2127 prev_sregs [j] = -1;
2130 mono_inst_set_src_registers (ins, sregs);
2133 /* Do this only for CAS for now */
2134 for (j = 1; j < num_sregs; ++j) {
2135 int sreg = sregs [j];
2136 int dest_sreg = dest_sregs [j];
2138 if (j == 2 && dest_sreg != -1) {
2141 g_assert (sreg == dest_sreg);
2143 for (k = 0; k < num_sregs; ++k) {
2145 g_assert (sregs [k] != dest_sreg);
2150 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2151 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2152 mono_regstate_free_int (rs, ins->sreg1);
2154 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2155 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2156 mono_regstate_free_int (rs, ins->sreg2);
2159 DEBUG (mono_print_ins_index (i, ins));
2162 // FIXME: Set MAX_FREGS to 8
2163 // FIXME: Optimize generated code
2164 #if MONO_ARCH_USE_FPSTACK
2166 * Make a forward pass over the code, simulating the fp stack, making sure the
2167 * arguments required by the fp opcodes are at the top of the stack.
2170 MonoInst *prev = NULL;
2174 g_assert (num_sregs <= 2);
2176 for (ins = bb->code; ins; ins = ins->next) {
2177 spec = ins_get_spec (ins->opcode);
2179 DEBUG (printf ("processing:"));
2180 DEBUG (mono_print_ins_index (0, ins));
2182 if (ins->opcode == OP_FMOVE) {
2183 /* Do it by renaming the source to the destination on the stack */
2184 // FIXME: Is this correct ?
2185 for (i = 0; i < sp; ++i)
2186 if (fpstack [i] == ins->sreg1)
2187 fpstack [i] = ins->dreg;
2192 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2193 /* Arg1 must be in %st(1) */
2197 while ((i < sp) && (fpstack [i] != ins->sreg1))
2201 if (sp - 1 - i > 0) {
2202 /* First move it to %st(0) */
2203 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2205 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2206 fxch->inst_imm = sp - 1 - i;
2208 mono_bblock_insert_after_ins (bb, prev, fxch);
2211 tmp = fpstack [sp - 1];
2212 fpstack [sp - 1] = fpstack [i];
2216 /* Then move it to %st(1) */
2217 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2219 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2222 mono_bblock_insert_after_ins (bb, prev, fxch);
2225 tmp = fpstack [sp - 1];
2226 fpstack [sp - 1] = fpstack [sp - 2];
2227 fpstack [sp - 2] = tmp;
2230 if (sreg2_is_fp (spec)) {
2233 if (fpstack [sp - 1] != ins->sreg2) {
2237 while ((i < sp) && (fpstack [i] != ins->sreg2))
2241 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2243 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2244 fxch->inst_imm = sp - 1 - i;
2246 mono_bblock_insert_after_ins (bb, prev, fxch);
2249 tmp = fpstack [sp - 1];
2250 fpstack [sp - 1] = fpstack [i];
2257 if (sreg1_is_fp (spec)) {
2260 if (fpstack [sp - 1] != ins->sreg1) {
2264 while ((i < sp) && (fpstack [i] != ins->sreg1))
2268 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2270 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2271 fxch->inst_imm = sp - 1 - i;
2273 mono_bblock_insert_after_ins (bb, prev, fxch);
2276 tmp = fpstack [sp - 1];
2277 fpstack [sp - 1] = fpstack [i];
2284 if (dreg_is_fp (spec)) {
2286 fpstack [sp ++] = ins->dreg;
2289 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2291 for (i = 0; i < sp; ++i)
2292 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2299 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2300 /* Remove remaining items from the fp stack */
2302 * These can remain for example as a result of a dead fmove like in
2303 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2306 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2307 mono_add_ins_to_end (bb, ins);
2316 mono_opcode_to_cond (int opcode)
2326 case OP_COND_EXC_EQ:
2327 case OP_COND_EXC_IEQ:
2334 case OP_COND_EXC_NE_UN:
2335 case OP_COND_EXC_INE_UN:
2336 case OP_CMOV_INE_UN:
2337 case OP_CMOV_LNE_UN:
2358 case OP_COND_EXC_LT:
2359 case OP_COND_EXC_ILT:
2370 case OP_COND_EXC_GT:
2371 case OP_COND_EXC_IGT:
2379 case OP_COND_EXC_LE_UN:
2380 case OP_COND_EXC_ILE_UN:
2381 case OP_CMOV_ILE_UN:
2382 case OP_CMOV_LLE_UN:
2387 case OP_CMOV_IGE_UN:
2388 case OP_CMOV_LGE_UN:
2397 case OP_COND_EXC_LT_UN:
2398 case OP_COND_EXC_ILT_UN:
2399 case OP_CMOV_ILT_UN:
2400 case OP_CMOV_LLT_UN:
2409 case OP_COND_EXC_GT_UN:
2410 case OP_COND_EXC_IGT_UN:
2411 case OP_CMOV_IGT_UN:
2412 case OP_CMOV_LGT_UN:
2415 printf ("%s\n", mono_inst_name (opcode));
2416 g_assert_not_reached ();
2422 mono_negate_cond (CompRelation cond)
2446 g_assert_not_reached ();
2451 mono_opcode_to_type (int opcode, int cmp_opcode)
2453 if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2455 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2457 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2459 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2461 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2463 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2465 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2467 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2469 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2470 switch (cmp_opcode) {
2472 case OP_ICOMPARE_IMM:
2478 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2483 #endif /* DISABLE_JIT */
2486 mono_is_regsize_var (MonoType *t)
2490 t = mono_type_get_underlying_type (t);
2492 case MONO_TYPE_BOOLEAN:
2493 case MONO_TYPE_CHAR:
2503 case MONO_TYPE_FNPTR:
2504 #if SIZEOF_REGISTER == 8
2509 case MONO_TYPE_OBJECT:
2510 case MONO_TYPE_STRING:
2511 case MONO_TYPE_CLASS:
2512 case MONO_TYPE_SZARRAY:
2513 case MONO_TYPE_ARRAY:
2515 case MONO_TYPE_GENERICINST:
2516 if (!mono_type_generic_inst_is_valuetype (t))
2519 case MONO_TYPE_VALUETYPE:
2529 * mono_peephole_ins:
2531 * Perform some architecture independent peephole optimizations.
2534 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2536 MonoInst *last_ins = ins->prev;
2538 switch (ins->opcode) {
2540 /* remove unnecessary multiplication with 1 */
2541 if (ins->inst_imm == 1) {
2542 if (ins->dreg != ins->sreg1)
2543 ins->opcode = OP_MOVE;
2545 MONO_DELETE_INS (bb, ins);
2548 case OP_LOAD_MEMBASE:
2549 case OP_LOADI4_MEMBASE:
2551 * Note: if reg1 = reg2 the load op is removed
2553 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2554 * OP_LOAD_MEMBASE offset(basereg), reg2
2556 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2557 * OP_MOVE reg1, reg2
2559 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2560 last_ins = last_ins->prev;
2562 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2563 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2564 ins->inst_basereg == last_ins->inst_destbasereg &&
2565 ins->inst_offset == last_ins->inst_offset) {
2566 if (ins->dreg == last_ins->sreg1) {
2567 MONO_DELETE_INS (bb, ins);
2570 ins->opcode = OP_MOVE;
2571 ins->sreg1 = last_ins->sreg1;
2575 * Note: reg1 must be different from the basereg in the second load
2576 * Note: if reg1 = reg2 is equal then second load is removed
2578 * OP_LOAD_MEMBASE offset(basereg), reg1
2579 * OP_LOAD_MEMBASE offset(basereg), reg2
2581 * OP_LOAD_MEMBASE offset(basereg), reg1
2582 * OP_MOVE reg1, reg2
2584 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2585 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2586 ins->inst_basereg != last_ins->dreg &&
2587 ins->inst_basereg == last_ins->inst_basereg &&
2588 ins->inst_offset == last_ins->inst_offset) {
2590 if (ins->dreg == last_ins->dreg) {
2591 MONO_DELETE_INS (bb, ins);
2593 ins->opcode = OP_MOVE;
2594 ins->sreg1 = last_ins->dreg;
2597 //g_assert_not_reached ();
2601 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2602 * OP_LOAD_MEMBASE offset(basereg), reg
2604 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2605 * OP_ICONST reg, imm
2607 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2608 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2609 ins->inst_basereg == last_ins->inst_destbasereg &&
2610 ins->inst_offset == last_ins->inst_offset) {
2611 ins->opcode = OP_ICONST;
2612 ins->inst_c0 = last_ins->inst_imm;
2613 g_assert_not_reached (); // check this rule
2617 case OP_LOADI1_MEMBASE:
2618 case OP_LOADU1_MEMBASE:
2620 * Note: if reg1 = reg2 the load op is removed
2622 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2623 * OP_LOAD_MEMBASE offset(basereg), reg2
2625 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2626 * OP_MOVE reg1, reg2
2628 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2629 ins->inst_basereg == last_ins->inst_destbasereg &&
2630 ins->inst_offset == last_ins->inst_offset) {
2631 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2632 ins->sreg1 = last_ins->sreg1;
2635 case OP_LOADI2_MEMBASE:
2636 case OP_LOADU2_MEMBASE:
2638 * Note: if reg1 = reg2 the load op is removed
2640 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2641 * OP_LOAD_MEMBASE offset(basereg), reg2
2643 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2644 * OP_MOVE reg1, reg2
2646 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2647 ins->inst_basereg == last_ins->inst_destbasereg &&
2648 ins->inst_offset == last_ins->inst_offset) {
2649 #if SIZEOF_REGISTER == 8
2650 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2652 /* The definition of OP_PCONV_TO_U2 is wrong */
2653 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2655 ins->sreg1 = last_ins->sreg1;
2665 if (ins->dreg == ins->sreg1) {
2666 MONO_DELETE_INS (bb, ins);
2672 * OP_MOVE sreg, dreg
2673 * OP_MOVE dreg, sreg
2675 if (last_ins && last_ins->opcode == ins->opcode &&
2676 ins->sreg1 == last_ins->dreg &&
2677 ins->dreg == last_ins->sreg1) {
2678 MONO_DELETE_INS (bb, ins);
2682 MONO_DELETE_INS (bb, ins);
2687 #endif /* DISABLE_JIT */