mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30 /*
  31  * Every hardware register belongs to a register type or register bank. bank 0
  32  * contains the int registers, bank 1 contains the fp registers.
  33  * int registers are used 99% of the time, so they are special cased in a lot of
  34  * places.
  35  */
  36
  37 static const int regbank_size [] = {
  38         MONO_MAX_IREGS,
  39         MONO_MAX_FREGS,
  40         MONO_MAX_XREGS
  41 };
  42
  43 static const int regbank_load_ops [] = {
  44         OP_LOAD_MEMBASE,
  45         OP_LOADR8_MEMBASE,
  46         OP_LOADX_MEMBASE
  47 };
  48
  49 static const int regbank_store_ops [] = {
  50         OP_STORE_MEMBASE_REG,
  51         OP_STORER8_MEMBASE_REG,
  52         OP_STOREX_MEMBASE
  53 };
  54
  55 static const int regbank_move_ops [] = {
  56         OP_MOVE,
  57         OP_FMOVE,
  58         OP_XMOVE
  59 };
  60
  61 #define regmask(reg) (((regmask_t)1) << (reg))
  62
  63 static const regmask_t regbank_callee_saved_regs [] = {
  64         MONO_ARCH_CALLEE_SAVED_REGS,
  65         MONO_ARCH_CALLEE_SAVED_FREGS,
  66         MONO_ARCH_CALLEE_SAVED_XREGS,
  67 };
  68
  69 static const regmask_t regbank_callee_regs [] = {
  70         MONO_ARCH_CALLEE_REGS,
  71         MONO_ARCH_CALLEE_FREGS,
  72         MONO_ARCH_CALLEE_XREGS,
  73 };
  74
  75 static const int regbank_spill_var_size[] = {
  76         sizeof (gpointer),
  77         sizeof (double),
  78         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
  79 };
  80
  81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
  82
  83 static inline GSList*
  84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
  85 {
  86         GSList *new_list;
  87         GSList *last;
  88
  89         new_list = mono_mempool_alloc (mp, sizeof (GSList));
  90         new_list->data = data;
  91         new_list->next = NULL;
  92
  93         if (list) {
  94                 last = list;
  95                 while (last->next)
  96                         last = last->next;
  97                 last->next = new_list;
  98
  99                 return list;
 100         } else
 101                 return new_list;
 102 }
 103
 104 static inline void
 105 mono_regstate_assign (MonoRegState *rs)
 106 {
 107         if (rs->next_vreg > rs->vassign_size) {
 108                 g_free (rs->vassign);
 109                 rs->vassign_size = MAX (rs->next_vreg, 256);
 110                 rs->vassign = g_malloc (rs->vassign_size * sizeof (int));
 111         }
 112
 113         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 114         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 115
 116         rs->symbolic [0] = rs->isymbolic;
 117         rs->symbolic [1] = rs->fsymbolic;
 118
 119 #ifdef MONO_ARCH_NEED_SIMD_BANK
 120         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 121         rs->symbolic [2] = rs->xsymbolic;
 122 #endif
 123 }
 124
 125 static inline int
 126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 127 {
 128         regmask_t mask = allow & rs->ifree_mask;
 129
 130 #if defined(__x86_64__) && defined(__GNUC__)
 131  {
 132         guint64 i;
 133
 134         if (mask == 0)
 135                 return -1;
 136
 137         __asm__("bsfq %1,%0\n\t"
 138                         : "=r" (i) : "rm" (mask));
 139
 140         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 141         return i;
 142  }
 143 #else
 144         int i;
 145
 146         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 147                 if (mask & ((regmask_t)1 << i)) {
 148                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 149                         return i;
 150                 }
 151         }
 152         return -1;
 153 #endif
 154 }
 155
 156 static inline void
 157 mono_regstate_free_int (MonoRegState *rs, int reg)
 158 {
 159         if (reg >= 0) {
 160                 rs->ifree_mask |= (regmask_t)1 << reg;
 161                 rs->isymbolic [reg] = 0;
 162         }
 163 }
 164
 165 static inline int
 166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 167 {
 168         int i;
 169         regmask_t mask = allow & rs->free_mask [bank];
 170         for (i = 0; i < regbank_size [bank]; ++i) {
 171                 if (mask & ((regmask_t)1 << i)) {
 172                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 173                         return i;
 174                 }
 175         }
 176         return -1;
 177 }
 178
 179 static inline void
 180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 181 {
 182         if (reg >= 0) {
 183                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 184                 rs->symbolic [bank][reg] = 0;
 185         }
 186 }
 187
 188 const char*
 189 mono_regname_full (int reg, int bank)
 190 {
 191         if (G_UNLIKELY (bank)) {
 192 #if MONO_ARCH_NEED_SIMD_BANK
 193                 if (bank == 2)
 194                         return mono_arch_xregname (reg);
 195 #endif
 196                 g_assert (bank == 1);
 197                 return mono_arch_fregname (reg);
 198         } else {
 199                 return mono_arch_regname (reg);
 200         }
 201 }
 202
 203 void
 204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 205 {
 206         guint32 regpair;
 207
 208         regpair = (((guint32)hreg) << 24) + vreg;
 209         if (G_UNLIKELY (bank)) {
 210                 g_assert (vreg >= regbank_size [bank]);
 211                 g_assert (hreg < regbank_size [bank]);
 212                 call->used_fregs |= 1 << hreg;
 213                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 214         } else {
 215                 g_assert (vreg >= MONO_MAX_IREGS);
 216                 g_assert (hreg < MONO_MAX_IREGS);
 217                 call->used_iregs |= 1 << hreg;
 218                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 219         }
 220 }
 221
 222 static void
 223 resize_spill_info (MonoCompile *cfg, int bank)
 224 {
 225         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 226         int orig_len = cfg->spill_info_len [bank];
 227         int new_len = orig_len ? orig_len * 2 : 16;
 228         MonoSpillInfo *new_info;
 229         int i;
 230
 231         g_assert (bank < MONO_NUM_REGBANKS);
 232
 233         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 234         if (orig_info)
 235                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 236         for (i = orig_len; i < new_len; ++i)
 237                 new_info [i].offset = -1;
 238
 239         cfg->spill_info [bank] = new_info;
 240         cfg->spill_info_len [bank] = new_len;
 241 }
 242
 243 /*
 244  * returns the offset used by spillvar. It allocates a new
 245  * spill variable if necessary.
 246  */
 247 static inline int
 248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 249 {
 250         MonoSpillInfo *info;
 251         int size;
 252
 253         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 254                 while (spillvar >= cfg->spill_info_len [bank])
 255                         resize_spill_info (cfg, bank);
 256         }
 257
 258         /*
 259          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 260          */
 261         info = &cfg->spill_info [bank][spillvar];
 262         if (info->offset == -1) {
 263                 cfg->stack_offset += sizeof (gpointer) - 1;
 264                 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
 265
 266                 g_assert (bank < MONO_NUM_REGBANKS);
 267                 if (G_UNLIKELY (bank))
 268                         size = regbank_spill_var_size [bank];
 269                 else
 270                         size = sizeof (gpointer);
 271
 272                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 273                         cfg->stack_offset += size - 1;
 274                         cfg->stack_offset &= ~(size - 1);
 275                         info->offset = cfg->stack_offset;
 276                         cfg->stack_offset += size;
 277                 } else {
 278                         cfg->stack_offset += size - 1;
 279                         cfg->stack_offset &= ~(size - 1);
 280                         cfg->stack_offset += size;
 281                         info->offset = - cfg->stack_offset;
 282                 }
 283         }
 284
 285         return info->offset;
 286 }
 287
 288 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 289 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 290 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 291 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 292 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 293 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 294
 295 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 296 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 297 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 298 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 299 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 300
 301 #ifndef MONO_ARCH_INST_IS_FLOAT
 302 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 303 #endif
 304
 305 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 306 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 307 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 308 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 309 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 310
 311 #define reg_is_simd(desc) ((desc) == 'x')
 312
 313 #ifdef MONO_ARCH_NEED_SIMD_BANK
 314
 315 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 316
 317 #else
 318
 319 #define reg_bank(desc) reg_is_fp ((desc))
 320
 321 #endif
 322
 323 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 324 #define sreg1_bank(spec) sreg_bank (0, (spec))
 325 #define sreg2_bank(spec) sreg_bank (1, (spec))
 326 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 327
 328 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 329 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 330 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 331 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 332
 333 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 334
 335 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 336 #undef is_global_ireg
 337 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 338 #endif
 339
 340 typedef struct {
 341         int born_in;
 342         int killed_in;
 343         /* Not (yet) used */
 344         //int last_use;
 345         //int prev_use;
 346         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 347 } RegTrack;
 348
 349 #ifndef DISABLE_LOGGING
 350 void
 351 mono_print_ins_index (int i, MonoInst *ins)
 352 {
 353         const char *spec = ins_get_spec (ins->opcode);
 354         int num_sregs, j;
 355         int sregs [MONO_MAX_SRC_REGS];
 356
 357         if (i != -1)
 358                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 359         else
 360                 printf (" %s", mono_inst_name (ins->opcode));
 361         if (spec == MONO_ARCH_CPU_SPEC) {
 362                 /* This is a lowered opcode */
 363                 if (ins->dreg != -1)
 364                         printf (" R%d <-", ins->dreg);
 365                 if (ins->sreg1 != -1)
 366                         printf (" R%d", ins->sreg1);
 367                 if (ins->sreg2 != -1)
 368                         printf (" R%d", ins->sreg2);
 369                 if (ins->sreg3 != -1)
 370                         printf (" R%d", ins->sreg3);
 371
 372                 switch (ins->opcode) {
 373                 case OP_LBNE_UN:
 374                 case OP_LBEQ:
 375                 case OP_LBLT:
 376                 case OP_LBLT_UN:
 377                 case OP_LBGT:
 378                 case OP_LBGT_UN:
 379                 case OP_LBGE:
 380                 case OP_LBGE_UN:
 381                 case OP_LBLE:
 382                 case OP_LBLE_UN:
 383                         if (!(ins->flags & MONO_INST_BRLABEL)) {
 384                                 if (!ins->inst_false_bb)
 385                                         printf (" [B%d]", ins->inst_true_bb->block_num);
 386                                 else
 387                                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 388                         }
 389                         break;
 390                 case OP_PHI:
 391                 case OP_VPHI:
 392                 case OP_XPHI:
 393                 case OP_FPHI: {
 394                         int i;
 395                         printf (" [%d (", (int)ins->inst_c0);
 396                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 397                                 if (i)
 398                                         printf (", ");
 399                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 400                         }
 401                         printf (")]");
 402                         break;
 403                 }
 404                 case OP_LDADDR:
 405                 case OP_OUTARG_VTRETADDR:
 406                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 407                         break;
 408                 case OP_REGOFFSET:
 409                         printf (" + 0x%lx", (long)ins->inst_offset);
 410                         break;
 411                 default:
 412                         break;
 413                 }
 414
 415                 printf ("\n");
 416                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 417                 return;
 418         }
 419
 420         if (spec [MONO_INST_DEST]) {
 421                 int bank = dreg_bank (spec);
 422                 if (is_soft_reg (ins->dreg, bank)) {
 423                         if (spec [MONO_INST_DEST] == 'b') {
 424                                 if (ins->inst_offset == 0)
 425                                         printf (" [R%d] <-", ins->dreg);
 426                                 else
 427                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 428                         }
 429                         else
 430                                 printf (" R%d <-", ins->dreg);
 431                 } else if (spec [MONO_INST_DEST] == 'b') {
 432                         if (ins->inst_offset == 0)
 433                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 434                         else
 435                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 436                 } else
 437                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 438         }
 439         if (spec [MONO_INST_SRC1]) {
 440                 int bank = sreg1_bank (spec);
 441                 if (is_soft_reg (ins->sreg1, bank)) {
 442                         if (spec [MONO_INST_SRC1] == 'b')
 443                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 444                         else
 445                                 printf (" R%d", ins->sreg1);
 446                 } else if (spec [MONO_INST_SRC1] == 'b')
 447                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 448                 else
 449                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 450         }
 451         num_sregs = mono_inst_get_src_registers (ins, sregs);
 452         for (j = 1; j < num_sregs; ++j) {
 453                 int bank = sreg_bank (j, spec);
 454                 if (is_soft_reg (sregs [j], bank))
 455                         printf (" R%d", sregs [j]);
 456                 else
 457                         printf (" %s", mono_regname_full (sregs [j], bank));
 458         }
 459
 460         switch (ins->opcode) {
 461         case OP_ICONST:
 462                 printf (" [%d]", (int)ins->inst_c0);
 463                 break;
 464 #if defined(__i386__) || defined(__x86_64__)
 465         case OP_X86_PUSH_IMM:
 466 #endif
 467         case OP_ICOMPARE_IMM:
 468         case OP_COMPARE_IMM:
 469         case OP_IADD_IMM:
 470         case OP_ISUB_IMM:
 471         case OP_IAND_IMM:
 472         case OP_IOR_IMM:
 473         case OP_IXOR_IMM:
 474                 printf (" [%d]", (int)ins->inst_imm);
 475                 break;
 476         case OP_ADD_IMM:
 477         case OP_LADD_IMM:
 478                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 479                 break;
 480         case OP_I8CONST:
 481                 printf (" [%lld]", (long long)ins->inst_l);
 482                 break;
 483         case OP_R8CONST:
 484                 printf (" [%f]", *(double*)ins->inst_p0);
 485                 break;
 486         case OP_R4CONST:
 487                 printf (" [%f]", *(float*)ins->inst_p0);
 488                 break;
 489         case CEE_CALL:
 490         case CEE_CALLVIRT:
 491         case OP_CALL:
 492         case OP_CALL_MEMBASE:
 493         case OP_CALL_REG:
 494         case OP_FCALL:
 495         case OP_FCALLVIRT:
 496         case OP_LCALL:
 497         case OP_LCALLVIRT:
 498         case OP_VCALL:
 499         case OP_VCALLVIRT:
 500         case OP_VCALL_REG:
 501         case OP_VCALL_MEMBASE:
 502         case OP_VCALL2:
 503         case OP_VCALL2_REG:
 504         case OP_VCALL2_MEMBASE:
 505         case OP_VOIDCALL:
 506         case OP_VOIDCALL_MEMBASE:
 507         case OP_VOIDCALLVIRT: {
 508                 MonoCallInst *call = (MonoCallInst*)ins;
 509                 GSList *list;
 510
 511                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 512                         /*
 513                          * These are lowered opcodes, but they are in the .md files since the old
 514                          * JIT passes them to backends.
 515                          */
 516                         if (ins->dreg != -1)
 517                                 printf (" R%d <-", ins->dreg);
 518                 }
 519
 520                 if (call->method) {
 521                         char *full_name = mono_method_full_name (call->method, TRUE);
 522                         printf (" [%s]", full_name);
 523                         g_free (full_name);
 524                 } else if (call->fptr) {
 525                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 526                         if (info)
 527                                 printf (" [%s]", info->name);
 528                 }
 529
 530                 list = call->out_ireg_args;
 531                 while (list) {
 532                         guint32 regpair;
 533                         int reg, hreg;
 534
 535                         regpair = (guint32)(gssize)(list->data);
 536                         hreg = regpair >> 24;
 537                         reg = regpair & 0xffffff;
 538
 539                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 540
 541                         list = g_slist_next (list);
 542                 }
 543                 break;
 544         }
 545         case OP_BR:
 546         case OP_CALL_HANDLER:
 547                 printf (" [B%d]", ins->inst_target_bb->block_num);
 548                 break;
 549         case CEE_BNE_UN:
 550         case CEE_BEQ:
 551         case CEE_BLT:
 552         case CEE_BLT_UN:
 553         case CEE_BGT:
 554         case CEE_BGT_UN:
 555         case CEE_BGE:
 556         case CEE_BGE_UN:
 557         case CEE_BLE:
 558         case CEE_BLE_UN:
 559         case OP_IBNE_UN:
 560         case OP_IBEQ:
 561         case OP_IBLT:
 562         case OP_IBLT_UN:
 563         case OP_IBGT:
 564         case OP_IBGT_UN:
 565         case OP_IBGE:
 566         case OP_IBGE_UN:
 567         case OP_IBLE:
 568         case OP_IBLE_UN:
 569         case OP_LBNE_UN:
 570         case OP_LBEQ:
 571         case OP_LBLT:
 572         case OP_LBLT_UN:
 573         case OP_LBGT:
 574         case OP_LBGT_UN:
 575         case OP_LBGE:
 576         case OP_LBGE_UN:
 577         case OP_LBLE:
 578         case OP_LBLE_UN:
 579                 if (!(ins->flags & MONO_INST_BRLABEL)) {
 580                         if (!ins->inst_false_bb)
 581                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 582                         else
 583                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 584                 }
 585                 break;
 586         case OP_LIVERANGE_START:
 587         case OP_LIVERANGE_END:
 588                 printf (" R%d", (int)ins->inst_c1);
 589                 break;
 590         default:
 591                 break;
 592         }
 593
 594         if (spec [MONO_INST_CLOB])
 595                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 596         printf ("\n");
 597 }
 598
 599 static void
 600 print_regtrack (RegTrack *t, int num)
 601 {
 602         int i;
 603         char buf [32];
 604         const char *r;
 605
 606         for (i = 0; i < num; ++i) {
 607                 if (!t [i].born_in)
 608                         continue;
 609                 if (i >= MONO_MAX_IREGS) {
 610                         g_snprintf (buf, sizeof(buf), "R%d", i);
 611                         r = buf;
 612                 } else
 613                         r = mono_arch_regname (i);
 614                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 615         }
 616 }
 617 #else
 618 void
 619 mono_print_ins_index (int i, MonoInst *ins)
 620 {
 621 }
 622 #endif /* DISABLE_LOGGING */
 623
 624 void
 625 mono_print_ins (MonoInst *ins)
 626 {
 627         mono_print_ins_index (-1, ins);
 628 }
 629
 630 static inline void
 631 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 632 {
 633         /*
 634          * If this function is called multiple times, the new instructions are inserted
 635          * in the proper order.
 636          */
 637         mono_bblock_insert_before_ins (bb, ins, to_insert);
 638 }
 639
 640 static inline void
 641 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 642 {
 643         /*
 644          * If this function is called multiple times, the new instructions are inserted in
 645          * proper order.
 646          */
 647         mono_bblock_insert_after_ins (bb, *last, to_insert);
 648
 649         *last = to_insert;
 650 }
 651
 652 /*
 653  * Force the spilling of the variable in the symbolic register 'reg'.
 654  */
 655 static int
 656 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 657 {
 658         MonoInst *load;
 659         int i, sel, spill;
 660         int *symbolic;
 661         MonoRegState *rs = cfg->rs;
 662
 663         symbolic = rs->symbolic [bank];
 664         sel = rs->vassign [reg];
 665
 666         /*i = rs->isymbolic [sel];
 667         g_assert (i == reg);*/
 668         i = reg;
 669         spill = ++cfg->spill_count;
 670         rs->vassign [i] = -spill - 1;
 671         if (G_UNLIKELY (bank))
 672                 mono_regstate_free_general (rs, sel, bank);
 673         else
 674                 mono_regstate_free_int (rs, sel);
 675         /* we need to create a spill var and insert a load to sel after the current instruction */
 676         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 677         load->dreg = sel;
 678         load->inst_basereg = cfg->frame_reg;
 679         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 680         insert_after_ins (bb, ins, last, load);
 681         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 682         if (G_UNLIKELY (bank))
 683                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 684         else
 685                 i = mono_regstate_alloc_int (rs, regmask (sel));
 686         g_assert (i == sel);
 687
 688         return sel;
 689 }
 690
 691 /* This isn't defined on older glib versions and on some platforms */
 692 #ifndef G_GUINT64_FORMAT
 693 #define G_GUINT64_FORMAT "ul"
 694 #endif
 695
 696 static int
 697 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 698 {
 699         MonoInst *load;
 700         int i, sel, spill, num_sregs;
 701         int sregs [MONO_MAX_SRC_REGS];
 702         int *symbolic;
 703         MonoRegState *rs = cfg->rs;
 704
 705         symbolic = rs->symbolic [bank];
 706
 707         g_assert (bank < MONO_NUM_REGBANKS);
 708
 709         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 710         /* exclude the registers in the current instruction */
 711         num_sregs = mono_inst_get_src_registers (ins, sregs);
 712         for (i = 0; i < num_sregs; ++i) {
 713                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 714                         if (is_soft_reg (sregs [i], bank))
 715                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 716                         else
 717                                 regmask &= ~ (regmask (sregs [i]));
 718                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 719                 }
 720         }
 721         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 722                 regmask &= ~ (regmask (ins->dreg));
 723                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 724         }
 725
 726         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 727         g_assert (regmask); /* need at least a register we can free */
 728         sel = 0;
 729         /* we should track prev_use and spill the register that's farther */
 730         if (G_UNLIKELY (bank)) {
 731                 for (i = 0; i < regbank_size [bank]; ++i) {
 732                         if (regmask & (regmask (i))) {
 733                                 sel = i;
 734                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 735                                 break;
 736                         }
 737                 }
 738
 739                 i = rs->symbolic [bank] [sel];
 740                 spill = ++cfg->spill_count;
 741                 rs->vassign [i] = -spill - 1;
 742                 mono_regstate_free_general (rs, sel, bank);
 743         }
 744         else {
 745                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 746                         if (regmask & (regmask (i))) {
 747                                 sel = i;
 748                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 749                                 break;
 750                         }
 751                 }
 752
 753                 i = rs->isymbolic [sel];
 754                 spill = ++cfg->spill_count;
 755                 rs->vassign [i] = -spill - 1;
 756                 mono_regstate_free_int (rs, sel);
 757         }
 758
 759         /* we need to create a spill var and insert a load to sel after the current instruction */
 760         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 761         load->dreg = sel;
 762         load->inst_basereg = cfg->frame_reg;
 763         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 764         insert_after_ins (bb, ins, last, load);
 765         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 766         if (G_UNLIKELY (bank))
 767                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 768         else
 769                 i = mono_regstate_alloc_int (rs, regmask (sel));
 770         g_assert (i == sel);
 771
 772         return sel;
 773 }
 774
 775 static void
 776 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 777 {
 778         if (G_UNLIKELY (bank)) {
 779                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 780                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 781                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 782                         mono_regstate_free_general (cfg->rs, hreg, bank);
 783                 }
 784         }
 785         else {
 786                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 787                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 788                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 789                         mono_regstate_free_int (cfg->rs, hreg);
 790                 }
 791         }
 792 }
 793
 794 static MonoInst*
 795 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 796 {
 797         MonoInst *copy;
 798
 799         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 800
 801         copy->dreg = dest;
 802         copy->sreg1 = src;
 803         copy->cil_code = ip;
 804         if (ins) {
 805                 mono_bblock_insert_after_ins (bb, ins, copy);
 806                 *last = copy;
 807         }
 808         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 809         return copy;
 810 }
 811
 812 static MonoInst*
 813 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 814 {
 815         MonoInst *store;
 816         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 817         store->sreg1 = reg;
 818         store->inst_destbasereg = cfg->frame_reg;
 819         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 820         if (ins) {
 821                 mono_bblock_insert_after_ins (bb, ins, store);
 822                 *last = store;
 823         }
 824         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 825         return store;
 826 }
 827
 828 /* flags used in reginfo->flags */
 829 enum {
 830         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 831         MONO_FP_NEEDS_SPILL                     = regmask (1),
 832         MONO_FP_NEEDS_LOAD                      = regmask (2)
 833 };
 834
 835 static inline int
 836 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 837 {
 838         int val;
 839
 840         if (info && info->preferred_mask) {
 841                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 842                 if (val >= 0) {
 843                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 844                         return val;
 845                 }
 846         }
 847
 848         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 849         if (val < 0)
 850                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 851
 852         return val;
 853 }
 854
 855 static inline int
 856 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 857 {
 858         int val;
 859
 860         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 861
 862         if (val < 0)
 863                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 864
 865         return val;
 866 }
 867
 868 static inline int
 869 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 870 {
 871         if (G_UNLIKELY (bank))
 872                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 873         else
 874                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 875 }
 876
 877 static inline void
 878 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 879 {
 880         if (G_UNLIKELY (bank)) {
 881                 g_assert (reg >= regbank_size [bank]);
 882                 g_assert (hreg < regbank_size [bank]);
 883                 g_assert (! is_global_freg (hreg));
 884
 885                 rs->vassign [reg] = hreg;
 886                 rs->symbolic [bank] [hreg] = reg;
 887                 rs->free_mask [bank] &= ~ (regmask (hreg));
 888         }
 889         else {
 890                 g_assert (reg >= MONO_MAX_IREGS);
 891                 g_assert (hreg < MONO_MAX_IREGS);
 892 #ifndef __arm__
 893                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 894                 g_assert (! is_global_ireg (hreg));
 895 #endif
 896
 897                 rs->vassign [reg] = hreg;
 898                 rs->isymbolic [hreg] = reg;
 899                 rs->ifree_mask &= ~ (regmask (hreg));
 900         }
 901 }
 902
 903 static inline regmask_t
 904 get_callee_mask (const char spec)
 905 {
 906         if (G_UNLIKELY (reg_bank (spec)))
 907                 return regbank_callee_regs [reg_bank (spec)];
 908         return MONO_ARCH_CALLEE_REGS;
 909 }
 910
 911 static gint8 desc_to_fixed_reg [256];
 912 static gboolean desc_to_fixed_reg_inited = FALSE;
 913
 914 /*
 915  * Local register allocation.
 916  * We first scan the list of instructions and we save the liveness info of
 917  * each register (when the register is first used, when it's value is set etc.).
 918  * We also reverse the list of instructions because assigning registers backwards allows
 919  * for more tricks to be used.
 920  */
 921 void
 922 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 923 {
 924         MonoInst *ins, *prev, *last;
 925         MonoInst **tmp;
 926         MonoRegState *rs = cfg->rs;
 927         int i, j, val, max;
 928         RegTrack *reginfo;
 929         const char *spec;
 930         unsigned char spec_src1, spec_dest;
 931         int bank = 0;
 932 #if MONO_ARCH_USE_FPSTACK
 933         gboolean has_fp = FALSE;
 934         int fpstack [8];
 935         int sp = 0;
 936 #endif
 937         int num_sregs;
 938         int sregs [MONO_MAX_SRC_REGS];
 939
 940         if (!bb->code)
 941                 return;
 942
 943         if (!desc_to_fixed_reg_inited) {
 944                 for (i = 0; i < 256; ++i)
 945                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
 946                 desc_to_fixed_reg_inited = TRUE;
 947         }
 948
 949         rs->next_vreg = bb->max_vreg;
 950         mono_regstate_assign (rs);
 951
 952         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
 953         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
 954                 rs->free_mask [i] = regbank_callee_regs [i];
 955
 956         max = rs->next_vreg;
 957
 958         if (cfg->reginfo && cfg->reginfo_len < max)
 959                 cfg->reginfo = NULL;
 960
 961         reginfo = cfg->reginfo;
 962         if (!reginfo) {
 963                 cfg->reginfo_len = MAX (1024, max * 2);
 964                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
 965         }
 966         else
 967                 g_assert (cfg->reginfo_len >= rs->next_vreg);
 968
 969         if (cfg->verbose_level > 1) {
 970                 /* print_regtrack reads the info of all variables */
 971                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
 972         }
 973
 974         /*
 975          * For large methods, next_vreg can be very large, so g_malloc0 time can
 976          * be prohibitive. So we manually init the reginfo entries used by the
 977          * bblock.
 978          */
 979         for (ins = bb->code; ins; ins = ins->next) {
 980                 spec = ins_get_spec (ins->opcode);
 981
 982                 if ((ins->dreg != -1) && (ins->dreg < max)) {
 983                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
 984 #if SIZEOF_REGISTER == 4
 985                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
 986                                 /**
 987                                  * In the new IR, the two vregs of the regpair do not alias the
 988                                  * original long vreg. shift the vreg here so the rest of the
 989                                  * allocator doesn't have to care about it.
 990                                  */
 991                                 ins->dreg ++;
 992                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
 993                         }
 994 #endif
 995                 }
 996
 997                 num_sregs = mono_inst_get_src_registers (ins, sregs);
 998                 for (j = 0; j < num_sregs; ++j) {
 999                         g_assert (sregs [j] != -1);
1000                         if (sregs [j] < max) {
1001                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1002 #if SIZEOF_REGISTER == 4
1003                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1004                                         sregs [j]++;
1005                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1006                                 }
1007 #endif
1008                         }
1009                 }
1010                 mono_inst_set_src_registers (ins, sregs);
1011         }
1012
1013         /*if (cfg->opt & MONO_OPT_COPYPROP)
1014                 local_copy_prop (cfg, ins);*/
1015
1016         i = 1;
1017         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1018         /* forward pass on the instructions to collect register liveness info */
1019         MONO_BB_FOR_EACH_INS (bb, ins) {
1020                 spec = ins_get_spec (ins->opcode);
1021                 spec_dest = spec [MONO_INST_DEST];
1022
1023                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1024                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1025                 }
1026
1027                 DEBUG (mono_print_ins_index (i, ins));
1028
1029                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1030
1031 #if MONO_ARCH_USE_FPSTACK
1032                 if (dreg_is_fp (spec)) {
1033                         has_fp = TRUE;
1034                 } else {
1035                         for (j = 0; j < num_sregs; ++j) {
1036                                 if (sreg_is_fp (j, spec))
1037                                         has_fp = TRUE;
1038                         }
1039                 }
1040 #endif
1041
1042                 for (j = 0; j < num_sregs; ++j) {
1043                         int sreg = sregs [j];
1044                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1045                         if (sreg_spec) {
1046                                 bank = sreg_bank (j, spec);
1047                                 g_assert (sreg != -1);
1048                                 if (is_soft_reg (sreg, bank))
1049                                         /* This means the vreg is not local to this bb */
1050                                         g_assert (reginfo [sreg].born_in > 0);
1051                                 rs->vassign [sreg] = -1;
1052                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1053                                 //reginfo [ins->sreg2].last_use = i;
1054                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1055                                         /* The virtual register is allocated sequentially */
1056                                         rs->vassign [sreg + 1] = -1;
1057                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1058                                         //reginfo [ins->sreg2 + 1].last_use = i;
1059                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1060                                                 reginfo [sreg + 1].born_in = i;
1061                                 }
1062                         } else {
1063                                 sregs [j] = -1;
1064                         }
1065                 }
1066                 mono_inst_set_src_registers (ins, sregs);
1067
1068                 if (spec_dest) {
1069                         int dest_dreg;
1070
1071                         bank = dreg_bank (spec);
1072                         if (spec_dest != 'b') /* it's not just a base register */
1073                                 reginfo [ins->dreg].killed_in = i;
1074                         g_assert (ins->dreg != -1);
1075                         rs->vassign [ins->dreg] = -1;
1076                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1077                         //reginfo [ins->dreg].last_use = i;
1078                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1079                                 reginfo [ins->dreg].born_in = i;
1080
1081                         dest_dreg = desc_to_fixed_reg [spec_dest];
1082                         if (dest_dreg != -1)
1083                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1084
1085 #ifdef MONO_ARCH_INST_FIXED_MASK
1086                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1087 #endif
1088
1089                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1090                                 /* The virtual register is allocated sequentially */
1091                                 rs->vassign [ins->dreg + 1] = -1;
1092                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1093                                 //reginfo [ins->dreg + 1].last_use = i;
1094                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1095                                         reginfo [ins->dreg + 1].born_in = i;
1096                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1097                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1098                         }
1099                 } else {
1100                         ins->dreg = -1;
1101                 }
1102
1103                 if (spec [MONO_INST_CLOB] == 'c') {
1104                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1105
1106                         MonoCallInst *call = (MonoCallInst*)ins;
1107                         GSList *list;
1108
1109                         list = call->out_ireg_args;
1110                         if (list) {
1111                                 while (list) {
1112                                         guint32 regpair;
1113                                         int reg, hreg;
1114
1115                                         regpair = (guint32)(gssize)(list->data);
1116                                         hreg = regpair >> 24;
1117                                         reg = regpair & 0xffffff;
1118
1119                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1120                                         //reginfo [reg].last_use = i;
1121
1122                                         list = g_slist_next (list);
1123                                 }
1124                         }
1125
1126                         list = call->out_freg_args;
1127                         if (list) {
1128                                 while (list) {
1129                                         guint32 regpair;
1130                                         int reg, hreg;
1131
1132                                         regpair = (guint32)(gssize)(list->data);
1133                                         hreg = regpair >> 24;
1134                                         reg = regpair & 0xffffff;
1135
1136                                         list = g_slist_next (list);
1137                                 }
1138                         }
1139                 }
1140
1141                 ++i;
1142         }
1143
1144         tmp = &last;
1145
1146         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1147         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1148                 int prev_dreg, clob_dreg;
1149                 int dest_dreg, clob_reg;
1150                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1151                 int dreg_high, sreg1_high;
1152                 regmask_t dreg_mask, mask;
1153                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1154                 regmask_t dreg_fixed_mask;
1155                 const unsigned char *ip;
1156                 --i;
1157                 spec = ins_get_spec (ins->opcode);
1158                 spec_src1 = spec [MONO_INST_SRC1];
1159                 spec_dest = spec [MONO_INST_DEST];
1160                 prev_dreg = -1;
1161                 clob_dreg = -1;
1162                 clob_reg = -1;
1163                 dest_dreg = -1;
1164                 dreg_high = -1;
1165                 sreg1_high = -1;
1166                 dreg_mask = get_callee_mask (spec_dest);
1167                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1168                         prev_sregs [j] = -1;
1169                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1170                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1171 #ifdef MONO_ARCH_INST_FIXED_MASK
1172                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1173 #else
1174                         sreg_fixed_masks [j] = 0;
1175 #endif
1176                 }
1177
1178                 DEBUG (printf ("processing:"));
1179                 DEBUG (mono_print_ins_index (i, ins));
1180
1181                 ip = ins->cil_code;
1182
1183                 last = ins;
1184
1185                 /*
1186                  * FIXED REGS
1187                  */
1188                 dest_dreg = desc_to_fixed_reg [spec_dest];
1189                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1190                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1191
1192 #ifdef MONO_ARCH_INST_FIXED_MASK
1193                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1194 #else
1195                 dreg_fixed_mask = 0;
1196 #endif
1197
1198                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1199
1200                 /*
1201                  * TRACK FIXED SREG2, 3, ...
1202                  */
1203                 for (j = 1; j < num_sregs; ++j) {
1204                         int sreg = sregs [j];
1205                         int dest_sreg = dest_sregs [j];
1206                         if (dest_sreg != -1) {
1207                                 if (rs->ifree_mask & (regmask (dest_sreg))) {
1208                                         if (is_global_ireg (sreg)) {
1209                                                 int k;
1210                                                 /* Argument already in hard reg, need to copy */
1211                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1212                                                 insert_before_ins (bb, ins, copy);
1213                                                 for (k = 0; k < num_sregs; ++k) {
1214                                                         if (k != j)
1215                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1216                                                 }
1217                                         }
1218                                         else {
1219                                                 val = rs->vassign [sreg];
1220                                                 if (val == -1) {
1221                                                         DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1222                                                         assign_reg (cfg, rs, sreg, dest_sreg, 0);
1223                                                 } else if (val < -1) {
1224                                                         /* FIXME: */
1225                                                         g_assert_not_reached ();
1226                                                 } else {
1227                                                         /* Argument already in hard reg, need to copy */
1228                                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1229                                                         insert_before_ins (bb, ins, copy);
1230                                                 }
1231                                         }
1232                                 } else {
1233                                         gboolean need_spill = TRUE;
1234                                         gboolean need_assign = TRUE;
1235                                         int k;
1236
1237                                         dreg_mask &= ~ (regmask (dest_sreg));
1238                                         for (k = 0; k < num_sregs; ++k) {
1239                                                 if (k != j)
1240                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1241                                         }
1242
1243                                         /*
1244                                          * First check if dreg is assigned to dest_sreg2, since we
1245                                          * can't spill a dreg.
1246                                          */
1247                                         val = rs->vassign [ins->dreg];
1248                                         if (val == dest_sreg && ins->dreg != sreg) {
1249                                                 /*
1250                                                  * the destination register is already assigned to
1251                                                  * dest_sreg2: we need to allocate another register for it
1252                                                  * and then copy from this to dest_sreg2.
1253                                                  */
1254                                                 int new_dest;
1255                                                 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1256                                                 g_assert (new_dest >= 0);
1257                                                 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1258
1259                                                 prev_dreg = ins->dreg;
1260                                                 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1261                                                 clob_dreg = ins->dreg;
1262                                                 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1263                                                 mono_regstate_free_int (rs, dest_sreg);
1264                                                 need_spill = FALSE;
1265                                         }
1266
1267                                         if (is_global_ireg (sreg)) {
1268                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1269                                                 insert_before_ins (bb, ins, copy);
1270                                                 need_assign = FALSE;
1271                                         }
1272                                         else {
1273                                                 val = rs->vassign [sreg];
1274                                                 if (val == dest_sreg) {
1275                                                         /* sreg2 is already assigned to the correct register */
1276                                                         need_spill = FALSE;
1277                                                 } else if (val < -1) {
1278                                                         /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1279                                                 } else if (val >= 0) {
1280                                                         /* sreg2 already assigned to another register */
1281                                                         /*
1282                                                          * We couldn't emit a copy from val to dest_sreg2, because
1283                                                          * val might be spilled later while processing this
1284                                                          * instruction. So we spill sreg2 so it can be allocated to
1285                                                          * dest_sreg2.
1286                                                          */
1287                                                         DEBUG (printf ("\tforced spill of R%d\n", sreg));
1288                                                         free_up_reg (cfg, bb, tmp, ins, val, 0);
1289                                                 }
1290                                         }
1291
1292                                         if (need_spill) {
1293                                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg]));
1294                                                 free_up_reg (cfg, bb, tmp, ins, dest_sreg, 0);
1295                                         }
1296
1297                                         if (need_assign) {
1298                                                 if (rs->vassign [sreg] < -1) {
1299                                                         MonoInst *store;
1300                                                         int spill;
1301
1302                                                         /* Need to emit a spill store */
1303                                                         spill = - rs->vassign [sreg] - 1;
1304                                                         store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
1305                                                         insert_before_ins (bb, ins, store);
1306                                                 }
1307                                                 /* force-set sreg2 */
1308                                                 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1309                                         }
1310                                 }
1311                                 sregs [j] = dest_sreg;
1312                         }
1313                 }
1314                 mono_inst_set_src_registers (ins, sregs);
1315
1316                 /*
1317                  * TRACK DREG
1318                  */
1319                 bank = dreg_bank (spec);
1320                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1321                         prev_dreg = ins->dreg;
1322                 }
1323
1324                 if (spec_dest == 'b') {
1325                         /*
1326                          * The dest reg is read by the instruction, not written, so
1327                          * avoid allocating sreg1/sreg2 to the same reg.
1328                          */
1329                         if (dest_sregs [0] != -1)
1330                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1331                         for (j = 1; j < num_sregs; ++j) {
1332                                 if (dest_sregs [j] != -1)
1333                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1334                         }
1335
1336                         val = rs->vassign [ins->dreg];
1337                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1338                                 /* DREG is already allocated to a register needed for sreg1 */
1339                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1340                                 mono_regstate_free_int (rs, val);
1341                         }
1342                 }
1343
1344                 /*
1345                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1346                  * various complex situations.
1347                  */
1348                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1349                         guint32 dreg2, dest_dreg2;
1350
1351                         g_assert (is_soft_reg (ins->dreg, bank));
1352
1353                         if (dest_dreg != -1) {
1354                                 if (rs->vassign [ins->dreg] != dest_dreg)
1355                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1356
1357                                 dreg2 = ins->dreg + 1;
1358                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1359                                 if (dest_dreg2 != -1) {
1360                                         if (rs->vassign [dreg2] != dest_dreg2)
1361                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1362                                 }
1363                         }
1364                 }
1365
1366                 if (dreg_fixed_mask) {
1367                         g_assert (!bank);
1368                         if (is_global_ireg (ins->dreg)) {
1369                                 /*
1370                                  * The argument is already in a hard reg, but that reg is
1371                                  * not usable by this instruction, so allocate a new one.
1372                                  */
1373                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1374                                 if (val < 0)
1375                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1376                                 mono_regstate_free_int (rs, val);
1377                                 dest_dreg = val;
1378
1379                                 /* Fall through */
1380                         }
1381                         else
1382                                 dreg_mask &= dreg_fixed_mask;
1383                 }
1384
1385                 if (is_soft_reg (ins->dreg, bank)) {
1386                         val = rs->vassign [ins->dreg];
1387
1388                         if (val < 0) {
1389                                 int spill = 0;
1390                                 if (val < -1) {
1391                                         /* the register gets spilled after this inst */
1392                                         spill = -val -1;
1393                                 }
1394                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1395                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1396                                 if (spill)
1397                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1398                         }
1399
1400                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1401                         ins->dreg = val;
1402                 }
1403
1404                 /* Handle regpairs */
1405                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1406                         int reg2 = prev_dreg + 1;
1407
1408                         g_assert (!bank);
1409                         g_assert (prev_dreg > -1);
1410                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1411                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1412 #ifdef __i386__
1413                         /* bug #80489 */
1414                         mask &= ~regmask (X86_ECX);
1415 #endif
1416                         val = rs->vassign [reg2];
1417                         if (val < 0) {
1418                                 int spill = 0;
1419                                 if (val < -1) {
1420                                         /* the register gets spilled after this inst */
1421                                         spill = -val -1;
1422                                 }
1423                                 val = mono_regstate_alloc_int (rs, mask);
1424                                 if (val < 0)
1425                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1426                                 if (spill)
1427                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1428                         }
1429                         else {
1430                                 if (! (mask & (regmask (val)))) {
1431                                         val = mono_regstate_alloc_int (rs, mask);
1432                                         if (val < 0)
1433                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1434
1435                                         /* Reallocate hreg to the correct register */
1436                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1437
1438                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1439                                 }
1440                         }
1441
1442                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1443                         assign_reg (cfg, rs, reg2, val, bank);
1444
1445                         dreg_high = val;
1446                         ins->backend.reg3 = val;
1447
1448                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1449                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1450                                 mono_regstate_free_int (rs, val);
1451                         }
1452                 }
1453
1454                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1455                         /*
1456                          * In theory, we could free up the hreg even if the vreg is alive,
1457                          * but branches inside bblocks force us to assign the same hreg
1458                          * to a vreg every time it is encountered.
1459                          */
1460                         int dreg = rs->vassign [prev_dreg];
1461                         g_assert (dreg >= 0);
1462                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1463                         if (G_UNLIKELY (bank))
1464                                 mono_regstate_free_general (rs, dreg, bank);
1465                         else
1466                                 mono_regstate_free_int (rs, dreg);
1467                         rs->vassign [prev_dreg] = -1;
1468                 }
1469
1470                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1471                         /* this instruction only outputs to dest_dreg, need to copy */
1472                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1473                         ins->dreg = dest_dreg;
1474
1475                         if (G_UNLIKELY (bank)) {
1476                                 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1477                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1478                         }
1479                         else {
1480                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1481                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1482                         }
1483                 }
1484
1485                 if (spec_dest == 'b') {
1486                         /*
1487                          * The dest reg is read by the instruction, not written, so
1488                          * avoid allocating sreg1/sreg2 to the same reg.
1489                          */
1490                         for (j = 0; j < num_sregs; ++j)
1491                                 if (!sreg_bank (j, spec))
1492                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1493                 }
1494
1495                 /*
1496                  * TRACK CLOBBERING
1497                  */
1498                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1499                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1500                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1501                         mono_regstate_free_int (rs, clob_reg);
1502                 }
1503
1504                 if (spec [MONO_INST_CLOB] == 'c') {
1505                         int j, s, dreg, dreg2, cur_bank;
1506                         guint64 clob_mask;
1507
1508                         clob_mask = MONO_ARCH_CALLEE_REGS;
1509
1510                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1511                                 /*
1512                                  * Need to avoid spilling the dreg since the dreg is not really
1513                                  * clobbered by the call.
1514                                  */
1515                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1516                                         dreg = rs->vassign [prev_dreg];
1517                                 else
1518                                         dreg = -1;
1519
1520                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1521                                         dreg2 = rs->vassign [prev_dreg + 1];
1522                                 else
1523                                         dreg2 = -1;
1524
1525                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1526                                         s = regmask (j);
1527                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1528                                                 if ((j != dreg) && (j != dreg2))
1529                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1530                                                 else if (rs->isymbolic [j])
1531                                                         /* The hreg is assigned to the dreg of this instruction */
1532                                                         rs->vassign [rs->isymbolic [j]] = -1;
1533                                                 mono_regstate_free_int (rs, j);
1534                                         }
1535                                 }
1536                         }
1537
1538                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1539                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1540                                         clob_mask = regbank_callee_regs [cur_bank];
1541                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1542                                                 dreg = rs->vassign [prev_dreg];
1543                                         else
1544                                                 dreg = -1;
1545
1546                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1547                                                 s = regmask (j);
1548                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1549                                                         if (j != dreg)
1550                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1551                                                         else if (rs->symbolic [cur_bank] [j])
1552                                                                 /* The hreg is assigned to the dreg of this instruction */
1553                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1554                                                         mono_regstate_free_general (rs, j, cur_bank);
1555                                                 }
1556                                         }
1557                                 }
1558                         }
1559                 }
1560
1561                 /*
1562                  * TRACK ARGUMENT REGS
1563                  */
1564                 if (spec [MONO_INST_CLOB] == 'c') {
1565                         MonoCallInst *call = (MonoCallInst*)ins;
1566                         GSList *list;
1567
1568                         /*
1569                          * This needs to be done before assigning sreg1, so sreg1 will
1570                          * not be assigned one of the argument regs.
1571                          */
1572
1573                         /*
1574                          * Assign all registers in call->out_reg_args to the proper
1575                          * argument registers.
1576                          */
1577
1578                         list = call->out_ireg_args;
1579                         if (list) {
1580                                 while (list) {
1581                                         guint32 regpair;
1582                                         int reg, hreg;
1583
1584                                         regpair = (guint32)(gssize)(list->data);
1585                                         hreg = regpair >> 24;
1586                                         reg = regpair & 0xffffff;
1587
1588                                         assign_reg (cfg, rs, reg, hreg, 0);
1589
1590                                         sreg_masks [0] &= ~(regmask (hreg));
1591
1592                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1593
1594                                         list = g_slist_next (list);
1595                                 }
1596                         }
1597
1598                         list = call->out_freg_args;
1599                         if (list) {
1600                                 while (list) {
1601                                         guint32 regpair;
1602                                         int reg, hreg;
1603
1604                                         regpair = (guint32)(gssize)(list->data);
1605                                         hreg = regpair >> 24;
1606                                         reg = regpair & 0xffffff;
1607
1608                                         assign_reg (cfg, rs, reg, hreg, 1);
1609
1610                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1611
1612                                         list = g_slist_next (list);
1613                                 }
1614                         }
1615                 }
1616
1617                 /*
1618                  * TRACK SREG1
1619                  */
1620                 bank = sreg1_bank (spec);
1621                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1622                         int sreg1 = sregs [0];
1623                         int dest_sreg1 = dest_sregs [0];
1624
1625                         g_assert (is_soft_reg (sreg1, bank));
1626
1627                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1628                         if (dest_sreg1 != -1)
1629                                 g_assert (dest_sreg1 == ins->dreg);
1630                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1631                         g_assert (val >= 0);
1632
1633                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1634                                 // FIXME:
1635                                 g_assert_not_reached ();
1636
1637                         assign_reg (cfg, rs, sreg1, val, bank);
1638
1639                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1640
1641                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1642                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1643                         g_assert (val >= 0);
1644
1645                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1646                                 // FIXME:
1647                                 g_assert_not_reached ();
1648
1649                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1650
1651                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1652
1653                         /* Skip rest of this section */
1654                         dest_sregs [0] = -1;
1655                 }
1656
1657                 if (sreg_fixed_masks [0]) {
1658                         g_assert (!bank);
1659                         if (is_global_ireg (sregs [0])) {
1660                                 /*
1661                                  * The argument is already in a hard reg, but that reg is
1662                                  * not usable by this instruction, so allocate a new one.
1663                                  */
1664                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1665                                 if (val < 0)
1666                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1667                                 mono_regstate_free_int (rs, val);
1668                                 dest_sregs [0] = val;
1669
1670                                 /* Fall through to the dest_sreg1 != -1 case */
1671                         }
1672                         else
1673                                 sreg_masks [0] &= sreg_fixed_masks [0];
1674                 }
1675
1676                 if (dest_sregs [0] != -1) {
1677                         sreg_masks [0] = regmask (dest_sregs [0]);
1678
1679                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1680                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sregs [0]]));
1681                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sregs [0]], 0);
1682                                 mono_regstate_free_int (rs, dest_sregs [0]);
1683                         }
1684                         if (is_global_ireg (sregs [0])) {
1685                                 /* The argument is already in a hard reg, need to copy */
1686                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1687                                 insert_before_ins (bb, ins, copy);
1688                                 sregs [0] = dest_sregs [0];
1689                         }
1690                 }
1691
1692                 if (is_soft_reg (sregs [0], bank)) {
1693                         val = rs->vassign [sregs [0]];
1694                         prev_sregs [0] = sregs [0];
1695                         if (val < 0) {
1696                                 int spill = 0;
1697                                 if (val < -1) {
1698                                         /* the register gets spilled after this inst */
1699                                         spill = -val -1;
1700                                 }
1701
1702                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1703                                         /*
1704                                          * Allocate the same hreg to sreg1 as well so the
1705                                          * peephole can get rid of the move.
1706                                          */
1707                                         sreg_masks [0] = regmask (ins->dreg);
1708                                 }
1709
1710                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1711                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1712                                         sreg_masks [0] = regmask (ins->dreg);
1713
1714                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1715                                 assign_reg (cfg, rs, sregs [0], val, bank);
1716                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1717
1718                                 if (spill) {
1719                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
1720                                         /*
1721                                          * Need to insert before the instruction since it can
1722                                          * overwrite sreg1.
1723                                          */
1724                                         insert_before_ins (bb, ins, store);
1725                                 }
1726                         }
1727                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1728                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1729                                 insert_before_ins (bb, ins, copy);
1730                                 for (j = 1; j < num_sregs; ++j)
1731                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1732                                 val = dest_sregs [0];
1733                         }
1734
1735                         sregs [0] = val;
1736                 }
1737                 else {
1738                         prev_sregs [0] = -1;
1739                 }
1740                 mono_inst_set_src_registers (ins, sregs);
1741
1742                 for (j = 1; j < num_sregs; ++j)
1743                         sreg_masks [j] &= ~(regmask (sregs [0]));
1744
1745                 /* Handle the case when sreg1 is a regpair but dreg is not */
1746                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1747                         int reg2 = prev_sregs [0] + 1;
1748
1749                         g_assert (!bank);
1750                         g_assert (prev_sregs [0] > -1);
1751                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1752                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1753                         val = rs->vassign [reg2];
1754                         if (val < 0) {
1755                                 int spill = 0;
1756                                 if (val < -1) {
1757                                         /* the register gets spilled after this inst */
1758                                         spill = -val -1;
1759                                 }
1760                                 val = mono_regstate_alloc_int (rs, mask);
1761                                 if (val < 0)
1762                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1763                                 if (spill)
1764                                         g_assert_not_reached ();
1765                         }
1766                         else {
1767                                 if (! (mask & (regmask (val)))) {
1768                                         /* The vreg is already allocated to a wrong hreg */
1769                                         /* FIXME: */
1770                                         g_assert_not_reached ();
1771 #if 0
1772                                         val = mono_regstate_alloc_int (rs, mask);
1773                                         if (val < 0)
1774                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1775
1776                                         /* Reallocate hreg to the correct register */
1777                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1778
1779                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1780 #endif
1781                                 }
1782                         }
1783
1784                         sreg1_high = val;
1785                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1786                         assign_reg (cfg, rs, reg2, val, bank);
1787                 }
1788
1789                 /* Handle dreg==sreg1 */
1790                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1791                         MonoInst *sreg2_copy = NULL;
1792                         MonoInst *copy;
1793                         int bank = reg_bank (spec_src1);
1794
1795                         if (ins->dreg == sregs [1]) {
1796                                 /*
1797                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1798                                  * register for it.
1799                                  */
1800                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1801
1802                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1803                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1804                                 prev_sregs [1] = sregs [1] = reg2;
1805
1806                                 if (G_UNLIKELY (bank))
1807                                         mono_regstate_free_general (rs, reg2, bank);
1808                                 else
1809                                         mono_regstate_free_int (rs, reg2);
1810                         }
1811
1812                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1813                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1814                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1815                                         /* FIXME: */
1816                                         g_assert_not_reached ();
1817
1818                                 /*
1819                                  * sreg1 and dest are already allocated to the same regpair by the
1820                                  * SREG1 allocation code.
1821                                  */
1822                                 g_assert (sregs [0] == ins->dreg);
1823                                 g_assert (dreg_high == sreg1_high);
1824                         }
1825
1826                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
1827                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
1828                         insert_before_ins (bb, ins, copy);
1829
1830                         if (sreg2_copy)
1831                                 insert_before_ins (bb, copy, sreg2_copy);
1832
1833                         /*
1834                          * Need to prevent sreg2 to be allocated to sreg1, since that
1835                          * would screw up the previous copy.
1836                          */
1837                         sreg_masks [1] &= ~ (regmask (sregs [0]));
1838                         /* we set sreg1 to dest as well */
1839                         prev_sregs [0] = sregs [0] = ins->dreg;
1840                         sreg_masks [1] &= ~ (regmask (ins->dreg));
1841                 }
1842                 mono_inst_set_src_registers (ins, sregs);
1843
1844                 /*
1845                  * TRACK SREG2, 3, ...
1846                  */
1847                 for (j = 1; j < num_sregs; ++j) {
1848                         int k;
1849
1850                         bank = sreg_bank (j, spec);
1851                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
1852                                 g_assert_not_reached ();
1853                         if (is_soft_reg (sregs [j], bank)) {
1854                                 val = rs->vassign [sregs [j]];
1855
1856                                 if (val < 0) {
1857                                         int spill = 0;
1858                                         if (val < -1) {
1859                                                 /* the register gets spilled after this inst */
1860                                                 spill = -val -1;
1861                                         }
1862                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
1863                                         assign_reg (cfg, rs, sregs [j], val, bank);
1864                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
1865                                         if (spill) {
1866                                                 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
1867                                                 /*
1868                                                  * Need to insert before the instruction since it can
1869                                                  * overwrite sreg2.
1870                                                  */
1871                                                 insert_before_ins (bb, ins, store);
1872                                         }
1873                                 }
1874                                 sregs [j] = val;
1875                                 for (k = j + 1; k < num_sregs; ++k)
1876                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
1877                         }
1878                         else {
1879                                 prev_sregs [j] = -1;
1880                         }
1881                 }
1882                 mono_inst_set_src_registers (ins, sregs);
1883
1884                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1885                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1886                         mono_regstate_free_int (rs, ins->sreg1);
1887                 }
1888                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1889                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1890                         mono_regstate_free_int (rs, ins->sreg2);
1891                 }*/
1892
1893                 DEBUG (mono_print_ins_index (i, ins));
1894         }
1895
1896         // FIXME: Set MAX_FREGS to 8
1897         // FIXME: Optimize generated code
1898 #if MONO_ARCH_USE_FPSTACK
1899         /*
1900          * Make a forward pass over the code, simulating the fp stack, making sure the
1901          * arguments required by the fp opcodes are at the top of the stack.
1902          */
1903         if (has_fp) {
1904                 MonoInst *prev = NULL;
1905                 MonoInst *fxch;
1906                 int tmp;
1907
1908                 g_assert (num_sregs <= 2);
1909
1910                 for (ins = bb->code; ins; ins = ins->next) {
1911                         spec = ins_get_spec (ins->opcode);
1912
1913                         DEBUG (printf ("processing:"));
1914                         DEBUG (mono_print_ins_index (0, ins));
1915
1916                         if (ins->opcode == OP_FMOVE) {
1917                                 /* Do it by renaming the source to the destination on the stack */
1918                                 // FIXME: Is this correct ?
1919                                 for (i = 0; i < sp; ++i)
1920                                         if (fpstack [i] == ins->sreg1)
1921                                                 fpstack [i] = ins->dreg;
1922                                 prev = ins;
1923                                 continue;
1924                         }
1925
1926                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1927                                 /* Arg1 must be in %st(1) */
1928                                 g_assert (prev);
1929
1930                                 i = 0;
1931                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
1932                                         i ++;
1933                                 g_assert (i < sp);
1934
1935                                 if (sp - 1 - i > 0) {
1936                                         /* First move it to %st(0) */
1937                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1938
1939                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1940                                         fxch->inst_imm = sp - 1 - i;
1941
1942                                         prev->next = fxch;
1943                                         fxch->next = ins;
1944                                         prev = fxch;
1945
1946                                         tmp = fpstack [sp - 1];
1947                                         fpstack [sp - 1] = fpstack [i];
1948                                         fpstack [i] = tmp;
1949                                 }
1950
1951                                 /* Then move it to %st(1) */
1952                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1953
1954                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1955                                 fxch->inst_imm = 1;
1956
1957                                 prev->next = fxch;
1958                                 fxch->next = ins;
1959                                 prev = fxch;
1960
1961                                 tmp = fpstack [sp - 1];
1962                                 fpstack [sp - 1] = fpstack [sp - 2];
1963                                 fpstack [sp - 2] = tmp;
1964                         }
1965
1966                         if (sreg2_is_fp (spec)) {
1967                                 g_assert (sp > 0);
1968
1969                                 if (fpstack [sp - 1] != ins->sreg2) {
1970                                         g_assert (prev);
1971
1972                                         i = 0;
1973                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
1974                                                 i ++;
1975                                         g_assert (i < sp);
1976
1977                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1978
1979                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1980                                         fxch->inst_imm = sp - 1 - i;
1981
1982                                         prev->next = fxch;
1983                                         fxch->next = ins;
1984                                         prev = fxch;
1985
1986                                         tmp = fpstack [sp - 1];
1987                                         fpstack [sp - 1] = fpstack [i];
1988                                         fpstack [i] = tmp;
1989                                 }
1990
1991                                 sp --;
1992                         }
1993
1994                         if (sreg1_is_fp (spec)) {
1995                                 g_assert (sp > 0);
1996
1997                                 if (fpstack [sp - 1] != ins->sreg1) {
1998                                         g_assert (prev);
1999
2000                                         i = 0;
2001                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2002                                                 i ++;
2003                                         g_assert (i < sp);
2004
2005                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2006
2007                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2008                                         fxch->inst_imm = sp - 1 - i;
2009
2010                                         prev->next = fxch;
2011                                         fxch->next = ins;
2012                                         prev = fxch;
2013
2014                                         tmp = fpstack [sp - 1];
2015                                         fpstack [sp - 1] = fpstack [i];
2016                                         fpstack [i] = tmp;
2017                                 }
2018
2019                                 sp --;
2020                         }
2021
2022                         if (dreg_is_fp (spec)) {
2023                                 g_assert (sp < 8);
2024                                 fpstack [sp ++] = ins->dreg;
2025                         }
2026
2027                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2028                                 printf ("\t[");
2029                                 for (i = 0; i < sp; ++i)
2030                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2031                                 printf ("]\n");
2032                         }
2033
2034                         prev = ins;
2035                 }
2036
2037                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2038                         /* Remove remaining items from the fp stack */
2039                         /*
2040                          * These can remain for example as a result of a dead fmove like in
2041                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2042                          */
2043                         while (sp) {
2044                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2045                                 mono_add_ins_to_end (bb, ins);
2046                                 sp --;
2047                         }
2048                 }
2049         }
2050 #endif
2051 }
2052
2053 CompRelation
2054 mono_opcode_to_cond (int opcode)
2055 {
2056         switch (opcode) {
2057         case CEE_BEQ:
2058         case OP_CEQ:
2059         case OP_IBEQ:
2060         case OP_ICEQ:
2061         case OP_LBEQ:
2062         case OP_LCEQ:
2063         case OP_FBEQ:
2064         case OP_FCEQ:
2065         case OP_COND_EXC_EQ:
2066         case OP_COND_EXC_IEQ:
2067         case OP_CMOV_IEQ:
2068         case OP_CMOV_LEQ:
2069                 return CMP_EQ;
2070         case CEE_BNE_UN:
2071         case OP_IBNE_UN:
2072         case OP_LBNE_UN:
2073         case OP_FBNE_UN:
2074         case OP_COND_EXC_NE_UN:
2075         case OP_COND_EXC_INE_UN:
2076         case OP_CMOV_INE_UN:
2077         case OP_CMOV_LNE_UN:
2078                 return CMP_NE;
2079         case CEE_BLE:
2080         case OP_IBLE:
2081         case OP_LBLE:
2082         case OP_FBLE:
2083         case OP_CMOV_ILE:
2084         case OP_CMOV_LLE:
2085                 return CMP_LE;
2086         case CEE_BGE:
2087         case OP_IBGE:
2088         case OP_LBGE:
2089         case OP_FBGE:
2090         case OP_CMOV_IGE:
2091         case OP_CMOV_LGE:
2092                 return CMP_GE;
2093         case CEE_BLT:
2094         case OP_CLT:
2095         case OP_IBLT:
2096         case OP_ICLT:
2097         case OP_LBLT:
2098         case OP_LCLT:
2099         case OP_FBLT:
2100         case OP_FCLT:
2101         case OP_COND_EXC_LT:
2102         case OP_COND_EXC_ILT:
2103         case OP_CMOV_ILT:
2104         case OP_CMOV_LLT:
2105                 return CMP_LT;
2106         case CEE_BGT:
2107         case OP_CGT:
2108         case OP_IBGT:
2109         case OP_ICGT:
2110         case OP_LBGT:
2111         case OP_LCGT:
2112         case OP_FBGT:
2113         case OP_FCGT:
2114         case OP_COND_EXC_GT:
2115         case OP_COND_EXC_IGT:
2116         case OP_CMOV_IGT:
2117         case OP_CMOV_LGT:
2118                 return CMP_GT;
2119
2120         case CEE_BLE_UN:
2121         case OP_IBLE_UN:
2122         case OP_LBLE_UN:
2123         case OP_FBLE_UN:
2124         case OP_COND_EXC_LE_UN:
2125         case OP_COND_EXC_ILE_UN:
2126         case OP_CMOV_ILE_UN:
2127         case OP_CMOV_LLE_UN:
2128                 return CMP_LE_UN;
2129         case CEE_BGE_UN:
2130         case OP_IBGE_UN:
2131         case OP_LBGE_UN:
2132         case OP_FBGE_UN:
2133         case OP_CMOV_IGE_UN:
2134         case OP_CMOV_LGE_UN:
2135                 return CMP_GE_UN;
2136         case CEE_BLT_UN:
2137         case OP_CLT_UN:
2138         case OP_IBLT_UN:
2139         case OP_ICLT_UN:
2140         case OP_LBLT_UN:
2141         case OP_LCLT_UN:
2142         case OP_FBLT_UN:
2143         case OP_FCLT_UN:
2144         case OP_COND_EXC_LT_UN:
2145         case OP_COND_EXC_ILT_UN:
2146         case OP_CMOV_ILT_UN:
2147         case OP_CMOV_LLT_UN:
2148                 return CMP_LT_UN;
2149         case CEE_BGT_UN:
2150         case OP_CGT_UN:
2151         case OP_IBGT_UN:
2152         case OP_ICGT_UN:
2153         case OP_LBGT_UN:
2154         case OP_LCGT_UN:
2155         case OP_FCGT_UN:
2156         case OP_FBGT_UN:
2157         case OP_COND_EXC_GT_UN:
2158         case OP_COND_EXC_IGT_UN:
2159         case OP_CMOV_IGT_UN:
2160         case OP_CMOV_LGT_UN:
2161                 return CMP_GT_UN;
2162         default:
2163                 printf ("%s\n", mono_inst_name (opcode));
2164                 g_assert_not_reached ();
2165                 return 0;
2166         }
2167 }
2168
2169 CompRelation
2170 mono_negate_cond (CompRelation cond)
2171 {
2172         switch (cond) {
2173         case CMP_EQ:
2174                 return CMP_NE;
2175         case CMP_NE:
2176                 return CMP_EQ;
2177         case CMP_LE:
2178                 return CMP_GT;
2179         case CMP_GE:
2180                 return CMP_LT;
2181         case CMP_LT:
2182                 return CMP_GE;
2183         case CMP_GT:
2184                 return CMP_LE;
2185         case CMP_LE_UN:
2186                 return CMP_GT_UN;
2187         case CMP_GE_UN:
2188                 return CMP_LT_UN;
2189         case CMP_LT_UN:
2190                 return CMP_GE_UN;
2191         case CMP_GT_UN:
2192                 return CMP_LE_UN;
2193         default:
2194                 g_assert_not_reached ();
2195         }
2196 }
2197
2198 CompType
2199 mono_opcode_to_type (int opcode, int cmp_opcode)
2200 {
2201         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2202                 return CMP_TYPE_L;
2203         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2204                 return CMP_TYPE_L;
2205         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2206                 return CMP_TYPE_I;
2207         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2208                 return CMP_TYPE_I;
2209         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2210                 return CMP_TYPE_L;
2211         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2212                 return CMP_TYPE_L;
2213         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2214                 return CMP_TYPE_F;
2215         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2216                 return CMP_TYPE_F;
2217         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2218                 return CMP_TYPE_I;
2219         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2220                 switch (cmp_opcode) {
2221                 case OP_ICOMPARE:
2222                 case OP_ICOMPARE_IMM:
2223                 case OP_LCOMPARE_IMM:
2224                         return CMP_TYPE_I;
2225                 default:
2226                         return CMP_TYPE_L;
2227                 }
2228         } else {
2229                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2230                 return 0;
2231         }
2232 }
2233
2234 gboolean
2235 mono_is_regsize_var (MonoType *t)
2236 {
2237         if (t->byref)
2238                 return TRUE;
2239         t = mono_type_get_underlying_type (t);
2240         switch (t->type) {
2241         case MONO_TYPE_BOOLEAN:
2242         case MONO_TYPE_CHAR:
2243         case MONO_TYPE_I1:
2244         case MONO_TYPE_U1:
2245         case MONO_TYPE_I2:
2246         case MONO_TYPE_U2:
2247         case MONO_TYPE_I4:
2248         case MONO_TYPE_U4:
2249         case MONO_TYPE_I:
2250         case MONO_TYPE_U:
2251         case MONO_TYPE_PTR:
2252         case MONO_TYPE_FNPTR:
2253 #if SIZEOF_REGISTER == 8
2254         case MONO_TYPE_I8:
2255         case MONO_TYPE_U8:
2256 #endif
2257                 return TRUE;
2258         case MONO_TYPE_OBJECT:
2259         case MONO_TYPE_STRING:
2260         case MONO_TYPE_CLASS:
2261         case MONO_TYPE_SZARRAY:
2262         case MONO_TYPE_ARRAY:
2263                 return TRUE;
2264         case MONO_TYPE_GENERICINST:
2265                 if (!mono_type_generic_inst_is_valuetype (t))
2266                         return TRUE;
2267                 return FALSE;
2268         case MONO_TYPE_VALUETYPE:
2269                 return FALSE;
2270         }
2271         return FALSE;
2272 }
2273
2274 /*
2275  * mono_peephole_ins:
2276  *
2277  *   Perform some architecture independent peephole optimizations.
2278  */
2279 void
2280 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2281 {
2282         MonoInst *last_ins = ins->prev;
2283
2284         switch (ins->opcode) {
2285         case OP_MUL_IMM:
2286                 /* remove unnecessary multiplication with 1 */
2287                 if (ins->inst_imm == 1) {
2288                         if (ins->dreg != ins->sreg1)
2289                                 ins->opcode = OP_MOVE;
2290                         else
2291                                 MONO_DELETE_INS (bb, ins);
2292                 }
2293                 break;
2294         case OP_LOAD_MEMBASE:
2295         case OP_LOADI4_MEMBASE:
2296                 /*
2297                  * Note: if reg1 = reg2 the load op is removed
2298                  *
2299                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2300                  * OP_LOAD_MEMBASE offset(basereg), reg2
2301                  * -->
2302                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2303                  * OP_MOVE reg1, reg2
2304                  */
2305                 if (last_ins &&
2306                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2307                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2308                         ins->inst_basereg == last_ins->inst_destbasereg &&
2309                         ins->inst_offset == last_ins->inst_offset) {
2310                         if (ins->dreg == last_ins->sreg1) {
2311                                 MONO_DELETE_INS (bb, ins);
2312                                 break;
2313                         } else {
2314                                 ins->opcode = OP_MOVE;
2315                                 ins->sreg1 = last_ins->sreg1;
2316                         }
2317
2318                         /*
2319                          * Note: reg1 must be different from the basereg in the second load
2320                          * Note: if reg1 = reg2 is equal then second load is removed
2321                          *
2322                          * OP_LOAD_MEMBASE offset(basereg), reg1
2323                          * OP_LOAD_MEMBASE offset(basereg), reg2
2324                          * -->
2325                          * OP_LOAD_MEMBASE offset(basereg), reg1
2326                          * OP_MOVE reg1, reg2
2327                          */
2328                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2329                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2330                           ins->inst_basereg != last_ins->dreg &&
2331                           ins->inst_basereg == last_ins->inst_basereg &&
2332                           ins->inst_offset == last_ins->inst_offset) {
2333
2334                         if (ins->dreg == last_ins->dreg) {
2335                                 MONO_DELETE_INS (bb, ins);
2336                         } else {
2337                                 ins->opcode = OP_MOVE;
2338                                 ins->sreg1 = last_ins->dreg;
2339                         }
2340
2341                         //g_assert_not_reached ();
2342
2343 #if 0
2344                         /*
2345                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2346                          * OP_LOAD_MEMBASE offset(basereg), reg
2347                          * -->
2348                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2349                          * OP_ICONST reg, imm
2350                          */
2351                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2352                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2353                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2354                                    ins->inst_offset == last_ins->inst_offset) {
2355                         ins->opcode = OP_ICONST;
2356                         ins->inst_c0 = last_ins->inst_imm;
2357                         g_assert_not_reached (); // check this rule
2358 #endif
2359                 }
2360                 break;
2361         case OP_LOADI1_MEMBASE:
2362         case OP_LOADU1_MEMBASE:
2363                 /*
2364                  * Note: if reg1 = reg2 the load op is removed
2365                  *
2366                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2367                  * OP_LOAD_MEMBASE offset(basereg), reg2
2368                  * -->
2369                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2370                  * OP_MOVE reg1, reg2
2371                  */
2372                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2373                         ins->inst_basereg == last_ins->inst_destbasereg &&
2374                         ins->inst_offset == last_ins->inst_offset) {
2375                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2376                         ins->sreg1 = last_ins->sreg1;
2377                 }
2378                 break;
2379         case OP_LOADI2_MEMBASE:
2380         case OP_LOADU2_MEMBASE:
2381                 /*
2382                  * Note: if reg1 = reg2 the load op is removed
2383                  *
2384                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2385                  * OP_LOAD_MEMBASE offset(basereg), reg2
2386                  * -->
2387                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2388                  * OP_MOVE reg1, reg2
2389                  */
2390                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2391                         ins->inst_basereg == last_ins->inst_destbasereg &&
2392                         ins->inst_offset == last_ins->inst_offset) {
2393 #if SIZEOF_REGISTER == 8
2394                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2395 #else
2396                         /* The definition of OP_PCONV_TO_U2 is wrong */
2397                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2398 #endif
2399                         ins->sreg1 = last_ins->sreg1;
2400                 }
2401                 break;
2402         case OP_MOVE:
2403         case OP_FMOVE:
2404                 /*
2405                  * Removes:
2406                  *
2407                  * OP_MOVE reg, reg
2408                  */
2409                 if (ins->dreg == ins->sreg1) {
2410                         MONO_DELETE_INS (bb, ins);
2411                         break;
2412                 }
2413                 /*
2414                  * Removes:
2415                  *
2416                  * OP_MOVE sreg, dreg
2417                  * OP_MOVE dreg, sreg
2418                  */
2419                 if (last_ins && last_ins->opcode == OP_MOVE &&
2420                         ins->sreg1 == last_ins->dreg &&
2421                         ins->dreg == last_ins->sreg1) {
2422                         MONO_DELETE_INS (bb, ins);
2423                 }
2424                 break;
2425         case OP_NOP:
2426                 MONO_DELETE_INS (bb, ins);
2427                 break;
2428         }
2429 }
2430