mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583         case OP_STORE_MEMBASE_IMM:
 584                 printf (" [%d]", (int)ins->inst_imm);
 585                 break;
 586         case OP_ADD_IMM:
 587         case OP_LADD_IMM:
 588                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 589                 break;
 590         case OP_I8CONST:
 591                 printf (" [%lld]", (long long)ins->inst_l);
 592                 break;
 593         case OP_R8CONST:
 594                 printf (" [%f]", *(double*)ins->inst_p0);
 595                 break;
 596         case OP_R4CONST:
 597                 printf (" [%f]", *(float*)ins->inst_p0);
 598                 break;
 599         case OP_CALL:
 600         case OP_CALL_MEMBASE:
 601         case OP_CALL_REG:
 602         case OP_FCALL:
 603         case OP_LCALL:
 604         case OP_VCALL:
 605         case OP_VCALL_REG:
 606         case OP_VCALL_MEMBASE:
 607         case OP_VCALL2:
 608         case OP_VCALL2_REG:
 609         case OP_VCALL2_MEMBASE:
 610         case OP_VOIDCALL:
 611         case OP_VOIDCALL_MEMBASE:
 612         case OP_TAILCALL: {
 613                 MonoCallInst *call = (MonoCallInst*)ins;
 614                 GSList *list;
 615
 616                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 617                         /*
 618                          * These are lowered opcodes, but they are in the .md files since the old
 619                          * JIT passes them to backends.
 620                          */
 621                         if (ins->dreg != -1)
 622                                 printf (" R%d <-", ins->dreg);
 623                 }
 624
 625                 if (call->method) {
 626                         char *full_name = mono_method_full_name (call->method, TRUE);
 627                         printf (" [%s]", full_name);
 628                         g_free (full_name);
 629                 } else if (call->fptr_is_patch) {
 630                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 631
 632                         printf (" ");
 633                         mono_print_ji (ji);
 634                 } else if (call->fptr) {
 635                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 636                         if (info)
 637                                 printf (" [%s]", info->name);
 638                 }
 639
 640                 list = call->out_ireg_args;
 641                 while (list) {
 642                         guint32 regpair;
 643                         int reg, hreg;
 644
 645                         regpair = (guint32)(gssize)(list->data);
 646                         hreg = regpair >> 24;
 647                         reg = regpair & 0xffffff;
 648
 649                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 650
 651                         list = g_slist_next (list);
 652                 }
 653                 list = call->out_freg_args;
 654                 while (list) {
 655                         guint32 regpair;
 656                         int reg, hreg;
 657
 658                         regpair = (guint32)(gssize)(list->data);
 659                         hreg = regpair >> 24;
 660                         reg = regpair & 0xffffff;
 661
 662                         printf (" [%s <- R%d]", mono_arch_fregname (hreg), reg);
 663
 664                         list = g_slist_next (list);
 665                 }
 666                 break;
 667         }
 668         case OP_BR:
 669         case OP_CALL_HANDLER:
 670                 printf (" [B%d]", ins->inst_target_bb->block_num);
 671                 break;
 672         case OP_IBNE_UN:
 673         case OP_IBEQ:
 674         case OP_IBLT:
 675         case OP_IBLT_UN:
 676         case OP_IBGT:
 677         case OP_IBGT_UN:
 678         case OP_IBGE:
 679         case OP_IBGE_UN:
 680         case OP_IBLE:
 681         case OP_IBLE_UN:
 682         case OP_LBNE_UN:
 683         case OP_LBEQ:
 684         case OP_LBLT:
 685         case OP_LBLT_UN:
 686         case OP_LBGT:
 687         case OP_LBGT_UN:
 688         case OP_LBGE:
 689         case OP_LBGE_UN:
 690         case OP_LBLE:
 691         case OP_LBLE_UN:
 692                 if (!ins->inst_false_bb)
 693                         printf (" [B%d]", ins->inst_true_bb->block_num);
 694                 else
 695                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 696                 break;
 697         case OP_LIVERANGE_START:
 698         case OP_LIVERANGE_END:
 699         case OP_GC_LIVENESS_DEF:
 700         case OP_GC_LIVENESS_USE:
 701                 printf (" R%d", (int)ins->inst_c1);
 702                 break;
 703         case OP_IL_SEQ_POINT:
 704         case OP_SEQ_POINT:
 705                 printf (" il: %x", (int)ins->inst_imm);
 706                 break;
 707         default:
 708                 break;
 709         }
 710
 711         if (spec [MONO_INST_CLOB])
 712                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 713         printf ("\n");
 714 }
 715
 716 static void
 717 print_regtrack (RegTrack *t, int num)
 718 {
 719         int i;
 720         char buf [32];
 721         const char *r;
 722
 723         for (i = 0; i < num; ++i) {
 724                 if (!t [i].born_in)
 725                         continue;
 726                 if (i >= MONO_MAX_IREGS) {
 727                         g_snprintf (buf, sizeof(buf), "R%d", i);
 728                         r = buf;
 729                 } else
 730                         r = mono_arch_regname (i);
 731                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 732         }
 733 }
 734 #else
 735
 736 void
 737 mono_print_ji (const MonoJumpInfo *ji)
 738 {
 739 }
 740
 741 void
 742 mono_print_ins_index (int i, MonoInst *ins)
 743 {
 744 }
 745 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 746
 747 void
 748 mono_print_ins (MonoInst *ins)
 749 {
 750         mono_print_ins_index (-1, ins);
 751 }
 752
 753 static inline void
 754 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 755 {
 756         /*
 757          * If this function is called multiple times, the new instructions are inserted
 758          * in the proper order.
 759          */
 760         mono_bblock_insert_before_ins (bb, ins, to_insert);
 761 }
 762
 763 static inline void
 764 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 765 {
 766         /*
 767          * If this function is called multiple times, the new instructions are inserted in
 768          * proper order.
 769          */
 770         mono_bblock_insert_after_ins (bb, *last, to_insert);
 771
 772         *last = to_insert;
 773 }
 774
 775 static inline int
 776 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 777 {
 778         if (vreg_is_ref (cfg, reg))
 779                 return MONO_REG_INT_REF;
 780         else if (vreg_is_mp (cfg, reg))
 781                 return MONO_REG_INT_MP;
 782         else
 783                 return bank;
 784 }
 785
 786 /*
 787  * Force the spilling of the variable in the symbolic register 'reg', and free
 788  * the hreg it was assigned to.
 789  */
 790 static void
 791 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 792 {
 793         MonoInst *load;
 794         int i, sel, spill;
 795         MonoRegState *rs = cfg->rs;
 796
 797         sel = rs->vassign [reg];
 798
 799         /* the vreg we need to spill lives in another logical reg bank */
 800         bank = translate_bank (cfg->rs, bank, sel);
 801
 802         /*i = rs->isymbolic [sel];
 803         g_assert (i == reg);*/
 804         i = reg;
 805         spill = ++cfg->spill_count;
 806         rs->vassign [i] = -spill - 1;
 807         if (G_UNLIKELY (bank))
 808                 mono_regstate_free_general (rs, sel, bank);
 809         else
 810                 mono_regstate_free_int (rs, sel);
 811         /* we need to create a spill var and insert a load to sel after the current instruction */
 812         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 813         load->dreg = sel;
 814         load->inst_basereg = cfg->frame_reg;
 815         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 816         insert_after_ins (bb, ins, last, load);
 817         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 818         if (G_UNLIKELY (bank))
 819                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 820         else
 821                 i = mono_regstate_alloc_int (rs, regmask (sel));
 822         g_assert (i == sel);
 823
 824         if (G_UNLIKELY (bank))
 825                 mono_regstate_free_general (rs, sel, bank);
 826         else
 827                 mono_regstate_free_int (rs, sel);
 828 }
 829
 830 /* This isn't defined on older glib versions and on some platforms */
 831 #ifndef G_GUINT64_FORMAT
 832 #define G_GUINT64_FORMAT "ul"
 833 #endif
 834
 835 static int
 836 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 837 {
 838         MonoInst *load;
 839         int i, sel, spill, num_sregs;
 840         int sregs [MONO_MAX_SRC_REGS];
 841         MonoRegState *rs = cfg->rs;
 842
 843         g_assert (bank < MONO_NUM_REGBANKS);
 844
 845         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 846         /* exclude the registers in the current instruction */
 847         num_sregs = mono_inst_get_src_registers (ins, sregs);
 848         for (i = 0; i < num_sregs; ++i) {
 849                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 850                         if (is_soft_reg (sregs [i], bank))
 851                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 852                         else
 853                                 regmask &= ~ (regmask (sregs [i]));
 854                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 855                 }
 856         }
 857         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 858                 regmask &= ~ (regmask (ins->dreg));
 859                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 860         }
 861
 862         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 863         g_assert (regmask); /* need at least a register we can free */
 864         sel = 0;
 865         /* we should track prev_use and spill the register that's farther */
 866         if (G_UNLIKELY (bank)) {
 867                 for (i = 0; i < regbank_size [bank]; ++i) {
 868                         if (regmask & (regmask (i))) {
 869                                 sel = i;
 870
 871                                 /* the vreg we need to load lives in another logical bank */
 872                                 bank = translate_bank (cfg->rs, bank, sel);
 873
 874                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 875                                 break;
 876                         }
 877                 }
 878
 879                 i = rs->symbolic [bank] [sel];
 880                 spill = ++cfg->spill_count;
 881                 rs->vassign [i] = -spill - 1;
 882                 mono_regstate_free_general (rs, sel, bank);
 883         }
 884         else {
 885                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 886                         if (regmask & (regmask (i))) {
 887                                 sel = i;
 888                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 889                                 break;
 890                         }
 891                 }
 892
 893                 i = rs->isymbolic [sel];
 894                 spill = ++cfg->spill_count;
 895                 rs->vassign [i] = -spill - 1;
 896                 mono_regstate_free_int (rs, sel);
 897         }
 898
 899         /* we need to create a spill var and insert a load to sel after the current instruction */
 900         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 901         load->dreg = sel;
 902         load->inst_basereg = cfg->frame_reg;
 903         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 904         insert_after_ins (bb, ins, last, load);
 905         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 906         if (G_UNLIKELY (bank))
 907                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 908         else
 909                 i = mono_regstate_alloc_int (rs, regmask (sel));
 910         g_assert (i == sel);
 911
 912         return sel;
 913 }
 914
 915 /*
 916  * free_up_hreg:
 917  *
 918  *   Free up the hreg HREG by spilling the vreg allocated to it.
 919  */
 920 static void
 921 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 922 {
 923         if (G_UNLIKELY (bank)) {
 924                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 925                         bank = translate_bank (cfg->rs, bank, hreg);
 926                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 927                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 928                 }
 929         }
 930         else {
 931                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 932                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 933                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 934                 }
 935         }
 936 }
 937
 938 static MonoInst*
 939 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 940 {
 941         MonoInst *copy;
 942
 943         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 944
 945         copy->dreg = dest;
 946         copy->sreg1 = src;
 947         copy->cil_code = ip;
 948         if (ins) {
 949                 mono_bblock_insert_after_ins (bb, ins, copy);
 950                 *last = copy;
 951         }
 952         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 953         return copy;
 954 }
 955
 956 static inline const char*
 957 regbank_to_string (int bank)
 958 {
 959         if (bank == MONO_REG_INT_REF)
 960                 return "REF ";
 961         else if (bank == MONO_REG_INT_MP)
 962                 return "MP ";
 963         else
 964                 return "";
 965 }
 966
 967 static void
 968 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 969 {
 970         MonoInst *store, *def;
 971
 972         bank = get_vreg_bank (cfg, prev_reg, bank);
 973
 974         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 975         store->sreg1 = reg;
 976         store->inst_destbasereg = cfg->frame_reg;
 977         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 978         if (ins) {
 979                 mono_bblock_insert_after_ins (bb, ins, store);
 980                 *last = store;
 981         } else if (insert_before) {
 982                 insert_before_ins (bb, insert_before, store);
 983         } else {
 984                 g_assert_not_reached ();
 985         }
 986         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 987
 988         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 989                 g_assert (prev_reg != -1);
 990                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 991                 def->inst_c0 = spill;
 992                 def->inst_c1 = bank;
 993                 mono_bblock_insert_after_ins (bb, store, def);
 994         }
 995 }
 996
 997 /* flags used in reginfo->flags */
 998 enum {
 999         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1000         MONO_FP_NEEDS_SPILL                     = regmask (1),
1001         MONO_FP_NEEDS_LOAD                      = regmask (2)
1002 };
1003
1004 static inline int
1005 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1006 {
1007         int val;
1008
1009         if (info && info->preferred_mask) {
1010                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1011                 if (val >= 0) {
1012                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1013                         return val;
1014                 }
1015         }
1016
1017         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1018         if (val < 0)
1019                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1020
1021         return val;
1022 }
1023
1024 static inline int
1025 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1026 {
1027         int val;
1028
1029         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1030
1031         if (val < 0)
1032                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1033
1034         return val;
1035 }
1036
1037 static inline int
1038 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1039 {
1040         if (G_UNLIKELY (bank))
1041                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1042         else
1043                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1044 }
1045
1046 static inline void
1047 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1048 {
1049         if (G_UNLIKELY (bank)) {
1050                 int mirrored_bank;
1051
1052                 g_assert (reg >= regbank_size [bank]);
1053                 g_assert (hreg < regbank_size [bank]);
1054                 g_assert (! is_global_freg (hreg));
1055
1056                 rs->vassign [reg] = hreg;
1057                 rs->symbolic [bank] [hreg] = reg;
1058                 rs->free_mask [bank] &= ~ (regmask (hreg));
1059
1060                 mirrored_bank = get_mirrored_bank (bank);
1061                 if (mirrored_bank == -1)
1062                         return;
1063
1064                 /* Make sure the other logical reg bank that this bank shares
1065                  * a single hard reg bank knows that this hard reg is not free.
1066                  */
1067                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1068
1069                 /* Mark the other logical bank that the this bank shares
1070                  * a single hard reg bank with as mirrored.
1071                  */
1072                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1073
1074         }
1075         else {
1076                 g_assert (reg >= MONO_MAX_IREGS);
1077                 g_assert (hreg < MONO_MAX_IREGS);
1078 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1079                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1080                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1081                 g_assert (! is_global_ireg (hreg));
1082 #endif
1083
1084                 rs->vassign [reg] = hreg;
1085                 rs->isymbolic [hreg] = reg;
1086                 rs->ifree_mask &= ~ (regmask (hreg));
1087         }
1088 }
1089
1090 static inline regmask_t
1091 get_callee_mask (const char spec)
1092 {
1093         if (G_UNLIKELY (reg_bank (spec)))
1094                 return regbank_callee_regs [reg_bank (spec)];
1095         return MONO_ARCH_CALLEE_REGS;
1096 }
1097
1098 static gint8 desc_to_fixed_reg [256];
1099 static gboolean desc_to_fixed_reg_inited = FALSE;
1100
1101 #ifndef DISABLE_JIT
1102
1103 /*
1104  * Local register allocation.
1105  * We first scan the list of instructions and we save the liveness info of
1106  * each register (when the register is first used, when it's value is set etc.).
1107  * We also reverse the list of instructions because assigning registers backwards allows
1108  * for more tricks to be used.
1109  */
1110 void
1111 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1112 {
1113         MonoInst *ins, *prev, *last;
1114         MonoInst **tmp;
1115         MonoRegState *rs = cfg->rs;
1116         int i, j, val, max;
1117         RegTrack *reginfo;
1118         const char *spec;
1119         unsigned char spec_src1, spec_dest;
1120         int bank = 0;
1121 #if MONO_ARCH_USE_FPSTACK
1122         gboolean has_fp = FALSE;
1123         int fpstack [8];
1124         int sp = 0;
1125 #endif
1126         int num_sregs = 0;
1127         int sregs [MONO_MAX_SRC_REGS];
1128
1129         if (!bb->code)
1130                 return;
1131
1132         if (!desc_to_fixed_reg_inited) {
1133                 for (i = 0; i < 256; ++i)
1134                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1135                 desc_to_fixed_reg_inited = TRUE;
1136
1137                 /* Validate the cpu description against the info in mini-ops.h */
1138 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1139                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1140                         const char *ispec;
1141
1142                         spec = ins_get_spec (i);
1143                         ispec = INS_INFO (i);
1144
1145                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1146                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1147                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1148                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1149                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1150                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1151                 }
1152 #endif
1153         }
1154
1155         rs->next_vreg = bb->max_vreg;
1156         mono_regstate_assign (rs);
1157
1158         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1159         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1160                 rs->free_mask [i] = regbank_callee_regs [i];
1161
1162         max = rs->next_vreg;
1163
1164         if (cfg->reginfo && cfg->reginfo_len < max)
1165                 cfg->reginfo = NULL;
1166
1167         reginfo = cfg->reginfo;
1168         if (!reginfo) {
1169                 cfg->reginfo_len = MAX (1024, max * 2);
1170                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1171         }
1172         else
1173                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1174
1175         if (cfg->verbose_level > 1) {
1176                 /* print_regtrack reads the info of all variables */
1177                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1178         }
1179
1180         /*
1181          * For large methods, next_vreg can be very large, so g_malloc0 time can
1182          * be prohibitive. So we manually init the reginfo entries used by the
1183          * bblock.
1184          */
1185         for (ins = bb->code; ins; ins = ins->next) {
1186                 gboolean modify = FALSE;
1187
1188                 spec = ins_get_spec (ins->opcode);
1189
1190                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1191                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1192 #if SIZEOF_REGISTER == 4
1193                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1194                                 /**
1195                                  * In the new IR, the two vregs of the regpair do not alias the
1196                                  * original long vreg. shift the vreg here so the rest of the
1197                                  * allocator doesn't have to care about it.
1198                                  */
1199                                 ins->dreg ++;
1200                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1201                         }
1202 #endif
1203                 }
1204
1205                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1206                 for (j = 0; j < num_sregs; ++j) {
1207                         g_assert (sregs [j] != -1);
1208                         if (sregs [j] < max) {
1209                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1210 #if SIZEOF_REGISTER == 4
1211                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1212                                         sregs [j]++;
1213                                         modify = TRUE;
1214                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1215                                 }
1216 #endif
1217                         }
1218                 }
1219                 if (modify)
1220                         mono_inst_set_src_registers (ins, sregs);
1221         }
1222
1223         /*if (cfg->opt & MONO_OPT_COPYPROP)
1224                 local_copy_prop (cfg, ins);*/
1225
1226         i = 1;
1227         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1228         /* forward pass on the instructions to collect register liveness info */
1229         MONO_BB_FOR_EACH_INS (bb, ins) {
1230                 spec = ins_get_spec (ins->opcode);
1231                 spec_dest = spec [MONO_INST_DEST];
1232
1233                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1234                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1235                 }
1236
1237                 DEBUG (mono_print_ins_index (i, ins));
1238
1239                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1240
1241 #if MONO_ARCH_USE_FPSTACK
1242                 if (dreg_is_fp (spec)) {
1243                         has_fp = TRUE;
1244                 } else {
1245                         for (j = 0; j < num_sregs; ++j) {
1246                                 if (sreg_is_fp (j, spec))
1247                                         has_fp = TRUE;
1248                         }
1249                 }
1250 #endif
1251
1252                 for (j = 0; j < num_sregs; ++j) {
1253                         int sreg = sregs [j];
1254                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1255                         if (sreg_spec) {
1256                                 bank = sreg_bank (j, spec);
1257                                 g_assert (sreg != -1);
1258                                 if (is_soft_reg (sreg, bank))
1259                                         /* This means the vreg is not local to this bb */
1260                                         g_assert (reginfo [sreg].born_in > 0);
1261                                 rs->vassign [sreg] = -1;
1262                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1263                                 //reginfo [ins->sreg2].last_use = i;
1264                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1265                                         /* The virtual register is allocated sequentially */
1266                                         rs->vassign [sreg + 1] = -1;
1267                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1268                                         //reginfo [ins->sreg2 + 1].last_use = i;
1269                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1270                                                 reginfo [sreg + 1].born_in = i;
1271                                 }
1272                         } else {
1273                                 sregs [j] = -1;
1274                         }
1275                 }
1276                 mono_inst_set_src_registers (ins, sregs);
1277
1278                 if (spec_dest) {
1279                         int dest_dreg;
1280
1281                         bank = dreg_bank (spec);
1282                         if (spec_dest != 'b') /* it's not just a base register */
1283                                 reginfo [ins->dreg].killed_in = i;
1284                         g_assert (ins->dreg != -1);
1285                         rs->vassign [ins->dreg] = -1;
1286                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1287                         //reginfo [ins->dreg].last_use = i;
1288                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1289                                 reginfo [ins->dreg].born_in = i;
1290
1291                         dest_dreg = desc_to_fixed_reg [spec_dest];
1292                         if (dest_dreg != -1)
1293                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1294
1295 #ifdef MONO_ARCH_INST_FIXED_MASK
1296                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1297 #endif
1298
1299                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1300                                 /* The virtual register is allocated sequentially */
1301                                 rs->vassign [ins->dreg + 1] = -1;
1302                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1303                                 //reginfo [ins->dreg + 1].last_use = i;
1304                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1305                                         reginfo [ins->dreg + 1].born_in = i;
1306                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1307                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1308                         }
1309                 } else {
1310                         ins->dreg = -1;
1311                 }
1312
1313                 ++i;
1314         }
1315
1316         tmp = &last;
1317
1318         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1319         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1320                 int prev_dreg;
1321                 int dest_dreg, clob_reg;
1322                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1323                 int dreg_high, sreg1_high;
1324                 regmask_t dreg_mask, mask;
1325                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1326                 regmask_t dreg_fixed_mask;
1327                 const unsigned char *ip;
1328                 --i;
1329                 spec = ins_get_spec (ins->opcode);
1330                 spec_src1 = spec [MONO_INST_SRC1];
1331                 spec_dest = spec [MONO_INST_DEST];
1332                 prev_dreg = -1;
1333                 clob_reg = -1;
1334                 dest_dreg = -1;
1335                 dreg_high = -1;
1336                 sreg1_high = -1;
1337                 dreg_mask = get_callee_mask (spec_dest);
1338                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1339                         prev_sregs [j] = -1;
1340                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1341                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1342 #ifdef MONO_ARCH_INST_FIXED_MASK
1343                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1344 #else
1345                         sreg_fixed_masks [j] = 0;
1346 #endif
1347                 }
1348
1349                 DEBUG (printf ("processing:"));
1350                 DEBUG (mono_print_ins_index (i, ins));
1351
1352                 ip = ins->cil_code;
1353
1354                 last = ins;
1355
1356                 /*
1357                  * FIXED REGS
1358                  */
1359                 dest_dreg = desc_to_fixed_reg [spec_dest];
1360                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1361                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1362
1363 #ifdef MONO_ARCH_INST_FIXED_MASK
1364                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1365 #else
1366                 dreg_fixed_mask = 0;
1367 #endif
1368
1369                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1370
1371                 /*
1372                  * TRACK FIXED SREG2, 3, ...
1373                  */
1374                 for (j = 1; j < num_sregs; ++j) {
1375                         int sreg = sregs [j];
1376                         int dest_sreg = dest_sregs [j];
1377
1378                         if (dest_sreg == -1)
1379                                 continue;
1380
1381                         if (j == 2) {
1382                                 int k;
1383
1384                                 /*
1385                                  * CAS.
1386                                  * We need to special case this, since on x86, there are only 3
1387                                  * free registers, and the code below assigns one of them to
1388                                  * sreg, so we can run out of registers when trying to assign
1389                                  * dreg. Instead, we just set up the register masks, and let the
1390                                  * normal sreg2 assignment code handle this. It would be nice to
1391                                  * do this for all the fixed reg cases too, but there is too much
1392                                  * risk of breakage.
1393                                  */
1394
1395                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1396                                 sreg_masks [j] = regmask (dest_sreg);
1397                                 for (k = 0; k < num_sregs; ++k) {
1398                                         if (k != j)
1399                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1400                                 }
1401
1402                                 /*
1403                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1404                                  */
1405                                 for (k = 0; k < num_sregs; ++k) {
1406                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1407                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1408                                 }
1409
1410                                 /*
1411                                  * We can also run out of registers while processing sreg2 if sreg3 is
1412                                  * assigned to another hreg, so spill sreg3 now.
1413                                  */
1414                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1415                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1416                                 }
1417                                 continue;
1418                         }
1419
1420                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1421                                 if (is_global_ireg (sreg)) {
1422                                         int k;
1423                                         /* Argument already in hard reg, need to copy */
1424                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1425                                         insert_before_ins (bb, ins, copy);
1426                                         for (k = 0; k < num_sregs; ++k) {
1427                                                 if (k != j)
1428                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1429                                         }
1430                                         /* See below */
1431                                         dreg_mask &= ~ (regmask (dest_sreg));
1432                                 } else {
1433                                         val = rs->vassign [sreg];
1434                                         if (val == -1) {
1435                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1436                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1437                                         } else if (val < -1) {
1438                                                 /* FIXME: */
1439                                                 g_assert_not_reached ();
1440                                         } else {
1441                                                 /* Argument already in hard reg, need to copy */
1442                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1443                                                 int k;
1444
1445                                                 insert_before_ins (bb, ins, copy);
1446                                                 for (k = 0; k < num_sregs; ++k) {
1447                                                         if (k != j)
1448                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1449                                                 }
1450                                                 /*
1451                                                  * Prevent the dreg from being allocated to dest_sreg
1452                                                  * too, since it could force sreg1 to be allocated to
1453                                                  * the same reg on x86.
1454                                                  */
1455                                                 dreg_mask &= ~ (regmask (dest_sreg));
1456                                         }
1457                                 }
1458                         } else {
1459                                 gboolean need_spill = TRUE;
1460                                 gboolean need_assign = TRUE;
1461                                 int k;
1462
1463                                 dreg_mask &= ~ (regmask (dest_sreg));
1464                                 for (k = 0; k < num_sregs; ++k) {
1465                                         if (k != j)
1466                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1467                                 }
1468
1469                                 /*
1470                                  * First check if dreg is assigned to dest_sreg2, since we
1471                                  * can't spill a dreg.
1472                                  */
1473                                 if (spec [MONO_INST_DEST])
1474                                         val = rs->vassign [ins->dreg];
1475                                 else
1476                                         val = -1;
1477                                 if (val == dest_sreg && ins->dreg != sreg) {
1478                                         /*
1479                                          * the destination register is already assigned to
1480                                          * dest_sreg2: we need to allocate another register for it
1481                                          * and then copy from this to dest_sreg2.
1482                                          */
1483                                         int new_dest;
1484                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1485                                         g_assert (new_dest >= 0);
1486                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1487
1488                                         prev_dreg = ins->dreg;
1489                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1490                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1491                                         mono_regstate_free_int (rs, dest_sreg);
1492                                         need_spill = FALSE;
1493                                 }
1494
1495                                 if (is_global_ireg (sreg)) {
1496                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1497                                         insert_before_ins (bb, ins, copy);
1498                                         need_assign = FALSE;
1499                                 }
1500                                 else {
1501                                         val = rs->vassign [sreg];
1502                                         if (val == dest_sreg) {
1503                                                 /* sreg2 is already assigned to the correct register */
1504                                                 need_spill = FALSE;
1505                                         } else if (val < -1) {
1506                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1507                                         } else if (val >= 0) {
1508                                                 /* sreg2 already assigned to another register */
1509                                                 /*
1510                                                  * We couldn't emit a copy from val to dest_sreg2, because
1511                                                  * val might be spilled later while processing this
1512                                                  * instruction. So we spill sreg2 so it can be allocated to
1513                                                  * dest_sreg2.
1514                                                  */
1515                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1516                                         }
1517                                 }
1518
1519                                 if (need_spill) {
1520                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1521                                 }
1522
1523                                 if (need_assign) {
1524                                         if (rs->vassign [sreg] < -1) {
1525                                                 int spill;
1526
1527                                                 /* Need to emit a spill store */
1528                                                 spill = - rs->vassign [sreg] - 1;
1529                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1530                                         }
1531                                         /* force-set sreg2 */
1532                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1533                                 }
1534                         }
1535                         sregs [j] = dest_sreg;
1536                 }
1537                 mono_inst_set_src_registers (ins, sregs);
1538
1539                 /*
1540                  * TRACK DREG
1541                  */
1542                 bank = dreg_bank (spec);
1543                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1544                         prev_dreg = ins->dreg;
1545                 }
1546
1547                 if (spec_dest == 'b') {
1548                         /*
1549                          * The dest reg is read by the instruction, not written, so
1550                          * avoid allocating sreg1/sreg2 to the same reg.
1551                          */
1552                         if (dest_sregs [0] != -1)
1553                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1554                         for (j = 1; j < num_sregs; ++j) {
1555                                 if (dest_sregs [j] != -1)
1556                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1557                         }
1558
1559                         val = rs->vassign [ins->dreg];
1560                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1561                                 /* DREG is already allocated to a register needed for sreg1 */
1562                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1563                         }
1564                 }
1565
1566                 /*
1567                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1568                  * various complex situations.
1569                  */
1570                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1571                         guint32 dreg2, dest_dreg2;
1572
1573                         g_assert (is_soft_reg (ins->dreg, bank));
1574
1575                         if (dest_dreg != -1) {
1576                                 if (rs->vassign [ins->dreg] != dest_dreg)
1577                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1578
1579                                 dreg2 = ins->dreg + 1;
1580                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1581                                 if (dest_dreg2 != -1) {
1582                                         if (rs->vassign [dreg2] != dest_dreg2)
1583                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1584                                 }
1585                         }
1586                 }
1587
1588                 if (dreg_fixed_mask) {
1589                         g_assert (!bank);
1590                         if (is_global_ireg (ins->dreg)) {
1591                                 /*
1592                                  * The argument is already in a hard reg, but that reg is
1593                                  * not usable by this instruction, so allocate a new one.
1594                                  */
1595                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1596                                 if (val < 0)
1597                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1598                                 mono_regstate_free_int (rs, val);
1599                                 dest_dreg = val;
1600
1601                                 /* Fall through */
1602                         }
1603                         else
1604                                 dreg_mask &= dreg_fixed_mask;
1605                 }
1606
1607                 if (is_soft_reg (ins->dreg, bank)) {
1608                         val = rs->vassign [ins->dreg];
1609
1610                         if (val < 0) {
1611                                 int spill = 0;
1612                                 if (val < -1) {
1613                                         /* the register gets spilled after this inst */
1614                                         spill = -val -1;
1615                                 }
1616                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1617                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1618                                 if (spill)
1619                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1620                         }
1621
1622                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1623                         ins->dreg = val;
1624                 }
1625
1626                 /* Handle regpairs */
1627                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1628                         int reg2 = prev_dreg + 1;
1629
1630                         g_assert (!bank);
1631                         g_assert (prev_dreg > -1);
1632                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1633                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1634 #ifdef TARGET_X86
1635                         /* bug #80489 */
1636                         mask &= ~regmask (X86_ECX);
1637 #endif
1638                         val = rs->vassign [reg2];
1639                         if (val < 0) {
1640                                 int spill = 0;
1641                                 if (val < -1) {
1642                                         /* the register gets spilled after this inst */
1643                                         spill = -val -1;
1644                                 }
1645                                 val = mono_regstate_alloc_int (rs, mask);
1646                                 if (val < 0)
1647                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1648                                 if (spill)
1649                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1650                         }
1651                         else {
1652                                 if (! (mask & (regmask (val)))) {
1653                                         val = mono_regstate_alloc_int (rs, mask);
1654                                         if (val < 0)
1655                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1656
1657                                         /* Reallocate hreg to the correct register */
1658                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1659
1660                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1661                                 }
1662                         }
1663
1664                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1665                         assign_reg (cfg, rs, reg2, val, bank);
1666
1667                         dreg_high = val;
1668                         ins->backend.reg3 = val;
1669
1670                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1671                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1672                                 mono_regstate_free_int (rs, val);
1673                         }
1674                 }
1675
1676                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1677                         /*
1678                          * In theory, we could free up the hreg even if the vreg is alive,
1679                          * but branches inside bblocks force us to assign the same hreg
1680                          * to a vreg every time it is encountered.
1681                          */
1682                         int dreg = rs->vassign [prev_dreg];
1683                         g_assert (dreg >= 0);
1684                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1685                         if (G_UNLIKELY (bank))
1686                                 mono_regstate_free_general (rs, dreg, bank);
1687                         else
1688                                 mono_regstate_free_int (rs, dreg);
1689                         rs->vassign [prev_dreg] = -1;
1690                 }
1691
1692                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1693                         /* this instruction only outputs to dest_dreg, need to copy */
1694                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1695                         ins->dreg = dest_dreg;
1696
1697                         if (G_UNLIKELY (bank)) {
1698                                 /* the register we need to free up may be used in another logical regbank
1699                                  * so do a translate just in case.
1700                                  */
1701                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1702                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1703                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1704                         }
1705                         else {
1706                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1707                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1708                         }
1709                 }
1710
1711                 if (spec_dest == 'b') {
1712                         /*
1713                          * The dest reg is read by the instruction, not written, so
1714                          * avoid allocating sreg1/sreg2 to the same reg.
1715                          */
1716                         for (j = 0; j < num_sregs; ++j)
1717                                 if (!sreg_bank (j, spec))
1718                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1719                 }
1720
1721                 /*
1722                  * TRACK CLOBBERING
1723                  */
1724                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1725                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1726                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1727                 }
1728
1729                 if (spec [MONO_INST_CLOB] == 'c') {
1730                         int j, s, dreg, dreg2, cur_bank;
1731                         guint64 clob_mask;
1732
1733                         clob_mask = MONO_ARCH_CALLEE_REGS;
1734
1735                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1736                                 /*
1737                                  * Need to avoid spilling the dreg since the dreg is not really
1738                                  * clobbered by the call.
1739                                  */
1740                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1741                                         dreg = rs->vassign [prev_dreg];
1742                                 else
1743                                         dreg = -1;
1744
1745                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1746                                         dreg2 = rs->vassign [prev_dreg + 1];
1747                                 else
1748                                         dreg2 = -1;
1749
1750                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1751                                         s = regmask (j);
1752                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1753                                                 if ((j != dreg) && (j != dreg2))
1754                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1755                                                 else if (rs->isymbolic [j])
1756                                                         /* The hreg is assigned to the dreg of this instruction */
1757                                                         rs->vassign [rs->isymbolic [j]] = -1;
1758                                                 mono_regstate_free_int (rs, j);
1759                                         }
1760                                 }
1761                         }
1762
1763                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1764                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1765                                         clob_mask = regbank_callee_regs [cur_bank];
1766                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1767                                                 dreg = rs->vassign [prev_dreg];
1768                                         else
1769                                                 dreg = -1;
1770
1771                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1772
1773                                                 /* we are looping though the banks in the outer loop
1774                                                  * so, we don't need to deal with mirrored hregs
1775                                                  * because we will get them in one of the other bank passes.
1776                                                  */
1777                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1778                                                         continue;
1779
1780                                                 s = regmask (j);
1781                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1782                                                         if (j != dreg)
1783                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1784                                                         else if (rs->symbolic [cur_bank] [j])
1785                                                                 /* The hreg is assigned to the dreg of this instruction */
1786                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1787                                                         mono_regstate_free_general (rs, j, cur_bank);
1788                                                 }
1789                                         }
1790                                 }
1791                         }
1792                 }
1793
1794                 /*
1795                  * TRACK ARGUMENT REGS
1796                  */
1797                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1798                         MonoCallInst *call = (MonoCallInst*)ins;
1799                         GSList *list;
1800
1801                         /*
1802                          * This needs to be done before assigning sreg1, so sreg1 will
1803                          * not be assigned one of the argument regs.
1804                          */
1805
1806                         /*
1807                          * Assign all registers in call->out_reg_args to the proper
1808                          * argument registers.
1809                          */
1810
1811                         list = call->out_ireg_args;
1812                         if (list) {
1813                                 while (list) {
1814                                         guint32 regpair;
1815                                         int reg, hreg;
1816
1817                                         regpair = (guint32)(gssize)(list->data);
1818                                         hreg = regpair >> 24;
1819                                         reg = regpair & 0xffffff;
1820
1821                                         assign_reg (cfg, rs, reg, hreg, 0);
1822
1823                                         sreg_masks [0] &= ~(regmask (hreg));
1824
1825                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1826
1827                                         list = g_slist_next (list);
1828                                 }
1829                         }
1830
1831                         list = call->out_freg_args;
1832                         if (list) {
1833                                 while (list) {
1834                                         guint32 regpair;
1835                                         int reg, hreg;
1836
1837                                         regpair = (guint32)(gssize)(list->data);
1838                                         hreg = regpair >> 24;
1839                                         reg = regpair & 0xffffff;
1840
1841                                         assign_reg (cfg, rs, reg, hreg, 1);
1842
1843                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1844
1845                                         list = g_slist_next (list);
1846                                 }
1847                         }
1848                 }
1849
1850                 /*
1851                  * TRACK SREG1
1852                  */
1853                 bank = sreg1_bank (spec);
1854                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1855                         int sreg1 = sregs [0];
1856                         int dest_sreg1 = dest_sregs [0];
1857
1858                         g_assert (is_soft_reg (sreg1, bank));
1859
1860                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1861                         if (dest_sreg1 != -1)
1862                                 g_assert (dest_sreg1 == ins->dreg);
1863                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1864                         g_assert (val >= 0);
1865
1866                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1867                                 // FIXME:
1868                                 g_assert_not_reached ();
1869
1870                         assign_reg (cfg, rs, sreg1, val, bank);
1871
1872                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1873
1874                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1875                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1876                         g_assert (val >= 0);
1877
1878                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1879                                 // FIXME:
1880                                 g_assert_not_reached ();
1881
1882                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1883
1884                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1885
1886                         /* Skip rest of this section */
1887                         dest_sregs [0] = -1;
1888                 }
1889
1890                 if (sreg_fixed_masks [0]) {
1891                         g_assert (!bank);
1892                         if (is_global_ireg (sregs [0])) {
1893                                 /*
1894                                  * The argument is already in a hard reg, but that reg is
1895                                  * not usable by this instruction, so allocate a new one.
1896                                  */
1897                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1898                                 if (val < 0)
1899                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1900                                 mono_regstate_free_int (rs, val);
1901                                 dest_sregs [0] = val;
1902
1903                                 /* Fall through to the dest_sreg1 != -1 case */
1904                         }
1905                         else
1906                                 sreg_masks [0] &= sreg_fixed_masks [0];
1907                 }
1908
1909                 if (dest_sregs [0] != -1) {
1910                         sreg_masks [0] = regmask (dest_sregs [0]);
1911
1912                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1913                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1914                         }
1915                         if (is_global_ireg (sregs [0])) {
1916                                 /* The argument is already in a hard reg, need to copy */
1917                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1918                                 insert_before_ins (bb, ins, copy);
1919                                 sregs [0] = dest_sregs [0];
1920                         }
1921                 }
1922
1923                 if (is_soft_reg (sregs [0], bank)) {
1924                         val = rs->vassign [sregs [0]];
1925                         prev_sregs [0] = sregs [0];
1926                         if (val < 0) {
1927                                 int spill = 0;
1928                                 if (val < -1) {
1929                                         /* the register gets spilled after this inst */
1930                                         spill = -val -1;
1931                                 }
1932
1933                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1934                                         /*
1935                                          * Allocate the same hreg to sreg1 as well so the
1936                                          * peephole can get rid of the move.
1937                                          */
1938                                         sreg_masks [0] = regmask (ins->dreg);
1939                                 }
1940
1941                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1942                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1943                                         sreg_masks [0] = regmask (ins->dreg);
1944
1945                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1946                                 assign_reg (cfg, rs, sregs [0], val, bank);
1947                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1948
1949                                 if (spill) {
1950                                         /*
1951                                          * Need to insert before the instruction since it can
1952                                          * overwrite sreg1.
1953                                          */
1954                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1955                                 }
1956                         }
1957                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1958                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1959                                 insert_before_ins (bb, ins, copy);
1960                                 for (j = 1; j < num_sregs; ++j)
1961                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1962                                 val = dest_sregs [0];
1963                         }
1964
1965                         sregs [0] = val;
1966                 }
1967                 else {
1968                         prev_sregs [0] = -1;
1969                 }
1970                 mono_inst_set_src_registers (ins, sregs);
1971
1972                 for (j = 1; j < num_sregs; ++j)
1973                         sreg_masks [j] &= ~(regmask (sregs [0]));
1974
1975                 /* Handle the case when sreg1 is a regpair but dreg is not */
1976                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1977                         int reg2 = prev_sregs [0] + 1;
1978
1979                         g_assert (!bank);
1980                         g_assert (prev_sregs [0] > -1);
1981                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1982                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1983                         val = rs->vassign [reg2];
1984                         if (val < 0) {
1985                                 int spill = 0;
1986                                 if (val < -1) {
1987                                         /* the register gets spilled after this inst */
1988                                         spill = -val -1;
1989                                 }
1990                                 val = mono_regstate_alloc_int (rs, mask);
1991                                 if (val < 0)
1992                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1993                                 if (spill)
1994                                         g_assert_not_reached ();
1995                         }
1996                         else {
1997                                 if (! (mask & (regmask (val)))) {
1998                                         /* The vreg is already allocated to a wrong hreg */
1999                                         /* FIXME: */
2000                                         g_assert_not_reached ();
2001 #if 0
2002                                         val = mono_regstate_alloc_int (rs, mask);
2003                                         if (val < 0)
2004                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2005
2006                                         /* Reallocate hreg to the correct register */
2007                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2008
2009                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2010 #endif
2011                                 }
2012                         }
2013
2014                         sreg1_high = val;
2015                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2016                         assign_reg (cfg, rs, reg2, val, bank);
2017                 }
2018
2019                 /* Handle dreg==sreg1 */
2020                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2021                         MonoInst *sreg2_copy = NULL;
2022                         MonoInst *copy;
2023                         int bank = reg_bank (spec_src1);
2024
2025                         if (ins->dreg == sregs [1]) {
2026                                 /*
2027                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2028                                  * register for it.
2029                                  */
2030                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2031
2032                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2033                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2034                                 prev_sregs [1] = sregs [1] = reg2;
2035
2036                                 if (G_UNLIKELY (bank))
2037                                         mono_regstate_free_general (rs, reg2, bank);
2038                                 else
2039                                         mono_regstate_free_int (rs, reg2);
2040                         }
2041
2042                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2043                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2044                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2045                                         /* FIXME: */
2046                                         g_assert_not_reached ();
2047
2048                                 /*
2049                                  * sreg1 and dest are already allocated to the same regpair by the
2050                                  * SREG1 allocation code.
2051                                  */
2052                                 g_assert (sregs [0] == ins->dreg);
2053                                 g_assert (dreg_high == sreg1_high);
2054                         }
2055
2056                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2057                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2058                         insert_before_ins (bb, ins, copy);
2059
2060                         if (sreg2_copy)
2061                                 insert_before_ins (bb, copy, sreg2_copy);
2062
2063                         /*
2064                          * Need to prevent sreg2 to be allocated to sreg1, since that
2065                          * would screw up the previous copy.
2066                          */
2067                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2068                         /* we set sreg1 to dest as well */
2069                         prev_sregs [0] = sregs [0] = ins->dreg;
2070                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2071                 }
2072                 mono_inst_set_src_registers (ins, sregs);
2073
2074                 /*
2075                  * TRACK SREG2, 3, ...
2076                  */
2077                 for (j = 1; j < num_sregs; ++j) {
2078                         int k;
2079
2080                         bank = sreg_bank (j, spec);
2081                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2082                                 g_assert_not_reached ();
2083
2084                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2085                                 /*
2086                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2087                                  * allocating it to the fixed reg.
2088                                  */
2089                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2090                                 insert_before_ins (bb, ins, copy);
2091                                 sregs [j] = dest_sregs [j];
2092                         } else if (is_soft_reg (sregs [j], bank)) {
2093                                 val = rs->vassign [sregs [j]];
2094
2095                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2096                                         /*
2097                                          * The sreg is already allocated to a hreg, but not to the fixed
2098                                          * reg required by the instruction. Spill the sreg, so it can be
2099                                          * allocated to the fixed reg by the code below.
2100                                          */
2101                                         /* Currently, this code should only be hit for CAS */
2102                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2103                                         val = rs->vassign [sregs [j]];
2104                                 }
2105
2106                                 if (val < 0) {
2107                                         int spill = 0;
2108                                         if (val < -1) {
2109                                                 /* the register gets spilled after this inst */
2110                                                 spill = -val -1;
2111                                         }
2112                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2113                                         assign_reg (cfg, rs, sregs [j], val, bank);
2114                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2115                                         if (spill) {
2116                                                 /*
2117                                                  * Need to insert before the instruction since it can
2118                                                  * overwrite sreg2.
2119                                                  */
2120                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2121                                         }
2122                                 }
2123                                 sregs [j] = val;
2124                                 for (k = j + 1; k < num_sregs; ++k)
2125                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2126                         }
2127                         else {
2128                                 prev_sregs [j] = -1;
2129                         }
2130                 }
2131                 mono_inst_set_src_registers (ins, sregs);
2132
2133                 /* Sanity check */
2134                 /* Do this only for CAS for now */
2135                 for (j = 1; j < num_sregs; ++j) {
2136                         int sreg = sregs [j];
2137                         int dest_sreg = dest_sregs [j];
2138
2139                         if (j == 2 && dest_sreg != -1) {
2140                                 int k;
2141
2142                                 g_assert (sreg == dest_sreg);
2143
2144                                 for (k = 0; k < num_sregs; ++k) {
2145                                         if (k != j)
2146                                                 g_assert (sregs [k] != dest_sreg);
2147                                 }
2148                         }
2149                 }
2150
2151                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2152                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2153                         mono_regstate_free_int (rs, ins->sreg1);
2154                 }
2155                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2156                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2157                         mono_regstate_free_int (rs, ins->sreg2);
2158                 }*/
2159
2160                 DEBUG (mono_print_ins_index (i, ins));
2161         }
2162
2163         // FIXME: Set MAX_FREGS to 8
2164         // FIXME: Optimize generated code
2165 #if MONO_ARCH_USE_FPSTACK
2166         /*
2167          * Make a forward pass over the code, simulating the fp stack, making sure the
2168          * arguments required by the fp opcodes are at the top of the stack.
2169          */
2170         if (has_fp) {
2171                 MonoInst *prev = NULL;
2172                 MonoInst *fxch;
2173                 int tmp;
2174
2175                 g_assert (num_sregs <= 2);
2176
2177                 for (ins = bb->code; ins; ins = ins->next) {
2178                         spec = ins_get_spec (ins->opcode);
2179
2180                         DEBUG (printf ("processing:"));
2181                         DEBUG (mono_print_ins_index (0, ins));
2182
2183                         if (ins->opcode == OP_FMOVE) {
2184                                 /* Do it by renaming the source to the destination on the stack */
2185                                 // FIXME: Is this correct ?
2186                                 for (i = 0; i < sp; ++i)
2187                                         if (fpstack [i] == ins->sreg1)
2188                                                 fpstack [i] = ins->dreg;
2189                                 prev = ins;
2190                                 continue;
2191                         }
2192
2193                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2194                                 /* Arg1 must be in %st(1) */
2195                                 g_assert (prev);
2196
2197                                 i = 0;
2198                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2199                                         i ++;
2200                                 g_assert (i < sp);
2201
2202                                 if (sp - 1 - i > 0) {
2203                                         /* First move it to %st(0) */
2204                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2205
2206                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2207                                         fxch->inst_imm = sp - 1 - i;
2208
2209                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2210                                         prev = fxch;
2211
2212                                         tmp = fpstack [sp - 1];
2213                                         fpstack [sp - 1] = fpstack [i];
2214                                         fpstack [i] = tmp;
2215                                 }
2216
2217                                 /* Then move it to %st(1) */
2218                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2219
2220                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2221                                 fxch->inst_imm = 1;
2222
2223                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2224                                 prev = fxch;
2225
2226                                 tmp = fpstack [sp - 1];
2227                                 fpstack [sp - 1] = fpstack [sp - 2];
2228                                 fpstack [sp - 2] = tmp;
2229                         }
2230
2231                         if (sreg2_is_fp (spec)) {
2232                                 g_assert (sp > 0);
2233
2234                                 if (fpstack [sp - 1] != ins->sreg2) {
2235                                         g_assert (prev);
2236
2237                                         i = 0;
2238                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2239                                                 i ++;
2240                                         g_assert (i < sp);
2241
2242                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2243
2244                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2245                                         fxch->inst_imm = sp - 1 - i;
2246
2247                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2248                                         prev = fxch;
2249
2250                                         tmp = fpstack [sp - 1];
2251                                         fpstack [sp - 1] = fpstack [i];
2252                                         fpstack [i] = tmp;
2253                                 }
2254
2255                                 sp --;
2256                         }
2257
2258                         if (sreg1_is_fp (spec)) {
2259                                 g_assert (sp > 0);
2260
2261                                 if (fpstack [sp - 1] != ins->sreg1) {
2262                                         g_assert (prev);
2263
2264                                         i = 0;
2265                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2266                                                 i ++;
2267                                         g_assert (i < sp);
2268
2269                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2270
2271                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2272                                         fxch->inst_imm = sp - 1 - i;
2273
2274                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2275                                         prev = fxch;
2276
2277                                         tmp = fpstack [sp - 1];
2278                                         fpstack [sp - 1] = fpstack [i];
2279                                         fpstack [i] = tmp;
2280                                 }
2281
2282                                 sp --;
2283                         }
2284
2285                         if (dreg_is_fp (spec)) {
2286                                 g_assert (sp < 8);
2287                                 fpstack [sp ++] = ins->dreg;
2288                         }
2289
2290                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2291                                 printf ("\t[");
2292                                 for (i = 0; i < sp; ++i)
2293                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2294                                 printf ("]\n");
2295                         }
2296
2297                         prev = ins;
2298                 }
2299
2300                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2301                         /* Remove remaining items from the fp stack */
2302                         /*
2303                          * These can remain for example as a result of a dead fmove like in
2304                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2305                          */
2306                         while (sp) {
2307                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2308                                 mono_add_ins_to_end (bb, ins);
2309                                 sp --;
2310                         }
2311                 }
2312         }
2313 #endif
2314 }
2315
2316 CompRelation
2317 mono_opcode_to_cond (int opcode)
2318 {
2319         switch (opcode) {
2320         case OP_CEQ:
2321         case OP_IBEQ:
2322         case OP_ICEQ:
2323         case OP_LBEQ:
2324         case OP_LCEQ:
2325         case OP_FBEQ:
2326         case OP_FCEQ:
2327         case OP_RBEQ:
2328         case OP_RCEQ:
2329         case OP_COND_EXC_EQ:
2330         case OP_COND_EXC_IEQ:
2331         case OP_CMOV_IEQ:
2332         case OP_CMOV_LEQ:
2333                 return CMP_EQ;
2334         case OP_FCNEQ:
2335         case OP_ICNEQ:
2336         case OP_IBNE_UN:
2337         case OP_LBNE_UN:
2338         case OP_FBNE_UN:
2339         case OP_COND_EXC_NE_UN:
2340         case OP_COND_EXC_INE_UN:
2341         case OP_CMOV_INE_UN:
2342         case OP_CMOV_LNE_UN:
2343                 return CMP_NE;
2344         case OP_FCLE:
2345         case OP_ICLE:
2346         case OP_IBLE:
2347         case OP_LBLE:
2348         case OP_FBLE:
2349         case OP_CMOV_ILE:
2350         case OP_CMOV_LLE:
2351                 return CMP_LE;
2352         case OP_FCGE:
2353         case OP_ICGE:
2354         case OP_IBGE:
2355         case OP_LBGE:
2356         case OP_FBGE:
2357         case OP_CMOV_IGE:
2358         case OP_CMOV_LGE:
2359                 return CMP_GE;
2360         case OP_CLT:
2361         case OP_IBLT:
2362         case OP_ICLT:
2363         case OP_LBLT:
2364         case OP_LCLT:
2365         case OP_FBLT:
2366         case OP_FCLT:
2367         case OP_RBLT:
2368         case OP_RCLT:
2369         case OP_COND_EXC_LT:
2370         case OP_COND_EXC_ILT:
2371         case OP_CMOV_ILT:
2372         case OP_CMOV_LLT:
2373                 return CMP_LT;
2374         case OP_CGT:
2375         case OP_IBGT:
2376         case OP_ICGT:
2377         case OP_LBGT:
2378         case OP_LCGT:
2379         case OP_FBGT:
2380         case OP_FCGT:
2381         case OP_RBGT:
2382         case OP_RCGT:
2383         case OP_COND_EXC_GT:
2384         case OP_COND_EXC_IGT:
2385         case OP_CMOV_IGT:
2386         case OP_CMOV_LGT:
2387                 return CMP_GT;
2388
2389         case OP_ICLE_UN:
2390         case OP_IBLE_UN:
2391         case OP_LBLE_UN:
2392         case OP_FBLE_UN:
2393         case OP_COND_EXC_LE_UN:
2394         case OP_COND_EXC_ILE_UN:
2395         case OP_CMOV_ILE_UN:
2396         case OP_CMOV_LLE_UN:
2397                 return CMP_LE_UN;
2398
2399         case OP_ICGE_UN:
2400         case OP_IBGE_UN:
2401         case OP_LBGE_UN:
2402         case OP_FBGE_UN:
2403         case OP_CMOV_IGE_UN:
2404         case OP_CMOV_LGE_UN:
2405                 return CMP_GE_UN;
2406         case OP_CLT_UN:
2407         case OP_IBLT_UN:
2408         case OP_ICLT_UN:
2409         case OP_LBLT_UN:
2410         case OP_LCLT_UN:
2411         case OP_FBLT_UN:
2412         case OP_FCLT_UN:
2413         case OP_RBLT_UN:
2414         case OP_RCLT_UN:
2415         case OP_COND_EXC_LT_UN:
2416         case OP_COND_EXC_ILT_UN:
2417         case OP_CMOV_ILT_UN:
2418         case OP_CMOV_LLT_UN:
2419                 return CMP_LT_UN;
2420         case OP_CGT_UN:
2421         case OP_IBGT_UN:
2422         case OP_ICGT_UN:
2423         case OP_LBGT_UN:
2424         case OP_LCGT_UN:
2425         case OP_FCGT_UN:
2426         case OP_FBGT_UN:
2427         case OP_RCGT_UN:
2428         case OP_RBGT_UN:
2429         case OP_COND_EXC_GT_UN:
2430         case OP_COND_EXC_IGT_UN:
2431         case OP_CMOV_IGT_UN:
2432         case OP_CMOV_LGT_UN:
2433                 return CMP_GT_UN;
2434         default:
2435                 printf ("%s\n", mono_inst_name (opcode));
2436                 g_assert_not_reached ();
2437                 return 0;
2438         }
2439 }
2440
2441 CompRelation
2442 mono_negate_cond (CompRelation cond)
2443 {
2444         switch (cond) {
2445         case CMP_EQ:
2446                 return CMP_NE;
2447         case CMP_NE:
2448                 return CMP_EQ;
2449         case CMP_LE:
2450                 return CMP_GT;
2451         case CMP_GE:
2452                 return CMP_LT;
2453         case CMP_LT:
2454                 return CMP_GE;
2455         case CMP_GT:
2456                 return CMP_LE;
2457         case CMP_LE_UN:
2458                 return CMP_GT_UN;
2459         case CMP_GE_UN:
2460                 return CMP_LT_UN;
2461         case CMP_LT_UN:
2462                 return CMP_GE_UN;
2463         case CMP_GT_UN:
2464                 return CMP_LE_UN;
2465         default:
2466                 g_assert_not_reached ();
2467         }
2468 }
2469
2470 CompType
2471 mono_opcode_to_type (int opcode, int cmp_opcode)
2472 {
2473         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2474                 return CMP_TYPE_L;
2475         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2476                 return CMP_TYPE_I;
2477         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2478                 return CMP_TYPE_I;
2479         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2480                 return CMP_TYPE_L;
2481         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2482                 return CMP_TYPE_L;
2483         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2484                 return CMP_TYPE_F;
2485         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2486                 return CMP_TYPE_F;
2487         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2488                 return CMP_TYPE_I;
2489         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2490                 switch (cmp_opcode) {
2491                 case OP_ICOMPARE:
2492                 case OP_ICOMPARE_IMM:
2493                         return CMP_TYPE_I;
2494                 default:
2495                         return CMP_TYPE_L;
2496                 }
2497         } else {
2498                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2499                 return 0;
2500         }
2501 }
2502
2503 #endif /* DISABLE_JIT */
2504
2505 gboolean
2506 mono_is_regsize_var (MonoType *t)
2507 {
2508         t = mini_type_get_underlying_type (NULL, t);
2509         switch (t->type) {
2510         case MONO_TYPE_I1:
2511         case MONO_TYPE_U1:
2512         case MONO_TYPE_I2:
2513         case MONO_TYPE_U2:
2514         case MONO_TYPE_I4:
2515         case MONO_TYPE_U4:
2516         case MONO_TYPE_I:
2517         case MONO_TYPE_U:
2518         case MONO_TYPE_PTR:
2519         case MONO_TYPE_FNPTR:
2520 #if SIZEOF_REGISTER == 8
2521         case MONO_TYPE_I8:
2522         case MONO_TYPE_U8:
2523 #endif
2524                 return TRUE;
2525         case MONO_TYPE_OBJECT:
2526         case MONO_TYPE_STRING:
2527         case MONO_TYPE_CLASS:
2528         case MONO_TYPE_SZARRAY:
2529         case MONO_TYPE_ARRAY:
2530                 return TRUE;
2531         case MONO_TYPE_GENERICINST:
2532                 if (!mono_type_generic_inst_is_valuetype (t))
2533                         return TRUE;
2534                 return FALSE;
2535         case MONO_TYPE_VALUETYPE:
2536                 return FALSE;
2537         default:
2538                 return FALSE;
2539         }
2540 }
2541
2542 #ifndef DISABLE_JIT
2543
2544 /*
2545  * mono_peephole_ins:
2546  *
2547  *   Perform some architecture independent peephole optimizations.
2548  */
2549 void
2550 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2551 {
2552         int filter = FILTER_IL_SEQ_POINT;
2553         MonoInst *last_ins = mono_inst_prev (ins, filter);
2554
2555         switch (ins->opcode) {
2556         case OP_MUL_IMM:
2557                 /* remove unnecessary multiplication with 1 */
2558                 if (ins->inst_imm == 1) {
2559                         if (ins->dreg != ins->sreg1)
2560                                 ins->opcode = OP_MOVE;
2561                         else
2562                                 MONO_DELETE_INS (bb, ins);
2563                 }
2564                 break;
2565         case OP_LOAD_MEMBASE:
2566         case OP_LOADI4_MEMBASE:
2567                 /*
2568                  * Note: if reg1 = reg2 the load op is removed
2569                  *
2570                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2571                  * OP_LOAD_MEMBASE offset(basereg), reg2
2572                  * -->
2573                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2574                  * OP_MOVE reg1, reg2
2575                  */
2576                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2577                         last_ins = mono_inst_prev (ins, filter);
2578                 if (last_ins &&
2579                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2580                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2581                         ins->inst_basereg == last_ins->inst_destbasereg &&
2582                         ins->inst_offset == last_ins->inst_offset) {
2583                         if (ins->dreg == last_ins->sreg1) {
2584                                 MONO_DELETE_INS (bb, ins);
2585                                 break;
2586                         } else {
2587                                 ins->opcode = OP_MOVE;
2588                                 ins->sreg1 = last_ins->sreg1;
2589                         }
2590
2591                         /*
2592                          * Note: reg1 must be different from the basereg in the second load
2593                          * Note: if reg1 = reg2 is equal then second load is removed
2594                          *
2595                          * OP_LOAD_MEMBASE offset(basereg), reg1
2596                          * OP_LOAD_MEMBASE offset(basereg), reg2
2597                          * -->
2598                          * OP_LOAD_MEMBASE offset(basereg), reg1
2599                          * OP_MOVE reg1, reg2
2600                          */
2601                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2602                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2603                           ins->inst_basereg != last_ins->dreg &&
2604                           ins->inst_basereg == last_ins->inst_basereg &&
2605                           ins->inst_offset == last_ins->inst_offset) {
2606
2607                         if (ins->dreg == last_ins->dreg) {
2608                                 MONO_DELETE_INS (bb, ins);
2609                         } else {
2610                                 ins->opcode = OP_MOVE;
2611                                 ins->sreg1 = last_ins->dreg;
2612                         }
2613
2614                         //g_assert_not_reached ();
2615
2616 #if 0
2617                         /*
2618                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2619                          * OP_LOAD_MEMBASE offset(basereg), reg
2620                          * -->
2621                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2622                          * OP_ICONST reg, imm
2623                          */
2624                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2625                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2626                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2627                                    ins->inst_offset == last_ins->inst_offset) {
2628                         ins->opcode = OP_ICONST;
2629                         ins->inst_c0 = last_ins->inst_imm;
2630                         g_assert_not_reached (); // check this rule
2631 #endif
2632                 }
2633                 break;
2634         case OP_LOADI1_MEMBASE:
2635         case OP_LOADU1_MEMBASE:
2636                 /*
2637                  * Note: if reg1 = reg2 the load op is removed
2638                  *
2639                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2640                  * OP_LOAD_MEMBASE offset(basereg), reg2
2641                  * -->
2642                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2643                  * OP_MOVE reg1, reg2
2644                  */
2645                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2646                         ins->inst_basereg == last_ins->inst_destbasereg &&
2647                         ins->inst_offset == last_ins->inst_offset) {
2648                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2649                         ins->sreg1 = last_ins->sreg1;
2650                 }
2651                 break;
2652         case OP_LOADI2_MEMBASE:
2653         case OP_LOADU2_MEMBASE:
2654                 /*
2655                  * Note: if reg1 = reg2 the load op is removed
2656                  *
2657                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2658                  * OP_LOAD_MEMBASE offset(basereg), reg2
2659                  * -->
2660                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2661                  * OP_MOVE reg1, reg2
2662                  */
2663                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2664                         ins->inst_basereg == last_ins->inst_destbasereg &&
2665                         ins->inst_offset == last_ins->inst_offset) {
2666 #if SIZEOF_REGISTER == 8
2667                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2668 #else
2669                         /* The definition of OP_PCONV_TO_U2 is wrong */
2670                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2671 #endif
2672                         ins->sreg1 = last_ins->sreg1;
2673                 }
2674                 break;
2675         case OP_MOVE:
2676         case OP_FMOVE:
2677                 /*
2678                  * Removes:
2679                  *
2680                  * OP_MOVE reg, reg
2681                  */
2682                 if (ins->dreg == ins->sreg1) {
2683                         MONO_DELETE_INS (bb, ins);
2684                         break;
2685                 }
2686                 /*
2687                  * Removes:
2688                  *
2689                  * OP_MOVE sreg, dreg
2690                  * OP_MOVE dreg, sreg
2691                  */
2692                 if (last_ins && last_ins->opcode == ins->opcode &&
2693                         ins->sreg1 == last_ins->dreg &&
2694                         ins->dreg == last_ins->sreg1) {
2695                         MONO_DELETE_INS (bb, ins);
2696                 }
2697                 break;
2698         case OP_NOP:
2699                 MONO_DELETE_INS (bb, ins);
2700                 break;
2701         }
2702 }
2703
2704 int
2705 mini_exception_id_by_name (const char *name)
2706 {
2707         if (strcmp (name, "IndexOutOfRangeException") == 0)
2708                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2709         if (strcmp (name, "OverflowException") == 0)
2710                 return MONO_EXC_OVERFLOW;
2711         if (strcmp (name, "ArithmeticException") == 0)
2712                 return MONO_EXC_ARITHMETIC;
2713         if (strcmp (name, "DivideByZeroException") == 0)
2714                 return MONO_EXC_DIVIDE_BY_ZERO;
2715         if (strcmp (name, "InvalidCastException") == 0)
2716                 return MONO_EXC_INVALID_CAST;
2717         if (strcmp (name, "NullReferenceException") == 0)
2718                 return MONO_EXC_NULL_REF;
2719         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2720                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2721         if (strcmp (name, "ArgumentException") == 0)
2722                 return MONO_EXC_ARGUMENT;
2723         g_error ("Unknown intrinsic exception %s\n", name);
2724         return -1;
2725 }
2726
2727 gboolean
2728 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2729 {
2730         MonoClass *klass;
2731         gpointer iter;
2732         MonoClassField *field;
2733         MonoType *ftype, *prev_ftype = NULL;
2734         int nfields = 0;
2735
2736         klass = mono_class_from_mono_type (t);
2737         iter = NULL;
2738         while ((field = mono_class_get_fields (klass, &iter))) {
2739                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2740                         continue;
2741                 ftype = mono_field_get_type (field);
2742                 ftype = mini_native_type_replace_type (ftype);
2743
2744                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2745                         int nested_nfields, nested_esize;
2746
2747                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2748                                 return FALSE;
2749                         if (nested_esize == 4)
2750                                 ftype = &mono_defaults.single_class->byval_arg;
2751                         else
2752                                 ftype = &mono_defaults.double_class->byval_arg;
2753                         if (prev_ftype && prev_ftype->type != ftype->type)
2754                                 return FALSE;
2755                         prev_ftype = ftype;
2756                         nfields += nested_nfields;
2757                         // FIXME: Nested float structs are aligned to 8 bytes
2758                         if (ftype->type == MONO_TYPE_R4)
2759                                 return FALSE;
2760                 } else {
2761                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2762                                 return FALSE;
2763                         if (prev_ftype && prev_ftype->type != ftype->type)
2764                                 return FALSE;
2765                         prev_ftype = ftype;
2766                         nfields ++;
2767                 }
2768         }
2769         if (nfields == 0 || nfields > 4)
2770                 return FALSE;
2771         *out_nfields = nfields;
2772         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2773         return TRUE;
2774 }
2775
2776 MonoRegState*
2777 mono_regstate_new (void)
2778 {
2779         MonoRegState* rs = g_new0 (MonoRegState, 1);
2780
2781         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2782 #ifdef MONO_ARCH_NEED_SIMD_BANK
2783         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2784 #endif
2785
2786         return rs;
2787 }
2788
2789 void
2790 mono_regstate_free (MonoRegState *rs) {
2791         g_free (rs->vassign);
2792         g_free (rs);
2793 }
2794
2795 #endif /* DISABLE_JIT */