2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
12 #include <mono/metadata/appdomain.h>
13 #include <mono/metadata/debug-helpers.h>
14 #include <mono/metadata/threads.h>
15 #include <mono/metadata/profiler-private.h>
16 #include <mono/utils/mono-math.h>
21 #include "mini-arch.h"
23 #define DEBUG(a) if (cfg->verbose_level > 1) a
25 #if defined(__x86_64__)
26 const char * const amd64_desc [OP_LAST];
27 static const char*const * ins_spec = amd64_desc;
28 #elif defined(__sparc__) || defined(sparc)
29 const char * const sparc_desc [OP_LAST];
30 static const char*const * ins_spec = sparc_desc;
31 #elif defined(__i386__)
32 const char * const pentium_desc [OP_LAST];
33 static const char*const * ins_spec = pentium_desc;
34 #elif defined(__ia64__)
35 const char * const ia64_desc [OP_LAST];
36 static const char*const * ins_spec = ia64_desc;
38 #error "Not implemented"
41 #define use_fpstack MONO_ARCH_USE_FPSTACK
44 mono_regname_full (int reg, gboolean fp)
47 return mono_arch_fregname (reg);
49 return mono_arch_regname (reg);
53 mono_call_inst_add_outarg_reg (MonoCallInst *call, int vreg, int hreg, gboolean fp)
57 regpair = (((guint32)hreg) << 24) + vreg;
59 call->out_freg_args = g_slist_append (call->out_freg_args, (gpointer)(gssize)(regpair));
61 call->out_ireg_args = g_slist_append (call->out_ireg_args, (gpointer)(gssize)(regpair));
65 * returns the offset used by spillvar. It allocates a new
66 * spill variable if necessary.
69 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
71 MonoSpillInfo **si, *info;
74 si = &cfg->spill_info;
76 while (i <= spillvar) {
79 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
81 cfg->stack_offset += sizeof (gpointer);
82 info->offset = - cfg->stack_offset;
92 g_assert_not_reached ();
97 * returns the offset used by spillvar. It allocates a new
98 * spill float variable if necessary.
99 * (same as mono_spillvar_offset but for float)
102 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
104 MonoSpillInfo **si, *info;
107 si = &cfg->spill_info_float;
109 while (i <= spillvar) {
112 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
114 cfg->stack_offset += sizeof (double);
115 info->offset = - cfg->stack_offset;
119 return (*si)->offset;
125 g_assert_not_reached ();
130 * Creates a store for spilled floating point items
133 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
136 MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
138 store->inst_destbasereg = cfg->frame_reg;
139 store->inst_offset = mono_spillvar_offset_float (cfg, spill);
141 DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)store->inst_offset, reg));
146 * Creates a load for spilled floating point items
149 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
152 MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
154 load->inst_basereg = cfg->frame_reg;
155 load->inst_offset = mono_spillvar_offset_float (cfg, spill);
157 DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)load->inst_offset, reg));
161 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
162 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
163 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (1 << (r))))
164 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (1 << (r))))
165 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (1 << (r))))
166 #define is_local_freg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_FREGS & (1 << (r))))
167 #define ireg_is_freeable(r) is_local_ireg ((r))
168 #define freg_is_freeable(r) is_hard_freg ((r))
170 #define reg_is_freeable(r,fp) ((fp) ? freg_is_freeable ((r)) : ireg_is_freeable ((r)))
171 #define is_hard_reg(r,fp) ((fp) ? ((r) < MONO_MAX_FREGS) : ((r) < MONO_MAX_IREGS))
172 #define is_soft_reg(r,fp) (!is_hard_reg((r),(fp)))
173 #define rassign(cfg,reg,fp) ((fp) ? (cfg)->rs->fassign [(reg)] : (cfg)->rs->iassign [(reg)])
174 #define sreg1_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC1] == 'f')
175 #define sreg2_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC2] == 'f')
177 #ifdef MONO_ARCH_INST_IS_FLOAT
178 #define dreg_is_fp(ins) (MONO_ARCH_INST_IS_FLOAT (ins_spec [(ins)->opcode] [MONO_INST_DEST]))
180 #define dreg_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_DEST] == 'f')
183 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (1 << MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1)) : MONO_ARCH_CALLEE_REGS)
190 int flags; /* used to track fp spill/load */
191 guint32 preferred_mask; /* the hreg where the register should be allocated, or 0 */
195 print_ins (int i, MonoInst *ins)
197 const char *spec = ins_spec [ins->opcode];
198 g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
200 g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
202 if (spec [MONO_INST_DEST]) {
203 gboolean fp = (spec [MONO_INST_DEST] == 'f');
204 if (is_soft_reg (ins->dreg, fp))
205 g_print (" R%d <-", ins->dreg);
206 else if (spec [MONO_INST_DEST] == 'b') {
207 if (ins->inst_offset == 0)
208 g_print (" [%s] <-", mono_arch_regname (ins->dreg));
210 g_print (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
212 g_print (" %s <-", mono_regname_full (ins->dreg, fp));
214 if (spec [MONO_INST_SRC1]) {
215 gboolean fp = (spec [MONO_INST_SRC1] == 'f');
216 if (is_soft_reg (ins->sreg1, fp))
217 g_print (" R%d", ins->sreg1);
218 else if (spec [MONO_INST_SRC1] == 'b')
219 g_print (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
221 g_print (" %s", mono_regname_full (ins->sreg1, fp));
223 if (spec [MONO_INST_SRC2]) {
224 gboolean fp = (spec [MONO_INST_SRC2] == 'f');
225 if (is_soft_reg (ins->sreg2, fp))
226 g_print (" R%d", ins->sreg2);
228 g_print (" %s", mono_regname_full (ins->sreg2, fp));
230 if (spec [MONO_INST_CLOB])
231 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
236 print_regtrack (RegTrack *t, int num)
242 for (i = 0; i < num; ++i) {
245 if (i >= MONO_MAX_IREGS) {
246 g_snprintf (buf, sizeof(buf), "R%d", i);
249 r = mono_arch_regname (i);
250 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
254 typedef struct InstList InstList;
262 static inline InstList*
263 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
265 InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
275 * Force the spilling of the variable in the symbolic register 'reg'.
278 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg, gboolean fp)
282 int *assign, *symbolic;
285 assign = cfg->rs->fassign;
286 symbolic = cfg->rs->fsymbolic;
289 assign = cfg->rs->iassign;
290 symbolic = cfg->rs->isymbolic;
294 /*i = cfg->rs->isymbolic [sel];
295 g_assert (i == reg);*/
297 spill = ++cfg->spill_count;
298 assign [i] = -spill - 1;
300 mono_regstate_free_float (cfg->rs, sel);
302 mono_regstate_free_int (cfg->rs, sel);
303 /* we need to create a spill var and insert a load to sel after the current instruction */
305 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
307 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
309 load->inst_basereg = cfg->frame_reg;
310 load->inst_offset = mono_spillvar_offset (cfg, spill);
312 while (ins->next != item->prev->data)
315 load->next = ins->next;
317 DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
319 i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
321 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
328 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg, gboolean fp)
332 int *assign, *symbolic;
335 assign = cfg->rs->fassign;
336 symbolic = cfg->rs->fsymbolic;
339 assign = cfg->rs->iassign;
340 symbolic = cfg->rs->isymbolic;
343 DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
344 /* exclude the registers in the current instruction */
345 if ((sreg1_is_fp (ins) == fp) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, fp) || (is_soft_reg (ins->sreg1, fp) && rassign (cfg, ins->sreg1, fp) >= 0))) {
346 if (is_soft_reg (ins->sreg1, fp))
347 regmask &= ~ (1 << rassign (cfg, ins->sreg1, fp));
349 regmask &= ~ (1 << ins->sreg1);
350 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_regname_full (ins->sreg1, fp)));
352 if ((sreg2_is_fp (ins) == fp) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, fp) || (is_soft_reg (ins->sreg2, fp) && rassign (cfg, ins->sreg2, fp) >= 0))) {
353 if (is_soft_reg (ins->sreg2, fp))
354 regmask &= ~ (1 << rassign (cfg, ins->sreg2, fp));
356 regmask &= ~ (1 << ins->sreg2);
357 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_regname_full (ins->sreg2, fp), ins->sreg2));
359 if ((dreg_is_fp (ins) == fp) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, fp)) {
360 regmask &= ~ (1 << ins->dreg);
361 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, fp)));
364 DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
365 g_assert (regmask); /* need at least a register we can free */
367 /* we should track prev_use and spill the register that's farther */
369 for (i = 0; i < MONO_MAX_FREGS; ++i) {
370 if (regmask & (1 << i)) {
372 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_fregname (sel), cfg->rs->fsymbolic [sel]));
377 i = cfg->rs->fsymbolic [sel];
378 spill = ++cfg->spill_count;
379 cfg->rs->fassign [i] = -spill - 1;
380 mono_regstate_free_float (cfg->rs, sel);
383 for (i = 0; i < MONO_MAX_IREGS; ++i) {
384 if (regmask & (1 << i)) {
386 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->isymbolic [sel]));
391 i = cfg->rs->isymbolic [sel];
392 spill = ++cfg->spill_count;
393 cfg->rs->iassign [i] = -spill - 1;
394 mono_regstate_free_int (cfg->rs, sel);
397 /* we need to create a spill var and insert a load to sel after the current instruction */
398 MONO_INST_NEW (cfg, load, fp ? OP_LOADR8_MEMBASE : OP_LOAD_MEMBASE);
400 load->inst_basereg = cfg->frame_reg;
401 load->inst_offset = mono_spillvar_offset (cfg, spill);
403 while (ins->next != item->prev->data)
406 load->next = ins->next;
408 DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
410 i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
412 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
419 free_up_ireg (MonoCompile *cfg, InstList *item, MonoInst *ins, int hreg)
421 if (!(cfg->rs->ifree_mask & (1 << hreg))) {
422 DEBUG (g_print ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
423 get_register_force_spilling (cfg, item, ins, cfg->rs->isymbolic [hreg], FALSE);
424 mono_regstate_free_int (cfg->rs, hreg);
429 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins, gboolean fp)
434 MONO_INST_NEW (cfg, copy, OP_FMOVE);
436 MONO_INST_NEW (cfg, copy, OP_MOVE);
441 copy->next = ins->next;
444 DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
449 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins, gboolean fp)
452 MONO_INST_NEW (cfg, store, fp ? OP_STORER8_MEMBASE_REG : OP_STORE_MEMBASE_REG);
454 store->inst_destbasereg = cfg->frame_reg;
455 store->inst_offset = mono_spillvar_offset (cfg, spill);
457 store->next = ins->next;
460 DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, fp)));
465 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
469 prev = item->next->data;
471 while (prev->next != ins)
473 to_insert->next = ins;
474 prev->next = to_insert;
476 to_insert->next = ins;
479 * needed otherwise in the next instruction we can add an ins to the
480 * end and that would get past this instruction.
482 item->data = to_insert;
485 /* flags used in reginfo->flags */
487 MONO_FP_NEEDS_LOAD_SPILL = 1 << 0,
488 MONO_FP_NEEDS_SPILL = 1 << 1,
489 MONO_FP_NEEDS_LOAD = 1 << 2
493 alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, RegTrack *info)
497 if (info && info->preferred_mask) {
498 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
500 DEBUG (g_print ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
505 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
507 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, FALSE);
513 alloc_float_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg)
517 val = mono_regstate_alloc_float (cfg->rs, dest_mask);
520 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, TRUE);
527 alloc_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, RegTrack *info, gboolean fp)
530 return alloc_float_reg (cfg, tmp, ins, dest_mask, sym_reg);
532 return alloc_int_reg (cfg, tmp, ins, dest_mask, sym_reg, info);
536 assign_reg (MonoRegState *rs, int reg, int hreg, gboolean fp)
539 g_assert (reg >= MONO_MAX_FREGS);
540 g_assert (hreg < MONO_MAX_FREGS);
541 g_assert (! is_global_freg (hreg));
543 rs->fassign [reg] = hreg;
544 rs->fsymbolic [hreg] = reg;
545 rs->ffree_mask &= ~ (1 << hreg);
548 g_assert (reg >= MONO_MAX_IREGS);
549 g_assert (hreg < MONO_MAX_IREGS);
550 g_assert (! is_global_ireg (hreg));
552 rs->iassign [reg] = hreg;
553 rs->isymbolic [hreg] = reg;
554 rs->ifree_mask &= ~ (1 << hreg);
559 assign_ireg (MonoRegState *rs, int reg, int hreg)
561 assign_reg (rs, reg, hreg, FALSE);
565 * Local register allocation.
566 * We first scan the list of instructions and we save the liveness info of
567 * each register (when the register is first used, when it's value is set etc.).
568 * We also reverse the list of instructions (in the InstList list) because assigning
569 * registers backwards allows for more tricks to be used.
572 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
575 MonoRegState *rs = cfg->rs;
577 RegTrack *reginfo, *reginfof;
578 RegTrack *reginfo1, *reginfo2, *reginfod;
579 InstList *tmp, *reversed = NULL;
581 GList *fspill_list = NULL;
588 rs->next_vireg = bb->max_ireg;
589 rs->next_vfreg = bb->max_freg;
590 mono_regstate_assign (rs);
591 reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
592 reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
593 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
594 rs->ffree_mask = MONO_ARCH_CALLEE_FREGS;
597 rs->ffree_mask = 0xff & ~(1 << MONO_ARCH_FPSTACK_SIZE);
601 /*if (cfg->opt & MONO_OPT_COPYPROP)
602 local_copy_prop (cfg, ins);*/
606 DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
607 /* forward pass on the instructions to collect register liveness info */
609 spec = ins_spec [ins->opcode];
612 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
615 DEBUG (print_ins (i, ins));
623 if (spec [MONO_INST_SRC1] == 'f') {
624 spill = g_list_first (fspill_list);
625 if (spill && fpcount < MONO_ARCH_FPSTACK_SIZE) {
626 reginfof [ins->sreg1].flags |= MONO_FP_NEEDS_LOAD;
627 fspill_list = g_list_remove (fspill_list, spill->data);
632 if (spec [MONO_INST_SRC2] == 'f') {
633 spill = g_list_first (fspill_list);
635 reginfof [ins->sreg2].flags |= MONO_FP_NEEDS_LOAD;
636 fspill_list = g_list_remove (fspill_list, spill->data);
637 if (fpcount >= MONO_ARCH_FPSTACK_SIZE) {
639 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
640 reginfof [ins->sreg2].flags |= MONO_FP_NEEDS_LOAD_SPILL;
646 if (spec [MONO_INST_DEST] == 'f') {
647 if (use_fpstack && (spec [MONO_INST_CLOB] != 'm')) {
648 if (fpcount >= MONO_ARCH_FPSTACK_SIZE) {
649 reginfof [ins->dreg].flags |= MONO_FP_NEEDS_SPILL;
651 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
659 if (spec [MONO_INST_SRC1]) {
660 if (spec [MONO_INST_SRC1] == 'f')
664 reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
665 reginfo1 [ins->sreg1].last_use = i;
666 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
667 /* The virtual register is allocated sequentially */
668 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
669 reginfo1 [ins->sreg1 + 1].last_use = i;
670 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
671 reginfo1 [ins->sreg1 + 1].born_in = i;
676 if (spec [MONO_INST_SRC2]) {
677 if (spec [MONO_INST_SRC2] == 'f')
681 reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
682 reginfo2 [ins->sreg2].last_use = i;
683 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
684 /* The virtual register is allocated sequentially */
685 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
686 reginfo2 [ins->sreg2 + 1].last_use = i;
687 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
688 reginfo2 [ins->sreg2 + 1].born_in = i;
693 if (spec [MONO_INST_DEST]) {
696 if (spec [MONO_INST_DEST] == 'f')
700 if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
701 reginfod [ins->dreg].killed_in = i;
702 reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
703 reginfod [ins->dreg].last_use = i;
704 if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
705 reginfod [ins->dreg].born_in = i;
707 dest_dreg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_DEST]);
709 reginfod [ins->dreg].preferred_mask = (1 << dest_dreg);
711 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
712 /* The virtual register is allocated sequentially */
713 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
714 reginfod [ins->dreg + 1].last_use = i;
715 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
716 reginfod [ins->dreg + 1].born_in = i;
717 if (MONO_ARCH_INST_REGPAIR_REG2 (spec [MONO_INST_DEST], -1) != -1)
718 reginfod [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec [MONO_INST_DEST], -1);
724 if (spec [MONO_INST_CLOB] == 'c') {
725 /* A call instruction implicitly uses all registers in call->out_ireg_args */
727 MonoCallInst *call = (MonoCallInst*)ins;
730 list = call->out_ireg_args;
736 regpair = (guint32)(gssize)(list->data);
737 hreg = regpair >> 24;
738 reg = regpair & 0xffffff;
740 reginfo [reg].prev_use = reginfo [reg].last_use;
741 reginfo [reg].last_use = i;
743 list = g_slist_next (list);
747 list = call->out_freg_args;
748 if (!use_fpstack && list) {
753 regpair = (guint32)(gssize)(list->data);
754 hreg = regpair >> 24;
755 reg = regpair & 0xffffff;
757 reginfof [reg].prev_use = reginfof [reg].last_use;
758 reginfof [reg].last_use = i;
760 list = g_slist_next (list);
765 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
770 // todo: check if we have anything left on fp stack, in verify mode?
773 DEBUG (print_regtrack (reginfo, rs->next_vireg));
774 DEBUG (print_regtrack (reginfof, rs->next_vfreg));
777 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
778 int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
779 int dreg_high, sreg1_high;
780 guint32 dreg_mask, sreg1_mask, sreg2_mask, mask;
783 spec = ins_spec [ins->opcode];
790 dreg_mask = dreg_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
791 sreg1_mask = sreg1_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
792 sreg2_mask = sreg2_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
794 DEBUG (g_print ("processing:"));
795 DEBUG (print_ins (i, ins));
800 dest_sreg1 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC1]);
801 dest_sreg2 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC2]);
802 dest_dreg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_DEST]);
803 clob_reg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_CLOB]);
804 sreg2_mask &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
809 if (use_fpstack && (spec [MONO_INST_CLOB] != 'm')) {
810 if (spec [MONO_INST_DEST] == 'f') {
811 if (reginfof [ins->dreg].flags & MONO_FP_NEEDS_SPILL) {
814 spill_node = g_list_first (fspill_list);
815 g_assert (spill_node);
817 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
818 insert_before_ins (ins, tmp, store);
819 fspill_list = g_list_remove (fspill_list, spill_node->data);
824 if (spec [MONO_INST_SRC1] == 'f') {
825 if (reginfof [ins->sreg1].flags & MONO_FP_NEEDS_LOAD) {
827 MonoInst *store = NULL;
829 if (reginfof [ins->sreg1].flags & MONO_FP_NEEDS_LOAD_SPILL) {
831 spill_node = g_list_first (fspill_list);
832 g_assert (spill_node);
834 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
835 fspill_list = g_list_remove (fspill_list, spill_node->data);
839 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
840 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
841 insert_before_ins (ins, tmp, load);
843 insert_before_ins (load, tmp, store);
847 if (spec [MONO_INST_SRC2] == 'f') {
848 if (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD) {
850 MonoInst *store = NULL;
852 if (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD_SPILL) {
855 spill_node = g_list_first (fspill_list);
856 g_assert (spill_node);
857 if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD_SPILL))
858 spill_node = g_list_next (spill_node);
860 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
861 fspill_list = g_list_remove (fspill_list, spill_node->data);
865 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
866 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
867 insert_before_ins (ins, tmp, load);
869 insert_before_ins (load, tmp, store);
877 if (dest_sreg2 != -1) {
878 if (rs->ifree_mask & (1 << dest_sreg2)) {
879 if (is_global_ireg (ins->sreg2)) {
880 /* Argument already in hard reg, need to copy */
881 MonoInst *copy = create_copy_ins (cfg, dest_sreg2, ins->sreg2, NULL, FALSE);
882 insert_before_ins (ins, tmp, copy);
885 DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
886 assign_ireg (rs, ins->sreg2, dest_sreg2);
889 int need_spill = TRUE;
891 dreg_mask &= ~ (1 << dest_sreg2);
892 sreg1_mask &= ~ (1 << dest_sreg2);
895 * First check if dreg is assigned to dest_sreg2, since we
896 * can't spill a dreg.
898 val = rs->iassign [ins->dreg];
899 if (val == dest_sreg2 && ins->dreg != ins->sreg2) {
901 * the destination register is already assigned to
902 * dest_sreg2: we need to allocate another register for it
903 * and then copy from this to dest_sreg2.
906 new_dest = alloc_int_reg (cfg, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
907 g_assert (new_dest >= 0);
908 DEBUG (g_print ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg2)));
910 prev_dreg = ins->dreg;
911 assign_ireg (rs, ins->dreg, new_dest);
912 clob_dreg = ins->dreg;
913 create_copy_ins (cfg, dest_sreg2, new_dest, ins, FALSE);
917 if (is_global_ireg (ins->sreg2)) {
918 MonoInst *copy = create_copy_ins (cfg, dest_sreg2, ins->sreg2, NULL, FALSE);
919 insert_before_ins (ins, tmp, copy);
922 val = rs->iassign [ins->sreg2];
923 if (val == dest_sreg2) {
924 /* sreg2 is already assigned to the correct register */
927 else if ((val >= 0) || (val < -1)) {
928 /* FIXME: sreg2 already assigned to another register */
929 g_assert_not_reached ();
934 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg2]));
935 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_sreg2], FALSE);
936 mono_regstate_free_int (rs, dest_sreg2);
939 if (!is_global_ireg (ins->sreg2))
940 /* force-set sreg2 */
941 assign_ireg (rs, ins->sreg2, dest_sreg2);
943 ins->sreg2 = dest_sreg2;
949 fp = dreg_is_fp (ins);
950 if (spec [MONO_INST_DEST] && (!fp || (fp && !use_fpstack)) && is_soft_reg (ins->dreg, fp))
951 prev_dreg = ins->dreg;
954 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
955 * various complex situations.
957 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
958 guint32 dreg2, dest_dreg2;
960 g_assert (is_soft_reg (ins->dreg, fp));
962 if (dest_dreg != -1) {
963 if (rs->iassign [ins->dreg] != dest_dreg)
964 free_up_ireg (cfg, tmp, ins, dest_dreg);
966 dreg2 = ins->dreg + 1;
967 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec [MONO_INST_DEST], dest_dreg);
968 if (dest_dreg2 != -1) {
969 if (rs->iassign [dreg2] != dest_dreg2)
970 free_up_ireg (cfg, tmp, ins, dest_dreg2);
975 if ((!fp || (fp && !use_fpstack)) && (is_soft_reg (ins->dreg, fp))) {
977 dreg_mask = (1 << dest_dreg);
979 val = rassign (cfg, ins->dreg, fp);
984 /* the register gets spilled after this inst */
987 val = alloc_reg (cfg, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], fp);
988 assign_reg (rs, ins->dreg, val, fp);
990 create_spilled_store (cfg, spill, val, prev_dreg, ins, fp);
993 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, fp), ins->dreg));
997 /* Handle regpairs */
998 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
999 int reg2 = prev_dreg + 1;
1002 g_assert (prev_dreg > -1);
1003 g_assert (!is_global_ireg (rs->iassign [prev_dreg]));
1004 mask = regpair_reg2_mask (spec [MONO_INST_DEST], rs->iassign [prev_dreg]);
1005 val = rs->iassign [reg2];
1009 /* the register gets spilled after this inst */
1012 val = mono_regstate_alloc_int (rs, mask);
1014 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1016 create_spilled_store (cfg, spill, val, reg2, ins, fp);
1019 if (! (mask & (1 << val))) {
1020 val = mono_regstate_alloc_int (rs, mask);
1022 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1024 /* Reallocate hreg to the correct register */
1025 create_copy_ins (cfg, rs->iassign [reg2], val, ins, fp);
1027 mono_regstate_free_int (rs, rs->iassign [reg2]);
1031 DEBUG (g_print ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1032 assign_reg (rs, reg2, val, fp);
1037 if (reg_is_freeable (val, fp) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1038 DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1039 mono_regstate_free_int (rs, val);
1043 if ((!fp || (fp && !use_fpstack)) && prev_dreg >= 0 && is_soft_reg (prev_dreg, fp) && (fp ? reginfof : reginfo) [prev_dreg].born_in >= i) {
1045 * In theory, we could free up the hreg even if the vreg is alive,
1046 * but branches inside bblocks force us to assign the same hreg
1047 * to a vreg every time it is encountered.
1049 int dreg = rassign (cfg, prev_dreg, fp);
1050 g_assert (dreg >= 0);
1051 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, fp), prev_dreg, (fp ? reginfof : reginfo) [prev_dreg].born_in));
1053 mono_regstate_free_float (rs, dreg);
1055 mono_regstate_free_int (rs, dreg);
1058 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1059 /* this instruction only outputs to dest_dreg, need to copy */
1060 create_copy_ins (cfg, ins->dreg, dest_dreg, ins, fp);
1061 ins->dreg = dest_dreg;
1063 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1064 free_up_ireg (cfg, tmp, ins, dest_dreg);
1070 if ((clob_reg != -1) && (!(rs->ifree_mask & (1 << clob_reg)))) {
1071 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1072 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg], FALSE);
1073 mono_regstate_free_int (rs, clob_reg);
1076 if (spec [MONO_INST_CLOB] == 'c') {
1077 int j, s, dreg, dreg2;
1080 clob_mask = MONO_ARCH_CALLEE_REGS;
1083 * Need to avoid spilling the dreg since the dreg is not really
1084 * clobbered by the call.
1086 if ((prev_dreg != -1) && !dreg_is_fp (ins))
1087 dreg = rassign (cfg, prev_dreg, dreg_is_fp (ins));
1091 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST]))
1092 dreg2 = rassign (cfg, prev_dreg + 1, dreg_is_fp (ins));
1096 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1098 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1) && (j != dreg) && (j != dreg2)) {
1099 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [j], FALSE);
1100 mono_regstate_free_int (rs, j);
1105 clob_mask = MONO_ARCH_CALLEE_FREGS;
1106 if ((prev_dreg != -1) && dreg_is_fp (ins))
1107 dreg = rassign (cfg, prev_dreg, dreg_is_fp (ins));
1111 for (j = 0; j < MONO_MAX_FREGS; ++j) {
1113 if ((clob_mask & s) && !(rs->ffree_mask & s) && (j != ins->sreg1) && (j != dreg)) {
1114 get_register_force_spilling (cfg, tmp, ins, rs->fsymbolic [j], TRUE);
1115 mono_regstate_free_float (rs, j);
1122 * TRACK ARGUMENT REGS
1124 if (spec [MONO_INST_CLOB] == 'c') {
1125 MonoCallInst *call = (MonoCallInst*)ins;
1129 * This needs to be done before assigning sreg1, so sreg1 will
1130 * not be assigned one of the argument regs.
1134 * Assign all registers in call->out_reg_args to the proper
1135 * argument registers.
1138 list = call->out_ireg_args;
1144 regpair = (guint32)(gssize)(list->data);
1145 hreg = regpair >> 24;
1146 reg = regpair & 0xffffff;
1148 assign_reg (rs, reg, hreg, FALSE);
1150 sreg1_mask &= ~(1 << hreg);
1152 DEBUG (g_print ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1154 list = g_slist_next (list);
1156 g_slist_free (call->out_ireg_args);
1159 list = call->out_freg_args;
1160 if (list && !use_fpstack) {
1165 regpair = (guint32)(gssize)(list->data);
1166 hreg = regpair >> 24;
1167 reg = regpair & 0xffffff;
1169 assign_reg (rs, reg, hreg, TRUE);
1171 DEBUG (g_print ("\tassigned arg reg %s to R%d\n", mono_arch_fregname (hreg), reg));
1173 list = g_slist_next (list);
1176 if (call->out_freg_args)
1177 g_slist_free (call->out_freg_args);
1183 fp = sreg1_is_fp (ins);
1184 if ((!fp || (fp && !use_fpstack))) {
1185 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST]) && (spec [MONO_INST_CLOB] == '1')) {
1186 g_assert (is_soft_reg (ins->sreg1, fp));
1188 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1189 if (dest_sreg1 != -1)
1190 g_assert (dest_sreg1 == ins->dreg);
1191 val = mono_regstate_alloc_int (rs, 1 << ins->dreg);
1192 g_assert (val >= 0);
1193 assign_reg (rs, ins->sreg1, val, fp);
1195 DEBUG (g_print ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, fp), ins->sreg1));
1197 g_assert ((1 << dreg_high) & regpair_reg2_mask (spec [MONO_INST_SRC1], ins->dreg));
1198 val = mono_regstate_alloc_int (rs, 1 << dreg_high);
1199 g_assert (val >= 0);
1200 assign_reg (rs, ins->sreg1 + 1, val, fp);
1202 DEBUG (g_print ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, fp), ins->sreg1 + 1));
1204 /* Skip rest of this section */
1208 if (dest_sreg1 != -1) {
1209 sreg1_mask = 1 << dest_sreg1;
1211 if (!(rs->ifree_mask & (1 << dest_sreg1))) {
1212 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg1]));
1213 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_sreg1], FALSE);
1214 mono_regstate_free_int (rs, dest_sreg1);
1216 if (is_global_ireg (ins->sreg1)) {
1217 /* The argument is already in a hard reg, need to copy */
1218 MonoInst *copy = create_copy_ins (cfg, dest_sreg1, ins->sreg1, NULL, FALSE);
1219 insert_before_ins (ins, tmp, copy);
1220 ins->sreg1 = dest_sreg1;
1224 if (is_soft_reg (ins->sreg1, fp)) {
1225 val = rassign (cfg, ins->sreg1, fp);
1226 prev_sreg1 = ins->sreg1;
1230 /* the register gets spilled after this inst */
1234 if (((ins->opcode == OP_MOVE) || (ins->opcode == OP_SETREG)) && !spill && !fp && (!is_global_ireg (ins->dreg) && (rs->ifree_mask & (1 << ins->dreg)))) {
1236 * Allocate the same hreg to sreg1 as well so the
1237 * peephole can get rid of the move.
1239 sreg1_mask = 1 << ins->dreg;
1242 val = alloc_reg (cfg, tmp, ins, sreg1_mask, ins->sreg1, ®info [ins->sreg1], fp);
1243 assign_reg (rs, ins->sreg1, val, fp);
1244 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, fp), ins->sreg1));
1247 MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL, fp);
1249 * Need to insert before the instruction since it can
1252 insert_before_ins (ins, tmp, store);
1255 else if ((dest_sreg1 != -1) && (dest_sreg1 != val)) {
1256 g_assert_not_reached ();
1264 sreg2_mask &= ~(1 << ins->sreg1);
1267 /* Handle the case when sreg1 is a regpair but dreg is not */
1268 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1]) && (spec [MONO_INST_CLOB] != '1')) {
1269 int reg2 = prev_sreg1 + 1;
1272 g_assert (prev_sreg1 > -1);
1273 g_assert (!is_global_ireg (rs->iassign [prev_sreg1]));
1274 mask = regpair_reg2_mask (spec [MONO_INST_SRC1], rs->iassign [prev_sreg1]);
1275 val = rs->iassign [reg2];
1279 /* the register gets spilled after this inst */
1282 val = mono_regstate_alloc_int (rs, mask);
1284 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1286 g_assert_not_reached ();
1289 if (! (mask & (1 << val))) {
1290 /* The vreg is already allocated to a wrong hreg */
1292 g_assert_not_reached ();
1294 val = mono_regstate_alloc_int (rs, mask);
1296 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1298 /* Reallocate hreg to the correct register */
1299 create_copy_ins (cfg, rs->iassign [reg2], val, ins, fp);
1301 mono_regstate_free_int (rs, rs->iassign [reg2]);
1307 DEBUG (g_print ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1308 assign_reg (rs, reg2, val, fp);
1311 /* Handle dreg==sreg1 */
1312 if (((spec [MONO_INST_DEST] == 'f' && spec [MONO_INST_SRC1] == 'f' && !use_fpstack) || spec [MONO_INST_CLOB] == '1') && ins->dreg != ins->sreg1) {
1313 MonoInst *sreg2_copy = NULL;
1315 gboolean fp = (spec [MONO_INST_SRC1] == 'f');
1317 if (ins->dreg == ins->sreg2) {
1319 * copying sreg1 to dreg could clobber sreg2, so allocate a new
1322 int reg2 = alloc_reg (cfg, tmp, ins, dreg_mask, ins->sreg2, NULL, fp);
1324 DEBUG (g_print ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (ins->sreg2, fp), mono_regname_full (reg2, fp)));
1325 sreg2_copy = create_copy_ins (cfg, reg2, ins->sreg2, NULL, fp);
1326 prev_sreg2 = ins->sreg2 = reg2;
1329 mono_regstate_free_float (rs, reg2);
1331 mono_regstate_free_int (rs, reg2);
1334 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1])) {
1335 /* Copying sreg1_high to dreg could also clobber sreg2 */
1336 if (rs->iassign [prev_sreg1 + 1] == ins->sreg2)
1338 g_assert_not_reached ();
1341 * sreg1 and dest are already allocated to the same regpair by the
1342 * SREG1 allocation code.
1344 g_assert (ins->sreg1 == ins->dreg);
1345 g_assert (dreg_high == sreg1_high);
1348 DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (ins->sreg1, fp), mono_regname_full (ins->dreg, fp)));
1349 copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL, fp);
1350 insert_before_ins (ins, tmp, copy);
1353 insert_before_ins (copy, tmp, sreg2_copy);
1356 * Need to prevent sreg2 to be allocated to sreg1, since that
1357 * would screw up the previous copy.
1359 sreg2_mask &= ~ (1 << ins->sreg1);
1360 /* we set sreg1 to dest as well */
1361 prev_sreg1 = ins->sreg1 = ins->dreg;
1362 sreg2_mask &= ~ (1 << ins->dreg);
1368 fp = sreg2_is_fp (ins);
1369 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2]))
1370 g_assert_not_reached ();
1371 if ((!fp || (fp && !use_fpstack)) && (is_soft_reg (ins->sreg2, fp))) {
1372 val = rassign (cfg, ins->sreg2, fp);
1377 /* the register gets spilled after this inst */
1380 val = alloc_reg (cfg, tmp, ins, sreg2_mask, ins->sreg2, ®info [ins->sreg2], fp);
1381 assign_reg (rs, ins->sreg2, val, fp);
1382 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_regname_full (val, fp), ins->sreg2));
1384 create_spilled_store (cfg, spill, val, prev_sreg2, ins, fp);
1392 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1393 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1394 mono_regstate_free_int (rs, ins->sreg1);
1396 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1397 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1398 mono_regstate_free_int (rs, ins->sreg2);
1401 DEBUG (print_ins (i, ins));
1402 /* this may result from a insert_before call */
1404 bb->code = tmp->data;
1410 g_list_free (fspill_list);