mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583                 printf (" [%d]", (int)ins->inst_imm);
 584                 break;
 585         case OP_ADD_IMM:
 586         case OP_LADD_IMM:
 587                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 588                 break;
 589         case OP_I8CONST:
 590                 printf (" [%lld]", (long long)ins->inst_l);
 591                 break;
 592         case OP_R8CONST:
 593                 printf (" [%f]", *(double*)ins->inst_p0);
 594                 break;
 595         case OP_R4CONST:
 596                 printf (" [%f]", *(float*)ins->inst_p0);
 597                 break;
 598         case OP_CALL:
 599         case OP_CALL_MEMBASE:
 600         case OP_CALL_REG:
 601         case OP_FCALL:
 602         case OP_LCALL:
 603         case OP_VCALL:
 604         case OP_VCALL_REG:
 605         case OP_VCALL_MEMBASE:
 606         case OP_VCALL2:
 607         case OP_VCALL2_REG:
 608         case OP_VCALL2_MEMBASE:
 609         case OP_VOIDCALL:
 610         case OP_VOIDCALL_MEMBASE:
 611         case OP_TAILCALL: {
 612                 MonoCallInst *call = (MonoCallInst*)ins;
 613                 GSList *list;
 614
 615                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 616                         /*
 617                          * These are lowered opcodes, but they are in the .md files since the old
 618                          * JIT passes them to backends.
 619                          */
 620                         if (ins->dreg != -1)
 621                                 printf (" R%d <-", ins->dreg);
 622                 }
 623
 624                 if (call->method) {
 625                         char *full_name = mono_method_full_name (call->method, TRUE);
 626                         printf (" [%s]", full_name);
 627                         g_free (full_name);
 628                 } else if (call->fptr_is_patch) {
 629                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 630
 631                         printf (" ");
 632                         mono_print_ji (ji);
 633                 } else if (call->fptr) {
 634                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 635                         if (info)
 636                                 printf (" [%s]", info->name);
 637                 }
 638
 639                 list = call->out_ireg_args;
 640                 while (list) {
 641                         guint32 regpair;
 642                         int reg, hreg;
 643
 644                         regpair = (guint32)(gssize)(list->data);
 645                         hreg = regpair >> 24;
 646                         reg = regpair & 0xffffff;
 647
 648                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 649
 650                         list = g_slist_next (list);
 651                 }
 652                 break;
 653         }
 654         case OP_BR:
 655         case OP_CALL_HANDLER:
 656                 printf (" [B%d]", ins->inst_target_bb->block_num);
 657                 break;
 658         case OP_IBNE_UN:
 659         case OP_IBEQ:
 660         case OP_IBLT:
 661         case OP_IBLT_UN:
 662         case OP_IBGT:
 663         case OP_IBGT_UN:
 664         case OP_IBGE:
 665         case OP_IBGE_UN:
 666         case OP_IBLE:
 667         case OP_IBLE_UN:
 668         case OP_LBNE_UN:
 669         case OP_LBEQ:
 670         case OP_LBLT:
 671         case OP_LBLT_UN:
 672         case OP_LBGT:
 673         case OP_LBGT_UN:
 674         case OP_LBGE:
 675         case OP_LBGE_UN:
 676         case OP_LBLE:
 677         case OP_LBLE_UN:
 678                 if (!ins->inst_false_bb)
 679                         printf (" [B%d]", ins->inst_true_bb->block_num);
 680                 else
 681                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 682                 break;
 683         case OP_LIVERANGE_START:
 684         case OP_LIVERANGE_END:
 685         case OP_GC_LIVENESS_DEF:
 686         case OP_GC_LIVENESS_USE:
 687                 printf (" R%d", (int)ins->inst_c1);
 688                 break;
 689         case OP_IL_SEQ_POINT:
 690         case OP_SEQ_POINT:
 691                 printf (" il: %x", (int)ins->inst_imm);
 692                 break;
 693         default:
 694                 break;
 695         }
 696
 697         if (spec [MONO_INST_CLOB])
 698                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 699         printf ("\n");
 700 }
 701
 702 static void
 703 print_regtrack (RegTrack *t, int num)
 704 {
 705         int i;
 706         char buf [32];
 707         const char *r;
 708
 709         for (i = 0; i < num; ++i) {
 710                 if (!t [i].born_in)
 711                         continue;
 712                 if (i >= MONO_MAX_IREGS) {
 713                         g_snprintf (buf, sizeof(buf), "R%d", i);
 714                         r = buf;
 715                 } else
 716                         r = mono_arch_regname (i);
 717                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 718         }
 719 }
 720 #else
 721
 722 void
 723 mono_print_ji (const MonoJumpInfo *ji)
 724 {
 725 }
 726
 727 void
 728 mono_print_ins_index (int i, MonoInst *ins)
 729 {
 730 }
 731 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 732
 733 void
 734 mono_print_ins (MonoInst *ins)
 735 {
 736         mono_print_ins_index (-1, ins);
 737 }
 738
 739 static inline void
 740 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 741 {
 742         /*
 743          * If this function is called multiple times, the new instructions are inserted
 744          * in the proper order.
 745          */
 746         mono_bblock_insert_before_ins (bb, ins, to_insert);
 747 }
 748
 749 static inline void
 750 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 751 {
 752         /*
 753          * If this function is called multiple times, the new instructions are inserted in
 754          * proper order.
 755          */
 756         mono_bblock_insert_after_ins (bb, *last, to_insert);
 757
 758         *last = to_insert;
 759 }
 760
 761 static inline int
 762 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 763 {
 764         if (vreg_is_ref (cfg, reg))
 765                 return MONO_REG_INT_REF;
 766         else if (vreg_is_mp (cfg, reg))
 767                 return MONO_REG_INT_MP;
 768         else
 769                 return bank;
 770 }
 771
 772 /*
 773  * Force the spilling of the variable in the symbolic register 'reg', and free
 774  * the hreg it was assigned to.
 775  */
 776 static void
 777 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 778 {
 779         MonoInst *load;
 780         int i, sel, spill;
 781         int *symbolic;
 782         MonoRegState *rs = cfg->rs;
 783
 784         symbolic = rs->symbolic [bank];
 785         sel = rs->vassign [reg];
 786
 787         /* the vreg we need to spill lives in another logical reg bank */
 788         bank = translate_bank (cfg->rs, bank, sel);
 789
 790         /*i = rs->isymbolic [sel];
 791         g_assert (i == reg);*/
 792         i = reg;
 793         spill = ++cfg->spill_count;
 794         rs->vassign [i] = -spill - 1;
 795         if (G_UNLIKELY (bank))
 796                 mono_regstate_free_general (rs, sel, bank);
 797         else
 798                 mono_regstate_free_int (rs, sel);
 799         /* we need to create a spill var and insert a load to sel after the current instruction */
 800         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 801         load->dreg = sel;
 802         load->inst_basereg = cfg->frame_reg;
 803         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 804         insert_after_ins (bb, ins, last, load);
 805         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 806         if (G_UNLIKELY (bank))
 807                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 808         else
 809                 i = mono_regstate_alloc_int (rs, regmask (sel));
 810         g_assert (i == sel);
 811
 812         if (G_UNLIKELY (bank))
 813                 mono_regstate_free_general (rs, sel, bank);
 814         else
 815                 mono_regstate_free_int (rs, sel);
 816 }
 817
 818 /* This isn't defined on older glib versions and on some platforms */
 819 #ifndef G_GUINT64_FORMAT
 820 #define G_GUINT64_FORMAT "ul"
 821 #endif
 822
 823 static int
 824 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 825 {
 826         MonoInst *load;
 827         int i, sel, spill, num_sregs;
 828         int sregs [MONO_MAX_SRC_REGS];
 829         int *symbolic;
 830         MonoRegState *rs = cfg->rs;
 831
 832         symbolic = rs->symbolic [bank];
 833
 834         g_assert (bank < MONO_NUM_REGBANKS);
 835
 836         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 837         /* exclude the registers in the current instruction */
 838         num_sregs = mono_inst_get_src_registers (ins, sregs);
 839         for (i = 0; i < num_sregs; ++i) {
 840                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 841                         if (is_soft_reg (sregs [i], bank))
 842                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 843                         else
 844                                 regmask &= ~ (regmask (sregs [i]));
 845                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 846                 }
 847         }
 848         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 849                 regmask &= ~ (regmask (ins->dreg));
 850                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 851         }
 852
 853         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 854         g_assert (regmask); /* need at least a register we can free */
 855         sel = 0;
 856         /* we should track prev_use and spill the register that's farther */
 857         if (G_UNLIKELY (bank)) {
 858                 for (i = 0; i < regbank_size [bank]; ++i) {
 859                         if (regmask & (regmask (i))) {
 860                                 sel = i;
 861
 862                                 /* the vreg we need to load lives in another logical bank */
 863                                 bank = translate_bank (cfg->rs, bank, sel);
 864
 865                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 866                                 break;
 867                         }
 868                 }
 869
 870                 i = rs->symbolic [bank] [sel];
 871                 spill = ++cfg->spill_count;
 872                 rs->vassign [i] = -spill - 1;
 873                 mono_regstate_free_general (rs, sel, bank);
 874         }
 875         else {
 876                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 877                         if (regmask & (regmask (i))) {
 878                                 sel = i;
 879                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 880                                 break;
 881                         }
 882                 }
 883
 884                 i = rs->isymbolic [sel];
 885                 spill = ++cfg->spill_count;
 886                 rs->vassign [i] = -spill - 1;
 887                 mono_regstate_free_int (rs, sel);
 888         }
 889
 890         /* we need to create a spill var and insert a load to sel after the current instruction */
 891         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 892         load->dreg = sel;
 893         load->inst_basereg = cfg->frame_reg;
 894         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 895         insert_after_ins (bb, ins, last, load);
 896         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 897         if (G_UNLIKELY (bank))
 898                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 899         else
 900                 i = mono_regstate_alloc_int (rs, regmask (sel));
 901         g_assert (i == sel);
 902
 903         return sel;
 904 }
 905
 906 /*
 907  * free_up_hreg:
 908  *
 909  *   Free up the hreg HREG by spilling the vreg allocated to it.
 910  */
 911 static void
 912 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 913 {
 914         if (G_UNLIKELY (bank)) {
 915                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 916                         bank = translate_bank (cfg->rs, bank, hreg);
 917                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 918                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 919                 }
 920         }
 921         else {
 922                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 923                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 924                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 925                 }
 926         }
 927 }
 928
 929 static MonoInst*
 930 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 931 {
 932         MonoInst *copy;
 933
 934         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 935
 936         copy->dreg = dest;
 937         copy->sreg1 = src;
 938         copy->cil_code = ip;
 939         if (ins) {
 940                 mono_bblock_insert_after_ins (bb, ins, copy);
 941                 *last = copy;
 942         }
 943         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 944         return copy;
 945 }
 946
 947 static inline const char*
 948 regbank_to_string (int bank)
 949 {
 950         if (bank == MONO_REG_INT_REF)
 951                 return "REF ";
 952         else if (bank == MONO_REG_INT_MP)
 953                 return "MP ";
 954         else
 955                 return "";
 956 }
 957
 958 static void
 959 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 960 {
 961         MonoInst *store, *def;
 962
 963         bank = get_vreg_bank (cfg, prev_reg, bank);
 964
 965         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 966         store->sreg1 = reg;
 967         store->inst_destbasereg = cfg->frame_reg;
 968         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 969         if (ins) {
 970                 mono_bblock_insert_after_ins (bb, ins, store);
 971                 *last = store;
 972         } else if (insert_before) {
 973                 insert_before_ins (bb, insert_before, store);
 974         } else {
 975                 g_assert_not_reached ();
 976         }
 977         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 978
 979         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 980                 g_assert (prev_reg != -1);
 981                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 982                 def->inst_c0 = spill;
 983                 def->inst_c1 = bank;
 984                 mono_bblock_insert_after_ins (bb, store, def);
 985         }
 986 }
 987
 988 /* flags used in reginfo->flags */
 989 enum {
 990         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 991         MONO_FP_NEEDS_SPILL                     = regmask (1),
 992         MONO_FP_NEEDS_LOAD                      = regmask (2)
 993 };
 994
 995 static inline int
 996 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 997 {
 998         int val;
 999
1000         if (info && info->preferred_mask) {
1001                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1002                 if (val >= 0) {
1003                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1004                         return val;
1005                 }
1006         }
1007
1008         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1009         if (val < 0)
1010                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1011
1012         return val;
1013 }
1014
1015 static inline int
1016 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1017 {
1018         int val;
1019
1020         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1021
1022         if (val < 0)
1023                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1024
1025         return val;
1026 }
1027
1028 static inline int
1029 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1030 {
1031         if (G_UNLIKELY (bank))
1032                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1033         else
1034                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1035 }
1036
1037 static inline void
1038 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1039 {
1040         if (G_UNLIKELY (bank)) {
1041                 int mirrored_bank;
1042
1043                 g_assert (reg >= regbank_size [bank]);
1044                 g_assert (hreg < regbank_size [bank]);
1045                 g_assert (! is_global_freg (hreg));
1046
1047                 rs->vassign [reg] = hreg;
1048                 rs->symbolic [bank] [hreg] = reg;
1049                 rs->free_mask [bank] &= ~ (regmask (hreg));
1050
1051                 mirrored_bank = get_mirrored_bank (bank);
1052                 if (mirrored_bank == -1)
1053                         return;
1054
1055                 /* Make sure the other logical reg bank that this bank shares
1056                  * a single hard reg bank knows that this hard reg is not free.
1057                  */
1058                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1059
1060                 /* Mark the other logical bank that the this bank shares
1061                  * a single hard reg bank with as mirrored.
1062                  */
1063                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1064
1065         }
1066         else {
1067                 g_assert (reg >= MONO_MAX_IREGS);
1068                 g_assert (hreg < MONO_MAX_IREGS);
1069 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1070                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1071                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1072                 g_assert (! is_global_ireg (hreg));
1073 #endif
1074
1075                 rs->vassign [reg] = hreg;
1076                 rs->isymbolic [hreg] = reg;
1077                 rs->ifree_mask &= ~ (regmask (hreg));
1078         }
1079 }
1080
1081 static inline regmask_t
1082 get_callee_mask (const char spec)
1083 {
1084         if (G_UNLIKELY (reg_bank (spec)))
1085                 return regbank_callee_regs [reg_bank (spec)];
1086         return MONO_ARCH_CALLEE_REGS;
1087 }
1088
1089 static gint8 desc_to_fixed_reg [256];
1090 static gboolean desc_to_fixed_reg_inited = FALSE;
1091
1092 #ifndef DISABLE_JIT
1093
1094 /*
1095  * Local register allocation.
1096  * We first scan the list of instructions and we save the liveness info of
1097  * each register (when the register is first used, when it's value is set etc.).
1098  * We also reverse the list of instructions because assigning registers backwards allows
1099  * for more tricks to be used.
1100  */
1101 void
1102 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1103 {
1104         MonoInst *ins, *prev, *last;
1105         MonoInst **tmp;
1106         MonoRegState *rs = cfg->rs;
1107         int i, j, val, max;
1108         RegTrack *reginfo;
1109         const char *spec;
1110         unsigned char spec_src1, spec_dest;
1111         int bank = 0;
1112 #if MONO_ARCH_USE_FPSTACK
1113         gboolean has_fp = FALSE;
1114         int fpstack [8];
1115         int sp = 0;
1116 #endif
1117         int num_sregs = 0;
1118         int sregs [MONO_MAX_SRC_REGS];
1119
1120         if (!bb->code)
1121                 return;
1122
1123         if (!desc_to_fixed_reg_inited) {
1124                 for (i = 0; i < 256; ++i)
1125                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1126                 desc_to_fixed_reg_inited = TRUE;
1127
1128                 /* Validate the cpu description against the info in mini-ops.h */
1129 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1130                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1131                         const char *ispec;
1132
1133                         spec = ins_get_spec (i);
1134                         ispec = INS_INFO (i);
1135
1136                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1137                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1138                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1139                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1140                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1141                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1142                 }
1143 #endif
1144         }
1145
1146         rs->next_vreg = bb->max_vreg;
1147         mono_regstate_assign (rs);
1148
1149         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1150         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1151                 rs->free_mask [i] = regbank_callee_regs [i];
1152
1153         max = rs->next_vreg;
1154
1155         if (cfg->reginfo && cfg->reginfo_len < max)
1156                 cfg->reginfo = NULL;
1157
1158         reginfo = cfg->reginfo;
1159         if (!reginfo) {
1160                 cfg->reginfo_len = MAX (1024, max * 2);
1161                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1162         }
1163         else
1164                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1165
1166         if (cfg->verbose_level > 1) {
1167                 /* print_regtrack reads the info of all variables */
1168                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1169         }
1170
1171         /*
1172          * For large methods, next_vreg can be very large, so g_malloc0 time can
1173          * be prohibitive. So we manually init the reginfo entries used by the
1174          * bblock.
1175          */
1176         for (ins = bb->code; ins; ins = ins->next) {
1177                 gboolean modify = FALSE;
1178
1179                 spec = ins_get_spec (ins->opcode);
1180
1181                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1182                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1183 #if SIZEOF_REGISTER == 4
1184                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1185                                 /**
1186                                  * In the new IR, the two vregs of the regpair do not alias the
1187                                  * original long vreg. shift the vreg here so the rest of the
1188                                  * allocator doesn't have to care about it.
1189                                  */
1190                                 ins->dreg ++;
1191                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1192                         }
1193 #endif
1194                 }
1195
1196                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1197                 for (j = 0; j < num_sregs; ++j) {
1198                         g_assert (sregs [j] != -1);
1199                         if (sregs [j] < max) {
1200                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1201 #if SIZEOF_REGISTER == 4
1202                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1203                                         sregs [j]++;
1204                                         modify = TRUE;
1205                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1206                                 }
1207 #endif
1208                         }
1209                 }
1210                 if (modify)
1211                         mono_inst_set_src_registers (ins, sregs);
1212         }
1213
1214         /*if (cfg->opt & MONO_OPT_COPYPROP)
1215                 local_copy_prop (cfg, ins);*/
1216
1217         i = 1;
1218         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1219         /* forward pass on the instructions to collect register liveness info */
1220         MONO_BB_FOR_EACH_INS (bb, ins) {
1221                 spec = ins_get_spec (ins->opcode);
1222                 spec_dest = spec [MONO_INST_DEST];
1223
1224                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1225                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1226                 }
1227
1228                 DEBUG (mono_print_ins_index (i, ins));
1229
1230                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1231
1232 #if MONO_ARCH_USE_FPSTACK
1233                 if (dreg_is_fp (spec)) {
1234                         has_fp = TRUE;
1235                 } else {
1236                         for (j = 0; j < num_sregs; ++j) {
1237                                 if (sreg_is_fp (j, spec))
1238                                         has_fp = TRUE;
1239                         }
1240                 }
1241 #endif
1242
1243                 for (j = 0; j < num_sregs; ++j) {
1244                         int sreg = sregs [j];
1245                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1246                         if (sreg_spec) {
1247                                 bank = sreg_bank (j, spec);
1248                                 g_assert (sreg != -1);
1249                                 if (is_soft_reg (sreg, bank))
1250                                         /* This means the vreg is not local to this bb */
1251                                         g_assert (reginfo [sreg].born_in > 0);
1252                                 rs->vassign [sreg] = -1;
1253                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1254                                 //reginfo [ins->sreg2].last_use = i;
1255                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1256                                         /* The virtual register is allocated sequentially */
1257                                         rs->vassign [sreg + 1] = -1;
1258                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1259                                         //reginfo [ins->sreg2 + 1].last_use = i;
1260                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1261                                                 reginfo [sreg + 1].born_in = i;
1262                                 }
1263                         } else {
1264                                 sregs [j] = -1;
1265                         }
1266                 }
1267                 mono_inst_set_src_registers (ins, sregs);
1268
1269                 if (spec_dest) {
1270                         int dest_dreg;
1271
1272                         bank = dreg_bank (spec);
1273                         if (spec_dest != 'b') /* it's not just a base register */
1274                                 reginfo [ins->dreg].killed_in = i;
1275                         g_assert (ins->dreg != -1);
1276                         rs->vassign [ins->dreg] = -1;
1277                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1278                         //reginfo [ins->dreg].last_use = i;
1279                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1280                                 reginfo [ins->dreg].born_in = i;
1281
1282                         dest_dreg = desc_to_fixed_reg [spec_dest];
1283                         if (dest_dreg != -1)
1284                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1285
1286 #ifdef MONO_ARCH_INST_FIXED_MASK
1287                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1288 #endif
1289
1290                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1291                                 /* The virtual register is allocated sequentially */
1292                                 rs->vassign [ins->dreg + 1] = -1;
1293                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1294                                 //reginfo [ins->dreg + 1].last_use = i;
1295                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1296                                         reginfo [ins->dreg + 1].born_in = i;
1297                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1298                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1299                         }
1300                 } else {
1301                         ins->dreg = -1;
1302                 }
1303
1304                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1305                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1306
1307                         MonoCallInst *call = (MonoCallInst*)ins;
1308                         GSList *list;
1309
1310                         list = call->out_ireg_args;
1311                         if (list) {
1312                                 while (list) {
1313                                         guint32 regpair;
1314                                         int reg, hreg;
1315
1316                                         regpair = (guint32)(gssize)(list->data);
1317                                         hreg = regpair >> 24;
1318                                         reg = regpair & 0xffffff;
1319
1320                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1321                                         //reginfo [reg].last_use = i;
1322
1323                                         list = g_slist_next (list);
1324                                 }
1325                         }
1326
1327                         list = call->out_freg_args;
1328                         if (list) {
1329                                 while (list) {
1330                                         guint32 regpair;
1331                                         int reg, hreg;
1332
1333                                         regpair = (guint32)(gssize)(list->data);
1334                                         hreg = regpair >> 24;
1335                                         reg = regpair & 0xffffff;
1336
1337                                         list = g_slist_next (list);
1338                                 }
1339                         }
1340                 }
1341
1342                 ++i;
1343         }
1344
1345         tmp = &last;
1346
1347         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1348         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1349                 int prev_dreg, clob_dreg;
1350                 int dest_dreg, clob_reg;
1351                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1352                 int dreg_high, sreg1_high;
1353                 regmask_t dreg_mask, mask;
1354                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1355                 regmask_t dreg_fixed_mask;
1356                 const unsigned char *ip;
1357                 --i;
1358                 spec = ins_get_spec (ins->opcode);
1359                 spec_src1 = spec [MONO_INST_SRC1];
1360                 spec_dest = spec [MONO_INST_DEST];
1361                 prev_dreg = -1;
1362                 clob_dreg = -1;
1363                 clob_reg = -1;
1364                 dest_dreg = -1;
1365                 dreg_high = -1;
1366                 sreg1_high = -1;
1367                 dreg_mask = get_callee_mask (spec_dest);
1368                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1369                         prev_sregs [j] = -1;
1370                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1371                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1372 #ifdef MONO_ARCH_INST_FIXED_MASK
1373                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1374 #else
1375                         sreg_fixed_masks [j] = 0;
1376 #endif
1377                 }
1378
1379                 DEBUG (printf ("processing:"));
1380                 DEBUG (mono_print_ins_index (i, ins));
1381
1382                 ip = ins->cil_code;
1383
1384                 last = ins;
1385
1386                 /*
1387                  * FIXED REGS
1388                  */
1389                 dest_dreg = desc_to_fixed_reg [spec_dest];
1390                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1391                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1392
1393 #ifdef MONO_ARCH_INST_FIXED_MASK
1394                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1395 #else
1396                 dreg_fixed_mask = 0;
1397 #endif
1398
1399                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1400
1401                 /*
1402                  * TRACK FIXED SREG2, 3, ...
1403                  */
1404                 for (j = 1; j < num_sregs; ++j) {
1405                         int sreg = sregs [j];
1406                         int dest_sreg = dest_sregs [j];
1407
1408                         if (dest_sreg == -1)
1409                                 continue;
1410
1411                         if (j == 2) {
1412                                 int k;
1413
1414                                 /*
1415                                  * CAS.
1416                                  * We need to special case this, since on x86, there are only 3
1417                                  * free registers, and the code below assigns one of them to
1418                                  * sreg, so we can run out of registers when trying to assign
1419                                  * dreg. Instead, we just set up the register masks, and let the
1420                                  * normal sreg2 assignment code handle this. It would be nice to
1421                                  * do this for all the fixed reg cases too, but there is too much
1422                                  * risk of breakage.
1423                                  */
1424
1425                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1426                                 sreg_masks [j] = regmask (dest_sreg);
1427                                 for (k = 0; k < num_sregs; ++k) {
1428                                         if (k != j)
1429                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1430                                 }
1431
1432                                 /*
1433                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1434                                  */
1435                                 for (k = 0; k < num_sregs; ++k) {
1436                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1437                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1438                                 }
1439
1440                                 /*
1441                                  * We can also run out of registers while processing sreg2 if sreg3 is
1442                                  * assigned to another hreg, so spill sreg3 now.
1443                                  */
1444                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1445                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1446                                 }
1447                                 continue;
1448                         }
1449
1450                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1451                                 if (is_global_ireg (sreg)) {
1452                                         int k;
1453                                         /* Argument already in hard reg, need to copy */
1454                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1455                                         insert_before_ins (bb, ins, copy);
1456                                         for (k = 0; k < num_sregs; ++k) {
1457                                                 if (k != j)
1458                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1459                                         }
1460                                         /* See below */
1461                                         dreg_mask &= ~ (regmask (dest_sreg));
1462                                 } else {
1463                                         val = rs->vassign [sreg];
1464                                         if (val == -1) {
1465                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1466                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1467                                         } else if (val < -1) {
1468                                                 /* FIXME: */
1469                                                 g_assert_not_reached ();
1470                                         } else {
1471                                                 /* Argument already in hard reg, need to copy */
1472                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1473                                                 int k;
1474
1475                                                 insert_before_ins (bb, ins, copy);
1476                                                 for (k = 0; k < num_sregs; ++k) {
1477                                                         if (k != j)
1478                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1479                                                 }
1480                                                 /*
1481                                                  * Prevent the dreg from being allocated to dest_sreg
1482                                                  * too, since it could force sreg1 to be allocated to
1483                                                  * the same reg on x86.
1484                                                  */
1485                                                 dreg_mask &= ~ (regmask (dest_sreg));
1486                                         }
1487                                 }
1488                         } else {
1489                                 gboolean need_spill = TRUE;
1490                                 gboolean need_assign = TRUE;
1491                                 int k;
1492
1493                                 dreg_mask &= ~ (regmask (dest_sreg));
1494                                 for (k = 0; k < num_sregs; ++k) {
1495                                         if (k != j)
1496                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1497                                 }
1498
1499                                 /*
1500                                  * First check if dreg is assigned to dest_sreg2, since we
1501                                  * can't spill a dreg.
1502                                  */
1503                                 if (spec [MONO_INST_DEST])
1504                                         val = rs->vassign [ins->dreg];
1505                                 else
1506                                         val = -1;
1507                                 if (val == dest_sreg && ins->dreg != sreg) {
1508                                         /*
1509                                          * the destination register is already assigned to
1510                                          * dest_sreg2: we need to allocate another register for it
1511                                          * and then copy from this to dest_sreg2.
1512                                          */
1513                                         int new_dest;
1514                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1515                                         g_assert (new_dest >= 0);
1516                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1517
1518                                         prev_dreg = ins->dreg;
1519                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1520                                         clob_dreg = ins->dreg;
1521                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1522                                         mono_regstate_free_int (rs, dest_sreg);
1523                                         need_spill = FALSE;
1524                                 }
1525
1526                                 if (is_global_ireg (sreg)) {
1527                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1528                                         insert_before_ins (bb, ins, copy);
1529                                         need_assign = FALSE;
1530                                 }
1531                                 else {
1532                                         val = rs->vassign [sreg];
1533                                         if (val == dest_sreg) {
1534                                                 /* sreg2 is already assigned to the correct register */
1535                                                 need_spill = FALSE;
1536                                         } else if (val < -1) {
1537                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1538                                         } else if (val >= 0) {
1539                                                 /* sreg2 already assigned to another register */
1540                                                 /*
1541                                                  * We couldn't emit a copy from val to dest_sreg2, because
1542                                                  * val might be spilled later while processing this
1543                                                  * instruction. So we spill sreg2 so it can be allocated to
1544                                                  * dest_sreg2.
1545                                                  */
1546                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1547                                         }
1548                                 }
1549
1550                                 if (need_spill) {
1551                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1552                                 }
1553
1554                                 if (need_assign) {
1555                                         if (rs->vassign [sreg] < -1) {
1556                                                 int spill;
1557
1558                                                 /* Need to emit a spill store */
1559                                                 spill = - rs->vassign [sreg] - 1;
1560                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1561                                         }
1562                                         /* force-set sreg2 */
1563                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1564                                 }
1565                         }
1566                         sregs [j] = dest_sreg;
1567                 }
1568                 mono_inst_set_src_registers (ins, sregs);
1569
1570                 /*
1571                  * TRACK DREG
1572                  */
1573                 bank = dreg_bank (spec);
1574                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1575                         prev_dreg = ins->dreg;
1576                 }
1577
1578                 if (spec_dest == 'b') {
1579                         /*
1580                          * The dest reg is read by the instruction, not written, so
1581                          * avoid allocating sreg1/sreg2 to the same reg.
1582                          */
1583                         if (dest_sregs [0] != -1)
1584                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1585                         for (j = 1; j < num_sregs; ++j) {
1586                                 if (dest_sregs [j] != -1)
1587                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1588                         }
1589
1590                         val = rs->vassign [ins->dreg];
1591                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1592                                 /* DREG is already allocated to a register needed for sreg1 */
1593                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1594                         }
1595                 }
1596
1597                 /*
1598                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1599                  * various complex situations.
1600                  */
1601                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1602                         guint32 dreg2, dest_dreg2;
1603
1604                         g_assert (is_soft_reg (ins->dreg, bank));
1605
1606                         if (dest_dreg != -1) {
1607                                 if (rs->vassign [ins->dreg] != dest_dreg)
1608                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1609
1610                                 dreg2 = ins->dreg + 1;
1611                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1612                                 if (dest_dreg2 != -1) {
1613                                         if (rs->vassign [dreg2] != dest_dreg2)
1614                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1615                                 }
1616                         }
1617                 }
1618
1619                 if (dreg_fixed_mask) {
1620                         g_assert (!bank);
1621                         if (is_global_ireg (ins->dreg)) {
1622                                 /*
1623                                  * The argument is already in a hard reg, but that reg is
1624                                  * not usable by this instruction, so allocate a new one.
1625                                  */
1626                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1627                                 if (val < 0)
1628                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1629                                 mono_regstate_free_int (rs, val);
1630                                 dest_dreg = val;
1631
1632                                 /* Fall through */
1633                         }
1634                         else
1635                                 dreg_mask &= dreg_fixed_mask;
1636                 }
1637
1638                 if (is_soft_reg (ins->dreg, bank)) {
1639                         val = rs->vassign [ins->dreg];
1640
1641                         if (val < 0) {
1642                                 int spill = 0;
1643                                 if (val < -1) {
1644                                         /* the register gets spilled after this inst */
1645                                         spill = -val -1;
1646                                 }
1647                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1648                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1649                                 if (spill)
1650                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1651                         }
1652
1653                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1654                         ins->dreg = val;
1655                 }
1656
1657                 /* Handle regpairs */
1658                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1659                         int reg2 = prev_dreg + 1;
1660
1661                         g_assert (!bank);
1662                         g_assert (prev_dreg > -1);
1663                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1664                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1665 #ifdef TARGET_X86
1666                         /* bug #80489 */
1667                         mask &= ~regmask (X86_ECX);
1668 #endif
1669                         val = rs->vassign [reg2];
1670                         if (val < 0) {
1671                                 int spill = 0;
1672                                 if (val < -1) {
1673                                         /* the register gets spilled after this inst */
1674                                         spill = -val -1;
1675                                 }
1676                                 val = mono_regstate_alloc_int (rs, mask);
1677                                 if (val < 0)
1678                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1679                                 if (spill)
1680                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1681                         }
1682                         else {
1683                                 if (! (mask & (regmask (val)))) {
1684                                         val = mono_regstate_alloc_int (rs, mask);
1685                                         if (val < 0)
1686                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1687
1688                                         /* Reallocate hreg to the correct register */
1689                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1690
1691                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1692                                 }
1693                         }
1694
1695                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1696                         assign_reg (cfg, rs, reg2, val, bank);
1697
1698                         dreg_high = val;
1699                         ins->backend.reg3 = val;
1700
1701                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1702                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1703                                 mono_regstate_free_int (rs, val);
1704                         }
1705                 }
1706
1707                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1708                         /*
1709                          * In theory, we could free up the hreg even if the vreg is alive,
1710                          * but branches inside bblocks force us to assign the same hreg
1711                          * to a vreg every time it is encountered.
1712                          */
1713                         int dreg = rs->vassign [prev_dreg];
1714                         g_assert (dreg >= 0);
1715                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1716                         if (G_UNLIKELY (bank))
1717                                 mono_regstate_free_general (rs, dreg, bank);
1718                         else
1719                                 mono_regstate_free_int (rs, dreg);
1720                         rs->vassign [prev_dreg] = -1;
1721                 }
1722
1723                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1724                         /* this instruction only outputs to dest_dreg, need to copy */
1725                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1726                         ins->dreg = dest_dreg;
1727
1728                         if (G_UNLIKELY (bank)) {
1729                                 /* the register we need to free up may be used in another logical regbank
1730                                  * so do a translate just in case.
1731                                  */
1732                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1733                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1734                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1735                         }
1736                         else {
1737                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1738                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1739                         }
1740                 }
1741
1742                 if (spec_dest == 'b') {
1743                         /*
1744                          * The dest reg is read by the instruction, not written, so
1745                          * avoid allocating sreg1/sreg2 to the same reg.
1746                          */
1747                         for (j = 0; j < num_sregs; ++j)
1748                                 if (!sreg_bank (j, spec))
1749                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1750                 }
1751
1752                 /*
1753                  * TRACK CLOBBERING
1754                  */
1755                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1756                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1757                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1758                 }
1759
1760                 if (spec [MONO_INST_CLOB] == 'c') {
1761                         int j, s, dreg, dreg2, cur_bank;
1762                         guint64 clob_mask;
1763
1764                         clob_mask = MONO_ARCH_CALLEE_REGS;
1765
1766                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1767                                 /*
1768                                  * Need to avoid spilling the dreg since the dreg is not really
1769                                  * clobbered by the call.
1770                                  */
1771                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1772                                         dreg = rs->vassign [prev_dreg];
1773                                 else
1774                                         dreg = -1;
1775
1776                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1777                                         dreg2 = rs->vassign [prev_dreg + 1];
1778                                 else
1779                                         dreg2 = -1;
1780
1781                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1782                                         s = regmask (j);
1783                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1784                                                 if ((j != dreg) && (j != dreg2))
1785                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1786                                                 else if (rs->isymbolic [j])
1787                                                         /* The hreg is assigned to the dreg of this instruction */
1788                                                         rs->vassign [rs->isymbolic [j]] = -1;
1789                                                 mono_regstate_free_int (rs, j);
1790                                         }
1791                                 }
1792                         }
1793
1794                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1795                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1796                                         clob_mask = regbank_callee_regs [cur_bank];
1797                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1798                                                 dreg = rs->vassign [prev_dreg];
1799                                         else
1800                                                 dreg = -1;
1801
1802                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1803
1804                                                 /* we are looping though the banks in the outer loop
1805                                                  * so, we don't need to deal with mirrored hregs
1806                                                  * because we will get them in one of the other bank passes.
1807                                                  */
1808                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1809                                                         continue;
1810
1811                                                 s = regmask (j);
1812                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1813                                                         if (j != dreg)
1814                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1815                                                         else if (rs->symbolic [cur_bank] [j])
1816                                                                 /* The hreg is assigned to the dreg of this instruction */
1817                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1818                                                         mono_regstate_free_general (rs, j, cur_bank);
1819                                                 }
1820                                         }
1821                                 }
1822                         }
1823                 }
1824
1825                 /*
1826                  * TRACK ARGUMENT REGS
1827                  */
1828                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1829                         MonoCallInst *call = (MonoCallInst*)ins;
1830                         GSList *list;
1831
1832                         /*
1833                          * This needs to be done before assigning sreg1, so sreg1 will
1834                          * not be assigned one of the argument regs.
1835                          */
1836
1837                         /*
1838                          * Assign all registers in call->out_reg_args to the proper
1839                          * argument registers.
1840                          */
1841
1842                         list = call->out_ireg_args;
1843                         if (list) {
1844                                 while (list) {
1845                                         guint32 regpair;
1846                                         int reg, hreg;
1847
1848                                         regpair = (guint32)(gssize)(list->data);
1849                                         hreg = regpair >> 24;
1850                                         reg = regpair & 0xffffff;
1851
1852                                         assign_reg (cfg, rs, reg, hreg, 0);
1853
1854                                         sreg_masks [0] &= ~(regmask (hreg));
1855
1856                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1857
1858                                         list = g_slist_next (list);
1859                                 }
1860                         }
1861
1862                         list = call->out_freg_args;
1863                         if (list) {
1864                                 while (list) {
1865                                         guint32 regpair;
1866                                         int reg, hreg;
1867
1868                                         regpair = (guint32)(gssize)(list->data);
1869                                         hreg = regpair >> 24;
1870                                         reg = regpair & 0xffffff;
1871
1872                                         assign_reg (cfg, rs, reg, hreg, 1);
1873
1874                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1875
1876                                         list = g_slist_next (list);
1877                                 }
1878                         }
1879                 }
1880
1881                 /*
1882                  * TRACK SREG1
1883                  */
1884                 bank = sreg1_bank (spec);
1885                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1886                         int sreg1 = sregs [0];
1887                         int dest_sreg1 = dest_sregs [0];
1888
1889                         g_assert (is_soft_reg (sreg1, bank));
1890
1891                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1892                         if (dest_sreg1 != -1)
1893                                 g_assert (dest_sreg1 == ins->dreg);
1894                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1895                         g_assert (val >= 0);
1896
1897                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1898                                 // FIXME:
1899                                 g_assert_not_reached ();
1900
1901                         assign_reg (cfg, rs, sreg1, val, bank);
1902
1903                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1904
1905                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1906                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1907                         g_assert (val >= 0);
1908
1909                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1910                                 // FIXME:
1911                                 g_assert_not_reached ();
1912
1913                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1914
1915                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1916
1917                         /* Skip rest of this section */
1918                         dest_sregs [0] = -1;
1919                 }
1920
1921                 if (sreg_fixed_masks [0]) {
1922                         g_assert (!bank);
1923                         if (is_global_ireg (sregs [0])) {
1924                                 /*
1925                                  * The argument is already in a hard reg, but that reg is
1926                                  * not usable by this instruction, so allocate a new one.
1927                                  */
1928                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1929                                 if (val < 0)
1930                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1931                                 mono_regstate_free_int (rs, val);
1932                                 dest_sregs [0] = val;
1933
1934                                 /* Fall through to the dest_sreg1 != -1 case */
1935                         }
1936                         else
1937                                 sreg_masks [0] &= sreg_fixed_masks [0];
1938                 }
1939
1940                 if (dest_sregs [0] != -1) {
1941                         sreg_masks [0] = regmask (dest_sregs [0]);
1942
1943                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1944                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1945                         }
1946                         if (is_global_ireg (sregs [0])) {
1947                                 /* The argument is already in a hard reg, need to copy */
1948                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1949                                 insert_before_ins (bb, ins, copy);
1950                                 sregs [0] = dest_sregs [0];
1951                         }
1952                 }
1953
1954                 if (is_soft_reg (sregs [0], bank)) {
1955                         val = rs->vassign [sregs [0]];
1956                         prev_sregs [0] = sregs [0];
1957                         if (val < 0) {
1958                                 int spill = 0;
1959                                 if (val < -1) {
1960                                         /* the register gets spilled after this inst */
1961                                         spill = -val -1;
1962                                 }
1963
1964                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1965                                         /*
1966                                          * Allocate the same hreg to sreg1 as well so the
1967                                          * peephole can get rid of the move.
1968                                          */
1969                                         sreg_masks [0] = regmask (ins->dreg);
1970                                 }
1971
1972                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1973                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1974                                         sreg_masks [0] = regmask (ins->dreg);
1975
1976                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1977                                 assign_reg (cfg, rs, sregs [0], val, bank);
1978                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1979
1980                                 if (spill) {
1981                                         /*
1982                                          * Need to insert before the instruction since it can
1983                                          * overwrite sreg1.
1984                                          */
1985                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1986                                 }
1987                         }
1988                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1989                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1990                                 insert_before_ins (bb, ins, copy);
1991                                 for (j = 1; j < num_sregs; ++j)
1992                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1993                                 val = dest_sregs [0];
1994                         }
1995
1996                         sregs [0] = val;
1997                 }
1998                 else {
1999                         prev_sregs [0] = -1;
2000                 }
2001                 mono_inst_set_src_registers (ins, sregs);
2002
2003                 for (j = 1; j < num_sregs; ++j)
2004                         sreg_masks [j] &= ~(regmask (sregs [0]));
2005
2006                 /* Handle the case when sreg1 is a regpair but dreg is not */
2007                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2008                         int reg2 = prev_sregs [0] + 1;
2009
2010                         g_assert (!bank);
2011                         g_assert (prev_sregs [0] > -1);
2012                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2013                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2014                         val = rs->vassign [reg2];
2015                         if (val < 0) {
2016                                 int spill = 0;
2017                                 if (val < -1) {
2018                                         /* the register gets spilled after this inst */
2019                                         spill = -val -1;
2020                                 }
2021                                 val = mono_regstate_alloc_int (rs, mask);
2022                                 if (val < 0)
2023                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2024                                 if (spill)
2025                                         g_assert_not_reached ();
2026                         }
2027                         else {
2028                                 if (! (mask & (regmask (val)))) {
2029                                         /* The vreg is already allocated to a wrong hreg */
2030                                         /* FIXME: */
2031                                         g_assert_not_reached ();
2032 #if 0
2033                                         val = mono_regstate_alloc_int (rs, mask);
2034                                         if (val < 0)
2035                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2036
2037                                         /* Reallocate hreg to the correct register */
2038                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2039
2040                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2041 #endif
2042                                 }
2043                         }
2044
2045                         sreg1_high = val;
2046                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2047                         assign_reg (cfg, rs, reg2, val, bank);
2048                 }
2049
2050                 /* Handle dreg==sreg1 */
2051                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2052                         MonoInst *sreg2_copy = NULL;
2053                         MonoInst *copy;
2054                         int bank = reg_bank (spec_src1);
2055
2056                         if (ins->dreg == sregs [1]) {
2057                                 /*
2058                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2059                                  * register for it.
2060                                  */
2061                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2062
2063                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2064                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2065                                 prev_sregs [1] = sregs [1] = reg2;
2066
2067                                 if (G_UNLIKELY (bank))
2068                                         mono_regstate_free_general (rs, reg2, bank);
2069                                 else
2070                                         mono_regstate_free_int (rs, reg2);
2071                         }
2072
2073                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2074                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2075                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2076                                         /* FIXME: */
2077                                         g_assert_not_reached ();
2078
2079                                 /*
2080                                  * sreg1 and dest are already allocated to the same regpair by the
2081                                  * SREG1 allocation code.
2082                                  */
2083                                 g_assert (sregs [0] == ins->dreg);
2084                                 g_assert (dreg_high == sreg1_high);
2085                         }
2086
2087                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2088                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2089                         insert_before_ins (bb, ins, copy);
2090
2091                         if (sreg2_copy)
2092                                 insert_before_ins (bb, copy, sreg2_copy);
2093
2094                         /*
2095                          * Need to prevent sreg2 to be allocated to sreg1, since that
2096                          * would screw up the previous copy.
2097                          */
2098                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2099                         /* we set sreg1 to dest as well */
2100                         prev_sregs [0] = sregs [0] = ins->dreg;
2101                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2102                 }
2103                 mono_inst_set_src_registers (ins, sregs);
2104
2105                 /*
2106                  * TRACK SREG2, 3, ...
2107                  */
2108                 for (j = 1; j < num_sregs; ++j) {
2109                         int k;
2110
2111                         bank = sreg_bank (j, spec);
2112                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2113                                 g_assert_not_reached ();
2114
2115                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2116                                 /*
2117                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2118                                  * allocating it to the fixed reg.
2119                                  */
2120                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2121                                 insert_before_ins (bb, ins, copy);
2122                                 sregs [j] = dest_sregs [j];
2123                         } else if (is_soft_reg (sregs [j], bank)) {
2124                                 val = rs->vassign [sregs [j]];
2125
2126                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2127                                         /*
2128                                          * The sreg is already allocated to a hreg, but not to the fixed
2129                                          * reg required by the instruction. Spill the sreg, so it can be
2130                                          * allocated to the fixed reg by the code below.
2131                                          */
2132                                         /* Currently, this code should only be hit for CAS */
2133                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2134                                         val = rs->vassign [sregs [j]];
2135                                 }
2136
2137                                 if (val < 0) {
2138                                         int spill = 0;
2139                                         if (val < -1) {
2140                                                 /* the register gets spilled after this inst */
2141                                                 spill = -val -1;
2142                                         }
2143                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2144                                         assign_reg (cfg, rs, sregs [j], val, bank);
2145                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2146                                         if (spill) {
2147                                                 /*
2148                                                  * Need to insert before the instruction since it can
2149                                                  * overwrite sreg2.
2150                                                  */
2151                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2152                                         }
2153                                 }
2154                                 sregs [j] = val;
2155                                 for (k = j + 1; k < num_sregs; ++k)
2156                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2157                         }
2158                         else {
2159                                 prev_sregs [j] = -1;
2160                         }
2161                 }
2162                 mono_inst_set_src_registers (ins, sregs);
2163
2164                 /* Sanity check */
2165                 /* Do this only for CAS for now */
2166                 for (j = 1; j < num_sregs; ++j) {
2167                         int sreg = sregs [j];
2168                         int dest_sreg = dest_sregs [j];
2169
2170                         if (j == 2 && dest_sreg != -1) {
2171                                 int k;
2172
2173                                 g_assert (sreg == dest_sreg);
2174
2175                                 for (k = 0; k < num_sregs; ++k) {
2176                                         if (k != j)
2177                                                 g_assert (sregs [k] != dest_sreg);
2178                                 }
2179                         }
2180                 }
2181
2182                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2183                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2184                         mono_regstate_free_int (rs, ins->sreg1);
2185                 }
2186                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2187                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2188                         mono_regstate_free_int (rs, ins->sreg2);
2189                 }*/
2190
2191                 DEBUG (mono_print_ins_index (i, ins));
2192         }
2193
2194         // FIXME: Set MAX_FREGS to 8
2195         // FIXME: Optimize generated code
2196 #if MONO_ARCH_USE_FPSTACK
2197         /*
2198          * Make a forward pass over the code, simulating the fp stack, making sure the
2199          * arguments required by the fp opcodes are at the top of the stack.
2200          */
2201         if (has_fp) {
2202                 MonoInst *prev = NULL;
2203                 MonoInst *fxch;
2204                 int tmp;
2205
2206                 g_assert (num_sregs <= 2);
2207
2208                 for (ins = bb->code; ins; ins = ins->next) {
2209                         spec = ins_get_spec (ins->opcode);
2210
2211                         DEBUG (printf ("processing:"));
2212                         DEBUG (mono_print_ins_index (0, ins));
2213
2214                         if (ins->opcode == OP_FMOVE) {
2215                                 /* Do it by renaming the source to the destination on the stack */
2216                                 // FIXME: Is this correct ?
2217                                 for (i = 0; i < sp; ++i)
2218                                         if (fpstack [i] == ins->sreg1)
2219                                                 fpstack [i] = ins->dreg;
2220                                 prev = ins;
2221                                 continue;
2222                         }
2223
2224                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2225                                 /* Arg1 must be in %st(1) */
2226                                 g_assert (prev);
2227
2228                                 i = 0;
2229                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2230                                         i ++;
2231                                 g_assert (i < sp);
2232
2233                                 if (sp - 1 - i > 0) {
2234                                         /* First move it to %st(0) */
2235                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2236
2237                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2238                                         fxch->inst_imm = sp - 1 - i;
2239
2240                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2241                                         prev = fxch;
2242
2243                                         tmp = fpstack [sp - 1];
2244                                         fpstack [sp - 1] = fpstack [i];
2245                                         fpstack [i] = tmp;
2246                                 }
2247
2248                                 /* Then move it to %st(1) */
2249                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2250
2251                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2252                                 fxch->inst_imm = 1;
2253
2254                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2255                                 prev = fxch;
2256
2257                                 tmp = fpstack [sp - 1];
2258                                 fpstack [sp - 1] = fpstack [sp - 2];
2259                                 fpstack [sp - 2] = tmp;
2260                         }
2261
2262                         if (sreg2_is_fp (spec)) {
2263                                 g_assert (sp > 0);
2264
2265                                 if (fpstack [sp - 1] != ins->sreg2) {
2266                                         g_assert (prev);
2267
2268                                         i = 0;
2269                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2270                                                 i ++;
2271                                         g_assert (i < sp);
2272
2273                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2274
2275                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2276                                         fxch->inst_imm = sp - 1 - i;
2277
2278                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2279                                         prev = fxch;
2280
2281                                         tmp = fpstack [sp - 1];
2282                                         fpstack [sp - 1] = fpstack [i];
2283                                         fpstack [i] = tmp;
2284                                 }
2285
2286                                 sp --;
2287                         }
2288
2289                         if (sreg1_is_fp (spec)) {
2290                                 g_assert (sp > 0);
2291
2292                                 if (fpstack [sp - 1] != ins->sreg1) {
2293                                         g_assert (prev);
2294
2295                                         i = 0;
2296                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2297                                                 i ++;
2298                                         g_assert (i < sp);
2299
2300                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2301
2302                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2303                                         fxch->inst_imm = sp - 1 - i;
2304
2305                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2306                                         prev = fxch;
2307
2308                                         tmp = fpstack [sp - 1];
2309                                         fpstack [sp - 1] = fpstack [i];
2310                                         fpstack [i] = tmp;
2311                                 }
2312
2313                                 sp --;
2314                         }
2315
2316                         if (dreg_is_fp (spec)) {
2317                                 g_assert (sp < 8);
2318                                 fpstack [sp ++] = ins->dreg;
2319                         }
2320
2321                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2322                                 printf ("\t[");
2323                                 for (i = 0; i < sp; ++i)
2324                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2325                                 printf ("]\n");
2326                         }
2327
2328                         prev = ins;
2329                 }
2330
2331                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2332                         /* Remove remaining items from the fp stack */
2333                         /*
2334                          * These can remain for example as a result of a dead fmove like in
2335                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2336                          */
2337                         while (sp) {
2338                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2339                                 mono_add_ins_to_end (bb, ins);
2340                                 sp --;
2341                         }
2342                 }
2343         }
2344 #endif
2345 }
2346
2347 CompRelation
2348 mono_opcode_to_cond (int opcode)
2349 {
2350         switch (opcode) {
2351         case OP_CEQ:
2352         case OP_IBEQ:
2353         case OP_ICEQ:
2354         case OP_LBEQ:
2355         case OP_LCEQ:
2356         case OP_FBEQ:
2357         case OP_FCEQ:
2358         case OP_COND_EXC_EQ:
2359         case OP_COND_EXC_IEQ:
2360         case OP_CMOV_IEQ:
2361         case OP_CMOV_LEQ:
2362                 return CMP_EQ;
2363         case OP_FCNEQ:
2364         case OP_ICNEQ:
2365         case OP_IBNE_UN:
2366         case OP_LBNE_UN:
2367         case OP_FBNE_UN:
2368         case OP_COND_EXC_NE_UN:
2369         case OP_COND_EXC_INE_UN:
2370         case OP_CMOV_INE_UN:
2371         case OP_CMOV_LNE_UN:
2372                 return CMP_NE;
2373         case OP_FCLE:
2374         case OP_ICLE:
2375         case OP_IBLE:
2376         case OP_LBLE:
2377         case OP_FBLE:
2378         case OP_CMOV_ILE:
2379         case OP_CMOV_LLE:
2380                 return CMP_LE;
2381         case OP_FCGE:
2382         case OP_ICGE:
2383         case OP_IBGE:
2384         case OP_LBGE:
2385         case OP_FBGE:
2386         case OP_CMOV_IGE:
2387         case OP_CMOV_LGE:
2388                 return CMP_GE;
2389         case OP_CLT:
2390         case OP_IBLT:
2391         case OP_ICLT:
2392         case OP_LBLT:
2393         case OP_LCLT:
2394         case OP_FBLT:
2395         case OP_FCLT:
2396         case OP_COND_EXC_LT:
2397         case OP_COND_EXC_ILT:
2398         case OP_CMOV_ILT:
2399         case OP_CMOV_LLT:
2400                 return CMP_LT;
2401         case OP_CGT:
2402         case OP_IBGT:
2403         case OP_ICGT:
2404         case OP_LBGT:
2405         case OP_LCGT:
2406         case OP_FBGT:
2407         case OP_FCGT:
2408         case OP_COND_EXC_GT:
2409         case OP_COND_EXC_IGT:
2410         case OP_CMOV_IGT:
2411         case OP_CMOV_LGT:
2412                 return CMP_GT;
2413
2414         case OP_ICLE_UN:
2415         case OP_IBLE_UN:
2416         case OP_LBLE_UN:
2417         case OP_FBLE_UN:
2418         case OP_COND_EXC_LE_UN:
2419         case OP_COND_EXC_ILE_UN:
2420         case OP_CMOV_ILE_UN:
2421         case OP_CMOV_LLE_UN:
2422                 return CMP_LE_UN;
2423
2424         case OP_ICGE_UN:
2425         case OP_IBGE_UN:
2426         case OP_LBGE_UN:
2427         case OP_FBGE_UN:
2428         case OP_CMOV_IGE_UN:
2429         case OP_CMOV_LGE_UN:
2430                 return CMP_GE_UN;
2431         case OP_CLT_UN:
2432         case OP_IBLT_UN:
2433         case OP_ICLT_UN:
2434         case OP_LBLT_UN:
2435         case OP_LCLT_UN:
2436         case OP_FBLT_UN:
2437         case OP_FCLT_UN:
2438         case OP_COND_EXC_LT_UN:
2439         case OP_COND_EXC_ILT_UN:
2440         case OP_CMOV_ILT_UN:
2441         case OP_CMOV_LLT_UN:
2442                 return CMP_LT_UN;
2443         case OP_CGT_UN:
2444         case OP_IBGT_UN:
2445         case OP_ICGT_UN:
2446         case OP_LBGT_UN:
2447         case OP_LCGT_UN:
2448         case OP_FCGT_UN:
2449         case OP_FBGT_UN:
2450         case OP_COND_EXC_GT_UN:
2451         case OP_COND_EXC_IGT_UN:
2452         case OP_CMOV_IGT_UN:
2453         case OP_CMOV_LGT_UN:
2454                 return CMP_GT_UN;
2455         default:
2456                 printf ("%s\n", mono_inst_name (opcode));
2457                 g_assert_not_reached ();
2458                 return 0;
2459         }
2460 }
2461
2462 CompRelation
2463 mono_negate_cond (CompRelation cond)
2464 {
2465         switch (cond) {
2466         case CMP_EQ:
2467                 return CMP_NE;
2468         case CMP_NE:
2469                 return CMP_EQ;
2470         case CMP_LE:
2471                 return CMP_GT;
2472         case CMP_GE:
2473                 return CMP_LT;
2474         case CMP_LT:
2475                 return CMP_GE;
2476         case CMP_GT:
2477                 return CMP_LE;
2478         case CMP_LE_UN:
2479                 return CMP_GT_UN;
2480         case CMP_GE_UN:
2481                 return CMP_LT_UN;
2482         case CMP_LT_UN:
2483                 return CMP_GE_UN;
2484         case CMP_GT_UN:
2485                 return CMP_LE_UN;
2486         default:
2487                 g_assert_not_reached ();
2488         }
2489 }
2490
2491 CompType
2492 mono_opcode_to_type (int opcode, int cmp_opcode)
2493 {
2494         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2495                 return CMP_TYPE_L;
2496         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2497                 return CMP_TYPE_I;
2498         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2499                 return CMP_TYPE_I;
2500         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2501                 return CMP_TYPE_L;
2502         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2503                 return CMP_TYPE_L;
2504         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2505                 return CMP_TYPE_F;
2506         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2507                 return CMP_TYPE_F;
2508         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2509                 return CMP_TYPE_I;
2510         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2511                 switch (cmp_opcode) {
2512                 case OP_ICOMPARE:
2513                 case OP_ICOMPARE_IMM:
2514                         return CMP_TYPE_I;
2515                 default:
2516                         return CMP_TYPE_L;
2517                 }
2518         } else {
2519                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2520                 return 0;
2521         }
2522 }
2523
2524 #endif /* DISABLE_JIT */
2525
2526 gboolean
2527 mono_is_regsize_var (MonoType *t)
2528 {
2529         if (t->byref)
2530                 return TRUE;
2531         t = mono_type_get_underlying_type (t);
2532         switch (t->type) {
2533         case MONO_TYPE_BOOLEAN:
2534         case MONO_TYPE_CHAR:
2535         case MONO_TYPE_I1:
2536         case MONO_TYPE_U1:
2537         case MONO_TYPE_I2:
2538         case MONO_TYPE_U2:
2539         case MONO_TYPE_I4:
2540         case MONO_TYPE_U4:
2541         case MONO_TYPE_I:
2542         case MONO_TYPE_U:
2543         case MONO_TYPE_PTR:
2544         case MONO_TYPE_FNPTR:
2545 #if SIZEOF_REGISTER == 8
2546         case MONO_TYPE_I8:
2547         case MONO_TYPE_U8:
2548 #endif
2549                 return TRUE;
2550         case MONO_TYPE_OBJECT:
2551         case MONO_TYPE_STRING:
2552         case MONO_TYPE_CLASS:
2553         case MONO_TYPE_SZARRAY:
2554         case MONO_TYPE_ARRAY:
2555                 return TRUE;
2556         case MONO_TYPE_GENERICINST:
2557                 if (!mono_type_generic_inst_is_valuetype (t))
2558                         return TRUE;
2559                 return FALSE;
2560         case MONO_TYPE_VALUETYPE:
2561                 return FALSE;
2562         default:
2563                 return FALSE;
2564         }
2565 }
2566
2567 #ifndef DISABLE_JIT
2568
2569 /*
2570  * mono_peephole_ins:
2571  *
2572  *   Perform some architecture independent peephole optimizations.
2573  */
2574 void
2575 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2576 {
2577         MonoInst *last_ins = ins->prev;
2578
2579         switch (ins->opcode) {
2580         case OP_MUL_IMM:
2581                 /* remove unnecessary multiplication with 1 */
2582                 if (ins->inst_imm == 1) {
2583                         if (ins->dreg != ins->sreg1)
2584                                 ins->opcode = OP_MOVE;
2585                         else
2586                                 MONO_DELETE_INS (bb, ins);
2587                 }
2588                 break;
2589         case OP_LOAD_MEMBASE:
2590         case OP_LOADI4_MEMBASE:
2591                 /*
2592                  * Note: if reg1 = reg2 the load op is removed
2593                  *
2594                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2595                  * OP_LOAD_MEMBASE offset(basereg), reg2
2596                  * -->
2597                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2598                  * OP_MOVE reg1, reg2
2599                  */
2600                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2601                         last_ins = last_ins->prev;
2602                 if (last_ins &&
2603                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2604                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2605                         ins->inst_basereg == last_ins->inst_destbasereg &&
2606                         ins->inst_offset == last_ins->inst_offset) {
2607                         if (ins->dreg == last_ins->sreg1) {
2608                                 MONO_DELETE_INS (bb, ins);
2609                                 break;
2610                         } else {
2611                                 ins->opcode = OP_MOVE;
2612                                 ins->sreg1 = last_ins->sreg1;
2613                         }
2614
2615                         /*
2616                          * Note: reg1 must be different from the basereg in the second load
2617                          * Note: if reg1 = reg2 is equal then second load is removed
2618                          *
2619                          * OP_LOAD_MEMBASE offset(basereg), reg1
2620                          * OP_LOAD_MEMBASE offset(basereg), reg2
2621                          * -->
2622                          * OP_LOAD_MEMBASE offset(basereg), reg1
2623                          * OP_MOVE reg1, reg2
2624                          */
2625                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2626                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2627                           ins->inst_basereg != last_ins->dreg &&
2628                           ins->inst_basereg == last_ins->inst_basereg &&
2629                           ins->inst_offset == last_ins->inst_offset) {
2630
2631                         if (ins->dreg == last_ins->dreg) {
2632                                 MONO_DELETE_INS (bb, ins);
2633                         } else {
2634                                 ins->opcode = OP_MOVE;
2635                                 ins->sreg1 = last_ins->dreg;
2636                         }
2637
2638                         //g_assert_not_reached ();
2639
2640 #if 0
2641                         /*
2642                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2643                          * OP_LOAD_MEMBASE offset(basereg), reg
2644                          * -->
2645                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2646                          * OP_ICONST reg, imm
2647                          */
2648                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2649                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2650                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2651                                    ins->inst_offset == last_ins->inst_offset) {
2652                         ins->opcode = OP_ICONST;
2653                         ins->inst_c0 = last_ins->inst_imm;
2654                         g_assert_not_reached (); // check this rule
2655 #endif
2656                 }
2657                 break;
2658         case OP_LOADI1_MEMBASE:
2659         case OP_LOADU1_MEMBASE:
2660                 /*
2661                  * Note: if reg1 = reg2 the load op is removed
2662                  *
2663                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2664                  * OP_LOAD_MEMBASE offset(basereg), reg2
2665                  * -->
2666                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2667                  * OP_MOVE reg1, reg2
2668                  */
2669                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2670                         ins->inst_basereg == last_ins->inst_destbasereg &&
2671                         ins->inst_offset == last_ins->inst_offset) {
2672                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2673                         ins->sreg1 = last_ins->sreg1;
2674                 }
2675                 break;
2676         case OP_LOADI2_MEMBASE:
2677         case OP_LOADU2_MEMBASE:
2678                 /*
2679                  * Note: if reg1 = reg2 the load op is removed
2680                  *
2681                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2682                  * OP_LOAD_MEMBASE offset(basereg), reg2
2683                  * -->
2684                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2685                  * OP_MOVE reg1, reg2
2686                  */
2687                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2688                         ins->inst_basereg == last_ins->inst_destbasereg &&
2689                         ins->inst_offset == last_ins->inst_offset) {
2690 #if SIZEOF_REGISTER == 8
2691                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2692 #else
2693                         /* The definition of OP_PCONV_TO_U2 is wrong */
2694                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2695 #endif
2696                         ins->sreg1 = last_ins->sreg1;
2697                 }
2698                 break;
2699         case OP_MOVE:
2700         case OP_FMOVE:
2701                 /*
2702                  * Removes:
2703                  *
2704                  * OP_MOVE reg, reg
2705                  */
2706                 if (ins->dreg == ins->sreg1) {
2707                         MONO_DELETE_INS (bb, ins);
2708                         break;
2709                 }
2710                 /*
2711                  * Removes:
2712                  *
2713                  * OP_MOVE sreg, dreg
2714                  * OP_MOVE dreg, sreg
2715                  */
2716                 if (last_ins && last_ins->opcode == ins->opcode &&
2717                         ins->sreg1 == last_ins->dreg &&
2718                         ins->dreg == last_ins->sreg1) {
2719                         MONO_DELETE_INS (bb, ins);
2720                 }
2721                 break;
2722         case OP_NOP:
2723                 MONO_DELETE_INS (bb, ins);
2724                 break;
2725         }
2726 }
2727
2728 int
2729 mini_exception_id_by_name (const char *name)
2730 {
2731         if (strcmp (name, "IndexOutOfRangeException") == 0)
2732                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2733         if (strcmp (name, "OverflowException") == 0)
2734                 return MONO_EXC_OVERFLOW;
2735         if (strcmp (name, "ArithmeticException") == 0)
2736                 return MONO_EXC_ARITHMETIC;
2737         if (strcmp (name, "DivideByZeroException") == 0)
2738                 return MONO_EXC_DIVIDE_BY_ZERO;
2739         if (strcmp (name, "InvalidCastException") == 0)
2740                 return MONO_EXC_INVALID_CAST;
2741         if (strcmp (name, "NullReferenceException") == 0)
2742                 return MONO_EXC_NULL_REF;
2743         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2744                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2745         if (strcmp (name, "ArgumentException") == 0)
2746                 return MONO_EXC_ARGUMENT;
2747         g_error ("Unknown intrinsic exception %s\n", name);
2748         return -1;
2749 }
2750
2751 #endif /* DISABLE_JIT */