mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30 /*
  31  * Every hardware register belongs to a register type or register bank. bank 0
  32  * contains the int registers, bank 1 contains the fp registers.
  33  * int registers are used 99% of the time, so they are special cased in a lot of
  34  * places.
  35  */
  36
  37 static const int regbank_size [] = {
  38         MONO_MAX_IREGS,
  39         MONO_MAX_FREGS,
  40         MONO_MAX_XREGS
  41 };
  42
  43 static const int regbank_load_ops [] = {
  44         OP_LOAD_MEMBASE,
  45         OP_LOADR8_MEMBASE,
  46         OP_LOADX_MEMBASE
  47 };
  48
  49 static const int regbank_store_ops [] = {
  50         OP_STORE_MEMBASE_REG,
  51         OP_STORER8_MEMBASE_REG,
  52         OP_STOREX_MEMBASE
  53 };
  54
  55 static const int regbank_move_ops [] = {
  56         OP_MOVE,
  57         OP_FMOVE,
  58         OP_XMOVE
  59 };
  60
  61 #define regmask(reg) (((regmask_t)1) << (reg))
  62
  63 static const regmask_t regbank_callee_saved_regs [] = {
  64         MONO_ARCH_CALLEE_SAVED_REGS,
  65         MONO_ARCH_CALLEE_SAVED_FREGS,
  66         MONO_ARCH_CALLEE_SAVED_XREGS,
  67 };
  68
  69 static const regmask_t regbank_callee_regs [] = {
  70         MONO_ARCH_CALLEE_REGS,
  71         MONO_ARCH_CALLEE_FREGS,
  72         MONO_ARCH_CALLEE_XREGS,
  73 };
  74
  75 static const int regbank_spill_var_size[] = {
  76         sizeof (gpointer),
  77         sizeof (double),
  78         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
  79 };
  80
  81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
  82
  83 static inline GSList*
  84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
  85 {
  86         GSList *new_list;
  87         GSList *last;
  88
  89         new_list = mono_mempool_alloc (mp, sizeof (GSList));
  90         new_list->data = data;
  91         new_list->next = NULL;
  92
  93         if (list) {
  94                 last = list;
  95                 while (last->next)
  96                         last = last->next;
  97                 last->next = new_list;
  98
  99                 return list;
 100         } else
 101                 return new_list;
 102 }
 103
 104 static inline void
 105 mono_regstate_assign (MonoRegState *rs)
 106 {
 107         if (rs->next_vreg > rs->vassign_size) {
 108                 g_free (rs->vassign);
 109                 rs->vassign_size = MAX (rs->next_vreg, 256);
 110                 rs->vassign = g_malloc (rs->vassign_size * sizeof (int));
 111         }
 112
 113         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 114         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 115
 116         rs->symbolic [0] = rs->isymbolic;
 117         rs->symbolic [1] = rs->fsymbolic;
 118
 119 #ifdef MONO_ARCH_NEED_SIMD_BANK
 120         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 121         rs->symbolic [2] = rs->xsymbolic;
 122 #endif
 123 }
 124
 125 static inline int
 126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 127 {
 128         regmask_t mask = allow & rs->ifree_mask;
 129
 130 #if defined(__x86_64__) && defined(__GNUC__)
 131  {
 132         guint64 i;
 133
 134         if (mask == 0)
 135                 return -1;
 136
 137         __asm__("bsfq %1,%0\n\t"
 138                         : "=r" (i) : "rm" (mask));
 139
 140         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 141         return i;
 142  }
 143 #else
 144         int i;
 145
 146         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 147                 if (mask & ((regmask_t)1 << i)) {
 148                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 149                         return i;
 150                 }
 151         }
 152         return -1;
 153 #endif
 154 }
 155
 156 static inline void
 157 mono_regstate_free_int (MonoRegState *rs, int reg)
 158 {
 159         if (reg >= 0) {
 160                 rs->ifree_mask |= (regmask_t)1 << reg;
 161                 rs->isymbolic [reg] = 0;
 162         }
 163 }
 164
 165 static inline int
 166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 167 {
 168         int i;
 169         regmask_t mask = allow & rs->free_mask [bank];
 170         for (i = 0; i < regbank_size [bank]; ++i) {
 171                 if (mask & ((regmask_t)1 << i)) {
 172                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 173                         return i;
 174                 }
 175         }
 176         return -1;
 177 }
 178
 179 static inline void
 180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 181 {
 182         if (reg >= 0) {
 183                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 184                 rs->symbolic [bank][reg] = 0;
 185         }
 186 }
 187
 188 const char*
 189 mono_regname_full (int reg, int bank)
 190 {
 191         if (G_UNLIKELY (bank)) {
 192 #if MONO_ARCH_NEED_SIMD_BANK
 193                 if (bank == 2)
 194                         return mono_arch_xregname (reg);
 195 #endif
 196                 g_assert (bank == 1);
 197                 return mono_arch_fregname (reg);
 198         } else {
 199                 return mono_arch_regname (reg);
 200         }
 201 }
 202
 203 void
 204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 205 {
 206         guint32 regpair;
 207
 208         regpair = (((guint32)hreg) << 24) + vreg;
 209         if (G_UNLIKELY (bank)) {
 210                 g_assert (vreg >= regbank_size [bank]);
 211                 g_assert (hreg < regbank_size [bank]);
 212                 call->used_fregs |= 1 << hreg;
 213                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 214         } else {
 215                 g_assert (vreg >= MONO_MAX_IREGS);
 216                 g_assert (hreg < MONO_MAX_IREGS);
 217                 call->used_iregs |= 1 << hreg;
 218                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 219         }
 220 }
 221
 222 static void
 223 resize_spill_info (MonoCompile *cfg, int bank)
 224 {
 225         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 226         int orig_len = cfg->spill_info_len [bank];
 227         int new_len = orig_len ? orig_len * 2 : 16;
 228         MonoSpillInfo *new_info;
 229         int i;
 230
 231         g_assert (bank < MONO_NUM_REGBANKS);
 232
 233         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 234         if (orig_info)
 235                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 236         for (i = orig_len; i < new_len; ++i)
 237                 new_info [i].offset = -1;
 238
 239         cfg->spill_info [bank] = new_info;
 240         cfg->spill_info_len [bank] = new_len;
 241 }
 242
 243 /*
 244  * returns the offset used by spillvar. It allocates a new
 245  * spill variable if necessary.
 246  */
 247 static inline int
 248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 249 {
 250         MonoSpillInfo *info;
 251         int size;
 252
 253         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 254                 while (spillvar >= cfg->spill_info_len [bank])
 255                         resize_spill_info (cfg, bank);
 256         }
 257
 258         /*
 259          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 260          */
 261         info = &cfg->spill_info [bank][spillvar];
 262         if (info->offset == -1) {
 263                 cfg->stack_offset += sizeof (gpointer) - 1;
 264                 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
 265
 266                 g_assert (bank < MONO_NUM_REGBANKS);
 267                 if (G_UNLIKELY (bank))
 268                         size = regbank_spill_var_size [bank];
 269                 else
 270                         size = sizeof (gpointer);
 271
 272                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 273                         cfg->stack_offset += size - 1;
 274                         cfg->stack_offset &= ~(size - 1);
 275                         info->offset = cfg->stack_offset;
 276                         cfg->stack_offset += size;
 277                 } else {
 278                         cfg->stack_offset += size - 1;
 279                         cfg->stack_offset &= ~(size - 1);
 280                         cfg->stack_offset += size;
 281                         info->offset = - cfg->stack_offset;
 282                 }
 283         }
 284
 285         return info->offset;
 286 }
 287
 288 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 289 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 290 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 291 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 292 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 293 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 294
 295 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 296 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 297 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 298 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 299 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 300
 301 #ifndef MONO_ARCH_INST_IS_FLOAT
 302 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 303 #endif
 304
 305 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 306 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 307 #define sreg1_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1]))
 308 #define sreg2_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC2]))
 309
 310 #define reg_is_simd(desc) ((desc) == 'x')
 311
 312 #ifdef MONO_ARCH_NEED_SIMD_BANK
 313
 314 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 315
 316 #else
 317
 318 #define reg_bank(desc) reg_is_fp ((desc))
 319
 320 #endif
 321
 322 #define sreg1_bank(spec) reg_bank ((spec)[MONO_INST_SRC1])
 323 #define sreg2_bank(spec) reg_bank ((spec)[MONO_INST_SRC2])
 324 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 325
 326 #define sreg1_bank_ins(ins) sreg1_bank (ins_get_spec ((ins)->opcode))
 327 #define sreg2_bank_ins(ins) sreg2_bank (ins_get_spec ((ins)->opcode))
 328 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 329
 330 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 331
 332 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 333 #undef is_global_ireg
 334 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 335 #endif
 336
 337 typedef struct {
 338         int born_in;
 339         int killed_in;
 340         /* Not (yet) used */
 341         //int last_use;
 342         //int prev_use;
 343         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 344 } RegTrack;
 345
 346 #ifndef DISABLE_LOGGING
 347 void
 348 mono_print_ins_index (int i, MonoInst *ins)
 349 {
 350         const char *spec = ins_get_spec (ins->opcode);
 351
 352         if (i != -1)
 353                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 354         else
 355                 printf (" %s", mono_inst_name (ins->opcode));
 356         if (spec == MONO_ARCH_CPU_SPEC) {
 357                 /* This is a lowered opcode */
 358                 if (ins->dreg != -1)
 359                         printf (" R%d <-", ins->dreg);
 360                 if (ins->sreg1 != -1)
 361                         printf (" R%d", ins->sreg1);
 362                 if (ins->sreg2 != -1)
 363                         printf (" R%d", ins->sreg2);
 364
 365                 switch (ins->opcode) {
 366                 case OP_LBNE_UN:
 367                 case OP_LBEQ:
 368                 case OP_LBLT:
 369                 case OP_LBLT_UN:
 370                 case OP_LBGT:
 371                 case OP_LBGT_UN:
 372                 case OP_LBGE:
 373                 case OP_LBGE_UN:
 374                 case OP_LBLE:
 375                 case OP_LBLE_UN:
 376                         if (!(ins->flags & MONO_INST_BRLABEL)) {
 377                                 if (!ins->inst_false_bb)
 378                                         printf (" [B%d]", ins->inst_true_bb->block_num);
 379                                 else
 380                                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 381                         }
 382                         break;
 383                 case OP_PHI:
 384                 case OP_FPHI: {
 385                         int i;
 386                         printf (" [%d (", (int)ins->inst_c0);
 387                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 388                                 if (i)
 389                                         printf (", ");
 390                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 391                         }
 392                         printf (")]");
 393                         break;
 394                 }
 395                 case OP_LDADDR:
 396                 case OP_OUTARG_VTRETADDR:
 397                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 398                         break;
 399                 case OP_REGOFFSET:
 400                         printf (" + 0x%lx", (long)ins->inst_offset);
 401                 default:
 402                         break;
 403                 }
 404
 405                 printf ("\n");
 406                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 407                 return;
 408         }
 409
 410         if (spec [MONO_INST_DEST]) {
 411                 int bank = dreg_bank (spec);
 412                 if (is_soft_reg (ins->dreg, bank)) {
 413                         if (spec [MONO_INST_DEST] == 'b') {
 414                                 if (ins->inst_offset == 0)
 415                                         printf (" [R%d] <-", ins->dreg);
 416                                 else
 417                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 418                         }
 419                         else
 420                                 printf (" R%d <-", ins->dreg);
 421                 } else if (spec [MONO_INST_DEST] == 'b') {
 422                         if (ins->inst_offset == 0)
 423                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 424                         else
 425                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 426                 } else
 427                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 428         }
 429         if (spec [MONO_INST_SRC1]) {
 430                 int bank = sreg1_bank (spec);
 431                 if (is_soft_reg (ins->sreg1, bank)) {
 432                         if (spec [MONO_INST_SRC1] == 'b')
 433                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 434                         else
 435                                 printf (" R%d", ins->sreg1);
 436                 } else if (spec [MONO_INST_SRC1] == 'b')
 437                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 438                 else
 439                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 440         }
 441         if (spec [MONO_INST_SRC2]) {
 442                 int bank = sreg2_bank (spec);
 443                 if (is_soft_reg (ins->sreg2, bank))
 444                         printf (" R%d", ins->sreg2);
 445                 else
 446                         printf (" %s", mono_regname_full (ins->sreg2, bank));
 447         }
 448
 449         switch (ins->opcode) {
 450         case OP_ICONST:
 451                 printf (" [%d]", (int)ins->inst_c0);
 452                 break;
 453 #if defined(__i386__) || defined(__x86_64__)
 454         case OP_X86_PUSH_IMM:
 455 #endif
 456         case OP_ICOMPARE_IMM:
 457         case OP_COMPARE_IMM:
 458         case OP_IADD_IMM:
 459         case OP_ISUB_IMM:
 460         case OP_IAND_IMM:
 461         case OP_IOR_IMM:
 462         case OP_IXOR_IMM:
 463                 printf (" [%d]", (int)ins->inst_imm);
 464                 break;
 465         case OP_ADD_IMM:
 466         case OP_LADD_IMM:
 467                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 468                 break;
 469         case OP_I8CONST:
 470                 printf (" [%lld]", (long long)ins->inst_l);
 471                 break;
 472         case OP_R8CONST:
 473                 printf (" [%f]", *(double*)ins->inst_p0);
 474                 break;
 475         case OP_R4CONST:
 476                 printf (" [%f]", *(float*)ins->inst_p0);
 477                 break;
 478         case CEE_CALL:
 479         case CEE_CALLVIRT:
 480         case OP_CALL:
 481         case OP_CALL_MEMBASE:
 482         case OP_CALL_REG:
 483         case OP_FCALL:
 484         case OP_FCALLVIRT:
 485         case OP_LCALL:
 486         case OP_LCALLVIRT:
 487         case OP_VCALL:
 488         case OP_VCALLVIRT:
 489         case OP_VCALL_REG:
 490         case OP_VCALL_MEMBASE:
 491         case OP_VCALL2:
 492         case OP_VCALL2_REG:
 493         case OP_VCALL2_MEMBASE:
 494         case OP_VOIDCALL:
 495         case OP_VOIDCALLVIRT: {
 496                 MonoCallInst *call = (MonoCallInst*)ins;
 497                 GSList *list;
 498
 499                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 500                         /*
 501                          * These are lowered opcodes, but they are in the .md files since the old
 502                          * JIT passes them to backends.
 503                          */
 504                         if (ins->dreg != -1)
 505                                 printf (" R%d <-", ins->dreg);
 506                 }
 507
 508                 if (call->method) {
 509                         char *full_name = mono_method_full_name (call->method, TRUE);
 510                         printf (" [%s]", full_name);
 511                         g_free (full_name);
 512                 } else if (call->fptr) {
 513                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 514                         if (info)
 515                                 printf (" [%s]", info->name);
 516                 }
 517
 518                 list = call->out_ireg_args;
 519                 while (list) {
 520                         guint32 regpair;
 521                         int reg, hreg;
 522
 523                         regpair = (guint32)(gssize)(list->data);
 524                         hreg = regpair >> 24;
 525                         reg = regpair & 0xffffff;
 526
 527                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 528
 529                         list = g_slist_next (list);
 530                 }
 531                 break;
 532         }
 533         case OP_BR:
 534         case OP_CALL_HANDLER:
 535                 printf (" [B%d]", ins->inst_target_bb->block_num);
 536                 break;
 537         case CEE_BNE_UN:
 538         case CEE_BEQ:
 539         case CEE_BLT:
 540         case CEE_BLT_UN:
 541         case CEE_BGT:
 542         case CEE_BGT_UN:
 543         case CEE_BGE:
 544         case CEE_BGE_UN:
 545         case CEE_BLE:
 546         case CEE_BLE_UN:
 547         case OP_IBNE_UN:
 548         case OP_IBEQ:
 549         case OP_IBLT:
 550         case OP_IBLT_UN:
 551         case OP_IBGT:
 552         case OP_IBGT_UN:
 553         case OP_IBGE:
 554         case OP_IBGE_UN:
 555         case OP_IBLE:
 556         case OP_IBLE_UN:
 557         case OP_LBNE_UN:
 558         case OP_LBEQ:
 559         case OP_LBLT:
 560         case OP_LBLT_UN:
 561         case OP_LBGT:
 562         case OP_LBGT_UN:
 563         case OP_LBGE:
 564         case OP_LBGE_UN:
 565         case OP_LBLE:
 566         case OP_LBLE_UN:
 567                 if (!(ins->flags & MONO_INST_BRLABEL)) {
 568                         if (!ins->inst_false_bb)
 569                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 570                         else
 571                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 572                 }
 573                 break;
 574         default:
 575                 break;
 576         }
 577
 578         if (spec [MONO_INST_CLOB])
 579                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 580         printf ("\n");
 581 }
 582
 583 static void
 584 print_regtrack (RegTrack *t, int num)
 585 {
 586         int i;
 587         char buf [32];
 588         const char *r;
 589
 590         for (i = 0; i < num; ++i) {
 591                 if (!t [i].born_in)
 592                         continue;
 593                 if (i >= MONO_MAX_IREGS) {
 594                         g_snprintf (buf, sizeof(buf), "R%d", i);
 595                         r = buf;
 596                 } else
 597                         r = mono_arch_regname (i);
 598                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 599         }
 600 }
 601 #else
 602 void
 603 mono_print_ins_index (int i, MonoInst *ins)
 604 {
 605 }
 606 #endif /* DISABLE_LOGGING */
 607
 608 void
 609 mono_print_ins (MonoInst *ins)
 610 {
 611         mono_print_ins_index (-1, ins);
 612 }
 613
 614 static inline void
 615 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 616 {
 617         /*
 618          * If this function is called multiple times, the new instructions are inserted
 619          * in the proper order.
 620          */
 621         mono_bblock_insert_before_ins (bb, ins, to_insert);
 622 }
 623
 624 static inline void
 625 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 626 {
 627         /*
 628          * If this function is called multiple times, the new instructions are inserted in
 629          * proper order.
 630          */
 631         mono_bblock_insert_after_ins (bb, *last, to_insert);
 632
 633         *last = to_insert;
 634 }
 635
 636 /*
 637  * Force the spilling of the variable in the symbolic register 'reg'.
 638  */
 639 static int
 640 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 641 {
 642         MonoInst *load;
 643         int i, sel, spill;
 644         int *symbolic;
 645         MonoRegState *rs = cfg->rs;
 646
 647         symbolic = rs->symbolic [bank];
 648         sel = rs->vassign [reg];
 649
 650         /*i = rs->isymbolic [sel];
 651         g_assert (i == reg);*/
 652         i = reg;
 653         spill = ++cfg->spill_count;
 654         rs->vassign [i] = -spill - 1;
 655         if (G_UNLIKELY (bank))
 656                 mono_regstate_free_general (rs, sel, bank);
 657         else
 658                 mono_regstate_free_int (rs, sel);
 659         /* we need to create a spill var and insert a load to sel after the current instruction */
 660         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 661         load->dreg = sel;
 662         load->inst_basereg = cfg->frame_reg;
 663         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 664         insert_after_ins (bb, ins, last, load);
 665         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 666         if (G_UNLIKELY (bank))
 667                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 668         else
 669                 i = mono_regstate_alloc_int (rs, regmask (sel));
 670         g_assert (i == sel);
 671
 672         return sel;
 673 }
 674
 675 /* This isn't defined on older glib versions and on some platforms */
 676 #ifndef G_GUINT64_FORMAT
 677 #define G_GUINT64_FORMAT "ul"
 678 #endif
 679
 680 static int
 681 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 682 {
 683         MonoInst *load;
 684         int i, sel, spill;
 685         int *symbolic;
 686         MonoRegState *rs = cfg->rs;
 687
 688         symbolic = rs->symbolic [bank];
 689
 690         g_assert (bank < MONO_NUM_REGBANKS);
 691
 692         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2));
 693         /* exclude the registers in the current instruction */
 694         if ((sreg1_bank_ins (ins) == bank) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, bank) || (is_soft_reg (ins->sreg1, bank) && rs->vassign [ins->sreg1] >= 0))) {
 695                 if (is_soft_reg (ins->sreg1, bank))
 696                         regmask &= ~ (regmask (rs->vassign [ins->sreg1]));
 697                 else
 698                         regmask &= ~ (regmask (ins->sreg1));
 699                 DEBUG (printf ("\t\texcluding sreg1 %s\n", mono_regname_full (ins->sreg1, bank)));
 700         }
 701         if ((sreg2_bank_ins (ins) == bank) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, bank) || (is_soft_reg (ins->sreg2, bank) && rs->vassign [ins->sreg2] >= 0))) {
 702                 if (is_soft_reg (ins->sreg2, bank))
 703                         regmask &= ~ (regmask (rs->vassign [ins->sreg2]));
 704                 else
 705                         regmask &= ~ (regmask (ins->sreg2));
 706                 DEBUG (printf ("\t\texcluding sreg2 %s %d\n", mono_regname_full (ins->sreg2, bank), ins->sreg2));
 707         }
 708         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 709                 regmask &= ~ (regmask (ins->dreg));
 710                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 711         }
 712
 713         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 714         g_assert (regmask); /* need at least a register we can free */
 715         sel = 0;
 716         /* we should track prev_use and spill the register that's farther */
 717         if (G_UNLIKELY (bank)) {
 718                 for (i = 0; i < regbank_size [bank]; ++i) {
 719                         if (regmask & (regmask (i))) {
 720                                 sel = i;
 721                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 722                                 break;
 723                         }
 724                 }
 725
 726                 i = rs->symbolic [bank] [sel];
 727                 spill = ++cfg->spill_count;
 728                 rs->vassign [i] = -spill - 1;
 729                 mono_regstate_free_general (rs, sel, bank);
 730         }
 731         else {
 732                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 733                         if (regmask & (regmask (i))) {
 734                                 sel = i;
 735                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 736                                 break;
 737                         }
 738                 }
 739
 740                 i = rs->isymbolic [sel];
 741                 spill = ++cfg->spill_count;
 742                 rs->vassign [i] = -spill - 1;
 743                 mono_regstate_free_int (rs, sel);
 744         }
 745
 746         /* we need to create a spill var and insert a load to sel after the current instruction */
 747         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 748         load->dreg = sel;
 749         load->inst_basereg = cfg->frame_reg;
 750         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 751         insert_after_ins (bb, ins, last, load);
 752         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 753         if (G_UNLIKELY (bank))
 754                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 755         else
 756                 i = mono_regstate_alloc_int (rs, regmask (sel));
 757         g_assert (i == sel);
 758
 759         return sel;
 760 }
 761
 762 static void
 763 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 764 {
 765         if (G_UNLIKELY (bank)) {
 766                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 767                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 768                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 769                         mono_regstate_free_general (cfg->rs, hreg, bank);
 770                 }
 771         }
 772         else {
 773                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 774                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 775                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 776                         mono_regstate_free_int (cfg->rs, hreg);
 777                 }
 778         }
 779 }
 780
 781 static MonoInst*
 782 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 783 {
 784         MonoInst *copy;
 785
 786         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 787
 788         copy->dreg = dest;
 789         copy->sreg1 = src;
 790         copy->cil_code = ip;
 791         if (ins) {
 792                 mono_bblock_insert_after_ins (bb, ins, copy);
 793                 *last = copy;
 794         }
 795         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 796         return copy;
 797 }
 798
 799 static MonoInst*
 800 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 801 {
 802         MonoInst *store;
 803         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 804         store->sreg1 = reg;
 805         store->inst_destbasereg = cfg->frame_reg;
 806         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 807         if (ins) {
 808                 mono_bblock_insert_after_ins (bb, ins, store);
 809                 *last = store;
 810         }
 811         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 812         return store;
 813 }
 814
 815 /* flags used in reginfo->flags */
 816 enum {
 817         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 818         MONO_FP_NEEDS_SPILL                     = regmask (1),
 819         MONO_FP_NEEDS_LOAD                      = regmask (2)
 820 };
 821
 822 static inline int
 823 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 824 {
 825         int val;
 826
 827         if (info && info->preferred_mask) {
 828                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 829                 if (val >= 0) {
 830                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 831                         return val;
 832                 }
 833         }
 834
 835         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 836         if (val < 0)
 837                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 838
 839         return val;
 840 }
 841
 842 static inline int
 843 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 844 {
 845         int val;
 846
 847         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 848
 849         if (val < 0)
 850                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 851
 852         return val;
 853 }
 854
 855 static inline int
 856 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 857 {
 858         if (G_UNLIKELY (bank))
 859                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 860         else
 861                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 862 }
 863
 864 static inline void
 865 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 866 {
 867         if (G_UNLIKELY (bank)) {
 868                 g_assert (reg >= regbank_size [bank]);
 869                 g_assert (hreg < regbank_size [bank]);
 870                 g_assert (! is_global_freg (hreg));
 871
 872                 rs->vassign [reg] = hreg;
 873                 rs->symbolic [bank] [hreg] = reg;
 874                 rs->free_mask [bank] &= ~ (regmask (hreg));
 875         }
 876         else {
 877                 g_assert (reg >= MONO_MAX_IREGS);
 878                 g_assert (hreg < MONO_MAX_IREGS);
 879 #ifndef __arm__
 880                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 881                 g_assert (! is_global_ireg (hreg));
 882 #endif
 883
 884                 rs->vassign [reg] = hreg;
 885                 rs->isymbolic [hreg] = reg;
 886                 rs->ifree_mask &= ~ (regmask (hreg));
 887         }
 888 }
 889
 890 static inline regmask_t
 891 get_callee_mask (const char spec)
 892 {
 893         if (G_UNLIKELY (reg_bank (spec)))
 894                 return regbank_callee_regs [reg_bank (spec)];
 895         return MONO_ARCH_CALLEE_REGS;
 896 }
 897
 898 static gint8 desc_to_fixed_reg [256];
 899 static gboolean desc_to_fixed_reg_inited = FALSE;
 900
 901 /*
 902  * Local register allocation.
 903  * We first scan the list of instructions and we save the liveness info of
 904  * each register (when the register is first used, when it's value is set etc.).
 905  * We also reverse the list of instructions because assigning registers backwards allows
 906  * for more tricks to be used.
 907  */
 908 void
 909 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 910 {
 911         MonoInst *ins, *prev, *last;
 912         MonoInst **tmp;
 913         MonoRegState *rs = cfg->rs;
 914         int i, val, max;
 915         RegTrack *reginfo;
 916         const char *spec;
 917         unsigned char spec_src1, spec_src2, spec_dest;
 918         int bank = 0;
 919 #if MONO_ARCH_USE_FPSTACK
 920         gboolean has_fp = FALSE;
 921         int fpstack [8];
 922         int sp = 0;
 923 #endif
 924
 925         if (!bb->code)
 926                 return;
 927
 928         if (!desc_to_fixed_reg_inited) {
 929                 for (i = 0; i < 256; ++i)
 930                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
 931                 desc_to_fixed_reg_inited = TRUE;
 932         }
 933
 934         rs->next_vreg = bb->max_vreg;
 935         mono_regstate_assign (rs);
 936
 937         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
 938         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
 939                 rs->free_mask [i] = regbank_callee_regs [i];
 940
 941         max = rs->next_vreg;
 942
 943         if (cfg->reginfo && cfg->reginfo_len < max)
 944                 cfg->reginfo = NULL;
 945
 946         reginfo = cfg->reginfo;
 947         if (!reginfo) {
 948                 cfg->reginfo_len = MAX (1024, max * 2);
 949                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
 950         }
 951         else
 952                 g_assert (cfg->reginfo_len >= rs->next_vreg);
 953
 954         if (cfg->verbose_level > 1) {
 955                 /* print_regtrack reads the info of all variables */
 956                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
 957         }
 958
 959         /*
 960          * For large methods, next_vreg can be very large, so g_malloc0 time can
 961          * be prohibitive. So we manually init the reginfo entries used by the
 962          * bblock.
 963          */
 964         for (ins = bb->code; ins; ins = ins->next) {
 965                 spec = ins_get_spec (ins->opcode);
 966
 967                 if ((ins->dreg != -1) && (ins->dreg < max)) {
 968                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
 969 #if SIZEOF_VOID_P == 4
 970                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
 971                                 /**
 972                                  * In the new IR, the two vregs of the regpair do not alias the
 973                                  * original long vreg. shift the vreg here so the rest of the
 974                                  * allocator doesn't have to care about it.
 975                                  */
 976                                 ins->dreg ++;
 977                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
 978                         }
 979 #endif
 980                 }
 981                 if ((ins->sreg1 != -1) && (ins->sreg1 < max)) {
 982                         memset (&reginfo [ins->sreg1], 0, sizeof (RegTrack));
 983 #if SIZEOF_VOID_P == 4
 984                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1])) {
 985                                 ins->sreg1 ++;
 986                                 memset (&reginfo [ins->sreg1 + 1], 0, sizeof (RegTrack));
 987                         }
 988 #endif
 989                 }
 990                 if ((ins->sreg2 != -1) && (ins->sreg2 < max)) {
 991                         memset (&reginfo [ins->sreg2], 0, sizeof (RegTrack));
 992 #if SIZEOF_VOID_P == 4
 993                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
 994                                 ins->sreg2 ++;
 995                                 memset (&reginfo [ins->sreg2 + 1], 0, sizeof (RegTrack));
 996                         }
 997 #endif
 998                 }
 999         }
1000
1001         /*if (cfg->opt & MONO_OPT_COPYPROP)
1002                 local_copy_prop (cfg, ins);*/
1003
1004         i = 1;
1005         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1006         /* forward pass on the instructions to collect register liveness info */
1007         MONO_BB_FOR_EACH_INS (bb, ins) {
1008                 spec = ins_get_spec (ins->opcode);
1009                 spec_src1 = spec [MONO_INST_SRC1];
1010                 spec_src2 = spec [MONO_INST_SRC2];
1011                 spec_dest = spec [MONO_INST_DEST];
1012
1013                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1014                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1015                 }
1016
1017                 DEBUG (mono_print_ins_index (i, ins));
1018
1019 #if MONO_ARCH_USE_FPSTACK
1020                 if (sreg1_is_fp (spec) || sreg2_is_fp (spec) || dreg_is_fp (spec))
1021                         has_fp = TRUE;
1022 #endif
1023
1024                 if (spec_src1) {
1025                         bank = sreg1_bank (spec);
1026                         g_assert (ins->sreg1 != -1);
1027                         if (is_soft_reg (ins->sreg1, bank))
1028                                 /* This means the vreg is not local to this bb */
1029                                 g_assert (reginfo [ins->sreg1].born_in > 0);
1030                         rs->vassign [ins->sreg1] = -1;
1031                         //reginfo [ins->sreg1].prev_use = reginfo [ins->sreg1].last_use;
1032                         //reginfo [ins->sreg1].last_use = i;
1033                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1034                                 /* The virtual register is allocated sequentially */
1035                                 rs->vassign [ins->sreg1 + 1] = -1;
1036                                 //reginfo [ins->sreg1 + 1].prev_use = reginfo [ins->sreg1 + 1].last_use;
1037                                 //reginfo [ins->sreg1 + 1].last_use = i;
1038                                 if (reginfo [ins->sreg1 + 1].born_in == 0 || reginfo [ins->sreg1 + 1].born_in > i)
1039                                         reginfo [ins->sreg1 + 1].born_in = i;
1040                         }
1041                 } else {
1042                         ins->sreg1 = -1;
1043                 }
1044                 if (spec_src2) {
1045                         bank = sreg2_bank (spec);
1046                         g_assert (ins->sreg2 != -1);
1047                         if (is_soft_reg (ins->sreg2, bank))
1048                                 /* This means the vreg is not local to this bb */
1049                                 g_assert (reginfo [ins->sreg2].born_in > 0);
1050                         rs->vassign [ins->sreg2] = -1;
1051                         //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1052                         //reginfo [ins->sreg2].last_use = i;
1053                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1054                                 /* The virtual register is allocated sequentially */
1055                                 rs->vassign [ins->sreg2 + 1] = -1;
1056                                 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1057                                 //reginfo [ins->sreg2 + 1].last_use = i;
1058                                 if (reginfo [ins->sreg2 + 1].born_in == 0 || reginfo [ins->sreg2 + 1].born_in > i)
1059                                         reginfo [ins->sreg2 + 1].born_in = i;
1060                         }
1061                 } else {
1062                         ins->sreg2 = -1;
1063                 }
1064                 if (spec_dest) {
1065                         int dest_dreg;
1066
1067                         bank = dreg_bank (spec);
1068                         if (spec_dest != 'b') /* it's not just a base register */
1069                                 reginfo [ins->dreg].killed_in = i;
1070                         g_assert (ins->dreg != -1);
1071                         rs->vassign [ins->dreg] = -1;
1072                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1073                         //reginfo [ins->dreg].last_use = i;
1074                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1075                                 reginfo [ins->dreg].born_in = i;
1076
1077                         dest_dreg = desc_to_fixed_reg [spec_dest];
1078                         if (dest_dreg != -1)
1079                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1080
1081 #ifdef MONO_ARCH_INST_FIXED_MASK
1082                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1083 #endif
1084
1085                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1086                                 /* The virtual register is allocated sequentially */
1087                                 rs->vassign [ins->dreg + 1] = -1;
1088                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1089                                 //reginfo [ins->dreg + 1].last_use = i;
1090                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1091                                         reginfo [ins->dreg + 1].born_in = i;
1092                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1093                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1094                         }
1095                 } else {
1096                         ins->dreg = -1;
1097                 }
1098
1099                 if (spec [MONO_INST_CLOB] == 'c') {
1100                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1101
1102                         MonoCallInst *call = (MonoCallInst*)ins;
1103                         GSList *list;
1104
1105                         list = call->out_ireg_args;
1106                         if (list) {
1107                                 while (list) {
1108                                         guint32 regpair;
1109                                         int reg, hreg;
1110
1111                                         regpair = (guint32)(gssize)(list->data);
1112                                         hreg = regpair >> 24;
1113                                         reg = regpair & 0xffffff;
1114
1115                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1116                                         //reginfo [reg].last_use = i;
1117
1118                                         list = g_slist_next (list);
1119                                 }
1120                         }
1121
1122                         list = call->out_freg_args;
1123                         if (list) {
1124                                 while (list) {
1125                                         guint32 regpair;
1126                                         int reg, hreg;
1127
1128                                         regpair = (guint32)(gssize)(list->data);
1129                                         hreg = regpair >> 24;
1130                                         reg = regpair & 0xffffff;
1131
1132                                         list = g_slist_next (list);
1133                                 }
1134                         }
1135                 }
1136
1137                 ++i;
1138         }
1139
1140         tmp = &last;
1141
1142         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1143         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1144                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1145                 int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
1146                 int dreg_high, sreg1_high;
1147                 regmask_t dreg_mask, sreg1_mask, sreg2_mask, mask;
1148                 regmask_t dreg_fixed_mask, sreg1_fixed_mask, sreg2_fixed_mask;
1149                 const unsigned char *ip;
1150                 --i;
1151                 spec = ins_get_spec (ins->opcode);
1152                 spec_src1 = spec [MONO_INST_SRC1];
1153                 spec_src2 = spec [MONO_INST_SRC2];
1154                 spec_dest = spec [MONO_INST_DEST];
1155                 prev_dreg = -1;
1156                 prev_sreg2 = -1;
1157                 clob_dreg = -1;
1158                 clob_reg = -1;
1159                 dest_dreg = -1;
1160                 dest_sreg1 = -1;
1161                 dest_sreg2 = -1;
1162                 prev_sreg1 = -1;
1163                 dreg_high = -1;
1164                 sreg1_high = -1;
1165                 dreg_mask = get_callee_mask (spec_dest);
1166                 sreg1_mask = get_callee_mask (spec_src1);
1167                 sreg2_mask = get_callee_mask (spec_src2);
1168
1169                 DEBUG (printf ("processing:"));
1170                 DEBUG (mono_print_ins_index (i, ins));
1171
1172                 ip = ins->cil_code;
1173
1174                 last = ins;
1175
1176                 /*
1177                  * FIXED REGS
1178                  */
1179                 dest_sreg1 = desc_to_fixed_reg [spec_src1];
1180                 dest_sreg2 = desc_to_fixed_reg [spec_src2];
1181                 dest_dreg = desc_to_fixed_reg [spec_dest];
1182                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1183                 sreg2_mask &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1184
1185 #ifdef MONO_ARCH_INST_FIXED_MASK
1186                 sreg1_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src1);
1187                 sreg2_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src2);
1188                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1189 #else
1190                 sreg1_fixed_mask = sreg2_fixed_mask = dreg_fixed_mask = 0;
1191 #endif
1192
1193                 /*
1194                  * TRACK FIXED SREG2
1195                  */
1196                 if (dest_sreg2 != -1) {
1197                         if (rs->ifree_mask & (regmask (dest_sreg2))) {
1198                                 if (is_global_ireg (ins->sreg2)) {
1199                                         /* Argument already in hard reg, need to copy */
1200                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1201                                         insert_before_ins (bb, ins, copy);
1202                                 }
1203                                 else {
1204                                         val = rs->vassign [ins->sreg2];
1205                                         if (val == -1) {
1206                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
1207                                                 assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1208                                         } else if (val < -1) {
1209                                                 /* FIXME: */
1210                                                 g_assert_not_reached ();
1211                                         } else {
1212                                                 /* Argument already in hard reg, need to copy */
1213                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, val, NULL, ip, 0);
1214                                                 insert_before_ins (bb, ins, copy);
1215                                         }
1216                                 }
1217                         } else {
1218                                 gboolean need_spill = TRUE;
1219                                 gboolean need_assign = TRUE;
1220
1221                                 dreg_mask &= ~ (regmask (dest_sreg2));
1222                                 sreg1_mask &= ~ (regmask (dest_sreg2));
1223
1224                                 /*
1225                                  * First check if dreg is assigned to dest_sreg2, since we
1226                                  * can't spill a dreg.
1227                                  */
1228                                 val = rs->vassign [ins->dreg];
1229                                 if (val == dest_sreg2 && ins->dreg != ins->sreg2) {
1230                                         /*
1231                                          * the destination register is already assigned to
1232                                          * dest_sreg2: we need to allocate another register for it
1233                                          * and then copy from this to dest_sreg2.
1234                                          */
1235                                         int new_dest;
1236                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1237                                         g_assert (new_dest >= 0);
1238                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg2)));
1239
1240                                         prev_dreg = ins->dreg;
1241                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1242                                         clob_dreg = ins->dreg;
1243                                         create_copy_ins (cfg, bb, tmp, dest_sreg2, new_dest, ins, ip, 0);
1244                                         mono_regstate_free_int (rs, dest_sreg2);
1245                                         need_spill = FALSE;
1246                                 }
1247
1248                                 if (is_global_ireg (ins->sreg2)) {
1249                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1250                                         insert_before_ins (bb, ins, copy);
1251                                         need_assign = FALSE;
1252                                 }
1253                                 else {
1254                                         val = rs->vassign [ins->sreg2];
1255                                         if (val == dest_sreg2) {
1256                                                 /* sreg2 is already assigned to the correct register */
1257                                                 need_spill = FALSE;
1258                                         } else if (val < -1) {
1259                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1260                                         } else if (val >= 0) {
1261                                                 /* sreg2 already assigned to another register */
1262                                                 /*
1263                                                  * We couldn't emit a copy from val to dest_sreg2, because
1264                                                  * val might be spilled later while processing this
1265                                                  * instruction. So we spill sreg2 so it can be allocated to
1266                                                  * dest_sreg2.
1267                                                  */
1268                                                 DEBUG (printf ("\tforced spill of R%d\n", ins->sreg2));
1269                                                 free_up_reg (cfg, bb, tmp, ins, val, 0);
1270                                         }
1271                                 }
1272
1273                                 if (need_spill) {
1274                                         DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg2]));
1275                                         free_up_reg (cfg, bb, tmp, ins, dest_sreg2, 0);
1276                                 }
1277
1278                                 if (need_assign) {
1279                                         if (rs->vassign [ins->sreg2] < -1) {
1280                                                 MonoInst *store;
1281                                                 int spill;
1282
1283                                                 /* Need to emit a spill store */
1284                                                 spill = - rs->vassign [ins->sreg2] - 1;
1285                                                 store = create_spilled_store (cfg, bb, spill, dest_sreg2, ins->sreg2, tmp, NULL, bank);
1286                                                 insert_before_ins (bb, ins, store);
1287                                         }
1288                                         /* force-set sreg2 */
1289                                         assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1290                                 }
1291                         }
1292                         ins->sreg2 = dest_sreg2;
1293                 }
1294
1295                 /*
1296                  * TRACK DREG
1297                  */
1298                 bank = dreg_bank (spec);
1299                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1300                         prev_dreg = ins->dreg;
1301                 }
1302
1303                 if (spec_dest == 'b') {
1304                         /*
1305                          * The dest reg is read by the instruction, not written, so
1306                          * avoid allocating sreg1/sreg2 to the same reg.
1307                          */
1308                         if (!dest_sreg1 != -1)
1309                                 dreg_mask &= ~ (regmask (dest_sreg1));
1310                         if (dest_sreg2 != -1)
1311                                 dreg_mask &= ~ (regmask (dest_sreg2));
1312
1313                         val = rs->vassign [ins->dreg];
1314                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1315                                 /* DREG is already allocated to a register needed for sreg1 */
1316                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1317                                 mono_regstate_free_int (rs, val);
1318                         }
1319                 }
1320
1321                 /*
1322                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1323                  * various complex situations.
1324                  */
1325                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1326                         guint32 dreg2, dest_dreg2;
1327
1328                         g_assert (is_soft_reg (ins->dreg, bank));
1329
1330                         if (dest_dreg != -1) {
1331                                 if (rs->vassign [ins->dreg] != dest_dreg)
1332                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1333
1334                                 dreg2 = ins->dreg + 1;
1335                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1336                                 if (dest_dreg2 != -1) {
1337                                         if (rs->vassign [dreg2] != dest_dreg2)
1338                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1339                                 }
1340                         }
1341                 }
1342
1343                 if (dreg_fixed_mask) {
1344                         g_assert (!bank);
1345                         if (is_global_ireg (ins->dreg)) {
1346                                 /*
1347                                  * The argument is already in a hard reg, but that reg is
1348                                  * not usable by this instruction, so allocate a new one.
1349                                  */
1350                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1351                                 if (val < 0)
1352                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1353                                 mono_regstate_free_int (rs, val);
1354                                 dest_dreg = val;
1355
1356                                 /* Fall through */
1357                         }
1358                         else
1359                                 dreg_mask &= dreg_fixed_mask;
1360                 }
1361
1362                 if (is_soft_reg (ins->dreg, bank)) {
1363                         val = rs->vassign [ins->dreg];
1364
1365                         if (val < 0) {
1366                                 int spill = 0;
1367                                 if (val < -1) {
1368                                         /* the register gets spilled after this inst */
1369                                         spill = -val -1;
1370                                 }
1371                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1372                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1373                                 if (spill)
1374                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1375                         }
1376
1377                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1378                         ins->dreg = val;
1379                 }
1380
1381                 /* Handle regpairs */
1382                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1383                         int reg2 = prev_dreg + 1;
1384
1385                         g_assert (!bank);
1386                         g_assert (prev_dreg > -1);
1387                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1388                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1389 #ifdef __i386__
1390                         /* bug #80489 */
1391                         mask &= ~regmask (X86_ECX);
1392 #endif
1393                         val = rs->vassign [reg2];
1394                         if (val < 0) {
1395                                 int spill = 0;
1396                                 if (val < -1) {
1397                                         /* the register gets spilled after this inst */
1398                                         spill = -val -1;
1399                                 }
1400                                 val = mono_regstate_alloc_int (rs, mask);
1401                                 if (val < 0)
1402                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1403                                 if (spill)
1404                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1405                         }
1406                         else {
1407                                 if (! (mask & (regmask (val)))) {
1408                                         val = mono_regstate_alloc_int (rs, mask);
1409                                         if (val < 0)
1410                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1411
1412                                         /* Reallocate hreg to the correct register */
1413                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1414
1415                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1416                                 }
1417                         }
1418
1419                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1420                         assign_reg (cfg, rs, reg2, val, bank);
1421
1422                         dreg_high = val;
1423                         ins->backend.reg3 = val;
1424
1425                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1426                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1427                                 mono_regstate_free_int (rs, val);
1428                         }
1429                 }
1430
1431                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1432                         /*
1433                          * In theory, we could free up the hreg even if the vreg is alive,
1434                          * but branches inside bblocks force us to assign the same hreg
1435                          * to a vreg every time it is encountered.
1436                          */
1437                         int dreg = rs->vassign [prev_dreg];
1438                         g_assert (dreg >= 0);
1439                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1440                         if (G_UNLIKELY (bank))
1441                                 mono_regstate_free_general (rs, dreg, bank);
1442                         else
1443                                 mono_regstate_free_int (rs, dreg);
1444                         rs->vassign [prev_dreg] = -1;
1445                 }
1446
1447                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1448                         /* this instruction only outputs to dest_dreg, need to copy */
1449                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1450                         ins->dreg = dest_dreg;
1451
1452                         if (G_UNLIKELY (bank)) {
1453                                 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1454                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1455                         }
1456                         else {
1457                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1458                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1459                         }
1460                 }
1461
1462                 if (spec_dest == 'b') {
1463                         /*
1464                          * The dest reg is read by the instruction, not written, so
1465                          * avoid allocating sreg1/sreg2 to the same reg.
1466                          */
1467                         if (!sreg1_bank (spec))
1468                                 sreg1_mask &= ~ (regmask (ins->dreg));
1469                         if (!sreg2_bank (spec))
1470                                 sreg2_mask &= ~ (regmask (ins->dreg));
1471                 }
1472
1473                 /*
1474                  * TRACK CLOBBERING
1475                  */
1476                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1477                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1478                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1479                         mono_regstate_free_int (rs, clob_reg);
1480                 }
1481
1482                 if (spec [MONO_INST_CLOB] == 'c') {
1483                         int j, s, dreg, dreg2, cur_bank;
1484                         guint64 clob_mask;
1485
1486                         clob_mask = MONO_ARCH_CALLEE_REGS;
1487
1488                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1489                                 /*
1490                                  * Need to avoid spilling the dreg since the dreg is not really
1491                                  * clobbered by the call.
1492                                  */
1493                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1494                                         dreg = rs->vassign [prev_dreg];
1495                                 else
1496                                         dreg = -1;
1497
1498                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1499                                         dreg2 = rs->vassign [prev_dreg + 1];
1500                                 else
1501                                         dreg2 = -1;
1502
1503                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1504                                         s = regmask (j);
1505                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1506                                                 if ((j != dreg) && (j != dreg2))
1507                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1508                                                 else if (rs->isymbolic [j])
1509                                                         /* The hreg is assigned to the dreg of this instruction */
1510                                                         rs->vassign [rs->isymbolic [j]] = -1;
1511                                                 mono_regstate_free_int (rs, j);
1512                                         }
1513                                 }
1514                         }
1515
1516                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1517                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1518                                         clob_mask = regbank_callee_regs [cur_bank];
1519                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1520                                                 dreg = rs->vassign [prev_dreg];
1521                                         else
1522                                                 dreg = -1;
1523
1524                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1525                                                 s = regmask (j);
1526                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1527                                                         if (j != dreg)
1528                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1529                                                         else if (rs->symbolic [cur_bank] [j])
1530                                                                 /* The hreg is assigned to the dreg of this instruction */
1531                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1532                                                         mono_regstate_free_general (rs, j, cur_bank);
1533                                                 }
1534                                         }
1535                                 }
1536                         }
1537                 }
1538
1539                 /*
1540                  * TRACK ARGUMENT REGS
1541                  */
1542                 if (spec [MONO_INST_CLOB] == 'c') {
1543                         MonoCallInst *call = (MonoCallInst*)ins;
1544                         GSList *list;
1545
1546                         /*
1547                          * This needs to be done before assigning sreg1, so sreg1 will
1548                          * not be assigned one of the argument regs.
1549                          */
1550
1551                         /*
1552                          * Assign all registers in call->out_reg_args to the proper
1553                          * argument registers.
1554                          */
1555
1556                         list = call->out_ireg_args;
1557                         if (list) {
1558                                 while (list) {
1559                                         guint32 regpair;
1560                                         int reg, hreg;
1561
1562                                         regpair = (guint32)(gssize)(list->data);
1563                                         hreg = regpair >> 24;
1564                                         reg = regpair & 0xffffff;
1565
1566                                         assign_reg (cfg, rs, reg, hreg, 0);
1567
1568                                         sreg1_mask &= ~(regmask (hreg));
1569
1570                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1571
1572                                         list = g_slist_next (list);
1573                                 }
1574                         }
1575
1576                         list = call->out_freg_args;
1577                         if (list) {
1578                                 while (list) {
1579                                         guint32 regpair;
1580                                         int reg, hreg;
1581
1582                                         regpair = (guint32)(gssize)(list->data);
1583                                         hreg = regpair >> 24;
1584                                         reg = regpair & 0xffffff;
1585
1586                                         assign_reg (cfg, rs, reg, hreg, 1);
1587
1588                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1589
1590                                         list = g_slist_next (list);
1591                                 }
1592                         }
1593                 }
1594
1595                 /*
1596                  * TRACK SREG1
1597                  */
1598                 bank = sreg1_bank (spec);
1599                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1600                         g_assert (is_soft_reg (ins->sreg1, bank));
1601
1602                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1603                         if (dest_sreg1 != -1)
1604                                 g_assert (dest_sreg1 == ins->dreg);
1605                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1606                         g_assert (val >= 0);
1607
1608                         if (rs->vassign [ins->sreg1] >= 0 && rs->vassign [ins->sreg1] != val)
1609                                 // FIXME:
1610                                 g_assert_not_reached ();
1611
1612                         assign_reg (cfg, rs, ins->sreg1, val, bank);
1613
1614                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1615
1616                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1617                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1618                         g_assert (val >= 0);
1619
1620                         if (rs->vassign [ins->sreg1 + 1] >= 0 && rs->vassign [ins->sreg1 + 1] != val)
1621                                 // FIXME:
1622                                 g_assert_not_reached ();
1623
1624                         assign_reg (cfg, rs, ins->sreg1 + 1, val, bank);
1625
1626                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), ins->sreg1 + 1));
1627
1628                         /* Skip rest of this section */
1629                         dest_sreg1 = -1;
1630                 }
1631
1632                 if (sreg1_fixed_mask) {
1633                         g_assert (!bank);
1634                         if (is_global_ireg (ins->sreg1)) {
1635                                 /*
1636                                  * The argument is already in a hard reg, but that reg is
1637                                  * not usable by this instruction, so allocate a new one.
1638                                  */
1639                                 val = mono_regstate_alloc_int (rs, sreg1_fixed_mask);
1640                                 if (val < 0)
1641                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg1_fixed_mask, -1, bank);
1642                                 mono_regstate_free_int (rs, val);
1643                                 dest_sreg1 = val;
1644
1645                                 /* Fall through to the dest_sreg1 != -1 case */
1646                         }
1647                         else
1648                                 sreg1_mask &= sreg1_fixed_mask;
1649                 }
1650
1651                 if (dest_sreg1 != -1) {
1652                         sreg1_mask = regmask (dest_sreg1);
1653
1654                         if ((rs->vassign [ins->sreg1] != dest_sreg1) && !(rs->ifree_mask & (regmask (dest_sreg1)))) {
1655                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg1]));
1656                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sreg1], 0);
1657                                 mono_regstate_free_int (rs, dest_sreg1);
1658                         }
1659                         if (is_global_ireg (ins->sreg1)) {
1660                                 /* The argument is already in a hard reg, need to copy */
1661                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, ins->sreg1, NULL, ip, 0);
1662                                 insert_before_ins (bb, ins, copy);
1663                                 ins->sreg1 = dest_sreg1;
1664                         }
1665                 }
1666
1667                 if (is_soft_reg (ins->sreg1, bank)) {
1668                         val = rs->vassign [ins->sreg1];
1669                         prev_sreg1 = ins->sreg1;
1670                         if (val < 0) {
1671                                 int spill = 0;
1672                                 if (val < -1) {
1673                                         /* the register gets spilled after this inst */
1674                                         spill = -val -1;
1675                                 }
1676
1677                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1678                                         /*
1679                                          * Allocate the same hreg to sreg1 as well so the
1680                                          * peephole can get rid of the move.
1681                                          */
1682                                         sreg1_mask = regmask (ins->dreg);
1683                                 }
1684
1685                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1686                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1687                                         sreg1_mask = regmask (ins->dreg);
1688
1689                                 val = alloc_reg (cfg, bb, tmp, ins, sreg1_mask, ins->sreg1, &reginfo [ins->sreg1], bank);
1690                                 assign_reg (cfg, rs, ins->sreg1, val, bank);
1691                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1692
1693                                 if (spill) {
1694                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg1, tmp, NULL, bank);
1695                                         /*
1696                                          * Need to insert before the instruction since it can
1697                                          * overwrite sreg1.
1698                                          */
1699                                         insert_before_ins (bb, ins, store);
1700                                 }
1701                         }
1702                         else if ((dest_sreg1 != -1) && (dest_sreg1 != val)) {
1703                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, val, NULL, ip, bank);
1704                                 insert_before_ins (bb, ins, copy);
1705                                 sreg2_mask &= ~(regmask (dest_sreg1));
1706                                 val = dest_sreg1;
1707                         }
1708
1709                         ins->sreg1 = val;
1710                 }
1711                 else {
1712                         prev_sreg1 = -1;
1713                 }
1714                 sreg2_mask &= ~(regmask (ins->sreg1));
1715
1716                 /* Handle the case when sreg1 is a regpair but dreg is not */
1717                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1718                         int reg2 = prev_sreg1 + 1;
1719
1720                         g_assert (!bank);
1721                         g_assert (prev_sreg1 > -1);
1722                         g_assert (!is_global_ireg (rs->vassign [prev_sreg1]));
1723                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sreg1]);
1724                         val = rs->vassign [reg2];
1725                         if (val < 0) {
1726                                 int spill = 0;
1727                                 if (val < -1) {
1728                                         /* the register gets spilled after this inst */
1729                                         spill = -val -1;
1730                                 }
1731                                 val = mono_regstate_alloc_int (rs, mask);
1732                                 if (val < 0)
1733                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1734                                 if (spill)
1735                                         g_assert_not_reached ();
1736                         }
1737                         else {
1738                                 if (! (mask & (regmask (val)))) {
1739                                         /* The vreg is already allocated to a wrong hreg */
1740                                         /* FIXME: */
1741                                         g_assert_not_reached ();
1742 #if 0
1743                                         val = mono_regstate_alloc_int (rs, mask);
1744                                         if (val < 0)
1745                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1746
1747                                         /* Reallocate hreg to the correct register */
1748                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1749
1750                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1751 #endif
1752                                 }
1753                         }
1754
1755                         sreg1_high = val;
1756                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1757                         assign_reg (cfg, rs, reg2, val, bank);
1758                 }
1759
1760                 /* Handle dreg==sreg1 */
1761                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != ins->sreg1) {
1762                         MonoInst *sreg2_copy = NULL;
1763                         MonoInst *copy;
1764                         int bank = reg_bank (spec_src1);
1765
1766                         if (ins->dreg == ins->sreg2) {
1767                                 /*
1768                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1769                                  * register for it.
1770                                  */
1771                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->sreg2, NULL, bank);
1772
1773                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (ins->sreg2, bank), mono_regname_full (reg2, bank)));
1774                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, ins->sreg2, NULL, ip, bank);
1775                                 prev_sreg2 = ins->sreg2 = reg2;
1776
1777                                 if (G_UNLIKELY (bank))
1778                                         mono_regstate_free_general (rs, reg2, bank);
1779                                 else
1780                                         mono_regstate_free_int (rs, reg2);
1781                         }
1782
1783                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1784                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1785                                 if (rs->vassign [prev_sreg1 + 1] == ins->sreg2)
1786                                         /* FIXME: */
1787                                         g_assert_not_reached ();
1788
1789                                 /*
1790                                  * sreg1 and dest are already allocated to the same regpair by the
1791                                  * SREG1 allocation code.
1792                                  */
1793                                 g_assert (ins->sreg1 == ins->dreg);
1794                                 g_assert (dreg_high == sreg1_high);
1795                         }
1796
1797                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (ins->sreg1, bank), mono_regname_full (ins->dreg, bank)));
1798                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, ins->sreg1, NULL, ip, bank);
1799                         insert_before_ins (bb, ins, copy);
1800
1801                         if (sreg2_copy)
1802                                 insert_before_ins (bb, copy, sreg2_copy);
1803
1804                         /*
1805                          * Need to prevent sreg2 to be allocated to sreg1, since that
1806                          * would screw up the previous copy.
1807                          */
1808                         sreg2_mask &= ~ (regmask (ins->sreg1));
1809                         /* we set sreg1 to dest as well */
1810                         prev_sreg1 = ins->sreg1 = ins->dreg;
1811                         sreg2_mask &= ~ (regmask (ins->dreg));
1812                 }
1813
1814                 /*
1815                  * TRACK SREG2
1816                  */
1817                 bank = sreg2_bank (spec);
1818                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src2))
1819                         g_assert_not_reached ();
1820                 if (is_soft_reg (ins->sreg2, bank)) {
1821                         val = rs->vassign [ins->sreg2];
1822
1823                         if (val < 0) {
1824                                 int spill = 0;
1825                                 if (val < -1) {
1826                                         /* the register gets spilled after this inst */
1827                                         spill = -val -1;
1828                                 }
1829                                 val = alloc_reg (cfg, bb, tmp, ins, sreg2_mask, ins->sreg2, &reginfo [ins->sreg2], bank);
1830                                 assign_reg (cfg, rs, ins->sreg2, val, bank);
1831                                 DEBUG (printf ("\tassigned sreg2 %s to R%d\n", mono_regname_full (val, bank), ins->sreg2));
1832                                 if (spill) {
1833                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg2, tmp, NULL, bank);
1834                                         /*
1835                                          * Need to insert before the instruction since it can
1836                                          * overwrite sreg2.
1837                                          */
1838                                         insert_before_ins (bb, ins, store);
1839                                 }
1840                         }
1841                         ins->sreg2 = val;
1842                 }
1843                 else {
1844                         prev_sreg2 = -1;
1845                 }
1846
1847                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1848                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1849                         mono_regstate_free_int (rs, ins->sreg1);
1850                 }
1851                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1852                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1853                         mono_regstate_free_int (rs, ins->sreg2);
1854                 }*/
1855
1856                 DEBUG (mono_print_ins_index (i, ins));
1857         }
1858
1859         // FIXME: Set MAX_FREGS to 8
1860         // FIXME: Optimize generated code
1861 #if MONO_ARCH_USE_FPSTACK
1862         /*
1863          * Make a forward pass over the code, simulating the fp stack, making sure the
1864          * arguments required by the fp opcodes are at the top of the stack.
1865          */
1866         if (has_fp) {
1867                 MonoInst *prev = NULL;
1868                 MonoInst *fxch;
1869                 int tmp;
1870
1871                 for (ins = bb->code; ins; ins = ins->next) {
1872                         spec = ins_get_spec (ins->opcode);
1873
1874                         DEBUG (printf ("processing:"));
1875                         DEBUG (mono_print_ins_index (0, ins));
1876
1877                         if (ins->opcode == OP_FMOVE) {
1878                                 /* Do it by renaming the source to the destination on the stack */
1879                                 // FIXME: Is this correct ?
1880                                 for (i = 0; i < sp; ++i)
1881                                         if (fpstack [i] == ins->sreg1)
1882                                                 fpstack [i] = ins->dreg;
1883                                 prev = ins;
1884                                 continue;
1885                         }
1886
1887                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1888                                 /* Arg1 must be in %st(1) */
1889                                 g_assert (prev);
1890
1891                                 i = 0;
1892                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
1893                                         i ++;
1894                                 g_assert (i < sp);
1895
1896                                 if (sp - 1 - i > 0) {
1897                                         /* First move it to %st(0) */
1898                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1899
1900                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1901                                         fxch->inst_imm = sp - 1 - i;
1902
1903                                         prev->next = fxch;
1904                                         fxch->next = ins;
1905                                         prev = fxch;
1906
1907                                         tmp = fpstack [sp - 1];
1908                                         fpstack [sp - 1] = fpstack [i];
1909                                         fpstack [i] = tmp;
1910                                 }
1911
1912                                 /* Then move it to %st(1) */
1913                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1914
1915                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1916                                 fxch->inst_imm = 1;
1917
1918                                 prev->next = fxch;
1919                                 fxch->next = ins;
1920                                 prev = fxch;
1921
1922                                 tmp = fpstack [sp - 1];
1923                                 fpstack [sp - 1] = fpstack [sp - 2];
1924                                 fpstack [sp - 2] = tmp;
1925                         }
1926
1927                         if (sreg2_is_fp (spec)) {
1928                                 g_assert (sp > 0);
1929
1930                                 if (fpstack [sp - 1] != ins->sreg2) {
1931                                         g_assert (prev);
1932
1933                                         i = 0;
1934                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
1935                                                 i ++;
1936                                         g_assert (i < sp);
1937
1938                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1939
1940                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1941                                         fxch->inst_imm = sp - 1 - i;
1942
1943                                         prev->next = fxch;
1944                                         fxch->next = ins;
1945                                         prev = fxch;
1946
1947                                         tmp = fpstack [sp - 1];
1948                                         fpstack [sp - 1] = fpstack [i];
1949                                         fpstack [i] = tmp;
1950                                 }
1951
1952                                 sp --;
1953                         }
1954
1955                         if (sreg1_is_fp (spec)) {
1956                                 g_assert (sp > 0);
1957
1958                                 if (fpstack [sp - 1] != ins->sreg1) {
1959                                         g_assert (prev);
1960
1961                                         i = 0;
1962                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
1963                                                 i ++;
1964                                         g_assert (i < sp);
1965
1966                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1967
1968                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1969                                         fxch->inst_imm = sp - 1 - i;
1970
1971                                         prev->next = fxch;
1972                                         fxch->next = ins;
1973                                         prev = fxch;
1974
1975                                         tmp = fpstack [sp - 1];
1976                                         fpstack [sp - 1] = fpstack [i];
1977                                         fpstack [i] = tmp;
1978                                 }
1979
1980                                 sp --;
1981                         }
1982
1983                         if (dreg_is_fp (spec)) {
1984                                 g_assert (sp < 8);
1985                                 fpstack [sp ++] = ins->dreg;
1986                         }
1987
1988                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
1989                                 printf ("\t[");
1990                                 for (i = 0; i < sp; ++i)
1991                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
1992                                 printf ("]\n");
1993                         }
1994
1995                         prev = ins;
1996                 }
1997
1998                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
1999                         /* Remove remaining items from the fp stack */
2000                         /*
2001                          * These can remain for example as a result of a dead fmove like in
2002                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2003                          */
2004                         while (sp) {
2005                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2006                                 mono_add_ins_to_end (bb, ins);
2007                                 sp --;
2008                         }
2009                 }
2010         }
2011 #endif
2012 }
2013
2014 CompRelation
2015 mono_opcode_to_cond (int opcode)
2016 {
2017         switch (opcode) {
2018         case CEE_BEQ:
2019         case OP_CEQ:
2020         case OP_IBEQ:
2021         case OP_ICEQ:
2022         case OP_LBEQ:
2023         case OP_LCEQ:
2024         case OP_FBEQ:
2025         case OP_FCEQ:
2026         case OP_COND_EXC_EQ:
2027         case OP_COND_EXC_IEQ:
2028         case OP_CMOV_IEQ:
2029         case OP_CMOV_LEQ:
2030                 return CMP_EQ;
2031         case CEE_BNE_UN:
2032         case OP_IBNE_UN:
2033         case OP_LBNE_UN:
2034         case OP_FBNE_UN:
2035         case OP_COND_EXC_NE_UN:
2036         case OP_COND_EXC_INE_UN:
2037         case OP_CMOV_INE_UN:
2038         case OP_CMOV_LNE_UN:
2039                 return CMP_NE;
2040         case CEE_BLE:
2041         case OP_IBLE:
2042         case OP_LBLE:
2043         case OP_FBLE:
2044         case OP_CMOV_ILE:
2045         case OP_CMOV_LLE:
2046                 return CMP_LE;
2047         case CEE_BGE:
2048         case OP_IBGE:
2049         case OP_LBGE:
2050         case OP_FBGE:
2051         case OP_CMOV_IGE:
2052         case OP_CMOV_LGE:
2053                 return CMP_GE;
2054         case CEE_BLT:
2055         case OP_CLT:
2056         case OP_IBLT:
2057         case OP_ICLT:
2058         case OP_LBLT:
2059         case OP_LCLT:
2060         case OP_FBLT:
2061         case OP_FCLT:
2062         case OP_COND_EXC_LT:
2063         case OP_COND_EXC_ILT:
2064         case OP_CMOV_ILT:
2065         case OP_CMOV_LLT:
2066                 return CMP_LT;
2067         case CEE_BGT:
2068         case OP_CGT:
2069         case OP_IBGT:
2070         case OP_ICGT:
2071         case OP_LBGT:
2072         case OP_LCGT:
2073         case OP_FBGT:
2074         case OP_FCGT:
2075         case OP_COND_EXC_GT:
2076         case OP_COND_EXC_IGT:
2077         case OP_CMOV_IGT:
2078         case OP_CMOV_LGT:
2079                 return CMP_GT;
2080
2081         case CEE_BLE_UN:
2082         case OP_IBLE_UN:
2083         case OP_LBLE_UN:
2084         case OP_FBLE_UN:
2085         case OP_COND_EXC_LE_UN:
2086         case OP_COND_EXC_ILE_UN:
2087         case OP_CMOV_ILE_UN:
2088         case OP_CMOV_LLE_UN:
2089                 return CMP_LE_UN;
2090         case CEE_BGE_UN:
2091         case OP_IBGE_UN:
2092         case OP_LBGE_UN:
2093         case OP_FBGE_UN:
2094         case OP_CMOV_IGE_UN:
2095         case OP_CMOV_LGE_UN:
2096                 return CMP_GE_UN;
2097         case CEE_BLT_UN:
2098         case OP_CLT_UN:
2099         case OP_IBLT_UN:
2100         case OP_ICLT_UN:
2101         case OP_LBLT_UN:
2102         case OP_LCLT_UN:
2103         case OP_FBLT_UN:
2104         case OP_FCLT_UN:
2105         case OP_COND_EXC_LT_UN:
2106         case OP_COND_EXC_ILT_UN:
2107         case OP_CMOV_ILT_UN:
2108         case OP_CMOV_LLT_UN:
2109                 return CMP_LT_UN;
2110         case CEE_BGT_UN:
2111         case OP_CGT_UN:
2112         case OP_IBGT_UN:
2113         case OP_ICGT_UN:
2114         case OP_LBGT_UN:
2115         case OP_LCGT_UN:
2116         case OP_FCGT_UN:
2117         case OP_FBGT_UN:
2118         case OP_COND_EXC_GT_UN:
2119         case OP_COND_EXC_IGT_UN:
2120         case OP_CMOV_IGT_UN:
2121         case OP_CMOV_LGT_UN:
2122                 return CMP_GT_UN;
2123         default:
2124                 printf ("%s\n", mono_inst_name (opcode));
2125                 g_assert_not_reached ();
2126                 return 0;
2127         }
2128 }
2129
2130 CompRelation
2131 mono_negate_cond (CompRelation cond)
2132 {
2133         switch (cond) {
2134         case CMP_EQ:
2135                 return CMP_NE;
2136         case CMP_NE:
2137                 return CMP_EQ;
2138         case CMP_LE:
2139                 return CMP_GT;
2140         case CMP_GE:
2141                 return CMP_LT;
2142         case CMP_LT:
2143                 return CMP_GE;
2144         case CMP_GT:
2145                 return CMP_LE;
2146         case CMP_LE_UN:
2147                 return CMP_GT_UN;
2148         case CMP_GE_UN:
2149                 return CMP_LT_UN;
2150         case CMP_LT_UN:
2151                 return CMP_GE_UN;
2152         case CMP_GT_UN:
2153                 return CMP_LE_UN;
2154         default:
2155                 g_assert_not_reached ();
2156         }
2157 }
2158
2159 CompType
2160 mono_opcode_to_type (int opcode, int cmp_opcode)
2161 {
2162         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2163                 return CMP_TYPE_L;
2164         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2165                 return CMP_TYPE_L;
2166         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2167                 return CMP_TYPE_I;
2168         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2169                 return CMP_TYPE_I;
2170         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2171                 return CMP_TYPE_L;
2172         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2173                 return CMP_TYPE_L;
2174         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2175                 return CMP_TYPE_F;
2176         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2177                 return CMP_TYPE_F;
2178         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2179                 return CMP_TYPE_I;
2180         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2181                 switch (cmp_opcode) {
2182                 case OP_ICOMPARE:
2183                 case OP_ICOMPARE_IMM:
2184                 case OP_LCOMPARE_IMM:
2185                         return CMP_TYPE_I;
2186                 default:
2187                         return CMP_TYPE_L;
2188                 }
2189         } else {
2190                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2191                 return 0;
2192         }
2193 }
2194
2195 gboolean
2196 mono_is_regsize_var (MonoType *t)
2197 {
2198         if (t->byref)
2199                 return TRUE;
2200         t = mono_type_get_underlying_type (t);
2201         switch (t->type) {
2202         case MONO_TYPE_BOOLEAN:
2203         case MONO_TYPE_CHAR:
2204         case MONO_TYPE_I1:
2205         case MONO_TYPE_U1:
2206         case MONO_TYPE_I2:
2207         case MONO_TYPE_U2:
2208         case MONO_TYPE_I4:
2209         case MONO_TYPE_U4:
2210         case MONO_TYPE_I:
2211         case MONO_TYPE_U:
2212         case MONO_TYPE_PTR:
2213         case MONO_TYPE_FNPTR:
2214 #if SIZEOF_VOID_P == 8
2215         case MONO_TYPE_I8:
2216         case MONO_TYPE_U8:
2217 #endif
2218                 return TRUE;
2219         case MONO_TYPE_OBJECT:
2220         case MONO_TYPE_STRING:
2221         case MONO_TYPE_CLASS:
2222         case MONO_TYPE_SZARRAY:
2223         case MONO_TYPE_ARRAY:
2224                 return TRUE;
2225         case MONO_TYPE_GENERICINST:
2226                 if (!mono_type_generic_inst_is_valuetype (t))
2227                         return TRUE;
2228                 return FALSE;
2229         case MONO_TYPE_VALUETYPE:
2230                 return FALSE;
2231         }
2232         return FALSE;
2233 }
2234
2235 /*
2236  * mono_peephole_ins:
2237  *
2238  *   Perform some architecture independent peephole optimizations.
2239  */
2240 void
2241 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2242 {
2243         MonoInst *last_ins = ins->prev;
2244
2245         switch (ins->opcode) {
2246         case OP_MUL_IMM:
2247                 /* remove unnecessary multiplication with 1 */
2248                 if (ins->inst_imm == 1) {
2249                         if (ins->dreg != ins->sreg1)
2250                                 ins->opcode = OP_MOVE;
2251                         else
2252                                 MONO_DELETE_INS (bb, ins);
2253                 }
2254                 break;
2255         case OP_LOAD_MEMBASE:
2256         case OP_LOADI4_MEMBASE:
2257                 /*
2258                  * Note: if reg1 = reg2 the load op is removed
2259                  *
2260                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2261                  * OP_LOAD_MEMBASE offset(basereg), reg2
2262                  * -->
2263                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2264                  * OP_MOVE reg1, reg2
2265                  */
2266                 if (last_ins &&
2267                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2268                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2269                         ins->inst_basereg == last_ins->inst_destbasereg &&
2270                         ins->inst_offset == last_ins->inst_offset) {
2271                         if (ins->dreg == last_ins->sreg1) {
2272                                 MONO_DELETE_INS (bb, ins);
2273                                 break;
2274                         } else {
2275                                 ins->opcode = OP_MOVE;
2276                                 ins->sreg1 = last_ins->sreg1;
2277                         }
2278
2279                         /*
2280                          * Note: reg1 must be different from the basereg in the second load
2281                          * Note: if reg1 = reg2 is equal then second load is removed
2282                          *
2283                          * OP_LOAD_MEMBASE offset(basereg), reg1
2284                          * OP_LOAD_MEMBASE offset(basereg), reg2
2285                          * -->
2286                          * OP_LOAD_MEMBASE offset(basereg), reg1
2287                          * OP_MOVE reg1, reg2
2288                          */
2289                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2290                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2291                           ins->inst_basereg != last_ins->dreg &&
2292                           ins->inst_basereg == last_ins->inst_basereg &&
2293                           ins->inst_offset == last_ins->inst_offset) {
2294
2295                         if (ins->dreg == last_ins->dreg) {
2296                                 MONO_DELETE_INS (bb, ins);
2297                         } else {
2298                                 ins->opcode = OP_MOVE;
2299                                 ins->sreg1 = last_ins->dreg;
2300                         }
2301
2302                         //g_assert_not_reached ();
2303
2304 #if 0
2305                         /*
2306                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2307                          * OP_LOAD_MEMBASE offset(basereg), reg
2308                          * -->
2309                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2310                          * OP_ICONST reg, imm
2311                          */
2312                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2313                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2314                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2315                                    ins->inst_offset == last_ins->inst_offset) {
2316                         ins->opcode = OP_ICONST;
2317                         ins->inst_c0 = last_ins->inst_imm;
2318                         g_assert_not_reached (); // check this rule
2319 #endif
2320                 }
2321                 break;
2322         case OP_LOADI1_MEMBASE:
2323         case OP_LOADU1_MEMBASE:
2324                 /*
2325                  * Note: if reg1 = reg2 the load op is removed
2326                  *
2327                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2328                  * OP_LOAD_MEMBASE offset(basereg), reg2
2329                  * -->
2330                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2331                  * OP_MOVE reg1, reg2
2332                  */
2333                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2334                         ins->inst_basereg == last_ins->inst_destbasereg &&
2335                         ins->inst_offset == last_ins->inst_offset) {
2336                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2337                         ins->sreg1 = last_ins->sreg1;
2338                 }
2339                 break;
2340         case OP_LOADI2_MEMBASE:
2341         case OP_LOADU2_MEMBASE:
2342                 /*
2343                  * Note: if reg1 = reg2 the load op is removed
2344                  *
2345                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2346                  * OP_LOAD_MEMBASE offset(basereg), reg2
2347                  * -->
2348                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2349                  * OP_MOVE reg1, reg2
2350                  */
2351                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2352                         ins->inst_basereg == last_ins->inst_destbasereg &&
2353                         ins->inst_offset == last_ins->inst_offset) {
2354 #if SIZEOF_VOID_P == 8
2355                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2356 #else
2357                         /* The definition of OP_PCONV_TO_U2 is wrong */
2358                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2359 #endif
2360                         ins->sreg1 = last_ins->sreg1;
2361                 }
2362                 break;
2363         case OP_MOVE:
2364         case OP_FMOVE:
2365                 /*
2366                  * Removes:
2367                  *
2368                  * OP_MOVE reg, reg
2369                  */
2370                 if (ins->dreg == ins->sreg1) {
2371                         MONO_DELETE_INS (bb, ins);
2372                         break;
2373                 }
2374                 /*
2375                  * Removes:
2376                  *
2377                  * OP_MOVE sreg, dreg
2378                  * OP_MOVE dreg, sreg
2379                  */
2380                 if (last_ins && last_ins->opcode == OP_MOVE &&
2381                         ins->sreg1 == last_ins->dreg &&
2382                         ins->dreg == last_ins->sreg1) {
2383                         MONO_DELETE_INS (bb, ins);
2384                 }
2385                 break;
2386         case OP_NOP:
2387                 MONO_DELETE_INS (bb, ins);
2388                 break;
2389         }
2390 }
2391