mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413 void
 414 mono_print_ins_index (int i, MonoInst *ins)
 415 {
 416         const char *spec = ins_get_spec (ins->opcode);
 417         int num_sregs, j;
 418         int sregs [MONO_MAX_SRC_REGS];
 419
 420         if (i != -1)
 421                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 422         else
 423                 printf (" %s", mono_inst_name (ins->opcode));
 424         if (spec == MONO_ARCH_CPU_SPEC) {
 425                 /* This is a lowered opcode */
 426                 if (ins->dreg != -1)
 427                         printf (" R%d <-", ins->dreg);
 428                 if (ins->sreg1 != -1)
 429                         printf (" R%d", ins->sreg1);
 430                 if (ins->sreg2 != -1)
 431                         printf (" R%d", ins->sreg2);
 432                 if (ins->sreg3 != -1)
 433                         printf (" R%d", ins->sreg3);
 434
 435                 switch (ins->opcode) {
 436                 case OP_LBNE_UN:
 437                 case OP_LBEQ:
 438                 case OP_LBLT:
 439                 case OP_LBLT_UN:
 440                 case OP_LBGT:
 441                 case OP_LBGT_UN:
 442                 case OP_LBGE:
 443                 case OP_LBGE_UN:
 444                 case OP_LBLE:
 445                 case OP_LBLE_UN:
 446                         if (!ins->inst_false_bb)
 447                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 448                         else
 449                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 450                         break;
 451                 case OP_PHI:
 452                 case OP_VPHI:
 453                 case OP_XPHI:
 454                 case OP_FPHI: {
 455                         int i;
 456                         printf (" [%d (", (int)ins->inst_c0);
 457                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 458                                 if (i)
 459                                         printf (", ");
 460                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 461                         }
 462                         printf (")]");
 463                         break;
 464                 }
 465                 case OP_LDADDR:
 466                 case OP_OUTARG_VTRETADDR:
 467                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 468                         break;
 469                 case OP_REGOFFSET:
 470                         printf (" + 0x%lx", (long)ins->inst_offset);
 471                         break;
 472                 default:
 473                         break;
 474                 }
 475
 476                 printf ("\n");
 477                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 478                 return;
 479         }
 480
 481         if (spec [MONO_INST_DEST]) {
 482                 int bank = dreg_bank (spec);
 483                 if (is_soft_reg (ins->dreg, bank)) {
 484                         if (spec [MONO_INST_DEST] == 'b') {
 485                                 if (ins->inst_offset == 0)
 486                                         printf (" [R%d] <-", ins->dreg);
 487                                 else
 488                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 489                         }
 490                         else
 491                                 printf (" R%d <-", ins->dreg);
 492                 } else if (spec [MONO_INST_DEST] == 'b') {
 493                         if (ins->inst_offset == 0)
 494                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 495                         else
 496                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 497                 } else
 498                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 499         }
 500         if (spec [MONO_INST_SRC1]) {
 501                 int bank = sreg1_bank (spec);
 502                 if (is_soft_reg (ins->sreg1, bank)) {
 503                         if (spec [MONO_INST_SRC1] == 'b')
 504                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 505                         else
 506                                 printf (" R%d", ins->sreg1);
 507                 } else if (spec [MONO_INST_SRC1] == 'b')
 508                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 509                 else
 510                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 511         }
 512         num_sregs = mono_inst_get_src_registers (ins, sregs);
 513         for (j = 1; j < num_sregs; ++j) {
 514                 int bank = sreg_bank (j, spec);
 515                 if (is_soft_reg (sregs [j], bank))
 516                         printf (" R%d", sregs [j]);
 517                 else
 518                         printf (" %s", mono_regname_full (sregs [j], bank));
 519         }
 520
 521         switch (ins->opcode) {
 522         case OP_ICONST:
 523                 printf (" [%d]", (int)ins->inst_c0);
 524                 break;
 525 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 526         case OP_X86_PUSH_IMM:
 527 #endif
 528         case OP_ICOMPARE_IMM:
 529         case OP_COMPARE_IMM:
 530         case OP_IADD_IMM:
 531         case OP_ISUB_IMM:
 532         case OP_IAND_IMM:
 533         case OP_IOR_IMM:
 534         case OP_IXOR_IMM:
 535                 printf (" [%d]", (int)ins->inst_imm);
 536                 break;
 537         case OP_ADD_IMM:
 538         case OP_LADD_IMM:
 539                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 540                 break;
 541         case OP_I8CONST:
 542                 printf (" [%lld]", (long long)ins->inst_l);
 543                 break;
 544         case OP_R8CONST:
 545                 printf (" [%f]", *(double*)ins->inst_p0);
 546                 break;
 547         case OP_R4CONST:
 548                 printf (" [%f]", *(float*)ins->inst_p0);
 549                 break;
 550         case OP_CALL:
 551         case OP_CALL_MEMBASE:
 552         case OP_CALL_REG:
 553         case OP_FCALL:
 554         case OP_FCALLVIRT:
 555         case OP_LCALL:
 556         case OP_LCALLVIRT:
 557         case OP_VCALL:
 558         case OP_VCALLVIRT:
 559         case OP_VCALL_REG:
 560         case OP_VCALL_MEMBASE:
 561         case OP_VCALL2:
 562         case OP_VCALL2_REG:
 563         case OP_VCALL2_MEMBASE:
 564         case OP_VOIDCALL:
 565         case OP_VOIDCALL_MEMBASE:
 566         case OP_VOIDCALLVIRT:
 567         case OP_TAILCALL: {
 568                 MonoCallInst *call = (MonoCallInst*)ins;
 569                 GSList *list;
 570
 571                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 572                         /*
 573                          * These are lowered opcodes, but they are in the .md files since the old
 574                          * JIT passes them to backends.
 575                          */
 576                         if (ins->dreg != -1)
 577                                 printf (" R%d <-", ins->dreg);
 578                 }
 579
 580                 if (call->method) {
 581                         char *full_name = mono_method_full_name (call->method, TRUE);
 582                         printf (" [%s]", full_name);
 583                         g_free (full_name);
 584                 } else if (call->fptr) {
 585                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 586                         if (info)
 587                                 printf (" [%s]", info->name);
 588                 }
 589
 590                 list = call->out_ireg_args;
 591                 while (list) {
 592                         guint32 regpair;
 593                         int reg, hreg;
 594
 595                         regpair = (guint32)(gssize)(list->data);
 596                         hreg = regpair >> 24;
 597                         reg = regpair & 0xffffff;
 598
 599                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 600
 601                         list = g_slist_next (list);
 602                 }
 603                 break;
 604         }
 605         case OP_BR:
 606         case OP_CALL_HANDLER:
 607                 printf (" [B%d]", ins->inst_target_bb->block_num);
 608                 break;
 609         case OP_IBNE_UN:
 610         case OP_IBEQ:
 611         case OP_IBLT:
 612         case OP_IBLT_UN:
 613         case OP_IBGT:
 614         case OP_IBGT_UN:
 615         case OP_IBGE:
 616         case OP_IBGE_UN:
 617         case OP_IBLE:
 618         case OP_IBLE_UN:
 619         case OP_LBNE_UN:
 620         case OP_LBEQ:
 621         case OP_LBLT:
 622         case OP_LBLT_UN:
 623         case OP_LBGT:
 624         case OP_LBGT_UN:
 625         case OP_LBGE:
 626         case OP_LBGE_UN:
 627         case OP_LBLE:
 628         case OP_LBLE_UN:
 629                 if (!ins->inst_false_bb)
 630                         printf (" [B%d]", ins->inst_true_bb->block_num);
 631                 else
 632                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 633                 break;
 634         case OP_LIVERANGE_START:
 635         case OP_LIVERANGE_END:
 636         case OP_GC_LIVENESS_DEF:
 637         case OP_GC_LIVENESS_USE:
 638                 printf (" R%d", (int)ins->inst_c1);
 639                 break;
 640         default:
 641                 break;
 642         }
 643
 644         if (spec [MONO_INST_CLOB])
 645                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 646         printf ("\n");
 647 }
 648
 649 static void
 650 print_regtrack (RegTrack *t, int num)
 651 {
 652         int i;
 653         char buf [32];
 654         const char *r;
 655
 656         for (i = 0; i < num; ++i) {
 657                 if (!t [i].born_in)
 658                         continue;
 659                 if (i >= MONO_MAX_IREGS) {
 660                         g_snprintf (buf, sizeof(buf), "R%d", i);
 661                         r = buf;
 662                 } else
 663                         r = mono_arch_regname (i);
 664                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 665         }
 666 }
 667 #else
 668 void
 669 mono_print_ins_index (int i, MonoInst *ins)
 670 {
 671 }
 672 #endif /* DISABLE_LOGGING */
 673
 674 void
 675 mono_print_ins (MonoInst *ins)
 676 {
 677         mono_print_ins_index (-1, ins);
 678 }
 679
 680 static inline void
 681 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 682 {
 683         /*
 684          * If this function is called multiple times, the new instructions are inserted
 685          * in the proper order.
 686          */
 687         mono_bblock_insert_before_ins (bb, ins, to_insert);
 688 }
 689
 690 static inline void
 691 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 692 {
 693         /*
 694          * If this function is called multiple times, the new instructions are inserted in
 695          * proper order.
 696          */
 697         mono_bblock_insert_after_ins (bb, *last, to_insert);
 698
 699         *last = to_insert;
 700 }
 701
 702 static inline int
 703 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 704 {
 705         if (vreg_is_ref (cfg, reg))
 706                 return MONO_REG_INT_REF;
 707         else if (vreg_is_mp (cfg, reg))
 708                 return MONO_REG_INT_MP;
 709         else
 710                 return bank;
 711 }
 712
 713 /*
 714  * Force the spilling of the variable in the symbolic register 'reg', and free
 715  * the hreg it was assigned to.
 716  */
 717 static void
 718 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 719 {
 720         MonoInst *load;
 721         int i, sel, spill;
 722         int *symbolic;
 723         MonoRegState *rs = cfg->rs;
 724
 725         symbolic = rs->symbolic [bank];
 726         sel = rs->vassign [reg];
 727
 728         /* the vreg we need to spill lives in another logical reg bank */
 729         bank = translate_bank (cfg->rs, bank, sel);
 730
 731         /*i = rs->isymbolic [sel];
 732         g_assert (i == reg);*/
 733         i = reg;
 734         spill = ++cfg->spill_count;
 735         rs->vassign [i] = -spill - 1;
 736         if (G_UNLIKELY (bank))
 737                 mono_regstate_free_general (rs, sel, bank);
 738         else
 739                 mono_regstate_free_int (rs, sel);
 740         /* we need to create a spill var and insert a load to sel after the current instruction */
 741         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 742         load->dreg = sel;
 743         load->inst_basereg = cfg->frame_reg;
 744         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 745         insert_after_ins (bb, ins, last, load);
 746         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 747         if (G_UNLIKELY (bank))
 748                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 749         else
 750                 i = mono_regstate_alloc_int (rs, regmask (sel));
 751         g_assert (i == sel);
 752
 753         if (G_UNLIKELY (bank))
 754                 mono_regstate_free_general (rs, sel, bank);
 755         else
 756                 mono_regstate_free_int (rs, sel);
 757 }
 758
 759 /* This isn't defined on older glib versions and on some platforms */
 760 #ifndef G_GUINT64_FORMAT
 761 #define G_GUINT64_FORMAT "ul"
 762 #endif
 763
 764 static int
 765 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 766 {
 767         MonoInst *load;
 768         int i, sel, spill, num_sregs;
 769         int sregs [MONO_MAX_SRC_REGS];
 770         int *symbolic;
 771         MonoRegState *rs = cfg->rs;
 772
 773         symbolic = rs->symbolic [bank];
 774
 775         g_assert (bank < MONO_NUM_REGBANKS);
 776
 777         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 778         /* exclude the registers in the current instruction */
 779         num_sregs = mono_inst_get_src_registers (ins, sregs);
 780         for (i = 0; i < num_sregs; ++i) {
 781                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 782                         if (is_soft_reg (sregs [i], bank))
 783                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 784                         else
 785                                 regmask &= ~ (regmask (sregs [i]));
 786                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 787                 }
 788         }
 789         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 790                 regmask &= ~ (regmask (ins->dreg));
 791                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 792         }
 793
 794         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 795         g_assert (regmask); /* need at least a register we can free */
 796         sel = 0;
 797         /* we should track prev_use and spill the register that's farther */
 798         if (G_UNLIKELY (bank)) {
 799                 for (i = 0; i < regbank_size [bank]; ++i) {
 800                         if (regmask & (regmask (i))) {
 801                                 sel = i;
 802
 803                                 /* the vreg we need to load lives in another logical bank */
 804                                 bank = translate_bank (cfg->rs, bank, sel);
 805
 806                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 807                                 break;
 808                         }
 809                 }
 810
 811                 i = rs->symbolic [bank] [sel];
 812                 spill = ++cfg->spill_count;
 813                 rs->vassign [i] = -spill - 1;
 814                 mono_regstate_free_general (rs, sel, bank);
 815         }
 816         else {
 817                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 818                         if (regmask & (regmask (i))) {
 819                                 sel = i;
 820                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 821                                 break;
 822                         }
 823                 }
 824
 825                 i = rs->isymbolic [sel];
 826                 spill = ++cfg->spill_count;
 827                 rs->vassign [i] = -spill - 1;
 828                 mono_regstate_free_int (rs, sel);
 829         }
 830
 831         /* we need to create a spill var and insert a load to sel after the current instruction */
 832         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 833         load->dreg = sel;
 834         load->inst_basereg = cfg->frame_reg;
 835         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 836         insert_after_ins (bb, ins, last, load);
 837         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 838         if (G_UNLIKELY (bank))
 839                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 840         else
 841                 i = mono_regstate_alloc_int (rs, regmask (sel));
 842         g_assert (i == sel);
 843
 844         return sel;
 845 }
 846
 847 /*
 848  * free_up_hreg:
 849  *
 850  *   Free up the hreg HREG by spilling the vreg allocated to it.
 851  */
 852 static void
 853 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 854 {
 855         if (G_UNLIKELY (bank)) {
 856                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 857                         bank = translate_bank (cfg->rs, bank, hreg);
 858                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 859                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 860                 }
 861         }
 862         else {
 863                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 864                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 865                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 866                 }
 867         }
 868 }
 869
 870 static MonoInst*
 871 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 872 {
 873         MonoInst *copy;
 874
 875         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 876
 877         copy->dreg = dest;
 878         copy->sreg1 = src;
 879         copy->cil_code = ip;
 880         if (ins) {
 881                 mono_bblock_insert_after_ins (bb, ins, copy);
 882                 *last = copy;
 883         }
 884         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 885         return copy;
 886 }
 887
 888 static inline const char*
 889 regbank_to_string (int bank)
 890 {
 891         if (bank == MONO_REG_INT_REF)
 892                 return "REF ";
 893         else if (bank == MONO_REG_INT_MP)
 894                 return "MP ";
 895         else
 896                 return "";
 897 }
 898
 899 static void
 900 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 901 {
 902         MonoInst *store, *def;
 903
 904         bank = get_vreg_bank (cfg, prev_reg, bank);
 905
 906         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 907         store->sreg1 = reg;
 908         store->inst_destbasereg = cfg->frame_reg;
 909         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 910         if (ins) {
 911                 mono_bblock_insert_after_ins (bb, ins, store);
 912                 *last = store;
 913         } else if (insert_before) {
 914                 insert_before_ins (bb, insert_before, store);
 915         } else {
 916                 g_assert_not_reached ();
 917         }
 918         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 919
 920         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 921                 g_assert (prev_reg != -1);
 922                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 923                 def->inst_c0 = spill;
 924                 def->inst_c1 = bank;
 925                 mono_bblock_insert_after_ins (bb, store, def);
 926         }
 927 }
 928
 929 /* flags used in reginfo->flags */
 930 enum {
 931         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 932         MONO_FP_NEEDS_SPILL                     = regmask (1),
 933         MONO_FP_NEEDS_LOAD                      = regmask (2)
 934 };
 935
 936 static inline int
 937 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 938 {
 939         int val;
 940
 941         if (info && info->preferred_mask) {
 942                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 943                 if (val >= 0) {
 944                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 945                         return val;
 946                 }
 947         }
 948
 949         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 950         if (val < 0)
 951                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 952
 953         return val;
 954 }
 955
 956 static inline int
 957 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 958 {
 959         int val;
 960
 961         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 962
 963         if (val < 0)
 964                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 965
 966         return val;
 967 }
 968
 969 static inline int
 970 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 971 {
 972         if (G_UNLIKELY (bank))
 973                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 974         else
 975                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 976 }
 977
 978 static inline void
 979 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 980 {
 981         if (G_UNLIKELY (bank)) {
 982                 int mirrored_bank;
 983
 984                 g_assert (reg >= regbank_size [bank]);
 985                 g_assert (hreg < regbank_size [bank]);
 986                 g_assert (! is_global_freg (hreg));
 987
 988                 rs->vassign [reg] = hreg;
 989                 rs->symbolic [bank] [hreg] = reg;
 990                 rs->free_mask [bank] &= ~ (regmask (hreg));
 991
 992                 mirrored_bank = get_mirrored_bank (bank);
 993                 if (mirrored_bank == -1)
 994                         return;
 995
 996                 /* Make sure the other logical reg bank that this bank shares
 997                  * a single hard reg bank knows that this hard reg is not free.
 998                  */
 999                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1000
1001                 /* Mark the other logical bank that the this bank shares
1002                  * a single hard reg bank with as mirrored.
1003                  */
1004                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1005
1006         }
1007         else {
1008                 g_assert (reg >= MONO_MAX_IREGS);
1009                 g_assert (hreg < MONO_MAX_IREGS);
1010 #ifndef TARGET_ARM
1011                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1012                 g_assert (! is_global_ireg (hreg));
1013 #endif
1014
1015                 rs->vassign [reg] = hreg;
1016                 rs->isymbolic [hreg] = reg;
1017                 rs->ifree_mask &= ~ (regmask (hreg));
1018         }
1019 }
1020
1021 static inline regmask_t
1022 get_callee_mask (const char spec)
1023 {
1024         if (G_UNLIKELY (reg_bank (spec)))
1025                 return regbank_callee_regs [reg_bank (spec)];
1026         return MONO_ARCH_CALLEE_REGS;
1027 }
1028
1029 static gint8 desc_to_fixed_reg [256];
1030 static gboolean desc_to_fixed_reg_inited = FALSE;
1031
1032 #ifndef DISABLE_JIT
1033
1034 /*
1035  * Local register allocation.
1036  * We first scan the list of instructions and we save the liveness info of
1037  * each register (when the register is first used, when it's value is set etc.).
1038  * We also reverse the list of instructions because assigning registers backwards allows
1039  * for more tricks to be used.
1040  */
1041 void
1042 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1043 {
1044         MonoInst *ins, *prev, *last;
1045         MonoInst **tmp;
1046         MonoRegState *rs = cfg->rs;
1047         int i, j, val, max;
1048         RegTrack *reginfo;
1049         const char *spec;
1050         unsigned char spec_src1, spec_dest;
1051         int bank = 0;
1052 #if MONO_ARCH_USE_FPSTACK
1053         gboolean has_fp = FALSE;
1054         int fpstack [8];
1055         int sp = 0;
1056 #endif
1057         int num_sregs = 0;
1058         int sregs [MONO_MAX_SRC_REGS];
1059
1060         if (!bb->code)
1061                 return;
1062
1063         if (!desc_to_fixed_reg_inited) {
1064                 for (i = 0; i < 256; ++i)
1065                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1066                 desc_to_fixed_reg_inited = TRUE;
1067
1068                 /* Validate the cpu description against the info in mini-ops.h */
1069 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1070                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1071                         const char *ispec;
1072
1073                         spec = ins_get_spec (i);
1074                         ispec = INS_INFO (i);
1075
1076                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1077                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1078                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1079                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1080                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1081                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1082                 }
1083 #endif
1084         }
1085
1086         rs->next_vreg = bb->max_vreg;
1087         mono_regstate_assign (rs);
1088
1089         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1090         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1091                 rs->free_mask [i] = regbank_callee_regs [i];
1092
1093         max = rs->next_vreg;
1094
1095         if (cfg->reginfo && cfg->reginfo_len < max)
1096                 cfg->reginfo = NULL;
1097
1098         reginfo = cfg->reginfo;
1099         if (!reginfo) {
1100                 cfg->reginfo_len = MAX (1024, max * 2);
1101                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1102         }
1103         else
1104                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1105
1106         if (cfg->verbose_level > 1) {
1107                 /* print_regtrack reads the info of all variables */
1108                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1109         }
1110
1111         /*
1112          * For large methods, next_vreg can be very large, so g_malloc0 time can
1113          * be prohibitive. So we manually init the reginfo entries used by the
1114          * bblock.
1115          */
1116         for (ins = bb->code; ins; ins = ins->next) {
1117                 spec = ins_get_spec (ins->opcode);
1118
1119                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1120                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1121 #if SIZEOF_REGISTER == 4
1122                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1123                                 /**
1124                                  * In the new IR, the two vregs of the regpair do not alias the
1125                                  * original long vreg. shift the vreg here so the rest of the
1126                                  * allocator doesn't have to care about it.
1127                                  */
1128                                 ins->dreg ++;
1129                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1130                         }
1131 #endif
1132                 }
1133
1134                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1135                 for (j = 0; j < num_sregs; ++j) {
1136                         g_assert (sregs [j] != -1);
1137                         if (sregs [j] < max) {
1138                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1139 #if SIZEOF_REGISTER == 4
1140                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1141                                         sregs [j]++;
1142                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1143                                 }
1144 #endif
1145                         }
1146                 }
1147                 mono_inst_set_src_registers (ins, sregs);
1148         }
1149
1150         /*if (cfg->opt & MONO_OPT_COPYPROP)
1151                 local_copy_prop (cfg, ins);*/
1152
1153         i = 1;
1154         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1155         /* forward pass on the instructions to collect register liveness info */
1156         MONO_BB_FOR_EACH_INS (bb, ins) {
1157                 spec = ins_get_spec (ins->opcode);
1158                 spec_dest = spec [MONO_INST_DEST];
1159
1160                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1161                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1162                 }
1163
1164                 DEBUG (mono_print_ins_index (i, ins));
1165
1166                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1167
1168 #if MONO_ARCH_USE_FPSTACK
1169                 if (dreg_is_fp (spec)) {
1170                         has_fp = TRUE;
1171                 } else {
1172                         for (j = 0; j < num_sregs; ++j) {
1173                                 if (sreg_is_fp (j, spec))
1174                                         has_fp = TRUE;
1175                         }
1176                 }
1177 #endif
1178
1179                 for (j = 0; j < num_sregs; ++j) {
1180                         int sreg = sregs [j];
1181                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1182                         if (sreg_spec) {
1183                                 bank = sreg_bank (j, spec);
1184                                 g_assert (sreg != -1);
1185                                 if (is_soft_reg (sreg, bank))
1186                                         /* This means the vreg is not local to this bb */
1187                                         g_assert (reginfo [sreg].born_in > 0);
1188                                 rs->vassign [sreg] = -1;
1189                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1190                                 //reginfo [ins->sreg2].last_use = i;
1191                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1192                                         /* The virtual register is allocated sequentially */
1193                                         rs->vassign [sreg + 1] = -1;
1194                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1195                                         //reginfo [ins->sreg2 + 1].last_use = i;
1196                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1197                                                 reginfo [sreg + 1].born_in = i;
1198                                 }
1199                         } else {
1200                                 sregs [j] = -1;
1201                         }
1202                 }
1203                 mono_inst_set_src_registers (ins, sregs);
1204
1205                 if (spec_dest) {
1206                         int dest_dreg;
1207
1208                         bank = dreg_bank (spec);
1209                         if (spec_dest != 'b') /* it's not just a base register */
1210                                 reginfo [ins->dreg].killed_in = i;
1211                         g_assert (ins->dreg != -1);
1212                         rs->vassign [ins->dreg] = -1;
1213                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1214                         //reginfo [ins->dreg].last_use = i;
1215                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1216                                 reginfo [ins->dreg].born_in = i;
1217
1218                         dest_dreg = desc_to_fixed_reg [spec_dest];
1219                         if (dest_dreg != -1)
1220                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1221
1222 #ifdef MONO_ARCH_INST_FIXED_MASK
1223                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1224 #endif
1225
1226                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1227                                 /* The virtual register is allocated sequentially */
1228                                 rs->vassign [ins->dreg + 1] = -1;
1229                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1230                                 //reginfo [ins->dreg + 1].last_use = i;
1231                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1232                                         reginfo [ins->dreg + 1].born_in = i;
1233                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1234                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1235                         }
1236                 } else {
1237                         ins->dreg = -1;
1238                 }
1239
1240                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1241                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1242
1243                         MonoCallInst *call = (MonoCallInst*)ins;
1244                         GSList *list;
1245
1246                         list = call->out_ireg_args;
1247                         if (list) {
1248                                 while (list) {
1249                                         guint32 regpair;
1250                                         int reg, hreg;
1251
1252                                         regpair = (guint32)(gssize)(list->data);
1253                                         hreg = regpair >> 24;
1254                                         reg = regpair & 0xffffff;
1255
1256                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1257                                         //reginfo [reg].last_use = i;
1258
1259                                         list = g_slist_next (list);
1260                                 }
1261                         }
1262
1263                         list = call->out_freg_args;
1264                         if (list) {
1265                                 while (list) {
1266                                         guint32 regpair;
1267                                         int reg, hreg;
1268
1269                                         regpair = (guint32)(gssize)(list->data);
1270                                         hreg = regpair >> 24;
1271                                         reg = regpair & 0xffffff;
1272
1273                                         list = g_slist_next (list);
1274                                 }
1275                         }
1276                 }
1277
1278                 ++i;
1279         }
1280
1281         tmp = &last;
1282
1283         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1284         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1285                 int prev_dreg, clob_dreg;
1286                 int dest_dreg, clob_reg;
1287                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1288                 int dreg_high, sreg1_high;
1289                 regmask_t dreg_mask, mask;
1290                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1291                 regmask_t dreg_fixed_mask;
1292                 const unsigned char *ip;
1293                 --i;
1294                 spec = ins_get_spec (ins->opcode);
1295                 spec_src1 = spec [MONO_INST_SRC1];
1296                 spec_dest = spec [MONO_INST_DEST];
1297                 prev_dreg = -1;
1298                 clob_dreg = -1;
1299                 clob_reg = -1;
1300                 dest_dreg = -1;
1301                 dreg_high = -1;
1302                 sreg1_high = -1;
1303                 dreg_mask = get_callee_mask (spec_dest);
1304                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1305                         prev_sregs [j] = -1;
1306                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1307                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1308 #ifdef MONO_ARCH_INST_FIXED_MASK
1309                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1310 #else
1311                         sreg_fixed_masks [j] = 0;
1312 #endif
1313                 }
1314
1315                 DEBUG (printf ("processing:"));
1316                 DEBUG (mono_print_ins_index (i, ins));
1317
1318                 ip = ins->cil_code;
1319
1320                 last = ins;
1321
1322                 /*
1323                  * FIXED REGS
1324                  */
1325                 dest_dreg = desc_to_fixed_reg [spec_dest];
1326                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1327                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1328
1329 #ifdef MONO_ARCH_INST_FIXED_MASK
1330                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1331 #else
1332                 dreg_fixed_mask = 0;
1333 #endif
1334
1335                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1336
1337                 /*
1338                  * TRACK FIXED SREG2, 3, ...
1339                  */
1340                 for (j = 1; j < num_sregs; ++j) {
1341                         int sreg = sregs [j];
1342                         int dest_sreg = dest_sregs [j];
1343
1344                         if (dest_sreg == -1)
1345                                 continue;
1346
1347                         if (j == 2) {
1348                                 int k;
1349
1350                                 /*
1351                                  * CAS.
1352                                  * We need to special case this, since on x86, there are only 3
1353                                  * free registers, and the code below assigns one of them to
1354                                  * sreg, so we can run out of registers when trying to assign
1355                                  * dreg. Instead, we just set up the register masks, and let the
1356                                  * normal sreg2 assignment code handle this. It would be nice to
1357                                  * do this for all the fixed reg cases too, but there is too much
1358                                  * risk of breakage.
1359                                  */
1360
1361                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1362                                 sreg_masks [j] = regmask (dest_sreg);
1363                                 for (k = 0; k < num_sregs; ++k) {
1364                                         if (k != j)
1365                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1366                                 }
1367
1368                                 /*
1369                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1370                                  */
1371                                 for (k = 0; k < num_sregs; ++k) {
1372                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1373                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1374                                 }
1375
1376                                 /*
1377                                  * We can also run out of registers while processing sreg2 if sreg3 is
1378                                  * assigned to another hreg, so spill sreg3 now.
1379                                  */
1380                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1381                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1382                                 }
1383                                 continue;
1384                         }
1385
1386                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1387                                 if (is_global_ireg (sreg)) {
1388                                         int k;
1389                                         /* Argument already in hard reg, need to copy */
1390                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1391                                         insert_before_ins (bb, ins, copy);
1392                                         for (k = 0; k < num_sregs; ++k) {
1393                                                 if (k != j)
1394                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1395                                         }
1396                                 } else {
1397                                         val = rs->vassign [sreg];
1398                                         if (val == -1) {
1399                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1400                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1401                                         } else if (val < -1) {
1402                                                 /* FIXME: */
1403                                                 g_assert_not_reached ();
1404                                         } else {
1405                                                 /* Argument already in hard reg, need to copy */
1406                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1407                                                 int k;
1408
1409                                                 insert_before_ins (bb, ins, copy);
1410                                                 for (k = 0; k < num_sregs; ++k) {
1411                                                         if (k != j)
1412                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1413                                                 }
1414                                                 /*
1415                                                  * Prevent the dreg from being allocate to dest_sreg
1416                                                  * too, since it could force sreg1 to be allocated to
1417                                                  * the same reg on x86.
1418                                                  */
1419                                                 dreg_mask &= ~ (regmask (dest_sreg));
1420                                         }
1421                                 }
1422                         } else {
1423                                 gboolean need_spill = TRUE;
1424                                 gboolean need_assign = TRUE;
1425                                 int k;
1426
1427                                 dreg_mask &= ~ (regmask (dest_sreg));
1428                                 for (k = 0; k < num_sregs; ++k) {
1429                                         if (k != j)
1430                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1431                                 }
1432
1433                                 /*
1434                                  * First check if dreg is assigned to dest_sreg2, since we
1435                                  * can't spill a dreg.
1436                                  */
1437                                 if (spec [MONO_INST_DEST])
1438                                         val = rs->vassign [ins->dreg];
1439                                 else
1440                                         val = -1;
1441                                 if (val == dest_sreg && ins->dreg != sreg) {
1442                                         /*
1443                                          * the destination register is already assigned to
1444                                          * dest_sreg2: we need to allocate another register for it
1445                                          * and then copy from this to dest_sreg2.
1446                                          */
1447                                         int new_dest;
1448                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1449                                         g_assert (new_dest >= 0);
1450                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1451
1452                                         prev_dreg = ins->dreg;
1453                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1454                                         clob_dreg = ins->dreg;
1455                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1456                                         mono_regstate_free_int (rs, dest_sreg);
1457                                         need_spill = FALSE;
1458                                 }
1459
1460                                 if (is_global_ireg (sreg)) {
1461                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1462                                         insert_before_ins (bb, ins, copy);
1463                                         need_assign = FALSE;
1464                                 }
1465                                 else {
1466                                         val = rs->vassign [sreg];
1467                                         if (val == dest_sreg) {
1468                                                 /* sreg2 is already assigned to the correct register */
1469                                                 need_spill = FALSE;
1470                                         } else if (val < -1) {
1471                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1472                                         } else if (val >= 0) {
1473                                                 /* sreg2 already assigned to another register */
1474                                                 /*
1475                                                  * We couldn't emit a copy from val to dest_sreg2, because
1476                                                  * val might be spilled later while processing this
1477                                                  * instruction. So we spill sreg2 so it can be allocated to
1478                                                  * dest_sreg2.
1479                                                  */
1480                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1481                                         }
1482                                 }
1483
1484                                 if (need_spill) {
1485                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1486                                 }
1487
1488                                 if (need_assign) {
1489                                         if (rs->vassign [sreg] < -1) {
1490                                                 int spill;
1491
1492                                                 /* Need to emit a spill store */
1493                                                 spill = - rs->vassign [sreg] - 1;
1494                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1495                                         }
1496                                         /* force-set sreg2 */
1497                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1498                                 }
1499                         }
1500                         sregs [j] = dest_sreg;
1501                 }
1502                 mono_inst_set_src_registers (ins, sregs);
1503
1504                 /*
1505                  * TRACK DREG
1506                  */
1507                 bank = dreg_bank (spec);
1508                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1509                         prev_dreg = ins->dreg;
1510                 }
1511
1512                 if (spec_dest == 'b') {
1513                         /*
1514                          * The dest reg is read by the instruction, not written, so
1515                          * avoid allocating sreg1/sreg2 to the same reg.
1516                          */
1517                         if (dest_sregs [0] != -1)
1518                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1519                         for (j = 1; j < num_sregs; ++j) {
1520                                 if (dest_sregs [j] != -1)
1521                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1522                         }
1523
1524                         val = rs->vassign [ins->dreg];
1525                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1526                                 /* DREG is already allocated to a register needed for sreg1 */
1527                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1528                         }
1529                 }
1530
1531                 /*
1532                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1533                  * various complex situations.
1534                  */
1535                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1536                         guint32 dreg2, dest_dreg2;
1537
1538                         g_assert (is_soft_reg (ins->dreg, bank));
1539
1540                         if (dest_dreg != -1) {
1541                                 if (rs->vassign [ins->dreg] != dest_dreg)
1542                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1543
1544                                 dreg2 = ins->dreg + 1;
1545                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1546                                 if (dest_dreg2 != -1) {
1547                                         if (rs->vassign [dreg2] != dest_dreg2)
1548                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1549                                 }
1550                         }
1551                 }
1552
1553                 if (dreg_fixed_mask) {
1554                         g_assert (!bank);
1555                         if (is_global_ireg (ins->dreg)) {
1556                                 /*
1557                                  * The argument is already in a hard reg, but that reg is
1558                                  * not usable by this instruction, so allocate a new one.
1559                                  */
1560                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1561                                 if (val < 0)
1562                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1563                                 mono_regstate_free_int (rs, val);
1564                                 dest_dreg = val;
1565
1566                                 /* Fall through */
1567                         }
1568                         else
1569                                 dreg_mask &= dreg_fixed_mask;
1570                 }
1571
1572                 if (is_soft_reg (ins->dreg, bank)) {
1573                         val = rs->vassign [ins->dreg];
1574
1575                         if (val < 0) {
1576                                 int spill = 0;
1577                                 if (val < -1) {
1578                                         /* the register gets spilled after this inst */
1579                                         spill = -val -1;
1580                                 }
1581                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1582                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1583                                 if (spill)
1584                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1585                         }
1586
1587                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1588                         ins->dreg = val;
1589                 }
1590
1591                 /* Handle regpairs */
1592                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1593                         int reg2 = prev_dreg + 1;
1594
1595                         g_assert (!bank);
1596                         g_assert (prev_dreg > -1);
1597                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1598                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1599 #ifdef TARGET_X86
1600                         /* bug #80489 */
1601                         mask &= ~regmask (X86_ECX);
1602 #endif
1603                         val = rs->vassign [reg2];
1604                         if (val < 0) {
1605                                 int spill = 0;
1606                                 if (val < -1) {
1607                                         /* the register gets spilled after this inst */
1608                                         spill = -val -1;
1609                                 }
1610                                 val = mono_regstate_alloc_int (rs, mask);
1611                                 if (val < 0)
1612                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1613                                 if (spill)
1614                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1615                         }
1616                         else {
1617                                 if (! (mask & (regmask (val)))) {
1618                                         val = mono_regstate_alloc_int (rs, mask);
1619                                         if (val < 0)
1620                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1621
1622                                         /* Reallocate hreg to the correct register */
1623                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1624
1625                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1626                                 }
1627                         }
1628
1629                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1630                         assign_reg (cfg, rs, reg2, val, bank);
1631
1632                         dreg_high = val;
1633                         ins->backend.reg3 = val;
1634
1635                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1636                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1637                                 mono_regstate_free_int (rs, val);
1638                         }
1639                 }
1640
1641                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1642                         /*
1643                          * In theory, we could free up the hreg even if the vreg is alive,
1644                          * but branches inside bblocks force us to assign the same hreg
1645                          * to a vreg every time it is encountered.
1646                          */
1647                         int dreg = rs->vassign [prev_dreg];
1648                         g_assert (dreg >= 0);
1649                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1650                         if (G_UNLIKELY (bank))
1651                                 mono_regstate_free_general (rs, dreg, bank);
1652                         else
1653                                 mono_regstate_free_int (rs, dreg);
1654                         rs->vassign [prev_dreg] = -1;
1655                 }
1656
1657                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1658                         /* this instruction only outputs to dest_dreg, need to copy */
1659                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1660                         ins->dreg = dest_dreg;
1661
1662                         if (G_UNLIKELY (bank)) {
1663                                 /* the register we need to free up may be used in another logical regbank
1664                                  * so do a translate just in case.
1665                                  */
1666                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1667                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1668                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1669                         }
1670                         else {
1671                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1672                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1673                         }
1674                 }
1675
1676                 if (spec_dest == 'b') {
1677                         /*
1678                          * The dest reg is read by the instruction, not written, so
1679                          * avoid allocating sreg1/sreg2 to the same reg.
1680                          */
1681                         for (j = 0; j < num_sregs; ++j)
1682                                 if (!sreg_bank (j, spec))
1683                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1684                 }
1685
1686                 /*
1687                  * TRACK CLOBBERING
1688                  */
1689                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1690                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1691                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1692                 }
1693
1694                 if (spec [MONO_INST_CLOB] == 'c') {
1695                         int j, s, dreg, dreg2, cur_bank;
1696                         guint64 clob_mask;
1697
1698                         clob_mask = MONO_ARCH_CALLEE_REGS;
1699
1700                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1701                                 /*
1702                                  * Need to avoid spilling the dreg since the dreg is not really
1703                                  * clobbered by the call.
1704                                  */
1705                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1706                                         dreg = rs->vassign [prev_dreg];
1707                                 else
1708                                         dreg = -1;
1709
1710                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1711                                         dreg2 = rs->vassign [prev_dreg + 1];
1712                                 else
1713                                         dreg2 = -1;
1714
1715                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1716                                         s = regmask (j);
1717                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1718                                                 if ((j != dreg) && (j != dreg2))
1719                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1720                                                 else if (rs->isymbolic [j])
1721                                                         /* The hreg is assigned to the dreg of this instruction */
1722                                                         rs->vassign [rs->isymbolic [j]] = -1;
1723                                                 mono_regstate_free_int (rs, j);
1724                                         }
1725                                 }
1726                         }
1727
1728                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1729                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1730                                         clob_mask = regbank_callee_regs [cur_bank];
1731                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1732                                                 dreg = rs->vassign [prev_dreg];
1733                                         else
1734                                                 dreg = -1;
1735
1736                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1737
1738                                                 /* we are looping though the banks in the outer loop
1739                                                  * so, we don't need to deal with mirrored hregs
1740                                                  * because we will get them in one of the other bank passes.
1741                                                  */
1742                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1743                                                         continue;
1744
1745                                                 s = regmask (j);
1746                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1747                                                         if (j != dreg)
1748                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1749                                                         else if (rs->symbolic [cur_bank] [j])
1750                                                                 /* The hreg is assigned to the dreg of this instruction */
1751                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1752                                                         mono_regstate_free_general (rs, j, cur_bank);
1753                                                 }
1754                                         }
1755                                 }
1756                         }
1757                 }
1758
1759                 /*
1760                  * TRACK ARGUMENT REGS
1761                  */
1762                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1763                         MonoCallInst *call = (MonoCallInst*)ins;
1764                         GSList *list;
1765
1766                         /*
1767                          * This needs to be done before assigning sreg1, so sreg1 will
1768                          * not be assigned one of the argument regs.
1769                          */
1770
1771                         /*
1772                          * Assign all registers in call->out_reg_args to the proper
1773                          * argument registers.
1774                          */
1775
1776                         list = call->out_ireg_args;
1777                         if (list) {
1778                                 while (list) {
1779                                         guint32 regpair;
1780                                         int reg, hreg;
1781
1782                                         regpair = (guint32)(gssize)(list->data);
1783                                         hreg = regpair >> 24;
1784                                         reg = regpair & 0xffffff;
1785
1786                                         assign_reg (cfg, rs, reg, hreg, 0);
1787
1788                                         sreg_masks [0] &= ~(regmask (hreg));
1789
1790                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1791
1792                                         list = g_slist_next (list);
1793                                 }
1794                         }
1795
1796                         list = call->out_freg_args;
1797                         if (list) {
1798                                 while (list) {
1799                                         guint32 regpair;
1800                                         int reg, hreg;
1801
1802                                         regpair = (guint32)(gssize)(list->data);
1803                                         hreg = regpair >> 24;
1804                                         reg = regpair & 0xffffff;
1805
1806                                         assign_reg (cfg, rs, reg, hreg, 1);
1807
1808                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1809
1810                                         list = g_slist_next (list);
1811                                 }
1812                         }
1813                 }
1814
1815                 /*
1816                  * TRACK SREG1
1817                  */
1818                 bank = sreg1_bank (spec);
1819                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1820                         int sreg1 = sregs [0];
1821                         int dest_sreg1 = dest_sregs [0];
1822
1823                         g_assert (is_soft_reg (sreg1, bank));
1824
1825                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1826                         if (dest_sreg1 != -1)
1827                                 g_assert (dest_sreg1 == ins->dreg);
1828                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1829                         g_assert (val >= 0);
1830
1831                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1832                                 // FIXME:
1833                                 g_assert_not_reached ();
1834
1835                         assign_reg (cfg, rs, sreg1, val, bank);
1836
1837                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1838
1839                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1840                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1841                         g_assert (val >= 0);
1842
1843                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1844                                 // FIXME:
1845                                 g_assert_not_reached ();
1846
1847                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1848
1849                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1850
1851                         /* Skip rest of this section */
1852                         dest_sregs [0] = -1;
1853                 }
1854
1855                 if (sreg_fixed_masks [0]) {
1856                         g_assert (!bank);
1857                         if (is_global_ireg (sregs [0])) {
1858                                 /*
1859                                  * The argument is already in a hard reg, but that reg is
1860                                  * not usable by this instruction, so allocate a new one.
1861                                  */
1862                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1863                                 if (val < 0)
1864                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1865                                 mono_regstate_free_int (rs, val);
1866                                 dest_sregs [0] = val;
1867
1868                                 /* Fall through to the dest_sreg1 != -1 case */
1869                         }
1870                         else
1871                                 sreg_masks [0] &= sreg_fixed_masks [0];
1872                 }
1873
1874                 if (dest_sregs [0] != -1) {
1875                         sreg_masks [0] = regmask (dest_sregs [0]);
1876
1877                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1878                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1879                         }
1880                         if (is_global_ireg (sregs [0])) {
1881                                 /* The argument is already in a hard reg, need to copy */
1882                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1883                                 insert_before_ins (bb, ins, copy);
1884                                 sregs [0] = dest_sregs [0];
1885                         }
1886                 }
1887
1888                 if (is_soft_reg (sregs [0], bank)) {
1889                         val = rs->vassign [sregs [0]];
1890                         prev_sregs [0] = sregs [0];
1891                         if (val < 0) {
1892                                 int spill = 0;
1893                                 if (val < -1) {
1894                                         /* the register gets spilled after this inst */
1895                                         spill = -val -1;
1896                                 }
1897
1898                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1899                                         /*
1900                                          * Allocate the same hreg to sreg1 as well so the
1901                                          * peephole can get rid of the move.
1902                                          */
1903                                         sreg_masks [0] = regmask (ins->dreg);
1904                                 }
1905
1906                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1907                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1908                                         sreg_masks [0] = regmask (ins->dreg);
1909
1910                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1911                                 assign_reg (cfg, rs, sregs [0], val, bank);
1912                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1913
1914                                 if (spill) {
1915                                         /*
1916                                          * Need to insert before the instruction since it can
1917                                          * overwrite sreg1.
1918                                          */
1919                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1920                                 }
1921                         }
1922                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1923                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1924                                 insert_before_ins (bb, ins, copy);
1925                                 for (j = 1; j < num_sregs; ++j)
1926                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1927                                 val = dest_sregs [0];
1928                         }
1929
1930                         sregs [0] = val;
1931                 }
1932                 else {
1933                         prev_sregs [0] = -1;
1934                 }
1935                 mono_inst_set_src_registers (ins, sregs);
1936
1937                 for (j = 1; j < num_sregs; ++j)
1938                         sreg_masks [j] &= ~(regmask (sregs [0]));
1939
1940                 /* Handle the case when sreg1 is a regpair but dreg is not */
1941                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1942                         int reg2 = prev_sregs [0] + 1;
1943
1944                         g_assert (!bank);
1945                         g_assert (prev_sregs [0] > -1);
1946                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1947                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1948                         val = rs->vassign [reg2];
1949                         if (val < 0) {
1950                                 int spill = 0;
1951                                 if (val < -1) {
1952                                         /* the register gets spilled after this inst */
1953                                         spill = -val -1;
1954                                 }
1955                                 val = mono_regstate_alloc_int (rs, mask);
1956                                 if (val < 0)
1957                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1958                                 if (spill)
1959                                         g_assert_not_reached ();
1960                         }
1961                         else {
1962                                 if (! (mask & (regmask (val)))) {
1963                                         /* The vreg is already allocated to a wrong hreg */
1964                                         /* FIXME: */
1965                                         g_assert_not_reached ();
1966 #if 0
1967                                         val = mono_regstate_alloc_int (rs, mask);
1968                                         if (val < 0)
1969                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1970
1971                                         /* Reallocate hreg to the correct register */
1972                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1973
1974                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1975 #endif
1976                                 }
1977                         }
1978
1979                         sreg1_high = val;
1980                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1981                         assign_reg (cfg, rs, reg2, val, bank);
1982                 }
1983
1984                 /* Handle dreg==sreg1 */
1985                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1986                         MonoInst *sreg2_copy = NULL;
1987                         MonoInst *copy;
1988                         int bank = reg_bank (spec_src1);
1989
1990                         if (ins->dreg == sregs [1]) {
1991                                 /*
1992                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1993                                  * register for it.
1994                                  */
1995                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1996
1997                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1998                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1999                                 prev_sregs [1] = sregs [1] = reg2;
2000
2001                                 if (G_UNLIKELY (bank))
2002                                         mono_regstate_free_general (rs, reg2, bank);
2003                                 else
2004                                         mono_regstate_free_int (rs, reg2);
2005                         }
2006
2007                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2008                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2009                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2010                                         /* FIXME: */
2011                                         g_assert_not_reached ();
2012
2013                                 /*
2014                                  * sreg1 and dest are already allocated to the same regpair by the
2015                                  * SREG1 allocation code.
2016                                  */
2017                                 g_assert (sregs [0] == ins->dreg);
2018                                 g_assert (dreg_high == sreg1_high);
2019                         }
2020
2021                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2022                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2023                         insert_before_ins (bb, ins, copy);
2024
2025                         if (sreg2_copy)
2026                                 insert_before_ins (bb, copy, sreg2_copy);
2027
2028                         /*
2029                          * Need to prevent sreg2 to be allocated to sreg1, since that
2030                          * would screw up the previous copy.
2031                          */
2032                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2033                         /* we set sreg1 to dest as well */
2034                         prev_sregs [0] = sregs [0] = ins->dreg;
2035                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2036                 }
2037                 mono_inst_set_src_registers (ins, sregs);
2038
2039                 /*
2040                  * TRACK SREG2, 3, ...
2041                  */
2042                 for (j = 1; j < num_sregs; ++j) {
2043                         int k;
2044
2045                         bank = sreg_bank (j, spec);
2046                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2047                                 g_assert_not_reached ();
2048
2049                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2050                                 /*
2051                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2052                                  * allocating it to the fixed reg.
2053                                  */
2054                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2055                                 insert_before_ins (bb, ins, copy);
2056                                 sregs [j] = dest_sregs [j];
2057                         } else if (is_soft_reg (sregs [j], bank)) {
2058                                 val = rs->vassign [sregs [j]];
2059
2060                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2061                                         /*
2062                                          * The sreg is already allocated to a hreg, but not to the fixed
2063                                          * reg required by the instruction. Spill the sreg, so it can be
2064                                          * allocated to the fixed reg by the code below.
2065                                          */
2066                                         /* Currently, this code should only be hit for CAS */
2067                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2068                                         val = rs->vassign [sregs [j]];
2069                                 }
2070
2071                                 if (val < 0) {
2072                                         int spill = 0;
2073                                         if (val < -1) {
2074                                                 /* the register gets spilled after this inst */
2075                                                 spill = -val -1;
2076                                         }
2077                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2078                                         assign_reg (cfg, rs, sregs [j], val, bank);
2079                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2080                                         if (spill) {
2081                                                 /*
2082                                                  * Need to insert before the instruction since it can
2083                                                  * overwrite sreg2.
2084                                                  */
2085                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2086                                         }
2087                                 }
2088                                 sregs [j] = val;
2089                                 for (k = j + 1; k < num_sregs; ++k)
2090                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2091                         }
2092                         else {
2093                                 prev_sregs [j] = -1;
2094                         }
2095                 }
2096                 mono_inst_set_src_registers (ins, sregs);
2097
2098                 /* Sanity check */
2099                 /* Do this only for CAS for now */
2100                 for (j = 1; j < num_sregs; ++j) {
2101                         int sreg = sregs [j];
2102                         int dest_sreg = dest_sregs [j];
2103
2104                         if (j == 2 && dest_sreg != -1) {
2105                                 int k;
2106
2107                                 g_assert (sreg == dest_sreg);
2108
2109                                 for (k = 0; k < num_sregs; ++k) {
2110                                         if (k != j)
2111                                                 g_assert (sregs [k] != dest_sreg);
2112                                 }
2113                         }
2114                 }
2115
2116                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2117                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2118                         mono_regstate_free_int (rs, ins->sreg1);
2119                 }
2120                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2121                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2122                         mono_regstate_free_int (rs, ins->sreg2);
2123                 }*/
2124
2125                 DEBUG (mono_print_ins_index (i, ins));
2126         }
2127
2128         // FIXME: Set MAX_FREGS to 8
2129         // FIXME: Optimize generated code
2130 #if MONO_ARCH_USE_FPSTACK
2131         /*
2132          * Make a forward pass over the code, simulating the fp stack, making sure the
2133          * arguments required by the fp opcodes are at the top of the stack.
2134          */
2135         if (has_fp) {
2136                 MonoInst *prev = NULL;
2137                 MonoInst *fxch;
2138                 int tmp;
2139
2140                 g_assert (num_sregs <= 2);
2141
2142                 for (ins = bb->code; ins; ins = ins->next) {
2143                         spec = ins_get_spec (ins->opcode);
2144
2145                         DEBUG (printf ("processing:"));
2146                         DEBUG (mono_print_ins_index (0, ins));
2147
2148                         if (ins->opcode == OP_FMOVE) {
2149                                 /* Do it by renaming the source to the destination on the stack */
2150                                 // FIXME: Is this correct ?
2151                                 for (i = 0; i < sp; ++i)
2152                                         if (fpstack [i] == ins->sreg1)
2153                                                 fpstack [i] = ins->dreg;
2154                                 prev = ins;
2155                                 continue;
2156                         }
2157
2158                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2159                                 /* Arg1 must be in %st(1) */
2160                                 g_assert (prev);
2161
2162                                 i = 0;
2163                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2164                                         i ++;
2165                                 g_assert (i < sp);
2166
2167                                 if (sp - 1 - i > 0) {
2168                                         /* First move it to %st(0) */
2169                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2170
2171                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2172                                         fxch->inst_imm = sp - 1 - i;
2173
2174                                         prev->next = fxch;
2175                                         fxch->next = ins;
2176                                         prev = fxch;
2177
2178                                         tmp = fpstack [sp - 1];
2179                                         fpstack [sp - 1] = fpstack [i];
2180                                         fpstack [i] = tmp;
2181                                 }
2182
2183                                 /* Then move it to %st(1) */
2184                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2185
2186                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2187                                 fxch->inst_imm = 1;
2188
2189                                 prev->next = fxch;
2190                                 fxch->next = ins;
2191                                 prev = fxch;
2192
2193                                 tmp = fpstack [sp - 1];
2194                                 fpstack [sp - 1] = fpstack [sp - 2];
2195                                 fpstack [sp - 2] = tmp;
2196                         }
2197
2198                         if (sreg2_is_fp (spec)) {
2199                                 g_assert (sp > 0);
2200
2201                                 if (fpstack [sp - 1] != ins->sreg2) {
2202                                         g_assert (prev);
2203
2204                                         i = 0;
2205                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2206                                                 i ++;
2207                                         g_assert (i < sp);
2208
2209                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2210
2211                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2212                                         fxch->inst_imm = sp - 1 - i;
2213
2214                                         prev->next = fxch;
2215                                         fxch->next = ins;
2216                                         prev = fxch;
2217
2218                                         tmp = fpstack [sp - 1];
2219                                         fpstack [sp - 1] = fpstack [i];
2220                                         fpstack [i] = tmp;
2221                                 }
2222
2223                                 sp --;
2224                         }
2225
2226                         if (sreg1_is_fp (spec)) {
2227                                 g_assert (sp > 0);
2228
2229                                 if (fpstack [sp - 1] != ins->sreg1) {
2230                                         g_assert (prev);
2231
2232                                         i = 0;
2233                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2234                                                 i ++;
2235                                         g_assert (i < sp);
2236
2237                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2238
2239                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2240                                         fxch->inst_imm = sp - 1 - i;
2241
2242                                         prev->next = fxch;
2243                                         fxch->next = ins;
2244                                         prev = fxch;
2245
2246                                         tmp = fpstack [sp - 1];
2247                                         fpstack [sp - 1] = fpstack [i];
2248                                         fpstack [i] = tmp;
2249                                 }
2250
2251                                 sp --;
2252                         }
2253
2254                         if (dreg_is_fp (spec)) {
2255                                 g_assert (sp < 8);
2256                                 fpstack [sp ++] = ins->dreg;
2257                         }
2258
2259                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2260                                 printf ("\t[");
2261                                 for (i = 0; i < sp; ++i)
2262                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2263                                 printf ("]\n");
2264                         }
2265
2266                         prev = ins;
2267                 }
2268
2269                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2270                         /* Remove remaining items from the fp stack */
2271                         /*
2272                          * These can remain for example as a result of a dead fmove like in
2273                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2274                          */
2275                         while (sp) {
2276                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2277                                 mono_add_ins_to_end (bb, ins);
2278                                 sp --;
2279                         }
2280                 }
2281         }
2282 #endif
2283 }
2284
2285 CompRelation
2286 mono_opcode_to_cond (int opcode)
2287 {
2288         switch (opcode) {
2289         case OP_CEQ:
2290         case OP_IBEQ:
2291         case OP_ICEQ:
2292         case OP_LBEQ:
2293         case OP_LCEQ:
2294         case OP_FBEQ:
2295         case OP_FCEQ:
2296         case OP_COND_EXC_EQ:
2297         case OP_COND_EXC_IEQ:
2298         case OP_CMOV_IEQ:
2299         case OP_CMOV_LEQ:
2300                 return CMP_EQ;
2301         case OP_IBNE_UN:
2302         case OP_LBNE_UN:
2303         case OP_FBNE_UN:
2304         case OP_COND_EXC_NE_UN:
2305         case OP_COND_EXC_INE_UN:
2306         case OP_CMOV_INE_UN:
2307         case OP_CMOV_LNE_UN:
2308                 return CMP_NE;
2309         case OP_IBLE:
2310         case OP_LBLE:
2311         case OP_FBLE:
2312         case OP_CMOV_ILE:
2313         case OP_CMOV_LLE:
2314                 return CMP_LE;
2315         case OP_IBGE:
2316         case OP_LBGE:
2317         case OP_FBGE:
2318         case OP_CMOV_IGE:
2319         case OP_CMOV_LGE:
2320                 return CMP_GE;
2321         case OP_CLT:
2322         case OP_IBLT:
2323         case OP_ICLT:
2324         case OP_LBLT:
2325         case OP_LCLT:
2326         case OP_FBLT:
2327         case OP_FCLT:
2328         case OP_COND_EXC_LT:
2329         case OP_COND_EXC_ILT:
2330         case OP_CMOV_ILT:
2331         case OP_CMOV_LLT:
2332                 return CMP_LT;
2333         case OP_CGT:
2334         case OP_IBGT:
2335         case OP_ICGT:
2336         case OP_LBGT:
2337         case OP_LCGT:
2338         case OP_FBGT:
2339         case OP_FCGT:
2340         case OP_COND_EXC_GT:
2341         case OP_COND_EXC_IGT:
2342         case OP_CMOV_IGT:
2343         case OP_CMOV_LGT:
2344                 return CMP_GT;
2345
2346         case OP_IBLE_UN:
2347         case OP_LBLE_UN:
2348         case OP_FBLE_UN:
2349         case OP_COND_EXC_LE_UN:
2350         case OP_COND_EXC_ILE_UN:
2351         case OP_CMOV_ILE_UN:
2352         case OP_CMOV_LLE_UN:
2353                 return CMP_LE_UN;
2354         case OP_IBGE_UN:
2355         case OP_LBGE_UN:
2356         case OP_FBGE_UN:
2357         case OP_CMOV_IGE_UN:
2358         case OP_CMOV_LGE_UN:
2359                 return CMP_GE_UN;
2360         case OP_CLT_UN:
2361         case OP_IBLT_UN:
2362         case OP_ICLT_UN:
2363         case OP_LBLT_UN:
2364         case OP_LCLT_UN:
2365         case OP_FBLT_UN:
2366         case OP_FCLT_UN:
2367         case OP_COND_EXC_LT_UN:
2368         case OP_COND_EXC_ILT_UN:
2369         case OP_CMOV_ILT_UN:
2370         case OP_CMOV_LLT_UN:
2371                 return CMP_LT_UN;
2372         case OP_CGT_UN:
2373         case OP_IBGT_UN:
2374         case OP_ICGT_UN:
2375         case OP_LBGT_UN:
2376         case OP_LCGT_UN:
2377         case OP_FCGT_UN:
2378         case OP_FBGT_UN:
2379         case OP_COND_EXC_GT_UN:
2380         case OP_COND_EXC_IGT_UN:
2381         case OP_CMOV_IGT_UN:
2382         case OP_CMOV_LGT_UN:
2383                 return CMP_GT_UN;
2384         default:
2385                 printf ("%s\n", mono_inst_name (opcode));
2386                 g_assert_not_reached ();
2387                 return 0;
2388         }
2389 }
2390
2391 CompRelation
2392 mono_negate_cond (CompRelation cond)
2393 {
2394         switch (cond) {
2395         case CMP_EQ:
2396                 return CMP_NE;
2397         case CMP_NE:
2398                 return CMP_EQ;
2399         case CMP_LE:
2400                 return CMP_GT;
2401         case CMP_GE:
2402                 return CMP_LT;
2403         case CMP_LT:
2404                 return CMP_GE;
2405         case CMP_GT:
2406                 return CMP_LE;
2407         case CMP_LE_UN:
2408                 return CMP_GT_UN;
2409         case CMP_GE_UN:
2410                 return CMP_LT_UN;
2411         case CMP_LT_UN:
2412                 return CMP_GE_UN;
2413         case CMP_GT_UN:
2414                 return CMP_LE_UN;
2415         default:
2416                 g_assert_not_reached ();
2417         }
2418 }
2419
2420 CompType
2421 mono_opcode_to_type (int opcode, int cmp_opcode)
2422 {
2423         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2424                 return CMP_TYPE_L;
2425         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2426                 return CMP_TYPE_I;
2427         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2428                 return CMP_TYPE_I;
2429         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2430                 return CMP_TYPE_L;
2431         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2432                 return CMP_TYPE_L;
2433         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2434                 return CMP_TYPE_F;
2435         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2436                 return CMP_TYPE_F;
2437         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2438                 return CMP_TYPE_I;
2439         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2440                 switch (cmp_opcode) {
2441                 case OP_ICOMPARE:
2442                 case OP_ICOMPARE_IMM:
2443                         return CMP_TYPE_I;
2444                 default:
2445                         return CMP_TYPE_L;
2446                 }
2447         } else {
2448                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2449                 return 0;
2450         }
2451 }
2452
2453 #endif /* DISABLE_JIT */
2454
2455 gboolean
2456 mono_is_regsize_var (MonoType *t)
2457 {
2458         if (t->byref)
2459                 return TRUE;
2460         t = mono_type_get_underlying_type (t);
2461         switch (t->type) {
2462         case MONO_TYPE_BOOLEAN:
2463         case MONO_TYPE_CHAR:
2464         case MONO_TYPE_I1:
2465         case MONO_TYPE_U1:
2466         case MONO_TYPE_I2:
2467         case MONO_TYPE_U2:
2468         case MONO_TYPE_I4:
2469         case MONO_TYPE_U4:
2470         case MONO_TYPE_I:
2471         case MONO_TYPE_U:
2472         case MONO_TYPE_PTR:
2473         case MONO_TYPE_FNPTR:
2474 #if SIZEOF_REGISTER == 8
2475         case MONO_TYPE_I8:
2476         case MONO_TYPE_U8:
2477 #endif
2478                 return TRUE;
2479         case MONO_TYPE_OBJECT:
2480         case MONO_TYPE_STRING:
2481         case MONO_TYPE_CLASS:
2482         case MONO_TYPE_SZARRAY:
2483         case MONO_TYPE_ARRAY:
2484                 return TRUE;
2485         case MONO_TYPE_GENERICINST:
2486                 if (!mono_type_generic_inst_is_valuetype (t))
2487                         return TRUE;
2488                 return FALSE;
2489         case MONO_TYPE_VALUETYPE:
2490                 return FALSE;
2491         default:
2492                 return FALSE;
2493         }
2494 }
2495
2496 #ifndef DISABLE_JIT
2497
2498 /*
2499  * mono_peephole_ins:
2500  *
2501  *   Perform some architecture independent peephole optimizations.
2502  */
2503 void
2504 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2505 {
2506         MonoInst *last_ins = ins->prev;
2507
2508         switch (ins->opcode) {
2509         case OP_MUL_IMM:
2510                 /* remove unnecessary multiplication with 1 */
2511                 if (ins->inst_imm == 1) {
2512                         if (ins->dreg != ins->sreg1)
2513                                 ins->opcode = OP_MOVE;
2514                         else
2515                                 MONO_DELETE_INS (bb, ins);
2516                 }
2517                 break;
2518         case OP_LOAD_MEMBASE:
2519         case OP_LOADI4_MEMBASE:
2520                 /*
2521                  * Note: if reg1 = reg2 the load op is removed
2522                  *
2523                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2524                  * OP_LOAD_MEMBASE offset(basereg), reg2
2525                  * -->
2526                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2527                  * OP_MOVE reg1, reg2
2528                  */
2529                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2530                         last_ins = last_ins->prev;
2531                 if (last_ins &&
2532                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2533                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2534                         ins->inst_basereg == last_ins->inst_destbasereg &&
2535                         ins->inst_offset == last_ins->inst_offset) {
2536                         if (ins->dreg == last_ins->sreg1) {
2537                                 MONO_DELETE_INS (bb, ins);
2538                                 break;
2539                         } else {
2540                                 ins->opcode = OP_MOVE;
2541                                 ins->sreg1 = last_ins->sreg1;
2542                         }
2543
2544                         /*
2545                          * Note: reg1 must be different from the basereg in the second load
2546                          * Note: if reg1 = reg2 is equal then second load is removed
2547                          *
2548                          * OP_LOAD_MEMBASE offset(basereg), reg1
2549                          * OP_LOAD_MEMBASE offset(basereg), reg2
2550                          * -->
2551                          * OP_LOAD_MEMBASE offset(basereg), reg1
2552                          * OP_MOVE reg1, reg2
2553                          */
2554                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2555                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2556                           ins->inst_basereg != last_ins->dreg &&
2557                           ins->inst_basereg == last_ins->inst_basereg &&
2558                           ins->inst_offset == last_ins->inst_offset) {
2559
2560                         if (ins->dreg == last_ins->dreg) {
2561                                 MONO_DELETE_INS (bb, ins);
2562                         } else {
2563                                 ins->opcode = OP_MOVE;
2564                                 ins->sreg1 = last_ins->dreg;
2565                         }
2566
2567                         //g_assert_not_reached ();
2568
2569 #if 0
2570                         /*
2571                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2572                          * OP_LOAD_MEMBASE offset(basereg), reg
2573                          * -->
2574                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2575                          * OP_ICONST reg, imm
2576                          */
2577                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2578                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2579                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2580                                    ins->inst_offset == last_ins->inst_offset) {
2581                         ins->opcode = OP_ICONST;
2582                         ins->inst_c0 = last_ins->inst_imm;
2583                         g_assert_not_reached (); // check this rule
2584 #endif
2585                 }
2586                 break;
2587         case OP_LOADI1_MEMBASE:
2588         case OP_LOADU1_MEMBASE:
2589                 /*
2590                  * Note: if reg1 = reg2 the load op is removed
2591                  *
2592                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2593                  * OP_LOAD_MEMBASE offset(basereg), reg2
2594                  * -->
2595                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2596                  * OP_MOVE reg1, reg2
2597                  */
2598                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2599                         ins->inst_basereg == last_ins->inst_destbasereg &&
2600                         ins->inst_offset == last_ins->inst_offset) {
2601                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2602                         ins->sreg1 = last_ins->sreg1;
2603                 }
2604                 break;
2605         case OP_LOADI2_MEMBASE:
2606         case OP_LOADU2_MEMBASE:
2607                 /*
2608                  * Note: if reg1 = reg2 the load op is removed
2609                  *
2610                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2611                  * OP_LOAD_MEMBASE offset(basereg), reg2
2612                  * -->
2613                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2614                  * OP_MOVE reg1, reg2
2615                  */
2616                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2617                         ins->inst_basereg == last_ins->inst_destbasereg &&
2618                         ins->inst_offset == last_ins->inst_offset) {
2619 #if SIZEOF_REGISTER == 8
2620                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2621 #else
2622                         /* The definition of OP_PCONV_TO_U2 is wrong */
2623                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2624 #endif
2625                         ins->sreg1 = last_ins->sreg1;
2626                 }
2627                 break;
2628         case OP_MOVE:
2629         case OP_FMOVE:
2630                 /*
2631                  * Removes:
2632                  *
2633                  * OP_MOVE reg, reg
2634                  */
2635                 if (ins->dreg == ins->sreg1) {
2636                         MONO_DELETE_INS (bb, ins);
2637                         break;
2638                 }
2639                 /*
2640                  * Removes:
2641                  *
2642                  * OP_MOVE sreg, dreg
2643                  * OP_MOVE dreg, sreg
2644                  */
2645                 if (last_ins && last_ins->opcode == ins->opcode &&
2646                         ins->sreg1 == last_ins->dreg &&
2647                         ins->dreg == last_ins->sreg1) {
2648                         MONO_DELETE_INS (bb, ins);
2649                 }
2650                 break;
2651         case OP_NOP:
2652                 MONO_DELETE_INS (bb, ins);
2653                 break;
2654         }
2655 }
2656
2657 #endif /* DISABLE_JIT */