mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_XREGS
  74 };
  75
  76 static const int regbank_load_ops [] = {
  77         OP_LOADR_MEMBASE,
  78         OP_LOADR8_MEMBASE,
  79         OP_LOADX_MEMBASE
  80 };
  81
  82 static const int regbank_store_ops [] = {
  83         OP_STORER_MEMBASE_REG,
  84         OP_STORER8_MEMBASE_REG,
  85         OP_STOREX_MEMBASE
  86 };
  87
  88 static const int regbank_move_ops [] = {
  89         OP_MOVE,
  90         OP_FMOVE,
  91         OP_XMOVE
  92 };
  93
  94 #define regmask(reg) (((regmask_t)1) << (reg))
  95
  96 static const regmask_t regbank_callee_saved_regs [] = {
  97         MONO_ARCH_CALLEE_SAVED_REGS,
  98         MONO_ARCH_CALLEE_SAVED_FREGS,
  99         MONO_ARCH_CALLEE_SAVED_XREGS,
 100 };
 101
 102 static const regmask_t regbank_callee_regs [] = {
 103         MONO_ARCH_CALLEE_REGS,
 104         MONO_ARCH_CALLEE_FREGS,
 105         MONO_ARCH_CALLEE_XREGS,
 106 };
 107
 108 static const int regbank_spill_var_size[] = {
 109         sizeof (mgreg_t),
 110         sizeof (double),
 111         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 112 };
 113
 114 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 115
 116 static inline void
 117 mono_regstate_assign (MonoRegState *rs)
 118 {
 119 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 120         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 121          * if the values here are not the same.
 122          */
 123         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 124         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 125         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 126 #endif
 127
 128         if (rs->next_vreg > rs->vassign_size) {
 129                 g_free (rs->vassign);
 130                 rs->vassign_size = MAX (rs->next_vreg, 256);
 131                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 132         }
 133
 134         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 135         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 136
 137         rs->symbolic [0] = rs->isymbolic;
 138         rs->symbolic [1] = rs->fsymbolic;
 139
 140 #ifdef MONO_ARCH_NEED_SIMD_BANK
 141         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 142         rs->symbolic [2] = rs->xsymbolic;
 143 #endif
 144 }
 145
 146 static inline int
 147 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 148 {
 149         regmask_t mask = allow & rs->ifree_mask;
 150
 151 #if defined(__x86_64__) && defined(__GNUC__)
 152  {
 153         guint64 i;
 154
 155         if (mask == 0)
 156                 return -1;
 157
 158         __asm__("bsfq %1,%0\n\t"
 159                         : "=r" (i) : "rm" (mask));
 160
 161         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 162         return i;
 163  }
 164 #else
 165         int i;
 166
 167         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 168                 if (mask & ((regmask_t)1 << i)) {
 169                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 170                         return i;
 171                 }
 172         }
 173         return -1;
 174 #endif
 175 }
 176
 177 static inline void
 178 mono_regstate_free_int (MonoRegState *rs, int reg)
 179 {
 180         if (reg >= 0) {
 181                 rs->ifree_mask |= (regmask_t)1 << reg;
 182                 rs->isymbolic [reg] = 0;
 183         }
 184 }
 185
 186 static inline int
 187 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 188 {
 189         int i;
 190         int mirrored_bank;
 191         regmask_t mask = allow & rs->free_mask [bank];
 192         for (i = 0; i < regbank_size [bank]; ++i) {
 193                 if (mask & ((regmask_t)1 << i)) {
 194                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 195
 196                         mirrored_bank = get_mirrored_bank (bank);
 197                         if (mirrored_bank == -1)
 198                                 return i;
 199
 200                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 201                         return i;
 202                 }
 203         }
 204         return -1;
 205 }
 206
 207 static inline void
 208 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 209 {
 210         int mirrored_bank;
 211
 212         if (reg >= 0) {
 213                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 214                 rs->symbolic [bank][reg] = 0;
 215
 216                 mirrored_bank = get_mirrored_bank (bank);
 217                 if (mirrored_bank == -1)
 218                         return;
 219                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 220                 rs->symbolic [mirrored_bank][reg] = 0;
 221         }
 222 }
 223
 224 const char*
 225 mono_regname_full (int reg, int bank)
 226 {
 227         if (G_UNLIKELY (bank)) {
 228 #if MONO_ARCH_NEED_SIMD_BANK
 229                 if (bank == 2)
 230                         return mono_arch_xregname (reg);
 231 #endif
 232                 g_assert (bank == 1);
 233                 return mono_arch_fregname (reg);
 234         } else {
 235                 return mono_arch_regname (reg);
 236         }
 237 }
 238
 239 void
 240 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 241 {
 242         guint32 regpair;
 243
 244         regpair = (((guint32)hreg) << 24) + vreg;
 245         if (G_UNLIKELY (bank)) {
 246                 g_assert (vreg >= regbank_size [bank]);
 247                 g_assert (hreg < regbank_size [bank]);
 248                 call->used_fregs |= 1 << hreg;
 249                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 250         } else {
 251                 g_assert (vreg >= MONO_MAX_IREGS);
 252                 g_assert (hreg < MONO_MAX_IREGS);
 253                 call->used_iregs |= 1 << hreg;
 254                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 255         }
 256 }
 257
 258 static void
 259 resize_spill_info (MonoCompile *cfg, int bank)
 260 {
 261         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 262         int orig_len = cfg->spill_info_len [bank];
 263         int new_len = orig_len ? orig_len * 2 : 16;
 264         MonoSpillInfo *new_info;
 265         int i;
 266
 267         g_assert (bank < MONO_NUM_REGBANKS);
 268
 269         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 270         if (orig_info)
 271                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 272         for (i = orig_len; i < new_len; ++i)
 273                 new_info [i].offset = -1;
 274
 275         cfg->spill_info [bank] = new_info;
 276         cfg->spill_info_len [bank] = new_len;
 277 }
 278
 279 /*
 280  * returns the offset used by spillvar. It allocates a new
 281  * spill variable if necessary.
 282  */
 283 static inline int
 284 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 285 {
 286         MonoSpillInfo *info;
 287         int size;
 288
 289         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 290                 while (spillvar >= cfg->spill_info_len [bank])
 291                         resize_spill_info (cfg, bank);
 292         }
 293
 294         /*
 295          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 296          */
 297         info = &cfg->spill_info [bank][spillvar];
 298         if (info->offset == -1) {
 299                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 300                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 301
 302                 g_assert (bank < MONO_NUM_REGBANKS);
 303                 if (G_UNLIKELY (bank))
 304                         size = regbank_spill_var_size [bank];
 305                 else
 306                         size = sizeof (mgreg_t);
 307
 308                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 309                         cfg->stack_offset += size - 1;
 310                         cfg->stack_offset &= ~(size - 1);
 311                         info->offset = cfg->stack_offset;
 312                         cfg->stack_offset += size;
 313                 } else {
 314                         cfg->stack_offset += size - 1;
 315                         cfg->stack_offset &= ~(size - 1);
 316                         cfg->stack_offset += size;
 317                         info->offset = - cfg->stack_offset;
 318                 }
 319         }
 320
 321         return info->offset;
 322 }
 323
 324 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 325 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 326 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 327 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 328 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 329 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 330
 331 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 332 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 333 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 334 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 335 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 336
 337 #ifndef MONO_ARCH_INST_IS_FLOAT
 338 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 339 #endif
 340
 341 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 342 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 343 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 344 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 345 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 346
 347 #define reg_is_simd(desc) ((desc) == 'x')
 348
 349 #ifdef MONO_ARCH_NEED_SIMD_BANK
 350
 351 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 352
 353 #else
 354
 355 #define reg_bank(desc) reg_is_fp ((desc))
 356
 357 #endif
 358
 359 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 360 #define sreg1_bank(spec) sreg_bank (0, (spec))
 361 #define sreg2_bank(spec) sreg_bank (1, (spec))
 362 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 363
 364 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 365 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 366 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 367 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 368
 369 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 370
 371 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 372 #undef is_global_ireg
 373 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 374 #endif
 375
 376 typedef struct {
 377         int born_in;
 378         int killed_in;
 379         /* Not (yet) used */
 380         //int last_use;
 381         //int prev_use;
 382         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 383 } RegTrack;
 384
 385 #ifndef DISABLE_LOGGING
 386 void
 387 mono_print_ins_index (int i, MonoInst *ins)
 388 {
 389         const char *spec = ins_get_spec (ins->opcode);
 390         int num_sregs, j;
 391         int sregs [MONO_MAX_SRC_REGS];
 392
 393         if (i != -1)
 394                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 395         else
 396                 printf (" %s", mono_inst_name (ins->opcode));
 397         if (spec == MONO_ARCH_CPU_SPEC) {
 398                 /* This is a lowered opcode */
 399                 if (ins->dreg != -1)
 400                         printf (" R%d <-", ins->dreg);
 401                 if (ins->sreg1 != -1)
 402                         printf (" R%d", ins->sreg1);
 403                 if (ins->sreg2 != -1)
 404                         printf (" R%d", ins->sreg2);
 405                 if (ins->sreg3 != -1)
 406                         printf (" R%d", ins->sreg3);
 407
 408                 switch (ins->opcode) {
 409                 case OP_LBNE_UN:
 410                 case OP_LBEQ:
 411                 case OP_LBLT:
 412                 case OP_LBLT_UN:
 413                 case OP_LBGT:
 414                 case OP_LBGT_UN:
 415                 case OP_LBGE:
 416                 case OP_LBGE_UN:
 417                 case OP_LBLE:
 418                 case OP_LBLE_UN:
 419                         if (!ins->inst_false_bb)
 420                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 421                         else
 422                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 423                         break;
 424                 case OP_PHI:
 425                 case OP_VPHI:
 426                 case OP_XPHI:
 427                 case OP_FPHI: {
 428                         int i;
 429                         printf (" [%d (", (int)ins->inst_c0);
 430                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 431                                 if (i)
 432                                         printf (", ");
 433                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 434                         }
 435                         printf (")]");
 436                         break;
 437                 }
 438                 case OP_LDADDR:
 439                 case OP_OUTARG_VTRETADDR:
 440                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 441                         break;
 442                 case OP_REGOFFSET:
 443                         printf (" + 0x%lx", (long)ins->inst_offset);
 444                         break;
 445                 default:
 446                         break;
 447                 }
 448
 449                 printf ("\n");
 450                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 451                 return;
 452         }
 453
 454         if (spec [MONO_INST_DEST]) {
 455                 int bank = dreg_bank (spec);
 456                 if (is_soft_reg (ins->dreg, bank)) {
 457                         if (spec [MONO_INST_DEST] == 'b') {
 458                                 if (ins->inst_offset == 0)
 459                                         printf (" [R%d] <-", ins->dreg);
 460                                 else
 461                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 462                         }
 463                         else
 464                                 printf (" R%d <-", ins->dreg);
 465                 } else if (spec [MONO_INST_DEST] == 'b') {
 466                         if (ins->inst_offset == 0)
 467                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 468                         else
 469                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 470                 } else
 471                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 472         }
 473         if (spec [MONO_INST_SRC1]) {
 474                 int bank = sreg1_bank (spec);
 475                 if (is_soft_reg (ins->sreg1, bank)) {
 476                         if (spec [MONO_INST_SRC1] == 'b')
 477                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 478                         else
 479                                 printf (" R%d", ins->sreg1);
 480                 } else if (spec [MONO_INST_SRC1] == 'b')
 481                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 482                 else
 483                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 484         }
 485         num_sregs = mono_inst_get_src_registers (ins, sregs);
 486         for (j = 1; j < num_sregs; ++j) {
 487                 int bank = sreg_bank (j, spec);
 488                 if (is_soft_reg (sregs [j], bank))
 489                         printf (" R%d", sregs [j]);
 490                 else
 491                         printf (" %s", mono_regname_full (sregs [j], bank));
 492         }
 493
 494         switch (ins->opcode) {
 495         case OP_ICONST:
 496                 printf (" [%d]", (int)ins->inst_c0);
 497                 break;
 498 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 499         case OP_X86_PUSH_IMM:
 500 #endif
 501         case OP_ICOMPARE_IMM:
 502         case OP_COMPARE_IMM:
 503         case OP_IADD_IMM:
 504         case OP_ISUB_IMM:
 505         case OP_IAND_IMM:
 506         case OP_IOR_IMM:
 507         case OP_IXOR_IMM:
 508                 printf (" [%d]", (int)ins->inst_imm);
 509                 break;
 510         case OP_ADD_IMM:
 511         case OP_LADD_IMM:
 512                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 513                 break;
 514         case OP_I8CONST:
 515                 printf (" [%lld]", (long long)ins->inst_l);
 516                 break;
 517         case OP_R8CONST:
 518                 printf (" [%f]", *(double*)ins->inst_p0);
 519                 break;
 520         case OP_R4CONST:
 521                 printf (" [%f]", *(float*)ins->inst_p0);
 522                 break;
 523         case OP_CALL:
 524         case OP_CALL_MEMBASE:
 525         case OP_CALL_REG:
 526         case OP_FCALL:
 527         case OP_FCALLVIRT:
 528         case OP_LCALL:
 529         case OP_LCALLVIRT:
 530         case OP_VCALL:
 531         case OP_VCALLVIRT:
 532         case OP_VCALL_REG:
 533         case OP_VCALL_MEMBASE:
 534         case OP_VCALL2:
 535         case OP_VCALL2_REG:
 536         case OP_VCALL2_MEMBASE:
 537         case OP_VOIDCALL:
 538         case OP_VOIDCALL_MEMBASE:
 539         case OP_VOIDCALLVIRT: {
 540                 MonoCallInst *call = (MonoCallInst*)ins;
 541                 GSList *list;
 542
 543                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 544                         /*
 545                          * These are lowered opcodes, but they are in the .md files since the old
 546                          * JIT passes them to backends.
 547                          */
 548                         if (ins->dreg != -1)
 549                                 printf (" R%d <-", ins->dreg);
 550                 }
 551
 552                 if (call->method) {
 553                         char *full_name = mono_method_full_name (call->method, TRUE);
 554                         printf (" [%s]", full_name);
 555                         g_free (full_name);
 556                 } else if (call->fptr) {
 557                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 558                         if (info)
 559                                 printf (" [%s]", info->name);
 560                 }
 561
 562                 list = call->out_ireg_args;
 563                 while (list) {
 564                         guint32 regpair;
 565                         int reg, hreg;
 566
 567                         regpair = (guint32)(gssize)(list->data);
 568                         hreg = regpair >> 24;
 569                         reg = regpair & 0xffffff;
 570
 571                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 572
 573                         list = g_slist_next (list);
 574                 }
 575                 break;
 576         }
 577         case OP_BR:
 578         case OP_CALL_HANDLER:
 579                 printf (" [B%d]", ins->inst_target_bb->block_num);
 580                 break;
 581         case OP_IBNE_UN:
 582         case OP_IBEQ:
 583         case OP_IBLT:
 584         case OP_IBLT_UN:
 585         case OP_IBGT:
 586         case OP_IBGT_UN:
 587         case OP_IBGE:
 588         case OP_IBGE_UN:
 589         case OP_IBLE:
 590         case OP_IBLE_UN:
 591         case OP_LBNE_UN:
 592         case OP_LBEQ:
 593         case OP_LBLT:
 594         case OP_LBLT_UN:
 595         case OP_LBGT:
 596         case OP_LBGT_UN:
 597         case OP_LBGE:
 598         case OP_LBGE_UN:
 599         case OP_LBLE:
 600         case OP_LBLE_UN:
 601                 if (!ins->inst_false_bb)
 602                         printf (" [B%d]", ins->inst_true_bb->block_num);
 603                 else
 604                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 605                 break;
 606         case OP_LIVERANGE_START:
 607         case OP_LIVERANGE_END:
 608         case OP_GC_LIVENESS_DEF:
 609         case OP_GC_LIVENESS_USE:
 610                 printf (" R%d", (int)ins->inst_c1);
 611                 break;
 612         default:
 613                 break;
 614         }
 615
 616         if (spec [MONO_INST_CLOB])
 617                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 618         printf ("\n");
 619 }
 620
 621 static void
 622 print_regtrack (RegTrack *t, int num)
 623 {
 624         int i;
 625         char buf [32];
 626         const char *r;
 627
 628         for (i = 0; i < num; ++i) {
 629                 if (!t [i].born_in)
 630                         continue;
 631                 if (i >= MONO_MAX_IREGS) {
 632                         g_snprintf (buf, sizeof(buf), "R%d", i);
 633                         r = buf;
 634                 } else
 635                         r = mono_arch_regname (i);
 636                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 637         }
 638 }
 639 #else
 640 void
 641 mono_print_ins_index (int i, MonoInst *ins)
 642 {
 643 }
 644 #endif /* DISABLE_LOGGING */
 645
 646 void
 647 mono_print_ins (MonoInst *ins)
 648 {
 649         mono_print_ins_index (-1, ins);
 650 }
 651
 652 static inline void
 653 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 654 {
 655         /*
 656          * If this function is called multiple times, the new instructions are inserted
 657          * in the proper order.
 658          */
 659         mono_bblock_insert_before_ins (bb, ins, to_insert);
 660 }
 661
 662 static inline void
 663 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 664 {
 665         /*
 666          * If this function is called multiple times, the new instructions are inserted in
 667          * proper order.
 668          */
 669         mono_bblock_insert_after_ins (bb, *last, to_insert);
 670
 671         *last = to_insert;
 672 }
 673
 674 /*
 675  * Force the spilling of the variable in the symbolic register 'reg', and free
 676  * the hreg it was assigned to.
 677  */
 678 static void
 679 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 680 {
 681         MonoInst *load;
 682         int i, sel, spill;
 683         int *symbolic;
 684         MonoRegState *rs = cfg->rs;
 685
 686         symbolic = rs->symbolic [bank];
 687         sel = rs->vassign [reg];
 688
 689         /* the vreg we need to spill lives in another logical reg bank */
 690         bank = translate_bank (cfg->rs, bank, sel);
 691
 692         /*i = rs->isymbolic [sel];
 693         g_assert (i == reg);*/
 694         i = reg;
 695         spill = ++cfg->spill_count;
 696         rs->vassign [i] = -spill - 1;
 697         if (G_UNLIKELY (bank))
 698                 mono_regstate_free_general (rs, sel, bank);
 699         else
 700                 mono_regstate_free_int (rs, sel);
 701         /* we need to create a spill var and insert a load to sel after the current instruction */
 702         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 703         load->dreg = sel;
 704         load->inst_basereg = cfg->frame_reg;
 705         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 706         insert_after_ins (bb, ins, last, load);
 707         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 708         if (G_UNLIKELY (bank))
 709                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 710         else
 711                 i = mono_regstate_alloc_int (rs, regmask (sel));
 712         g_assert (i == sel);
 713
 714         if (G_UNLIKELY (bank))
 715                 mono_regstate_free_general (rs, sel, bank);
 716         else
 717                 mono_regstate_free_int (rs, sel);
 718 }
 719
 720 /* This isn't defined on older glib versions and on some platforms */
 721 #ifndef G_GUINT64_FORMAT
 722 #define G_GUINT64_FORMAT "ul"
 723 #endif
 724
 725 static int
 726 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 727 {
 728         MonoInst *load;
 729         int i, sel, spill, num_sregs;
 730         int sregs [MONO_MAX_SRC_REGS];
 731         int *symbolic;
 732         MonoRegState *rs = cfg->rs;
 733
 734         symbolic = rs->symbolic [bank];
 735
 736         g_assert (bank < MONO_NUM_REGBANKS);
 737
 738         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 739         /* exclude the registers in the current instruction */
 740         num_sregs = mono_inst_get_src_registers (ins, sregs);
 741         for (i = 0; i < num_sregs; ++i) {
 742                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 743                         if (is_soft_reg (sregs [i], bank))
 744                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 745                         else
 746                                 regmask &= ~ (regmask (sregs [i]));
 747                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 748                 }
 749         }
 750         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 751                 regmask &= ~ (regmask (ins->dreg));
 752                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 753         }
 754
 755         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 756         g_assert (regmask); /* need at least a register we can free */
 757         sel = 0;
 758         /* we should track prev_use and spill the register that's farther */
 759         if (G_UNLIKELY (bank)) {
 760                 for (i = 0; i < regbank_size [bank]; ++i) {
 761                         if (regmask & (regmask (i))) {
 762                                 sel = i;
 763
 764                                 /* the vreg we need to load lives in another logical bank */
 765                                 bank = translate_bank (cfg->rs, bank, sel);
 766
 767                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 768                                 break;
 769                         }
 770                 }
 771
 772                 i = rs->symbolic [bank] [sel];
 773                 spill = ++cfg->spill_count;
 774                 rs->vassign [i] = -spill - 1;
 775                 mono_regstate_free_general (rs, sel, bank);
 776         }
 777         else {
 778                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 779                         if (regmask & (regmask (i))) {
 780                                 sel = i;
 781                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 782                                 break;
 783                         }
 784                 }
 785
 786                 i = rs->isymbolic [sel];
 787                 spill = ++cfg->spill_count;
 788                 rs->vassign [i] = -spill - 1;
 789                 mono_regstate_free_int (rs, sel);
 790         }
 791
 792         /* we need to create a spill var and insert a load to sel after the current instruction */
 793         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 794         load->dreg = sel;
 795         load->inst_basereg = cfg->frame_reg;
 796         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 797         insert_after_ins (bb, ins, last, load);
 798         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 799         if (G_UNLIKELY (bank))
 800                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 801         else
 802                 i = mono_regstate_alloc_int (rs, regmask (sel));
 803         g_assert (i == sel);
 804
 805         return sel;
 806 }
 807
 808 /*
 809  * free_up_hreg:
 810  *
 811  *   Free up the hreg HREG by spilling the vreg allocated to it.
 812  */
 813 static void
 814 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 815 {
 816         if (G_UNLIKELY (bank)) {
 817                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 818                         bank = translate_bank (cfg->rs, bank, hreg);
 819                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 820                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 821                 }
 822         }
 823         else {
 824                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 825                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 826                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 827                 }
 828         }
 829 }
 830
 831 static MonoInst*
 832 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 833 {
 834         MonoInst *copy;
 835
 836         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 837
 838         copy->dreg = dest;
 839         copy->sreg1 = src;
 840         copy->cil_code = ip;
 841         if (ins) {
 842                 mono_bblock_insert_after_ins (bb, ins, copy);
 843                 *last = copy;
 844         }
 845         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 846         return copy;
 847 }
 848
 849 static MonoInst*
 850 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 851 {
 852         MonoInst *store;
 853         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 854         store->sreg1 = reg;
 855         store->inst_destbasereg = cfg->frame_reg;
 856         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 857         if (ins) {
 858                 mono_bblock_insert_after_ins (bb, ins, store);
 859                 *last = store;
 860         }
 861         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 862         return store;
 863 }
 864
 865 /* flags used in reginfo->flags */
 866 enum {
 867         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 868         MONO_FP_NEEDS_SPILL                     = regmask (1),
 869         MONO_FP_NEEDS_LOAD                      = regmask (2)
 870 };
 871
 872 static inline int
 873 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 874 {
 875         int val;
 876
 877         if (info && info->preferred_mask) {
 878                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 879                 if (val >= 0) {
 880                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 881                         return val;
 882                 }
 883         }
 884
 885         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 886         if (val < 0)
 887                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 888
 889         return val;
 890 }
 891
 892 static inline int
 893 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 894 {
 895         int val;
 896
 897         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 898
 899         if (val < 0)
 900                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 901
 902         return val;
 903 }
 904
 905 static inline int
 906 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 907 {
 908         if (G_UNLIKELY (bank))
 909                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 910         else
 911                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 912 }
 913
 914 static inline void
 915 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 916 {
 917         if (G_UNLIKELY (bank)) {
 918                 int mirrored_bank;
 919
 920                 g_assert (reg >= regbank_size [bank]);
 921                 g_assert (hreg < regbank_size [bank]);
 922                 g_assert (! is_global_freg (hreg));
 923
 924                 rs->vassign [reg] = hreg;
 925                 rs->symbolic [bank] [hreg] = reg;
 926                 rs->free_mask [bank] &= ~ (regmask (hreg));
 927
 928                 mirrored_bank = get_mirrored_bank (bank);
 929                 if (mirrored_bank == -1)
 930                         return;
 931
 932                 /* Make sure the other logical reg bank that this bank shares
 933                  * a single hard reg bank knows that this hard reg is not free.
 934                  */
 935                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 936
 937                 /* Mark the other logical bank that the this bank shares
 938                  * a single hard reg bank with as mirrored.
 939                  */
 940                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
 941
 942         }
 943         else {
 944                 g_assert (reg >= MONO_MAX_IREGS);
 945                 g_assert (hreg < MONO_MAX_IREGS);
 946 #ifndef TARGET_ARM
 947                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 948                 g_assert (! is_global_ireg (hreg));
 949 #endif
 950
 951                 rs->vassign [reg] = hreg;
 952                 rs->isymbolic [hreg] = reg;
 953                 rs->ifree_mask &= ~ (regmask (hreg));
 954         }
 955 }
 956
 957 static inline regmask_t
 958 get_callee_mask (const char spec)
 959 {
 960         if (G_UNLIKELY (reg_bank (spec)))
 961                 return regbank_callee_regs [reg_bank (spec)];
 962         return MONO_ARCH_CALLEE_REGS;
 963 }
 964
 965 static gint8 desc_to_fixed_reg [256];
 966 static gboolean desc_to_fixed_reg_inited = FALSE;
 967
 968 #ifndef DISABLE_JIT
 969
 970 /*
 971  * Local register allocation.
 972  * We first scan the list of instructions and we save the liveness info of
 973  * each register (when the register is first used, when it's value is set etc.).
 974  * We also reverse the list of instructions because assigning registers backwards allows
 975  * for more tricks to be used.
 976  */
 977 void
 978 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 979 {
 980         MonoInst *ins, *prev, *last;
 981         MonoInst **tmp;
 982         MonoRegState *rs = cfg->rs;
 983         int i, j, val, max;
 984         RegTrack *reginfo;
 985         const char *spec;
 986         unsigned char spec_src1, spec_dest;
 987         int bank = 0;
 988 #if MONO_ARCH_USE_FPSTACK
 989         gboolean has_fp = FALSE;
 990         int fpstack [8];
 991         int sp = 0;
 992 #endif
 993         int num_sregs;
 994         int sregs [MONO_MAX_SRC_REGS];
 995
 996         if (!bb->code)
 997                 return;
 998
 999         if (!desc_to_fixed_reg_inited) {
1000                 for (i = 0; i < 256; ++i)
1001                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1002                 desc_to_fixed_reg_inited = TRUE;
1003
1004                 /* Validate the cpu description against the info in mini-ops.h */
1005 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1006                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1007                         const char *ispec;
1008
1009                         spec = ins_get_spec (i);
1010                         ispec = INS_INFO (i);
1011
1012                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1013                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1014                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1015                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1016                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1017                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1018                 }
1019 #endif
1020         }
1021
1022         rs->next_vreg = bb->max_vreg;
1023         mono_regstate_assign (rs);
1024
1025         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1026         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1027                 rs->free_mask [i] = regbank_callee_regs [i];
1028
1029         max = rs->next_vreg;
1030
1031         if (cfg->reginfo && cfg->reginfo_len < max)
1032                 cfg->reginfo = NULL;
1033
1034         reginfo = cfg->reginfo;
1035         if (!reginfo) {
1036                 cfg->reginfo_len = MAX (1024, max * 2);
1037                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1038         }
1039         else
1040                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1041
1042         if (cfg->verbose_level > 1) {
1043                 /* print_regtrack reads the info of all variables */
1044                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1045         }
1046
1047         /*
1048          * For large methods, next_vreg can be very large, so g_malloc0 time can
1049          * be prohibitive. So we manually init the reginfo entries used by the
1050          * bblock.
1051          */
1052         for (ins = bb->code; ins; ins = ins->next) {
1053                 spec = ins_get_spec (ins->opcode);
1054
1055                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1056                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1057 #if SIZEOF_REGISTER == 4
1058                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1059                                 /**
1060                                  * In the new IR, the two vregs of the regpair do not alias the
1061                                  * original long vreg. shift the vreg here so the rest of the
1062                                  * allocator doesn't have to care about it.
1063                                  */
1064                                 ins->dreg ++;
1065                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1066                         }
1067 #endif
1068                 }
1069
1070                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1071                 for (j = 0; j < num_sregs; ++j) {
1072                         g_assert (sregs [j] != -1);
1073                         if (sregs [j] < max) {
1074                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1075 #if SIZEOF_REGISTER == 4
1076                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1077                                         sregs [j]++;
1078                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1079                                 }
1080 #endif
1081                         }
1082                 }
1083                 mono_inst_set_src_registers (ins, sregs);
1084         }
1085
1086         /*if (cfg->opt & MONO_OPT_COPYPROP)
1087                 local_copy_prop (cfg, ins);*/
1088
1089         i = 1;
1090         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1091         /* forward pass on the instructions to collect register liveness info */
1092         MONO_BB_FOR_EACH_INS (bb, ins) {
1093                 spec = ins_get_spec (ins->opcode);
1094                 spec_dest = spec [MONO_INST_DEST];
1095
1096                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1097                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1098                 }
1099
1100                 DEBUG (mono_print_ins_index (i, ins));
1101
1102                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1103
1104 #if MONO_ARCH_USE_FPSTACK
1105                 if (dreg_is_fp (spec)) {
1106                         has_fp = TRUE;
1107                 } else {
1108                         for (j = 0; j < num_sregs; ++j) {
1109                                 if (sreg_is_fp (j, spec))
1110                                         has_fp = TRUE;
1111                         }
1112                 }
1113 #endif
1114
1115                 for (j = 0; j < num_sregs; ++j) {
1116                         int sreg = sregs [j];
1117                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1118                         if (sreg_spec) {
1119                                 bank = sreg_bank (j, spec);
1120                                 g_assert (sreg != -1);
1121                                 if (is_soft_reg (sreg, bank))
1122                                         /* This means the vreg is not local to this bb */
1123                                         g_assert (reginfo [sreg].born_in > 0);
1124                                 rs->vassign [sreg] = -1;
1125                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1126                                 //reginfo [ins->sreg2].last_use = i;
1127                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1128                                         /* The virtual register is allocated sequentially */
1129                                         rs->vassign [sreg + 1] = -1;
1130                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1131                                         //reginfo [ins->sreg2 + 1].last_use = i;
1132                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1133                                                 reginfo [sreg + 1].born_in = i;
1134                                 }
1135                         } else {
1136                                 sregs [j] = -1;
1137                         }
1138                 }
1139                 mono_inst_set_src_registers (ins, sregs);
1140
1141                 if (spec_dest) {
1142                         int dest_dreg;
1143
1144                         bank = dreg_bank (spec);
1145                         if (spec_dest != 'b') /* it's not just a base register */
1146                                 reginfo [ins->dreg].killed_in = i;
1147                         g_assert (ins->dreg != -1);
1148                         rs->vassign [ins->dreg] = -1;
1149                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1150                         //reginfo [ins->dreg].last_use = i;
1151                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1152                                 reginfo [ins->dreg].born_in = i;
1153
1154                         dest_dreg = desc_to_fixed_reg [spec_dest];
1155                         if (dest_dreg != -1)
1156                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1157
1158 #ifdef MONO_ARCH_INST_FIXED_MASK
1159                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1160 #endif
1161
1162                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1163                                 /* The virtual register is allocated sequentially */
1164                                 rs->vassign [ins->dreg + 1] = -1;
1165                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1166                                 //reginfo [ins->dreg + 1].last_use = i;
1167                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1168                                         reginfo [ins->dreg + 1].born_in = i;
1169                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1170                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1171                         }
1172                 } else {
1173                         ins->dreg = -1;
1174                 }
1175
1176                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1177                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1178
1179                         MonoCallInst *call = (MonoCallInst*)ins;
1180                         GSList *list;
1181
1182                         list = call->out_ireg_args;
1183                         if (list) {
1184                                 while (list) {
1185                                         guint32 regpair;
1186                                         int reg, hreg;
1187
1188                                         regpair = (guint32)(gssize)(list->data);
1189                                         hreg = regpair >> 24;
1190                                         reg = regpair & 0xffffff;
1191
1192                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1193                                         //reginfo [reg].last_use = i;
1194
1195                                         list = g_slist_next (list);
1196                                 }
1197                         }
1198
1199                         list = call->out_freg_args;
1200                         if (list) {
1201                                 while (list) {
1202                                         guint32 regpair;
1203                                         int reg, hreg;
1204
1205                                         regpair = (guint32)(gssize)(list->data);
1206                                         hreg = regpair >> 24;
1207                                         reg = regpair & 0xffffff;
1208
1209                                         list = g_slist_next (list);
1210                                 }
1211                         }
1212                 }
1213
1214                 ++i;
1215         }
1216
1217         tmp = &last;
1218
1219         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1220         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1221                 int prev_dreg, clob_dreg;
1222                 int dest_dreg, clob_reg;
1223                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1224                 int dreg_high, sreg1_high;
1225                 regmask_t dreg_mask, mask;
1226                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1227                 regmask_t dreg_fixed_mask;
1228                 const unsigned char *ip;
1229                 --i;
1230                 spec = ins_get_spec (ins->opcode);
1231                 spec_src1 = spec [MONO_INST_SRC1];
1232                 spec_dest = spec [MONO_INST_DEST];
1233                 prev_dreg = -1;
1234                 clob_dreg = -1;
1235                 clob_reg = -1;
1236                 dest_dreg = -1;
1237                 dreg_high = -1;
1238                 sreg1_high = -1;
1239                 dreg_mask = get_callee_mask (spec_dest);
1240                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1241                         prev_sregs [j] = -1;
1242                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1243                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1244 #ifdef MONO_ARCH_INST_FIXED_MASK
1245                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1246 #else
1247                         sreg_fixed_masks [j] = 0;
1248 #endif
1249                 }
1250
1251                 DEBUG (printf ("processing:"));
1252                 DEBUG (mono_print_ins_index (i, ins));
1253
1254                 ip = ins->cil_code;
1255
1256                 last = ins;
1257
1258                 /*
1259                  * FIXED REGS
1260                  */
1261                 dest_dreg = desc_to_fixed_reg [spec_dest];
1262                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1263                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1264
1265 #ifdef MONO_ARCH_INST_FIXED_MASK
1266                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1267 #else
1268                 dreg_fixed_mask = 0;
1269 #endif
1270
1271                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1272
1273                 /*
1274                  * TRACK FIXED SREG2, 3, ...
1275                  */
1276                 for (j = 1; j < num_sregs; ++j) {
1277                         int sreg = sregs [j];
1278                         int dest_sreg = dest_sregs [j];
1279
1280                         if (dest_sreg == -1)
1281                                 continue;
1282
1283                         if (j == 2) {
1284                                 int k;
1285
1286                                 /*
1287                                  * CAS.
1288                                  * We need to special case this, since on x86, there are only 3
1289                                  * free registers, and the code below assigns one of them to
1290                                  * sreg, so we can run out of registers when trying to assign
1291                                  * dreg. Instead, we just set up the register masks, and let the
1292                                  * normal sreg2 assignment code handle this. It would be nice to
1293                                  * do this for all the fixed reg cases too, but there is too much
1294                                  * risk of breakage.
1295                                  */
1296
1297                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1298                                 sreg_masks [j] = regmask (dest_sreg);
1299                                 for (k = 0; k < num_sregs; ++k) {
1300                                         if (k != j)
1301                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1302                                 }
1303
1304                                 /*
1305                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1306                                  */
1307                                 for (k = 0; k < num_sregs; ++k) {
1308                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1309                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1310                                 }
1311
1312                                 /*
1313                                  * We can also run out of registers while processing sreg2 if sreg3 is
1314                                  * assigned to another hreg, so spill sreg3 now.
1315                                  */
1316                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1317                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1318                                 }
1319                                 continue;
1320                         }
1321
1322                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1323                                 if (is_global_ireg (sreg)) {
1324                                         int k;
1325                                         /* Argument already in hard reg, need to copy */
1326                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1327                                         insert_before_ins (bb, ins, copy);
1328                                         for (k = 0; k < num_sregs; ++k) {
1329                                                 if (k != j)
1330                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1331                                         }
1332                                 } else {
1333                                         val = rs->vassign [sreg];
1334                                         if (val == -1) {
1335                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1336                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1337                                         } else if (val < -1) {
1338                                                 /* FIXME: */
1339                                                 g_assert_not_reached ();
1340                                         } else {
1341                                                 /* Argument already in hard reg, need to copy */
1342                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1343                                                 int k;
1344
1345                                                 insert_before_ins (bb, ins, copy);
1346                                                 for (k = 0; k < num_sregs; ++k) {
1347                                                         if (k != j)
1348                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1349                                                 }
1350                                                 /*
1351                                                  * Prevent the dreg from being allocate to dest_sreg
1352                                                  * too, since it could force sreg1 to be allocated to
1353                                                  * the same reg on x86.
1354                                                  */
1355                                                 dreg_mask &= ~ (regmask (dest_sreg));
1356                                         }
1357                                 }
1358                         } else {
1359                                 gboolean need_spill = TRUE;
1360                                 gboolean need_assign = TRUE;
1361                                 int k;
1362
1363                                 dreg_mask &= ~ (regmask (dest_sreg));
1364                                 for (k = 0; k < num_sregs; ++k) {
1365                                         if (k != j)
1366                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1367                                 }
1368
1369                                 /*
1370                                  * First check if dreg is assigned to dest_sreg2, since we
1371                                  * can't spill a dreg.
1372                                  */
1373                                 if (spec [MONO_INST_DEST])
1374                                         val = rs->vassign [ins->dreg];
1375                                 else
1376                                         val = -1;
1377                                 if (val == dest_sreg && ins->dreg != sreg) {
1378                                         /*
1379                                          * the destination register is already assigned to
1380                                          * dest_sreg2: we need to allocate another register for it
1381                                          * and then copy from this to dest_sreg2.
1382                                          */
1383                                         int new_dest;
1384                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1385                                         g_assert (new_dest >= 0);
1386                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1387
1388                                         prev_dreg = ins->dreg;
1389                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1390                                         clob_dreg = ins->dreg;
1391                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1392                                         mono_regstate_free_int (rs, dest_sreg);
1393                                         need_spill = FALSE;
1394                                 }
1395
1396                                 if (is_global_ireg (sreg)) {
1397                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1398                                         insert_before_ins (bb, ins, copy);
1399                                         need_assign = FALSE;
1400                                 }
1401                                 else {
1402                                         val = rs->vassign [sreg];
1403                                         if (val == dest_sreg) {
1404                                                 /* sreg2 is already assigned to the correct register */
1405                                                 need_spill = FALSE;
1406                                         } else if (val < -1) {
1407                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1408                                         } else if (val >= 0) {
1409                                                 /* sreg2 already assigned to another register */
1410                                                 /*
1411                                                  * We couldn't emit a copy from val to dest_sreg2, because
1412                                                  * val might be spilled later while processing this
1413                                                  * instruction. So we spill sreg2 so it can be allocated to
1414                                                  * dest_sreg2.
1415                                                  */
1416                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1417                                         }
1418                                 }
1419
1420                                 if (need_spill) {
1421                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1422                                 }
1423
1424                                 if (need_assign) {
1425                                         if (rs->vassign [sreg] < -1) {
1426                                                 MonoInst *store;
1427                                                 int spill;
1428
1429                                                 /* Need to emit a spill store */
1430                                                 spill = - rs->vassign [sreg] - 1;
1431                                                 store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
1432                                                 insert_before_ins (bb, ins, store);
1433                                         }
1434                                         /* force-set sreg2 */
1435                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1436                                 }
1437                         }
1438                         sregs [j] = dest_sreg;
1439                 }
1440                 mono_inst_set_src_registers (ins, sregs);
1441
1442                 /*
1443                  * TRACK DREG
1444                  */
1445                 bank = dreg_bank (spec);
1446                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1447                         prev_dreg = ins->dreg;
1448                 }
1449
1450                 if (spec_dest == 'b') {
1451                         /*
1452                          * The dest reg is read by the instruction, not written, so
1453                          * avoid allocating sreg1/sreg2 to the same reg.
1454                          */
1455                         if (dest_sregs [0] != -1)
1456                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1457                         for (j = 1; j < num_sregs; ++j) {
1458                                 if (dest_sregs [j] != -1)
1459                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1460                         }
1461
1462                         val = rs->vassign [ins->dreg];
1463                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1464                                 /* DREG is already allocated to a register needed for sreg1 */
1465                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1466                         }
1467                 }
1468
1469                 /*
1470                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1471                  * various complex situations.
1472                  */
1473                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1474                         guint32 dreg2, dest_dreg2;
1475
1476                         g_assert (is_soft_reg (ins->dreg, bank));
1477
1478                         if (dest_dreg != -1) {
1479                                 if (rs->vassign [ins->dreg] != dest_dreg)
1480                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1481
1482                                 dreg2 = ins->dreg + 1;
1483                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1484                                 if (dest_dreg2 != -1) {
1485                                         if (rs->vassign [dreg2] != dest_dreg2)
1486                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1487                                 }
1488                         }
1489                 }
1490
1491                 if (dreg_fixed_mask) {
1492                         g_assert (!bank);
1493                         if (is_global_ireg (ins->dreg)) {
1494                                 /*
1495                                  * The argument is already in a hard reg, but that reg is
1496                                  * not usable by this instruction, so allocate a new one.
1497                                  */
1498                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1499                                 if (val < 0)
1500                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1501                                 mono_regstate_free_int (rs, val);
1502                                 dest_dreg = val;
1503
1504                                 /* Fall through */
1505                         }
1506                         else
1507                                 dreg_mask &= dreg_fixed_mask;
1508                 }
1509
1510                 if (is_soft_reg (ins->dreg, bank)) {
1511                         val = rs->vassign [ins->dreg];
1512
1513                         if (val < 0) {
1514                                 int spill = 0;
1515                                 if (val < -1) {
1516                                         /* the register gets spilled after this inst */
1517                                         spill = -val -1;
1518                                 }
1519                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1520                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1521                                 if (spill)
1522                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1523                         }
1524
1525                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1526                         ins->dreg = val;
1527                 }
1528
1529                 /* Handle regpairs */
1530                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1531                         int reg2 = prev_dreg + 1;
1532
1533                         g_assert (!bank);
1534                         g_assert (prev_dreg > -1);
1535                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1536                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1537 #ifdef TARGET_X86
1538                         /* bug #80489 */
1539                         mask &= ~regmask (X86_ECX);
1540 #endif
1541                         val = rs->vassign [reg2];
1542                         if (val < 0) {
1543                                 int spill = 0;
1544                                 if (val < -1) {
1545                                         /* the register gets spilled after this inst */
1546                                         spill = -val -1;
1547                                 }
1548                                 val = mono_regstate_alloc_int (rs, mask);
1549                                 if (val < 0)
1550                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1551                                 if (spill)
1552                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1553                         }
1554                         else {
1555                                 if (! (mask & (regmask (val)))) {
1556                                         val = mono_regstate_alloc_int (rs, mask);
1557                                         if (val < 0)
1558                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1559
1560                                         /* Reallocate hreg to the correct register */
1561                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1562
1563                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1564                                 }
1565                         }
1566
1567                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1568                         assign_reg (cfg, rs, reg2, val, bank);
1569
1570                         dreg_high = val;
1571                         ins->backend.reg3 = val;
1572
1573                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1574                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1575                                 mono_regstate_free_int (rs, val);
1576                         }
1577                 }
1578
1579                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1580                         /*
1581                          * In theory, we could free up the hreg even if the vreg is alive,
1582                          * but branches inside bblocks force us to assign the same hreg
1583                          * to a vreg every time it is encountered.
1584                          */
1585                         int dreg = rs->vassign [prev_dreg];
1586                         g_assert (dreg >= 0);
1587                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1588                         if (G_UNLIKELY (bank))
1589                                 mono_regstate_free_general (rs, dreg, bank);
1590                         else
1591                                 mono_regstate_free_int (rs, dreg);
1592                         rs->vassign [prev_dreg] = -1;
1593                 }
1594
1595                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1596                         /* this instruction only outputs to dest_dreg, need to copy */
1597                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1598                         ins->dreg = dest_dreg;
1599
1600                         if (G_UNLIKELY (bank)) {
1601                                 /* the register we need to free up may be used in another logical regbank
1602                                  * so do a translate just in case.
1603                                  */
1604                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1605                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1606                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1607                         }
1608                         else {
1609                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1610                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1611                         }
1612                 }
1613
1614                 if (spec_dest == 'b') {
1615                         /*
1616                          * The dest reg is read by the instruction, not written, so
1617                          * avoid allocating sreg1/sreg2 to the same reg.
1618                          */
1619                         for (j = 0; j < num_sregs; ++j)
1620                                 if (!sreg_bank (j, spec))
1621                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1622                 }
1623
1624                 /*
1625                  * TRACK CLOBBERING
1626                  */
1627                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1628                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1629                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1630                 }
1631
1632                 if (spec [MONO_INST_CLOB] == 'c') {
1633                         int j, s, dreg, dreg2, cur_bank;
1634                         guint64 clob_mask;
1635
1636                         clob_mask = MONO_ARCH_CALLEE_REGS;
1637
1638                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1639                                 /*
1640                                  * Need to avoid spilling the dreg since the dreg is not really
1641                                  * clobbered by the call.
1642                                  */
1643                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1644                                         dreg = rs->vassign [prev_dreg];
1645                                 else
1646                                         dreg = -1;
1647
1648                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1649                                         dreg2 = rs->vassign [prev_dreg + 1];
1650                                 else
1651                                         dreg2 = -1;
1652
1653                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1654                                         s = regmask (j);
1655                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1656                                                 if ((j != dreg) && (j != dreg2))
1657                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1658                                                 else if (rs->isymbolic [j])
1659                                                         /* The hreg is assigned to the dreg of this instruction */
1660                                                         rs->vassign [rs->isymbolic [j]] = -1;
1661                                                 mono_regstate_free_int (rs, j);
1662                                         }
1663                                 }
1664                         }
1665
1666                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1667                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1668                                         clob_mask = regbank_callee_regs [cur_bank];
1669                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1670                                                 dreg = rs->vassign [prev_dreg];
1671                                         else
1672                                                 dreg = -1;
1673
1674                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1675
1676                                                 /* we are looping though the banks in the outer loop
1677                                                  * so, we don't need to deal with mirrored hregs
1678                                                  * because we will get them in one of the other bank passes.
1679                                                  */
1680                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1681                                                         continue;
1682
1683                                                 s = regmask (j);
1684                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1685                                                         if (j != dreg)
1686                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1687                                                         else if (rs->symbolic [cur_bank] [j])
1688                                                                 /* The hreg is assigned to the dreg of this instruction */
1689                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1690                                                         mono_regstate_free_general (rs, j, cur_bank);
1691                                                 }
1692                                         }
1693                                 }
1694                         }
1695                 }
1696
1697                 /*
1698                  * TRACK ARGUMENT REGS
1699                  */
1700                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1701                         MonoCallInst *call = (MonoCallInst*)ins;
1702                         GSList *list;
1703
1704                         /*
1705                          * This needs to be done before assigning sreg1, so sreg1 will
1706                          * not be assigned one of the argument regs.
1707                          */
1708
1709                         /*
1710                          * Assign all registers in call->out_reg_args to the proper
1711                          * argument registers.
1712                          */
1713
1714                         list = call->out_ireg_args;
1715                         if (list) {
1716                                 while (list) {
1717                                         guint32 regpair;
1718                                         int reg, hreg;
1719
1720                                         regpair = (guint32)(gssize)(list->data);
1721                                         hreg = regpair >> 24;
1722                                         reg = regpair & 0xffffff;
1723
1724                                         assign_reg (cfg, rs, reg, hreg, 0);
1725
1726                                         sreg_masks [0] &= ~(regmask (hreg));
1727
1728                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1729
1730                                         list = g_slist_next (list);
1731                                 }
1732                         }
1733
1734                         list = call->out_freg_args;
1735                         if (list) {
1736                                 while (list) {
1737                                         guint32 regpair;
1738                                         int reg, hreg;
1739
1740                                         regpair = (guint32)(gssize)(list->data);
1741                                         hreg = regpair >> 24;
1742                                         reg = regpair & 0xffffff;
1743
1744                                         assign_reg (cfg, rs, reg, hreg, 1);
1745
1746                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1747
1748                                         list = g_slist_next (list);
1749                                 }
1750                         }
1751                 }
1752
1753                 /*
1754                  * TRACK SREG1
1755                  */
1756                 bank = sreg1_bank (spec);
1757                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1758                         int sreg1 = sregs [0];
1759                         int dest_sreg1 = dest_sregs [0];
1760
1761                         g_assert (is_soft_reg (sreg1, bank));
1762
1763                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1764                         if (dest_sreg1 != -1)
1765                                 g_assert (dest_sreg1 == ins->dreg);
1766                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1767                         g_assert (val >= 0);
1768
1769                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1770                                 // FIXME:
1771                                 g_assert_not_reached ();
1772
1773                         assign_reg (cfg, rs, sreg1, val, bank);
1774
1775                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1776
1777                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1778                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1779                         g_assert (val >= 0);
1780
1781                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1782                                 // FIXME:
1783                                 g_assert_not_reached ();
1784
1785                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1786
1787                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1788
1789                         /* Skip rest of this section */
1790                         dest_sregs [0] = -1;
1791                 }
1792
1793                 if (sreg_fixed_masks [0]) {
1794                         g_assert (!bank);
1795                         if (is_global_ireg (sregs [0])) {
1796                                 /*
1797                                  * The argument is already in a hard reg, but that reg is
1798                                  * not usable by this instruction, so allocate a new one.
1799                                  */
1800                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1801                                 if (val < 0)
1802                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1803                                 mono_regstate_free_int (rs, val);
1804                                 dest_sregs [0] = val;
1805
1806                                 /* Fall through to the dest_sreg1 != -1 case */
1807                         }
1808                         else
1809                                 sreg_masks [0] &= sreg_fixed_masks [0];
1810                 }
1811
1812                 if (dest_sregs [0] != -1) {
1813                         sreg_masks [0] = regmask (dest_sregs [0]);
1814
1815                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1816                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1817                         }
1818                         if (is_global_ireg (sregs [0])) {
1819                                 /* The argument is already in a hard reg, need to copy */
1820                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1821                                 insert_before_ins (bb, ins, copy);
1822                                 sregs [0] = dest_sregs [0];
1823                         }
1824                 }
1825
1826                 if (is_soft_reg (sregs [0], bank)) {
1827                         val = rs->vassign [sregs [0]];
1828                         prev_sregs [0] = sregs [0];
1829                         if (val < 0) {
1830                                 int spill = 0;
1831                                 if (val < -1) {
1832                                         /* the register gets spilled after this inst */
1833                                         spill = -val -1;
1834                                 }
1835
1836                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1837                                         /*
1838                                          * Allocate the same hreg to sreg1 as well so the
1839                                          * peephole can get rid of the move.
1840                                          */
1841                                         sreg_masks [0] = regmask (ins->dreg);
1842                                 }
1843
1844                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1845                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1846                                         sreg_masks [0] = regmask (ins->dreg);
1847
1848                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1849                                 assign_reg (cfg, rs, sregs [0], val, bank);
1850                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1851
1852                                 if (spill) {
1853                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
1854                                         /*
1855                                          * Need to insert before the instruction since it can
1856                                          * overwrite sreg1.
1857                                          */
1858                                         insert_before_ins (bb, ins, store);
1859                                 }
1860                         }
1861                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1862                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1863                                 insert_before_ins (bb, ins, copy);
1864                                 for (j = 1; j < num_sregs; ++j)
1865                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1866                                 val = dest_sregs [0];
1867                         }
1868
1869                         sregs [0] = val;
1870                 }
1871                 else {
1872                         prev_sregs [0] = -1;
1873                 }
1874                 mono_inst_set_src_registers (ins, sregs);
1875
1876                 for (j = 1; j < num_sregs; ++j)
1877                         sreg_masks [j] &= ~(regmask (sregs [0]));
1878
1879                 /* Handle the case when sreg1 is a regpair but dreg is not */
1880                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1881                         int reg2 = prev_sregs [0] + 1;
1882
1883                         g_assert (!bank);
1884                         g_assert (prev_sregs [0] > -1);
1885                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1886                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1887                         val = rs->vassign [reg2];
1888                         if (val < 0) {
1889                                 int spill = 0;
1890                                 if (val < -1) {
1891                                         /* the register gets spilled after this inst */
1892                                         spill = -val -1;
1893                                 }
1894                                 val = mono_regstate_alloc_int (rs, mask);
1895                                 if (val < 0)
1896                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1897                                 if (spill)
1898                                         g_assert_not_reached ();
1899                         }
1900                         else {
1901                                 if (! (mask & (regmask (val)))) {
1902                                         /* The vreg is already allocated to a wrong hreg */
1903                                         /* FIXME: */
1904                                         g_assert_not_reached ();
1905 #if 0
1906                                         val = mono_regstate_alloc_int (rs, mask);
1907                                         if (val < 0)
1908                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1909
1910                                         /* Reallocate hreg to the correct register */
1911                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1912
1913                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1914 #endif
1915                                 }
1916                         }
1917
1918                         sreg1_high = val;
1919                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1920                         assign_reg (cfg, rs, reg2, val, bank);
1921                 }
1922
1923                 /* Handle dreg==sreg1 */
1924                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1925                         MonoInst *sreg2_copy = NULL;
1926                         MonoInst *copy;
1927                         int bank = reg_bank (spec_src1);
1928
1929                         if (ins->dreg == sregs [1]) {
1930                                 /*
1931                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1932                                  * register for it.
1933                                  */
1934                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1935
1936                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1937                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1938                                 prev_sregs [1] = sregs [1] = reg2;
1939
1940                                 if (G_UNLIKELY (bank))
1941                                         mono_regstate_free_general (rs, reg2, bank);
1942                                 else
1943                                         mono_regstate_free_int (rs, reg2);
1944                         }
1945
1946                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1947                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1948                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1949                                         /* FIXME: */
1950                                         g_assert_not_reached ();
1951
1952                                 /*
1953                                  * sreg1 and dest are already allocated to the same regpair by the
1954                                  * SREG1 allocation code.
1955                                  */
1956                                 g_assert (sregs [0] == ins->dreg);
1957                                 g_assert (dreg_high == sreg1_high);
1958                         }
1959
1960                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
1961                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
1962                         insert_before_ins (bb, ins, copy);
1963
1964                         if (sreg2_copy)
1965                                 insert_before_ins (bb, copy, sreg2_copy);
1966
1967                         /*
1968                          * Need to prevent sreg2 to be allocated to sreg1, since that
1969                          * would screw up the previous copy.
1970                          */
1971                         sreg_masks [1] &= ~ (regmask (sregs [0]));
1972                         /* we set sreg1 to dest as well */
1973                         prev_sregs [0] = sregs [0] = ins->dreg;
1974                         sreg_masks [1] &= ~ (regmask (ins->dreg));
1975                 }
1976                 mono_inst_set_src_registers (ins, sregs);
1977
1978                 /*
1979                  * TRACK SREG2, 3, ...
1980                  */
1981                 for (j = 1; j < num_sregs; ++j) {
1982                         int k;
1983
1984                         bank = sreg_bank (j, spec);
1985                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
1986                                 g_assert_not_reached ();
1987
1988                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
1989                                 /*
1990                                  * Argument already in a global hard reg, copy it to the fixed reg, without
1991                                  * allocating it to the fixed reg.
1992                                  */
1993                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
1994                                 insert_before_ins (bb, ins, copy);
1995                                 sregs [j] = dest_sregs [j];
1996                         } else if (is_soft_reg (sregs [j], bank)) {
1997                                 val = rs->vassign [sregs [j]];
1998
1999                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2000                                         /*
2001                                          * The sreg is already allocated to a hreg, but not to the fixed
2002                                          * reg required by the instruction. Spill the sreg, so it can be
2003                                          * allocated to the fixed reg by the code below.
2004                                          */
2005                                         /* Currently, this code should only be hit for CAS */
2006                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2007                                         val = rs->vassign [sregs [j]];
2008                                 }
2009
2010                                 if (val < 0) {
2011                                         int spill = 0;
2012                                         if (val < -1) {
2013                                                 /* the register gets spilled after this inst */
2014                                                 spill = -val -1;
2015                                         }
2016                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2017                                         assign_reg (cfg, rs, sregs [j], val, bank);
2018                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2019                                         if (spill) {
2020                                                 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
2021                                                 /*
2022                                                  * Need to insert before the instruction since it can
2023                                                  * overwrite sreg2.
2024                                                  */
2025                                                 insert_before_ins (bb, ins, store);
2026                                         }
2027                                 }
2028                                 sregs [j] = val;
2029                                 for (k = j + 1; k < num_sregs; ++k)
2030                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2031                         }
2032                         else {
2033                                 prev_sregs [j] = -1;
2034                         }
2035                 }
2036                 mono_inst_set_src_registers (ins, sregs);
2037
2038                 /* Sanity check */
2039                 /* Do this only for CAS for now */
2040                 for (j = 1; j < num_sregs; ++j) {
2041                         int sreg = sregs [j];
2042                         int dest_sreg = dest_sregs [j];
2043
2044                         if (j == 2 && dest_sreg != -1) {
2045                                 int k;
2046
2047                                 g_assert (sreg == dest_sreg);
2048
2049                                 for (k = 0; k < num_sregs; ++k) {
2050                                         if (k != j)
2051                                                 g_assert (sregs [k] != dest_sreg);
2052                                 }
2053                         }
2054                 }
2055
2056                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2057                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2058                         mono_regstate_free_int (rs, ins->sreg1);
2059                 }
2060                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2061                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2062                         mono_regstate_free_int (rs, ins->sreg2);
2063                 }*/
2064
2065                 DEBUG (mono_print_ins_index (i, ins));
2066         }
2067
2068         // FIXME: Set MAX_FREGS to 8
2069         // FIXME: Optimize generated code
2070 #if MONO_ARCH_USE_FPSTACK
2071         /*
2072          * Make a forward pass over the code, simulating the fp stack, making sure the
2073          * arguments required by the fp opcodes are at the top of the stack.
2074          */
2075         if (has_fp) {
2076                 MonoInst *prev = NULL;
2077                 MonoInst *fxch;
2078                 int tmp;
2079
2080                 g_assert (num_sregs <= 2);
2081
2082                 for (ins = bb->code; ins; ins = ins->next) {
2083                         spec = ins_get_spec (ins->opcode);
2084
2085                         DEBUG (printf ("processing:"));
2086                         DEBUG (mono_print_ins_index (0, ins));
2087
2088                         if (ins->opcode == OP_FMOVE) {
2089                                 /* Do it by renaming the source to the destination on the stack */
2090                                 // FIXME: Is this correct ?
2091                                 for (i = 0; i < sp; ++i)
2092                                         if (fpstack [i] == ins->sreg1)
2093                                                 fpstack [i] = ins->dreg;
2094                                 prev = ins;
2095                                 continue;
2096                         }
2097
2098                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2099                                 /* Arg1 must be in %st(1) */
2100                                 g_assert (prev);
2101
2102                                 i = 0;
2103                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2104                                         i ++;
2105                                 g_assert (i < sp);
2106
2107                                 if (sp - 1 - i > 0) {
2108                                         /* First move it to %st(0) */
2109                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2110
2111                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2112                                         fxch->inst_imm = sp - 1 - i;
2113
2114                                         prev->next = fxch;
2115                                         fxch->next = ins;
2116                                         prev = fxch;
2117
2118                                         tmp = fpstack [sp - 1];
2119                                         fpstack [sp - 1] = fpstack [i];
2120                                         fpstack [i] = tmp;
2121                                 }
2122
2123                                 /* Then move it to %st(1) */
2124                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2125
2126                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2127                                 fxch->inst_imm = 1;
2128
2129                                 prev->next = fxch;
2130                                 fxch->next = ins;
2131                                 prev = fxch;
2132
2133                                 tmp = fpstack [sp - 1];
2134                                 fpstack [sp - 1] = fpstack [sp - 2];
2135                                 fpstack [sp - 2] = tmp;
2136                         }
2137
2138                         if (sreg2_is_fp (spec)) {
2139                                 g_assert (sp > 0);
2140
2141                                 if (fpstack [sp - 1] != ins->sreg2) {
2142                                         g_assert (prev);
2143
2144                                         i = 0;
2145                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2146                                                 i ++;
2147                                         g_assert (i < sp);
2148
2149                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2150
2151                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2152                                         fxch->inst_imm = sp - 1 - i;
2153
2154                                         prev->next = fxch;
2155                                         fxch->next = ins;
2156                                         prev = fxch;
2157
2158                                         tmp = fpstack [sp - 1];
2159                                         fpstack [sp - 1] = fpstack [i];
2160                                         fpstack [i] = tmp;
2161                                 }
2162
2163                                 sp --;
2164                         }
2165
2166                         if (sreg1_is_fp (spec)) {
2167                                 g_assert (sp > 0);
2168
2169                                 if (fpstack [sp - 1] != ins->sreg1) {
2170                                         g_assert (prev);
2171
2172                                         i = 0;
2173                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2174                                                 i ++;
2175                                         g_assert (i < sp);
2176
2177                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2178
2179                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2180                                         fxch->inst_imm = sp - 1 - i;
2181
2182                                         prev->next = fxch;
2183                                         fxch->next = ins;
2184                                         prev = fxch;
2185
2186                                         tmp = fpstack [sp - 1];
2187                                         fpstack [sp - 1] = fpstack [i];
2188                                         fpstack [i] = tmp;
2189                                 }
2190
2191                                 sp --;
2192                         }
2193
2194                         if (dreg_is_fp (spec)) {
2195                                 g_assert (sp < 8);
2196                                 fpstack [sp ++] = ins->dreg;
2197                         }
2198
2199                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2200                                 printf ("\t[");
2201                                 for (i = 0; i < sp; ++i)
2202                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2203                                 printf ("]\n");
2204                         }
2205
2206                         prev = ins;
2207                 }
2208
2209                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2210                         /* Remove remaining items from the fp stack */
2211                         /*
2212                          * These can remain for example as a result of a dead fmove like in
2213                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2214                          */
2215                         while (sp) {
2216                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2217                                 mono_add_ins_to_end (bb, ins);
2218                                 sp --;
2219                         }
2220                 }
2221         }
2222 #endif
2223 }
2224
2225 CompRelation
2226 mono_opcode_to_cond (int opcode)
2227 {
2228         switch (opcode) {
2229         case OP_CEQ:
2230         case OP_IBEQ:
2231         case OP_ICEQ:
2232         case OP_LBEQ:
2233         case OP_LCEQ:
2234         case OP_FBEQ:
2235         case OP_FCEQ:
2236         case OP_COND_EXC_EQ:
2237         case OP_COND_EXC_IEQ:
2238         case OP_CMOV_IEQ:
2239         case OP_CMOV_LEQ:
2240                 return CMP_EQ;
2241         case OP_IBNE_UN:
2242         case OP_LBNE_UN:
2243         case OP_FBNE_UN:
2244         case OP_COND_EXC_NE_UN:
2245         case OP_COND_EXC_INE_UN:
2246         case OP_CMOV_INE_UN:
2247         case OP_CMOV_LNE_UN:
2248                 return CMP_NE;
2249         case OP_IBLE:
2250         case OP_LBLE:
2251         case OP_FBLE:
2252         case OP_CMOV_ILE:
2253         case OP_CMOV_LLE:
2254                 return CMP_LE;
2255         case OP_IBGE:
2256         case OP_LBGE:
2257         case OP_FBGE:
2258         case OP_CMOV_IGE:
2259         case OP_CMOV_LGE:
2260                 return CMP_GE;
2261         case OP_CLT:
2262         case OP_IBLT:
2263         case OP_ICLT:
2264         case OP_LBLT:
2265         case OP_LCLT:
2266         case OP_FBLT:
2267         case OP_FCLT:
2268         case OP_COND_EXC_LT:
2269         case OP_COND_EXC_ILT:
2270         case OP_CMOV_ILT:
2271         case OP_CMOV_LLT:
2272                 return CMP_LT;
2273         case OP_CGT:
2274         case OP_IBGT:
2275         case OP_ICGT:
2276         case OP_LBGT:
2277         case OP_LCGT:
2278         case OP_FBGT:
2279         case OP_FCGT:
2280         case OP_COND_EXC_GT:
2281         case OP_COND_EXC_IGT:
2282         case OP_CMOV_IGT:
2283         case OP_CMOV_LGT:
2284                 return CMP_GT;
2285
2286         case OP_IBLE_UN:
2287         case OP_LBLE_UN:
2288         case OP_FBLE_UN:
2289         case OP_COND_EXC_LE_UN:
2290         case OP_COND_EXC_ILE_UN:
2291         case OP_CMOV_ILE_UN:
2292         case OP_CMOV_LLE_UN:
2293                 return CMP_LE_UN;
2294         case OP_IBGE_UN:
2295         case OP_LBGE_UN:
2296         case OP_FBGE_UN:
2297         case OP_CMOV_IGE_UN:
2298         case OP_CMOV_LGE_UN:
2299                 return CMP_GE_UN;
2300         case OP_CLT_UN:
2301         case OP_IBLT_UN:
2302         case OP_ICLT_UN:
2303         case OP_LBLT_UN:
2304         case OP_LCLT_UN:
2305         case OP_FBLT_UN:
2306         case OP_FCLT_UN:
2307         case OP_COND_EXC_LT_UN:
2308         case OP_COND_EXC_ILT_UN:
2309         case OP_CMOV_ILT_UN:
2310         case OP_CMOV_LLT_UN:
2311                 return CMP_LT_UN;
2312         case OP_CGT_UN:
2313         case OP_IBGT_UN:
2314         case OP_ICGT_UN:
2315         case OP_LBGT_UN:
2316         case OP_LCGT_UN:
2317         case OP_FCGT_UN:
2318         case OP_FBGT_UN:
2319         case OP_COND_EXC_GT_UN:
2320         case OP_COND_EXC_IGT_UN:
2321         case OP_CMOV_IGT_UN:
2322         case OP_CMOV_LGT_UN:
2323                 return CMP_GT_UN;
2324         default:
2325                 printf ("%s\n", mono_inst_name (opcode));
2326                 g_assert_not_reached ();
2327                 return 0;
2328         }
2329 }
2330
2331 CompRelation
2332 mono_negate_cond (CompRelation cond)
2333 {
2334         switch (cond) {
2335         case CMP_EQ:
2336                 return CMP_NE;
2337         case CMP_NE:
2338                 return CMP_EQ;
2339         case CMP_LE:
2340                 return CMP_GT;
2341         case CMP_GE:
2342                 return CMP_LT;
2343         case CMP_LT:
2344                 return CMP_GE;
2345         case CMP_GT:
2346                 return CMP_LE;
2347         case CMP_LE_UN:
2348                 return CMP_GT_UN;
2349         case CMP_GE_UN:
2350                 return CMP_LT_UN;
2351         case CMP_LT_UN:
2352                 return CMP_GE_UN;
2353         case CMP_GT_UN:
2354                 return CMP_LE_UN;
2355         default:
2356                 g_assert_not_reached ();
2357         }
2358 }
2359
2360 CompType
2361 mono_opcode_to_type (int opcode, int cmp_opcode)
2362 {
2363         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2364                 return CMP_TYPE_L;
2365         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2366                 return CMP_TYPE_I;
2367         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2368                 return CMP_TYPE_I;
2369         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2370                 return CMP_TYPE_L;
2371         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2372                 return CMP_TYPE_L;
2373         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2374                 return CMP_TYPE_F;
2375         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2376                 return CMP_TYPE_F;
2377         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2378                 return CMP_TYPE_I;
2379         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2380                 switch (cmp_opcode) {
2381                 case OP_ICOMPARE:
2382                 case OP_ICOMPARE_IMM:
2383                 case OP_LCOMPARE_IMM:
2384                         return CMP_TYPE_I;
2385                 default:
2386                         return CMP_TYPE_L;
2387                 }
2388         } else {
2389                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2390                 return 0;
2391         }
2392 }
2393
2394 #endif /* DISABLE_JIT */
2395
2396 gboolean
2397 mono_is_regsize_var (MonoType *t)
2398 {
2399         if (t->byref)
2400                 return TRUE;
2401         t = mono_type_get_underlying_type (t);
2402         switch (t->type) {
2403         case MONO_TYPE_BOOLEAN:
2404         case MONO_TYPE_CHAR:
2405         case MONO_TYPE_I1:
2406         case MONO_TYPE_U1:
2407         case MONO_TYPE_I2:
2408         case MONO_TYPE_U2:
2409         case MONO_TYPE_I4:
2410         case MONO_TYPE_U4:
2411         case MONO_TYPE_I:
2412         case MONO_TYPE_U:
2413         case MONO_TYPE_PTR:
2414         case MONO_TYPE_FNPTR:
2415 #if SIZEOF_REGISTER == 8
2416         case MONO_TYPE_I8:
2417         case MONO_TYPE_U8:
2418 #endif
2419                 return TRUE;
2420         case MONO_TYPE_OBJECT:
2421         case MONO_TYPE_STRING:
2422         case MONO_TYPE_CLASS:
2423         case MONO_TYPE_SZARRAY:
2424         case MONO_TYPE_ARRAY:
2425                 return TRUE;
2426         case MONO_TYPE_GENERICINST:
2427                 if (!mono_type_generic_inst_is_valuetype (t))
2428                         return TRUE;
2429                 return FALSE;
2430         case MONO_TYPE_VALUETYPE:
2431                 return FALSE;
2432         }
2433         return FALSE;
2434 }
2435
2436 #ifndef DISABLE_JIT
2437
2438 /*
2439  * mono_peephole_ins:
2440  *
2441  *   Perform some architecture independent peephole optimizations.
2442  */
2443 void
2444 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2445 {
2446         MonoInst *last_ins = ins->prev;
2447
2448         switch (ins->opcode) {
2449         case OP_MUL_IMM:
2450                 /* remove unnecessary multiplication with 1 */
2451                 if (ins->inst_imm == 1) {
2452                         if (ins->dreg != ins->sreg1)
2453                                 ins->opcode = OP_MOVE;
2454                         else
2455                                 MONO_DELETE_INS (bb, ins);
2456                 }
2457                 break;
2458         case OP_LOAD_MEMBASE:
2459         case OP_LOADI4_MEMBASE:
2460                 /*
2461                  * Note: if reg1 = reg2 the load op is removed
2462                  *
2463                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2464                  * OP_LOAD_MEMBASE offset(basereg), reg2
2465                  * -->
2466                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2467                  * OP_MOVE reg1, reg2
2468                  */
2469                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2470                         last_ins = last_ins->prev;
2471                 if (last_ins &&
2472                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2473                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2474                         ins->inst_basereg == last_ins->inst_destbasereg &&
2475                         ins->inst_offset == last_ins->inst_offset) {
2476                         if (ins->dreg == last_ins->sreg1) {
2477                                 MONO_DELETE_INS (bb, ins);
2478                                 break;
2479                         } else {
2480                                 ins->opcode = OP_MOVE;
2481                                 ins->sreg1 = last_ins->sreg1;
2482                         }
2483
2484                         /*
2485                          * Note: reg1 must be different from the basereg in the second load
2486                          * Note: if reg1 = reg2 is equal then second load is removed
2487                          *
2488                          * OP_LOAD_MEMBASE offset(basereg), reg1
2489                          * OP_LOAD_MEMBASE offset(basereg), reg2
2490                          * -->
2491                          * OP_LOAD_MEMBASE offset(basereg), reg1
2492                          * OP_MOVE reg1, reg2
2493                          */
2494                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2495                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2496                           ins->inst_basereg != last_ins->dreg &&
2497                           ins->inst_basereg == last_ins->inst_basereg &&
2498                           ins->inst_offset == last_ins->inst_offset) {
2499
2500                         if (ins->dreg == last_ins->dreg) {
2501                                 MONO_DELETE_INS (bb, ins);
2502                         } else {
2503                                 ins->opcode = OP_MOVE;
2504                                 ins->sreg1 = last_ins->dreg;
2505                         }
2506
2507                         //g_assert_not_reached ();
2508
2509 #if 0
2510                         /*
2511                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2512                          * OP_LOAD_MEMBASE offset(basereg), reg
2513                          * -->
2514                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2515                          * OP_ICONST reg, imm
2516                          */
2517                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2518                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2519                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2520                                    ins->inst_offset == last_ins->inst_offset) {
2521                         ins->opcode = OP_ICONST;
2522                         ins->inst_c0 = last_ins->inst_imm;
2523                         g_assert_not_reached (); // check this rule
2524 #endif
2525                 }
2526                 break;
2527         case OP_LOADI1_MEMBASE:
2528         case OP_LOADU1_MEMBASE:
2529                 /*
2530                  * Note: if reg1 = reg2 the load op is removed
2531                  *
2532                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2533                  * OP_LOAD_MEMBASE offset(basereg), reg2
2534                  * -->
2535                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2536                  * OP_MOVE reg1, reg2
2537                  */
2538                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2539                         ins->inst_basereg == last_ins->inst_destbasereg &&
2540                         ins->inst_offset == last_ins->inst_offset) {
2541                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2542                         ins->sreg1 = last_ins->sreg1;
2543                 }
2544                 break;
2545         case OP_LOADI2_MEMBASE:
2546         case OP_LOADU2_MEMBASE:
2547                 /*
2548                  * Note: if reg1 = reg2 the load op is removed
2549                  *
2550                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2551                  * OP_LOAD_MEMBASE offset(basereg), reg2
2552                  * -->
2553                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2554                  * OP_MOVE reg1, reg2
2555                  */
2556                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2557                         ins->inst_basereg == last_ins->inst_destbasereg &&
2558                         ins->inst_offset == last_ins->inst_offset) {
2559 #if SIZEOF_REGISTER == 8
2560                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2561 #else
2562                         /* The definition of OP_PCONV_TO_U2 is wrong */
2563                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2564 #endif
2565                         ins->sreg1 = last_ins->sreg1;
2566                 }
2567                 break;
2568         case OP_MOVE:
2569         case OP_FMOVE:
2570                 /*
2571                  * Removes:
2572                  *
2573                  * OP_MOVE reg, reg
2574                  */
2575                 if (ins->dreg == ins->sreg1) {
2576                         MONO_DELETE_INS (bb, ins);
2577                         break;
2578                 }
2579                 /*
2580                  * Removes:
2581                  *
2582                  * OP_MOVE sreg, dreg
2583                  * OP_MOVE dreg, sreg
2584                  */
2585                 if (last_ins && last_ins->opcode == ins->opcode &&
2586                         ins->sreg1 == last_ins->dreg &&
2587                         ins->dreg == last_ins->sreg1) {
2588                         MONO_DELETE_INS (bb, ins);
2589                 }
2590                 break;
2591         case OP_NOP:
2592                 MONO_DELETE_INS (bb, ins);
2593                 break;
2594         }
2595 }
2596
2597 #endif /* DISABLE_JIT */