mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30 /*
  31  * Every hardware register belongs to a register type or register bank. bank 0
  32  * contains the int registers, bank 1 contains the fp registers.
  33  * int registers are used 99% of the time, so they are special cased in a lot of
  34  * places.
  35  */
  36
  37 static const int regbank_size [] = {
  38         MONO_MAX_IREGS,
  39         MONO_MAX_FREGS,
  40         MONO_MAX_XREGS
  41 };
  42
  43 static const int regbank_load_ops [] = {
  44         OP_LOAD_MEMBASE,
  45         OP_LOADR8_MEMBASE,
  46         OP_LOADX_MEMBASE
  47 };
  48
  49 static const int regbank_store_ops [] = {
  50         OP_STORE_MEMBASE_REG,
  51         OP_STORER8_MEMBASE_REG,
  52         OP_STOREX_MEMBASE
  53 };
  54
  55 static const int regbank_move_ops [] = {
  56         OP_MOVE,
  57         OP_FMOVE,
  58         OP_XMOVE
  59 };
  60
  61 #define regmask(reg) (((regmask_t)1) << (reg))
  62
  63 static const regmask_t regbank_callee_saved_regs [] = {
  64         MONO_ARCH_CALLEE_SAVED_REGS,
  65         MONO_ARCH_CALLEE_SAVED_FREGS,
  66         MONO_ARCH_CALLEE_SAVED_XREGS,
  67 };
  68
  69 static const regmask_t regbank_callee_regs [] = {
  70         MONO_ARCH_CALLEE_REGS,
  71         MONO_ARCH_CALLEE_FREGS,
  72         MONO_ARCH_CALLEE_XREGS,
  73 };
  74
  75 static const int regbank_spill_var_size[] = {
  76         sizeof (gpointer),
  77         sizeof (double),
  78         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
  79 };
  80
  81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
  82
  83 static inline GSList*
  84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
  85 {
  86         GSList *new_list;
  87         GSList *last;
  88
  89         new_list = mono_mempool_alloc (mp, sizeof (GSList));
  90         new_list->data = data;
  91         new_list->next = NULL;
  92
  93         if (list) {
  94                 last = list;
  95                 while (last->next)
  96                         last = last->next;
  97                 last->next = new_list;
  98
  99                 return list;
 100         } else
 101                 return new_list;
 102 }
 103
 104 static inline void
 105 mono_regstate_assign (MonoRegState *rs)
 106 {
 107         if (rs->next_vreg > rs->vassign_size) {
 108                 g_free (rs->vassign);
 109                 rs->vassign_size = MAX (rs->next_vreg, 256);
 110                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 111         }
 112
 113         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 114         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 115
 116         rs->symbolic [0] = rs->isymbolic;
 117         rs->symbolic [1] = rs->fsymbolic;
 118
 119 #ifdef MONO_ARCH_NEED_SIMD_BANK
 120         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 121         rs->symbolic [2] = rs->xsymbolic;
 122 #endif
 123 }
 124
 125 static inline int
 126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 127 {
 128         regmask_t mask = allow & rs->ifree_mask;
 129
 130 #if defined(__x86_64__) && defined(__GNUC__)
 131  {
 132         guint64 i;
 133
 134         if (mask == 0)
 135                 return -1;
 136
 137         __asm__("bsfq %1,%0\n\t"
 138                         : "=r" (i) : "rm" (mask));
 139
 140         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 141         return i;
 142  }
 143 #else
 144         int i;
 145
 146         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 147                 if (mask & ((regmask_t)1 << i)) {
 148                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 149                         return i;
 150                 }
 151         }
 152         return -1;
 153 #endif
 154 }
 155
 156 static inline void
 157 mono_regstate_free_int (MonoRegState *rs, int reg)
 158 {
 159         if (reg >= 0) {
 160                 rs->ifree_mask |= (regmask_t)1 << reg;
 161                 rs->isymbolic [reg] = 0;
 162         }
 163 }
 164
 165 static inline int
 166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 167 {
 168         int i;
 169         regmask_t mask = allow & rs->free_mask [bank];
 170         for (i = 0; i < regbank_size [bank]; ++i) {
 171                 if (mask & ((regmask_t)1 << i)) {
 172                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 173                         return i;
 174                 }
 175         }
 176         return -1;
 177 }
 178
 179 static inline void
 180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 181 {
 182         if (reg >= 0) {
 183                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 184                 rs->symbolic [bank][reg] = 0;
 185         }
 186 }
 187
 188 const char*
 189 mono_regname_full (int reg, int bank)
 190 {
 191         if (G_UNLIKELY (bank)) {
 192 #if MONO_ARCH_NEED_SIMD_BANK
 193                 if (bank == 2)
 194                         return mono_arch_xregname (reg);
 195 #endif
 196                 g_assert (bank == 1);
 197                 return mono_arch_fregname (reg);
 198         } else {
 199                 return mono_arch_regname (reg);
 200         }
 201 }
 202
 203 void
 204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 205 {
 206         guint32 regpair;
 207
 208         regpair = (((guint32)hreg) << 24) + vreg;
 209         if (G_UNLIKELY (bank)) {
 210                 g_assert (vreg >= regbank_size [bank]);
 211                 g_assert (hreg < regbank_size [bank]);
 212                 call->used_fregs |= 1 << hreg;
 213                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 214         } else {
 215                 g_assert (vreg >= MONO_MAX_IREGS);
 216                 g_assert (hreg < MONO_MAX_IREGS);
 217                 call->used_iregs |= 1 << hreg;
 218                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 219         }
 220 }
 221
 222 static void
 223 resize_spill_info (MonoCompile *cfg, int bank)
 224 {
 225         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 226         int orig_len = cfg->spill_info_len [bank];
 227         int new_len = orig_len ? orig_len * 2 : 16;
 228         MonoSpillInfo *new_info;
 229         int i;
 230
 231         g_assert (bank < MONO_NUM_REGBANKS);
 232
 233         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 234         if (orig_info)
 235                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 236         for (i = orig_len; i < new_len; ++i)
 237                 new_info [i].offset = -1;
 238
 239         cfg->spill_info [bank] = new_info;
 240         cfg->spill_info_len [bank] = new_len;
 241 }
 242
 243 /*
 244  * returns the offset used by spillvar. It allocates a new
 245  * spill variable if necessary.
 246  */
 247 static inline int
 248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 249 {
 250         MonoSpillInfo *info;
 251         int size;
 252
 253         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 254                 while (spillvar >= cfg->spill_info_len [bank])
 255                         resize_spill_info (cfg, bank);
 256         }
 257
 258         /*
 259          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 260          */
 261         info = &cfg->spill_info [bank][spillvar];
 262         if (info->offset == -1) {
 263                 cfg->stack_offset += sizeof (gpointer) - 1;
 264                 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
 265
 266                 g_assert (bank < MONO_NUM_REGBANKS);
 267                 if (G_UNLIKELY (bank))
 268                         size = regbank_spill_var_size [bank];
 269                 else
 270                         size = sizeof (gpointer);
 271
 272                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 273                         cfg->stack_offset += size - 1;
 274                         cfg->stack_offset &= ~(size - 1);
 275                         info->offset = cfg->stack_offset;
 276                         cfg->stack_offset += size;
 277                 } else {
 278                         cfg->stack_offset += size - 1;
 279                         cfg->stack_offset &= ~(size - 1);
 280                         cfg->stack_offset += size;
 281                         info->offset = - cfg->stack_offset;
 282                 }
 283         }
 284
 285         return info->offset;
 286 }
 287
 288 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 289 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 290 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 291 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 292 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 293 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 294
 295 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 296 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 297 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 298 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 299 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 300
 301 #ifndef MONO_ARCH_INST_IS_FLOAT
 302 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 303 #endif
 304
 305 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 306 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 307 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 308 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 309 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 310
 311 #define reg_is_simd(desc) ((desc) == 'x')
 312
 313 #ifdef MONO_ARCH_NEED_SIMD_BANK
 314
 315 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 316
 317 #else
 318
 319 #define reg_bank(desc) reg_is_fp ((desc))
 320
 321 #endif
 322
 323 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 324 #define sreg1_bank(spec) sreg_bank (0, (spec))
 325 #define sreg2_bank(spec) sreg_bank (1, (spec))
 326 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 327
 328 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 329 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 330 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 331 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 332
 333 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 334
 335 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 336 #undef is_global_ireg
 337 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 338 #endif
 339
 340 typedef struct {
 341         int born_in;
 342         int killed_in;
 343         /* Not (yet) used */
 344         //int last_use;
 345         //int prev_use;
 346         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 347 } RegTrack;
 348
 349 #ifndef DISABLE_LOGGING
 350 void
 351 mono_print_ins_index (int i, MonoInst *ins)
 352 {
 353         const char *spec = ins_get_spec (ins->opcode);
 354         int num_sregs, j;
 355         int sregs [MONO_MAX_SRC_REGS];
 356
 357         if (i != -1)
 358                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 359         else
 360                 printf (" %s", mono_inst_name (ins->opcode));
 361         if (spec == MONO_ARCH_CPU_SPEC) {
 362                 /* This is a lowered opcode */
 363                 if (ins->dreg != -1)
 364                         printf (" R%d <-", ins->dreg);
 365                 if (ins->sreg1 != -1)
 366                         printf (" R%d", ins->sreg1);
 367                 if (ins->sreg2 != -1)
 368                         printf (" R%d", ins->sreg2);
 369                 if (ins->sreg3 != -1)
 370                         printf (" R%d", ins->sreg3);
 371
 372                 switch (ins->opcode) {
 373                 case OP_LBNE_UN:
 374                 case OP_LBEQ:
 375                 case OP_LBLT:
 376                 case OP_LBLT_UN:
 377                 case OP_LBGT:
 378                 case OP_LBGT_UN:
 379                 case OP_LBGE:
 380                 case OP_LBGE_UN:
 381                 case OP_LBLE:
 382                 case OP_LBLE_UN:
 383                         if (!ins->inst_false_bb)
 384                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 385                         else
 386                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 387                         break;
 388                 case OP_PHI:
 389                 case OP_VPHI:
 390                 case OP_XPHI:
 391                 case OP_FPHI: {
 392                         int i;
 393                         printf (" [%d (", (int)ins->inst_c0);
 394                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 395                                 if (i)
 396                                         printf (", ");
 397                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 398                         }
 399                         printf (")]");
 400                         break;
 401                 }
 402                 case OP_LDADDR:
 403                 case OP_OUTARG_VTRETADDR:
 404                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 405                         break;
 406                 case OP_REGOFFSET:
 407                         printf (" + 0x%lx", (long)ins->inst_offset);
 408                         break;
 409                 default:
 410                         break;
 411                 }
 412
 413                 printf ("\n");
 414                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 415                 return;
 416         }
 417
 418         if (spec [MONO_INST_DEST]) {
 419                 int bank = dreg_bank (spec);
 420                 if (is_soft_reg (ins->dreg, bank)) {
 421                         if (spec [MONO_INST_DEST] == 'b') {
 422                                 if (ins->inst_offset == 0)
 423                                         printf (" [R%d] <-", ins->dreg);
 424                                 else
 425                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 426                         }
 427                         else
 428                                 printf (" R%d <-", ins->dreg);
 429                 } else if (spec [MONO_INST_DEST] == 'b') {
 430                         if (ins->inst_offset == 0)
 431                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 432                         else
 433                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 434                 } else
 435                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 436         }
 437         if (spec [MONO_INST_SRC1]) {
 438                 int bank = sreg1_bank (spec);
 439                 if (is_soft_reg (ins->sreg1, bank)) {
 440                         if (spec [MONO_INST_SRC1] == 'b')
 441                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 442                         else
 443                                 printf (" R%d", ins->sreg1);
 444                 } else if (spec [MONO_INST_SRC1] == 'b')
 445                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 446                 else
 447                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 448         }
 449         num_sregs = mono_inst_get_src_registers (ins, sregs);
 450         for (j = 1; j < num_sregs; ++j) {
 451                 int bank = sreg_bank (j, spec);
 452                 if (is_soft_reg (sregs [j], bank))
 453                         printf (" R%d", sregs [j]);
 454                 else
 455                         printf (" %s", mono_regname_full (sregs [j], bank));
 456         }
 457
 458         switch (ins->opcode) {
 459         case OP_ICONST:
 460                 printf (" [%d]", (int)ins->inst_c0);
 461                 break;
 462 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 463         case OP_X86_PUSH_IMM:
 464 #endif
 465         case OP_ICOMPARE_IMM:
 466         case OP_COMPARE_IMM:
 467         case OP_IADD_IMM:
 468         case OP_ISUB_IMM:
 469         case OP_IAND_IMM:
 470         case OP_IOR_IMM:
 471         case OP_IXOR_IMM:
 472                 printf (" [%d]", (int)ins->inst_imm);
 473                 break;
 474         case OP_ADD_IMM:
 475         case OP_LADD_IMM:
 476                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 477                 break;
 478         case OP_I8CONST:
 479                 printf (" [%lld]", (long long)ins->inst_l);
 480                 break;
 481         case OP_R8CONST:
 482                 printf (" [%f]", *(double*)ins->inst_p0);
 483                 break;
 484         case OP_R4CONST:
 485                 printf (" [%f]", *(float*)ins->inst_p0);
 486                 break;
 487         case CEE_CALL:
 488         case CEE_CALLVIRT:
 489         case OP_CALL:
 490         case OP_CALL_MEMBASE:
 491         case OP_CALL_REG:
 492         case OP_FCALL:
 493         case OP_FCALLVIRT:
 494         case OP_LCALL:
 495         case OP_LCALLVIRT:
 496         case OP_VCALL:
 497         case OP_VCALLVIRT:
 498         case OP_VCALL_REG:
 499         case OP_VCALL_MEMBASE:
 500         case OP_VCALL2:
 501         case OP_VCALL2_REG:
 502         case OP_VCALL2_MEMBASE:
 503         case OP_VOIDCALL:
 504         case OP_VOIDCALL_MEMBASE:
 505         case OP_VOIDCALLVIRT: {
 506                 MonoCallInst *call = (MonoCallInst*)ins;
 507                 GSList *list;
 508
 509                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 510                         /*
 511                          * These are lowered opcodes, but they are in the .md files since the old
 512                          * JIT passes them to backends.
 513                          */
 514                         if (ins->dreg != -1)
 515                                 printf (" R%d <-", ins->dreg);
 516                 }
 517
 518                 if (call->method) {
 519                         char *full_name = mono_method_full_name (call->method, TRUE);
 520                         printf (" [%s]", full_name);
 521                         g_free (full_name);
 522                 } else if (call->fptr) {
 523                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 524                         if (info)
 525                                 printf (" [%s]", info->name);
 526                 }
 527
 528                 list = call->out_ireg_args;
 529                 while (list) {
 530                         guint32 regpair;
 531                         int reg, hreg;
 532
 533                         regpair = (guint32)(gssize)(list->data);
 534                         hreg = regpair >> 24;
 535                         reg = regpair & 0xffffff;
 536
 537                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 538
 539                         list = g_slist_next (list);
 540                 }
 541                 break;
 542         }
 543         case OP_BR:
 544         case OP_CALL_HANDLER:
 545                 printf (" [B%d]", ins->inst_target_bb->block_num);
 546                 break;
 547         case CEE_BNE_UN:
 548         case CEE_BEQ:
 549         case CEE_BLT:
 550         case CEE_BLT_UN:
 551         case CEE_BGT:
 552         case CEE_BGT_UN:
 553         case CEE_BGE:
 554         case CEE_BGE_UN:
 555         case CEE_BLE:
 556         case CEE_BLE_UN:
 557         case OP_IBNE_UN:
 558         case OP_IBEQ:
 559         case OP_IBLT:
 560         case OP_IBLT_UN:
 561         case OP_IBGT:
 562         case OP_IBGT_UN:
 563         case OP_IBGE:
 564         case OP_IBGE_UN:
 565         case OP_IBLE:
 566         case OP_IBLE_UN:
 567         case OP_LBNE_UN:
 568         case OP_LBEQ:
 569         case OP_LBLT:
 570         case OP_LBLT_UN:
 571         case OP_LBGT:
 572         case OP_LBGT_UN:
 573         case OP_LBGE:
 574         case OP_LBGE_UN:
 575         case OP_LBLE:
 576         case OP_LBLE_UN:
 577                 if (!ins->inst_false_bb)
 578                         printf (" [B%d]", ins->inst_true_bb->block_num);
 579                 else
 580                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 581                 break;
 582         case OP_LIVERANGE_START:
 583         case OP_LIVERANGE_END:
 584                 printf (" R%d", (int)ins->inst_c1);
 585                 break;
 586         default:
 587                 break;
 588         }
 589
 590         if (spec [MONO_INST_CLOB])
 591                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 592         printf ("\n");
 593 }
 594
 595 static void
 596 print_regtrack (RegTrack *t, int num)
 597 {
 598         int i;
 599         char buf [32];
 600         const char *r;
 601
 602         for (i = 0; i < num; ++i) {
 603                 if (!t [i].born_in)
 604                         continue;
 605                 if (i >= MONO_MAX_IREGS) {
 606                         g_snprintf (buf, sizeof(buf), "R%d", i);
 607                         r = buf;
 608                 } else
 609                         r = mono_arch_regname (i);
 610                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 611         }
 612 }
 613 #else
 614 void
 615 mono_print_ins_index (int i, MonoInst *ins)
 616 {
 617 }
 618 #endif /* DISABLE_LOGGING */
 619
 620 void
 621 mono_print_ins (MonoInst *ins)
 622 {
 623         mono_print_ins_index (-1, ins);
 624 }
 625
 626 static inline void
 627 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 628 {
 629         /*
 630          * If this function is called multiple times, the new instructions are inserted
 631          * in the proper order.
 632          */
 633         mono_bblock_insert_before_ins (bb, ins, to_insert);
 634 }
 635
 636 static inline void
 637 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 638 {
 639         /*
 640          * If this function is called multiple times, the new instructions are inserted in
 641          * proper order.
 642          */
 643         mono_bblock_insert_after_ins (bb, *last, to_insert);
 644
 645         *last = to_insert;
 646 }
 647
 648 /*
 649  * Force the spilling of the variable in the symbolic register 'reg'.
 650  */
 651 static int
 652 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 653 {
 654         MonoInst *load;
 655         int i, sel, spill;
 656         int *symbolic;
 657         MonoRegState *rs = cfg->rs;
 658
 659         symbolic = rs->symbolic [bank];
 660         sel = rs->vassign [reg];
 661
 662         /*i = rs->isymbolic [sel];
 663         g_assert (i == reg);*/
 664         i = reg;
 665         spill = ++cfg->spill_count;
 666         rs->vassign [i] = -spill - 1;
 667         if (G_UNLIKELY (bank))
 668                 mono_regstate_free_general (rs, sel, bank);
 669         else
 670                 mono_regstate_free_int (rs, sel);
 671         /* we need to create a spill var and insert a load to sel after the current instruction */
 672         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 673         load->dreg = sel;
 674         load->inst_basereg = cfg->frame_reg;
 675         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 676         insert_after_ins (bb, ins, last, load);
 677         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 678         if (G_UNLIKELY (bank))
 679                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 680         else
 681                 i = mono_regstate_alloc_int (rs, regmask (sel));
 682         g_assert (i == sel);
 683
 684         return sel;
 685 }
 686
 687 /* This isn't defined on older glib versions and on some platforms */
 688 #ifndef G_GUINT64_FORMAT
 689 #define G_GUINT64_FORMAT "ul"
 690 #endif
 691
 692 static int
 693 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 694 {
 695         MonoInst *load;
 696         int i, sel, spill, num_sregs;
 697         int sregs [MONO_MAX_SRC_REGS];
 698         int *symbolic;
 699         MonoRegState *rs = cfg->rs;
 700
 701         symbolic = rs->symbolic [bank];
 702
 703         g_assert (bank < MONO_NUM_REGBANKS);
 704
 705         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 706         /* exclude the registers in the current instruction */
 707         num_sregs = mono_inst_get_src_registers (ins, sregs);
 708         for (i = 0; i < num_sregs; ++i) {
 709                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 710                         if (is_soft_reg (sregs [i], bank))
 711                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 712                         else
 713                                 regmask &= ~ (regmask (sregs [i]));
 714                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 715                 }
 716         }
 717         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 718                 regmask &= ~ (regmask (ins->dreg));
 719                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 720         }
 721
 722         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 723         g_assert (regmask); /* need at least a register we can free */
 724         sel = 0;
 725         /* we should track prev_use and spill the register that's farther */
 726         if (G_UNLIKELY (bank)) {
 727                 for (i = 0; i < regbank_size [bank]; ++i) {
 728                         if (regmask & (regmask (i))) {
 729                                 sel = i;
 730                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 731                                 break;
 732                         }
 733                 }
 734
 735                 i = rs->symbolic [bank] [sel];
 736                 spill = ++cfg->spill_count;
 737                 rs->vassign [i] = -spill - 1;
 738                 mono_regstate_free_general (rs, sel, bank);
 739         }
 740         else {
 741                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 742                         if (regmask & (regmask (i))) {
 743                                 sel = i;
 744                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 745                                 break;
 746                         }
 747                 }
 748
 749                 i = rs->isymbolic [sel];
 750                 spill = ++cfg->spill_count;
 751                 rs->vassign [i] = -spill - 1;
 752                 mono_regstate_free_int (rs, sel);
 753         }
 754
 755         /* we need to create a spill var and insert a load to sel after the current instruction */
 756         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 757         load->dreg = sel;
 758         load->inst_basereg = cfg->frame_reg;
 759         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 760         insert_after_ins (bb, ins, last, load);
 761         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 762         if (G_UNLIKELY (bank))
 763                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 764         else
 765                 i = mono_regstate_alloc_int (rs, regmask (sel));
 766         g_assert (i == sel);
 767
 768         return sel;
 769 }
 770
 771 static void
 772 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 773 {
 774         if (G_UNLIKELY (bank)) {
 775                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 776                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 777                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 778                         mono_regstate_free_general (cfg->rs, hreg, bank);
 779                 }
 780         }
 781         else {
 782                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 783                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 784                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 785                         mono_regstate_free_int (cfg->rs, hreg);
 786                 }
 787         }
 788 }
 789
 790 static MonoInst*
 791 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 792 {
 793         MonoInst *copy;
 794
 795         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 796
 797         copy->dreg = dest;
 798         copy->sreg1 = src;
 799         copy->cil_code = ip;
 800         if (ins) {
 801                 mono_bblock_insert_after_ins (bb, ins, copy);
 802                 *last = copy;
 803         }
 804         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 805         return copy;
 806 }
 807
 808 static MonoInst*
 809 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 810 {
 811         MonoInst *store;
 812         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 813         store->sreg1 = reg;
 814         store->inst_destbasereg = cfg->frame_reg;
 815         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 816         if (ins) {
 817                 mono_bblock_insert_after_ins (bb, ins, store);
 818                 *last = store;
 819         }
 820         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 821         return store;
 822 }
 823
 824 /* flags used in reginfo->flags */
 825 enum {
 826         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 827         MONO_FP_NEEDS_SPILL                     = regmask (1),
 828         MONO_FP_NEEDS_LOAD                      = regmask (2)
 829 };
 830
 831 static inline int
 832 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 833 {
 834         int val;
 835
 836         if (info && info->preferred_mask) {
 837                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 838                 if (val >= 0) {
 839                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 840                         return val;
 841                 }
 842         }
 843
 844         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 845         if (val < 0)
 846                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 847
 848         return val;
 849 }
 850
 851 static inline int
 852 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 853 {
 854         int val;
 855
 856         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 857
 858         if (val < 0)
 859                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 860
 861         return val;
 862 }
 863
 864 static inline int
 865 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 866 {
 867         if (G_UNLIKELY (bank))
 868                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 869         else
 870                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 871 }
 872
 873 static inline void
 874 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 875 {
 876         if (G_UNLIKELY (bank)) {
 877                 g_assert (reg >= regbank_size [bank]);
 878                 g_assert (hreg < regbank_size [bank]);
 879                 g_assert (! is_global_freg (hreg));
 880
 881                 rs->vassign [reg] = hreg;
 882                 rs->symbolic [bank] [hreg] = reg;
 883                 rs->free_mask [bank] &= ~ (regmask (hreg));
 884         }
 885         else {
 886                 g_assert (reg >= MONO_MAX_IREGS);
 887                 g_assert (hreg < MONO_MAX_IREGS);
 888 #ifndef TARGET_ARM
 889                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 890                 g_assert (! is_global_ireg (hreg));
 891 #endif
 892
 893                 rs->vassign [reg] = hreg;
 894                 rs->isymbolic [hreg] = reg;
 895                 rs->ifree_mask &= ~ (regmask (hreg));
 896         }
 897 }
 898
 899 static inline regmask_t
 900 get_callee_mask (const char spec)
 901 {
 902         if (G_UNLIKELY (reg_bank (spec)))
 903                 return regbank_callee_regs [reg_bank (spec)];
 904         return MONO_ARCH_CALLEE_REGS;
 905 }
 906
 907 static gint8 desc_to_fixed_reg [256];
 908 static gboolean desc_to_fixed_reg_inited = FALSE;
 909
 910 /*
 911  * Local register allocation.
 912  * We first scan the list of instructions and we save the liveness info of
 913  * each register (when the register is first used, when it's value is set etc.).
 914  * We also reverse the list of instructions because assigning registers backwards allows
 915  * for more tricks to be used.
 916  */
 917 void
 918 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 919 {
 920         MonoInst *ins, *prev, *last;
 921         MonoInst **tmp;
 922         MonoRegState *rs = cfg->rs;
 923         int i, j, val, max;
 924         RegTrack *reginfo;
 925         const char *spec;
 926         unsigned char spec_src1, spec_dest;
 927         int bank = 0;
 928 #if MONO_ARCH_USE_FPSTACK
 929         gboolean has_fp = FALSE;
 930         int fpstack [8];
 931         int sp = 0;
 932 #endif
 933         int num_sregs;
 934         int sregs [MONO_MAX_SRC_REGS];
 935
 936         if (!bb->code)
 937                 return;
 938
 939         if (!desc_to_fixed_reg_inited) {
 940                 for (i = 0; i < 256; ++i)
 941                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
 942                 desc_to_fixed_reg_inited = TRUE;
 943         }
 944
 945         rs->next_vreg = bb->max_vreg;
 946         mono_regstate_assign (rs);
 947
 948         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
 949         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
 950                 rs->free_mask [i] = regbank_callee_regs [i];
 951
 952         max = rs->next_vreg;
 953
 954         if (cfg->reginfo && cfg->reginfo_len < max)
 955                 cfg->reginfo = NULL;
 956
 957         reginfo = cfg->reginfo;
 958         if (!reginfo) {
 959                 cfg->reginfo_len = MAX (1024, max * 2);
 960                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
 961         }
 962         else
 963                 g_assert (cfg->reginfo_len >= rs->next_vreg);
 964
 965         if (cfg->verbose_level > 1) {
 966                 /* print_regtrack reads the info of all variables */
 967                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
 968         }
 969
 970         /*
 971          * For large methods, next_vreg can be very large, so g_malloc0 time can
 972          * be prohibitive. So we manually init the reginfo entries used by the
 973          * bblock.
 974          */
 975         for (ins = bb->code; ins; ins = ins->next) {
 976                 spec = ins_get_spec (ins->opcode);
 977
 978                 if ((ins->dreg != -1) && (ins->dreg < max)) {
 979                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
 980 #if SIZEOF_REGISTER == 4
 981                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
 982                                 /**
 983                                  * In the new IR, the two vregs of the regpair do not alias the
 984                                  * original long vreg. shift the vreg here so the rest of the
 985                                  * allocator doesn't have to care about it.
 986                                  */
 987                                 ins->dreg ++;
 988                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
 989                         }
 990 #endif
 991                 }
 992
 993                 num_sregs = mono_inst_get_src_registers (ins, sregs);
 994                 for (j = 0; j < num_sregs; ++j) {
 995                         g_assert (sregs [j] != -1);
 996                         if (sregs [j] < max) {
 997                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
 998 #if SIZEOF_REGISTER == 4
 999                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1000                                         sregs [j]++;
1001                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1002                                 }
1003 #endif
1004                         }
1005                 }
1006                 mono_inst_set_src_registers (ins, sregs);
1007         }
1008
1009         /*if (cfg->opt & MONO_OPT_COPYPROP)
1010                 local_copy_prop (cfg, ins);*/
1011
1012         i = 1;
1013         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1014         /* forward pass on the instructions to collect register liveness info */
1015         MONO_BB_FOR_EACH_INS (bb, ins) {
1016                 spec = ins_get_spec (ins->opcode);
1017                 spec_dest = spec [MONO_INST_DEST];
1018
1019                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1020                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1021                 }
1022
1023                 DEBUG (mono_print_ins_index (i, ins));
1024
1025                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1026
1027 #if MONO_ARCH_USE_FPSTACK
1028                 if (dreg_is_fp (spec)) {
1029                         has_fp = TRUE;
1030                 } else {
1031                         for (j = 0; j < num_sregs; ++j) {
1032                                 if (sreg_is_fp (j, spec))
1033                                         has_fp = TRUE;
1034                         }
1035                 }
1036 #endif
1037
1038                 for (j = 0; j < num_sregs; ++j) {
1039                         int sreg = sregs [j];
1040                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1041                         if (sreg_spec) {
1042                                 bank = sreg_bank (j, spec);
1043                                 g_assert (sreg != -1);
1044                                 if (is_soft_reg (sreg, bank))
1045                                         /* This means the vreg is not local to this bb */
1046                                         g_assert (reginfo [sreg].born_in > 0);
1047                                 rs->vassign [sreg] = -1;
1048                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1049                                 //reginfo [ins->sreg2].last_use = i;
1050                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1051                                         /* The virtual register is allocated sequentially */
1052                                         rs->vassign [sreg + 1] = -1;
1053                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1054                                         //reginfo [ins->sreg2 + 1].last_use = i;
1055                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1056                                                 reginfo [sreg + 1].born_in = i;
1057                                 }
1058                         } else {
1059                                 sregs [j] = -1;
1060                         }
1061                 }
1062                 mono_inst_set_src_registers (ins, sregs);
1063
1064                 if (spec_dest) {
1065                         int dest_dreg;
1066
1067                         bank = dreg_bank (spec);
1068                         if (spec_dest != 'b') /* it's not just a base register */
1069                                 reginfo [ins->dreg].killed_in = i;
1070                         g_assert (ins->dreg != -1);
1071                         rs->vassign [ins->dreg] = -1;
1072                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1073                         //reginfo [ins->dreg].last_use = i;
1074                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1075                                 reginfo [ins->dreg].born_in = i;
1076
1077                         dest_dreg = desc_to_fixed_reg [spec_dest];
1078                         if (dest_dreg != -1)
1079                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1080
1081 #ifdef MONO_ARCH_INST_FIXED_MASK
1082                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1083 #endif
1084
1085                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1086                                 /* The virtual register is allocated sequentially */
1087                                 rs->vassign [ins->dreg + 1] = -1;
1088                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1089                                 //reginfo [ins->dreg + 1].last_use = i;
1090                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1091                                         reginfo [ins->dreg + 1].born_in = i;
1092                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1093                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1094                         }
1095                 } else {
1096                         ins->dreg = -1;
1097                 }
1098
1099                 if (spec [MONO_INST_CLOB] == 'c') {
1100                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1101
1102                         MonoCallInst *call = (MonoCallInst*)ins;
1103                         GSList *list;
1104
1105                         list = call->out_ireg_args;
1106                         if (list) {
1107                                 while (list) {
1108                                         guint32 regpair;
1109                                         int reg, hreg;
1110
1111                                         regpair = (guint32)(gssize)(list->data);
1112                                         hreg = regpair >> 24;
1113                                         reg = regpair & 0xffffff;
1114
1115                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1116                                         //reginfo [reg].last_use = i;
1117
1118                                         list = g_slist_next (list);
1119                                 }
1120                         }
1121
1122                         list = call->out_freg_args;
1123                         if (list) {
1124                                 while (list) {
1125                                         guint32 regpair;
1126                                         int reg, hreg;
1127
1128                                         regpair = (guint32)(gssize)(list->data);
1129                                         hreg = regpair >> 24;
1130                                         reg = regpair & 0xffffff;
1131
1132                                         list = g_slist_next (list);
1133                                 }
1134                         }
1135                 }
1136
1137                 ++i;
1138         }
1139
1140         tmp = &last;
1141
1142         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1143         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1144                 int prev_dreg, clob_dreg;
1145                 int dest_dreg, clob_reg;
1146                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1147                 int dreg_high, sreg1_high;
1148                 regmask_t dreg_mask, mask;
1149                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1150                 regmask_t dreg_fixed_mask;
1151                 const unsigned char *ip;
1152                 --i;
1153                 spec = ins_get_spec (ins->opcode);
1154                 spec_src1 = spec [MONO_INST_SRC1];
1155                 spec_dest = spec [MONO_INST_DEST];
1156                 prev_dreg = -1;
1157                 clob_dreg = -1;
1158                 clob_reg = -1;
1159                 dest_dreg = -1;
1160                 dreg_high = -1;
1161                 sreg1_high = -1;
1162                 dreg_mask = get_callee_mask (spec_dest);
1163                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1164                         prev_sregs [j] = -1;
1165                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1166                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1167 #ifdef MONO_ARCH_INST_FIXED_MASK
1168                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1169 #else
1170                         sreg_fixed_masks [j] = 0;
1171 #endif
1172                 }
1173
1174                 DEBUG (printf ("processing:"));
1175                 DEBUG (mono_print_ins_index (i, ins));
1176
1177                 ip = ins->cil_code;
1178
1179                 last = ins;
1180
1181                 /*
1182                  * FIXED REGS
1183                  */
1184                 dest_dreg = desc_to_fixed_reg [spec_dest];
1185                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1186                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1187
1188 #ifdef MONO_ARCH_INST_FIXED_MASK
1189                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1190 #else
1191                 dreg_fixed_mask = 0;
1192 #endif
1193
1194                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1195
1196                 /*
1197                  * TRACK FIXED SREG2, 3, ...
1198                  */
1199                 for (j = 1; j < num_sregs; ++j) {
1200                         int sreg = sregs [j];
1201                         int dest_sreg = dest_sregs [j];
1202                         if (dest_sreg != -1) {
1203                                 if (rs->ifree_mask & (regmask (dest_sreg))) {
1204                                         if (is_global_ireg (sreg)) {
1205                                                 int k;
1206                                                 /* Argument already in hard reg, need to copy */
1207                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1208                                                 insert_before_ins (bb, ins, copy);
1209                                                 for (k = 0; k < num_sregs; ++k) {
1210                                                         if (k != j)
1211                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1212                                                 }
1213                                         }
1214                                         else {
1215                                                 val = rs->vassign [sreg];
1216                                                 if (val == -1) {
1217                                                         DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1218                                                         assign_reg (cfg, rs, sreg, dest_sreg, 0);
1219                                                 } else if (val < -1) {
1220                                                         /* FIXME: */
1221                                                         g_assert_not_reached ();
1222                                                 } else {
1223                                                         /* Argument already in hard reg, need to copy */
1224                                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1225                                                         int k;
1226
1227                                                         insert_before_ins (bb, ins, copy);
1228                                                         for (k = 0; k < num_sregs; ++k) {
1229                                                                 if (k != j)
1230                                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1231                                                         }
1232                                                         /*
1233                                                          * Prevent the dreg from being allocate to dest_sreg
1234                                                          * too, since it could force sreg1 to be allocated to
1235                                                          * the same reg on x86.
1236                                                          */
1237                                                         dreg_mask &= ~ (regmask (dest_sreg));
1238                                                 }
1239                                         }
1240                                 } else {
1241                                         gboolean need_spill = TRUE;
1242                                         gboolean need_assign = TRUE;
1243                                         int k;
1244
1245                                         dreg_mask &= ~ (regmask (dest_sreg));
1246                                         for (k = 0; k < num_sregs; ++k) {
1247                                                 if (k != j)
1248                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1249                                         }
1250
1251                                         /*
1252                                          * First check if dreg is assigned to dest_sreg2, since we
1253                                          * can't spill a dreg.
1254                                          */
1255                                         val = rs->vassign [ins->dreg];
1256                                         if (val == dest_sreg && ins->dreg != sreg) {
1257                                                 /*
1258                                                  * the destination register is already assigned to
1259                                                  * dest_sreg2: we need to allocate another register for it
1260                                                  * and then copy from this to dest_sreg2.
1261                                                  */
1262                                                 int new_dest;
1263                                                 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1264                                                 g_assert (new_dest >= 0);
1265                                                 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1266
1267                                                 prev_dreg = ins->dreg;
1268                                                 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1269                                                 clob_dreg = ins->dreg;
1270                                                 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1271                                                 mono_regstate_free_int (rs, dest_sreg);
1272                                                 need_spill = FALSE;
1273                                         }
1274
1275                                         if (is_global_ireg (sreg)) {
1276                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1277                                                 insert_before_ins (bb, ins, copy);
1278                                                 need_assign = FALSE;
1279                                         }
1280                                         else {
1281                                                 val = rs->vassign [sreg];
1282                                                 if (val == dest_sreg) {
1283                                                         /* sreg2 is already assigned to the correct register */
1284                                                         need_spill = FALSE;
1285                                                 } else if (val < -1) {
1286                                                         /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1287                                                 } else if (val >= 0) {
1288                                                         /* sreg2 already assigned to another register */
1289                                                         /*
1290                                                          * We couldn't emit a copy from val to dest_sreg2, because
1291                                                          * val might be spilled later while processing this
1292                                                          * instruction. So we spill sreg2 so it can be allocated to
1293                                                          * dest_sreg2.
1294                                                          */
1295                                                         DEBUG (printf ("\tforced spill of R%d\n", sreg));
1296                                                         free_up_reg (cfg, bb, tmp, ins, val, 0);
1297                                                 }
1298                                         }
1299
1300                                         if (need_spill) {
1301                                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg]));
1302                                                 free_up_reg (cfg, bb, tmp, ins, dest_sreg, 0);
1303                                         }
1304
1305                                         if (need_assign) {
1306                                                 if (rs->vassign [sreg] < -1) {
1307                                                         MonoInst *store;
1308                                                         int spill;
1309
1310                                                         /* Need to emit a spill store */
1311                                                         spill = - rs->vassign [sreg] - 1;
1312                                                         store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
1313                                                         insert_before_ins (bb, ins, store);
1314                                                 }
1315                                                 /* force-set sreg2 */
1316                                                 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1317                                         }
1318                                 }
1319                                 sregs [j] = dest_sreg;
1320                         }
1321                 }
1322                 mono_inst_set_src_registers (ins, sregs);
1323
1324                 /*
1325                  * TRACK DREG
1326                  */
1327                 bank = dreg_bank (spec);
1328                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1329                         prev_dreg = ins->dreg;
1330                 }
1331
1332                 if (spec_dest == 'b') {
1333                         /*
1334                          * The dest reg is read by the instruction, not written, so
1335                          * avoid allocating sreg1/sreg2 to the same reg.
1336                          */
1337                         if (dest_sregs [0] != -1)
1338                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1339                         for (j = 1; j < num_sregs; ++j) {
1340                                 if (dest_sregs [j] != -1)
1341                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1342                         }
1343
1344                         val = rs->vassign [ins->dreg];
1345                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1346                                 /* DREG is already allocated to a register needed for sreg1 */
1347                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1348                                 mono_regstate_free_int (rs, val);
1349                         }
1350                 }
1351
1352                 /*
1353                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1354                  * various complex situations.
1355                  */
1356                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1357                         guint32 dreg2, dest_dreg2;
1358
1359                         g_assert (is_soft_reg (ins->dreg, bank));
1360
1361                         if (dest_dreg != -1) {
1362                                 if (rs->vassign [ins->dreg] != dest_dreg)
1363                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1364
1365                                 dreg2 = ins->dreg + 1;
1366                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1367                                 if (dest_dreg2 != -1) {
1368                                         if (rs->vassign [dreg2] != dest_dreg2)
1369                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1370                                 }
1371                         }
1372                 }
1373
1374                 if (dreg_fixed_mask) {
1375                         g_assert (!bank);
1376                         if (is_global_ireg (ins->dreg)) {
1377                                 /*
1378                                  * The argument is already in a hard reg, but that reg is
1379                                  * not usable by this instruction, so allocate a new one.
1380                                  */
1381                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1382                                 if (val < 0)
1383                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1384                                 mono_regstate_free_int (rs, val);
1385                                 dest_dreg = val;
1386
1387                                 /* Fall through */
1388                         }
1389                         else
1390                                 dreg_mask &= dreg_fixed_mask;
1391                 }
1392
1393                 if (is_soft_reg (ins->dreg, bank)) {
1394                         val = rs->vassign [ins->dreg];
1395
1396                         if (val < 0) {
1397                                 int spill = 0;
1398                                 if (val < -1) {
1399                                         /* the register gets spilled after this inst */
1400                                         spill = -val -1;
1401                                 }
1402                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1403                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1404                                 if (spill)
1405                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1406                         }
1407
1408                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1409                         ins->dreg = val;
1410                 }
1411
1412                 /* Handle regpairs */
1413                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1414                         int reg2 = prev_dreg + 1;
1415
1416                         g_assert (!bank);
1417                         g_assert (prev_dreg > -1);
1418                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1419                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1420 #ifdef TARGET_X86
1421                         /* bug #80489 */
1422                         mask &= ~regmask (X86_ECX);
1423 #endif
1424                         val = rs->vassign [reg2];
1425                         if (val < 0) {
1426                                 int spill = 0;
1427                                 if (val < -1) {
1428                                         /* the register gets spilled after this inst */
1429                                         spill = -val -1;
1430                                 }
1431                                 val = mono_regstate_alloc_int (rs, mask);
1432                                 if (val < 0)
1433                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1434                                 if (spill)
1435                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1436                         }
1437                         else {
1438                                 if (! (mask & (regmask (val)))) {
1439                                         val = mono_regstate_alloc_int (rs, mask);
1440                                         if (val < 0)
1441                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1442
1443                                         /* Reallocate hreg to the correct register */
1444                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1445
1446                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1447                                 }
1448                         }
1449
1450                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1451                         assign_reg (cfg, rs, reg2, val, bank);
1452
1453                         dreg_high = val;
1454                         ins->backend.reg3 = val;
1455
1456                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1457                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1458                                 mono_regstate_free_int (rs, val);
1459                         }
1460                 }
1461
1462                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1463                         /*
1464                          * In theory, we could free up the hreg even if the vreg is alive,
1465                          * but branches inside bblocks force us to assign the same hreg
1466                          * to a vreg every time it is encountered.
1467                          */
1468                         int dreg = rs->vassign [prev_dreg];
1469                         g_assert (dreg >= 0);
1470                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1471                         if (G_UNLIKELY (bank))
1472                                 mono_regstate_free_general (rs, dreg, bank);
1473                         else
1474                                 mono_regstate_free_int (rs, dreg);
1475                         rs->vassign [prev_dreg] = -1;
1476                 }
1477
1478                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1479                         /* this instruction only outputs to dest_dreg, need to copy */
1480                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1481                         ins->dreg = dest_dreg;
1482
1483                         if (G_UNLIKELY (bank)) {
1484                                 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1485                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1486                         }
1487                         else {
1488                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1489                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1490                         }
1491                 }
1492
1493                 if (spec_dest == 'b') {
1494                         /*
1495                          * The dest reg is read by the instruction, not written, so
1496                          * avoid allocating sreg1/sreg2 to the same reg.
1497                          */
1498                         for (j = 0; j < num_sregs; ++j)
1499                                 if (!sreg_bank (j, spec))
1500                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1501                 }
1502
1503                 /*
1504                  * TRACK CLOBBERING
1505                  */
1506                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1507                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1508                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1509                         mono_regstate_free_int (rs, clob_reg);
1510                 }
1511
1512                 if (spec [MONO_INST_CLOB] == 'c') {
1513                         int j, s, dreg, dreg2, cur_bank;
1514                         guint64 clob_mask;
1515
1516                         clob_mask = MONO_ARCH_CALLEE_REGS;
1517
1518                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1519                                 /*
1520                                  * Need to avoid spilling the dreg since the dreg is not really
1521                                  * clobbered by the call.
1522                                  */
1523                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1524                                         dreg = rs->vassign [prev_dreg];
1525                                 else
1526                                         dreg = -1;
1527
1528                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1529                                         dreg2 = rs->vassign [prev_dreg + 1];
1530                                 else
1531                                         dreg2 = -1;
1532
1533                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1534                                         s = regmask (j);
1535                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1536                                                 if ((j != dreg) && (j != dreg2))
1537                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1538                                                 else if (rs->isymbolic [j])
1539                                                         /* The hreg is assigned to the dreg of this instruction */
1540                                                         rs->vassign [rs->isymbolic [j]] = -1;
1541                                                 mono_regstate_free_int (rs, j);
1542                                         }
1543                                 }
1544                         }
1545
1546                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1547                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1548                                         clob_mask = regbank_callee_regs [cur_bank];
1549                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1550                                                 dreg = rs->vassign [prev_dreg];
1551                                         else
1552                                                 dreg = -1;
1553
1554                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1555                                                 s = regmask (j);
1556                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1557                                                         if (j != dreg)
1558                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1559                                                         else if (rs->symbolic [cur_bank] [j])
1560                                                                 /* The hreg is assigned to the dreg of this instruction */
1561                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1562                                                         mono_regstate_free_general (rs, j, cur_bank);
1563                                                 }
1564                                         }
1565                                 }
1566                         }
1567                 }
1568
1569                 /*
1570                  * TRACK ARGUMENT REGS
1571                  */
1572                 if (spec [MONO_INST_CLOB] == 'c') {
1573                         MonoCallInst *call = (MonoCallInst*)ins;
1574                         GSList *list;
1575
1576                         /*
1577                          * This needs to be done before assigning sreg1, so sreg1 will
1578                          * not be assigned one of the argument regs.
1579                          */
1580
1581                         /*
1582                          * Assign all registers in call->out_reg_args to the proper
1583                          * argument registers.
1584                          */
1585
1586                         list = call->out_ireg_args;
1587                         if (list) {
1588                                 while (list) {
1589                                         guint32 regpair;
1590                                         int reg, hreg;
1591
1592                                         regpair = (guint32)(gssize)(list->data);
1593                                         hreg = regpair >> 24;
1594                                         reg = regpair & 0xffffff;
1595
1596                                         assign_reg (cfg, rs, reg, hreg, 0);
1597
1598                                         sreg_masks [0] &= ~(regmask (hreg));
1599
1600                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1601
1602                                         list = g_slist_next (list);
1603                                 }
1604                         }
1605
1606                         list = call->out_freg_args;
1607                         if (list) {
1608                                 while (list) {
1609                                         guint32 regpair;
1610                                         int reg, hreg;
1611
1612                                         regpair = (guint32)(gssize)(list->data);
1613                                         hreg = regpair >> 24;
1614                                         reg = regpair & 0xffffff;
1615
1616                                         assign_reg (cfg, rs, reg, hreg, 1);
1617
1618                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1619
1620                                         list = g_slist_next (list);
1621                                 }
1622                         }
1623                 }
1624
1625                 /*
1626                  * TRACK SREG1
1627                  */
1628                 bank = sreg1_bank (spec);
1629                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1630                         int sreg1 = sregs [0];
1631                         int dest_sreg1 = dest_sregs [0];
1632
1633                         g_assert (is_soft_reg (sreg1, bank));
1634
1635                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1636                         if (dest_sreg1 != -1)
1637                                 g_assert (dest_sreg1 == ins->dreg);
1638                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1639                         g_assert (val >= 0);
1640
1641                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1642                                 // FIXME:
1643                                 g_assert_not_reached ();
1644
1645                         assign_reg (cfg, rs, sreg1, val, bank);
1646
1647                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1648
1649                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1650                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1651                         g_assert (val >= 0);
1652
1653                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1654                                 // FIXME:
1655                                 g_assert_not_reached ();
1656
1657                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1658
1659                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1660
1661                         /* Skip rest of this section */
1662                         dest_sregs [0] = -1;
1663                 }
1664
1665                 if (sreg_fixed_masks [0]) {
1666                         g_assert (!bank);
1667                         if (is_global_ireg (sregs [0])) {
1668                                 /*
1669                                  * The argument is already in a hard reg, but that reg is
1670                                  * not usable by this instruction, so allocate a new one.
1671                                  */
1672                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1673                                 if (val < 0)
1674                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1675                                 mono_regstate_free_int (rs, val);
1676                                 dest_sregs [0] = val;
1677
1678                                 /* Fall through to the dest_sreg1 != -1 case */
1679                         }
1680                         else
1681                                 sreg_masks [0] &= sreg_fixed_masks [0];
1682                 }
1683
1684                 if (dest_sregs [0] != -1) {
1685                         sreg_masks [0] = regmask (dest_sregs [0]);
1686
1687                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1688                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sregs [0]]));
1689                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sregs [0]], 0);
1690                                 mono_regstate_free_int (rs, dest_sregs [0]);
1691                         }
1692                         if (is_global_ireg (sregs [0])) {
1693                                 /* The argument is already in a hard reg, need to copy */
1694                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1695                                 insert_before_ins (bb, ins, copy);
1696                                 sregs [0] = dest_sregs [0];
1697                         }
1698                 }
1699
1700                 if (is_soft_reg (sregs [0], bank)) {
1701                         val = rs->vassign [sregs [0]];
1702                         prev_sregs [0] = sregs [0];
1703                         if (val < 0) {
1704                                 int spill = 0;
1705                                 if (val < -1) {
1706                                         /* the register gets spilled after this inst */
1707                                         spill = -val -1;
1708                                 }
1709
1710                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1711                                         /*
1712                                          * Allocate the same hreg to sreg1 as well so the
1713                                          * peephole can get rid of the move.
1714                                          */
1715                                         sreg_masks [0] = regmask (ins->dreg);
1716                                 }
1717
1718                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1719                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1720                                         sreg_masks [0] = regmask (ins->dreg);
1721
1722                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1723                                 assign_reg (cfg, rs, sregs [0], val, bank);
1724                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1725
1726                                 if (spill) {
1727                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
1728                                         /*
1729                                          * Need to insert before the instruction since it can
1730                                          * overwrite sreg1.
1731                                          */
1732                                         insert_before_ins (bb, ins, store);
1733                                 }
1734                         }
1735                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1736                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1737                                 insert_before_ins (bb, ins, copy);
1738                                 for (j = 1; j < num_sregs; ++j)
1739                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1740                                 val = dest_sregs [0];
1741                         }
1742
1743                         sregs [0] = val;
1744                 }
1745                 else {
1746                         prev_sregs [0] = -1;
1747                 }
1748                 mono_inst_set_src_registers (ins, sregs);
1749
1750                 for (j = 1; j < num_sregs; ++j)
1751                         sreg_masks [j] &= ~(regmask (sregs [0]));
1752
1753                 /* Handle the case when sreg1 is a regpair but dreg is not */
1754                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1755                         int reg2 = prev_sregs [0] + 1;
1756
1757                         g_assert (!bank);
1758                         g_assert (prev_sregs [0] > -1);
1759                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1760                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1761                         val = rs->vassign [reg2];
1762                         if (val < 0) {
1763                                 int spill = 0;
1764                                 if (val < -1) {
1765                                         /* the register gets spilled after this inst */
1766                                         spill = -val -1;
1767                                 }
1768                                 val = mono_regstate_alloc_int (rs, mask);
1769                                 if (val < 0)
1770                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1771                                 if (spill)
1772                                         g_assert_not_reached ();
1773                         }
1774                         else {
1775                                 if (! (mask & (regmask (val)))) {
1776                                         /* The vreg is already allocated to a wrong hreg */
1777                                         /* FIXME: */
1778                                         g_assert_not_reached ();
1779 #if 0
1780                                         val = mono_regstate_alloc_int (rs, mask);
1781                                         if (val < 0)
1782                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1783
1784                                         /* Reallocate hreg to the correct register */
1785                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1786
1787                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1788 #endif
1789                                 }
1790                         }
1791
1792                         sreg1_high = val;
1793                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1794                         assign_reg (cfg, rs, reg2, val, bank);
1795                 }
1796
1797                 /* Handle dreg==sreg1 */
1798                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1799                         MonoInst *sreg2_copy = NULL;
1800                         MonoInst *copy;
1801                         int bank = reg_bank (spec_src1);
1802
1803                         if (ins->dreg == sregs [1]) {
1804                                 /*
1805                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1806                                  * register for it.
1807                                  */
1808                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1809
1810                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1811                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1812                                 prev_sregs [1] = sregs [1] = reg2;
1813
1814                                 if (G_UNLIKELY (bank))
1815                                         mono_regstate_free_general (rs, reg2, bank);
1816                                 else
1817                                         mono_regstate_free_int (rs, reg2);
1818                         }
1819
1820                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1821                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1822                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1823                                         /* FIXME: */
1824                                         g_assert_not_reached ();
1825
1826                                 /*
1827                                  * sreg1 and dest are already allocated to the same regpair by the
1828                                  * SREG1 allocation code.
1829                                  */
1830                                 g_assert (sregs [0] == ins->dreg);
1831                                 g_assert (dreg_high == sreg1_high);
1832                         }
1833
1834                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
1835                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
1836                         insert_before_ins (bb, ins, copy);
1837
1838                         if (sreg2_copy)
1839                                 insert_before_ins (bb, copy, sreg2_copy);
1840
1841                         /*
1842                          * Need to prevent sreg2 to be allocated to sreg1, since that
1843                          * would screw up the previous copy.
1844                          */
1845                         sreg_masks [1] &= ~ (regmask (sregs [0]));
1846                         /* we set sreg1 to dest as well */
1847                         prev_sregs [0] = sregs [0] = ins->dreg;
1848                         sreg_masks [1] &= ~ (regmask (ins->dreg));
1849                 }
1850                 mono_inst_set_src_registers (ins, sregs);
1851
1852                 /*
1853                  * TRACK SREG2, 3, ...
1854                  */
1855                 for (j = 1; j < num_sregs; ++j) {
1856                         int k;
1857
1858                         bank = sreg_bank (j, spec);
1859                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
1860                                 g_assert_not_reached ();
1861                         if (is_soft_reg (sregs [j], bank)) {
1862                                 val = rs->vassign [sregs [j]];
1863
1864                                 if (val < 0) {
1865                                         int spill = 0;
1866                                         if (val < -1) {
1867                                                 /* the register gets spilled after this inst */
1868                                                 spill = -val -1;
1869                                         }
1870                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
1871                                         assign_reg (cfg, rs, sregs [j], val, bank);
1872                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
1873                                         if (spill) {
1874                                                 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
1875                                                 /*
1876                                                  * Need to insert before the instruction since it can
1877                                                  * overwrite sreg2.
1878                                                  */
1879                                                 insert_before_ins (bb, ins, store);
1880                                         }
1881                                 }
1882                                 sregs [j] = val;
1883                                 for (k = j + 1; k < num_sregs; ++k)
1884                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
1885                         }
1886                         else {
1887                                 prev_sregs [j] = -1;
1888                         }
1889                 }
1890                 mono_inst_set_src_registers (ins, sregs);
1891
1892                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1893                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1894                         mono_regstate_free_int (rs, ins->sreg1);
1895                 }
1896                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1897                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1898                         mono_regstate_free_int (rs, ins->sreg2);
1899                 }*/
1900
1901                 DEBUG (mono_print_ins_index (i, ins));
1902         }
1903
1904         // FIXME: Set MAX_FREGS to 8
1905         // FIXME: Optimize generated code
1906 #if MONO_ARCH_USE_FPSTACK
1907         /*
1908          * Make a forward pass over the code, simulating the fp stack, making sure the
1909          * arguments required by the fp opcodes are at the top of the stack.
1910          */
1911         if (has_fp) {
1912                 MonoInst *prev = NULL;
1913                 MonoInst *fxch;
1914                 int tmp;
1915
1916                 g_assert (num_sregs <= 2);
1917
1918                 for (ins = bb->code; ins; ins = ins->next) {
1919                         spec = ins_get_spec (ins->opcode);
1920
1921                         DEBUG (printf ("processing:"));
1922                         DEBUG (mono_print_ins_index (0, ins));
1923
1924                         if (ins->opcode == OP_FMOVE) {
1925                                 /* Do it by renaming the source to the destination on the stack */
1926                                 // FIXME: Is this correct ?
1927                                 for (i = 0; i < sp; ++i)
1928                                         if (fpstack [i] == ins->sreg1)
1929                                                 fpstack [i] = ins->dreg;
1930                                 prev = ins;
1931                                 continue;
1932                         }
1933
1934                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1935                                 /* Arg1 must be in %st(1) */
1936                                 g_assert (prev);
1937
1938                                 i = 0;
1939                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
1940                                         i ++;
1941                                 g_assert (i < sp);
1942
1943                                 if (sp - 1 - i > 0) {
1944                                         /* First move it to %st(0) */
1945                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1946
1947                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1948                                         fxch->inst_imm = sp - 1 - i;
1949
1950                                         prev->next = fxch;
1951                                         fxch->next = ins;
1952                                         prev = fxch;
1953
1954                                         tmp = fpstack [sp - 1];
1955                                         fpstack [sp - 1] = fpstack [i];
1956                                         fpstack [i] = tmp;
1957                                 }
1958
1959                                 /* Then move it to %st(1) */
1960                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1961
1962                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1963                                 fxch->inst_imm = 1;
1964
1965                                 prev->next = fxch;
1966                                 fxch->next = ins;
1967                                 prev = fxch;
1968
1969                                 tmp = fpstack [sp - 1];
1970                                 fpstack [sp - 1] = fpstack [sp - 2];
1971                                 fpstack [sp - 2] = tmp;
1972                         }
1973
1974                         if (sreg2_is_fp (spec)) {
1975                                 g_assert (sp > 0);
1976
1977                                 if (fpstack [sp - 1] != ins->sreg2) {
1978                                         g_assert (prev);
1979
1980                                         i = 0;
1981                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
1982                                                 i ++;
1983                                         g_assert (i < sp);
1984
1985                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1986
1987                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1988                                         fxch->inst_imm = sp - 1 - i;
1989
1990                                         prev->next = fxch;
1991                                         fxch->next = ins;
1992                                         prev = fxch;
1993
1994                                         tmp = fpstack [sp - 1];
1995                                         fpstack [sp - 1] = fpstack [i];
1996                                         fpstack [i] = tmp;
1997                                 }
1998
1999                                 sp --;
2000                         }
2001
2002                         if (sreg1_is_fp (spec)) {
2003                                 g_assert (sp > 0);
2004
2005                                 if (fpstack [sp - 1] != ins->sreg1) {
2006                                         g_assert (prev);
2007
2008                                         i = 0;
2009                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2010                                                 i ++;
2011                                         g_assert (i < sp);
2012
2013                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2014
2015                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2016                                         fxch->inst_imm = sp - 1 - i;
2017
2018                                         prev->next = fxch;
2019                                         fxch->next = ins;
2020                                         prev = fxch;
2021
2022                                         tmp = fpstack [sp - 1];
2023                                         fpstack [sp - 1] = fpstack [i];
2024                                         fpstack [i] = tmp;
2025                                 }
2026
2027                                 sp --;
2028                         }
2029
2030                         if (dreg_is_fp (spec)) {
2031                                 g_assert (sp < 8);
2032                                 fpstack [sp ++] = ins->dreg;
2033                         }
2034
2035                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2036                                 printf ("\t[");
2037                                 for (i = 0; i < sp; ++i)
2038                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2039                                 printf ("]\n");
2040                         }
2041
2042                         prev = ins;
2043                 }
2044
2045                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2046                         /* Remove remaining items from the fp stack */
2047                         /*
2048                          * These can remain for example as a result of a dead fmove like in
2049                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2050                          */
2051                         while (sp) {
2052                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2053                                 mono_add_ins_to_end (bb, ins);
2054                                 sp --;
2055                         }
2056                 }
2057         }
2058 #endif
2059 }
2060
2061 CompRelation
2062 mono_opcode_to_cond (int opcode)
2063 {
2064         switch (opcode) {
2065         case CEE_BEQ:
2066         case OP_CEQ:
2067         case OP_IBEQ:
2068         case OP_ICEQ:
2069         case OP_LBEQ:
2070         case OP_LCEQ:
2071         case OP_FBEQ:
2072         case OP_FCEQ:
2073         case OP_COND_EXC_EQ:
2074         case OP_COND_EXC_IEQ:
2075         case OP_CMOV_IEQ:
2076         case OP_CMOV_LEQ:
2077                 return CMP_EQ;
2078         case CEE_BNE_UN:
2079         case OP_IBNE_UN:
2080         case OP_LBNE_UN:
2081         case OP_FBNE_UN:
2082         case OP_COND_EXC_NE_UN:
2083         case OP_COND_EXC_INE_UN:
2084         case OP_CMOV_INE_UN:
2085         case OP_CMOV_LNE_UN:
2086                 return CMP_NE;
2087         case CEE_BLE:
2088         case OP_IBLE:
2089         case OP_LBLE:
2090         case OP_FBLE:
2091         case OP_CMOV_ILE:
2092         case OP_CMOV_LLE:
2093                 return CMP_LE;
2094         case CEE_BGE:
2095         case OP_IBGE:
2096         case OP_LBGE:
2097         case OP_FBGE:
2098         case OP_CMOV_IGE:
2099         case OP_CMOV_LGE:
2100                 return CMP_GE;
2101         case CEE_BLT:
2102         case OP_CLT:
2103         case OP_IBLT:
2104         case OP_ICLT:
2105         case OP_LBLT:
2106         case OP_LCLT:
2107         case OP_FBLT:
2108         case OP_FCLT:
2109         case OP_COND_EXC_LT:
2110         case OP_COND_EXC_ILT:
2111         case OP_CMOV_ILT:
2112         case OP_CMOV_LLT:
2113                 return CMP_LT;
2114         case CEE_BGT:
2115         case OP_CGT:
2116         case OP_IBGT:
2117         case OP_ICGT:
2118         case OP_LBGT:
2119         case OP_LCGT:
2120         case OP_FBGT:
2121         case OP_FCGT:
2122         case OP_COND_EXC_GT:
2123         case OP_COND_EXC_IGT:
2124         case OP_CMOV_IGT:
2125         case OP_CMOV_LGT:
2126                 return CMP_GT;
2127
2128         case CEE_BLE_UN:
2129         case OP_IBLE_UN:
2130         case OP_LBLE_UN:
2131         case OP_FBLE_UN:
2132         case OP_COND_EXC_LE_UN:
2133         case OP_COND_EXC_ILE_UN:
2134         case OP_CMOV_ILE_UN:
2135         case OP_CMOV_LLE_UN:
2136                 return CMP_LE_UN;
2137         case CEE_BGE_UN:
2138         case OP_IBGE_UN:
2139         case OP_LBGE_UN:
2140         case OP_FBGE_UN:
2141         case OP_CMOV_IGE_UN:
2142         case OP_CMOV_LGE_UN:
2143                 return CMP_GE_UN;
2144         case CEE_BLT_UN:
2145         case OP_CLT_UN:
2146         case OP_IBLT_UN:
2147         case OP_ICLT_UN:
2148         case OP_LBLT_UN:
2149         case OP_LCLT_UN:
2150         case OP_FBLT_UN:
2151         case OP_FCLT_UN:
2152         case OP_COND_EXC_LT_UN:
2153         case OP_COND_EXC_ILT_UN:
2154         case OP_CMOV_ILT_UN:
2155         case OP_CMOV_LLT_UN:
2156                 return CMP_LT_UN;
2157         case CEE_BGT_UN:
2158         case OP_CGT_UN:
2159         case OP_IBGT_UN:
2160         case OP_ICGT_UN:
2161         case OP_LBGT_UN:
2162         case OP_LCGT_UN:
2163         case OP_FCGT_UN:
2164         case OP_FBGT_UN:
2165         case OP_COND_EXC_GT_UN:
2166         case OP_COND_EXC_IGT_UN:
2167         case OP_CMOV_IGT_UN:
2168         case OP_CMOV_LGT_UN:
2169                 return CMP_GT_UN;
2170         default:
2171                 printf ("%s\n", mono_inst_name (opcode));
2172                 g_assert_not_reached ();
2173                 return 0;
2174         }
2175 }
2176
2177 CompRelation
2178 mono_negate_cond (CompRelation cond)
2179 {
2180         switch (cond) {
2181         case CMP_EQ:
2182                 return CMP_NE;
2183         case CMP_NE:
2184                 return CMP_EQ;
2185         case CMP_LE:
2186                 return CMP_GT;
2187         case CMP_GE:
2188                 return CMP_LT;
2189         case CMP_LT:
2190                 return CMP_GE;
2191         case CMP_GT:
2192                 return CMP_LE;
2193         case CMP_LE_UN:
2194                 return CMP_GT_UN;
2195         case CMP_GE_UN:
2196                 return CMP_LT_UN;
2197         case CMP_LT_UN:
2198                 return CMP_GE_UN;
2199         case CMP_GT_UN:
2200                 return CMP_LE_UN;
2201         default:
2202                 g_assert_not_reached ();
2203         }
2204 }
2205
2206 CompType
2207 mono_opcode_to_type (int opcode, int cmp_opcode)
2208 {
2209         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2210                 return CMP_TYPE_L;
2211         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2212                 return CMP_TYPE_L;
2213         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2214                 return CMP_TYPE_I;
2215         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2216                 return CMP_TYPE_I;
2217         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2218                 return CMP_TYPE_L;
2219         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2220                 return CMP_TYPE_L;
2221         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2222                 return CMP_TYPE_F;
2223         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2224                 return CMP_TYPE_F;
2225         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2226                 return CMP_TYPE_I;
2227         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2228                 switch (cmp_opcode) {
2229                 case OP_ICOMPARE:
2230                 case OP_ICOMPARE_IMM:
2231                 case OP_LCOMPARE_IMM:
2232                         return CMP_TYPE_I;
2233                 default:
2234                         return CMP_TYPE_L;
2235                 }
2236         } else {
2237                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2238                 return 0;
2239         }
2240 }
2241
2242 gboolean
2243 mono_is_regsize_var (MonoType *t)
2244 {
2245         if (t->byref)
2246                 return TRUE;
2247         t = mono_type_get_underlying_type (t);
2248         switch (t->type) {
2249         case MONO_TYPE_BOOLEAN:
2250         case MONO_TYPE_CHAR:
2251         case MONO_TYPE_I1:
2252         case MONO_TYPE_U1:
2253         case MONO_TYPE_I2:
2254         case MONO_TYPE_U2:
2255         case MONO_TYPE_I4:
2256         case MONO_TYPE_U4:
2257         case MONO_TYPE_I:
2258         case MONO_TYPE_U:
2259         case MONO_TYPE_PTR:
2260         case MONO_TYPE_FNPTR:
2261 #if SIZEOF_REGISTER == 8
2262         case MONO_TYPE_I8:
2263         case MONO_TYPE_U8:
2264 #endif
2265                 return TRUE;
2266         case MONO_TYPE_OBJECT:
2267         case MONO_TYPE_STRING:
2268         case MONO_TYPE_CLASS:
2269         case MONO_TYPE_SZARRAY:
2270         case MONO_TYPE_ARRAY:
2271                 return TRUE;
2272         case MONO_TYPE_GENERICINST:
2273                 if (!mono_type_generic_inst_is_valuetype (t))
2274                         return TRUE;
2275                 return FALSE;
2276         case MONO_TYPE_VALUETYPE:
2277                 return FALSE;
2278         }
2279         return FALSE;
2280 }
2281
2282 /*
2283  * mono_peephole_ins:
2284  *
2285  *   Perform some architecture independent peephole optimizations.
2286  */
2287 void
2288 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2289 {
2290         MonoInst *last_ins = ins->prev;
2291
2292         switch (ins->opcode) {
2293         case OP_MUL_IMM:
2294                 /* remove unnecessary multiplication with 1 */
2295                 if (ins->inst_imm == 1) {
2296                         if (ins->dreg != ins->sreg1)
2297                                 ins->opcode = OP_MOVE;
2298                         else
2299                                 MONO_DELETE_INS (bb, ins);
2300                 }
2301                 break;
2302         case OP_LOAD_MEMBASE:
2303         case OP_LOADI4_MEMBASE:
2304                 /*
2305                  * Note: if reg1 = reg2 the load op is removed
2306                  *
2307                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2308                  * OP_LOAD_MEMBASE offset(basereg), reg2
2309                  * -->
2310                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2311                  * OP_MOVE reg1, reg2
2312                  */
2313                 if (last_ins &&
2314                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2315                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2316                         ins->inst_basereg == last_ins->inst_destbasereg &&
2317                         ins->inst_offset == last_ins->inst_offset) {
2318                         if (ins->dreg == last_ins->sreg1) {
2319                                 MONO_DELETE_INS (bb, ins);
2320                                 break;
2321                         } else {
2322                                 ins->opcode = OP_MOVE;
2323                                 ins->sreg1 = last_ins->sreg1;
2324                         }
2325
2326                         /*
2327                          * Note: reg1 must be different from the basereg in the second load
2328                          * Note: if reg1 = reg2 is equal then second load is removed
2329                          *
2330                          * OP_LOAD_MEMBASE offset(basereg), reg1
2331                          * OP_LOAD_MEMBASE offset(basereg), reg2
2332                          * -->
2333                          * OP_LOAD_MEMBASE offset(basereg), reg1
2334                          * OP_MOVE reg1, reg2
2335                          */
2336                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2337                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2338                           ins->inst_basereg != last_ins->dreg &&
2339                           ins->inst_basereg == last_ins->inst_basereg &&
2340                           ins->inst_offset == last_ins->inst_offset) {
2341
2342                         if (ins->dreg == last_ins->dreg) {
2343                                 MONO_DELETE_INS (bb, ins);
2344                         } else {
2345                                 ins->opcode = OP_MOVE;
2346                                 ins->sreg1 = last_ins->dreg;
2347                         }
2348
2349                         //g_assert_not_reached ();
2350
2351 #if 0
2352                         /*
2353                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2354                          * OP_LOAD_MEMBASE offset(basereg), reg
2355                          * -->
2356                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2357                          * OP_ICONST reg, imm
2358                          */
2359                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2360                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2361                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2362                                    ins->inst_offset == last_ins->inst_offset) {
2363                         ins->opcode = OP_ICONST;
2364                         ins->inst_c0 = last_ins->inst_imm;
2365                         g_assert_not_reached (); // check this rule
2366 #endif
2367                 }
2368                 break;
2369         case OP_LOADI1_MEMBASE:
2370         case OP_LOADU1_MEMBASE:
2371                 /*
2372                  * Note: if reg1 = reg2 the load op is removed
2373                  *
2374                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2375                  * OP_LOAD_MEMBASE offset(basereg), reg2
2376                  * -->
2377                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2378                  * OP_MOVE reg1, reg2
2379                  */
2380                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2381                         ins->inst_basereg == last_ins->inst_destbasereg &&
2382                         ins->inst_offset == last_ins->inst_offset) {
2383                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2384                         ins->sreg1 = last_ins->sreg1;
2385                 }
2386                 break;
2387         case OP_LOADI2_MEMBASE:
2388         case OP_LOADU2_MEMBASE:
2389                 /*
2390                  * Note: if reg1 = reg2 the load op is removed
2391                  *
2392                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2393                  * OP_LOAD_MEMBASE offset(basereg), reg2
2394                  * -->
2395                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2396                  * OP_MOVE reg1, reg2
2397                  */
2398                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2399                         ins->inst_basereg == last_ins->inst_destbasereg &&
2400                         ins->inst_offset == last_ins->inst_offset) {
2401 #if SIZEOF_REGISTER == 8
2402                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2403 #else
2404                         /* The definition of OP_PCONV_TO_U2 is wrong */
2405                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2406 #endif
2407                         ins->sreg1 = last_ins->sreg1;
2408                 }
2409                 break;
2410         case OP_MOVE:
2411         case OP_FMOVE:
2412                 /*
2413                  * Removes:
2414                  *
2415                  * OP_MOVE reg, reg
2416                  */
2417                 if (ins->dreg == ins->sreg1) {
2418                         MONO_DELETE_INS (bb, ins);
2419                         break;
2420                 }
2421                 /*
2422                  * Removes:
2423                  *
2424                  * OP_MOVE sreg, dreg
2425                  * OP_MOVE dreg, sreg
2426                  */
2427                 if (last_ins && last_ins->opcode == OP_MOVE &&
2428                         ins->sreg1 == last_ins->dreg &&
2429                         ins->dreg == last_ins->sreg1) {
2430                         MONO_DELETE_INS (bb, ins);
2431                 }
2432                 break;
2433         case OP_NOP:
2434                 MONO_DELETE_INS (bb, ins);
2435                 break;
2436         }
2437 }
2438