2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/metadata/threads.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/mempool-internals.h>
20 #include <mono/utils/mono-math.h>
24 #include "mini-arch.h"
28 #ifndef MONO_MAX_XREGS
30 #define MONO_MAX_XREGS 0
31 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
32 #define MONO_ARCH_CALLEE_XREGS 0
36 #define MONO_ARCH_BANK_MIRRORED -2
38 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
40 #ifndef MONO_ARCH_NEED_SIMD_BANK
41 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
44 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
46 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
52 #define get_mirrored_bank(bank) (-1)
54 #define is_hreg_mirrored(rs, bank, hreg) (0)
59 /* If the bank is mirrored return the true logical bank that the register in the
60 * physical register bank is allocated to.
62 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
63 return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
67 * Every hardware register belongs to a register type or register bank. bank 0
68 * contains the int registers, bank 1 contains the fp registers.
69 * int registers are used 99% of the time, so they are special cased in a lot of
73 static const int regbank_size [] = {
81 static const int regbank_load_ops [] = {
89 static const int regbank_store_ops [] = {
90 OP_STORER_MEMBASE_REG,
91 OP_STORER8_MEMBASE_REG,
92 OP_STORER_MEMBASE_REG,
93 OP_STORER_MEMBASE_REG,
97 static const int regbank_move_ops [] = {
105 #define regmask(reg) (((regmask_t)1) << (reg))
107 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
108 static const regmask_t regbank_callee_saved_regs [] = {
109 MONO_ARCH_CALLEE_SAVED_REGS,
110 MONO_ARCH_CALLEE_SAVED_FREGS,
111 MONO_ARCH_CALLEE_SAVED_REGS,
112 MONO_ARCH_CALLEE_SAVED_REGS,
113 MONO_ARCH_CALLEE_SAVED_XREGS,
117 static const regmask_t regbank_callee_regs [] = {
118 MONO_ARCH_CALLEE_REGS,
119 MONO_ARCH_CALLEE_FREGS,
120 MONO_ARCH_CALLEE_REGS,
121 MONO_ARCH_CALLEE_REGS,
122 MONO_ARCH_CALLEE_XREGS,
125 static const int regbank_spill_var_size[] = {
130 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
133 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
136 mono_regstate_assign (MonoRegState *rs)
138 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
139 /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
140 * if the values here are not the same.
142 g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
143 g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
144 g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
147 if (rs->next_vreg > rs->vassign_size) {
148 g_free (rs->vassign);
149 rs->vassign_size = MAX (rs->next_vreg, 256);
150 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
153 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
154 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
156 rs->symbolic [MONO_REG_INT] = rs->isymbolic;
157 rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
159 #ifdef MONO_ARCH_NEED_SIMD_BANK
160 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
161 rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
166 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
168 regmask_t mask = allow & rs->ifree_mask;
170 #if defined(__x86_64__) && defined(__GNUC__)
177 __asm__("bsfq %1,%0\n\t"
178 : "=r" (i) : "rm" (mask));
180 rs->ifree_mask &= ~ ((regmask_t)1 << i);
186 for (i = 0; i < MONO_MAX_IREGS; ++i) {
187 if (mask & ((regmask_t)1 << i)) {
188 rs->ifree_mask &= ~ ((regmask_t)1 << i);
197 mono_regstate_free_int (MonoRegState *rs, int reg)
200 rs->ifree_mask |= (regmask_t)1 << reg;
201 rs->isymbolic [reg] = 0;
206 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
210 regmask_t mask = allow & rs->free_mask [bank];
211 for (i = 0; i < regbank_size [bank]; ++i) {
212 if (mask & ((regmask_t)1 << i)) {
213 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
215 mirrored_bank = get_mirrored_bank (bank);
216 if (mirrored_bank == -1)
219 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
227 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
232 rs->free_mask [bank] |= (regmask_t)1 << reg;
233 rs->symbolic [bank][reg] = 0;
235 mirrored_bank = get_mirrored_bank (bank);
236 if (mirrored_bank == -1)
238 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
239 rs->symbolic [mirrored_bank][reg] = 0;
244 mono_regname_full (int reg, int bank)
246 if (G_UNLIKELY (bank)) {
247 #if MONO_ARCH_NEED_SIMD_BANK
248 if (bank == MONO_REG_SIMD)
249 return mono_arch_xregname (reg);
251 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
252 return mono_arch_regname (reg);
253 g_assert (bank == MONO_REG_DOUBLE);
254 return mono_arch_fregname (reg);
256 return mono_arch_regname (reg);
261 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
265 regpair = (((guint32)hreg) << 24) + vreg;
266 if (G_UNLIKELY (bank)) {
267 g_assert (vreg >= regbank_size [bank]);
268 g_assert (hreg < regbank_size [bank]);
269 call->used_fregs |= 1 << hreg;
270 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
272 g_assert (vreg >= MONO_MAX_IREGS);
273 g_assert (hreg < MONO_MAX_IREGS);
274 call->used_iregs |= 1 << hreg;
275 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
280 * mono_call_inst_add_outarg_vt:
282 * Register OUTARG_VT as belonging to CALL.
285 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
287 call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
291 resize_spill_info (MonoCompile *cfg, int bank)
293 MonoSpillInfo *orig_info = cfg->spill_info [bank];
294 int orig_len = cfg->spill_info_len [bank];
295 int new_len = orig_len ? orig_len * 2 : 16;
296 MonoSpillInfo *new_info;
299 g_assert (bank < MONO_NUM_REGBANKS);
301 new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
303 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
304 for (i = orig_len; i < new_len; ++i)
305 new_info [i].offset = -1;
307 cfg->spill_info [bank] = new_info;
308 cfg->spill_info_len [bank] = new_len;
312 * returns the offset used by spillvar. It allocates a new
313 * spill variable if necessary.
316 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
321 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
322 while (spillvar >= cfg->spill_info_len [bank])
323 resize_spill_info (cfg, bank);
327 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
329 info = &cfg->spill_info [bank][spillvar];
330 if (info->offset == -1) {
331 cfg->stack_offset += sizeof (mgreg_t) - 1;
332 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
334 g_assert (bank < MONO_NUM_REGBANKS);
335 if (G_UNLIKELY (bank))
336 size = regbank_spill_var_size [bank];
338 size = sizeof (mgreg_t);
340 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
341 cfg->stack_offset += size - 1;
342 cfg->stack_offset &= ~(size - 1);
343 info->offset = cfg->stack_offset;
344 cfg->stack_offset += size;
346 cfg->stack_offset += size - 1;
347 cfg->stack_offset &= ~(size - 1);
348 cfg->stack_offset += size;
349 info->offset = - cfg->stack_offset;
356 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
357 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
358 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
359 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
360 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
361 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
363 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
364 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
365 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
366 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
367 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
369 #ifndef MONO_ARCH_INST_IS_FLOAT
370 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
373 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
374 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
375 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
376 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
377 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
379 #define reg_is_simd(desc) ((desc) == 'x')
381 #ifdef MONO_ARCH_NEED_SIMD_BANK
383 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
387 #define reg_bank(desc) reg_is_fp ((desc))
391 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
392 #define sreg1_bank(spec) sreg_bank (0, (spec))
393 #define sreg2_bank(spec) sreg_bank (1, (spec))
394 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
396 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
397 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
398 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
399 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
401 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
403 #ifdef MONO_ARCH_IS_GLOBAL_IREG
404 #undef is_global_ireg
405 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
414 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
417 #if !defined(DISABLE_LOGGING)
420 mono_print_ins_index (int i, MonoInst *ins)
422 GString *buf = mono_print_ins_index_strbuf (i, ins);
423 printf ("%s\n", buf->str);
424 g_string_free (buf, TRUE);
428 mono_print_ins_index_strbuf (int i, MonoInst *ins)
430 const char *spec = ins_get_spec (ins->opcode);
431 GString *sbuf = g_string_new (NULL);
433 int sregs [MONO_MAX_SRC_REGS];
436 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
438 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
439 if (spec == MONO_ARCH_CPU_SPEC) {
440 gboolean dest_base = FALSE;
441 switch (ins->opcode) {
442 case OP_STOREV_MEMBASE:
449 /* This is a lowered opcode */
450 if (ins->dreg != -1) {
452 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
454 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
456 if (ins->sreg1 != -1)
457 g_string_append_printf (sbuf, " R%d", ins->sreg1);
458 if (ins->sreg2 != -1)
459 g_string_append_printf (sbuf, " R%d", ins->sreg2);
460 if (ins->sreg3 != -1)
461 g_string_append_printf (sbuf, " R%d", ins->sreg3);
463 switch (ins->opcode) {
474 if (!ins->inst_false_bb)
475 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
477 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
484 g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
485 for (i = 0; i < ins->inst_phi_args [0]; i++) {
487 g_string_append_printf (sbuf, ", ");
488 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
490 g_string_append_printf (sbuf, ")]");
494 case OP_OUTARG_VTRETADDR:
495 g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
498 case OP_GSHAREDVT_ARG_REGOFFSET:
499 g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
503 g_string_append_printf (sbuf, " %s", ins->klass->name);
509 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
513 if (spec [MONO_INST_DEST]) {
514 int bank = dreg_bank (spec);
515 if (is_soft_reg (ins->dreg, bank)) {
516 if (spec [MONO_INST_DEST] == 'b') {
517 if (ins->inst_offset == 0)
518 g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
520 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
523 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
524 } else if (spec [MONO_INST_DEST] == 'b') {
525 if (ins->inst_offset == 0)
526 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
528 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
530 g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
532 if (spec [MONO_INST_SRC1]) {
533 int bank = sreg1_bank (spec);
534 if (is_soft_reg (ins->sreg1, bank)) {
535 if (spec [MONO_INST_SRC1] == 'b')
536 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
538 g_string_append_printf (sbuf, " R%d", ins->sreg1);
539 } else if (spec [MONO_INST_SRC1] == 'b')
540 g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
542 g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
544 num_sregs = mono_inst_get_src_registers (ins, sregs);
545 for (j = 1; j < num_sregs; ++j) {
546 int bank = sreg_bank (j, spec);
547 if (is_soft_reg (sregs [j], bank))
548 g_string_append_printf (sbuf, " R%d", sregs [j]);
550 g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
553 switch (ins->opcode) {
555 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
557 #if defined(TARGET_X86) || defined(TARGET_AMD64)
558 case OP_X86_PUSH_IMM:
560 case OP_ICOMPARE_IMM:
568 case OP_STORE_MEMBASE_IMM:
569 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
573 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
576 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
579 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
582 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
585 case OP_CALL_MEMBASE:
591 case OP_VCALL_MEMBASE:
594 case OP_VCALL2_MEMBASE:
596 case OP_VOIDCALL_MEMBASE:
598 MonoCallInst *call = (MonoCallInst*)ins;
601 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
603 * These are lowered opcodes, but they are in the .md files since the old
604 * JIT passes them to backends.
607 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
611 char *full_name = mono_method_full_name (call->method, TRUE);
612 g_string_append_printf (sbuf, " [%s]", full_name);
614 } else if (call->fptr_is_patch) {
615 MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
617 g_string_append_printf (sbuf, " ");
619 } else if (call->fptr) {
620 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
622 g_string_append_printf (sbuf, " [%s]", info->name);
625 list = call->out_ireg_args;
630 regpair = (guint32)(gssize)(list->data);
631 hreg = regpair >> 24;
632 reg = regpair & 0xffffff;
634 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
636 list = g_slist_next (list);
638 list = call->out_freg_args;
643 regpair = (guint32)(gssize)(list->data);
644 hreg = regpair >> 24;
645 reg = regpair & 0xffffff;
647 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
649 list = g_slist_next (list);
654 case OP_CALL_HANDLER:
655 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
677 if (!ins->inst_false_bb)
678 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
680 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
682 case OP_LIVERANGE_START:
683 case OP_LIVERANGE_END:
684 case OP_GC_LIVENESS_DEF:
685 case OP_GC_LIVENESS_USE:
686 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
688 case OP_IL_SEQ_POINT:
690 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
697 case OP_COND_EXC_NE_UN:
698 case OP_COND_EXC_GE_UN:
699 case OP_COND_EXC_GT_UN:
700 case OP_COND_EXC_LE_UN:
701 case OP_COND_EXC_LT_UN:
706 case OP_COND_EXC_IEQ:
707 case OP_COND_EXC_IGE:
708 case OP_COND_EXC_IGT:
709 case OP_COND_EXC_ILE:
710 case OP_COND_EXC_ILT:
711 case OP_COND_EXC_INE_UN:
712 case OP_COND_EXC_IGE_UN:
713 case OP_COND_EXC_IGT_UN:
714 case OP_COND_EXC_ILE_UN:
715 case OP_COND_EXC_ILT_UN:
716 case OP_COND_EXC_IOV:
717 case OP_COND_EXC_INO:
719 case OP_COND_EXC_INC:
720 g_string_append_printf (sbuf, " %s", ins->inst_p1);
726 if (spec [MONO_INST_CLOB])
727 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
732 print_regtrack (RegTrack *t, int num)
738 for (i = 0; i < num; ++i) {
741 if (i >= MONO_MAX_IREGS) {
742 g_snprintf (buf, sizeof(buf), "R%d", i);
745 r = mono_arch_regname (i);
746 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
752 mono_print_ins_index (int i, MonoInst *ins)
755 #endif /* !defined(DISABLE_LOGGING) */
758 mono_print_ins (MonoInst *ins)
760 mono_print_ins_index (-1, ins);
764 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
767 * If this function is called multiple times, the new instructions are inserted
768 * in the proper order.
770 mono_bblock_insert_before_ins (bb, ins, to_insert);
774 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
777 * If this function is called multiple times, the new instructions are inserted in
780 mono_bblock_insert_after_ins (bb, *last, to_insert);
786 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
788 if (vreg_is_ref (cfg, reg))
789 return MONO_REG_INT_REF;
790 else if (vreg_is_mp (cfg, reg))
791 return MONO_REG_INT_MP;
797 * Force the spilling of the variable in the symbolic register 'reg', and free
798 * the hreg it was assigned to.
801 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
805 MonoRegState *rs = cfg->rs;
807 sel = rs->vassign [reg];
809 /* the vreg we need to spill lives in another logical reg bank */
810 bank = translate_bank (cfg->rs, bank, sel);
812 /*i = rs->isymbolic [sel];
813 g_assert (i == reg);*/
815 spill = ++cfg->spill_count;
816 rs->vassign [i] = -spill - 1;
817 if (G_UNLIKELY (bank))
818 mono_regstate_free_general (rs, sel, bank);
820 mono_regstate_free_int (rs, sel);
821 /* we need to create a spill var and insert a load to sel after the current instruction */
822 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
824 load->inst_basereg = cfg->frame_reg;
825 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
826 insert_after_ins (bb, ins, last, load);
827 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
828 if (G_UNLIKELY (bank))
829 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
831 i = mono_regstate_alloc_int (rs, regmask (sel));
834 if (G_UNLIKELY (bank))
835 mono_regstate_free_general (rs, sel, bank);
837 mono_regstate_free_int (rs, sel);
841 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
844 int i, sel, spill, num_sregs;
845 int sregs [MONO_MAX_SRC_REGS];
846 MonoRegState *rs = cfg->rs;
848 g_assert (bank < MONO_NUM_REGBANKS);
850 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
851 /* exclude the registers in the current instruction */
852 num_sregs = mono_inst_get_src_registers (ins, sregs);
853 for (i = 0; i < num_sregs; ++i) {
854 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
855 if (is_soft_reg (sregs [i], bank))
856 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
858 regmask &= ~ (regmask (sregs [i]));
859 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
862 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
863 regmask &= ~ (regmask (ins->dreg));
864 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
867 DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
868 g_assert (regmask); /* need at least a register we can free */
870 /* we should track prev_use and spill the register that's farther */
871 if (G_UNLIKELY (bank)) {
872 for (i = 0; i < regbank_size [bank]; ++i) {
873 if (regmask & (regmask (i))) {
876 /* the vreg we need to load lives in another logical bank */
877 bank = translate_bank (cfg->rs, bank, sel);
879 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
884 i = rs->symbolic [bank] [sel];
885 spill = ++cfg->spill_count;
886 rs->vassign [i] = -spill - 1;
887 mono_regstate_free_general (rs, sel, bank);
890 for (i = 0; i < MONO_MAX_IREGS; ++i) {
891 if (regmask & (regmask (i))) {
893 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
898 i = rs->isymbolic [sel];
899 spill = ++cfg->spill_count;
900 rs->vassign [i] = -spill - 1;
901 mono_regstate_free_int (rs, sel);
904 /* we need to create a spill var and insert a load to sel after the current instruction */
905 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
907 load->inst_basereg = cfg->frame_reg;
908 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
909 insert_after_ins (bb, ins, last, load);
910 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
911 if (G_UNLIKELY (bank))
912 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
914 i = mono_regstate_alloc_int (rs, regmask (sel));
923 * Free up the hreg HREG by spilling the vreg allocated to it.
926 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
928 if (G_UNLIKELY (bank)) {
929 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
930 bank = translate_bank (cfg->rs, bank, hreg);
931 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
932 spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
936 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
937 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
938 spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
944 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
948 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
954 mono_bblock_insert_after_ins (bb, ins, copy);
957 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
961 static inline const char*
962 regbank_to_string (int bank)
964 if (bank == MONO_REG_INT_REF)
966 else if (bank == MONO_REG_INT_MP)
973 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
975 MonoInst *store, *def;
977 bank = get_vreg_bank (cfg, prev_reg, bank);
979 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
981 store->inst_destbasereg = cfg->frame_reg;
982 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
984 mono_bblock_insert_after_ins (bb, ins, store);
986 } else if (insert_before) {
987 insert_before_ins (bb, insert_before, store);
989 g_assert_not_reached ();
991 DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
993 if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
994 g_assert (prev_reg != -1);
995 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
996 def->inst_c0 = spill;
998 mono_bblock_insert_after_ins (bb, store, def);
1002 /* flags used in reginfo->flags */
1004 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
1005 MONO_FP_NEEDS_SPILL = regmask (1),
1006 MONO_FP_NEEDS_LOAD = regmask (2)
1010 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1014 if (info && info->preferred_mask) {
1015 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1017 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1022 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1024 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1030 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1034 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1037 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1043 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1045 if (G_UNLIKELY (bank))
1046 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1048 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1052 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1054 if (G_UNLIKELY (bank)) {
1057 g_assert (reg >= regbank_size [bank]);
1058 g_assert (hreg < regbank_size [bank]);
1059 g_assert (! is_global_freg (hreg));
1061 rs->vassign [reg] = hreg;
1062 rs->symbolic [bank] [hreg] = reg;
1063 rs->free_mask [bank] &= ~ (regmask (hreg));
1065 mirrored_bank = get_mirrored_bank (bank);
1066 if (mirrored_bank == -1)
1069 /* Make sure the other logical reg bank that this bank shares
1070 * a single hard reg bank knows that this hard reg is not free.
1072 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1074 /* Mark the other logical bank that the this bank shares
1075 * a single hard reg bank with as mirrored.
1077 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1081 g_assert (reg >= MONO_MAX_IREGS);
1082 g_assert (hreg < MONO_MAX_IREGS);
1083 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1084 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1085 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1086 g_assert (! is_global_ireg (hreg));
1089 rs->vassign [reg] = hreg;
1090 rs->isymbolic [hreg] = reg;
1091 rs->ifree_mask &= ~ (regmask (hreg));
1095 static inline regmask_t
1096 get_callee_mask (const char spec)
1098 if (G_UNLIKELY (reg_bank (spec)))
1099 return regbank_callee_regs [reg_bank (spec)];
1100 return MONO_ARCH_CALLEE_REGS;
1103 static gint8 desc_to_fixed_reg [256];
1104 static gboolean desc_to_fixed_reg_inited = FALSE;
1107 * Local register allocation.
1108 * We first scan the list of instructions and we save the liveness info of
1109 * each register (when the register is first used, when it's value is set etc.).
1110 * We also reverse the list of instructions because assigning registers backwards allows
1111 * for more tricks to be used.
1114 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1116 MonoInst *ins, *prev, *last;
1118 MonoRegState *rs = cfg->rs;
1122 unsigned char spec_src1, spec_dest;
1124 #if MONO_ARCH_USE_FPSTACK
1125 gboolean has_fp = FALSE;
1130 int sregs [MONO_MAX_SRC_REGS];
1135 if (!desc_to_fixed_reg_inited) {
1136 for (i = 0; i < 256; ++i)
1137 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1138 desc_to_fixed_reg_inited = TRUE;
1140 /* Validate the cpu description against the info in mini-ops.h */
1141 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1142 for (i = OP_LOAD; i < OP_LAST; ++i) {
1145 spec = ins_get_spec (i);
1146 ispec = INS_INFO (i);
1148 if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1149 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1150 if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1151 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1152 if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1153 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1158 rs->next_vreg = bb->max_vreg;
1159 mono_regstate_assign (rs);
1161 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1162 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1163 rs->free_mask [i] = regbank_callee_regs [i];
1165 max = rs->next_vreg;
1167 if (cfg->reginfo && cfg->reginfo_len < max)
1168 cfg->reginfo = NULL;
1170 reginfo = (RegTrack *)cfg->reginfo;
1172 cfg->reginfo_len = MAX (1024, max * 2);
1173 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1174 cfg->reginfo = reginfo;
1177 g_assert (cfg->reginfo_len >= rs->next_vreg);
1179 if (cfg->verbose_level > 1) {
1180 /* print_regtrack reads the info of all variables */
1181 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1185 * For large methods, next_vreg can be very large, so g_malloc0 time can
1186 * be prohibitive. So we manually init the reginfo entries used by the
1189 for (ins = bb->code; ins; ins = ins->next) {
1190 gboolean modify = FALSE;
1192 spec = ins_get_spec (ins->opcode);
1194 if ((ins->dreg != -1) && (ins->dreg < max)) {
1195 memset (®info [ins->dreg], 0, sizeof (RegTrack));
1196 #if SIZEOF_REGISTER == 4
1197 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1199 * In the new IR, the two vregs of the regpair do not alias the
1200 * original long vreg. shift the vreg here so the rest of the
1201 * allocator doesn't have to care about it.
1204 memset (®info [ins->dreg + 1], 0, sizeof (RegTrack));
1209 num_sregs = mono_inst_get_src_registers (ins, sregs);
1210 for (j = 0; j < num_sregs; ++j) {
1211 g_assert (sregs [j] != -1);
1212 if (sregs [j] < max) {
1213 memset (®info [sregs [j]], 0, sizeof (RegTrack));
1214 #if SIZEOF_REGISTER == 4
1215 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1218 memset (®info [sregs [j] + 1], 0, sizeof (RegTrack));
1224 mono_inst_set_src_registers (ins, sregs);
1227 /*if (cfg->opt & MONO_OPT_COPYPROP)
1228 local_copy_prop (cfg, ins);*/
1231 DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1232 /* forward pass on the instructions to collect register liveness info */
1233 MONO_BB_FOR_EACH_INS (bb, ins) {
1234 spec = ins_get_spec (ins->opcode);
1235 spec_dest = spec [MONO_INST_DEST];
1237 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1238 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1241 DEBUG (mono_print_ins_index (i, ins));
1243 num_sregs = mono_inst_get_src_registers (ins, sregs);
1245 #if MONO_ARCH_USE_FPSTACK
1246 if (dreg_is_fp (spec)) {
1249 for (j = 0; j < num_sregs; ++j) {
1250 if (sreg_is_fp (j, spec))
1256 for (j = 0; j < num_sregs; ++j) {
1257 int sreg = sregs [j];
1258 int sreg_spec = spec [MONO_INST_SRC1 + j];
1260 bank = sreg_bank (j, spec);
1261 g_assert (sreg != -1);
1262 if (is_soft_reg (sreg, bank))
1263 /* This means the vreg is not local to this bb */
1264 g_assert (reginfo [sreg].born_in > 0);
1265 rs->vassign [sreg] = -1;
1266 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1267 //reginfo [ins->sreg2].last_use = i;
1268 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1269 /* The virtual register is allocated sequentially */
1270 rs->vassign [sreg + 1] = -1;
1271 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1272 //reginfo [ins->sreg2 + 1].last_use = i;
1273 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1274 reginfo [sreg + 1].born_in = i;
1280 mono_inst_set_src_registers (ins, sregs);
1285 bank = dreg_bank (spec);
1286 if (spec_dest != 'b') /* it's not just a base register */
1287 reginfo [ins->dreg].killed_in = i;
1288 g_assert (ins->dreg != -1);
1289 rs->vassign [ins->dreg] = -1;
1290 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1291 //reginfo [ins->dreg].last_use = i;
1292 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1293 reginfo [ins->dreg].born_in = i;
1295 dest_dreg = desc_to_fixed_reg [spec_dest];
1296 if (dest_dreg != -1)
1297 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1299 #ifdef MONO_ARCH_INST_FIXED_MASK
1300 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1303 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1304 /* The virtual register is allocated sequentially */
1305 rs->vassign [ins->dreg + 1] = -1;
1306 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1307 //reginfo [ins->dreg + 1].last_use = i;
1308 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1309 reginfo [ins->dreg + 1].born_in = i;
1310 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1311 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1322 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1323 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1325 int dest_dreg, clob_reg;
1326 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1327 int dreg_high, sreg1_high;
1328 regmask_t dreg_mask, mask;
1329 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1330 regmask_t dreg_fixed_mask;
1331 const unsigned char *ip;
1333 spec = ins_get_spec (ins->opcode);
1334 spec_src1 = spec [MONO_INST_SRC1];
1335 spec_dest = spec [MONO_INST_DEST];
1341 dreg_mask = get_callee_mask (spec_dest);
1342 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1343 prev_sregs [j] = -1;
1344 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1345 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1346 #ifdef MONO_ARCH_INST_FIXED_MASK
1347 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1349 sreg_fixed_masks [j] = 0;
1353 DEBUG (printf ("processing:"));
1354 DEBUG (mono_print_ins_index (i, ins));
1363 dest_dreg = desc_to_fixed_reg [spec_dest];
1364 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1365 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1367 #ifdef MONO_ARCH_INST_FIXED_MASK
1368 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1370 dreg_fixed_mask = 0;
1373 num_sregs = mono_inst_get_src_registers (ins, sregs);
1376 * TRACK FIXED SREG2, 3, ...
1378 for (j = 1; j < num_sregs; ++j) {
1379 int sreg = sregs [j];
1380 int dest_sreg = dest_sregs [j];
1382 if (dest_sreg == -1)
1390 * We need to special case this, since on x86, there are only 3
1391 * free registers, and the code below assigns one of them to
1392 * sreg, so we can run out of registers when trying to assign
1393 * dreg. Instead, we just set up the register masks, and let the
1394 * normal sreg2 assignment code handle this. It would be nice to
1395 * do this for all the fixed reg cases too, but there is too much
1399 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1400 sreg_masks [j] = regmask (dest_sreg);
1401 for (k = 0; k < num_sregs; ++k) {
1403 sreg_masks [k] &= ~ (regmask (dest_sreg));
1407 * Spill sreg1/2 if they are assigned to dest_sreg.
1409 for (k = 0; k < num_sregs; ++k) {
1410 if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1411 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1415 * We can also run out of registers while processing sreg2 if sreg3 is
1416 * assigned to another hreg, so spill sreg3 now.
1418 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1419 spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1424 if (rs->ifree_mask & (regmask (dest_sreg))) {
1425 if (is_global_ireg (sreg)) {
1427 /* Argument already in hard reg, need to copy */
1428 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1429 insert_before_ins (bb, ins, copy);
1430 for (k = 0; k < num_sregs; ++k) {
1432 sreg_masks [k] &= ~ (regmask (dest_sreg));
1435 dreg_mask &= ~ (regmask (dest_sreg));
1437 val = rs->vassign [sreg];
1439 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1440 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1441 } else if (val < -1) {
1443 g_assert_not_reached ();
1445 /* Argument already in hard reg, need to copy */
1446 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1449 insert_before_ins (bb, ins, copy);
1450 for (k = 0; k < num_sregs; ++k) {
1452 sreg_masks [k] &= ~ (regmask (dest_sreg));
1455 * Prevent the dreg from being allocated to dest_sreg
1456 * too, since it could force sreg1 to be allocated to
1457 * the same reg on x86.
1459 dreg_mask &= ~ (regmask (dest_sreg));
1463 gboolean need_spill = TRUE;
1464 gboolean need_assign = TRUE;
1467 dreg_mask &= ~ (regmask (dest_sreg));
1468 for (k = 0; k < num_sregs; ++k) {
1470 sreg_masks [k] &= ~ (regmask (dest_sreg));
1474 * First check if dreg is assigned to dest_sreg2, since we
1475 * can't spill a dreg.
1477 if (spec [MONO_INST_DEST])
1478 val = rs->vassign [ins->dreg];
1481 if (val == dest_sreg && ins->dreg != sreg) {
1483 * the destination register is already assigned to
1484 * dest_sreg2: we need to allocate another register for it
1485 * and then copy from this to dest_sreg2.
1488 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
1489 g_assert (new_dest >= 0);
1490 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1492 prev_dreg = ins->dreg;
1493 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1494 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1495 mono_regstate_free_int (rs, dest_sreg);
1499 if (is_global_ireg (sreg)) {
1500 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1501 insert_before_ins (bb, ins, copy);
1502 need_assign = FALSE;
1505 val = rs->vassign [sreg];
1506 if (val == dest_sreg) {
1507 /* sreg2 is already assigned to the correct register */
1509 } else if (val < -1) {
1510 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1511 } else if (val >= 0) {
1512 /* sreg2 already assigned to another register */
1514 * We couldn't emit a copy from val to dest_sreg2, because
1515 * val might be spilled later while processing this
1516 * instruction. So we spill sreg2 so it can be allocated to
1519 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1524 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1528 if (rs->vassign [sreg] < -1) {
1531 /* Need to emit a spill store */
1532 spill = - rs->vassign [sreg] - 1;
1533 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1535 /* force-set sreg2 */
1536 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1539 sregs [j] = dest_sreg;
1541 mono_inst_set_src_registers (ins, sregs);
1546 bank = dreg_bank (spec);
1547 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1548 prev_dreg = ins->dreg;
1551 if (spec_dest == 'b') {
1553 * The dest reg is read by the instruction, not written, so
1554 * avoid allocating sreg1/sreg2 to the same reg.
1556 if (dest_sregs [0] != -1)
1557 dreg_mask &= ~ (regmask (dest_sregs [0]));
1558 for (j = 1; j < num_sregs; ++j) {
1559 if (dest_sregs [j] != -1)
1560 dreg_mask &= ~ (regmask (dest_sregs [j]));
1563 val = rs->vassign [ins->dreg];
1564 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1565 /* DREG is already allocated to a register needed for sreg1 */
1566 spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1571 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1572 * various complex situations.
1574 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1575 guint32 dreg2, dest_dreg2;
1577 g_assert (is_soft_reg (ins->dreg, bank));
1579 if (dest_dreg != -1) {
1580 if (rs->vassign [ins->dreg] != dest_dreg)
1581 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1583 dreg2 = ins->dreg + 1;
1584 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1585 if (dest_dreg2 != -1) {
1586 if (rs->vassign [dreg2] != dest_dreg2)
1587 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1592 if (dreg_fixed_mask) {
1594 if (is_global_ireg (ins->dreg)) {
1596 * The argument is already in a hard reg, but that reg is
1597 * not usable by this instruction, so allocate a new one.
1599 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1601 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1602 mono_regstate_free_int (rs, val);
1608 dreg_mask &= dreg_fixed_mask;
1611 if (is_soft_reg (ins->dreg, bank)) {
1612 val = rs->vassign [ins->dreg];
1617 /* the register gets spilled after this inst */
1620 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
1621 assign_reg (cfg, rs, ins->dreg, val, bank);
1623 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1626 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1630 /* Handle regpairs */
1631 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1632 int reg2 = prev_dreg + 1;
1635 g_assert (prev_dreg > -1);
1636 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1637 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1640 mask &= ~regmask (X86_ECX);
1642 val = rs->vassign [reg2];
1646 /* the register gets spilled after this inst */
1649 val = mono_regstate_alloc_int (rs, mask);
1651 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1653 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1656 if (! (mask & (regmask (val)))) {
1657 val = mono_regstate_alloc_int (rs, mask);
1659 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1661 /* Reallocate hreg to the correct register */
1662 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1664 mono_regstate_free_int (rs, rs->vassign [reg2]);
1668 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1669 assign_reg (cfg, rs, reg2, val, bank);
1672 ins->backend.reg3 = val;
1674 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1675 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1676 mono_regstate_free_int (rs, val);
1680 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1682 * In theory, we could free up the hreg even if the vreg is alive,
1683 * but branches inside bblocks force us to assign the same hreg
1684 * to a vreg every time it is encountered.
1686 int dreg = rs->vassign [prev_dreg];
1687 g_assert (dreg >= 0);
1688 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1689 if (G_UNLIKELY (bank))
1690 mono_regstate_free_general (rs, dreg, bank);
1692 mono_regstate_free_int (rs, dreg);
1693 rs->vassign [prev_dreg] = -1;
1696 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1697 /* this instruction only outputs to dest_dreg, need to copy */
1698 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1699 ins->dreg = dest_dreg;
1701 if (G_UNLIKELY (bank)) {
1702 /* the register we need to free up may be used in another logical regbank
1703 * so do a translate just in case.
1705 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1706 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1707 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1710 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1711 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1715 if (spec_dest == 'b') {
1717 * The dest reg is read by the instruction, not written, so
1718 * avoid allocating sreg1/sreg2 to the same reg.
1720 for (j = 0; j < num_sregs; ++j)
1721 if (!sreg_bank (j, spec))
1722 sreg_masks [j] &= ~ (regmask (ins->dreg));
1728 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1729 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1730 free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1733 if (spec [MONO_INST_CLOB] == 'c') {
1734 int j, s, dreg, dreg2, cur_bank;
1737 clob_mask = MONO_ARCH_CALLEE_REGS;
1739 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1741 * Need to avoid spilling the dreg since the dreg is not really
1742 * clobbered by the call.
1744 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1745 dreg = rs->vassign [prev_dreg];
1749 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1750 dreg2 = rs->vassign [prev_dreg + 1];
1754 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1756 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1757 if ((j != dreg) && (j != dreg2))
1758 free_up_hreg (cfg, bb, tmp, ins, j, 0);
1759 else if (rs->isymbolic [j])
1760 /* The hreg is assigned to the dreg of this instruction */
1761 rs->vassign [rs->isymbolic [j]] = -1;
1762 mono_regstate_free_int (rs, j);
1767 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1768 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1769 clob_mask = regbank_callee_regs [cur_bank];
1770 if ((prev_dreg != -1) && reg_bank (spec_dest))
1771 dreg = rs->vassign [prev_dreg];
1775 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1777 /* we are looping though the banks in the outer loop
1778 * so, we don't need to deal with mirrored hregs
1779 * because we will get them in one of the other bank passes.
1781 if (is_hreg_mirrored (rs, cur_bank, j))
1785 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1787 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1788 else if (rs->symbolic [cur_bank] [j])
1789 /* The hreg is assigned to the dreg of this instruction */
1790 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1791 mono_regstate_free_general (rs, j, cur_bank);
1799 * TRACK ARGUMENT REGS
1801 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1802 MonoCallInst *call = (MonoCallInst*)ins;
1806 * This needs to be done before assigning sreg1, so sreg1 will
1807 * not be assigned one of the argument regs.
1811 * Assign all registers in call->out_reg_args to the proper
1812 * argument registers.
1815 list = call->out_ireg_args;
1821 regpair = (guint32)(gssize)(list->data);
1822 hreg = regpair >> 24;
1823 reg = regpair & 0xffffff;
1825 assign_reg (cfg, rs, reg, hreg, 0);
1827 sreg_masks [0] &= ~(regmask (hreg));
1829 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1831 list = g_slist_next (list);
1835 list = call->out_freg_args;
1841 regpair = (guint32)(gssize)(list->data);
1842 hreg = regpair >> 24;
1843 reg = regpair & 0xffffff;
1845 assign_reg (cfg, rs, reg, hreg, 1);
1847 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1849 list = g_slist_next (list);
1857 bank = sreg1_bank (spec);
1858 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1859 int sreg1 = sregs [0];
1860 int dest_sreg1 = dest_sregs [0];
1862 g_assert (is_soft_reg (sreg1, bank));
1864 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1865 if (dest_sreg1 != -1)
1866 g_assert (dest_sreg1 == ins->dreg);
1867 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1868 g_assert (val >= 0);
1870 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1872 g_assert_not_reached ();
1874 assign_reg (cfg, rs, sreg1, val, bank);
1876 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1878 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1879 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1880 g_assert (val >= 0);
1882 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1884 g_assert_not_reached ();
1886 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1888 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1890 /* Skip rest of this section */
1891 dest_sregs [0] = -1;
1894 if (sreg_fixed_masks [0]) {
1896 if (is_global_ireg (sregs [0])) {
1898 * The argument is already in a hard reg, but that reg is
1899 * not usable by this instruction, so allocate a new one.
1901 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1903 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1904 mono_regstate_free_int (rs, val);
1905 dest_sregs [0] = val;
1907 /* Fall through to the dest_sreg1 != -1 case */
1910 sreg_masks [0] &= sreg_fixed_masks [0];
1913 if (dest_sregs [0] != -1) {
1914 sreg_masks [0] = regmask (dest_sregs [0]);
1916 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1917 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1919 if (is_global_ireg (sregs [0])) {
1920 /* The argument is already in a hard reg, need to copy */
1921 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1922 insert_before_ins (bb, ins, copy);
1923 sregs [0] = dest_sregs [0];
1927 if (is_soft_reg (sregs [0], bank)) {
1928 val = rs->vassign [sregs [0]];
1929 prev_sregs [0] = sregs [0];
1933 /* the register gets spilled after this inst */
1937 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1939 * Allocate the same hreg to sreg1 as well so the
1940 * peephole can get rid of the move.
1942 sreg_masks [0] = regmask (ins->dreg);
1945 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1946 /* Allocate the same reg to sreg1 to avoid a copy later */
1947 sreg_masks [0] = regmask (ins->dreg);
1949 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], ®info [sregs [0]], bank);
1950 assign_reg (cfg, rs, sregs [0], val, bank);
1951 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1955 * Need to insert before the instruction since it can
1958 create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1961 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1962 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1963 insert_before_ins (bb, ins, copy);
1964 for (j = 1; j < num_sregs; ++j)
1965 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1966 val = dest_sregs [0];
1972 prev_sregs [0] = -1;
1974 mono_inst_set_src_registers (ins, sregs);
1976 for (j = 1; j < num_sregs; ++j)
1977 sreg_masks [j] &= ~(regmask (sregs [0]));
1979 /* Handle the case when sreg1 is a regpair but dreg is not */
1980 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1981 int reg2 = prev_sregs [0] + 1;
1984 g_assert (prev_sregs [0] > -1);
1985 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1986 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1987 val = rs->vassign [reg2];
1991 /* the register gets spilled after this inst */
1994 val = mono_regstate_alloc_int (rs, mask);
1996 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1998 g_assert_not_reached ();
2001 if (! (mask & (regmask (val)))) {
2002 /* The vreg is already allocated to a wrong hreg */
2004 g_assert_not_reached ();
2006 val = mono_regstate_alloc_int (rs, mask);
2008 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2010 /* Reallocate hreg to the correct register */
2011 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2013 mono_regstate_free_int (rs, rs->vassign [reg2]);
2019 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2020 assign_reg (cfg, rs, reg2, val, bank);
2023 /* Handle dreg==sreg1 */
2024 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2025 MonoInst *sreg2_copy = NULL;
2027 int bank = reg_bank (spec_src1);
2029 if (ins->dreg == sregs [1]) {
2031 * copying sreg1 to dreg could clobber sreg2, so allocate a new
2034 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2036 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2037 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2038 prev_sregs [1] = sregs [1] = reg2;
2040 if (G_UNLIKELY (bank))
2041 mono_regstate_free_general (rs, reg2, bank);
2043 mono_regstate_free_int (rs, reg2);
2046 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2047 /* Copying sreg1_high to dreg could also clobber sreg2 */
2048 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2050 g_assert_not_reached ();
2053 * sreg1 and dest are already allocated to the same regpair by the
2054 * SREG1 allocation code.
2056 g_assert (sregs [0] == ins->dreg);
2057 g_assert (dreg_high == sreg1_high);
2060 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2061 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2062 insert_before_ins (bb, ins, copy);
2065 insert_before_ins (bb, copy, sreg2_copy);
2068 * Need to prevent sreg2 to be allocated to sreg1, since that
2069 * would screw up the previous copy.
2071 sreg_masks [1] &= ~ (regmask (sregs [0]));
2072 /* we set sreg1 to dest as well */
2073 prev_sregs [0] = sregs [0] = ins->dreg;
2074 sreg_masks [1] &= ~ (regmask (ins->dreg));
2076 mono_inst_set_src_registers (ins, sregs);
2079 * TRACK SREG2, 3, ...
2081 for (j = 1; j < num_sregs; ++j) {
2084 bank = sreg_bank (j, spec);
2085 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2086 g_assert_not_reached ();
2088 if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2090 * Argument already in a global hard reg, copy it to the fixed reg, without
2091 * allocating it to the fixed reg.
2093 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2094 insert_before_ins (bb, ins, copy);
2095 sregs [j] = dest_sregs [j];
2096 } else if (is_soft_reg (sregs [j], bank)) {
2097 val = rs->vassign [sregs [j]];
2099 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2101 * The sreg is already allocated to a hreg, but not to the fixed
2102 * reg required by the instruction. Spill the sreg, so it can be
2103 * allocated to the fixed reg by the code below.
2105 /* Currently, this code should only be hit for CAS */
2106 spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2107 val = rs->vassign [sregs [j]];
2113 /* the register gets spilled after this inst */
2116 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], ®info [sregs [j]], bank);
2117 assign_reg (cfg, rs, sregs [j], val, bank);
2118 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2121 * Need to insert before the instruction since it can
2124 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2128 for (k = j + 1; k < num_sregs; ++k)
2129 sreg_masks [k] &= ~ (regmask (sregs [j]));
2132 prev_sregs [j] = -1;
2135 mono_inst_set_src_registers (ins, sregs);
2138 /* Do this only for CAS for now */
2139 for (j = 1; j < num_sregs; ++j) {
2140 int sreg = sregs [j];
2141 int dest_sreg = dest_sregs [j];
2143 if (j == 2 && dest_sreg != -1) {
2146 g_assert (sreg == dest_sreg);
2148 for (k = 0; k < num_sregs; ++k) {
2150 g_assert (sregs [k] != dest_sreg);
2155 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2156 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2157 mono_regstate_free_int (rs, ins->sreg1);
2159 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2160 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2161 mono_regstate_free_int (rs, ins->sreg2);
2164 DEBUG (mono_print_ins_index (i, ins));
2167 // FIXME: Set MAX_FREGS to 8
2168 // FIXME: Optimize generated code
2169 #if MONO_ARCH_USE_FPSTACK
2171 * Make a forward pass over the code, simulating the fp stack, making sure the
2172 * arguments required by the fp opcodes are at the top of the stack.
2175 MonoInst *prev = NULL;
2179 g_assert (num_sregs <= 2);
2181 for (ins = bb->code; ins; ins = ins->next) {
2182 spec = ins_get_spec (ins->opcode);
2184 DEBUG (printf ("processing:"));
2185 DEBUG (mono_print_ins_index (0, ins));
2187 if (ins->opcode == OP_FMOVE) {
2188 /* Do it by renaming the source to the destination on the stack */
2189 // FIXME: Is this correct ?
2190 for (i = 0; i < sp; ++i)
2191 if (fpstack [i] == ins->sreg1)
2192 fpstack [i] = ins->dreg;
2197 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2198 /* Arg1 must be in %st(1) */
2202 while ((i < sp) && (fpstack [i] != ins->sreg1))
2206 if (sp - 1 - i > 0) {
2207 /* First move it to %st(0) */
2208 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2210 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2211 fxch->inst_imm = sp - 1 - i;
2213 mono_bblock_insert_after_ins (bb, prev, fxch);
2216 tmp = fpstack [sp - 1];
2217 fpstack [sp - 1] = fpstack [i];
2221 /* Then move it to %st(1) */
2222 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2224 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2227 mono_bblock_insert_after_ins (bb, prev, fxch);
2230 tmp = fpstack [sp - 1];
2231 fpstack [sp - 1] = fpstack [sp - 2];
2232 fpstack [sp - 2] = tmp;
2235 if (sreg2_is_fp (spec)) {
2238 if (fpstack [sp - 1] != ins->sreg2) {
2242 while ((i < sp) && (fpstack [i] != ins->sreg2))
2246 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2248 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2249 fxch->inst_imm = sp - 1 - i;
2251 mono_bblock_insert_after_ins (bb, prev, fxch);
2254 tmp = fpstack [sp - 1];
2255 fpstack [sp - 1] = fpstack [i];
2262 if (sreg1_is_fp (spec)) {
2265 if (fpstack [sp - 1] != ins->sreg1) {
2269 while ((i < sp) && (fpstack [i] != ins->sreg1))
2273 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2275 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2276 fxch->inst_imm = sp - 1 - i;
2278 mono_bblock_insert_after_ins (bb, prev, fxch);
2281 tmp = fpstack [sp - 1];
2282 fpstack [sp - 1] = fpstack [i];
2289 if (dreg_is_fp (spec)) {
2291 fpstack [sp ++] = ins->dreg;
2294 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2296 for (i = 0; i < sp; ++i)
2297 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2304 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2305 /* Remove remaining items from the fp stack */
2307 * These can remain for example as a result of a dead fmove like in
2308 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2311 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2312 mono_add_ins_to_end (bb, ins);
2321 mono_opcode_to_cond (int opcode)
2333 case OP_COND_EXC_EQ:
2334 case OP_COND_EXC_IEQ:
2343 case OP_COND_EXC_NE_UN:
2344 case OP_COND_EXC_INE_UN:
2345 case OP_CMOV_INE_UN:
2346 case OP_CMOV_LNE_UN:
2373 case OP_COND_EXC_LT:
2374 case OP_COND_EXC_ILT:
2387 case OP_COND_EXC_GT:
2388 case OP_COND_EXC_IGT:
2397 case OP_COND_EXC_LE_UN:
2398 case OP_COND_EXC_ILE_UN:
2399 case OP_CMOV_ILE_UN:
2400 case OP_CMOV_LLE_UN:
2407 case OP_CMOV_IGE_UN:
2408 case OP_CMOV_LGE_UN:
2419 case OP_COND_EXC_LT_UN:
2420 case OP_COND_EXC_ILT_UN:
2421 case OP_CMOV_ILT_UN:
2422 case OP_CMOV_LLT_UN:
2433 case OP_COND_EXC_GT_UN:
2434 case OP_COND_EXC_IGT_UN:
2435 case OP_CMOV_IGT_UN:
2436 case OP_CMOV_LGT_UN:
2439 printf ("%s\n", mono_inst_name (opcode));
2440 g_assert_not_reached ();
2441 return (CompRelation)0;
2446 mono_negate_cond (CompRelation cond)
2470 g_assert_not_reached ();
2475 mono_opcode_to_type (int opcode, int cmp_opcode)
2477 if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2479 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2481 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2483 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2485 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2487 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2489 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2491 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2493 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2494 switch (cmp_opcode) {
2496 case OP_ICOMPARE_IMM:
2502 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2508 * mono_peephole_ins:
2510 * Perform some architecture independent peephole optimizations.
2513 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2515 int filter = FILTER_IL_SEQ_POINT;
2516 MonoInst *last_ins = mono_inst_prev (ins, filter);
2518 switch (ins->opcode) {
2520 /* remove unnecessary multiplication with 1 */
2521 if (ins->inst_imm == 1) {
2522 if (ins->dreg != ins->sreg1)
2523 ins->opcode = OP_MOVE;
2525 MONO_DELETE_INS (bb, ins);
2528 case OP_LOAD_MEMBASE:
2529 case OP_LOADI4_MEMBASE:
2531 * Note: if reg1 = reg2 the load op is removed
2533 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2534 * OP_LOAD_MEMBASE offset(basereg), reg2
2536 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2537 * OP_MOVE reg1, reg2
2539 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2540 last_ins = mono_inst_prev (ins, filter);
2542 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2543 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2544 ins->inst_basereg == last_ins->inst_destbasereg &&
2545 ins->inst_offset == last_ins->inst_offset) {
2546 if (ins->dreg == last_ins->sreg1) {
2547 MONO_DELETE_INS (bb, ins);
2550 ins->opcode = OP_MOVE;
2551 ins->sreg1 = last_ins->sreg1;
2555 * Note: reg1 must be different from the basereg in the second load
2556 * Note: if reg1 = reg2 is equal then second load is removed
2558 * OP_LOAD_MEMBASE offset(basereg), reg1
2559 * OP_LOAD_MEMBASE offset(basereg), reg2
2561 * OP_LOAD_MEMBASE offset(basereg), reg1
2562 * OP_MOVE reg1, reg2
2564 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2565 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2566 ins->inst_basereg != last_ins->dreg &&
2567 ins->inst_basereg == last_ins->inst_basereg &&
2568 ins->inst_offset == last_ins->inst_offset) {
2570 if (ins->dreg == last_ins->dreg) {
2571 MONO_DELETE_INS (bb, ins);
2573 ins->opcode = OP_MOVE;
2574 ins->sreg1 = last_ins->dreg;
2577 //g_assert_not_reached ();
2581 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2582 * OP_LOAD_MEMBASE offset(basereg), reg
2584 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2585 * OP_ICONST reg, imm
2587 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2588 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2589 ins->inst_basereg == last_ins->inst_destbasereg &&
2590 ins->inst_offset == last_ins->inst_offset) {
2591 ins->opcode = OP_ICONST;
2592 ins->inst_c0 = last_ins->inst_imm;
2593 g_assert_not_reached (); // check this rule
2597 case OP_LOADI1_MEMBASE:
2598 case OP_LOADU1_MEMBASE:
2600 * Note: if reg1 = reg2 the load op is removed
2602 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2603 * OP_LOAD_MEMBASE offset(basereg), reg2
2605 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2606 * OP_MOVE reg1, reg2
2608 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2609 ins->inst_basereg == last_ins->inst_destbasereg &&
2610 ins->inst_offset == last_ins->inst_offset) {
2611 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2612 ins->sreg1 = last_ins->sreg1;
2615 case OP_LOADI2_MEMBASE:
2616 case OP_LOADU2_MEMBASE:
2618 * Note: if reg1 = reg2 the load op is removed
2620 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2621 * OP_LOAD_MEMBASE offset(basereg), reg2
2623 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2624 * OP_MOVE reg1, reg2
2626 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2627 ins->inst_basereg == last_ins->inst_destbasereg &&
2628 ins->inst_offset == last_ins->inst_offset) {
2629 #if SIZEOF_REGISTER == 8
2630 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2632 /* The definition of OP_PCONV_TO_U2 is wrong */
2633 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2635 ins->sreg1 = last_ins->sreg1;
2638 case OP_LOADX_MEMBASE:
2639 if (last_ins && last_ins->opcode == OP_STOREX_MEMBASE &&
2640 ins->inst_basereg == last_ins->inst_destbasereg &&
2641 ins->inst_offset == last_ins->inst_offset) {
2642 if (ins->dreg == last_ins->sreg1) {
2643 MONO_DELETE_INS (bb, ins);
2646 ins->opcode = OP_XMOVE;
2647 ins->sreg1 = last_ins->sreg1;
2658 if (ins->dreg == ins->sreg1) {
2659 MONO_DELETE_INS (bb, ins);
2665 * OP_MOVE sreg, dreg
2666 * OP_MOVE dreg, sreg
2668 if (last_ins && last_ins->opcode == ins->opcode &&
2669 ins->sreg1 == last_ins->dreg &&
2670 ins->dreg == last_ins->sreg1) {
2671 MONO_DELETE_INS (bb, ins);
2675 MONO_DELETE_INS (bb, ins);
2681 mini_exception_id_by_name (const char *name)
2683 if (strcmp (name, "IndexOutOfRangeException") == 0)
2684 return MONO_EXC_INDEX_OUT_OF_RANGE;
2685 if (strcmp (name, "OverflowException") == 0)
2686 return MONO_EXC_OVERFLOW;
2687 if (strcmp (name, "ArithmeticException") == 0)
2688 return MONO_EXC_ARITHMETIC;
2689 if (strcmp (name, "DivideByZeroException") == 0)
2690 return MONO_EXC_DIVIDE_BY_ZERO;
2691 if (strcmp (name, "InvalidCastException") == 0)
2692 return MONO_EXC_INVALID_CAST;
2693 if (strcmp (name, "NullReferenceException") == 0)
2694 return MONO_EXC_NULL_REF;
2695 if (strcmp (name, "ArrayTypeMismatchException") == 0)
2696 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2697 if (strcmp (name, "ArgumentException") == 0)
2698 return MONO_EXC_ARGUMENT;
2699 g_error ("Unknown intrinsic exception %s\n", name);
2704 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2708 MonoClassField *field;
2709 MonoType *ftype, *prev_ftype = NULL;
2712 klass = mono_class_from_mono_type (t);
2714 while ((field = mono_class_get_fields (klass, &iter))) {
2715 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2717 ftype = mono_field_get_type (field);
2718 ftype = mini_native_type_replace_type (ftype);
2720 if (MONO_TYPE_ISSTRUCT (ftype)) {
2721 int nested_nfields, nested_esize;
2723 if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2725 if (nested_esize == 4)
2726 ftype = &mono_defaults.single_class->byval_arg;
2728 ftype = &mono_defaults.double_class->byval_arg;
2729 if (prev_ftype && prev_ftype->type != ftype->type)
2732 nfields += nested_nfields;
2734 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2736 if (prev_ftype && prev_ftype->type != ftype->type)
2744 *out_nfields = nfields;
2745 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2750 mono_regstate_new (void)
2752 MonoRegState* rs = g_new0 (MonoRegState, 1);
2754 rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2755 #ifdef MONO_ARCH_NEED_SIMD_BANK
2756 rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2763 mono_regstate_free (MonoRegState *rs) {
2764 g_free (rs->vassign);
2768 #endif /* DISABLE_JIT */
2771 mono_is_regsize_var (MonoType *t)
2773 t = mini_get_underlying_type (t);
2784 case MONO_TYPE_FNPTR:
2785 #if SIZEOF_REGISTER == 8
2790 case MONO_TYPE_OBJECT:
2791 case MONO_TYPE_STRING:
2792 case MONO_TYPE_CLASS:
2793 case MONO_TYPE_SZARRAY:
2794 case MONO_TYPE_ARRAY:
2796 case MONO_TYPE_GENERICINST:
2797 if (!mono_type_generic_inst_is_valuetype (t))
2800 case MONO_TYPE_VALUETYPE: