mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 const char*
 423 mono_ji_type_to_string (MonoJumpInfoType type)
 424 {
 425         return patch_info_str [type];
 426 }
 427
 428 void
 429 mono_print_ji (const MonoJumpInfo *ji)
 430 {
 431         switch (ji->type) {
 432         case MONO_PATCH_INFO_RGCTX_FETCH: {
 433                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 434
 435                 printf ("[RGCTX_FETCH ");
 436                 mono_print_ji (entry->data);
 437                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 438                 break;
 439         }
 440         case MONO_PATCH_INFO_METHODCONST: {
 441                 char *s = mono_method_full_name (ji->data.method, TRUE);
 442                 printf ("[METHODCONST - %s]", s);
 443                 g_free (s);
 444                 break;
 445         }
 446         case MONO_PATCH_INFO_INTERNAL_METHOD: {
 447                 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
 448                 break;
 449         }
 450         default:
 451                 printf ("[%s]", patch_info_str [ji->type]);
 452                 break;
 453         }
 454 }
 455
 456 void
 457 mono_print_ins_index (int i, MonoInst *ins)
 458 {
 459         const char *spec = ins_get_spec (ins->opcode);
 460         int num_sregs, j;
 461         int sregs [MONO_MAX_SRC_REGS];
 462
 463         if (i != -1)
 464                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 465         else
 466                 printf (" %s", mono_inst_name (ins->opcode));
 467         if (spec == MONO_ARCH_CPU_SPEC) {
 468                 gboolean dest_base = FALSE;
 469                 switch (ins->opcode) {
 470                 case OP_STOREV_MEMBASE:
 471                         dest_base = TRUE;
 472                         break;
 473                 default:
 474                         break;
 475                 }
 476
 477                 /* This is a lowered opcode */
 478                 if (ins->dreg != -1) {
 479                         if (dest_base)
 480                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 481                         else
 482                                 printf (" R%d <-", ins->dreg);
 483                 }
 484                 if (ins->sreg1 != -1)
 485                         printf (" R%d", ins->sreg1);
 486                 if (ins->sreg2 != -1)
 487                         printf (" R%d", ins->sreg2);
 488                 if (ins->sreg3 != -1)
 489                         printf (" R%d", ins->sreg3);
 490
 491                 switch (ins->opcode) {
 492                 case OP_LBNE_UN:
 493                 case OP_LBEQ:
 494                 case OP_LBLT:
 495                 case OP_LBLT_UN:
 496                 case OP_LBGT:
 497                 case OP_LBGT_UN:
 498                 case OP_LBGE:
 499                 case OP_LBGE_UN:
 500                 case OP_LBLE:
 501                 case OP_LBLE_UN:
 502                         if (!ins->inst_false_bb)
 503                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 504                         else
 505                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 506                         break;
 507                 case OP_PHI:
 508                 case OP_VPHI:
 509                 case OP_XPHI:
 510                 case OP_FPHI: {
 511                         int i;
 512                         printf (" [%d (", (int)ins->inst_c0);
 513                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 514                                 if (i)
 515                                         printf (", ");
 516                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 517                         }
 518                         printf (")]");
 519                         break;
 520                 }
 521                 case OP_LDADDR:
 522                 case OP_OUTARG_VTRETADDR:
 523                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 524                         break;
 525                 case OP_REGOFFSET:
 526                 case OP_GSHAREDVT_ARG_REGOFFSET:
 527                         printf (" + 0x%lx", (long)ins->inst_offset);
 528                         break;
 529                 default:
 530                         break;
 531                 }
 532
 533                 printf ("\n");
 534                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 535                 return;
 536         }
 537
 538         if (spec [MONO_INST_DEST]) {
 539                 int bank = dreg_bank (spec);
 540                 if (is_soft_reg (ins->dreg, bank)) {
 541                         if (spec [MONO_INST_DEST] == 'b') {
 542                                 if (ins->inst_offset == 0)
 543                                         printf (" [R%d] <-", ins->dreg);
 544                                 else
 545                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 546                         }
 547                         else
 548                                 printf (" R%d <-", ins->dreg);
 549                 } else if (spec [MONO_INST_DEST] == 'b') {
 550                         if (ins->inst_offset == 0)
 551                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 552                         else
 553                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 554                 } else
 555                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 556         }
 557         if (spec [MONO_INST_SRC1]) {
 558                 int bank = sreg1_bank (spec);
 559                 if (is_soft_reg (ins->sreg1, bank)) {
 560                         if (spec [MONO_INST_SRC1] == 'b')
 561                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 562                         else
 563                                 printf (" R%d", ins->sreg1);
 564                 } else if (spec [MONO_INST_SRC1] == 'b')
 565                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 566                 else
 567                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 568         }
 569         num_sregs = mono_inst_get_src_registers (ins, sregs);
 570         for (j = 1; j < num_sregs; ++j) {
 571                 int bank = sreg_bank (j, spec);
 572                 if (is_soft_reg (sregs [j], bank))
 573                         printf (" R%d", sregs [j]);
 574                 else
 575                         printf (" %s", mono_regname_full (sregs [j], bank));
 576         }
 577
 578         switch (ins->opcode) {
 579         case OP_ICONST:
 580                 printf (" [%d]", (int)ins->inst_c0);
 581                 break;
 582 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 583         case OP_X86_PUSH_IMM:
 584 #endif
 585         case OP_ICOMPARE_IMM:
 586         case OP_COMPARE_IMM:
 587         case OP_IADD_IMM:
 588         case OP_ISUB_IMM:
 589         case OP_IAND_IMM:
 590         case OP_IOR_IMM:
 591         case OP_IXOR_IMM:
 592         case OP_SUB_IMM:
 593         case OP_STORE_MEMBASE_IMM:
 594                 printf (" [%d]", (int)ins->inst_imm);
 595                 break;
 596         case OP_ADD_IMM:
 597         case OP_LADD_IMM:
 598                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 599                 break;
 600         case OP_I8CONST:
 601                 printf (" [%lld]", (long long)ins->inst_l);
 602                 break;
 603         case OP_R8CONST:
 604                 printf (" [%f]", *(double*)ins->inst_p0);
 605                 break;
 606         case OP_R4CONST:
 607                 printf (" [%f]", *(float*)ins->inst_p0);
 608                 break;
 609         case OP_CALL:
 610         case OP_CALL_MEMBASE:
 611         case OP_CALL_REG:
 612         case OP_FCALL:
 613         case OP_LCALL:
 614         case OP_VCALL:
 615         case OP_VCALL_REG:
 616         case OP_VCALL_MEMBASE:
 617         case OP_VCALL2:
 618         case OP_VCALL2_REG:
 619         case OP_VCALL2_MEMBASE:
 620         case OP_VOIDCALL:
 621         case OP_VOIDCALL_MEMBASE:
 622         case OP_TAILCALL: {
 623                 MonoCallInst *call = (MonoCallInst*)ins;
 624                 GSList *list;
 625
 626                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 627                         /*
 628                          * These are lowered opcodes, but they are in the .md files since the old
 629                          * JIT passes them to backends.
 630                          */
 631                         if (ins->dreg != -1)
 632                                 printf (" R%d <-", ins->dreg);
 633                 }
 634
 635                 if (call->method) {
 636                         char *full_name = mono_method_full_name (call->method, TRUE);
 637                         printf (" [%s]", full_name);
 638                         g_free (full_name);
 639                 } else if (call->fptr_is_patch) {
 640                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 641
 642                         printf (" ");
 643                         mono_print_ji (ji);
 644                 } else if (call->fptr) {
 645                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 646                         if (info)
 647                                 printf (" [%s]", info->name);
 648                 }
 649
 650                 list = call->out_ireg_args;
 651                 while (list) {
 652                         guint32 regpair;
 653                         int reg, hreg;
 654
 655                         regpair = (guint32)(gssize)(list->data);
 656                         hreg = regpair >> 24;
 657                         reg = regpair & 0xffffff;
 658
 659                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 660
 661                         list = g_slist_next (list);
 662                 }
 663                 list = call->out_freg_args;
 664                 while (list) {
 665                         guint32 regpair;
 666                         int reg, hreg;
 667
 668                         regpair = (guint32)(gssize)(list->data);
 669                         hreg = regpair >> 24;
 670                         reg = regpair & 0xffffff;
 671
 672                         printf (" [%s <- R%d]", mono_arch_fregname (hreg), reg);
 673
 674                         list = g_slist_next (list);
 675                 }
 676                 break;
 677         }
 678         case OP_BR:
 679         case OP_CALL_HANDLER:
 680                 printf (" [B%d]", ins->inst_target_bb->block_num);
 681                 break;
 682         case OP_IBNE_UN:
 683         case OP_IBEQ:
 684         case OP_IBLT:
 685         case OP_IBLT_UN:
 686         case OP_IBGT:
 687         case OP_IBGT_UN:
 688         case OP_IBGE:
 689         case OP_IBGE_UN:
 690         case OP_IBLE:
 691         case OP_IBLE_UN:
 692         case OP_LBNE_UN:
 693         case OP_LBEQ:
 694         case OP_LBLT:
 695         case OP_LBLT_UN:
 696         case OP_LBGT:
 697         case OP_LBGT_UN:
 698         case OP_LBGE:
 699         case OP_LBGE_UN:
 700         case OP_LBLE:
 701         case OP_LBLE_UN:
 702                 if (!ins->inst_false_bb)
 703                         printf (" [B%d]", ins->inst_true_bb->block_num);
 704                 else
 705                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 706                 break;
 707         case OP_LIVERANGE_START:
 708         case OP_LIVERANGE_END:
 709         case OP_GC_LIVENESS_DEF:
 710         case OP_GC_LIVENESS_USE:
 711                 printf (" R%d", (int)ins->inst_c1);
 712                 break;
 713         case OP_IL_SEQ_POINT:
 714         case OP_SEQ_POINT:
 715                 printf (" il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 716                 break;
 717         default:
 718                 break;
 719         }
 720
 721         if (spec [MONO_INST_CLOB])
 722                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 723         printf ("\n");
 724 }
 725
 726 static void
 727 print_regtrack (RegTrack *t, int num)
 728 {
 729         int i;
 730         char buf [32];
 731         const char *r;
 732
 733         for (i = 0; i < num; ++i) {
 734                 if (!t [i].born_in)
 735                         continue;
 736                 if (i >= MONO_MAX_IREGS) {
 737                         g_snprintf (buf, sizeof(buf), "R%d", i);
 738                         r = buf;
 739                 } else
 740                         r = mono_arch_regname (i);
 741                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 742         }
 743 }
 744 #else
 745
 746 const char*
 747 mono_ji_type_to_string (MonoJumpInfoType type)
 748 {
 749         return "";
 750 }
 751
 752 void
 753 mono_print_ji (const MonoJumpInfo *ji)
 754 {
 755 }
 756
 757 void
 758 mono_print_ins_index (int i, MonoInst *ins)
 759 {
 760 }
 761 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 762
 763 void
 764 mono_print_ins (MonoInst *ins)
 765 {
 766         mono_print_ins_index (-1, ins);
 767 }
 768
 769 static inline void
 770 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 771 {
 772         /*
 773          * If this function is called multiple times, the new instructions are inserted
 774          * in the proper order.
 775          */
 776         mono_bblock_insert_before_ins (bb, ins, to_insert);
 777 }
 778
 779 static inline void
 780 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 781 {
 782         /*
 783          * If this function is called multiple times, the new instructions are inserted in
 784          * proper order.
 785          */
 786         mono_bblock_insert_after_ins (bb, *last, to_insert);
 787
 788         *last = to_insert;
 789 }
 790
 791 static inline int
 792 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 793 {
 794         if (vreg_is_ref (cfg, reg))
 795                 return MONO_REG_INT_REF;
 796         else if (vreg_is_mp (cfg, reg))
 797                 return MONO_REG_INT_MP;
 798         else
 799                 return bank;
 800 }
 801
 802 /*
 803  * Force the spilling of the variable in the symbolic register 'reg', and free
 804  * the hreg it was assigned to.
 805  */
 806 static void
 807 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 808 {
 809         MonoInst *load;
 810         int i, sel, spill;
 811         MonoRegState *rs = cfg->rs;
 812
 813         sel = rs->vassign [reg];
 814
 815         /* the vreg we need to spill lives in another logical reg bank */
 816         bank = translate_bank (cfg->rs, bank, sel);
 817
 818         /*i = rs->isymbolic [sel];
 819         g_assert (i == reg);*/
 820         i = reg;
 821         spill = ++cfg->spill_count;
 822         rs->vassign [i] = -spill - 1;
 823         if (G_UNLIKELY (bank))
 824                 mono_regstate_free_general (rs, sel, bank);
 825         else
 826                 mono_regstate_free_int (rs, sel);
 827         /* we need to create a spill var and insert a load to sel after the current instruction */
 828         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 829         load->dreg = sel;
 830         load->inst_basereg = cfg->frame_reg;
 831         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 832         insert_after_ins (bb, ins, last, load);
 833         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 834         if (G_UNLIKELY (bank))
 835                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 836         else
 837                 i = mono_regstate_alloc_int (rs, regmask (sel));
 838         g_assert (i == sel);
 839
 840         if (G_UNLIKELY (bank))
 841                 mono_regstate_free_general (rs, sel, bank);
 842         else
 843                 mono_regstate_free_int (rs, sel);
 844 }
 845
 846 /* This isn't defined on older glib versions and on some platforms */
 847 #ifndef G_GUINT64_FORMAT
 848 #define G_GUINT64_FORMAT "ul"
 849 #endif
 850
 851 static int
 852 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 853 {
 854         MonoInst *load;
 855         int i, sel, spill, num_sregs;
 856         int sregs [MONO_MAX_SRC_REGS];
 857         MonoRegState *rs = cfg->rs;
 858
 859         g_assert (bank < MONO_NUM_REGBANKS);
 860
 861         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 862         /* exclude the registers in the current instruction */
 863         num_sregs = mono_inst_get_src_registers (ins, sregs);
 864         for (i = 0; i < num_sregs; ++i) {
 865                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 866                         if (is_soft_reg (sregs [i], bank))
 867                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 868                         else
 869                                 regmask &= ~ (regmask (sregs [i]));
 870                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 871                 }
 872         }
 873         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 874                 regmask &= ~ (regmask (ins->dreg));
 875                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 876         }
 877
 878         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 879         g_assert (regmask); /* need at least a register we can free */
 880         sel = 0;
 881         /* we should track prev_use and spill the register that's farther */
 882         if (G_UNLIKELY (bank)) {
 883                 for (i = 0; i < regbank_size [bank]; ++i) {
 884                         if (regmask & (regmask (i))) {
 885                                 sel = i;
 886
 887                                 /* the vreg we need to load lives in another logical bank */
 888                                 bank = translate_bank (cfg->rs, bank, sel);
 889
 890                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 891                                 break;
 892                         }
 893                 }
 894
 895                 i = rs->symbolic [bank] [sel];
 896                 spill = ++cfg->spill_count;
 897                 rs->vassign [i] = -spill - 1;
 898                 mono_regstate_free_general (rs, sel, bank);
 899         }
 900         else {
 901                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 902                         if (regmask & (regmask (i))) {
 903                                 sel = i;
 904                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 905                                 break;
 906                         }
 907                 }
 908
 909                 i = rs->isymbolic [sel];
 910                 spill = ++cfg->spill_count;
 911                 rs->vassign [i] = -spill - 1;
 912                 mono_regstate_free_int (rs, sel);
 913         }
 914
 915         /* we need to create a spill var and insert a load to sel after the current instruction */
 916         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 917         load->dreg = sel;
 918         load->inst_basereg = cfg->frame_reg;
 919         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 920         insert_after_ins (bb, ins, last, load);
 921         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 922         if (G_UNLIKELY (bank))
 923                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 924         else
 925                 i = mono_regstate_alloc_int (rs, regmask (sel));
 926         g_assert (i == sel);
 927
 928         return sel;
 929 }
 930
 931 /*
 932  * free_up_hreg:
 933  *
 934  *   Free up the hreg HREG by spilling the vreg allocated to it.
 935  */
 936 static void
 937 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 938 {
 939         if (G_UNLIKELY (bank)) {
 940                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 941                         bank = translate_bank (cfg->rs, bank, hreg);
 942                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 943                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 944                 }
 945         }
 946         else {
 947                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 948                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 949                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 950                 }
 951         }
 952 }
 953
 954 static MonoInst*
 955 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 956 {
 957         MonoInst *copy;
 958
 959         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 960
 961         copy->dreg = dest;
 962         copy->sreg1 = src;
 963         copy->cil_code = ip;
 964         if (ins) {
 965                 mono_bblock_insert_after_ins (bb, ins, copy);
 966                 *last = copy;
 967         }
 968         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 969         return copy;
 970 }
 971
 972 static inline const char*
 973 regbank_to_string (int bank)
 974 {
 975         if (bank == MONO_REG_INT_REF)
 976                 return "REF ";
 977         else if (bank == MONO_REG_INT_MP)
 978                 return "MP ";
 979         else
 980                 return "";
 981 }
 982
 983 static void
 984 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 985 {
 986         MonoInst *store, *def;
 987
 988         bank = get_vreg_bank (cfg, prev_reg, bank);
 989
 990         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 991         store->sreg1 = reg;
 992         store->inst_destbasereg = cfg->frame_reg;
 993         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 994         if (ins) {
 995                 mono_bblock_insert_after_ins (bb, ins, store);
 996                 *last = store;
 997         } else if (insert_before) {
 998                 insert_before_ins (bb, insert_before, store);
 999         } else {
1000                 g_assert_not_reached ();
1001         }
1002         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
1003
1004         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1005                 g_assert (prev_reg != -1);
1006                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1007                 def->inst_c0 = spill;
1008                 def->inst_c1 = bank;
1009                 mono_bblock_insert_after_ins (bb, store, def);
1010         }
1011 }
1012
1013 /* flags used in reginfo->flags */
1014 enum {
1015         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1016         MONO_FP_NEEDS_SPILL                     = regmask (1),
1017         MONO_FP_NEEDS_LOAD                      = regmask (2)
1018 };
1019
1020 static inline int
1021 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1022 {
1023         int val;
1024
1025         if (info && info->preferred_mask) {
1026                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1027                 if (val >= 0) {
1028                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1029                         return val;
1030                 }
1031         }
1032
1033         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1034         if (val < 0)
1035                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1036
1037         return val;
1038 }
1039
1040 static inline int
1041 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1042 {
1043         int val;
1044
1045         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1046
1047         if (val < 0)
1048                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1049
1050         return val;
1051 }
1052
1053 static inline int
1054 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1055 {
1056         if (G_UNLIKELY (bank))
1057                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1058         else
1059                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1060 }
1061
1062 static inline void
1063 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1064 {
1065         if (G_UNLIKELY (bank)) {
1066                 int mirrored_bank;
1067
1068                 g_assert (reg >= regbank_size [bank]);
1069                 g_assert (hreg < regbank_size [bank]);
1070                 g_assert (! is_global_freg (hreg));
1071
1072                 rs->vassign [reg] = hreg;
1073                 rs->symbolic [bank] [hreg] = reg;
1074                 rs->free_mask [bank] &= ~ (regmask (hreg));
1075
1076                 mirrored_bank = get_mirrored_bank (bank);
1077                 if (mirrored_bank == -1)
1078                         return;
1079
1080                 /* Make sure the other logical reg bank that this bank shares
1081                  * a single hard reg bank knows that this hard reg is not free.
1082                  */
1083                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1084
1085                 /* Mark the other logical bank that the this bank shares
1086                  * a single hard reg bank with as mirrored.
1087                  */
1088                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1089
1090         }
1091         else {
1092                 g_assert (reg >= MONO_MAX_IREGS);
1093                 g_assert (hreg < MONO_MAX_IREGS);
1094 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1095                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1096                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1097                 g_assert (! is_global_ireg (hreg));
1098 #endif
1099
1100                 rs->vassign [reg] = hreg;
1101                 rs->isymbolic [hreg] = reg;
1102                 rs->ifree_mask &= ~ (regmask (hreg));
1103         }
1104 }
1105
1106 static inline regmask_t
1107 get_callee_mask (const char spec)
1108 {
1109         if (G_UNLIKELY (reg_bank (spec)))
1110                 return regbank_callee_regs [reg_bank (spec)];
1111         return MONO_ARCH_CALLEE_REGS;
1112 }
1113
1114 static gint8 desc_to_fixed_reg [256];
1115 static gboolean desc_to_fixed_reg_inited = FALSE;
1116
1117 #ifndef DISABLE_JIT
1118
1119 /*
1120  * Local register allocation.
1121  * We first scan the list of instructions and we save the liveness info of
1122  * each register (when the register is first used, when it's value is set etc.).
1123  * We also reverse the list of instructions because assigning registers backwards allows
1124  * for more tricks to be used.
1125  */
1126 void
1127 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1128 {
1129         MonoInst *ins, *prev, *last;
1130         MonoInst **tmp;
1131         MonoRegState *rs = cfg->rs;
1132         int i, j, val, max;
1133         RegTrack *reginfo;
1134         const char *spec;
1135         unsigned char spec_src1, spec_dest;
1136         int bank = 0;
1137 #if MONO_ARCH_USE_FPSTACK
1138         gboolean has_fp = FALSE;
1139         int fpstack [8];
1140         int sp = 0;
1141 #endif
1142         int num_sregs = 0;
1143         int sregs [MONO_MAX_SRC_REGS];
1144
1145         if (!bb->code)
1146                 return;
1147
1148         if (!desc_to_fixed_reg_inited) {
1149                 for (i = 0; i < 256; ++i)
1150                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1151                 desc_to_fixed_reg_inited = TRUE;
1152
1153                 /* Validate the cpu description against the info in mini-ops.h */
1154 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1155                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1156                         const char *ispec;
1157
1158                         spec = ins_get_spec (i);
1159                         ispec = INS_INFO (i);
1160
1161                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1162                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1163                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1164                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1165                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1166                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1167                 }
1168 #endif
1169         }
1170
1171         rs->next_vreg = bb->max_vreg;
1172         mono_regstate_assign (rs);
1173
1174         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1175         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1176                 rs->free_mask [i] = regbank_callee_regs [i];
1177
1178         max = rs->next_vreg;
1179
1180         if (cfg->reginfo && cfg->reginfo_len < max)
1181                 cfg->reginfo = NULL;
1182
1183         reginfo = (RegTrack *)cfg->reginfo;
1184         if (!reginfo) {
1185                 cfg->reginfo_len = MAX (1024, max * 2);
1186                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1187                 cfg->reginfo = reginfo;
1188         }
1189         else
1190                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1191
1192         if (cfg->verbose_level > 1) {
1193                 /* print_regtrack reads the info of all variables */
1194                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1195         }
1196
1197         /*
1198          * For large methods, next_vreg can be very large, so g_malloc0 time can
1199          * be prohibitive. So we manually init the reginfo entries used by the
1200          * bblock.
1201          */
1202         for (ins = bb->code; ins; ins = ins->next) {
1203                 gboolean modify = FALSE;
1204
1205                 spec = ins_get_spec (ins->opcode);
1206
1207                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1208                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1209 #if SIZEOF_REGISTER == 4
1210                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1211                                 /**
1212                                  * In the new IR, the two vregs of the regpair do not alias the
1213                                  * original long vreg. shift the vreg here so the rest of the
1214                                  * allocator doesn't have to care about it.
1215                                  */
1216                                 ins->dreg ++;
1217                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1218                         }
1219 #endif
1220                 }
1221
1222                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1223                 for (j = 0; j < num_sregs; ++j) {
1224                         g_assert (sregs [j] != -1);
1225                         if (sregs [j] < max) {
1226                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1227 #if SIZEOF_REGISTER == 4
1228                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1229                                         sregs [j]++;
1230                                         modify = TRUE;
1231                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1232                                 }
1233 #endif
1234                         }
1235                 }
1236                 if (modify)
1237                         mono_inst_set_src_registers (ins, sregs);
1238         }
1239
1240         /*if (cfg->opt & MONO_OPT_COPYPROP)
1241                 local_copy_prop (cfg, ins);*/
1242
1243         i = 1;
1244         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1245         /* forward pass on the instructions to collect register liveness info */
1246         MONO_BB_FOR_EACH_INS (bb, ins) {
1247                 spec = ins_get_spec (ins->opcode);
1248                 spec_dest = spec [MONO_INST_DEST];
1249
1250                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1251                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1252                 }
1253
1254                 DEBUG (mono_print_ins_index (i, ins));
1255
1256                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1257
1258 #if MONO_ARCH_USE_FPSTACK
1259                 if (dreg_is_fp (spec)) {
1260                         has_fp = TRUE;
1261                 } else {
1262                         for (j = 0; j < num_sregs; ++j) {
1263                                 if (sreg_is_fp (j, spec))
1264                                         has_fp = TRUE;
1265                         }
1266                 }
1267 #endif
1268
1269                 for (j = 0; j < num_sregs; ++j) {
1270                         int sreg = sregs [j];
1271                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1272                         if (sreg_spec) {
1273                                 bank = sreg_bank (j, spec);
1274                                 g_assert (sreg != -1);
1275                                 if (is_soft_reg (sreg, bank))
1276                                         /* This means the vreg is not local to this bb */
1277                                         g_assert (reginfo [sreg].born_in > 0);
1278                                 rs->vassign [sreg] = -1;
1279                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1280                                 //reginfo [ins->sreg2].last_use = i;
1281                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1282                                         /* The virtual register is allocated sequentially */
1283                                         rs->vassign [sreg + 1] = -1;
1284                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1285                                         //reginfo [ins->sreg2 + 1].last_use = i;
1286                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1287                                                 reginfo [sreg + 1].born_in = i;
1288                                 }
1289                         } else {
1290                                 sregs [j] = -1;
1291                         }
1292                 }
1293                 mono_inst_set_src_registers (ins, sregs);
1294
1295                 if (spec_dest) {
1296                         int dest_dreg;
1297
1298                         bank = dreg_bank (spec);
1299                         if (spec_dest != 'b') /* it's not just a base register */
1300                                 reginfo [ins->dreg].killed_in = i;
1301                         g_assert (ins->dreg != -1);
1302                         rs->vassign [ins->dreg] = -1;
1303                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1304                         //reginfo [ins->dreg].last_use = i;
1305                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1306                                 reginfo [ins->dreg].born_in = i;
1307
1308                         dest_dreg = desc_to_fixed_reg [spec_dest];
1309                         if (dest_dreg != -1)
1310                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1311
1312 #ifdef MONO_ARCH_INST_FIXED_MASK
1313                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1314 #endif
1315
1316                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1317                                 /* The virtual register is allocated sequentially */
1318                                 rs->vassign [ins->dreg + 1] = -1;
1319                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1320                                 //reginfo [ins->dreg + 1].last_use = i;
1321                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1322                                         reginfo [ins->dreg + 1].born_in = i;
1323                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1324                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1325                         }
1326                 } else {
1327                         ins->dreg = -1;
1328                 }
1329
1330                 ++i;
1331         }
1332
1333         tmp = &last;
1334
1335         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1336         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1337                 int prev_dreg;
1338                 int dest_dreg, clob_reg;
1339                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1340                 int dreg_high, sreg1_high;
1341                 regmask_t dreg_mask, mask;
1342                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1343                 regmask_t dreg_fixed_mask;
1344                 const unsigned char *ip;
1345                 --i;
1346                 spec = ins_get_spec (ins->opcode);
1347                 spec_src1 = spec [MONO_INST_SRC1];
1348                 spec_dest = spec [MONO_INST_DEST];
1349                 prev_dreg = -1;
1350                 clob_reg = -1;
1351                 dest_dreg = -1;
1352                 dreg_high = -1;
1353                 sreg1_high = -1;
1354                 dreg_mask = get_callee_mask (spec_dest);
1355                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1356                         prev_sregs [j] = -1;
1357                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1358                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1359 #ifdef MONO_ARCH_INST_FIXED_MASK
1360                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1361 #else
1362                         sreg_fixed_masks [j] = 0;
1363 #endif
1364                 }
1365
1366                 DEBUG (printf ("processing:"));
1367                 DEBUG (mono_print_ins_index (i, ins));
1368
1369                 ip = ins->cil_code;
1370
1371                 last = ins;
1372
1373                 /*
1374                  * FIXED REGS
1375                  */
1376                 dest_dreg = desc_to_fixed_reg [spec_dest];
1377                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1378                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1379
1380 #ifdef MONO_ARCH_INST_FIXED_MASK
1381                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1382 #else
1383                 dreg_fixed_mask = 0;
1384 #endif
1385
1386                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1387
1388                 /*
1389                  * TRACK FIXED SREG2, 3, ...
1390                  */
1391                 for (j = 1; j < num_sregs; ++j) {
1392                         int sreg = sregs [j];
1393                         int dest_sreg = dest_sregs [j];
1394
1395                         if (dest_sreg == -1)
1396                                 continue;
1397
1398                         if (j == 2) {
1399                                 int k;
1400
1401                                 /*
1402                                  * CAS.
1403                                  * We need to special case this, since on x86, there are only 3
1404                                  * free registers, and the code below assigns one of them to
1405                                  * sreg, so we can run out of registers when trying to assign
1406                                  * dreg. Instead, we just set up the register masks, and let the
1407                                  * normal sreg2 assignment code handle this. It would be nice to
1408                                  * do this for all the fixed reg cases too, but there is too much
1409                                  * risk of breakage.
1410                                  */
1411
1412                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1413                                 sreg_masks [j] = regmask (dest_sreg);
1414                                 for (k = 0; k < num_sregs; ++k) {
1415                                         if (k != j)
1416                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1417                                 }
1418
1419                                 /*
1420                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1421                                  */
1422                                 for (k = 0; k < num_sregs; ++k) {
1423                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1424                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1425                                 }
1426
1427                                 /*
1428                                  * We can also run out of registers while processing sreg2 if sreg3 is
1429                                  * assigned to another hreg, so spill sreg3 now.
1430                                  */
1431                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1432                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1433                                 }
1434                                 continue;
1435                         }
1436
1437                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1438                                 if (is_global_ireg (sreg)) {
1439                                         int k;
1440                                         /* Argument already in hard reg, need to copy */
1441                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1442                                         insert_before_ins (bb, ins, copy);
1443                                         for (k = 0; k < num_sregs; ++k) {
1444                                                 if (k != j)
1445                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1446                                         }
1447                                         /* See below */
1448                                         dreg_mask &= ~ (regmask (dest_sreg));
1449                                 } else {
1450                                         val = rs->vassign [sreg];
1451                                         if (val == -1) {
1452                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1453                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1454                                         } else if (val < -1) {
1455                                                 /* FIXME: */
1456                                                 g_assert_not_reached ();
1457                                         } else {
1458                                                 /* Argument already in hard reg, need to copy */
1459                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1460                                                 int k;
1461
1462                                                 insert_before_ins (bb, ins, copy);
1463                                                 for (k = 0; k < num_sregs; ++k) {
1464                                                         if (k != j)
1465                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1466                                                 }
1467                                                 /*
1468                                                  * Prevent the dreg from being allocated to dest_sreg
1469                                                  * too, since it could force sreg1 to be allocated to
1470                                                  * the same reg on x86.
1471                                                  */
1472                                                 dreg_mask &= ~ (regmask (dest_sreg));
1473                                         }
1474                                 }
1475                         } else {
1476                                 gboolean need_spill = TRUE;
1477                                 gboolean need_assign = TRUE;
1478                                 int k;
1479
1480                                 dreg_mask &= ~ (regmask (dest_sreg));
1481                                 for (k = 0; k < num_sregs; ++k) {
1482                                         if (k != j)
1483                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1484                                 }
1485
1486                                 /*
1487                                  * First check if dreg is assigned to dest_sreg2, since we
1488                                  * can't spill a dreg.
1489                                  */
1490                                 if (spec [MONO_INST_DEST])
1491                                         val = rs->vassign [ins->dreg];
1492                                 else
1493                                         val = -1;
1494                                 if (val == dest_sreg && ins->dreg != sreg) {
1495                                         /*
1496                                          * the destination register is already assigned to
1497                                          * dest_sreg2: we need to allocate another register for it
1498                                          * and then copy from this to dest_sreg2.
1499                                          */
1500                                         int new_dest;
1501                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1502                                         g_assert (new_dest >= 0);
1503                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1504
1505                                         prev_dreg = ins->dreg;
1506                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1507                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1508                                         mono_regstate_free_int (rs, dest_sreg);
1509                                         need_spill = FALSE;
1510                                 }
1511
1512                                 if (is_global_ireg (sreg)) {
1513                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1514                                         insert_before_ins (bb, ins, copy);
1515                                         need_assign = FALSE;
1516                                 }
1517                                 else {
1518                                         val = rs->vassign [sreg];
1519                                         if (val == dest_sreg) {
1520                                                 /* sreg2 is already assigned to the correct register */
1521                                                 need_spill = FALSE;
1522                                         } else if (val < -1) {
1523                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1524                                         } else if (val >= 0) {
1525                                                 /* sreg2 already assigned to another register */
1526                                                 /*
1527                                                  * We couldn't emit a copy from val to dest_sreg2, because
1528                                                  * val might be spilled later while processing this
1529                                                  * instruction. So we spill sreg2 so it can be allocated to
1530                                                  * dest_sreg2.
1531                                                  */
1532                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1533                                         }
1534                                 }
1535
1536                                 if (need_spill) {
1537                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1538                                 }
1539
1540                                 if (need_assign) {
1541                                         if (rs->vassign [sreg] < -1) {
1542                                                 int spill;
1543
1544                                                 /* Need to emit a spill store */
1545                                                 spill = - rs->vassign [sreg] - 1;
1546                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1547                                         }
1548                                         /* force-set sreg2 */
1549                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1550                                 }
1551                         }
1552                         sregs [j] = dest_sreg;
1553                 }
1554                 mono_inst_set_src_registers (ins, sregs);
1555
1556                 /*
1557                  * TRACK DREG
1558                  */
1559                 bank = dreg_bank (spec);
1560                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1561                         prev_dreg = ins->dreg;
1562                 }
1563
1564                 if (spec_dest == 'b') {
1565                         /*
1566                          * The dest reg is read by the instruction, not written, so
1567                          * avoid allocating sreg1/sreg2 to the same reg.
1568                          */
1569                         if (dest_sregs [0] != -1)
1570                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1571                         for (j = 1; j < num_sregs; ++j) {
1572                                 if (dest_sregs [j] != -1)
1573                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1574                         }
1575
1576                         val = rs->vassign [ins->dreg];
1577                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1578                                 /* DREG is already allocated to a register needed for sreg1 */
1579                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1580                         }
1581                 }
1582
1583                 /*
1584                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1585                  * various complex situations.
1586                  */
1587                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1588                         guint32 dreg2, dest_dreg2;
1589
1590                         g_assert (is_soft_reg (ins->dreg, bank));
1591
1592                         if (dest_dreg != -1) {
1593                                 if (rs->vassign [ins->dreg] != dest_dreg)
1594                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1595
1596                                 dreg2 = ins->dreg + 1;
1597                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1598                                 if (dest_dreg2 != -1) {
1599                                         if (rs->vassign [dreg2] != dest_dreg2)
1600                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1601                                 }
1602                         }
1603                 }
1604
1605                 if (dreg_fixed_mask) {
1606                         g_assert (!bank);
1607                         if (is_global_ireg (ins->dreg)) {
1608                                 /*
1609                                  * The argument is already in a hard reg, but that reg is
1610                                  * not usable by this instruction, so allocate a new one.
1611                                  */
1612                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1613                                 if (val < 0)
1614                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1615                                 mono_regstate_free_int (rs, val);
1616                                 dest_dreg = val;
1617
1618                                 /* Fall through */
1619                         }
1620                         else
1621                                 dreg_mask &= dreg_fixed_mask;
1622                 }
1623
1624                 if (is_soft_reg (ins->dreg, bank)) {
1625                         val = rs->vassign [ins->dreg];
1626
1627                         if (val < 0) {
1628                                 int spill = 0;
1629                                 if (val < -1) {
1630                                         /* the register gets spilled after this inst */
1631                                         spill = -val -1;
1632                                 }
1633                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1634                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1635                                 if (spill)
1636                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1637                         }
1638
1639                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1640                         ins->dreg = val;
1641                 }
1642
1643                 /* Handle regpairs */
1644                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1645                         int reg2 = prev_dreg + 1;
1646
1647                         g_assert (!bank);
1648                         g_assert (prev_dreg > -1);
1649                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1650                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1651 #ifdef TARGET_X86
1652                         /* bug #80489 */
1653                         mask &= ~regmask (X86_ECX);
1654 #endif
1655                         val = rs->vassign [reg2];
1656                         if (val < 0) {
1657                                 int spill = 0;
1658                                 if (val < -1) {
1659                                         /* the register gets spilled after this inst */
1660                                         spill = -val -1;
1661                                 }
1662                                 val = mono_regstate_alloc_int (rs, mask);
1663                                 if (val < 0)
1664                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1665                                 if (spill)
1666                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1667                         }
1668                         else {
1669                                 if (! (mask & (regmask (val)))) {
1670                                         val = mono_regstate_alloc_int (rs, mask);
1671                                         if (val < 0)
1672                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1673
1674                                         /* Reallocate hreg to the correct register */
1675                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1676
1677                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1678                                 }
1679                         }
1680
1681                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1682                         assign_reg (cfg, rs, reg2, val, bank);
1683
1684                         dreg_high = val;
1685                         ins->backend.reg3 = val;
1686
1687                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1688                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1689                                 mono_regstate_free_int (rs, val);
1690                         }
1691                 }
1692
1693                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1694                         /*
1695                          * In theory, we could free up the hreg even if the vreg is alive,
1696                          * but branches inside bblocks force us to assign the same hreg
1697                          * to a vreg every time it is encountered.
1698                          */
1699                         int dreg = rs->vassign [prev_dreg];
1700                         g_assert (dreg >= 0);
1701                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1702                         if (G_UNLIKELY (bank))
1703                                 mono_regstate_free_general (rs, dreg, bank);
1704                         else
1705                                 mono_regstate_free_int (rs, dreg);
1706                         rs->vassign [prev_dreg] = -1;
1707                 }
1708
1709                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1710                         /* this instruction only outputs to dest_dreg, need to copy */
1711                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1712                         ins->dreg = dest_dreg;
1713
1714                         if (G_UNLIKELY (bank)) {
1715                                 /* the register we need to free up may be used in another logical regbank
1716                                  * so do a translate just in case.
1717                                  */
1718                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1719                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1720                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1721                         }
1722                         else {
1723                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1724                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1725                         }
1726                 }
1727
1728                 if (spec_dest == 'b') {
1729                         /*
1730                          * The dest reg is read by the instruction, not written, so
1731                          * avoid allocating sreg1/sreg2 to the same reg.
1732                          */
1733                         for (j = 0; j < num_sregs; ++j)
1734                                 if (!sreg_bank (j, spec))
1735                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1736                 }
1737
1738                 /*
1739                  * TRACK CLOBBERING
1740                  */
1741                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1742                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1743                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1744                 }
1745
1746                 if (spec [MONO_INST_CLOB] == 'c') {
1747                         int j, s, dreg, dreg2, cur_bank;
1748                         guint64 clob_mask;
1749
1750                         clob_mask = MONO_ARCH_CALLEE_REGS;
1751
1752                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1753                                 /*
1754                                  * Need to avoid spilling the dreg since the dreg is not really
1755                                  * clobbered by the call.
1756                                  */
1757                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1758                                         dreg = rs->vassign [prev_dreg];
1759                                 else
1760                                         dreg = -1;
1761
1762                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1763                                         dreg2 = rs->vassign [prev_dreg + 1];
1764                                 else
1765                                         dreg2 = -1;
1766
1767                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1768                                         s = regmask (j);
1769                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1770                                                 if ((j != dreg) && (j != dreg2))
1771                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1772                                                 else if (rs->isymbolic [j])
1773                                                         /* The hreg is assigned to the dreg of this instruction */
1774                                                         rs->vassign [rs->isymbolic [j]] = -1;
1775                                                 mono_regstate_free_int (rs, j);
1776                                         }
1777                                 }
1778                         }
1779
1780                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1781                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1782                                         clob_mask = regbank_callee_regs [cur_bank];
1783                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1784                                                 dreg = rs->vassign [prev_dreg];
1785                                         else
1786                                                 dreg = -1;
1787
1788                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1789
1790                                                 /* we are looping though the banks in the outer loop
1791                                                  * so, we don't need to deal with mirrored hregs
1792                                                  * because we will get them in one of the other bank passes.
1793                                                  */
1794                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1795                                                         continue;
1796
1797                                                 s = regmask (j);
1798                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1799                                                         if (j != dreg)
1800                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1801                                                         else if (rs->symbolic [cur_bank] [j])
1802                                                                 /* The hreg is assigned to the dreg of this instruction */
1803                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1804                                                         mono_regstate_free_general (rs, j, cur_bank);
1805                                                 }
1806                                         }
1807                                 }
1808                         }
1809                 }
1810
1811                 /*
1812                  * TRACK ARGUMENT REGS
1813                  */
1814                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1815                         MonoCallInst *call = (MonoCallInst*)ins;
1816                         GSList *list;
1817
1818                         /*
1819                          * This needs to be done before assigning sreg1, so sreg1 will
1820                          * not be assigned one of the argument regs.
1821                          */
1822
1823                         /*
1824                          * Assign all registers in call->out_reg_args to the proper
1825                          * argument registers.
1826                          */
1827
1828                         list = call->out_ireg_args;
1829                         if (list) {
1830                                 while (list) {
1831                                         guint32 regpair;
1832                                         int reg, hreg;
1833
1834                                         regpair = (guint32)(gssize)(list->data);
1835                                         hreg = regpair >> 24;
1836                                         reg = regpair & 0xffffff;
1837
1838                                         assign_reg (cfg, rs, reg, hreg, 0);
1839
1840                                         sreg_masks [0] &= ~(regmask (hreg));
1841
1842                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1843
1844                                         list = g_slist_next (list);
1845                                 }
1846                         }
1847
1848                         list = call->out_freg_args;
1849                         if (list) {
1850                                 while (list) {
1851                                         guint32 regpair;
1852                                         int reg, hreg;
1853
1854                                         regpair = (guint32)(gssize)(list->data);
1855                                         hreg = regpair >> 24;
1856                                         reg = regpair & 0xffffff;
1857
1858                                         assign_reg (cfg, rs, reg, hreg, 1);
1859
1860                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1861
1862                                         list = g_slist_next (list);
1863                                 }
1864                         }
1865                 }
1866
1867                 /*
1868                  * TRACK SREG1
1869                  */
1870                 bank = sreg1_bank (spec);
1871                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1872                         int sreg1 = sregs [0];
1873                         int dest_sreg1 = dest_sregs [0];
1874
1875                         g_assert (is_soft_reg (sreg1, bank));
1876
1877                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1878                         if (dest_sreg1 != -1)
1879                                 g_assert (dest_sreg1 == ins->dreg);
1880                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1881                         g_assert (val >= 0);
1882
1883                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1884                                 // FIXME:
1885                                 g_assert_not_reached ();
1886
1887                         assign_reg (cfg, rs, sreg1, val, bank);
1888
1889                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1890
1891                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1892                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1893                         g_assert (val >= 0);
1894
1895                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1896                                 // FIXME:
1897                                 g_assert_not_reached ();
1898
1899                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1900
1901                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1902
1903                         /* Skip rest of this section */
1904                         dest_sregs [0] = -1;
1905                 }
1906
1907                 if (sreg_fixed_masks [0]) {
1908                         g_assert (!bank);
1909                         if (is_global_ireg (sregs [0])) {
1910                                 /*
1911                                  * The argument is already in a hard reg, but that reg is
1912                                  * not usable by this instruction, so allocate a new one.
1913                                  */
1914                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1915                                 if (val < 0)
1916                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1917                                 mono_regstate_free_int (rs, val);
1918                                 dest_sregs [0] = val;
1919
1920                                 /* Fall through to the dest_sreg1 != -1 case */
1921                         }
1922                         else
1923                                 sreg_masks [0] &= sreg_fixed_masks [0];
1924                 }
1925
1926                 if (dest_sregs [0] != -1) {
1927                         sreg_masks [0] = regmask (dest_sregs [0]);
1928
1929                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1930                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1931                         }
1932                         if (is_global_ireg (sregs [0])) {
1933                                 /* The argument is already in a hard reg, need to copy */
1934                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1935                                 insert_before_ins (bb, ins, copy);
1936                                 sregs [0] = dest_sregs [0];
1937                         }
1938                 }
1939
1940                 if (is_soft_reg (sregs [0], bank)) {
1941                         val = rs->vassign [sregs [0]];
1942                         prev_sregs [0] = sregs [0];
1943                         if (val < 0) {
1944                                 int spill = 0;
1945                                 if (val < -1) {
1946                                         /* the register gets spilled after this inst */
1947                                         spill = -val -1;
1948                                 }
1949
1950                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1951                                         /*
1952                                          * Allocate the same hreg to sreg1 as well so the
1953                                          * peephole can get rid of the move.
1954                                          */
1955                                         sreg_masks [0] = regmask (ins->dreg);
1956                                 }
1957
1958                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1959                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1960                                         sreg_masks [0] = regmask (ins->dreg);
1961
1962                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1963                                 assign_reg (cfg, rs, sregs [0], val, bank);
1964                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1965
1966                                 if (spill) {
1967                                         /*
1968                                          * Need to insert before the instruction since it can
1969                                          * overwrite sreg1.
1970                                          */
1971                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1972                                 }
1973                         }
1974                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1975                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1976                                 insert_before_ins (bb, ins, copy);
1977                                 for (j = 1; j < num_sregs; ++j)
1978                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1979                                 val = dest_sregs [0];
1980                         }
1981
1982                         sregs [0] = val;
1983                 }
1984                 else {
1985                         prev_sregs [0] = -1;
1986                 }
1987                 mono_inst_set_src_registers (ins, sregs);
1988
1989                 for (j = 1; j < num_sregs; ++j)
1990                         sreg_masks [j] &= ~(regmask (sregs [0]));
1991
1992                 /* Handle the case when sreg1 is a regpair but dreg is not */
1993                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1994                         int reg2 = prev_sregs [0] + 1;
1995
1996                         g_assert (!bank);
1997                         g_assert (prev_sregs [0] > -1);
1998                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1999                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2000                         val = rs->vassign [reg2];
2001                         if (val < 0) {
2002                                 int spill = 0;
2003                                 if (val < -1) {
2004                                         /* the register gets spilled after this inst */
2005                                         spill = -val -1;
2006                                 }
2007                                 val = mono_regstate_alloc_int (rs, mask);
2008                                 if (val < 0)
2009                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2010                                 if (spill)
2011                                         g_assert_not_reached ();
2012                         }
2013                         else {
2014                                 if (! (mask & (regmask (val)))) {
2015                                         /* The vreg is already allocated to a wrong hreg */
2016                                         /* FIXME: */
2017                                         g_assert_not_reached ();
2018 #if 0
2019                                         val = mono_regstate_alloc_int (rs, mask);
2020                                         if (val < 0)
2021                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2022
2023                                         /* Reallocate hreg to the correct register */
2024                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2025
2026                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2027 #endif
2028                                 }
2029                         }
2030
2031                         sreg1_high = val;
2032                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2033                         assign_reg (cfg, rs, reg2, val, bank);
2034                 }
2035
2036                 /* Handle dreg==sreg1 */
2037                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2038                         MonoInst *sreg2_copy = NULL;
2039                         MonoInst *copy;
2040                         int bank = reg_bank (spec_src1);
2041
2042                         if (ins->dreg == sregs [1]) {
2043                                 /*
2044                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2045                                  * register for it.
2046                                  */
2047                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2048
2049                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2050                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2051                                 prev_sregs [1] = sregs [1] = reg2;
2052
2053                                 if (G_UNLIKELY (bank))
2054                                         mono_regstate_free_general (rs, reg2, bank);
2055                                 else
2056                                         mono_regstate_free_int (rs, reg2);
2057                         }
2058
2059                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2060                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2061                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2062                                         /* FIXME: */
2063                                         g_assert_not_reached ();
2064
2065                                 /*
2066                                  * sreg1 and dest are already allocated to the same regpair by the
2067                                  * SREG1 allocation code.
2068                                  */
2069                                 g_assert (sregs [0] == ins->dreg);
2070                                 g_assert (dreg_high == sreg1_high);
2071                         }
2072
2073                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2074                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2075                         insert_before_ins (bb, ins, copy);
2076
2077                         if (sreg2_copy)
2078                                 insert_before_ins (bb, copy, sreg2_copy);
2079
2080                         /*
2081                          * Need to prevent sreg2 to be allocated to sreg1, since that
2082                          * would screw up the previous copy.
2083                          */
2084                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2085                         /* we set sreg1 to dest as well */
2086                         prev_sregs [0] = sregs [0] = ins->dreg;
2087                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2088                 }
2089                 mono_inst_set_src_registers (ins, sregs);
2090
2091                 /*
2092                  * TRACK SREG2, 3, ...
2093                  */
2094                 for (j = 1; j < num_sregs; ++j) {
2095                         int k;
2096
2097                         bank = sreg_bank (j, spec);
2098                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2099                                 g_assert_not_reached ();
2100
2101                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2102                                 /*
2103                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2104                                  * allocating it to the fixed reg.
2105                                  */
2106                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2107                                 insert_before_ins (bb, ins, copy);
2108                                 sregs [j] = dest_sregs [j];
2109                         } else if (is_soft_reg (sregs [j], bank)) {
2110                                 val = rs->vassign [sregs [j]];
2111
2112                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2113                                         /*
2114                                          * The sreg is already allocated to a hreg, but not to the fixed
2115                                          * reg required by the instruction. Spill the sreg, so it can be
2116                                          * allocated to the fixed reg by the code below.
2117                                          */
2118                                         /* Currently, this code should only be hit for CAS */
2119                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2120                                         val = rs->vassign [sregs [j]];
2121                                 }
2122
2123                                 if (val < 0) {
2124                                         int spill = 0;
2125                                         if (val < -1) {
2126                                                 /* the register gets spilled after this inst */
2127                                                 spill = -val -1;
2128                                         }
2129                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2130                                         assign_reg (cfg, rs, sregs [j], val, bank);
2131                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2132                                         if (spill) {
2133                                                 /*
2134                                                  * Need to insert before the instruction since it can
2135                                                  * overwrite sreg2.
2136                                                  */
2137                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2138                                         }
2139                                 }
2140                                 sregs [j] = val;
2141                                 for (k = j + 1; k < num_sregs; ++k)
2142                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2143                         }
2144                         else {
2145                                 prev_sregs [j] = -1;
2146                         }
2147                 }
2148                 mono_inst_set_src_registers (ins, sregs);
2149
2150                 /* Sanity check */
2151                 /* Do this only for CAS for now */
2152                 for (j = 1; j < num_sregs; ++j) {
2153                         int sreg = sregs [j];
2154                         int dest_sreg = dest_sregs [j];
2155
2156                         if (j == 2 && dest_sreg != -1) {
2157                                 int k;
2158
2159                                 g_assert (sreg == dest_sreg);
2160
2161                                 for (k = 0; k < num_sregs; ++k) {
2162                                         if (k != j)
2163                                                 g_assert (sregs [k] != dest_sreg);
2164                                 }
2165                         }
2166                 }
2167
2168                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2169                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2170                         mono_regstate_free_int (rs, ins->sreg1);
2171                 }
2172                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2173                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2174                         mono_regstate_free_int (rs, ins->sreg2);
2175                 }*/
2176
2177                 DEBUG (mono_print_ins_index (i, ins));
2178         }
2179
2180         // FIXME: Set MAX_FREGS to 8
2181         // FIXME: Optimize generated code
2182 #if MONO_ARCH_USE_FPSTACK
2183         /*
2184          * Make a forward pass over the code, simulating the fp stack, making sure the
2185          * arguments required by the fp opcodes are at the top of the stack.
2186          */
2187         if (has_fp) {
2188                 MonoInst *prev = NULL;
2189                 MonoInst *fxch;
2190                 int tmp;
2191
2192                 g_assert (num_sregs <= 2);
2193
2194                 for (ins = bb->code; ins; ins = ins->next) {
2195                         spec = ins_get_spec (ins->opcode);
2196
2197                         DEBUG (printf ("processing:"));
2198                         DEBUG (mono_print_ins_index (0, ins));
2199
2200                         if (ins->opcode == OP_FMOVE) {
2201                                 /* Do it by renaming the source to the destination on the stack */
2202                                 // FIXME: Is this correct ?
2203                                 for (i = 0; i < sp; ++i)
2204                                         if (fpstack [i] == ins->sreg1)
2205                                                 fpstack [i] = ins->dreg;
2206                                 prev = ins;
2207                                 continue;
2208                         }
2209
2210                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2211                                 /* Arg1 must be in %st(1) */
2212                                 g_assert (prev);
2213
2214                                 i = 0;
2215                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2216                                         i ++;
2217                                 g_assert (i < sp);
2218
2219                                 if (sp - 1 - i > 0) {
2220                                         /* First move it to %st(0) */
2221                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2222
2223                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2224                                         fxch->inst_imm = sp - 1 - i;
2225
2226                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2227                                         prev = fxch;
2228
2229                                         tmp = fpstack [sp - 1];
2230                                         fpstack [sp - 1] = fpstack [i];
2231                                         fpstack [i] = tmp;
2232                                 }
2233
2234                                 /* Then move it to %st(1) */
2235                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2236
2237                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2238                                 fxch->inst_imm = 1;
2239
2240                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2241                                 prev = fxch;
2242
2243                                 tmp = fpstack [sp - 1];
2244                                 fpstack [sp - 1] = fpstack [sp - 2];
2245                                 fpstack [sp - 2] = tmp;
2246                         }
2247
2248                         if (sreg2_is_fp (spec)) {
2249                                 g_assert (sp > 0);
2250
2251                                 if (fpstack [sp - 1] != ins->sreg2) {
2252                                         g_assert (prev);
2253
2254                                         i = 0;
2255                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2256                                                 i ++;
2257                                         g_assert (i < sp);
2258
2259                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2260
2261                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2262                                         fxch->inst_imm = sp - 1 - i;
2263
2264                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2265                                         prev = fxch;
2266
2267                                         tmp = fpstack [sp - 1];
2268                                         fpstack [sp - 1] = fpstack [i];
2269                                         fpstack [i] = tmp;
2270                                 }
2271
2272                                 sp --;
2273                         }
2274
2275                         if (sreg1_is_fp (spec)) {
2276                                 g_assert (sp > 0);
2277
2278                                 if (fpstack [sp - 1] != ins->sreg1) {
2279                                         g_assert (prev);
2280
2281                                         i = 0;
2282                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2283                                                 i ++;
2284                                         g_assert (i < sp);
2285
2286                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2287
2288                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2289                                         fxch->inst_imm = sp - 1 - i;
2290
2291                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2292                                         prev = fxch;
2293
2294                                         tmp = fpstack [sp - 1];
2295                                         fpstack [sp - 1] = fpstack [i];
2296                                         fpstack [i] = tmp;
2297                                 }
2298
2299                                 sp --;
2300                         }
2301
2302                         if (dreg_is_fp (spec)) {
2303                                 g_assert (sp < 8);
2304                                 fpstack [sp ++] = ins->dreg;
2305                         }
2306
2307                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2308                                 printf ("\t[");
2309                                 for (i = 0; i < sp; ++i)
2310                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2311                                 printf ("]\n");
2312                         }
2313
2314                         prev = ins;
2315                 }
2316
2317                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2318                         /* Remove remaining items from the fp stack */
2319                         /*
2320                          * These can remain for example as a result of a dead fmove like in
2321                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2322                          */
2323                         while (sp) {
2324                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2325                                 mono_add_ins_to_end (bb, ins);
2326                                 sp --;
2327                         }
2328                 }
2329         }
2330 #endif
2331 }
2332
2333 CompRelation
2334 mono_opcode_to_cond (int opcode)
2335 {
2336         switch (opcode) {
2337         case OP_CEQ:
2338         case OP_IBEQ:
2339         case OP_ICEQ:
2340         case OP_LBEQ:
2341         case OP_LCEQ:
2342         case OP_FBEQ:
2343         case OP_FCEQ:
2344         case OP_RBEQ:
2345         case OP_RCEQ:
2346         case OP_COND_EXC_EQ:
2347         case OP_COND_EXC_IEQ:
2348         case OP_CMOV_IEQ:
2349         case OP_CMOV_LEQ:
2350                 return CMP_EQ;
2351         case OP_FCNEQ:
2352         case OP_ICNEQ:
2353         case OP_IBNE_UN:
2354         case OP_LBNE_UN:
2355         case OP_FBNE_UN:
2356         case OP_COND_EXC_NE_UN:
2357         case OP_COND_EXC_INE_UN:
2358         case OP_CMOV_INE_UN:
2359         case OP_CMOV_LNE_UN:
2360                 return CMP_NE;
2361         case OP_FCLE:
2362         case OP_ICLE:
2363         case OP_IBLE:
2364         case OP_LBLE:
2365         case OP_FBLE:
2366         case OP_CMOV_ILE:
2367         case OP_CMOV_LLE:
2368                 return CMP_LE;
2369         case OP_FCGE:
2370         case OP_ICGE:
2371         case OP_IBGE:
2372         case OP_LBGE:
2373         case OP_FBGE:
2374         case OP_CMOV_IGE:
2375         case OP_CMOV_LGE:
2376                 return CMP_GE;
2377         case OP_CLT:
2378         case OP_IBLT:
2379         case OP_ICLT:
2380         case OP_LBLT:
2381         case OP_LCLT:
2382         case OP_FBLT:
2383         case OP_FCLT:
2384         case OP_RBLT:
2385         case OP_RCLT:
2386         case OP_COND_EXC_LT:
2387         case OP_COND_EXC_ILT:
2388         case OP_CMOV_ILT:
2389         case OP_CMOV_LLT:
2390                 return CMP_LT;
2391         case OP_CGT:
2392         case OP_IBGT:
2393         case OP_ICGT:
2394         case OP_LBGT:
2395         case OP_LCGT:
2396         case OP_FBGT:
2397         case OP_FCGT:
2398         case OP_RBGT:
2399         case OP_RCGT:
2400         case OP_COND_EXC_GT:
2401         case OP_COND_EXC_IGT:
2402         case OP_CMOV_IGT:
2403         case OP_CMOV_LGT:
2404                 return CMP_GT;
2405
2406         case OP_ICLE_UN:
2407         case OP_IBLE_UN:
2408         case OP_LBLE_UN:
2409         case OP_FBLE_UN:
2410         case OP_COND_EXC_LE_UN:
2411         case OP_COND_EXC_ILE_UN:
2412         case OP_CMOV_ILE_UN:
2413         case OP_CMOV_LLE_UN:
2414                 return CMP_LE_UN;
2415
2416         case OP_ICGE_UN:
2417         case OP_IBGE_UN:
2418         case OP_LBGE_UN:
2419         case OP_FBGE_UN:
2420         case OP_CMOV_IGE_UN:
2421         case OP_CMOV_LGE_UN:
2422                 return CMP_GE_UN;
2423         case OP_CLT_UN:
2424         case OP_IBLT_UN:
2425         case OP_ICLT_UN:
2426         case OP_LBLT_UN:
2427         case OP_LCLT_UN:
2428         case OP_FBLT_UN:
2429         case OP_FCLT_UN:
2430         case OP_RBLT_UN:
2431         case OP_RCLT_UN:
2432         case OP_COND_EXC_LT_UN:
2433         case OP_COND_EXC_ILT_UN:
2434         case OP_CMOV_ILT_UN:
2435         case OP_CMOV_LLT_UN:
2436                 return CMP_LT_UN;
2437         case OP_CGT_UN:
2438         case OP_IBGT_UN:
2439         case OP_ICGT_UN:
2440         case OP_LBGT_UN:
2441         case OP_LCGT_UN:
2442         case OP_FCGT_UN:
2443         case OP_FBGT_UN:
2444         case OP_RCGT_UN:
2445         case OP_RBGT_UN:
2446         case OP_COND_EXC_GT_UN:
2447         case OP_COND_EXC_IGT_UN:
2448         case OP_CMOV_IGT_UN:
2449         case OP_CMOV_LGT_UN:
2450                 return CMP_GT_UN;
2451         default:
2452                 printf ("%s\n", mono_inst_name (opcode));
2453                 g_assert_not_reached ();
2454                 return (CompRelation)0;
2455         }
2456 }
2457
2458 CompRelation
2459 mono_negate_cond (CompRelation cond)
2460 {
2461         switch (cond) {
2462         case CMP_EQ:
2463                 return CMP_NE;
2464         case CMP_NE:
2465                 return CMP_EQ;
2466         case CMP_LE:
2467                 return CMP_GT;
2468         case CMP_GE:
2469                 return CMP_LT;
2470         case CMP_LT:
2471                 return CMP_GE;
2472         case CMP_GT:
2473                 return CMP_LE;
2474         case CMP_LE_UN:
2475                 return CMP_GT_UN;
2476         case CMP_GE_UN:
2477                 return CMP_LT_UN;
2478         case CMP_LT_UN:
2479                 return CMP_GE_UN;
2480         case CMP_GT_UN:
2481                 return CMP_LE_UN;
2482         default:
2483                 g_assert_not_reached ();
2484         }
2485 }
2486
2487 CompType
2488 mono_opcode_to_type (int opcode, int cmp_opcode)
2489 {
2490         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2491                 return CMP_TYPE_L;
2492         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2493                 return CMP_TYPE_I;
2494         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2495                 return CMP_TYPE_I;
2496         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2497                 return CMP_TYPE_L;
2498         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2499                 return CMP_TYPE_L;
2500         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2501                 return CMP_TYPE_F;
2502         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2503                 return CMP_TYPE_F;
2504         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2505                 return CMP_TYPE_I;
2506         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2507                 switch (cmp_opcode) {
2508                 case OP_ICOMPARE:
2509                 case OP_ICOMPARE_IMM:
2510                         return CMP_TYPE_I;
2511                 default:
2512                         return CMP_TYPE_L;
2513                 }
2514         } else {
2515                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2516                 return (CompType)0;
2517         }
2518 }
2519
2520 #endif /* DISABLE_JIT */
2521
2522 gboolean
2523 mono_is_regsize_var (MonoType *t)
2524 {
2525         t = mini_get_underlying_type (t);
2526         switch (t->type) {
2527         case MONO_TYPE_I1:
2528         case MONO_TYPE_U1:
2529         case MONO_TYPE_I2:
2530         case MONO_TYPE_U2:
2531         case MONO_TYPE_I4:
2532         case MONO_TYPE_U4:
2533         case MONO_TYPE_I:
2534         case MONO_TYPE_U:
2535         case MONO_TYPE_PTR:
2536         case MONO_TYPE_FNPTR:
2537 #if SIZEOF_REGISTER == 8
2538         case MONO_TYPE_I8:
2539         case MONO_TYPE_U8:
2540 #endif
2541                 return TRUE;
2542         case MONO_TYPE_OBJECT:
2543         case MONO_TYPE_STRING:
2544         case MONO_TYPE_CLASS:
2545         case MONO_TYPE_SZARRAY:
2546         case MONO_TYPE_ARRAY:
2547                 return TRUE;
2548         case MONO_TYPE_GENERICINST:
2549                 if (!mono_type_generic_inst_is_valuetype (t))
2550                         return TRUE;
2551                 return FALSE;
2552         case MONO_TYPE_VALUETYPE:
2553                 return FALSE;
2554         default:
2555                 return FALSE;
2556         }
2557 }
2558
2559 #ifndef DISABLE_JIT
2560
2561 /*
2562  * mono_peephole_ins:
2563  *
2564  *   Perform some architecture independent peephole optimizations.
2565  */
2566 void
2567 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2568 {
2569         int filter = FILTER_IL_SEQ_POINT;
2570         MonoInst *last_ins = mono_inst_prev (ins, filter);
2571
2572         switch (ins->opcode) {
2573         case OP_MUL_IMM:
2574                 /* remove unnecessary multiplication with 1 */
2575                 if (ins->inst_imm == 1) {
2576                         if (ins->dreg != ins->sreg1)
2577                                 ins->opcode = OP_MOVE;
2578                         else
2579                                 MONO_DELETE_INS (bb, ins);
2580                 }
2581                 break;
2582         case OP_LOAD_MEMBASE:
2583         case OP_LOADI4_MEMBASE:
2584                 /*
2585                  * Note: if reg1 = reg2 the load op is removed
2586                  *
2587                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2588                  * OP_LOAD_MEMBASE offset(basereg), reg2
2589                  * -->
2590                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2591                  * OP_MOVE reg1, reg2
2592                  */
2593                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2594                         last_ins = mono_inst_prev (ins, filter);
2595                 if (last_ins &&
2596                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2597                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2598                         ins->inst_basereg == last_ins->inst_destbasereg &&
2599                         ins->inst_offset == last_ins->inst_offset) {
2600                         if (ins->dreg == last_ins->sreg1) {
2601                                 MONO_DELETE_INS (bb, ins);
2602                                 break;
2603                         } else {
2604                                 ins->opcode = OP_MOVE;
2605                                 ins->sreg1 = last_ins->sreg1;
2606                         }
2607
2608                         /*
2609                          * Note: reg1 must be different from the basereg in the second load
2610                          * Note: if reg1 = reg2 is equal then second load is removed
2611                          *
2612                          * OP_LOAD_MEMBASE offset(basereg), reg1
2613                          * OP_LOAD_MEMBASE offset(basereg), reg2
2614                          * -->
2615                          * OP_LOAD_MEMBASE offset(basereg), reg1
2616                          * OP_MOVE reg1, reg2
2617                          */
2618                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2619                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2620                           ins->inst_basereg != last_ins->dreg &&
2621                           ins->inst_basereg == last_ins->inst_basereg &&
2622                           ins->inst_offset == last_ins->inst_offset) {
2623
2624                         if (ins->dreg == last_ins->dreg) {
2625                                 MONO_DELETE_INS (bb, ins);
2626                         } else {
2627                                 ins->opcode = OP_MOVE;
2628                                 ins->sreg1 = last_ins->dreg;
2629                         }
2630
2631                         //g_assert_not_reached ();
2632
2633 #if 0
2634                         /*
2635                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2636                          * OP_LOAD_MEMBASE offset(basereg), reg
2637                          * -->
2638                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2639                          * OP_ICONST reg, imm
2640                          */
2641                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2642                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2643                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2644                                    ins->inst_offset == last_ins->inst_offset) {
2645                         ins->opcode = OP_ICONST;
2646                         ins->inst_c0 = last_ins->inst_imm;
2647                         g_assert_not_reached (); // check this rule
2648 #endif
2649                 }
2650                 break;
2651         case OP_LOADI1_MEMBASE:
2652         case OP_LOADU1_MEMBASE:
2653                 /*
2654                  * Note: if reg1 = reg2 the load op is removed
2655                  *
2656                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2657                  * OP_LOAD_MEMBASE offset(basereg), reg2
2658                  * -->
2659                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2660                  * OP_MOVE reg1, reg2
2661                  */
2662                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2663                         ins->inst_basereg == last_ins->inst_destbasereg &&
2664                         ins->inst_offset == last_ins->inst_offset) {
2665                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2666                         ins->sreg1 = last_ins->sreg1;
2667                 }
2668                 break;
2669         case OP_LOADI2_MEMBASE:
2670         case OP_LOADU2_MEMBASE:
2671                 /*
2672                  * Note: if reg1 = reg2 the load op is removed
2673                  *
2674                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2675                  * OP_LOAD_MEMBASE offset(basereg), reg2
2676                  * -->
2677                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2678                  * OP_MOVE reg1, reg2
2679                  */
2680                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2681                         ins->inst_basereg == last_ins->inst_destbasereg &&
2682                         ins->inst_offset == last_ins->inst_offset) {
2683 #if SIZEOF_REGISTER == 8
2684                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2685 #else
2686                         /* The definition of OP_PCONV_TO_U2 is wrong */
2687                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2688 #endif
2689                         ins->sreg1 = last_ins->sreg1;
2690                 }
2691                 break;
2692         case OP_MOVE:
2693         case OP_FMOVE:
2694                 /*
2695                  * Removes:
2696                  *
2697                  * OP_MOVE reg, reg
2698                  */
2699                 if (ins->dreg == ins->sreg1) {
2700                         MONO_DELETE_INS (bb, ins);
2701                         break;
2702                 }
2703                 /*
2704                  * Removes:
2705                  *
2706                  * OP_MOVE sreg, dreg
2707                  * OP_MOVE dreg, sreg
2708                  */
2709                 if (last_ins && last_ins->opcode == ins->opcode &&
2710                         ins->sreg1 == last_ins->dreg &&
2711                         ins->dreg == last_ins->sreg1) {
2712                         MONO_DELETE_INS (bb, ins);
2713                 }
2714                 break;
2715         case OP_NOP:
2716                 MONO_DELETE_INS (bb, ins);
2717                 break;
2718         }
2719 }
2720
2721 int
2722 mini_exception_id_by_name (const char *name)
2723 {
2724         if (strcmp (name, "IndexOutOfRangeException") == 0)
2725                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2726         if (strcmp (name, "OverflowException") == 0)
2727                 return MONO_EXC_OVERFLOW;
2728         if (strcmp (name, "ArithmeticException") == 0)
2729                 return MONO_EXC_ARITHMETIC;
2730         if (strcmp (name, "DivideByZeroException") == 0)
2731                 return MONO_EXC_DIVIDE_BY_ZERO;
2732         if (strcmp (name, "InvalidCastException") == 0)
2733                 return MONO_EXC_INVALID_CAST;
2734         if (strcmp (name, "NullReferenceException") == 0)
2735                 return MONO_EXC_NULL_REF;
2736         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2737                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2738         if (strcmp (name, "ArgumentException") == 0)
2739                 return MONO_EXC_ARGUMENT;
2740         g_error ("Unknown intrinsic exception %s\n", name);
2741         return -1;
2742 }
2743
2744 gboolean
2745 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2746 {
2747         MonoClass *klass;
2748         gpointer iter;
2749         MonoClassField *field;
2750         MonoType *ftype, *prev_ftype = NULL;
2751         int nfields = 0;
2752
2753         klass = mono_class_from_mono_type (t);
2754         iter = NULL;
2755         while ((field = mono_class_get_fields (klass, &iter))) {
2756                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2757                         continue;
2758                 ftype = mono_field_get_type (field);
2759                 ftype = mini_native_type_replace_type (ftype);
2760
2761                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2762                         int nested_nfields, nested_esize;
2763
2764                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2765                                 return FALSE;
2766                         if (nested_esize == 4)
2767                                 ftype = &mono_defaults.single_class->byval_arg;
2768                         else
2769                                 ftype = &mono_defaults.double_class->byval_arg;
2770                         if (prev_ftype && prev_ftype->type != ftype->type)
2771                                 return FALSE;
2772                         prev_ftype = ftype;
2773                         nfields += nested_nfields;
2774                 } else {
2775                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2776                                 return FALSE;
2777                         if (prev_ftype && prev_ftype->type != ftype->type)
2778                                 return FALSE;
2779                         prev_ftype = ftype;
2780                         nfields ++;
2781                 }
2782         }
2783         if (nfields == 0)
2784                 return FALSE;
2785         *out_nfields = nfields;
2786         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2787         return TRUE;
2788 }
2789
2790 MonoRegState*
2791 mono_regstate_new (void)
2792 {
2793         MonoRegState* rs = g_new0 (MonoRegState, 1);
2794
2795         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2796 #ifdef MONO_ARCH_NEED_SIMD_BANK
2797         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2798 #endif
2799
2800         return rs;
2801 }
2802
2803 void
2804 mono_regstate_free (MonoRegState *rs) {
2805         g_free (rs->vassign);
2806         g_free (rs);
2807 }
2808
2809 #endif /* DISABLE_JIT */