2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
13 #include <mono/metadata/appdomain.h>
14 #include <mono/metadata/debug-helpers.h>
15 #include <mono/metadata/threads.h>
16 #include <mono/metadata/profiler-private.h>
17 #include <mono/metadata/mempool-internals.h>
18 #include <mono/utils/mono-math.h>
22 #include "mini-arch.h"
24 #ifndef MONO_MAX_XREGS
26 #define MONO_MAX_XREGS 0
27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
28 #define MONO_ARCH_CALLEE_XREGS 0
33 #define MONO_ARCH_BANK_MIRRORED -2
35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
37 #ifndef MONO_ARCH_NEED_SIMD_BANK
38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
49 #define get_mirrored_bank(bank) (-1)
51 #define is_hreg_mirrored(rs, bank, hreg) (0)
56 /* If the bank is mirrored return the true logical bank that the register in the
57 * physical register bank is allocated to.
59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
60 return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
64 * Every hardware register belongs to a register type or register bank. bank 0
65 * contains the int registers, bank 1 contains the fp registers.
66 * int registers are used 99% of the time, so they are special cased in a lot of
70 static const int regbank_size [] = {
78 static const int regbank_load_ops [] = {
86 static const int regbank_store_ops [] = {
87 OP_STORER_MEMBASE_REG,
88 OP_STORER8_MEMBASE_REG,
89 OP_STORER_MEMBASE_REG,
90 OP_STORER_MEMBASE_REG,
94 static const int regbank_move_ops [] = {
102 #define regmask(reg) (((regmask_t)1) << (reg))
104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
105 static const regmask_t regbank_callee_saved_regs [] = {
106 MONO_ARCH_CALLEE_SAVED_REGS,
107 MONO_ARCH_CALLEE_SAVED_FREGS,
108 MONO_ARCH_CALLEE_SAVED_REGS,
109 MONO_ARCH_CALLEE_SAVED_REGS,
110 MONO_ARCH_CALLEE_SAVED_XREGS,
114 static const regmask_t regbank_callee_regs [] = {
115 MONO_ARCH_CALLEE_REGS,
116 MONO_ARCH_CALLEE_FREGS,
117 MONO_ARCH_CALLEE_REGS,
118 MONO_ARCH_CALLEE_REGS,
119 MONO_ARCH_CALLEE_XREGS,
122 static const int regbank_spill_var_size[] = {
127 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
133 mono_regstate_assign (MonoRegState *rs)
135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
136 /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
137 * if the values here are not the same.
139 g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
140 g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
141 g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
144 if (rs->next_vreg > rs->vassign_size) {
145 g_free (rs->vassign);
146 rs->vassign_size = MAX (rs->next_vreg, 256);
147 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
150 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
151 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
153 rs->symbolic [MONO_REG_INT] = rs->isymbolic;
154 rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
156 #ifdef MONO_ARCH_NEED_SIMD_BANK
157 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
158 rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
165 regmask_t mask = allow & rs->ifree_mask;
167 #if defined(__x86_64__) && defined(__GNUC__)
174 __asm__("bsfq %1,%0\n\t"
175 : "=r" (i) : "rm" (mask));
177 rs->ifree_mask &= ~ ((regmask_t)1 << i);
183 for (i = 0; i < MONO_MAX_IREGS; ++i) {
184 if (mask & ((regmask_t)1 << i)) {
185 rs->ifree_mask &= ~ ((regmask_t)1 << i);
194 mono_regstate_free_int (MonoRegState *rs, int reg)
197 rs->ifree_mask |= (regmask_t)1 << reg;
198 rs->isymbolic [reg] = 0;
203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
207 regmask_t mask = allow & rs->free_mask [bank];
208 for (i = 0; i < regbank_size [bank]; ++i) {
209 if (mask & ((regmask_t)1 << i)) {
210 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
212 mirrored_bank = get_mirrored_bank (bank);
213 if (mirrored_bank == -1)
216 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
229 rs->free_mask [bank] |= (regmask_t)1 << reg;
230 rs->symbolic [bank][reg] = 0;
232 mirrored_bank = get_mirrored_bank (bank);
233 if (mirrored_bank == -1)
235 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
236 rs->symbolic [mirrored_bank][reg] = 0;
241 mono_regname_full (int reg, int bank)
243 if (G_UNLIKELY (bank)) {
244 #if MONO_ARCH_NEED_SIMD_BANK
245 if (bank == MONO_REG_SIMD)
246 return mono_arch_xregname (reg);
248 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
249 return mono_arch_regname (reg);
250 g_assert (bank == MONO_REG_DOUBLE);
251 return mono_arch_fregname (reg);
253 return mono_arch_regname (reg);
258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
262 regpair = (((guint32)hreg) << 24) + vreg;
263 if (G_UNLIKELY (bank)) {
264 g_assert (vreg >= regbank_size [bank]);
265 g_assert (hreg < regbank_size [bank]);
266 call->used_fregs |= 1 << hreg;
267 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
269 g_assert (vreg >= MONO_MAX_IREGS);
270 g_assert (hreg < MONO_MAX_IREGS);
271 call->used_iregs |= 1 << hreg;
272 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
277 * mono_call_inst_add_outarg_vt:
279 * Register OUTARG_VT as belonging to CALL.
282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
284 call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
288 resize_spill_info (MonoCompile *cfg, int bank)
290 MonoSpillInfo *orig_info = cfg->spill_info [bank];
291 int orig_len = cfg->spill_info_len [bank];
292 int new_len = orig_len ? orig_len * 2 : 16;
293 MonoSpillInfo *new_info;
296 g_assert (bank < MONO_NUM_REGBANKS);
298 new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
300 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
301 for (i = orig_len; i < new_len; ++i)
302 new_info [i].offset = -1;
304 cfg->spill_info [bank] = new_info;
305 cfg->spill_info_len [bank] = new_len;
309 * returns the offset used by spillvar. It allocates a new
310 * spill variable if necessary.
313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
318 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
319 while (spillvar >= cfg->spill_info_len [bank])
320 resize_spill_info (cfg, bank);
324 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
326 info = &cfg->spill_info [bank][spillvar];
327 if (info->offset == -1) {
328 cfg->stack_offset += sizeof (mgreg_t) - 1;
329 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
331 g_assert (bank < MONO_NUM_REGBANKS);
332 if (G_UNLIKELY (bank))
333 size = regbank_spill_var_size [bank];
335 size = sizeof (mgreg_t);
337 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
338 cfg->stack_offset += size - 1;
339 cfg->stack_offset &= ~(size - 1);
340 info->offset = cfg->stack_offset;
341 cfg->stack_offset += size;
343 cfg->stack_offset += size - 1;
344 cfg->stack_offset &= ~(size - 1);
345 cfg->stack_offset += size;
346 info->offset = - cfg->stack_offset;
353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
366 #ifndef MONO_ARCH_INST_IS_FLOAT
367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
371 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
376 #define reg_is_simd(desc) ((desc) == 'x')
378 #ifdef MONO_ARCH_NEED_SIMD_BANK
380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
384 #define reg_bank(desc) reg_is_fp ((desc))
388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
389 #define sreg1_bank(spec) sreg_bank (0, (spec))
390 #define sreg2_bank(spec) sreg_bank (1, (spec))
391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
401 #undef is_global_ireg
402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
411 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
416 static const char* const patch_info_str[] = {
417 #define PATCH_INFO(a,b) "" #a,
418 #include "patch-info.h"
423 mono_ji_type_to_string (MonoJumpInfoType type)
425 return patch_info_str [type];
429 mono_print_ji (const MonoJumpInfo *ji)
432 case MONO_PATCH_INFO_RGCTX_FETCH: {
433 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
435 printf ("[RGCTX_FETCH ");
436 mono_print_ji (entry->data);
437 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
440 case MONO_PATCH_INFO_METHODCONST: {
441 char *s = mono_method_full_name (ji->data.method, TRUE);
442 printf ("[METHODCONST - %s]", s);
446 case MONO_PATCH_INFO_INTERNAL_METHOD: {
447 printf ("[INTERNAL_METHOD - %s]", ji->data.name);
451 printf ("[%s]", patch_info_str [ji->type]);
457 mono_print_ins_index (int i, MonoInst *ins)
459 const char *spec = ins_get_spec (ins->opcode);
461 int sregs [MONO_MAX_SRC_REGS];
464 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
466 printf (" %s", mono_inst_name (ins->opcode));
467 if (spec == MONO_ARCH_CPU_SPEC) {
468 gboolean dest_base = FALSE;
469 switch (ins->opcode) {
470 case OP_STOREV_MEMBASE:
477 /* This is a lowered opcode */
478 if (ins->dreg != -1) {
480 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
482 printf (" R%d <-", ins->dreg);
484 if (ins->sreg1 != -1)
485 printf (" R%d", ins->sreg1);
486 if (ins->sreg2 != -1)
487 printf (" R%d", ins->sreg2);
488 if (ins->sreg3 != -1)
489 printf (" R%d", ins->sreg3);
491 switch (ins->opcode) {
502 if (!ins->inst_false_bb)
503 printf (" [B%d]", ins->inst_true_bb->block_num);
505 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
512 printf (" [%d (", (int)ins->inst_c0);
513 for (i = 0; i < ins->inst_phi_args [0]; i++) {
516 printf ("R%d", ins->inst_phi_args [i + 1]);
522 case OP_OUTARG_VTRETADDR:
523 printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
526 case OP_GSHAREDVT_ARG_REGOFFSET:
527 printf (" + 0x%lx", (long)ins->inst_offset);
534 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
538 if (spec [MONO_INST_DEST]) {
539 int bank = dreg_bank (spec);
540 if (is_soft_reg (ins->dreg, bank)) {
541 if (spec [MONO_INST_DEST] == 'b') {
542 if (ins->inst_offset == 0)
543 printf (" [R%d] <-", ins->dreg);
545 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
548 printf (" R%d <-", ins->dreg);
549 } else if (spec [MONO_INST_DEST] == 'b') {
550 if (ins->inst_offset == 0)
551 printf (" [%s] <-", mono_arch_regname (ins->dreg));
553 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
555 printf (" %s <-", mono_regname_full (ins->dreg, bank));
557 if (spec [MONO_INST_SRC1]) {
558 int bank = sreg1_bank (spec);
559 if (is_soft_reg (ins->sreg1, bank)) {
560 if (spec [MONO_INST_SRC1] == 'b')
561 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
563 printf (" R%d", ins->sreg1);
564 } else if (spec [MONO_INST_SRC1] == 'b')
565 printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
567 printf (" %s", mono_regname_full (ins->sreg1, bank));
569 num_sregs = mono_inst_get_src_registers (ins, sregs);
570 for (j = 1; j < num_sregs; ++j) {
571 int bank = sreg_bank (j, spec);
572 if (is_soft_reg (sregs [j], bank))
573 printf (" R%d", sregs [j]);
575 printf (" %s", mono_regname_full (sregs [j], bank));
578 switch (ins->opcode) {
580 printf (" [%d]", (int)ins->inst_c0);
582 #if defined(TARGET_X86) || defined(TARGET_AMD64)
583 case OP_X86_PUSH_IMM:
585 case OP_ICOMPARE_IMM:
593 case OP_STORE_MEMBASE_IMM:
594 printf (" [%d]", (int)ins->inst_imm);
598 printf (" [%d]", (int)(gssize)ins->inst_p1);
601 printf (" [%lld]", (long long)ins->inst_l);
604 printf (" [%f]", *(double*)ins->inst_p0);
607 printf (" [%f]", *(float*)ins->inst_p0);
610 case OP_CALL_MEMBASE:
616 case OP_VCALL_MEMBASE:
619 case OP_VCALL2_MEMBASE:
621 case OP_VOIDCALL_MEMBASE:
623 MonoCallInst *call = (MonoCallInst*)ins;
626 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
628 * These are lowered opcodes, but they are in the .md files since the old
629 * JIT passes them to backends.
632 printf (" R%d <-", ins->dreg);
636 char *full_name = mono_method_full_name (call->method, TRUE);
637 printf (" [%s]", full_name);
639 } else if (call->fptr_is_patch) {
640 MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
644 } else if (call->fptr) {
645 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
647 printf (" [%s]", info->name);
650 list = call->out_ireg_args;
655 regpair = (guint32)(gssize)(list->data);
656 hreg = regpair >> 24;
657 reg = regpair & 0xffffff;
659 printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
661 list = g_slist_next (list);
663 list = call->out_freg_args;
668 regpair = (guint32)(gssize)(list->data);
669 hreg = regpair >> 24;
670 reg = regpair & 0xffffff;
672 printf (" [%s <- R%d]", mono_arch_fregname (hreg), reg);
674 list = g_slist_next (list);
679 case OP_CALL_HANDLER:
680 printf (" [B%d]", ins->inst_target_bb->block_num);
702 if (!ins->inst_false_bb)
703 printf (" [B%d]", ins->inst_true_bb->block_num);
705 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
707 case OP_LIVERANGE_START:
708 case OP_LIVERANGE_END:
709 case OP_GC_LIVENESS_DEF:
710 case OP_GC_LIVENESS_USE:
711 printf (" R%d", (int)ins->inst_c1);
713 case OP_IL_SEQ_POINT:
715 printf (" il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
721 if (spec [MONO_INST_CLOB])
722 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
727 print_regtrack (RegTrack *t, int num)
733 for (i = 0; i < num; ++i) {
736 if (i >= MONO_MAX_IREGS) {
737 g_snprintf (buf, sizeof(buf), "R%d", i);
740 r = mono_arch_regname (i);
741 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
747 mono_ji_type_to_string (MonoJumpInfoType type)
753 mono_print_ji (const MonoJumpInfo *ji)
758 mono_print_ins_index (int i, MonoInst *ins)
761 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
764 mono_print_ins (MonoInst *ins)
766 mono_print_ins_index (-1, ins);
770 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
773 * If this function is called multiple times, the new instructions are inserted
774 * in the proper order.
776 mono_bblock_insert_before_ins (bb, ins, to_insert);
780 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
783 * If this function is called multiple times, the new instructions are inserted in
786 mono_bblock_insert_after_ins (bb, *last, to_insert);
792 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
794 if (vreg_is_ref (cfg, reg))
795 return MONO_REG_INT_REF;
796 else if (vreg_is_mp (cfg, reg))
797 return MONO_REG_INT_MP;
803 * Force the spilling of the variable in the symbolic register 'reg', and free
804 * the hreg it was assigned to.
807 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
811 MonoRegState *rs = cfg->rs;
813 sel = rs->vassign [reg];
815 /* the vreg we need to spill lives in another logical reg bank */
816 bank = translate_bank (cfg->rs, bank, sel);
818 /*i = rs->isymbolic [sel];
819 g_assert (i == reg);*/
821 spill = ++cfg->spill_count;
822 rs->vassign [i] = -spill - 1;
823 if (G_UNLIKELY (bank))
824 mono_regstate_free_general (rs, sel, bank);
826 mono_regstate_free_int (rs, sel);
827 /* we need to create a spill var and insert a load to sel after the current instruction */
828 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
830 load->inst_basereg = cfg->frame_reg;
831 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
832 insert_after_ins (bb, ins, last, load);
833 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
834 if (G_UNLIKELY (bank))
835 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
837 i = mono_regstate_alloc_int (rs, regmask (sel));
840 if (G_UNLIKELY (bank))
841 mono_regstate_free_general (rs, sel, bank);
843 mono_regstate_free_int (rs, sel);
846 /* This isn't defined on older glib versions and on some platforms */
847 #ifndef G_GUINT64_FORMAT
848 #define G_GUINT64_FORMAT "ul"
852 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
855 int i, sel, spill, num_sregs;
856 int sregs [MONO_MAX_SRC_REGS];
857 MonoRegState *rs = cfg->rs;
859 g_assert (bank < MONO_NUM_REGBANKS);
861 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
862 /* exclude the registers in the current instruction */
863 num_sregs = mono_inst_get_src_registers (ins, sregs);
864 for (i = 0; i < num_sregs; ++i) {
865 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
866 if (is_soft_reg (sregs [i], bank))
867 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
869 regmask &= ~ (regmask (sregs [i]));
870 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
873 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
874 regmask &= ~ (regmask (ins->dreg));
875 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
878 DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
879 g_assert (regmask); /* need at least a register we can free */
881 /* we should track prev_use and spill the register that's farther */
882 if (G_UNLIKELY (bank)) {
883 for (i = 0; i < regbank_size [bank]; ++i) {
884 if (regmask & (regmask (i))) {
887 /* the vreg we need to load lives in another logical bank */
888 bank = translate_bank (cfg->rs, bank, sel);
890 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
895 i = rs->symbolic [bank] [sel];
896 spill = ++cfg->spill_count;
897 rs->vassign [i] = -spill - 1;
898 mono_regstate_free_general (rs, sel, bank);
901 for (i = 0; i < MONO_MAX_IREGS; ++i) {
902 if (regmask & (regmask (i))) {
904 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
909 i = rs->isymbolic [sel];
910 spill = ++cfg->spill_count;
911 rs->vassign [i] = -spill - 1;
912 mono_regstate_free_int (rs, sel);
915 /* we need to create a spill var and insert a load to sel after the current instruction */
916 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
918 load->inst_basereg = cfg->frame_reg;
919 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
920 insert_after_ins (bb, ins, last, load);
921 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
922 if (G_UNLIKELY (bank))
923 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
925 i = mono_regstate_alloc_int (rs, regmask (sel));
934 * Free up the hreg HREG by spilling the vreg allocated to it.
937 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
939 if (G_UNLIKELY (bank)) {
940 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
941 bank = translate_bank (cfg->rs, bank, hreg);
942 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
943 spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
947 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
948 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
949 spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
955 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
959 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
965 mono_bblock_insert_after_ins (bb, ins, copy);
968 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
972 static inline const char*
973 regbank_to_string (int bank)
975 if (bank == MONO_REG_INT_REF)
977 else if (bank == MONO_REG_INT_MP)
984 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
986 MonoInst *store, *def;
988 bank = get_vreg_bank (cfg, prev_reg, bank);
990 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
992 store->inst_destbasereg = cfg->frame_reg;
993 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
995 mono_bblock_insert_after_ins (bb, ins, store);
997 } else if (insert_before) {
998 insert_before_ins (bb, insert_before, store);
1000 g_assert_not_reached ();
1002 DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
1004 if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
1005 g_assert (prev_reg != -1);
1006 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
1007 def->inst_c0 = spill;
1008 def->inst_c1 = bank;
1009 mono_bblock_insert_after_ins (bb, store, def);
1013 /* flags used in reginfo->flags */
1015 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
1016 MONO_FP_NEEDS_SPILL = regmask (1),
1017 MONO_FP_NEEDS_LOAD = regmask (2)
1021 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1025 if (info && info->preferred_mask) {
1026 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1028 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1033 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1035 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1041 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1045 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1048 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1054 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1056 if (G_UNLIKELY (bank))
1057 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1059 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1063 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1065 if (G_UNLIKELY (bank)) {
1068 g_assert (reg >= regbank_size [bank]);
1069 g_assert (hreg < regbank_size [bank]);
1070 g_assert (! is_global_freg (hreg));
1072 rs->vassign [reg] = hreg;
1073 rs->symbolic [bank] [hreg] = reg;
1074 rs->free_mask [bank] &= ~ (regmask (hreg));
1076 mirrored_bank = get_mirrored_bank (bank);
1077 if (mirrored_bank == -1)
1080 /* Make sure the other logical reg bank that this bank shares
1081 * a single hard reg bank knows that this hard reg is not free.
1083 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1085 /* Mark the other logical bank that the this bank shares
1086 * a single hard reg bank with as mirrored.
1088 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1092 g_assert (reg >= MONO_MAX_IREGS);
1093 g_assert (hreg < MONO_MAX_IREGS);
1094 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1095 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1096 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1097 g_assert (! is_global_ireg (hreg));
1100 rs->vassign [reg] = hreg;
1101 rs->isymbolic [hreg] = reg;
1102 rs->ifree_mask &= ~ (regmask (hreg));
1106 static inline regmask_t
1107 get_callee_mask (const char spec)
1109 if (G_UNLIKELY (reg_bank (spec)))
1110 return regbank_callee_regs [reg_bank (spec)];
1111 return MONO_ARCH_CALLEE_REGS;
1114 static gint8 desc_to_fixed_reg [256];
1115 static gboolean desc_to_fixed_reg_inited = FALSE;
1120 * Local register allocation.
1121 * We first scan the list of instructions and we save the liveness info of
1122 * each register (when the register is first used, when it's value is set etc.).
1123 * We also reverse the list of instructions because assigning registers backwards allows
1124 * for more tricks to be used.
1127 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1129 MonoInst *ins, *prev, *last;
1131 MonoRegState *rs = cfg->rs;
1135 unsigned char spec_src1, spec_dest;
1137 #if MONO_ARCH_USE_FPSTACK
1138 gboolean has_fp = FALSE;
1143 int sregs [MONO_MAX_SRC_REGS];
1148 if (!desc_to_fixed_reg_inited) {
1149 for (i = 0; i < 256; ++i)
1150 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1151 desc_to_fixed_reg_inited = TRUE;
1153 /* Validate the cpu description against the info in mini-ops.h */
1154 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1155 for (i = OP_LOAD; i < OP_LAST; ++i) {
1158 spec = ins_get_spec (i);
1159 ispec = INS_INFO (i);
1161 if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1162 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1163 if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1164 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1165 if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1166 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1171 rs->next_vreg = bb->max_vreg;
1172 mono_regstate_assign (rs);
1174 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1175 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1176 rs->free_mask [i] = regbank_callee_regs [i];
1178 max = rs->next_vreg;
1180 if (cfg->reginfo && cfg->reginfo_len < max)
1181 cfg->reginfo = NULL;
1183 reginfo = (RegTrack *)cfg->reginfo;
1185 cfg->reginfo_len = MAX (1024, max * 2);
1186 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1187 cfg->reginfo = reginfo;
1190 g_assert (cfg->reginfo_len >= rs->next_vreg);
1192 if (cfg->verbose_level > 1) {
1193 /* print_regtrack reads the info of all variables */
1194 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1198 * For large methods, next_vreg can be very large, so g_malloc0 time can
1199 * be prohibitive. So we manually init the reginfo entries used by the
1202 for (ins = bb->code; ins; ins = ins->next) {
1203 gboolean modify = FALSE;
1205 spec = ins_get_spec (ins->opcode);
1207 if ((ins->dreg != -1) && (ins->dreg < max)) {
1208 memset (®info [ins->dreg], 0, sizeof (RegTrack));
1209 #if SIZEOF_REGISTER == 4
1210 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1212 * In the new IR, the two vregs of the regpair do not alias the
1213 * original long vreg. shift the vreg here so the rest of the
1214 * allocator doesn't have to care about it.
1217 memset (®info [ins->dreg + 1], 0, sizeof (RegTrack));
1222 num_sregs = mono_inst_get_src_registers (ins, sregs);
1223 for (j = 0; j < num_sregs; ++j) {
1224 g_assert (sregs [j] != -1);
1225 if (sregs [j] < max) {
1226 memset (®info [sregs [j]], 0, sizeof (RegTrack));
1227 #if SIZEOF_REGISTER == 4
1228 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1231 memset (®info [sregs [j] + 1], 0, sizeof (RegTrack));
1237 mono_inst_set_src_registers (ins, sregs);
1240 /*if (cfg->opt & MONO_OPT_COPYPROP)
1241 local_copy_prop (cfg, ins);*/
1244 DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1245 /* forward pass on the instructions to collect register liveness info */
1246 MONO_BB_FOR_EACH_INS (bb, ins) {
1247 spec = ins_get_spec (ins->opcode);
1248 spec_dest = spec [MONO_INST_DEST];
1250 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1251 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1254 DEBUG (mono_print_ins_index (i, ins));
1256 num_sregs = mono_inst_get_src_registers (ins, sregs);
1258 #if MONO_ARCH_USE_FPSTACK
1259 if (dreg_is_fp (spec)) {
1262 for (j = 0; j < num_sregs; ++j) {
1263 if (sreg_is_fp (j, spec))
1269 for (j = 0; j < num_sregs; ++j) {
1270 int sreg = sregs [j];
1271 int sreg_spec = spec [MONO_INST_SRC1 + j];
1273 bank = sreg_bank (j, spec);
1274 g_assert (sreg != -1);
1275 if (is_soft_reg (sreg, bank))
1276 /* This means the vreg is not local to this bb */
1277 g_assert (reginfo [sreg].born_in > 0);
1278 rs->vassign [sreg] = -1;
1279 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1280 //reginfo [ins->sreg2].last_use = i;
1281 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1282 /* The virtual register is allocated sequentially */
1283 rs->vassign [sreg + 1] = -1;
1284 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1285 //reginfo [ins->sreg2 + 1].last_use = i;
1286 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1287 reginfo [sreg + 1].born_in = i;
1293 mono_inst_set_src_registers (ins, sregs);
1298 bank = dreg_bank (spec);
1299 if (spec_dest != 'b') /* it's not just a base register */
1300 reginfo [ins->dreg].killed_in = i;
1301 g_assert (ins->dreg != -1);
1302 rs->vassign [ins->dreg] = -1;
1303 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1304 //reginfo [ins->dreg].last_use = i;
1305 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1306 reginfo [ins->dreg].born_in = i;
1308 dest_dreg = desc_to_fixed_reg [spec_dest];
1309 if (dest_dreg != -1)
1310 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1312 #ifdef MONO_ARCH_INST_FIXED_MASK
1313 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1316 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1317 /* The virtual register is allocated sequentially */
1318 rs->vassign [ins->dreg + 1] = -1;
1319 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1320 //reginfo [ins->dreg + 1].last_use = i;
1321 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1322 reginfo [ins->dreg + 1].born_in = i;
1323 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1324 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1335 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1336 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1338 int dest_dreg, clob_reg;
1339 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1340 int dreg_high, sreg1_high;
1341 regmask_t dreg_mask, mask;
1342 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1343 regmask_t dreg_fixed_mask;
1344 const unsigned char *ip;
1346 spec = ins_get_spec (ins->opcode);
1347 spec_src1 = spec [MONO_INST_SRC1];
1348 spec_dest = spec [MONO_INST_DEST];
1354 dreg_mask = get_callee_mask (spec_dest);
1355 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1356 prev_sregs [j] = -1;
1357 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1358 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1359 #ifdef MONO_ARCH_INST_FIXED_MASK
1360 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1362 sreg_fixed_masks [j] = 0;
1366 DEBUG (printf ("processing:"));
1367 DEBUG (mono_print_ins_index (i, ins));
1376 dest_dreg = desc_to_fixed_reg [spec_dest];
1377 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1378 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1380 #ifdef MONO_ARCH_INST_FIXED_MASK
1381 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1383 dreg_fixed_mask = 0;
1386 num_sregs = mono_inst_get_src_registers (ins, sregs);
1389 * TRACK FIXED SREG2, 3, ...
1391 for (j = 1; j < num_sregs; ++j) {
1392 int sreg = sregs [j];
1393 int dest_sreg = dest_sregs [j];
1395 if (dest_sreg == -1)
1403 * We need to special case this, since on x86, there are only 3
1404 * free registers, and the code below assigns one of them to
1405 * sreg, so we can run out of registers when trying to assign
1406 * dreg. Instead, we just set up the register masks, and let the
1407 * normal sreg2 assignment code handle this. It would be nice to
1408 * do this for all the fixed reg cases too, but there is too much
1412 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1413 sreg_masks [j] = regmask (dest_sreg);
1414 for (k = 0; k < num_sregs; ++k) {
1416 sreg_masks [k] &= ~ (regmask (dest_sreg));
1420 * Spill sreg1/2 if they are assigned to dest_sreg.
1422 for (k = 0; k < num_sregs; ++k) {
1423 if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1424 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1428 * We can also run out of registers while processing sreg2 if sreg3 is
1429 * assigned to another hreg, so spill sreg3 now.
1431 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1432 spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1437 if (rs->ifree_mask & (regmask (dest_sreg))) {
1438 if (is_global_ireg (sreg)) {
1440 /* Argument already in hard reg, need to copy */
1441 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1442 insert_before_ins (bb, ins, copy);
1443 for (k = 0; k < num_sregs; ++k) {
1445 sreg_masks [k] &= ~ (regmask (dest_sreg));
1448 dreg_mask &= ~ (regmask (dest_sreg));
1450 val = rs->vassign [sreg];
1452 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1453 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1454 } else if (val < -1) {
1456 g_assert_not_reached ();
1458 /* Argument already in hard reg, need to copy */
1459 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1462 insert_before_ins (bb, ins, copy);
1463 for (k = 0; k < num_sregs; ++k) {
1465 sreg_masks [k] &= ~ (regmask (dest_sreg));
1468 * Prevent the dreg from being allocated to dest_sreg
1469 * too, since it could force sreg1 to be allocated to
1470 * the same reg on x86.
1472 dreg_mask &= ~ (regmask (dest_sreg));
1476 gboolean need_spill = TRUE;
1477 gboolean need_assign = TRUE;
1480 dreg_mask &= ~ (regmask (dest_sreg));
1481 for (k = 0; k < num_sregs; ++k) {
1483 sreg_masks [k] &= ~ (regmask (dest_sreg));
1487 * First check if dreg is assigned to dest_sreg2, since we
1488 * can't spill a dreg.
1490 if (spec [MONO_INST_DEST])
1491 val = rs->vassign [ins->dreg];
1494 if (val == dest_sreg && ins->dreg != sreg) {
1496 * the destination register is already assigned to
1497 * dest_sreg2: we need to allocate another register for it
1498 * and then copy from this to dest_sreg2.
1501 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
1502 g_assert (new_dest >= 0);
1503 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1505 prev_dreg = ins->dreg;
1506 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1507 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1508 mono_regstate_free_int (rs, dest_sreg);
1512 if (is_global_ireg (sreg)) {
1513 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1514 insert_before_ins (bb, ins, copy);
1515 need_assign = FALSE;
1518 val = rs->vassign [sreg];
1519 if (val == dest_sreg) {
1520 /* sreg2 is already assigned to the correct register */
1522 } else if (val < -1) {
1523 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1524 } else if (val >= 0) {
1525 /* sreg2 already assigned to another register */
1527 * We couldn't emit a copy from val to dest_sreg2, because
1528 * val might be spilled later while processing this
1529 * instruction. So we spill sreg2 so it can be allocated to
1532 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1537 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1541 if (rs->vassign [sreg] < -1) {
1544 /* Need to emit a spill store */
1545 spill = - rs->vassign [sreg] - 1;
1546 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1548 /* force-set sreg2 */
1549 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1552 sregs [j] = dest_sreg;
1554 mono_inst_set_src_registers (ins, sregs);
1559 bank = dreg_bank (spec);
1560 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1561 prev_dreg = ins->dreg;
1564 if (spec_dest == 'b') {
1566 * The dest reg is read by the instruction, not written, so
1567 * avoid allocating sreg1/sreg2 to the same reg.
1569 if (dest_sregs [0] != -1)
1570 dreg_mask &= ~ (regmask (dest_sregs [0]));
1571 for (j = 1; j < num_sregs; ++j) {
1572 if (dest_sregs [j] != -1)
1573 dreg_mask &= ~ (regmask (dest_sregs [j]));
1576 val = rs->vassign [ins->dreg];
1577 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1578 /* DREG is already allocated to a register needed for sreg1 */
1579 spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1584 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1585 * various complex situations.
1587 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1588 guint32 dreg2, dest_dreg2;
1590 g_assert (is_soft_reg (ins->dreg, bank));
1592 if (dest_dreg != -1) {
1593 if (rs->vassign [ins->dreg] != dest_dreg)
1594 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1596 dreg2 = ins->dreg + 1;
1597 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1598 if (dest_dreg2 != -1) {
1599 if (rs->vassign [dreg2] != dest_dreg2)
1600 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1605 if (dreg_fixed_mask) {
1607 if (is_global_ireg (ins->dreg)) {
1609 * The argument is already in a hard reg, but that reg is
1610 * not usable by this instruction, so allocate a new one.
1612 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1614 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1615 mono_regstate_free_int (rs, val);
1621 dreg_mask &= dreg_fixed_mask;
1624 if (is_soft_reg (ins->dreg, bank)) {
1625 val = rs->vassign [ins->dreg];
1630 /* the register gets spilled after this inst */
1633 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
1634 assign_reg (cfg, rs, ins->dreg, val, bank);
1636 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1639 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1643 /* Handle regpairs */
1644 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1645 int reg2 = prev_dreg + 1;
1648 g_assert (prev_dreg > -1);
1649 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1650 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1653 mask &= ~regmask (X86_ECX);
1655 val = rs->vassign [reg2];
1659 /* the register gets spilled after this inst */
1662 val = mono_regstate_alloc_int (rs, mask);
1664 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1666 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1669 if (! (mask & (regmask (val)))) {
1670 val = mono_regstate_alloc_int (rs, mask);
1672 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1674 /* Reallocate hreg to the correct register */
1675 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1677 mono_regstate_free_int (rs, rs->vassign [reg2]);
1681 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1682 assign_reg (cfg, rs, reg2, val, bank);
1685 ins->backend.reg3 = val;
1687 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1688 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1689 mono_regstate_free_int (rs, val);
1693 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1695 * In theory, we could free up the hreg even if the vreg is alive,
1696 * but branches inside bblocks force us to assign the same hreg
1697 * to a vreg every time it is encountered.
1699 int dreg = rs->vassign [prev_dreg];
1700 g_assert (dreg >= 0);
1701 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1702 if (G_UNLIKELY (bank))
1703 mono_regstate_free_general (rs, dreg, bank);
1705 mono_regstate_free_int (rs, dreg);
1706 rs->vassign [prev_dreg] = -1;
1709 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1710 /* this instruction only outputs to dest_dreg, need to copy */
1711 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1712 ins->dreg = dest_dreg;
1714 if (G_UNLIKELY (bank)) {
1715 /* the register we need to free up may be used in another logical regbank
1716 * so do a translate just in case.
1718 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1719 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1720 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1723 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1724 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1728 if (spec_dest == 'b') {
1730 * The dest reg is read by the instruction, not written, so
1731 * avoid allocating sreg1/sreg2 to the same reg.
1733 for (j = 0; j < num_sregs; ++j)
1734 if (!sreg_bank (j, spec))
1735 sreg_masks [j] &= ~ (regmask (ins->dreg));
1741 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1742 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1743 free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1746 if (spec [MONO_INST_CLOB] == 'c') {
1747 int j, s, dreg, dreg2, cur_bank;
1750 clob_mask = MONO_ARCH_CALLEE_REGS;
1752 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1754 * Need to avoid spilling the dreg since the dreg is not really
1755 * clobbered by the call.
1757 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1758 dreg = rs->vassign [prev_dreg];
1762 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1763 dreg2 = rs->vassign [prev_dreg + 1];
1767 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1769 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1770 if ((j != dreg) && (j != dreg2))
1771 free_up_hreg (cfg, bb, tmp, ins, j, 0);
1772 else if (rs->isymbolic [j])
1773 /* The hreg is assigned to the dreg of this instruction */
1774 rs->vassign [rs->isymbolic [j]] = -1;
1775 mono_regstate_free_int (rs, j);
1780 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1781 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1782 clob_mask = regbank_callee_regs [cur_bank];
1783 if ((prev_dreg != -1) && reg_bank (spec_dest))
1784 dreg = rs->vassign [prev_dreg];
1788 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1790 /* we are looping though the banks in the outer loop
1791 * so, we don't need to deal with mirrored hregs
1792 * because we will get them in one of the other bank passes.
1794 if (is_hreg_mirrored (rs, cur_bank, j))
1798 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1800 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1801 else if (rs->symbolic [cur_bank] [j])
1802 /* The hreg is assigned to the dreg of this instruction */
1803 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1804 mono_regstate_free_general (rs, j, cur_bank);
1812 * TRACK ARGUMENT REGS
1814 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1815 MonoCallInst *call = (MonoCallInst*)ins;
1819 * This needs to be done before assigning sreg1, so sreg1 will
1820 * not be assigned one of the argument regs.
1824 * Assign all registers in call->out_reg_args to the proper
1825 * argument registers.
1828 list = call->out_ireg_args;
1834 regpair = (guint32)(gssize)(list->data);
1835 hreg = regpair >> 24;
1836 reg = regpair & 0xffffff;
1838 assign_reg (cfg, rs, reg, hreg, 0);
1840 sreg_masks [0] &= ~(regmask (hreg));
1842 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1844 list = g_slist_next (list);
1848 list = call->out_freg_args;
1854 regpair = (guint32)(gssize)(list->data);
1855 hreg = regpair >> 24;
1856 reg = regpair & 0xffffff;
1858 assign_reg (cfg, rs, reg, hreg, 1);
1860 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1862 list = g_slist_next (list);
1870 bank = sreg1_bank (spec);
1871 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1872 int sreg1 = sregs [0];
1873 int dest_sreg1 = dest_sregs [0];
1875 g_assert (is_soft_reg (sreg1, bank));
1877 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1878 if (dest_sreg1 != -1)
1879 g_assert (dest_sreg1 == ins->dreg);
1880 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1881 g_assert (val >= 0);
1883 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1885 g_assert_not_reached ();
1887 assign_reg (cfg, rs, sreg1, val, bank);
1889 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1891 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1892 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1893 g_assert (val >= 0);
1895 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1897 g_assert_not_reached ();
1899 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1901 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1903 /* Skip rest of this section */
1904 dest_sregs [0] = -1;
1907 if (sreg_fixed_masks [0]) {
1909 if (is_global_ireg (sregs [0])) {
1911 * The argument is already in a hard reg, but that reg is
1912 * not usable by this instruction, so allocate a new one.
1914 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1916 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1917 mono_regstate_free_int (rs, val);
1918 dest_sregs [0] = val;
1920 /* Fall through to the dest_sreg1 != -1 case */
1923 sreg_masks [0] &= sreg_fixed_masks [0];
1926 if (dest_sregs [0] != -1) {
1927 sreg_masks [0] = regmask (dest_sregs [0]);
1929 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1930 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1932 if (is_global_ireg (sregs [0])) {
1933 /* The argument is already in a hard reg, need to copy */
1934 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1935 insert_before_ins (bb, ins, copy);
1936 sregs [0] = dest_sregs [0];
1940 if (is_soft_reg (sregs [0], bank)) {
1941 val = rs->vassign [sregs [0]];
1942 prev_sregs [0] = sregs [0];
1946 /* the register gets spilled after this inst */
1950 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1952 * Allocate the same hreg to sreg1 as well so the
1953 * peephole can get rid of the move.
1955 sreg_masks [0] = regmask (ins->dreg);
1958 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1959 /* Allocate the same reg to sreg1 to avoid a copy later */
1960 sreg_masks [0] = regmask (ins->dreg);
1962 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], ®info [sregs [0]], bank);
1963 assign_reg (cfg, rs, sregs [0], val, bank);
1964 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1968 * Need to insert before the instruction since it can
1971 create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1974 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1975 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1976 insert_before_ins (bb, ins, copy);
1977 for (j = 1; j < num_sregs; ++j)
1978 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1979 val = dest_sregs [0];
1985 prev_sregs [0] = -1;
1987 mono_inst_set_src_registers (ins, sregs);
1989 for (j = 1; j < num_sregs; ++j)
1990 sreg_masks [j] &= ~(regmask (sregs [0]));
1992 /* Handle the case when sreg1 is a regpair but dreg is not */
1993 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1994 int reg2 = prev_sregs [0] + 1;
1997 g_assert (prev_sregs [0] > -1);
1998 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1999 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2000 val = rs->vassign [reg2];
2004 /* the register gets spilled after this inst */
2007 val = mono_regstate_alloc_int (rs, mask);
2009 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2011 g_assert_not_reached ();
2014 if (! (mask & (regmask (val)))) {
2015 /* The vreg is already allocated to a wrong hreg */
2017 g_assert_not_reached ();
2019 val = mono_regstate_alloc_int (rs, mask);
2021 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2023 /* Reallocate hreg to the correct register */
2024 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2026 mono_regstate_free_int (rs, rs->vassign [reg2]);
2032 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2033 assign_reg (cfg, rs, reg2, val, bank);
2036 /* Handle dreg==sreg1 */
2037 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2038 MonoInst *sreg2_copy = NULL;
2040 int bank = reg_bank (spec_src1);
2042 if (ins->dreg == sregs [1]) {
2044 * copying sreg1 to dreg could clobber sreg2, so allocate a new
2047 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2049 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2050 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2051 prev_sregs [1] = sregs [1] = reg2;
2053 if (G_UNLIKELY (bank))
2054 mono_regstate_free_general (rs, reg2, bank);
2056 mono_regstate_free_int (rs, reg2);
2059 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2060 /* Copying sreg1_high to dreg could also clobber sreg2 */
2061 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2063 g_assert_not_reached ();
2066 * sreg1 and dest are already allocated to the same regpair by the
2067 * SREG1 allocation code.
2069 g_assert (sregs [0] == ins->dreg);
2070 g_assert (dreg_high == sreg1_high);
2073 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2074 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2075 insert_before_ins (bb, ins, copy);
2078 insert_before_ins (bb, copy, sreg2_copy);
2081 * Need to prevent sreg2 to be allocated to sreg1, since that
2082 * would screw up the previous copy.
2084 sreg_masks [1] &= ~ (regmask (sregs [0]));
2085 /* we set sreg1 to dest as well */
2086 prev_sregs [0] = sregs [0] = ins->dreg;
2087 sreg_masks [1] &= ~ (regmask (ins->dreg));
2089 mono_inst_set_src_registers (ins, sregs);
2092 * TRACK SREG2, 3, ...
2094 for (j = 1; j < num_sregs; ++j) {
2097 bank = sreg_bank (j, spec);
2098 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2099 g_assert_not_reached ();
2101 if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2103 * Argument already in a global hard reg, copy it to the fixed reg, without
2104 * allocating it to the fixed reg.
2106 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2107 insert_before_ins (bb, ins, copy);
2108 sregs [j] = dest_sregs [j];
2109 } else if (is_soft_reg (sregs [j], bank)) {
2110 val = rs->vassign [sregs [j]];
2112 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2114 * The sreg is already allocated to a hreg, but not to the fixed
2115 * reg required by the instruction. Spill the sreg, so it can be
2116 * allocated to the fixed reg by the code below.
2118 /* Currently, this code should only be hit for CAS */
2119 spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2120 val = rs->vassign [sregs [j]];
2126 /* the register gets spilled after this inst */
2129 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], ®info [sregs [j]], bank);
2130 assign_reg (cfg, rs, sregs [j], val, bank);
2131 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2134 * Need to insert before the instruction since it can
2137 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2141 for (k = j + 1; k < num_sregs; ++k)
2142 sreg_masks [k] &= ~ (regmask (sregs [j]));
2145 prev_sregs [j] = -1;
2148 mono_inst_set_src_registers (ins, sregs);
2151 /* Do this only for CAS for now */
2152 for (j = 1; j < num_sregs; ++j) {
2153 int sreg = sregs [j];
2154 int dest_sreg = dest_sregs [j];
2156 if (j == 2 && dest_sreg != -1) {
2159 g_assert (sreg == dest_sreg);
2161 for (k = 0; k < num_sregs; ++k) {
2163 g_assert (sregs [k] != dest_sreg);
2168 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2169 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2170 mono_regstate_free_int (rs, ins->sreg1);
2172 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2173 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2174 mono_regstate_free_int (rs, ins->sreg2);
2177 DEBUG (mono_print_ins_index (i, ins));
2180 // FIXME: Set MAX_FREGS to 8
2181 // FIXME: Optimize generated code
2182 #if MONO_ARCH_USE_FPSTACK
2184 * Make a forward pass over the code, simulating the fp stack, making sure the
2185 * arguments required by the fp opcodes are at the top of the stack.
2188 MonoInst *prev = NULL;
2192 g_assert (num_sregs <= 2);
2194 for (ins = bb->code; ins; ins = ins->next) {
2195 spec = ins_get_spec (ins->opcode);
2197 DEBUG (printf ("processing:"));
2198 DEBUG (mono_print_ins_index (0, ins));
2200 if (ins->opcode == OP_FMOVE) {
2201 /* Do it by renaming the source to the destination on the stack */
2202 // FIXME: Is this correct ?
2203 for (i = 0; i < sp; ++i)
2204 if (fpstack [i] == ins->sreg1)
2205 fpstack [i] = ins->dreg;
2210 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2211 /* Arg1 must be in %st(1) */
2215 while ((i < sp) && (fpstack [i] != ins->sreg1))
2219 if (sp - 1 - i > 0) {
2220 /* First move it to %st(0) */
2221 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2223 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2224 fxch->inst_imm = sp - 1 - i;
2226 mono_bblock_insert_after_ins (bb, prev, fxch);
2229 tmp = fpstack [sp - 1];
2230 fpstack [sp - 1] = fpstack [i];
2234 /* Then move it to %st(1) */
2235 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2237 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2240 mono_bblock_insert_after_ins (bb, prev, fxch);
2243 tmp = fpstack [sp - 1];
2244 fpstack [sp - 1] = fpstack [sp - 2];
2245 fpstack [sp - 2] = tmp;
2248 if (sreg2_is_fp (spec)) {
2251 if (fpstack [sp - 1] != ins->sreg2) {
2255 while ((i < sp) && (fpstack [i] != ins->sreg2))
2259 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2261 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2262 fxch->inst_imm = sp - 1 - i;
2264 mono_bblock_insert_after_ins (bb, prev, fxch);
2267 tmp = fpstack [sp - 1];
2268 fpstack [sp - 1] = fpstack [i];
2275 if (sreg1_is_fp (spec)) {
2278 if (fpstack [sp - 1] != ins->sreg1) {
2282 while ((i < sp) && (fpstack [i] != ins->sreg1))
2286 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2288 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2289 fxch->inst_imm = sp - 1 - i;
2291 mono_bblock_insert_after_ins (bb, prev, fxch);
2294 tmp = fpstack [sp - 1];
2295 fpstack [sp - 1] = fpstack [i];
2302 if (dreg_is_fp (spec)) {
2304 fpstack [sp ++] = ins->dreg;
2307 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2309 for (i = 0; i < sp; ++i)
2310 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2317 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2318 /* Remove remaining items from the fp stack */
2320 * These can remain for example as a result of a dead fmove like in
2321 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2324 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2325 mono_add_ins_to_end (bb, ins);
2334 mono_opcode_to_cond (int opcode)
2346 case OP_COND_EXC_EQ:
2347 case OP_COND_EXC_IEQ:
2356 case OP_COND_EXC_NE_UN:
2357 case OP_COND_EXC_INE_UN:
2358 case OP_CMOV_INE_UN:
2359 case OP_CMOV_LNE_UN:
2386 case OP_COND_EXC_LT:
2387 case OP_COND_EXC_ILT:
2400 case OP_COND_EXC_GT:
2401 case OP_COND_EXC_IGT:
2410 case OP_COND_EXC_LE_UN:
2411 case OP_COND_EXC_ILE_UN:
2412 case OP_CMOV_ILE_UN:
2413 case OP_CMOV_LLE_UN:
2420 case OP_CMOV_IGE_UN:
2421 case OP_CMOV_LGE_UN:
2432 case OP_COND_EXC_LT_UN:
2433 case OP_COND_EXC_ILT_UN:
2434 case OP_CMOV_ILT_UN:
2435 case OP_CMOV_LLT_UN:
2446 case OP_COND_EXC_GT_UN:
2447 case OP_COND_EXC_IGT_UN:
2448 case OP_CMOV_IGT_UN:
2449 case OP_CMOV_LGT_UN:
2452 printf ("%s\n", mono_inst_name (opcode));
2453 g_assert_not_reached ();
2454 return (CompRelation)0;
2459 mono_negate_cond (CompRelation cond)
2483 g_assert_not_reached ();
2488 mono_opcode_to_type (int opcode, int cmp_opcode)
2490 if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2492 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2494 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2496 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2498 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2500 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2502 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2504 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2506 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2507 switch (cmp_opcode) {
2509 case OP_ICOMPARE_IMM:
2515 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2520 #endif /* DISABLE_JIT */
2523 mono_is_regsize_var (MonoType *t)
2525 t = mini_get_underlying_type (t);
2536 case MONO_TYPE_FNPTR:
2537 #if SIZEOF_REGISTER == 8
2542 case MONO_TYPE_OBJECT:
2543 case MONO_TYPE_STRING:
2544 case MONO_TYPE_CLASS:
2545 case MONO_TYPE_SZARRAY:
2546 case MONO_TYPE_ARRAY:
2548 case MONO_TYPE_GENERICINST:
2549 if (!mono_type_generic_inst_is_valuetype (t))
2552 case MONO_TYPE_VALUETYPE:
2562 * mono_peephole_ins:
2564 * Perform some architecture independent peephole optimizations.
2567 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2569 int filter = FILTER_IL_SEQ_POINT;
2570 MonoInst *last_ins = mono_inst_prev (ins, filter);
2572 switch (ins->opcode) {
2574 /* remove unnecessary multiplication with 1 */
2575 if (ins->inst_imm == 1) {
2576 if (ins->dreg != ins->sreg1)
2577 ins->opcode = OP_MOVE;
2579 MONO_DELETE_INS (bb, ins);
2582 case OP_LOAD_MEMBASE:
2583 case OP_LOADI4_MEMBASE:
2585 * Note: if reg1 = reg2 the load op is removed
2587 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2588 * OP_LOAD_MEMBASE offset(basereg), reg2
2590 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2591 * OP_MOVE reg1, reg2
2593 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2594 last_ins = mono_inst_prev (ins, filter);
2596 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2597 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2598 ins->inst_basereg == last_ins->inst_destbasereg &&
2599 ins->inst_offset == last_ins->inst_offset) {
2600 if (ins->dreg == last_ins->sreg1) {
2601 MONO_DELETE_INS (bb, ins);
2604 ins->opcode = OP_MOVE;
2605 ins->sreg1 = last_ins->sreg1;
2609 * Note: reg1 must be different from the basereg in the second load
2610 * Note: if reg1 = reg2 is equal then second load is removed
2612 * OP_LOAD_MEMBASE offset(basereg), reg1
2613 * OP_LOAD_MEMBASE offset(basereg), reg2
2615 * OP_LOAD_MEMBASE offset(basereg), reg1
2616 * OP_MOVE reg1, reg2
2618 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2619 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2620 ins->inst_basereg != last_ins->dreg &&
2621 ins->inst_basereg == last_ins->inst_basereg &&
2622 ins->inst_offset == last_ins->inst_offset) {
2624 if (ins->dreg == last_ins->dreg) {
2625 MONO_DELETE_INS (bb, ins);
2627 ins->opcode = OP_MOVE;
2628 ins->sreg1 = last_ins->dreg;
2631 //g_assert_not_reached ();
2635 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2636 * OP_LOAD_MEMBASE offset(basereg), reg
2638 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2639 * OP_ICONST reg, imm
2641 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2642 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2643 ins->inst_basereg == last_ins->inst_destbasereg &&
2644 ins->inst_offset == last_ins->inst_offset) {
2645 ins->opcode = OP_ICONST;
2646 ins->inst_c0 = last_ins->inst_imm;
2647 g_assert_not_reached (); // check this rule
2651 case OP_LOADI1_MEMBASE:
2652 case OP_LOADU1_MEMBASE:
2654 * Note: if reg1 = reg2 the load op is removed
2656 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2657 * OP_LOAD_MEMBASE offset(basereg), reg2
2659 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2660 * OP_MOVE reg1, reg2
2662 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2663 ins->inst_basereg == last_ins->inst_destbasereg &&
2664 ins->inst_offset == last_ins->inst_offset) {
2665 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2666 ins->sreg1 = last_ins->sreg1;
2669 case OP_LOADI2_MEMBASE:
2670 case OP_LOADU2_MEMBASE:
2672 * Note: if reg1 = reg2 the load op is removed
2674 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2675 * OP_LOAD_MEMBASE offset(basereg), reg2
2677 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2678 * OP_MOVE reg1, reg2
2680 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2681 ins->inst_basereg == last_ins->inst_destbasereg &&
2682 ins->inst_offset == last_ins->inst_offset) {
2683 #if SIZEOF_REGISTER == 8
2684 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2686 /* The definition of OP_PCONV_TO_U2 is wrong */
2687 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2689 ins->sreg1 = last_ins->sreg1;
2699 if (ins->dreg == ins->sreg1) {
2700 MONO_DELETE_INS (bb, ins);
2706 * OP_MOVE sreg, dreg
2707 * OP_MOVE dreg, sreg
2709 if (last_ins && last_ins->opcode == ins->opcode &&
2710 ins->sreg1 == last_ins->dreg &&
2711 ins->dreg == last_ins->sreg1) {
2712 MONO_DELETE_INS (bb, ins);
2716 MONO_DELETE_INS (bb, ins);
2722 mini_exception_id_by_name (const char *name)
2724 if (strcmp (name, "IndexOutOfRangeException") == 0)
2725 return MONO_EXC_INDEX_OUT_OF_RANGE;
2726 if (strcmp (name, "OverflowException") == 0)
2727 return MONO_EXC_OVERFLOW;
2728 if (strcmp (name, "ArithmeticException") == 0)
2729 return MONO_EXC_ARITHMETIC;
2730 if (strcmp (name, "DivideByZeroException") == 0)
2731 return MONO_EXC_DIVIDE_BY_ZERO;
2732 if (strcmp (name, "InvalidCastException") == 0)
2733 return MONO_EXC_INVALID_CAST;
2734 if (strcmp (name, "NullReferenceException") == 0)
2735 return MONO_EXC_NULL_REF;
2736 if (strcmp (name, "ArrayTypeMismatchException") == 0)
2737 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2738 if (strcmp (name, "ArgumentException") == 0)
2739 return MONO_EXC_ARGUMENT;
2740 g_error ("Unknown intrinsic exception %s\n", name);
2745 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2749 MonoClassField *field;
2750 MonoType *ftype, *prev_ftype = NULL;
2753 klass = mono_class_from_mono_type (t);
2755 while ((field = mono_class_get_fields (klass, &iter))) {
2756 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2758 ftype = mono_field_get_type (field);
2759 ftype = mini_native_type_replace_type (ftype);
2761 if (MONO_TYPE_ISSTRUCT (ftype)) {
2762 int nested_nfields, nested_esize;
2764 if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2766 if (nested_esize == 4)
2767 ftype = &mono_defaults.single_class->byval_arg;
2769 ftype = &mono_defaults.double_class->byval_arg;
2770 if (prev_ftype && prev_ftype->type != ftype->type)
2773 nfields += nested_nfields;
2775 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2777 if (prev_ftype && prev_ftype->type != ftype->type)
2785 *out_nfields = nfields;
2786 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2791 mono_regstate_new (void)
2793 MonoRegState* rs = g_new0 (MonoRegState, 1);
2795 rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2796 #ifdef MONO_ARCH_NEED_SIMD_BANK
2797 rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2804 mono_regstate_free (MonoRegState *rs) {
2805 g_free (rs->vassign);
2809 #endif /* DISABLE_JIT */