mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 /*
 275  * mono_call_inst_add_outarg_vt:
 276  *
 277  *   Register OUTARG_VT as belonging to CALL.
 278  */
 279 void
 280 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 281 {
 282         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 283 }
 284
 285 static void
 286 resize_spill_info (MonoCompile *cfg, int bank)
 287 {
 288         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 289         int orig_len = cfg->spill_info_len [bank];
 290         int new_len = orig_len ? orig_len * 2 : 16;
 291         MonoSpillInfo *new_info;
 292         int i;
 293
 294         g_assert (bank < MONO_NUM_REGBANKS);
 295
 296         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 297         if (orig_info)
 298                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 299         for (i = orig_len; i < new_len; ++i)
 300                 new_info [i].offset = -1;
 301
 302         cfg->spill_info [bank] = new_info;
 303         cfg->spill_info_len [bank] = new_len;
 304 }
 305
 306 /*
 307  * returns the offset used by spillvar. It allocates a new
 308  * spill variable if necessary.
 309  */
 310 static inline int
 311 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 312 {
 313         MonoSpillInfo *info;
 314         int size;
 315
 316         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 317                 while (spillvar >= cfg->spill_info_len [bank])
 318                         resize_spill_info (cfg, bank);
 319         }
 320
 321         /*
 322          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 323          */
 324         info = &cfg->spill_info [bank][spillvar];
 325         if (info->offset == -1) {
 326                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 327                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 328
 329                 g_assert (bank < MONO_NUM_REGBANKS);
 330                 if (G_UNLIKELY (bank))
 331                         size = regbank_spill_var_size [bank];
 332                 else
 333                         size = sizeof (mgreg_t);
 334
 335                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 336                         cfg->stack_offset += size - 1;
 337                         cfg->stack_offset &= ~(size - 1);
 338                         info->offset = cfg->stack_offset;
 339                         cfg->stack_offset += size;
 340                 } else {
 341                         cfg->stack_offset += size - 1;
 342                         cfg->stack_offset &= ~(size - 1);
 343                         cfg->stack_offset += size;
 344                         info->offset = - cfg->stack_offset;
 345                 }
 346         }
 347
 348         return info->offset;
 349 }
 350
 351 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 352 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 353 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 354 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 355 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 356 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 357
 358 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 359 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 360 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 361 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 362 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 363
 364 #ifndef MONO_ARCH_INST_IS_FLOAT
 365 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 366 #endif
 367
 368 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 369 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 370 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 371 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 372 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 373
 374 #define reg_is_simd(desc) ((desc) == 'x')
 375
 376 #ifdef MONO_ARCH_NEED_SIMD_BANK
 377
 378 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 379
 380 #else
 381
 382 #define reg_bank(desc) reg_is_fp ((desc))
 383
 384 #endif
 385
 386 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 387 #define sreg1_bank(spec) sreg_bank (0, (spec))
 388 #define sreg2_bank(spec) sreg_bank (1, (spec))
 389 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 390
 391 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 392 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 393 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 394 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 395
 396 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 397
 398 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 399 #undef is_global_ireg
 400 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 401 #endif
 402
 403 typedef struct {
 404         int born_in;
 405         int killed_in;
 406         /* Not (yet) used */
 407         //int last_use;
 408         //int prev_use;
 409         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 410 } RegTrack;
 411
 412 #ifndef DISABLE_LOGGING
 413
 414 static const char* const patch_info_str[] = {
 415 #define PATCH_INFO(a,b) "" #a,
 416 #include "patch-info.h"
 417 #undef PATCH_INFO
 418 };
 419
 420 void
 421 mono_print_ji (const MonoJumpInfo *ji)
 422 {
 423         switch (ji->type) {
 424         case MONO_PATCH_INFO_RGCTX_FETCH: {
 425                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 426
 427                 printf ("[RGCTX_FETCH ");
 428                 mono_print_ji (entry->data);
 429                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 430                 break;
 431         }
 432         case MONO_PATCH_INFO_METHODCONST: {
 433                 char *s = mono_method_full_name (ji->data.method, TRUE);
 434                 printf ("[METHODCONST - %s]", s);
 435                 g_free (s);
 436                 break;
 437         }
 438         default:
 439                 printf ("[%s]", patch_info_str [ji->type]);
 440                 break;
 441         }
 442 }
 443
 444 void
 445 mono_print_ins_index (int i, MonoInst *ins)
 446 {
 447         const char *spec = ins_get_spec (ins->opcode);
 448         int num_sregs, j;
 449         int sregs [MONO_MAX_SRC_REGS];
 450
 451         if (i != -1)
 452                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 453         else
 454                 printf (" %s", mono_inst_name (ins->opcode));
 455         if (spec == MONO_ARCH_CPU_SPEC) {
 456                 /* This is a lowered opcode */
 457                 if (ins->dreg != -1)
 458                         printf (" R%d <-", ins->dreg);
 459                 if (ins->sreg1 != -1)
 460                         printf (" R%d", ins->sreg1);
 461                 if (ins->sreg2 != -1)
 462                         printf (" R%d", ins->sreg2);
 463                 if (ins->sreg3 != -1)
 464                         printf (" R%d", ins->sreg3);
 465
 466                 switch (ins->opcode) {
 467                 case OP_LBNE_UN:
 468                 case OP_LBEQ:
 469                 case OP_LBLT:
 470                 case OP_LBLT_UN:
 471                 case OP_LBGT:
 472                 case OP_LBGT_UN:
 473                 case OP_LBGE:
 474                 case OP_LBGE_UN:
 475                 case OP_LBLE:
 476                 case OP_LBLE_UN:
 477                         if (!ins->inst_false_bb)
 478                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 479                         else
 480                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 481                         break;
 482                 case OP_PHI:
 483                 case OP_VPHI:
 484                 case OP_XPHI:
 485                 case OP_FPHI: {
 486                         int i;
 487                         printf (" [%d (", (int)ins->inst_c0);
 488                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 489                                 if (i)
 490                                         printf (", ");
 491                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 492                         }
 493                         printf (")]");
 494                         break;
 495                 }
 496                 case OP_LDADDR:
 497                 case OP_OUTARG_VTRETADDR:
 498                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 499                         break;
 500                 case OP_REGOFFSET:
 501                 case OP_GSHAREDVT_ARG_REGOFFSET:
 502                         printf (" + 0x%lx", (long)ins->inst_offset);
 503                         break;
 504                 default:
 505                         break;
 506                 }
 507
 508                 printf ("\n");
 509                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 510                 return;
 511         }
 512
 513         if (spec [MONO_INST_DEST]) {
 514                 int bank = dreg_bank (spec);
 515                 if (is_soft_reg (ins->dreg, bank)) {
 516                         if (spec [MONO_INST_DEST] == 'b') {
 517                                 if (ins->inst_offset == 0)
 518                                         printf (" [R%d] <-", ins->dreg);
 519                                 else
 520                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 521                         }
 522                         else
 523                                 printf (" R%d <-", ins->dreg);
 524                 } else if (spec [MONO_INST_DEST] == 'b') {
 525                         if (ins->inst_offset == 0)
 526                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 527                         else
 528                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 529                 } else
 530                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 531         }
 532         if (spec [MONO_INST_SRC1]) {
 533                 int bank = sreg1_bank (spec);
 534                 if (is_soft_reg (ins->sreg1, bank)) {
 535                         if (spec [MONO_INST_SRC1] == 'b')
 536                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 537                         else
 538                                 printf (" R%d", ins->sreg1);
 539                 } else if (spec [MONO_INST_SRC1] == 'b')
 540                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 541                 else
 542                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 543         }
 544         num_sregs = mono_inst_get_src_registers (ins, sregs);
 545         for (j = 1; j < num_sregs; ++j) {
 546                 int bank = sreg_bank (j, spec);
 547                 if (is_soft_reg (sregs [j], bank))
 548                         printf (" R%d", sregs [j]);
 549                 else
 550                         printf (" %s", mono_regname_full (sregs [j], bank));
 551         }
 552
 553         switch (ins->opcode) {
 554         case OP_ICONST:
 555                 printf (" [%d]", (int)ins->inst_c0);
 556                 break;
 557 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 558         case OP_X86_PUSH_IMM:
 559 #endif
 560         case OP_ICOMPARE_IMM:
 561         case OP_COMPARE_IMM:
 562         case OP_IADD_IMM:
 563         case OP_ISUB_IMM:
 564         case OP_IAND_IMM:
 565         case OP_IOR_IMM:
 566         case OP_IXOR_IMM:
 567         case OP_SUB_IMM:
 568                 printf (" [%d]", (int)ins->inst_imm);
 569                 break;
 570         case OP_ADD_IMM:
 571         case OP_LADD_IMM:
 572                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 573                 break;
 574         case OP_I8CONST:
 575                 printf (" [%lld]", (long long)ins->inst_l);
 576                 break;
 577         case OP_R8CONST:
 578                 printf (" [%f]", *(double*)ins->inst_p0);
 579                 break;
 580         case OP_R4CONST:
 581                 printf (" [%f]", *(float*)ins->inst_p0);
 582                 break;
 583         case OP_CALL:
 584         case OP_CALL_MEMBASE:
 585         case OP_CALL_REG:
 586         case OP_FCALL:
 587         case OP_FCALLVIRT:
 588         case OP_LCALL:
 589         case OP_LCALLVIRT:
 590         case OP_VCALL:
 591         case OP_VCALLVIRT:
 592         case OP_VCALL_REG:
 593         case OP_VCALL_MEMBASE:
 594         case OP_VCALL2:
 595         case OP_VCALL2_REG:
 596         case OP_VCALL2_MEMBASE:
 597         case OP_VOIDCALL:
 598         case OP_VOIDCALL_MEMBASE:
 599         case OP_VOIDCALLVIRT:
 600         case OP_TAILCALL: {
 601                 MonoCallInst *call = (MonoCallInst*)ins;
 602                 GSList *list;
 603
 604                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 605                         /*
 606                          * These are lowered opcodes, but they are in the .md files since the old
 607                          * JIT passes them to backends.
 608                          */
 609                         if (ins->dreg != -1)
 610                                 printf (" R%d <-", ins->dreg);
 611                 }
 612
 613                 if (call->method) {
 614                         char *full_name = mono_method_full_name (call->method, TRUE);
 615                         printf (" [%s]", full_name);
 616                         g_free (full_name);
 617                 } else if (call->fptr_is_patch) {
 618                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 619
 620                         printf (" ");
 621                         mono_print_ji (ji);
 622                 } else if (call->fptr) {
 623                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 624                         if (info)
 625                                 printf (" [%s]", info->name);
 626                 }
 627
 628                 list = call->out_ireg_args;
 629                 while (list) {
 630                         guint32 regpair;
 631                         int reg, hreg;
 632
 633                         regpair = (guint32)(gssize)(list->data);
 634                         hreg = regpair >> 24;
 635                         reg = regpair & 0xffffff;
 636
 637                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 638
 639                         list = g_slist_next (list);
 640                 }
 641                 break;
 642         }
 643         case OP_BR:
 644         case OP_CALL_HANDLER:
 645                 printf (" [B%d]", ins->inst_target_bb->block_num);
 646                 break;
 647         case OP_IBNE_UN:
 648         case OP_IBEQ:
 649         case OP_IBLT:
 650         case OP_IBLT_UN:
 651         case OP_IBGT:
 652         case OP_IBGT_UN:
 653         case OP_IBGE:
 654         case OP_IBGE_UN:
 655         case OP_IBLE:
 656         case OP_IBLE_UN:
 657         case OP_LBNE_UN:
 658         case OP_LBEQ:
 659         case OP_LBLT:
 660         case OP_LBLT_UN:
 661         case OP_LBGT:
 662         case OP_LBGT_UN:
 663         case OP_LBGE:
 664         case OP_LBGE_UN:
 665         case OP_LBLE:
 666         case OP_LBLE_UN:
 667                 if (!ins->inst_false_bb)
 668                         printf (" [B%d]", ins->inst_true_bb->block_num);
 669                 else
 670                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 671                 break;
 672         case OP_LIVERANGE_START:
 673         case OP_LIVERANGE_END:
 674         case OP_GC_LIVENESS_DEF:
 675         case OP_GC_LIVENESS_USE:
 676                 printf (" R%d", (int)ins->inst_c1);
 677                 break;
 678         case OP_SEQ_POINT:
 679                 printf (" il: %x", (int)ins->inst_imm);
 680                 break;
 681         default:
 682                 break;
 683         }
 684
 685         if (spec [MONO_INST_CLOB])
 686                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 687         printf ("\n");
 688 }
 689
 690 static void
 691 print_regtrack (RegTrack *t, int num)
 692 {
 693         int i;
 694         char buf [32];
 695         const char *r;
 696
 697         for (i = 0; i < num; ++i) {
 698                 if (!t [i].born_in)
 699                         continue;
 700                 if (i >= MONO_MAX_IREGS) {
 701                         g_snprintf (buf, sizeof(buf), "R%d", i);
 702                         r = buf;
 703                 } else
 704                         r = mono_arch_regname (i);
 705                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 706         }
 707 }
 708 #else
 709
 710 void
 711 mono_print_ji (const MonoJumpInfo *ji)
 712 {
 713 }
 714
 715 void
 716 mono_print_ins_index (int i, MonoInst *ins)
 717 {
 718 }
 719 #endif /* DISABLE_LOGGING */
 720
 721 void
 722 mono_print_ins (MonoInst *ins)
 723 {
 724         mono_print_ins_index (-1, ins);
 725 }
 726
 727 static inline void
 728 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 729 {
 730         /*
 731          * If this function is called multiple times, the new instructions are inserted
 732          * in the proper order.
 733          */
 734         mono_bblock_insert_before_ins (bb, ins, to_insert);
 735 }
 736
 737 static inline void
 738 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 739 {
 740         /*
 741          * If this function is called multiple times, the new instructions are inserted in
 742          * proper order.
 743          */
 744         mono_bblock_insert_after_ins (bb, *last, to_insert);
 745
 746         *last = to_insert;
 747 }
 748
 749 static inline int
 750 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 751 {
 752         if (vreg_is_ref (cfg, reg))
 753                 return MONO_REG_INT_REF;
 754         else if (vreg_is_mp (cfg, reg))
 755                 return MONO_REG_INT_MP;
 756         else
 757                 return bank;
 758 }
 759
 760 /*
 761  * Force the spilling of the variable in the symbolic register 'reg', and free
 762  * the hreg it was assigned to.
 763  */
 764 static void
 765 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 766 {
 767         MonoInst *load;
 768         int i, sel, spill;
 769         int *symbolic;
 770         MonoRegState *rs = cfg->rs;
 771
 772         symbolic = rs->symbolic [bank];
 773         sel = rs->vassign [reg];
 774
 775         /* the vreg we need to spill lives in another logical reg bank */
 776         bank = translate_bank (cfg->rs, bank, sel);
 777
 778         /*i = rs->isymbolic [sel];
 779         g_assert (i == reg);*/
 780         i = reg;
 781         spill = ++cfg->spill_count;
 782         rs->vassign [i] = -spill - 1;
 783         if (G_UNLIKELY (bank))
 784                 mono_regstate_free_general (rs, sel, bank);
 785         else
 786                 mono_regstate_free_int (rs, sel);
 787         /* we need to create a spill var and insert a load to sel after the current instruction */
 788         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 789         load->dreg = sel;
 790         load->inst_basereg = cfg->frame_reg;
 791         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 792         insert_after_ins (bb, ins, last, load);
 793         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 794         if (G_UNLIKELY (bank))
 795                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 796         else
 797                 i = mono_regstate_alloc_int (rs, regmask (sel));
 798         g_assert (i == sel);
 799
 800         if (G_UNLIKELY (bank))
 801                 mono_regstate_free_general (rs, sel, bank);
 802         else
 803                 mono_regstate_free_int (rs, sel);
 804 }
 805
 806 /* This isn't defined on older glib versions and on some platforms */
 807 #ifndef G_GUINT64_FORMAT
 808 #define G_GUINT64_FORMAT "ul"
 809 #endif
 810
 811 static int
 812 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 813 {
 814         MonoInst *load;
 815         int i, sel, spill, num_sregs;
 816         int sregs [MONO_MAX_SRC_REGS];
 817         int *symbolic;
 818         MonoRegState *rs = cfg->rs;
 819
 820         symbolic = rs->symbolic [bank];
 821
 822         g_assert (bank < MONO_NUM_REGBANKS);
 823
 824         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 825         /* exclude the registers in the current instruction */
 826         num_sregs = mono_inst_get_src_registers (ins, sregs);
 827         for (i = 0; i < num_sregs; ++i) {
 828                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 829                         if (is_soft_reg (sregs [i], bank))
 830                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 831                         else
 832                                 regmask &= ~ (regmask (sregs [i]));
 833                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 834                 }
 835         }
 836         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 837                 regmask &= ~ (regmask (ins->dreg));
 838                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 839         }
 840
 841         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 842         g_assert (regmask); /* need at least a register we can free */
 843         sel = 0;
 844         /* we should track prev_use and spill the register that's farther */
 845         if (G_UNLIKELY (bank)) {
 846                 for (i = 0; i < regbank_size [bank]; ++i) {
 847                         if (regmask & (regmask (i))) {
 848                                 sel = i;
 849
 850                                 /* the vreg we need to load lives in another logical bank */
 851                                 bank = translate_bank (cfg->rs, bank, sel);
 852
 853                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 854                                 break;
 855                         }
 856                 }
 857
 858                 i = rs->symbolic [bank] [sel];
 859                 spill = ++cfg->spill_count;
 860                 rs->vassign [i] = -spill - 1;
 861                 mono_regstate_free_general (rs, sel, bank);
 862         }
 863         else {
 864                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 865                         if (regmask & (regmask (i))) {
 866                                 sel = i;
 867                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 868                                 break;
 869                         }
 870                 }
 871
 872                 i = rs->isymbolic [sel];
 873                 spill = ++cfg->spill_count;
 874                 rs->vassign [i] = -spill - 1;
 875                 mono_regstate_free_int (rs, sel);
 876         }
 877
 878         /* we need to create a spill var and insert a load to sel after the current instruction */
 879         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 880         load->dreg = sel;
 881         load->inst_basereg = cfg->frame_reg;
 882         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 883         insert_after_ins (bb, ins, last, load);
 884         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 885         if (G_UNLIKELY (bank))
 886                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 887         else
 888                 i = mono_regstate_alloc_int (rs, regmask (sel));
 889         g_assert (i == sel);
 890
 891         return sel;
 892 }
 893
 894 /*
 895  * free_up_hreg:
 896  *
 897  *   Free up the hreg HREG by spilling the vreg allocated to it.
 898  */
 899 static void
 900 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 901 {
 902         if (G_UNLIKELY (bank)) {
 903                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 904                         bank = translate_bank (cfg->rs, bank, hreg);
 905                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 906                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 907                 }
 908         }
 909         else {
 910                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 911                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 912                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 913                 }
 914         }
 915 }
 916
 917 static MonoInst*
 918 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 919 {
 920         MonoInst *copy;
 921
 922         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 923
 924         copy->dreg = dest;
 925         copy->sreg1 = src;
 926         copy->cil_code = ip;
 927         if (ins) {
 928                 mono_bblock_insert_after_ins (bb, ins, copy);
 929                 *last = copy;
 930         }
 931         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 932         return copy;
 933 }
 934
 935 static inline const char*
 936 regbank_to_string (int bank)
 937 {
 938         if (bank == MONO_REG_INT_REF)
 939                 return "REF ";
 940         else if (bank == MONO_REG_INT_MP)
 941                 return "MP ";
 942         else
 943                 return "";
 944 }
 945
 946 static void
 947 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 948 {
 949         MonoInst *store, *def;
 950
 951         bank = get_vreg_bank (cfg, prev_reg, bank);
 952
 953         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 954         store->sreg1 = reg;
 955         store->inst_destbasereg = cfg->frame_reg;
 956         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 957         if (ins) {
 958                 mono_bblock_insert_after_ins (bb, ins, store);
 959                 *last = store;
 960         } else if (insert_before) {
 961                 insert_before_ins (bb, insert_before, store);
 962         } else {
 963                 g_assert_not_reached ();
 964         }
 965         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 966
 967         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 968                 g_assert (prev_reg != -1);
 969                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 970                 def->inst_c0 = spill;
 971                 def->inst_c1 = bank;
 972                 mono_bblock_insert_after_ins (bb, store, def);
 973         }
 974 }
 975
 976 /* flags used in reginfo->flags */
 977 enum {
 978         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 979         MONO_FP_NEEDS_SPILL                     = regmask (1),
 980         MONO_FP_NEEDS_LOAD                      = regmask (2)
 981 };
 982
 983 static inline int
 984 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 985 {
 986         int val;
 987
 988         if (info && info->preferred_mask) {
 989                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 990                 if (val >= 0) {
 991                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 992                         return val;
 993                 }
 994         }
 995
 996         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 997         if (val < 0)
 998                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 999
1000         return val;
1001 }
1002
1003 static inline int
1004 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1005 {
1006         int val;
1007
1008         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1009
1010         if (val < 0)
1011                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1012
1013         return val;
1014 }
1015
1016 static inline int
1017 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1018 {
1019         if (G_UNLIKELY (bank))
1020                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1021         else
1022                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1023 }
1024
1025 static inline void
1026 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1027 {
1028         if (G_UNLIKELY (bank)) {
1029                 int mirrored_bank;
1030
1031                 g_assert (reg >= regbank_size [bank]);
1032                 g_assert (hreg < regbank_size [bank]);
1033                 g_assert (! is_global_freg (hreg));
1034
1035                 rs->vassign [reg] = hreg;
1036                 rs->symbolic [bank] [hreg] = reg;
1037                 rs->free_mask [bank] &= ~ (regmask (hreg));
1038
1039                 mirrored_bank = get_mirrored_bank (bank);
1040                 if (mirrored_bank == -1)
1041                         return;
1042
1043                 /* Make sure the other logical reg bank that this bank shares
1044                  * a single hard reg bank knows that this hard reg is not free.
1045                  */
1046                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1047
1048                 /* Mark the other logical bank that the this bank shares
1049                  * a single hard reg bank with as mirrored.
1050                  */
1051                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1052
1053         }
1054         else {
1055                 g_assert (reg >= MONO_MAX_IREGS);
1056                 g_assert (hreg < MONO_MAX_IREGS);
1057 #ifndef TARGET_ARM
1058                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1059                 g_assert (! is_global_ireg (hreg));
1060 #endif
1061
1062                 rs->vassign [reg] = hreg;
1063                 rs->isymbolic [hreg] = reg;
1064                 rs->ifree_mask &= ~ (regmask (hreg));
1065         }
1066 }
1067
1068 static inline regmask_t
1069 get_callee_mask (const char spec)
1070 {
1071         if (G_UNLIKELY (reg_bank (spec)))
1072                 return regbank_callee_regs [reg_bank (spec)];
1073         return MONO_ARCH_CALLEE_REGS;
1074 }
1075
1076 static gint8 desc_to_fixed_reg [256];
1077 static gboolean desc_to_fixed_reg_inited = FALSE;
1078
1079 #ifndef DISABLE_JIT
1080
1081 /*
1082  * Local register allocation.
1083  * We first scan the list of instructions and we save the liveness info of
1084  * each register (when the register is first used, when it's value is set etc.).
1085  * We also reverse the list of instructions because assigning registers backwards allows
1086  * for more tricks to be used.
1087  */
1088 void
1089 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1090 {
1091         MonoInst *ins, *prev, *last;
1092         MonoInst **tmp;
1093         MonoRegState *rs = cfg->rs;
1094         int i, j, val, max;
1095         RegTrack *reginfo;
1096         const char *spec;
1097         unsigned char spec_src1, spec_dest;
1098         int bank = 0;
1099 #if MONO_ARCH_USE_FPSTACK
1100         gboolean has_fp = FALSE;
1101         int fpstack [8];
1102         int sp = 0;
1103 #endif
1104         int num_sregs = 0;
1105         int sregs [MONO_MAX_SRC_REGS];
1106
1107         if (!bb->code)
1108                 return;
1109
1110         if (!desc_to_fixed_reg_inited) {
1111                 for (i = 0; i < 256; ++i)
1112                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1113                 desc_to_fixed_reg_inited = TRUE;
1114
1115                 /* Validate the cpu description against the info in mini-ops.h */
1116 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1117                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1118                         const char *ispec;
1119
1120                         spec = ins_get_spec (i);
1121                         ispec = INS_INFO (i);
1122
1123                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1124                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1125                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1126                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1127                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1128                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1129                 }
1130 #endif
1131         }
1132
1133         rs->next_vreg = bb->max_vreg;
1134         mono_regstate_assign (rs);
1135
1136         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1137         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1138                 rs->free_mask [i] = regbank_callee_regs [i];
1139
1140         max = rs->next_vreg;
1141
1142         if (cfg->reginfo && cfg->reginfo_len < max)
1143                 cfg->reginfo = NULL;
1144
1145         reginfo = cfg->reginfo;
1146         if (!reginfo) {
1147                 cfg->reginfo_len = MAX (1024, max * 2);
1148                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1149         }
1150         else
1151                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1152
1153         if (cfg->verbose_level > 1) {
1154                 /* print_regtrack reads the info of all variables */
1155                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1156         }
1157
1158         /*
1159          * For large methods, next_vreg can be very large, so g_malloc0 time can
1160          * be prohibitive. So we manually init the reginfo entries used by the
1161          * bblock.
1162          */
1163         for (ins = bb->code; ins; ins = ins->next) {
1164                 spec = ins_get_spec (ins->opcode);
1165
1166                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1167                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1168 #if SIZEOF_REGISTER == 4
1169                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1170                                 /**
1171                                  * In the new IR, the two vregs of the regpair do not alias the
1172                                  * original long vreg. shift the vreg here so the rest of the
1173                                  * allocator doesn't have to care about it.
1174                                  */
1175                                 ins->dreg ++;
1176                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1177                         }
1178 #endif
1179                 }
1180
1181                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1182                 for (j = 0; j < num_sregs; ++j) {
1183                         g_assert (sregs [j] != -1);
1184                         if (sregs [j] < max) {
1185                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1186 #if SIZEOF_REGISTER == 4
1187                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1188                                         sregs [j]++;
1189                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1190                                 }
1191 #endif
1192                         }
1193                 }
1194                 mono_inst_set_src_registers (ins, sregs);
1195         }
1196
1197         /*if (cfg->opt & MONO_OPT_COPYPROP)
1198                 local_copy_prop (cfg, ins);*/
1199
1200         i = 1;
1201         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1202         /* forward pass on the instructions to collect register liveness info */
1203         MONO_BB_FOR_EACH_INS (bb, ins) {
1204                 spec = ins_get_spec (ins->opcode);
1205                 spec_dest = spec [MONO_INST_DEST];
1206
1207                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1208                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1209                 }
1210
1211                 DEBUG (mono_print_ins_index (i, ins));
1212
1213                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1214
1215 #if MONO_ARCH_USE_FPSTACK
1216                 if (dreg_is_fp (spec)) {
1217                         has_fp = TRUE;
1218                 } else {
1219                         for (j = 0; j < num_sregs; ++j) {
1220                                 if (sreg_is_fp (j, spec))
1221                                         has_fp = TRUE;
1222                         }
1223                 }
1224 #endif
1225
1226                 for (j = 0; j < num_sregs; ++j) {
1227                         int sreg = sregs [j];
1228                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1229                         if (sreg_spec) {
1230                                 bank = sreg_bank (j, spec);
1231                                 g_assert (sreg != -1);
1232                                 if (is_soft_reg (sreg, bank))
1233                                         /* This means the vreg is not local to this bb */
1234                                         g_assert (reginfo [sreg].born_in > 0);
1235                                 rs->vassign [sreg] = -1;
1236                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1237                                 //reginfo [ins->sreg2].last_use = i;
1238                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1239                                         /* The virtual register is allocated sequentially */
1240                                         rs->vassign [sreg + 1] = -1;
1241                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1242                                         //reginfo [ins->sreg2 + 1].last_use = i;
1243                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1244                                                 reginfo [sreg + 1].born_in = i;
1245                                 }
1246                         } else {
1247                                 sregs [j] = -1;
1248                         }
1249                 }
1250                 mono_inst_set_src_registers (ins, sregs);
1251
1252                 if (spec_dest) {
1253                         int dest_dreg;
1254
1255                         bank = dreg_bank (spec);
1256                         if (spec_dest != 'b') /* it's not just a base register */
1257                                 reginfo [ins->dreg].killed_in = i;
1258                         g_assert (ins->dreg != -1);
1259                         rs->vassign [ins->dreg] = -1;
1260                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1261                         //reginfo [ins->dreg].last_use = i;
1262                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1263                                 reginfo [ins->dreg].born_in = i;
1264
1265                         dest_dreg = desc_to_fixed_reg [spec_dest];
1266                         if (dest_dreg != -1)
1267                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1268
1269 #ifdef MONO_ARCH_INST_FIXED_MASK
1270                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1271 #endif
1272
1273                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1274                                 /* The virtual register is allocated sequentially */
1275                                 rs->vassign [ins->dreg + 1] = -1;
1276                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1277                                 //reginfo [ins->dreg + 1].last_use = i;
1278                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1279                                         reginfo [ins->dreg + 1].born_in = i;
1280                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1281                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1282                         }
1283                 } else {
1284                         ins->dreg = -1;
1285                 }
1286
1287                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1288                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1289
1290                         MonoCallInst *call = (MonoCallInst*)ins;
1291                         GSList *list;
1292
1293                         list = call->out_ireg_args;
1294                         if (list) {
1295                                 while (list) {
1296                                         guint32 regpair;
1297                                         int reg, hreg;
1298
1299                                         regpair = (guint32)(gssize)(list->data);
1300                                         hreg = regpair >> 24;
1301                                         reg = regpair & 0xffffff;
1302
1303                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1304                                         //reginfo [reg].last_use = i;
1305
1306                                         list = g_slist_next (list);
1307                                 }
1308                         }
1309
1310                         list = call->out_freg_args;
1311                         if (list) {
1312                                 while (list) {
1313                                         guint32 regpair;
1314                                         int reg, hreg;
1315
1316                                         regpair = (guint32)(gssize)(list->data);
1317                                         hreg = regpair >> 24;
1318                                         reg = regpair & 0xffffff;
1319
1320                                         list = g_slist_next (list);
1321                                 }
1322                         }
1323                 }
1324
1325                 ++i;
1326         }
1327
1328         tmp = &last;
1329
1330         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1331         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1332                 int prev_dreg, clob_dreg;
1333                 int dest_dreg, clob_reg;
1334                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1335                 int dreg_high, sreg1_high;
1336                 regmask_t dreg_mask, mask;
1337                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1338                 regmask_t dreg_fixed_mask;
1339                 const unsigned char *ip;
1340                 --i;
1341                 spec = ins_get_spec (ins->opcode);
1342                 spec_src1 = spec [MONO_INST_SRC1];
1343                 spec_dest = spec [MONO_INST_DEST];
1344                 prev_dreg = -1;
1345                 clob_dreg = -1;
1346                 clob_reg = -1;
1347                 dest_dreg = -1;
1348                 dreg_high = -1;
1349                 sreg1_high = -1;
1350                 dreg_mask = get_callee_mask (spec_dest);
1351                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1352                         prev_sregs [j] = -1;
1353                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1354                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1355 #ifdef MONO_ARCH_INST_FIXED_MASK
1356                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1357 #else
1358                         sreg_fixed_masks [j] = 0;
1359 #endif
1360                 }
1361
1362                 DEBUG (printf ("processing:"));
1363                 DEBUG (mono_print_ins_index (i, ins));
1364
1365                 ip = ins->cil_code;
1366
1367                 last = ins;
1368
1369                 /*
1370                  * FIXED REGS
1371                  */
1372                 dest_dreg = desc_to_fixed_reg [spec_dest];
1373                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1374                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1375
1376 #ifdef MONO_ARCH_INST_FIXED_MASK
1377                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1378 #else
1379                 dreg_fixed_mask = 0;
1380 #endif
1381
1382                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1383
1384                 /*
1385                  * TRACK FIXED SREG2, 3, ...
1386                  */
1387                 for (j = 1; j < num_sregs; ++j) {
1388                         int sreg = sregs [j];
1389                         int dest_sreg = dest_sregs [j];
1390
1391                         if (dest_sreg == -1)
1392                                 continue;
1393
1394                         if (j == 2) {
1395                                 int k;
1396
1397                                 /*
1398                                  * CAS.
1399                                  * We need to special case this, since on x86, there are only 3
1400                                  * free registers, and the code below assigns one of them to
1401                                  * sreg, so we can run out of registers when trying to assign
1402                                  * dreg. Instead, we just set up the register masks, and let the
1403                                  * normal sreg2 assignment code handle this. It would be nice to
1404                                  * do this for all the fixed reg cases too, but there is too much
1405                                  * risk of breakage.
1406                                  */
1407
1408                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1409                                 sreg_masks [j] = regmask (dest_sreg);
1410                                 for (k = 0; k < num_sregs; ++k) {
1411                                         if (k != j)
1412                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1413                                 }
1414
1415                                 /*
1416                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1417                                  */
1418                                 for (k = 0; k < num_sregs; ++k) {
1419                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1420                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1421                                 }
1422
1423                                 /*
1424                                  * We can also run out of registers while processing sreg2 if sreg3 is
1425                                  * assigned to another hreg, so spill sreg3 now.
1426                                  */
1427                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1428                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1429                                 }
1430                                 continue;
1431                         }
1432
1433                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1434                                 if (is_global_ireg (sreg)) {
1435                                         int k;
1436                                         /* Argument already in hard reg, need to copy */
1437                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1438                                         insert_before_ins (bb, ins, copy);
1439                                         for (k = 0; k < num_sregs; ++k) {
1440                                                 if (k != j)
1441                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1442                                         }
1443                                 } else {
1444                                         val = rs->vassign [sreg];
1445                                         if (val == -1) {
1446                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1447                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1448                                         } else if (val < -1) {
1449                                                 /* FIXME: */
1450                                                 g_assert_not_reached ();
1451                                         } else {
1452                                                 /* Argument already in hard reg, need to copy */
1453                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1454                                                 int k;
1455
1456                                                 insert_before_ins (bb, ins, copy);
1457                                                 for (k = 0; k < num_sregs; ++k) {
1458                                                         if (k != j)
1459                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1460                                                 }
1461                                                 /*
1462                                                  * Prevent the dreg from being allocate to dest_sreg
1463                                                  * too, since it could force sreg1 to be allocated to
1464                                                  * the same reg on x86.
1465                                                  */
1466                                                 dreg_mask &= ~ (regmask (dest_sreg));
1467                                         }
1468                                 }
1469                         } else {
1470                                 gboolean need_spill = TRUE;
1471                                 gboolean need_assign = TRUE;
1472                                 int k;
1473
1474                                 dreg_mask &= ~ (regmask (dest_sreg));
1475                                 for (k = 0; k < num_sregs; ++k) {
1476                                         if (k != j)
1477                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1478                                 }
1479
1480                                 /*
1481                                  * First check if dreg is assigned to dest_sreg2, since we
1482                                  * can't spill a dreg.
1483                                  */
1484                                 if (spec [MONO_INST_DEST])
1485                                         val = rs->vassign [ins->dreg];
1486                                 else
1487                                         val = -1;
1488                                 if (val == dest_sreg && ins->dreg != sreg) {
1489                                         /*
1490                                          * the destination register is already assigned to
1491                                          * dest_sreg2: we need to allocate another register for it
1492                                          * and then copy from this to dest_sreg2.
1493                                          */
1494                                         int new_dest;
1495                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1496                                         g_assert (new_dest >= 0);
1497                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1498
1499                                         prev_dreg = ins->dreg;
1500                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1501                                         clob_dreg = ins->dreg;
1502                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1503                                         mono_regstate_free_int (rs, dest_sreg);
1504                                         need_spill = FALSE;
1505                                 }
1506
1507                                 if (is_global_ireg (sreg)) {
1508                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1509                                         insert_before_ins (bb, ins, copy);
1510                                         need_assign = FALSE;
1511                                 }
1512                                 else {
1513                                         val = rs->vassign [sreg];
1514                                         if (val == dest_sreg) {
1515                                                 /* sreg2 is already assigned to the correct register */
1516                                                 need_spill = FALSE;
1517                                         } else if (val < -1) {
1518                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1519                                         } else if (val >= 0) {
1520                                                 /* sreg2 already assigned to another register */
1521                                                 /*
1522                                                  * We couldn't emit a copy from val to dest_sreg2, because
1523                                                  * val might be spilled later while processing this
1524                                                  * instruction. So we spill sreg2 so it can be allocated to
1525                                                  * dest_sreg2.
1526                                                  */
1527                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1528                                         }
1529                                 }
1530
1531                                 if (need_spill) {
1532                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1533                                 }
1534
1535                                 if (need_assign) {
1536                                         if (rs->vassign [sreg] < -1) {
1537                                                 int spill;
1538
1539                                                 /* Need to emit a spill store */
1540                                                 spill = - rs->vassign [sreg] - 1;
1541                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1542                                         }
1543                                         /* force-set sreg2 */
1544                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1545                                 }
1546                         }
1547                         sregs [j] = dest_sreg;
1548                 }
1549                 mono_inst_set_src_registers (ins, sregs);
1550
1551                 /*
1552                  * TRACK DREG
1553                  */
1554                 bank = dreg_bank (spec);
1555                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1556                         prev_dreg = ins->dreg;
1557                 }
1558
1559                 if (spec_dest == 'b') {
1560                         /*
1561                          * The dest reg is read by the instruction, not written, so
1562                          * avoid allocating sreg1/sreg2 to the same reg.
1563                          */
1564                         if (dest_sregs [0] != -1)
1565                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1566                         for (j = 1; j < num_sregs; ++j) {
1567                                 if (dest_sregs [j] != -1)
1568                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1569                         }
1570
1571                         val = rs->vassign [ins->dreg];
1572                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1573                                 /* DREG is already allocated to a register needed for sreg1 */
1574                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1575                         }
1576                 }
1577
1578                 /*
1579                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1580                  * various complex situations.
1581                  */
1582                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1583                         guint32 dreg2, dest_dreg2;
1584
1585                         g_assert (is_soft_reg (ins->dreg, bank));
1586
1587                         if (dest_dreg != -1) {
1588                                 if (rs->vassign [ins->dreg] != dest_dreg)
1589                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1590
1591                                 dreg2 = ins->dreg + 1;
1592                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1593                                 if (dest_dreg2 != -1) {
1594                                         if (rs->vassign [dreg2] != dest_dreg2)
1595                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1596                                 }
1597                         }
1598                 }
1599
1600                 if (dreg_fixed_mask) {
1601                         g_assert (!bank);
1602                         if (is_global_ireg (ins->dreg)) {
1603                                 /*
1604                                  * The argument is already in a hard reg, but that reg is
1605                                  * not usable by this instruction, so allocate a new one.
1606                                  */
1607                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1608                                 if (val < 0)
1609                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1610                                 mono_regstate_free_int (rs, val);
1611                                 dest_dreg = val;
1612
1613                                 /* Fall through */
1614                         }
1615                         else
1616                                 dreg_mask &= dreg_fixed_mask;
1617                 }
1618
1619                 if (is_soft_reg (ins->dreg, bank)) {
1620                         val = rs->vassign [ins->dreg];
1621
1622                         if (val < 0) {
1623                                 int spill = 0;
1624                                 if (val < -1) {
1625                                         /* the register gets spilled after this inst */
1626                                         spill = -val -1;
1627                                 }
1628                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1629                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1630                                 if (spill)
1631                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1632                         }
1633
1634                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1635                         ins->dreg = val;
1636                 }
1637
1638                 /* Handle regpairs */
1639                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1640                         int reg2 = prev_dreg + 1;
1641
1642                         g_assert (!bank);
1643                         g_assert (prev_dreg > -1);
1644                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1645                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1646 #ifdef TARGET_X86
1647                         /* bug #80489 */
1648                         mask &= ~regmask (X86_ECX);
1649 #endif
1650                         val = rs->vassign [reg2];
1651                         if (val < 0) {
1652                                 int spill = 0;
1653                                 if (val < -1) {
1654                                         /* the register gets spilled after this inst */
1655                                         spill = -val -1;
1656                                 }
1657                                 val = mono_regstate_alloc_int (rs, mask);
1658                                 if (val < 0)
1659                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1660                                 if (spill)
1661                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1662                         }
1663                         else {
1664                                 if (! (mask & (regmask (val)))) {
1665                                         val = mono_regstate_alloc_int (rs, mask);
1666                                         if (val < 0)
1667                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1668
1669                                         /* Reallocate hreg to the correct register */
1670                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1671
1672                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1673                                 }
1674                         }
1675
1676                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1677                         assign_reg (cfg, rs, reg2, val, bank);
1678
1679                         dreg_high = val;
1680                         ins->backend.reg3 = val;
1681
1682                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1683                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1684                                 mono_regstate_free_int (rs, val);
1685                         }
1686                 }
1687
1688                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1689                         /*
1690                          * In theory, we could free up the hreg even if the vreg is alive,
1691                          * but branches inside bblocks force us to assign the same hreg
1692                          * to a vreg every time it is encountered.
1693                          */
1694                         int dreg = rs->vassign [prev_dreg];
1695                         g_assert (dreg >= 0);
1696                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1697                         if (G_UNLIKELY (bank))
1698                                 mono_regstate_free_general (rs, dreg, bank);
1699                         else
1700                                 mono_regstate_free_int (rs, dreg);
1701                         rs->vassign [prev_dreg] = -1;
1702                 }
1703
1704                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1705                         /* this instruction only outputs to dest_dreg, need to copy */
1706                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1707                         ins->dreg = dest_dreg;
1708
1709                         if (G_UNLIKELY (bank)) {
1710                                 /* the register we need to free up may be used in another logical regbank
1711                                  * so do a translate just in case.
1712                                  */
1713                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1714                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1715                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1716                         }
1717                         else {
1718                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1719                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1720                         }
1721                 }
1722
1723                 if (spec_dest == 'b') {
1724                         /*
1725                          * The dest reg is read by the instruction, not written, so
1726                          * avoid allocating sreg1/sreg2 to the same reg.
1727                          */
1728                         for (j = 0; j < num_sregs; ++j)
1729                                 if (!sreg_bank (j, spec))
1730                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1731                 }
1732
1733                 /*
1734                  * TRACK CLOBBERING
1735                  */
1736                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1737                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1738                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1739                 }
1740
1741                 if (spec [MONO_INST_CLOB] == 'c') {
1742                         int j, s, dreg, dreg2, cur_bank;
1743                         guint64 clob_mask;
1744
1745                         clob_mask = MONO_ARCH_CALLEE_REGS;
1746
1747                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1748                                 /*
1749                                  * Need to avoid spilling the dreg since the dreg is not really
1750                                  * clobbered by the call.
1751                                  */
1752                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1753                                         dreg = rs->vassign [prev_dreg];
1754                                 else
1755                                         dreg = -1;
1756
1757                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1758                                         dreg2 = rs->vassign [prev_dreg + 1];
1759                                 else
1760                                         dreg2 = -1;
1761
1762                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1763                                         s = regmask (j);
1764                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1765                                                 if ((j != dreg) && (j != dreg2))
1766                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1767                                                 else if (rs->isymbolic [j])
1768                                                         /* The hreg is assigned to the dreg of this instruction */
1769                                                         rs->vassign [rs->isymbolic [j]] = -1;
1770                                                 mono_regstate_free_int (rs, j);
1771                                         }
1772                                 }
1773                         }
1774
1775                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1776                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1777                                         clob_mask = regbank_callee_regs [cur_bank];
1778                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1779                                                 dreg = rs->vassign [prev_dreg];
1780                                         else
1781                                                 dreg = -1;
1782
1783                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1784
1785                                                 /* we are looping though the banks in the outer loop
1786                                                  * so, we don't need to deal with mirrored hregs
1787                                                  * because we will get them in one of the other bank passes.
1788                                                  */
1789                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1790                                                         continue;
1791
1792                                                 s = regmask (j);
1793                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1794                                                         if (j != dreg)
1795                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1796                                                         else if (rs->symbolic [cur_bank] [j])
1797                                                                 /* The hreg is assigned to the dreg of this instruction */
1798                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1799                                                         mono_regstate_free_general (rs, j, cur_bank);
1800                                                 }
1801                                         }
1802                                 }
1803                         }
1804                 }
1805
1806                 /*
1807                  * TRACK ARGUMENT REGS
1808                  */
1809                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1810                         MonoCallInst *call = (MonoCallInst*)ins;
1811                         GSList *list;
1812
1813                         /*
1814                          * This needs to be done before assigning sreg1, so sreg1 will
1815                          * not be assigned one of the argument regs.
1816                          */
1817
1818                         /*
1819                          * Assign all registers in call->out_reg_args to the proper
1820                          * argument registers.
1821                          */
1822
1823                         list = call->out_ireg_args;
1824                         if (list) {
1825                                 while (list) {
1826                                         guint32 regpair;
1827                                         int reg, hreg;
1828
1829                                         regpair = (guint32)(gssize)(list->data);
1830                                         hreg = regpair >> 24;
1831                                         reg = regpair & 0xffffff;
1832
1833                                         assign_reg (cfg, rs, reg, hreg, 0);
1834
1835                                         sreg_masks [0] &= ~(regmask (hreg));
1836
1837                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1838
1839                                         list = g_slist_next (list);
1840                                 }
1841                         }
1842
1843                         list = call->out_freg_args;
1844                         if (list) {
1845                                 while (list) {
1846                                         guint32 regpair;
1847                                         int reg, hreg;
1848
1849                                         regpair = (guint32)(gssize)(list->data);
1850                                         hreg = regpair >> 24;
1851                                         reg = regpair & 0xffffff;
1852
1853                                         assign_reg (cfg, rs, reg, hreg, 1);
1854
1855                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1856
1857                                         list = g_slist_next (list);
1858                                 }
1859                         }
1860                 }
1861
1862                 /*
1863                  * TRACK SREG1
1864                  */
1865                 bank = sreg1_bank (spec);
1866                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1867                         int sreg1 = sregs [0];
1868                         int dest_sreg1 = dest_sregs [0];
1869
1870                         g_assert (is_soft_reg (sreg1, bank));
1871
1872                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1873                         if (dest_sreg1 != -1)
1874                                 g_assert (dest_sreg1 == ins->dreg);
1875                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1876                         g_assert (val >= 0);
1877
1878                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1879                                 // FIXME:
1880                                 g_assert_not_reached ();
1881
1882                         assign_reg (cfg, rs, sreg1, val, bank);
1883
1884                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1885
1886                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1887                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1888                         g_assert (val >= 0);
1889
1890                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1891                                 // FIXME:
1892                                 g_assert_not_reached ();
1893
1894                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1895
1896                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1897
1898                         /* Skip rest of this section */
1899                         dest_sregs [0] = -1;
1900                 }
1901
1902                 if (sreg_fixed_masks [0]) {
1903                         g_assert (!bank);
1904                         if (is_global_ireg (sregs [0])) {
1905                                 /*
1906                                  * The argument is already in a hard reg, but that reg is
1907                                  * not usable by this instruction, so allocate a new one.
1908                                  */
1909                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1910                                 if (val < 0)
1911                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1912                                 mono_regstate_free_int (rs, val);
1913                                 dest_sregs [0] = val;
1914
1915                                 /* Fall through to the dest_sreg1 != -1 case */
1916                         }
1917                         else
1918                                 sreg_masks [0] &= sreg_fixed_masks [0];
1919                 }
1920
1921                 if (dest_sregs [0] != -1) {
1922                         sreg_masks [0] = regmask (dest_sregs [0]);
1923
1924                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1925                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1926                         }
1927                         if (is_global_ireg (sregs [0])) {
1928                                 /* The argument is already in a hard reg, need to copy */
1929                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1930                                 insert_before_ins (bb, ins, copy);
1931                                 sregs [0] = dest_sregs [0];
1932                         }
1933                 }
1934
1935                 if (is_soft_reg (sregs [0], bank)) {
1936                         val = rs->vassign [sregs [0]];
1937                         prev_sregs [0] = sregs [0];
1938                         if (val < 0) {
1939                                 int spill = 0;
1940                                 if (val < -1) {
1941                                         /* the register gets spilled after this inst */
1942                                         spill = -val -1;
1943                                 }
1944
1945                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1946                                         /*
1947                                          * Allocate the same hreg to sreg1 as well so the
1948                                          * peephole can get rid of the move.
1949                                          */
1950                                         sreg_masks [0] = regmask (ins->dreg);
1951                                 }
1952
1953                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1954                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1955                                         sreg_masks [0] = regmask (ins->dreg);
1956
1957                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1958                                 assign_reg (cfg, rs, sregs [0], val, bank);
1959                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1960
1961                                 if (spill) {
1962                                         /*
1963                                          * Need to insert before the instruction since it can
1964                                          * overwrite sreg1.
1965                                          */
1966                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1967                                 }
1968                         }
1969                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1970                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1971                                 insert_before_ins (bb, ins, copy);
1972                                 for (j = 1; j < num_sregs; ++j)
1973                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1974                                 val = dest_sregs [0];
1975                         }
1976
1977                         sregs [0] = val;
1978                 }
1979                 else {
1980                         prev_sregs [0] = -1;
1981                 }
1982                 mono_inst_set_src_registers (ins, sregs);
1983
1984                 for (j = 1; j < num_sregs; ++j)
1985                         sreg_masks [j] &= ~(regmask (sregs [0]));
1986
1987                 /* Handle the case when sreg1 is a regpair but dreg is not */
1988                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1989                         int reg2 = prev_sregs [0] + 1;
1990
1991                         g_assert (!bank);
1992                         g_assert (prev_sregs [0] > -1);
1993                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1994                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1995                         val = rs->vassign [reg2];
1996                         if (val < 0) {
1997                                 int spill = 0;
1998                                 if (val < -1) {
1999                                         /* the register gets spilled after this inst */
2000                                         spill = -val -1;
2001                                 }
2002                                 val = mono_regstate_alloc_int (rs, mask);
2003                                 if (val < 0)
2004                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2005                                 if (spill)
2006                                         g_assert_not_reached ();
2007                         }
2008                         else {
2009                                 if (! (mask & (regmask (val)))) {
2010                                         /* The vreg is already allocated to a wrong hreg */
2011                                         /* FIXME: */
2012                                         g_assert_not_reached ();
2013 #if 0
2014                                         val = mono_regstate_alloc_int (rs, mask);
2015                                         if (val < 0)
2016                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2017
2018                                         /* Reallocate hreg to the correct register */
2019                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2020
2021                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2022 #endif
2023                                 }
2024                         }
2025
2026                         sreg1_high = val;
2027                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2028                         assign_reg (cfg, rs, reg2, val, bank);
2029                 }
2030
2031                 /* Handle dreg==sreg1 */
2032                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2033                         MonoInst *sreg2_copy = NULL;
2034                         MonoInst *copy;
2035                         int bank = reg_bank (spec_src1);
2036
2037                         if (ins->dreg == sregs [1]) {
2038                                 /*
2039                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2040                                  * register for it.
2041                                  */
2042                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2043
2044                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2045                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2046                                 prev_sregs [1] = sregs [1] = reg2;
2047
2048                                 if (G_UNLIKELY (bank))
2049                                         mono_regstate_free_general (rs, reg2, bank);
2050                                 else
2051                                         mono_regstate_free_int (rs, reg2);
2052                         }
2053
2054                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2055                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2056                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2057                                         /* FIXME: */
2058                                         g_assert_not_reached ();
2059
2060                                 /*
2061                                  * sreg1 and dest are already allocated to the same regpair by the
2062                                  * SREG1 allocation code.
2063                                  */
2064                                 g_assert (sregs [0] == ins->dreg);
2065                                 g_assert (dreg_high == sreg1_high);
2066                         }
2067
2068                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2069                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2070                         insert_before_ins (bb, ins, copy);
2071
2072                         if (sreg2_copy)
2073                                 insert_before_ins (bb, copy, sreg2_copy);
2074
2075                         /*
2076                          * Need to prevent sreg2 to be allocated to sreg1, since that
2077                          * would screw up the previous copy.
2078                          */
2079                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2080                         /* we set sreg1 to dest as well */
2081                         prev_sregs [0] = sregs [0] = ins->dreg;
2082                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2083                 }
2084                 mono_inst_set_src_registers (ins, sregs);
2085
2086                 /*
2087                  * TRACK SREG2, 3, ...
2088                  */
2089                 for (j = 1; j < num_sregs; ++j) {
2090                         int k;
2091
2092                         bank = sreg_bank (j, spec);
2093                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2094                                 g_assert_not_reached ();
2095
2096                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2097                                 /*
2098                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2099                                  * allocating it to the fixed reg.
2100                                  */
2101                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2102                                 insert_before_ins (bb, ins, copy);
2103                                 sregs [j] = dest_sregs [j];
2104                         } else if (is_soft_reg (sregs [j], bank)) {
2105                                 val = rs->vassign [sregs [j]];
2106
2107                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2108                                         /*
2109                                          * The sreg is already allocated to a hreg, but not to the fixed
2110                                          * reg required by the instruction. Spill the sreg, so it can be
2111                                          * allocated to the fixed reg by the code below.
2112                                          */
2113                                         /* Currently, this code should only be hit for CAS */
2114                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2115                                         val = rs->vassign [sregs [j]];
2116                                 }
2117
2118                                 if (val < 0) {
2119                                         int spill = 0;
2120                                         if (val < -1) {
2121                                                 /* the register gets spilled after this inst */
2122                                                 spill = -val -1;
2123                                         }
2124                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2125                                         assign_reg (cfg, rs, sregs [j], val, bank);
2126                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2127                                         if (spill) {
2128                                                 /*
2129                                                  * Need to insert before the instruction since it can
2130                                                  * overwrite sreg2.
2131                                                  */
2132                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2133                                         }
2134                                 }
2135                                 sregs [j] = val;
2136                                 for (k = j + 1; k < num_sregs; ++k)
2137                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2138                         }
2139                         else {
2140                                 prev_sregs [j] = -1;
2141                         }
2142                 }
2143                 mono_inst_set_src_registers (ins, sregs);
2144
2145                 /* Sanity check */
2146                 /* Do this only for CAS for now */
2147                 for (j = 1; j < num_sregs; ++j) {
2148                         int sreg = sregs [j];
2149                         int dest_sreg = dest_sregs [j];
2150
2151                         if (j == 2 && dest_sreg != -1) {
2152                                 int k;
2153
2154                                 g_assert (sreg == dest_sreg);
2155
2156                                 for (k = 0; k < num_sregs; ++k) {
2157                                         if (k != j)
2158                                                 g_assert (sregs [k] != dest_sreg);
2159                                 }
2160                         }
2161                 }
2162
2163                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2164                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2165                         mono_regstate_free_int (rs, ins->sreg1);
2166                 }
2167                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2168                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2169                         mono_regstate_free_int (rs, ins->sreg2);
2170                 }*/
2171
2172                 DEBUG (mono_print_ins_index (i, ins));
2173         }
2174
2175         // FIXME: Set MAX_FREGS to 8
2176         // FIXME: Optimize generated code
2177 #if MONO_ARCH_USE_FPSTACK
2178         /*
2179          * Make a forward pass over the code, simulating the fp stack, making sure the
2180          * arguments required by the fp opcodes are at the top of the stack.
2181          */
2182         if (has_fp) {
2183                 MonoInst *prev = NULL;
2184                 MonoInst *fxch;
2185                 int tmp;
2186
2187                 g_assert (num_sregs <= 2);
2188
2189                 for (ins = bb->code; ins; ins = ins->next) {
2190                         spec = ins_get_spec (ins->opcode);
2191
2192                         DEBUG (printf ("processing:"));
2193                         DEBUG (mono_print_ins_index (0, ins));
2194
2195                         if (ins->opcode == OP_FMOVE) {
2196                                 /* Do it by renaming the source to the destination on the stack */
2197                                 // FIXME: Is this correct ?
2198                                 for (i = 0; i < sp; ++i)
2199                                         if (fpstack [i] == ins->sreg1)
2200                                                 fpstack [i] = ins->dreg;
2201                                 prev = ins;
2202                                 continue;
2203                         }
2204
2205                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2206                                 /* Arg1 must be in %st(1) */
2207                                 g_assert (prev);
2208
2209                                 i = 0;
2210                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2211                                         i ++;
2212                                 g_assert (i < sp);
2213
2214                                 if (sp - 1 - i > 0) {
2215                                         /* First move it to %st(0) */
2216                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2217
2218                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2219                                         fxch->inst_imm = sp - 1 - i;
2220
2221                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2222                                         prev = fxch;
2223
2224                                         tmp = fpstack [sp - 1];
2225                                         fpstack [sp - 1] = fpstack [i];
2226                                         fpstack [i] = tmp;
2227                                 }
2228
2229                                 /* Then move it to %st(1) */
2230                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2231
2232                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2233                                 fxch->inst_imm = 1;
2234
2235                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2236                                 prev = fxch;
2237
2238                                 tmp = fpstack [sp - 1];
2239                                 fpstack [sp - 1] = fpstack [sp - 2];
2240                                 fpstack [sp - 2] = tmp;
2241                         }
2242
2243                         if (sreg2_is_fp (spec)) {
2244                                 g_assert (sp > 0);
2245
2246                                 if (fpstack [sp - 1] != ins->sreg2) {
2247                                         g_assert (prev);
2248
2249                                         i = 0;
2250                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2251                                                 i ++;
2252                                         g_assert (i < sp);
2253
2254                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2255
2256                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2257                                         fxch->inst_imm = sp - 1 - i;
2258
2259                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2260                                         prev = fxch;
2261
2262                                         tmp = fpstack [sp - 1];
2263                                         fpstack [sp - 1] = fpstack [i];
2264                                         fpstack [i] = tmp;
2265                                 }
2266
2267                                 sp --;
2268                         }
2269
2270                         if (sreg1_is_fp (spec)) {
2271                                 g_assert (sp > 0);
2272
2273                                 if (fpstack [sp - 1] != ins->sreg1) {
2274                                         g_assert (prev);
2275
2276                                         i = 0;
2277                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2278                                                 i ++;
2279                                         g_assert (i < sp);
2280
2281                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2282
2283                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2284                                         fxch->inst_imm = sp - 1 - i;
2285
2286                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2287                                         prev = fxch;
2288
2289                                         tmp = fpstack [sp - 1];
2290                                         fpstack [sp - 1] = fpstack [i];
2291                                         fpstack [i] = tmp;
2292                                 }
2293
2294                                 sp --;
2295                         }
2296
2297                         if (dreg_is_fp (spec)) {
2298                                 g_assert (sp < 8);
2299                                 fpstack [sp ++] = ins->dreg;
2300                         }
2301
2302                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2303                                 printf ("\t[");
2304                                 for (i = 0; i < sp; ++i)
2305                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2306                                 printf ("]\n");
2307                         }
2308
2309                         prev = ins;
2310                 }
2311
2312                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2313                         /* Remove remaining items from the fp stack */
2314                         /*
2315                          * These can remain for example as a result of a dead fmove like in
2316                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2317                          */
2318                         while (sp) {
2319                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2320                                 mono_add_ins_to_end (bb, ins);
2321                                 sp --;
2322                         }
2323                 }
2324         }
2325 #endif
2326 }
2327
2328 CompRelation
2329 mono_opcode_to_cond (int opcode)
2330 {
2331         switch (opcode) {
2332         case OP_CEQ:
2333         case OP_IBEQ:
2334         case OP_ICEQ:
2335         case OP_LBEQ:
2336         case OP_LCEQ:
2337         case OP_FBEQ:
2338         case OP_FCEQ:
2339         case OP_COND_EXC_EQ:
2340         case OP_COND_EXC_IEQ:
2341         case OP_CMOV_IEQ:
2342         case OP_CMOV_LEQ:
2343                 return CMP_EQ;
2344         case OP_IBNE_UN:
2345         case OP_LBNE_UN:
2346         case OP_FBNE_UN:
2347         case OP_COND_EXC_NE_UN:
2348         case OP_COND_EXC_INE_UN:
2349         case OP_CMOV_INE_UN:
2350         case OP_CMOV_LNE_UN:
2351                 return CMP_NE;
2352         case OP_IBLE:
2353         case OP_LBLE:
2354         case OP_FBLE:
2355         case OP_CMOV_ILE:
2356         case OP_CMOV_LLE:
2357                 return CMP_LE;
2358         case OP_IBGE:
2359         case OP_LBGE:
2360         case OP_FBGE:
2361         case OP_CMOV_IGE:
2362         case OP_CMOV_LGE:
2363                 return CMP_GE;
2364         case OP_CLT:
2365         case OP_IBLT:
2366         case OP_ICLT:
2367         case OP_LBLT:
2368         case OP_LCLT:
2369         case OP_FBLT:
2370         case OP_FCLT:
2371         case OP_COND_EXC_LT:
2372         case OP_COND_EXC_ILT:
2373         case OP_CMOV_ILT:
2374         case OP_CMOV_LLT:
2375                 return CMP_LT;
2376         case OP_CGT:
2377         case OP_IBGT:
2378         case OP_ICGT:
2379         case OP_LBGT:
2380         case OP_LCGT:
2381         case OP_FBGT:
2382         case OP_FCGT:
2383         case OP_COND_EXC_GT:
2384         case OP_COND_EXC_IGT:
2385         case OP_CMOV_IGT:
2386         case OP_CMOV_LGT:
2387                 return CMP_GT;
2388
2389         case OP_IBLE_UN:
2390         case OP_LBLE_UN:
2391         case OP_FBLE_UN:
2392         case OP_COND_EXC_LE_UN:
2393         case OP_COND_EXC_ILE_UN:
2394         case OP_CMOV_ILE_UN:
2395         case OP_CMOV_LLE_UN:
2396                 return CMP_LE_UN;
2397         case OP_IBGE_UN:
2398         case OP_LBGE_UN:
2399         case OP_FBGE_UN:
2400         case OP_CMOV_IGE_UN:
2401         case OP_CMOV_LGE_UN:
2402                 return CMP_GE_UN;
2403         case OP_CLT_UN:
2404         case OP_IBLT_UN:
2405         case OP_ICLT_UN:
2406         case OP_LBLT_UN:
2407         case OP_LCLT_UN:
2408         case OP_FBLT_UN:
2409         case OP_FCLT_UN:
2410         case OP_COND_EXC_LT_UN:
2411         case OP_COND_EXC_ILT_UN:
2412         case OP_CMOV_ILT_UN:
2413         case OP_CMOV_LLT_UN:
2414                 return CMP_LT_UN;
2415         case OP_CGT_UN:
2416         case OP_IBGT_UN:
2417         case OP_ICGT_UN:
2418         case OP_LBGT_UN:
2419         case OP_LCGT_UN:
2420         case OP_FCGT_UN:
2421         case OP_FBGT_UN:
2422         case OP_COND_EXC_GT_UN:
2423         case OP_COND_EXC_IGT_UN:
2424         case OP_CMOV_IGT_UN:
2425         case OP_CMOV_LGT_UN:
2426                 return CMP_GT_UN;
2427         default:
2428                 printf ("%s\n", mono_inst_name (opcode));
2429                 g_assert_not_reached ();
2430                 return 0;
2431         }
2432 }
2433
2434 CompRelation
2435 mono_negate_cond (CompRelation cond)
2436 {
2437         switch (cond) {
2438         case CMP_EQ:
2439                 return CMP_NE;
2440         case CMP_NE:
2441                 return CMP_EQ;
2442         case CMP_LE:
2443                 return CMP_GT;
2444         case CMP_GE:
2445                 return CMP_LT;
2446         case CMP_LT:
2447                 return CMP_GE;
2448         case CMP_GT:
2449                 return CMP_LE;
2450         case CMP_LE_UN:
2451                 return CMP_GT_UN;
2452         case CMP_GE_UN:
2453                 return CMP_LT_UN;
2454         case CMP_LT_UN:
2455                 return CMP_GE_UN;
2456         case CMP_GT_UN:
2457                 return CMP_LE_UN;
2458         default:
2459                 g_assert_not_reached ();
2460         }
2461 }
2462
2463 CompType
2464 mono_opcode_to_type (int opcode, int cmp_opcode)
2465 {
2466         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2467                 return CMP_TYPE_L;
2468         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2469                 return CMP_TYPE_I;
2470         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2471                 return CMP_TYPE_I;
2472         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2473                 return CMP_TYPE_L;
2474         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2475                 return CMP_TYPE_L;
2476         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2477                 return CMP_TYPE_F;
2478         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2479                 return CMP_TYPE_F;
2480         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2481                 return CMP_TYPE_I;
2482         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2483                 switch (cmp_opcode) {
2484                 case OP_ICOMPARE:
2485                 case OP_ICOMPARE_IMM:
2486                         return CMP_TYPE_I;
2487                 default:
2488                         return CMP_TYPE_L;
2489                 }
2490         } else {
2491                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2492                 return 0;
2493         }
2494 }
2495
2496 #endif /* DISABLE_JIT */
2497
2498 gboolean
2499 mono_is_regsize_var (MonoType *t)
2500 {
2501         if (t->byref)
2502                 return TRUE;
2503         t = mono_type_get_underlying_type (t);
2504         switch (t->type) {
2505         case MONO_TYPE_BOOLEAN:
2506         case MONO_TYPE_CHAR:
2507         case MONO_TYPE_I1:
2508         case MONO_TYPE_U1:
2509         case MONO_TYPE_I2:
2510         case MONO_TYPE_U2:
2511         case MONO_TYPE_I4:
2512         case MONO_TYPE_U4:
2513         case MONO_TYPE_I:
2514         case MONO_TYPE_U:
2515         case MONO_TYPE_PTR:
2516         case MONO_TYPE_FNPTR:
2517 #if SIZEOF_REGISTER == 8
2518         case MONO_TYPE_I8:
2519         case MONO_TYPE_U8:
2520 #endif
2521                 return TRUE;
2522         case MONO_TYPE_OBJECT:
2523         case MONO_TYPE_STRING:
2524         case MONO_TYPE_CLASS:
2525         case MONO_TYPE_SZARRAY:
2526         case MONO_TYPE_ARRAY:
2527                 return TRUE;
2528         case MONO_TYPE_GENERICINST:
2529                 if (!mono_type_generic_inst_is_valuetype (t))
2530                         return TRUE;
2531                 return FALSE;
2532         case MONO_TYPE_VALUETYPE:
2533                 return FALSE;
2534         default:
2535                 return FALSE;
2536         }
2537 }
2538
2539 #ifndef DISABLE_JIT
2540
2541 /*
2542  * mono_peephole_ins:
2543  *
2544  *   Perform some architecture independent peephole optimizations.
2545  */
2546 void
2547 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2548 {
2549         MonoInst *last_ins = ins->prev;
2550
2551         switch (ins->opcode) {
2552         case OP_MUL_IMM:
2553                 /* remove unnecessary multiplication with 1 */
2554                 if (ins->inst_imm == 1) {
2555                         if (ins->dreg != ins->sreg1)
2556                                 ins->opcode = OP_MOVE;
2557                         else
2558                                 MONO_DELETE_INS (bb, ins);
2559                 }
2560                 break;
2561         case OP_LOAD_MEMBASE:
2562         case OP_LOADI4_MEMBASE:
2563                 /*
2564                  * Note: if reg1 = reg2 the load op is removed
2565                  *
2566                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2567                  * OP_LOAD_MEMBASE offset(basereg), reg2
2568                  * -->
2569                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2570                  * OP_MOVE reg1, reg2
2571                  */
2572                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2573                         last_ins = last_ins->prev;
2574                 if (last_ins &&
2575                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2576                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2577                         ins->inst_basereg == last_ins->inst_destbasereg &&
2578                         ins->inst_offset == last_ins->inst_offset) {
2579                         if (ins->dreg == last_ins->sreg1) {
2580                                 MONO_DELETE_INS (bb, ins);
2581                                 break;
2582                         } else {
2583                                 ins->opcode = OP_MOVE;
2584                                 ins->sreg1 = last_ins->sreg1;
2585                         }
2586
2587                         /*
2588                          * Note: reg1 must be different from the basereg in the second load
2589                          * Note: if reg1 = reg2 is equal then second load is removed
2590                          *
2591                          * OP_LOAD_MEMBASE offset(basereg), reg1
2592                          * OP_LOAD_MEMBASE offset(basereg), reg2
2593                          * -->
2594                          * OP_LOAD_MEMBASE offset(basereg), reg1
2595                          * OP_MOVE reg1, reg2
2596                          */
2597                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2598                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2599                           ins->inst_basereg != last_ins->dreg &&
2600                           ins->inst_basereg == last_ins->inst_basereg &&
2601                           ins->inst_offset == last_ins->inst_offset) {
2602
2603                         if (ins->dreg == last_ins->dreg) {
2604                                 MONO_DELETE_INS (bb, ins);
2605                         } else {
2606                                 ins->opcode = OP_MOVE;
2607                                 ins->sreg1 = last_ins->dreg;
2608                         }
2609
2610                         //g_assert_not_reached ();
2611
2612 #if 0
2613                         /*
2614                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2615                          * OP_LOAD_MEMBASE offset(basereg), reg
2616                          * -->
2617                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2618                          * OP_ICONST reg, imm
2619                          */
2620                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2621                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2622                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2623                                    ins->inst_offset == last_ins->inst_offset) {
2624                         ins->opcode = OP_ICONST;
2625                         ins->inst_c0 = last_ins->inst_imm;
2626                         g_assert_not_reached (); // check this rule
2627 #endif
2628                 }
2629                 break;
2630         case OP_LOADI1_MEMBASE:
2631         case OP_LOADU1_MEMBASE:
2632                 /*
2633                  * Note: if reg1 = reg2 the load op is removed
2634                  *
2635                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2636                  * OP_LOAD_MEMBASE offset(basereg), reg2
2637                  * -->
2638                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2639                  * OP_MOVE reg1, reg2
2640                  */
2641                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2642                         ins->inst_basereg == last_ins->inst_destbasereg &&
2643                         ins->inst_offset == last_ins->inst_offset) {
2644                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2645                         ins->sreg1 = last_ins->sreg1;
2646                 }
2647                 break;
2648         case OP_LOADI2_MEMBASE:
2649         case OP_LOADU2_MEMBASE:
2650                 /*
2651                  * Note: if reg1 = reg2 the load op is removed
2652                  *
2653                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2654                  * OP_LOAD_MEMBASE offset(basereg), reg2
2655                  * -->
2656                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2657                  * OP_MOVE reg1, reg2
2658                  */
2659                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2660                         ins->inst_basereg == last_ins->inst_destbasereg &&
2661                         ins->inst_offset == last_ins->inst_offset) {
2662 #if SIZEOF_REGISTER == 8
2663                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2664 #else
2665                         /* The definition of OP_PCONV_TO_U2 is wrong */
2666                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2667 #endif
2668                         ins->sreg1 = last_ins->sreg1;
2669                 }
2670                 break;
2671         case OP_MOVE:
2672         case OP_FMOVE:
2673                 /*
2674                  * Removes:
2675                  *
2676                  * OP_MOVE reg, reg
2677                  */
2678                 if (ins->dreg == ins->sreg1) {
2679                         MONO_DELETE_INS (bb, ins);
2680                         break;
2681                 }
2682                 /*
2683                  * Removes:
2684                  *
2685                  * OP_MOVE sreg, dreg
2686                  * OP_MOVE dreg, sreg
2687                  */
2688                 if (last_ins && last_ins->opcode == ins->opcode &&
2689                         ins->sreg1 == last_ins->dreg &&
2690                         ins->dreg == last_ins->sreg1) {
2691                         MONO_DELETE_INS (bb, ins);
2692                 }
2693                 break;
2694         case OP_NOP:
2695                 MONO_DELETE_INS (bb, ins);
2696                 break;
2697         }
2698 }
2699
2700 #endif /* DISABLE_JIT */