mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583                 printf (" [%d]", (int)ins->inst_imm);
 584                 break;
 585         case OP_ADD_IMM:
 586         case OP_LADD_IMM:
 587                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 588                 break;
 589         case OP_I8CONST:
 590                 printf (" [%lld]", (long long)ins->inst_l);
 591                 break;
 592         case OP_R8CONST:
 593                 printf (" [%f]", *(double*)ins->inst_p0);
 594                 break;
 595         case OP_R4CONST:
 596                 printf (" [%f]", *(float*)ins->inst_p0);
 597                 break;
 598         case OP_CALL:
 599         case OP_CALL_MEMBASE:
 600         case OP_CALL_REG:
 601         case OP_FCALL:
 602         case OP_LCALL:
 603         case OP_VCALL:
 604         case OP_VCALL_REG:
 605         case OP_VCALL_MEMBASE:
 606         case OP_VCALL2:
 607         case OP_VCALL2_REG:
 608         case OP_VCALL2_MEMBASE:
 609         case OP_VOIDCALL:
 610         case OP_VOIDCALL_MEMBASE:
 611         case OP_TAILCALL: {
 612                 MonoCallInst *call = (MonoCallInst*)ins;
 613                 GSList *list;
 614
 615                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 616                         /*
 617                          * These are lowered opcodes, but they are in the .md files since the old
 618                          * JIT passes them to backends.
 619                          */
 620                         if (ins->dreg != -1)
 621                                 printf (" R%d <-", ins->dreg);
 622                 }
 623
 624                 if (call->method) {
 625                         char *full_name = mono_method_full_name (call->method, TRUE);
 626                         printf (" [%s]", full_name);
 627                         g_free (full_name);
 628                 } else if (call->fptr_is_patch) {
 629                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 630
 631                         printf (" ");
 632                         mono_print_ji (ji);
 633                 } else if (call->fptr) {
 634                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 635                         if (info)
 636                                 printf (" [%s]", info->name);
 637                 }
 638
 639                 list = call->out_ireg_args;
 640                 while (list) {
 641                         guint32 regpair;
 642                         int reg, hreg;
 643
 644                         regpair = (guint32)(gssize)(list->data);
 645                         hreg = regpair >> 24;
 646                         reg = regpair & 0xffffff;
 647
 648                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 649
 650                         list = g_slist_next (list);
 651                 }
 652                 break;
 653         }
 654         case OP_BR:
 655         case OP_CALL_HANDLER:
 656                 printf (" [B%d]", ins->inst_target_bb->block_num);
 657                 break;
 658         case OP_IBNE_UN:
 659         case OP_IBEQ:
 660         case OP_IBLT:
 661         case OP_IBLT_UN:
 662         case OP_IBGT:
 663         case OP_IBGT_UN:
 664         case OP_IBGE:
 665         case OP_IBGE_UN:
 666         case OP_IBLE:
 667         case OP_IBLE_UN:
 668         case OP_LBNE_UN:
 669         case OP_LBEQ:
 670         case OP_LBLT:
 671         case OP_LBLT_UN:
 672         case OP_LBGT:
 673         case OP_LBGT_UN:
 674         case OP_LBGE:
 675         case OP_LBGE_UN:
 676         case OP_LBLE:
 677         case OP_LBLE_UN:
 678                 if (!ins->inst_false_bb)
 679                         printf (" [B%d]", ins->inst_true_bb->block_num);
 680                 else
 681                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 682                 break;
 683         case OP_LIVERANGE_START:
 684         case OP_LIVERANGE_END:
 685         case OP_GC_LIVENESS_DEF:
 686         case OP_GC_LIVENESS_USE:
 687                 printf (" R%d", (int)ins->inst_c1);
 688                 break;
 689         case OP_SEQ_POINT:
 690                 printf (" il: %x", (int)ins->inst_imm);
 691                 break;
 692         default:
 693                 break;
 694         }
 695
 696         if (spec [MONO_INST_CLOB])
 697                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 698         printf ("\n");
 699 }
 700
 701 static void
 702 print_regtrack (RegTrack *t, int num)
 703 {
 704         int i;
 705         char buf [32];
 706         const char *r;
 707
 708         for (i = 0; i < num; ++i) {
 709                 if (!t [i].born_in)
 710                         continue;
 711                 if (i >= MONO_MAX_IREGS) {
 712                         g_snprintf (buf, sizeof(buf), "R%d", i);
 713                         r = buf;
 714                 } else
 715                         r = mono_arch_regname (i);
 716                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 717         }
 718 }
 719 #else
 720
 721 void
 722 mono_print_ji (const MonoJumpInfo *ji)
 723 {
 724 }
 725
 726 void
 727 mono_print_ins_index (int i, MonoInst *ins)
 728 {
 729 }
 730 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 731
 732 void
 733 mono_print_ins (MonoInst *ins)
 734 {
 735         mono_print_ins_index (-1, ins);
 736 }
 737
 738 static inline void
 739 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 740 {
 741         /*
 742          * If this function is called multiple times, the new instructions are inserted
 743          * in the proper order.
 744          */
 745         mono_bblock_insert_before_ins (bb, ins, to_insert);
 746 }
 747
 748 static inline void
 749 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 750 {
 751         /*
 752          * If this function is called multiple times, the new instructions are inserted in
 753          * proper order.
 754          */
 755         mono_bblock_insert_after_ins (bb, *last, to_insert);
 756
 757         *last = to_insert;
 758 }
 759
 760 static inline int
 761 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 762 {
 763         if (vreg_is_ref (cfg, reg))
 764                 return MONO_REG_INT_REF;
 765         else if (vreg_is_mp (cfg, reg))
 766                 return MONO_REG_INT_MP;
 767         else
 768                 return bank;
 769 }
 770
 771 /*
 772  * Force the spilling of the variable in the symbolic register 'reg', and free
 773  * the hreg it was assigned to.
 774  */
 775 static void
 776 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 777 {
 778         MonoInst *load;
 779         int i, sel, spill;
 780         int *symbolic;
 781         MonoRegState *rs = cfg->rs;
 782
 783         symbolic = rs->symbolic [bank];
 784         sel = rs->vassign [reg];
 785
 786         /* the vreg we need to spill lives in another logical reg bank */
 787         bank = translate_bank (cfg->rs, bank, sel);
 788
 789         /*i = rs->isymbolic [sel];
 790         g_assert (i == reg);*/
 791         i = reg;
 792         spill = ++cfg->spill_count;
 793         rs->vassign [i] = -spill - 1;
 794         if (G_UNLIKELY (bank))
 795                 mono_regstate_free_general (rs, sel, bank);
 796         else
 797                 mono_regstate_free_int (rs, sel);
 798         /* we need to create a spill var and insert a load to sel after the current instruction */
 799         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 800         load->dreg = sel;
 801         load->inst_basereg = cfg->frame_reg;
 802         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 803         insert_after_ins (bb, ins, last, load);
 804         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 805         if (G_UNLIKELY (bank))
 806                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 807         else
 808                 i = mono_regstate_alloc_int (rs, regmask (sel));
 809         g_assert (i == sel);
 810
 811         if (G_UNLIKELY (bank))
 812                 mono_regstate_free_general (rs, sel, bank);
 813         else
 814                 mono_regstate_free_int (rs, sel);
 815 }
 816
 817 /* This isn't defined on older glib versions and on some platforms */
 818 #ifndef G_GUINT64_FORMAT
 819 #define G_GUINT64_FORMAT "ul"
 820 #endif
 821
 822 static int
 823 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 824 {
 825         MonoInst *load;
 826         int i, sel, spill, num_sregs;
 827         int sregs [MONO_MAX_SRC_REGS];
 828         int *symbolic;
 829         MonoRegState *rs = cfg->rs;
 830
 831         symbolic = rs->symbolic [bank];
 832
 833         g_assert (bank < MONO_NUM_REGBANKS);
 834
 835         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 836         /* exclude the registers in the current instruction */
 837         num_sregs = mono_inst_get_src_registers (ins, sregs);
 838         for (i = 0; i < num_sregs; ++i) {
 839                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 840                         if (is_soft_reg (sregs [i], bank))
 841                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 842                         else
 843                                 regmask &= ~ (regmask (sregs [i]));
 844                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 845                 }
 846         }
 847         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 848                 regmask &= ~ (regmask (ins->dreg));
 849                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 850         }
 851
 852         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 853         g_assert (regmask); /* need at least a register we can free */
 854         sel = 0;
 855         /* we should track prev_use and spill the register that's farther */
 856         if (G_UNLIKELY (bank)) {
 857                 for (i = 0; i < regbank_size [bank]; ++i) {
 858                         if (regmask & (regmask (i))) {
 859                                 sel = i;
 860
 861                                 /* the vreg we need to load lives in another logical bank */
 862                                 bank = translate_bank (cfg->rs, bank, sel);
 863
 864                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 865                                 break;
 866                         }
 867                 }
 868
 869                 i = rs->symbolic [bank] [sel];
 870                 spill = ++cfg->spill_count;
 871                 rs->vassign [i] = -spill - 1;
 872                 mono_regstate_free_general (rs, sel, bank);
 873         }
 874         else {
 875                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 876                         if (regmask & (regmask (i))) {
 877                                 sel = i;
 878                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 879                                 break;
 880                         }
 881                 }
 882
 883                 i = rs->isymbolic [sel];
 884                 spill = ++cfg->spill_count;
 885                 rs->vassign [i] = -spill - 1;
 886                 mono_regstate_free_int (rs, sel);
 887         }
 888
 889         /* we need to create a spill var and insert a load to sel after the current instruction */
 890         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 891         load->dreg = sel;
 892         load->inst_basereg = cfg->frame_reg;
 893         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 894         insert_after_ins (bb, ins, last, load);
 895         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 896         if (G_UNLIKELY (bank))
 897                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 898         else
 899                 i = mono_regstate_alloc_int (rs, regmask (sel));
 900         g_assert (i == sel);
 901
 902         return sel;
 903 }
 904
 905 /*
 906  * free_up_hreg:
 907  *
 908  *   Free up the hreg HREG by spilling the vreg allocated to it.
 909  */
 910 static void
 911 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 912 {
 913         if (G_UNLIKELY (bank)) {
 914                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 915                         bank = translate_bank (cfg->rs, bank, hreg);
 916                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 917                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 918                 }
 919         }
 920         else {
 921                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 922                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 923                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 924                 }
 925         }
 926 }
 927
 928 static MonoInst*
 929 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 930 {
 931         MonoInst *copy;
 932
 933         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 934
 935         copy->dreg = dest;
 936         copy->sreg1 = src;
 937         copy->cil_code = ip;
 938         if (ins) {
 939                 mono_bblock_insert_after_ins (bb, ins, copy);
 940                 *last = copy;
 941         }
 942         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 943         return copy;
 944 }
 945
 946 static inline const char*
 947 regbank_to_string (int bank)
 948 {
 949         if (bank == MONO_REG_INT_REF)
 950                 return "REF ";
 951         else if (bank == MONO_REG_INT_MP)
 952                 return "MP ";
 953         else
 954                 return "";
 955 }
 956
 957 static void
 958 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 959 {
 960         MonoInst *store, *def;
 961
 962         bank = get_vreg_bank (cfg, prev_reg, bank);
 963
 964         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 965         store->sreg1 = reg;
 966         store->inst_destbasereg = cfg->frame_reg;
 967         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 968         if (ins) {
 969                 mono_bblock_insert_after_ins (bb, ins, store);
 970                 *last = store;
 971         } else if (insert_before) {
 972                 insert_before_ins (bb, insert_before, store);
 973         } else {
 974                 g_assert_not_reached ();
 975         }
 976         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 977
 978         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 979                 g_assert (prev_reg != -1);
 980                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 981                 def->inst_c0 = spill;
 982                 def->inst_c1 = bank;
 983                 mono_bblock_insert_after_ins (bb, store, def);
 984         }
 985 }
 986
 987 /* flags used in reginfo->flags */
 988 enum {
 989         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 990         MONO_FP_NEEDS_SPILL                     = regmask (1),
 991         MONO_FP_NEEDS_LOAD                      = regmask (2)
 992 };
 993
 994 static inline int
 995 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 996 {
 997         int val;
 998
 999         if (info && info->preferred_mask) {
1000                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1001                 if (val >= 0) {
1002                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1003                         return val;
1004                 }
1005         }
1006
1007         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1008         if (val < 0)
1009                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1010
1011         return val;
1012 }
1013
1014 static inline int
1015 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1016 {
1017         int val;
1018
1019         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1020
1021         if (val < 0)
1022                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1023
1024         return val;
1025 }
1026
1027 static inline int
1028 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1029 {
1030         if (G_UNLIKELY (bank))
1031                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1032         else
1033                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1034 }
1035
1036 static inline void
1037 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1038 {
1039         if (G_UNLIKELY (bank)) {
1040                 int mirrored_bank;
1041
1042                 g_assert (reg >= regbank_size [bank]);
1043                 g_assert (hreg < regbank_size [bank]);
1044                 g_assert (! is_global_freg (hreg));
1045
1046                 rs->vassign [reg] = hreg;
1047                 rs->symbolic [bank] [hreg] = reg;
1048                 rs->free_mask [bank] &= ~ (regmask (hreg));
1049
1050                 mirrored_bank = get_mirrored_bank (bank);
1051                 if (mirrored_bank == -1)
1052                         return;
1053
1054                 /* Make sure the other logical reg bank that this bank shares
1055                  * a single hard reg bank knows that this hard reg is not free.
1056                  */
1057                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1058
1059                 /* Mark the other logical bank that the this bank shares
1060                  * a single hard reg bank with as mirrored.
1061                  */
1062                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1063
1064         }
1065         else {
1066                 g_assert (reg >= MONO_MAX_IREGS);
1067                 g_assert (hreg < MONO_MAX_IREGS);
1068 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1069                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1070                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1071                 g_assert (! is_global_ireg (hreg));
1072 #endif
1073
1074                 rs->vassign [reg] = hreg;
1075                 rs->isymbolic [hreg] = reg;
1076                 rs->ifree_mask &= ~ (regmask (hreg));
1077         }
1078 }
1079
1080 static inline regmask_t
1081 get_callee_mask (const char spec)
1082 {
1083         if (G_UNLIKELY (reg_bank (spec)))
1084                 return regbank_callee_regs [reg_bank (spec)];
1085         return MONO_ARCH_CALLEE_REGS;
1086 }
1087
1088 static gint8 desc_to_fixed_reg [256];
1089 static gboolean desc_to_fixed_reg_inited = FALSE;
1090
1091 #ifndef DISABLE_JIT
1092
1093 /*
1094  * Local register allocation.
1095  * We first scan the list of instructions and we save the liveness info of
1096  * each register (when the register is first used, when it's value is set etc.).
1097  * We also reverse the list of instructions because assigning registers backwards allows
1098  * for more tricks to be used.
1099  */
1100 void
1101 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1102 {
1103         MonoInst *ins, *prev, *last;
1104         MonoInst **tmp;
1105         MonoRegState *rs = cfg->rs;
1106         int i, j, val, max;
1107         RegTrack *reginfo;
1108         const char *spec;
1109         unsigned char spec_src1, spec_dest;
1110         int bank = 0;
1111 #if MONO_ARCH_USE_FPSTACK
1112         gboolean has_fp = FALSE;
1113         int fpstack [8];
1114         int sp = 0;
1115 #endif
1116         int num_sregs = 0;
1117         int sregs [MONO_MAX_SRC_REGS];
1118
1119         if (!bb->code)
1120                 return;
1121
1122         if (!desc_to_fixed_reg_inited) {
1123                 for (i = 0; i < 256; ++i)
1124                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1125                 desc_to_fixed_reg_inited = TRUE;
1126
1127                 /* Validate the cpu description against the info in mini-ops.h */
1128 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1129                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1130                         const char *ispec;
1131
1132                         spec = ins_get_spec (i);
1133                         ispec = INS_INFO (i);
1134
1135                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1136                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1137                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1138                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1139                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1140                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1141                 }
1142 #endif
1143         }
1144
1145         rs->next_vreg = bb->max_vreg;
1146         mono_regstate_assign (rs);
1147
1148         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1149         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1150                 rs->free_mask [i] = regbank_callee_regs [i];
1151
1152         max = rs->next_vreg;
1153
1154         if (cfg->reginfo && cfg->reginfo_len < max)
1155                 cfg->reginfo = NULL;
1156
1157         reginfo = cfg->reginfo;
1158         if (!reginfo) {
1159                 cfg->reginfo_len = MAX (1024, max * 2);
1160                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1161         }
1162         else
1163                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1164
1165         if (cfg->verbose_level > 1) {
1166                 /* print_regtrack reads the info of all variables */
1167                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1168         }
1169
1170         /*
1171          * For large methods, next_vreg can be very large, so g_malloc0 time can
1172          * be prohibitive. So we manually init the reginfo entries used by the
1173          * bblock.
1174          */
1175         for (ins = bb->code; ins; ins = ins->next) {
1176                 spec = ins_get_spec (ins->opcode);
1177
1178                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1179                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1180 #if SIZEOF_REGISTER == 4
1181                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1182                                 /**
1183                                  * In the new IR, the two vregs of the regpair do not alias the
1184                                  * original long vreg. shift the vreg here so the rest of the
1185                                  * allocator doesn't have to care about it.
1186                                  */
1187                                 ins->dreg ++;
1188                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1189                         }
1190 #endif
1191                 }
1192
1193                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1194                 for (j = 0; j < num_sregs; ++j) {
1195                         g_assert (sregs [j] != -1);
1196                         if (sregs [j] < max) {
1197                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1198 #if SIZEOF_REGISTER == 4
1199                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1200                                         sregs [j]++;
1201                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1202                                 }
1203 #endif
1204                         }
1205                 }
1206                 mono_inst_set_src_registers (ins, sregs);
1207         }
1208
1209         /*if (cfg->opt & MONO_OPT_COPYPROP)
1210                 local_copy_prop (cfg, ins);*/
1211
1212         i = 1;
1213         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1214         /* forward pass on the instructions to collect register liveness info */
1215         MONO_BB_FOR_EACH_INS (bb, ins) {
1216                 spec = ins_get_spec (ins->opcode);
1217                 spec_dest = spec [MONO_INST_DEST];
1218
1219                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1220                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1221                 }
1222
1223                 DEBUG (mono_print_ins_index (i, ins));
1224
1225                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1226
1227 #if MONO_ARCH_USE_FPSTACK
1228                 if (dreg_is_fp (spec)) {
1229                         has_fp = TRUE;
1230                 } else {
1231                         for (j = 0; j < num_sregs; ++j) {
1232                                 if (sreg_is_fp (j, spec))
1233                                         has_fp = TRUE;
1234                         }
1235                 }
1236 #endif
1237
1238                 for (j = 0; j < num_sregs; ++j) {
1239                         int sreg = sregs [j];
1240                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1241                         if (sreg_spec) {
1242                                 bank = sreg_bank (j, spec);
1243                                 g_assert (sreg != -1);
1244                                 if (is_soft_reg (sreg, bank))
1245                                         /* This means the vreg is not local to this bb */
1246                                         g_assert (reginfo [sreg].born_in > 0);
1247                                 rs->vassign [sreg] = -1;
1248                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1249                                 //reginfo [ins->sreg2].last_use = i;
1250                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1251                                         /* The virtual register is allocated sequentially */
1252                                         rs->vassign [sreg + 1] = -1;
1253                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1254                                         //reginfo [ins->sreg2 + 1].last_use = i;
1255                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1256                                                 reginfo [sreg + 1].born_in = i;
1257                                 }
1258                         } else {
1259                                 sregs [j] = -1;
1260                         }
1261                 }
1262                 mono_inst_set_src_registers (ins, sregs);
1263
1264                 if (spec_dest) {
1265                         int dest_dreg;
1266
1267                         bank = dreg_bank (spec);
1268                         if (spec_dest != 'b') /* it's not just a base register */
1269                                 reginfo [ins->dreg].killed_in = i;
1270                         g_assert (ins->dreg != -1);
1271                         rs->vassign [ins->dreg] = -1;
1272                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1273                         //reginfo [ins->dreg].last_use = i;
1274                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1275                                 reginfo [ins->dreg].born_in = i;
1276
1277                         dest_dreg = desc_to_fixed_reg [spec_dest];
1278                         if (dest_dreg != -1)
1279                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1280
1281 #ifdef MONO_ARCH_INST_FIXED_MASK
1282                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1283 #endif
1284
1285                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1286                                 /* The virtual register is allocated sequentially */
1287                                 rs->vassign [ins->dreg + 1] = -1;
1288                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1289                                 //reginfo [ins->dreg + 1].last_use = i;
1290                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1291                                         reginfo [ins->dreg + 1].born_in = i;
1292                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1293                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1294                         }
1295                 } else {
1296                         ins->dreg = -1;
1297                 }
1298
1299                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1300                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1301
1302                         MonoCallInst *call = (MonoCallInst*)ins;
1303                         GSList *list;
1304
1305                         list = call->out_ireg_args;
1306                         if (list) {
1307                                 while (list) {
1308                                         guint32 regpair;
1309                                         int reg, hreg;
1310
1311                                         regpair = (guint32)(gssize)(list->data);
1312                                         hreg = regpair >> 24;
1313                                         reg = regpair & 0xffffff;
1314
1315                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1316                                         //reginfo [reg].last_use = i;
1317
1318                                         list = g_slist_next (list);
1319                                 }
1320                         }
1321
1322                         list = call->out_freg_args;
1323                         if (list) {
1324                                 while (list) {
1325                                         guint32 regpair;
1326                                         int reg, hreg;
1327
1328                                         regpair = (guint32)(gssize)(list->data);
1329                                         hreg = regpair >> 24;
1330                                         reg = regpair & 0xffffff;
1331
1332                                         list = g_slist_next (list);
1333                                 }
1334                         }
1335                 }
1336
1337                 ++i;
1338         }
1339
1340         tmp = &last;
1341
1342         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1343         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1344                 int prev_dreg, clob_dreg;
1345                 int dest_dreg, clob_reg;
1346                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1347                 int dreg_high, sreg1_high;
1348                 regmask_t dreg_mask, mask;
1349                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1350                 regmask_t dreg_fixed_mask;
1351                 const unsigned char *ip;
1352                 --i;
1353                 spec = ins_get_spec (ins->opcode);
1354                 spec_src1 = spec [MONO_INST_SRC1];
1355                 spec_dest = spec [MONO_INST_DEST];
1356                 prev_dreg = -1;
1357                 clob_dreg = -1;
1358                 clob_reg = -1;
1359                 dest_dreg = -1;
1360                 dreg_high = -1;
1361                 sreg1_high = -1;
1362                 dreg_mask = get_callee_mask (spec_dest);
1363                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1364                         prev_sregs [j] = -1;
1365                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1366                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1367 #ifdef MONO_ARCH_INST_FIXED_MASK
1368                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1369 #else
1370                         sreg_fixed_masks [j] = 0;
1371 #endif
1372                 }
1373
1374                 DEBUG (printf ("processing:"));
1375                 DEBUG (mono_print_ins_index (i, ins));
1376
1377                 ip = ins->cil_code;
1378
1379                 last = ins;
1380
1381                 /*
1382                  * FIXED REGS
1383                  */
1384                 dest_dreg = desc_to_fixed_reg [spec_dest];
1385                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1386                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1387
1388 #ifdef MONO_ARCH_INST_FIXED_MASK
1389                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1390 #else
1391                 dreg_fixed_mask = 0;
1392 #endif
1393
1394                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1395
1396                 /*
1397                  * TRACK FIXED SREG2, 3, ...
1398                  */
1399                 for (j = 1; j < num_sregs; ++j) {
1400                         int sreg = sregs [j];
1401                         int dest_sreg = dest_sregs [j];
1402
1403                         if (dest_sreg == -1)
1404                                 continue;
1405
1406                         if (j == 2) {
1407                                 int k;
1408
1409                                 /*
1410                                  * CAS.
1411                                  * We need to special case this, since on x86, there are only 3
1412                                  * free registers, and the code below assigns one of them to
1413                                  * sreg, so we can run out of registers when trying to assign
1414                                  * dreg. Instead, we just set up the register masks, and let the
1415                                  * normal sreg2 assignment code handle this. It would be nice to
1416                                  * do this for all the fixed reg cases too, but there is too much
1417                                  * risk of breakage.
1418                                  */
1419
1420                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1421                                 sreg_masks [j] = regmask (dest_sreg);
1422                                 for (k = 0; k < num_sregs; ++k) {
1423                                         if (k != j)
1424                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1425                                 }
1426
1427                                 /*
1428                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1429                                  */
1430                                 for (k = 0; k < num_sregs; ++k) {
1431                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1432                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1433                                 }
1434
1435                                 /*
1436                                  * We can also run out of registers while processing sreg2 if sreg3 is
1437                                  * assigned to another hreg, so spill sreg3 now.
1438                                  */
1439                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1440                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1441                                 }
1442                                 continue;
1443                         }
1444
1445                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1446                                 if (is_global_ireg (sreg)) {
1447                                         int k;
1448                                         /* Argument already in hard reg, need to copy */
1449                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1450                                         insert_before_ins (bb, ins, copy);
1451                                         for (k = 0; k < num_sregs; ++k) {
1452                                                 if (k != j)
1453                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1454                                         }
1455                                 } else {
1456                                         val = rs->vassign [sreg];
1457                                         if (val == -1) {
1458                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1459                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1460                                         } else if (val < -1) {
1461                                                 /* FIXME: */
1462                                                 g_assert_not_reached ();
1463                                         } else {
1464                                                 /* Argument already in hard reg, need to copy */
1465                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1466                                                 int k;
1467
1468                                                 insert_before_ins (bb, ins, copy);
1469                                                 for (k = 0; k < num_sregs; ++k) {
1470                                                         if (k != j)
1471                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1472                                                 }
1473                                                 /*
1474                                                  * Prevent the dreg from being allocate to dest_sreg
1475                                                  * too, since it could force sreg1 to be allocated to
1476                                                  * the same reg on x86.
1477                                                  */
1478                                                 dreg_mask &= ~ (regmask (dest_sreg));
1479                                         }
1480                                 }
1481                         } else {
1482                                 gboolean need_spill = TRUE;
1483                                 gboolean need_assign = TRUE;
1484                                 int k;
1485
1486                                 dreg_mask &= ~ (regmask (dest_sreg));
1487                                 for (k = 0; k < num_sregs; ++k) {
1488                                         if (k != j)
1489                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1490                                 }
1491
1492                                 /*
1493                                  * First check if dreg is assigned to dest_sreg2, since we
1494                                  * can't spill a dreg.
1495                                  */
1496                                 if (spec [MONO_INST_DEST])
1497                                         val = rs->vassign [ins->dreg];
1498                                 else
1499                                         val = -1;
1500                                 if (val == dest_sreg && ins->dreg != sreg) {
1501                                         /*
1502                                          * the destination register is already assigned to
1503                                          * dest_sreg2: we need to allocate another register for it
1504                                          * and then copy from this to dest_sreg2.
1505                                          */
1506                                         int new_dest;
1507                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1508                                         g_assert (new_dest >= 0);
1509                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1510
1511                                         prev_dreg = ins->dreg;
1512                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1513                                         clob_dreg = ins->dreg;
1514                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1515                                         mono_regstate_free_int (rs, dest_sreg);
1516                                         need_spill = FALSE;
1517                                 }
1518
1519                                 if (is_global_ireg (sreg)) {
1520                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1521                                         insert_before_ins (bb, ins, copy);
1522                                         need_assign = FALSE;
1523                                 }
1524                                 else {
1525                                         val = rs->vassign [sreg];
1526                                         if (val == dest_sreg) {
1527                                                 /* sreg2 is already assigned to the correct register */
1528                                                 need_spill = FALSE;
1529                                         } else if (val < -1) {
1530                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1531                                         } else if (val >= 0) {
1532                                                 /* sreg2 already assigned to another register */
1533                                                 /*
1534                                                  * We couldn't emit a copy from val to dest_sreg2, because
1535                                                  * val might be spilled later while processing this
1536                                                  * instruction. So we spill sreg2 so it can be allocated to
1537                                                  * dest_sreg2.
1538                                                  */
1539                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1540                                         }
1541                                 }
1542
1543                                 if (need_spill) {
1544                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1545                                 }
1546
1547                                 if (need_assign) {
1548                                         if (rs->vassign [sreg] < -1) {
1549                                                 int spill;
1550
1551                                                 /* Need to emit a spill store */
1552                                                 spill = - rs->vassign [sreg] - 1;
1553                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1554                                         }
1555                                         /* force-set sreg2 */
1556                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1557                                 }
1558                         }
1559                         sregs [j] = dest_sreg;
1560                 }
1561                 mono_inst_set_src_registers (ins, sregs);
1562
1563                 /*
1564                  * TRACK DREG
1565                  */
1566                 bank = dreg_bank (spec);
1567                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1568                         prev_dreg = ins->dreg;
1569                 }
1570
1571                 if (spec_dest == 'b') {
1572                         /*
1573                          * The dest reg is read by the instruction, not written, so
1574                          * avoid allocating sreg1/sreg2 to the same reg.
1575                          */
1576                         if (dest_sregs [0] != -1)
1577                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1578                         for (j = 1; j < num_sregs; ++j) {
1579                                 if (dest_sregs [j] != -1)
1580                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1581                         }
1582
1583                         val = rs->vassign [ins->dreg];
1584                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1585                                 /* DREG is already allocated to a register needed for sreg1 */
1586                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1587                         }
1588                 }
1589
1590                 /*
1591                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1592                  * various complex situations.
1593                  */
1594                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1595                         guint32 dreg2, dest_dreg2;
1596
1597                         g_assert (is_soft_reg (ins->dreg, bank));
1598
1599                         if (dest_dreg != -1) {
1600                                 if (rs->vassign [ins->dreg] != dest_dreg)
1601                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1602
1603                                 dreg2 = ins->dreg + 1;
1604                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1605                                 if (dest_dreg2 != -1) {
1606                                         if (rs->vassign [dreg2] != dest_dreg2)
1607                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1608                                 }
1609                         }
1610                 }
1611
1612                 if (dreg_fixed_mask) {
1613                         g_assert (!bank);
1614                         if (is_global_ireg (ins->dreg)) {
1615                                 /*
1616                                  * The argument is already in a hard reg, but that reg is
1617                                  * not usable by this instruction, so allocate a new one.
1618                                  */
1619                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1620                                 if (val < 0)
1621                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1622                                 mono_regstate_free_int (rs, val);
1623                                 dest_dreg = val;
1624
1625                                 /* Fall through */
1626                         }
1627                         else
1628                                 dreg_mask &= dreg_fixed_mask;
1629                 }
1630
1631                 if (is_soft_reg (ins->dreg, bank)) {
1632                         val = rs->vassign [ins->dreg];
1633
1634                         if (val < 0) {
1635                                 int spill = 0;
1636                                 if (val < -1) {
1637                                         /* the register gets spilled after this inst */
1638                                         spill = -val -1;
1639                                 }
1640                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1641                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1642                                 if (spill)
1643                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1644                         }
1645
1646                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1647                         ins->dreg = val;
1648                 }
1649
1650                 /* Handle regpairs */
1651                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1652                         int reg2 = prev_dreg + 1;
1653
1654                         g_assert (!bank);
1655                         g_assert (prev_dreg > -1);
1656                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1657                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1658 #ifdef TARGET_X86
1659                         /* bug #80489 */
1660                         mask &= ~regmask (X86_ECX);
1661 #endif
1662                         val = rs->vassign [reg2];
1663                         if (val < 0) {
1664                                 int spill = 0;
1665                                 if (val < -1) {
1666                                         /* the register gets spilled after this inst */
1667                                         spill = -val -1;
1668                                 }
1669                                 val = mono_regstate_alloc_int (rs, mask);
1670                                 if (val < 0)
1671                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1672                                 if (spill)
1673                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1674                         }
1675                         else {
1676                                 if (! (mask & (regmask (val)))) {
1677                                         val = mono_regstate_alloc_int (rs, mask);
1678                                         if (val < 0)
1679                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1680
1681                                         /* Reallocate hreg to the correct register */
1682                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1683
1684                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1685                                 }
1686                         }
1687
1688                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1689                         assign_reg (cfg, rs, reg2, val, bank);
1690
1691                         dreg_high = val;
1692                         ins->backend.reg3 = val;
1693
1694                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1695                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1696                                 mono_regstate_free_int (rs, val);
1697                         }
1698                 }
1699
1700                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1701                         /*
1702                          * In theory, we could free up the hreg even if the vreg is alive,
1703                          * but branches inside bblocks force us to assign the same hreg
1704                          * to a vreg every time it is encountered.
1705                          */
1706                         int dreg = rs->vassign [prev_dreg];
1707                         g_assert (dreg >= 0);
1708                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1709                         if (G_UNLIKELY (bank))
1710                                 mono_regstate_free_general (rs, dreg, bank);
1711                         else
1712                                 mono_regstate_free_int (rs, dreg);
1713                         rs->vassign [prev_dreg] = -1;
1714                 }
1715
1716                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1717                         /* this instruction only outputs to dest_dreg, need to copy */
1718                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1719                         ins->dreg = dest_dreg;
1720
1721                         if (G_UNLIKELY (bank)) {
1722                                 /* the register we need to free up may be used in another logical regbank
1723                                  * so do a translate just in case.
1724                                  */
1725                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1726                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1727                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1728                         }
1729                         else {
1730                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1731                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1732                         }
1733                 }
1734
1735                 if (spec_dest == 'b') {
1736                         /*
1737                          * The dest reg is read by the instruction, not written, so
1738                          * avoid allocating sreg1/sreg2 to the same reg.
1739                          */
1740                         for (j = 0; j < num_sregs; ++j)
1741                                 if (!sreg_bank (j, spec))
1742                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1743                 }
1744
1745                 /*
1746                  * TRACK CLOBBERING
1747                  */
1748                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1749                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1750                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1751                 }
1752
1753                 if (spec [MONO_INST_CLOB] == 'c') {
1754                         int j, s, dreg, dreg2, cur_bank;
1755                         guint64 clob_mask;
1756
1757                         clob_mask = MONO_ARCH_CALLEE_REGS;
1758
1759                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1760                                 /*
1761                                  * Need to avoid spilling the dreg since the dreg is not really
1762                                  * clobbered by the call.
1763                                  */
1764                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1765                                         dreg = rs->vassign [prev_dreg];
1766                                 else
1767                                         dreg = -1;
1768
1769                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1770                                         dreg2 = rs->vassign [prev_dreg + 1];
1771                                 else
1772                                         dreg2 = -1;
1773
1774                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1775                                         s = regmask (j);
1776                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1777                                                 if ((j != dreg) && (j != dreg2))
1778                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1779                                                 else if (rs->isymbolic [j])
1780                                                         /* The hreg is assigned to the dreg of this instruction */
1781                                                         rs->vassign [rs->isymbolic [j]] = -1;
1782                                                 mono_regstate_free_int (rs, j);
1783                                         }
1784                                 }
1785                         }
1786
1787                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1788                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1789                                         clob_mask = regbank_callee_regs [cur_bank];
1790                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1791                                                 dreg = rs->vassign [prev_dreg];
1792                                         else
1793                                                 dreg = -1;
1794
1795                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1796
1797                                                 /* we are looping though the banks in the outer loop
1798                                                  * so, we don't need to deal with mirrored hregs
1799                                                  * because we will get them in one of the other bank passes.
1800                                                  */
1801                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1802                                                         continue;
1803
1804                                                 s = regmask (j);
1805                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1806                                                         if (j != dreg)
1807                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1808                                                         else if (rs->symbolic [cur_bank] [j])
1809                                                                 /* The hreg is assigned to the dreg of this instruction */
1810                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1811                                                         mono_regstate_free_general (rs, j, cur_bank);
1812                                                 }
1813                                         }
1814                                 }
1815                         }
1816                 }
1817
1818                 /*
1819                  * TRACK ARGUMENT REGS
1820                  */
1821                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1822                         MonoCallInst *call = (MonoCallInst*)ins;
1823                         GSList *list;
1824
1825                         /*
1826                          * This needs to be done before assigning sreg1, so sreg1 will
1827                          * not be assigned one of the argument regs.
1828                          */
1829
1830                         /*
1831                          * Assign all registers in call->out_reg_args to the proper
1832                          * argument registers.
1833                          */
1834
1835                         list = call->out_ireg_args;
1836                         if (list) {
1837                                 while (list) {
1838                                         guint32 regpair;
1839                                         int reg, hreg;
1840
1841                                         regpair = (guint32)(gssize)(list->data);
1842                                         hreg = regpair >> 24;
1843                                         reg = regpair & 0xffffff;
1844
1845                                         assign_reg (cfg, rs, reg, hreg, 0);
1846
1847                                         sreg_masks [0] &= ~(regmask (hreg));
1848
1849                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1850
1851                                         list = g_slist_next (list);
1852                                 }
1853                         }
1854
1855                         list = call->out_freg_args;
1856                         if (list) {
1857                                 while (list) {
1858                                         guint32 regpair;
1859                                         int reg, hreg;
1860
1861                                         regpair = (guint32)(gssize)(list->data);
1862                                         hreg = regpair >> 24;
1863                                         reg = regpair & 0xffffff;
1864
1865                                         assign_reg (cfg, rs, reg, hreg, 1);
1866
1867                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1868
1869                                         list = g_slist_next (list);
1870                                 }
1871                         }
1872                 }
1873
1874                 /*
1875                  * TRACK SREG1
1876                  */
1877                 bank = sreg1_bank (spec);
1878                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1879                         int sreg1 = sregs [0];
1880                         int dest_sreg1 = dest_sregs [0];
1881
1882                         g_assert (is_soft_reg (sreg1, bank));
1883
1884                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1885                         if (dest_sreg1 != -1)
1886                                 g_assert (dest_sreg1 == ins->dreg);
1887                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1888                         g_assert (val >= 0);
1889
1890                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1891                                 // FIXME:
1892                                 g_assert_not_reached ();
1893
1894                         assign_reg (cfg, rs, sreg1, val, bank);
1895
1896                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1897
1898                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1899                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1900                         g_assert (val >= 0);
1901
1902                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1903                                 // FIXME:
1904                                 g_assert_not_reached ();
1905
1906                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1907
1908                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1909
1910                         /* Skip rest of this section */
1911                         dest_sregs [0] = -1;
1912                 }
1913
1914                 if (sreg_fixed_masks [0]) {
1915                         g_assert (!bank);
1916                         if (is_global_ireg (sregs [0])) {
1917                                 /*
1918                                  * The argument is already in a hard reg, but that reg is
1919                                  * not usable by this instruction, so allocate a new one.
1920                                  */
1921                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1922                                 if (val < 0)
1923                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1924                                 mono_regstate_free_int (rs, val);
1925                                 dest_sregs [0] = val;
1926
1927                                 /* Fall through to the dest_sreg1 != -1 case */
1928                         }
1929                         else
1930                                 sreg_masks [0] &= sreg_fixed_masks [0];
1931                 }
1932
1933                 if (dest_sregs [0] != -1) {
1934                         sreg_masks [0] = regmask (dest_sregs [0]);
1935
1936                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1937                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1938                         }
1939                         if (is_global_ireg (sregs [0])) {
1940                                 /* The argument is already in a hard reg, need to copy */
1941                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1942                                 insert_before_ins (bb, ins, copy);
1943                                 sregs [0] = dest_sregs [0];
1944                         }
1945                 }
1946
1947                 if (is_soft_reg (sregs [0], bank)) {
1948                         val = rs->vassign [sregs [0]];
1949                         prev_sregs [0] = sregs [0];
1950                         if (val < 0) {
1951                                 int spill = 0;
1952                                 if (val < -1) {
1953                                         /* the register gets spilled after this inst */
1954                                         spill = -val -1;
1955                                 }
1956
1957                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1958                                         /*
1959                                          * Allocate the same hreg to sreg1 as well so the
1960                                          * peephole can get rid of the move.
1961                                          */
1962                                         sreg_masks [0] = regmask (ins->dreg);
1963                                 }
1964
1965                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1966                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1967                                         sreg_masks [0] = regmask (ins->dreg);
1968
1969                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1970                                 assign_reg (cfg, rs, sregs [0], val, bank);
1971                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1972
1973                                 if (spill) {
1974                                         /*
1975                                          * Need to insert before the instruction since it can
1976                                          * overwrite sreg1.
1977                                          */
1978                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1979                                 }
1980                         }
1981                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1982                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1983                                 insert_before_ins (bb, ins, copy);
1984                                 for (j = 1; j < num_sregs; ++j)
1985                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1986                                 val = dest_sregs [0];
1987                         }
1988
1989                         sregs [0] = val;
1990                 }
1991                 else {
1992                         prev_sregs [0] = -1;
1993                 }
1994                 mono_inst_set_src_registers (ins, sregs);
1995
1996                 for (j = 1; j < num_sregs; ++j)
1997                         sreg_masks [j] &= ~(regmask (sregs [0]));
1998
1999                 /* Handle the case when sreg1 is a regpair but dreg is not */
2000                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2001                         int reg2 = prev_sregs [0] + 1;
2002
2003                         g_assert (!bank);
2004                         g_assert (prev_sregs [0] > -1);
2005                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2006                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2007                         val = rs->vassign [reg2];
2008                         if (val < 0) {
2009                                 int spill = 0;
2010                                 if (val < -1) {
2011                                         /* the register gets spilled after this inst */
2012                                         spill = -val -1;
2013                                 }
2014                                 val = mono_regstate_alloc_int (rs, mask);
2015                                 if (val < 0)
2016                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2017                                 if (spill)
2018                                         g_assert_not_reached ();
2019                         }
2020                         else {
2021                                 if (! (mask & (regmask (val)))) {
2022                                         /* The vreg is already allocated to a wrong hreg */
2023                                         /* FIXME: */
2024                                         g_assert_not_reached ();
2025 #if 0
2026                                         val = mono_regstate_alloc_int (rs, mask);
2027                                         if (val < 0)
2028                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2029
2030                                         /* Reallocate hreg to the correct register */
2031                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2032
2033                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2034 #endif
2035                                 }
2036                         }
2037
2038                         sreg1_high = val;
2039                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2040                         assign_reg (cfg, rs, reg2, val, bank);
2041                 }
2042
2043                 /* Handle dreg==sreg1 */
2044                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2045                         MonoInst *sreg2_copy = NULL;
2046                         MonoInst *copy;
2047                         int bank = reg_bank (spec_src1);
2048
2049                         if (ins->dreg == sregs [1]) {
2050                                 /*
2051                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2052                                  * register for it.
2053                                  */
2054                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2055
2056                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2057                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2058                                 prev_sregs [1] = sregs [1] = reg2;
2059
2060                                 if (G_UNLIKELY (bank))
2061                                         mono_regstate_free_general (rs, reg2, bank);
2062                                 else
2063                                         mono_regstate_free_int (rs, reg2);
2064                         }
2065
2066                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2067                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2068                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2069                                         /* FIXME: */
2070                                         g_assert_not_reached ();
2071
2072                                 /*
2073                                  * sreg1 and dest are already allocated to the same regpair by the
2074                                  * SREG1 allocation code.
2075                                  */
2076                                 g_assert (sregs [0] == ins->dreg);
2077                                 g_assert (dreg_high == sreg1_high);
2078                         }
2079
2080                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2081                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2082                         insert_before_ins (bb, ins, copy);
2083
2084                         if (sreg2_copy)
2085                                 insert_before_ins (bb, copy, sreg2_copy);
2086
2087                         /*
2088                          * Need to prevent sreg2 to be allocated to sreg1, since that
2089                          * would screw up the previous copy.
2090                          */
2091                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2092                         /* we set sreg1 to dest as well */
2093                         prev_sregs [0] = sregs [0] = ins->dreg;
2094                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2095                 }
2096                 mono_inst_set_src_registers (ins, sregs);
2097
2098                 /*
2099                  * TRACK SREG2, 3, ...
2100                  */
2101                 for (j = 1; j < num_sregs; ++j) {
2102                         int k;
2103
2104                         bank = sreg_bank (j, spec);
2105                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2106                                 g_assert_not_reached ();
2107
2108                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2109                                 /*
2110                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2111                                  * allocating it to the fixed reg.
2112                                  */
2113                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2114                                 insert_before_ins (bb, ins, copy);
2115                                 sregs [j] = dest_sregs [j];
2116                         } else if (is_soft_reg (sregs [j], bank)) {
2117                                 val = rs->vassign [sregs [j]];
2118
2119                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2120                                         /*
2121                                          * The sreg is already allocated to a hreg, but not to the fixed
2122                                          * reg required by the instruction. Spill the sreg, so it can be
2123                                          * allocated to the fixed reg by the code below.
2124                                          */
2125                                         /* Currently, this code should only be hit for CAS */
2126                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2127                                         val = rs->vassign [sregs [j]];
2128                                 }
2129
2130                                 if (val < 0) {
2131                                         int spill = 0;
2132                                         if (val < -1) {
2133                                                 /* the register gets spilled after this inst */
2134                                                 spill = -val -1;
2135                                         }
2136                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2137                                         assign_reg (cfg, rs, sregs [j], val, bank);
2138                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2139                                         if (spill) {
2140                                                 /*
2141                                                  * Need to insert before the instruction since it can
2142                                                  * overwrite sreg2.
2143                                                  */
2144                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2145                                         }
2146                                 }
2147                                 sregs [j] = val;
2148                                 for (k = j + 1; k < num_sregs; ++k)
2149                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2150                         }
2151                         else {
2152                                 prev_sregs [j] = -1;
2153                         }
2154                 }
2155                 mono_inst_set_src_registers (ins, sregs);
2156
2157                 /* Sanity check */
2158                 /* Do this only for CAS for now */
2159                 for (j = 1; j < num_sregs; ++j) {
2160                         int sreg = sregs [j];
2161                         int dest_sreg = dest_sregs [j];
2162
2163                         if (j == 2 && dest_sreg != -1) {
2164                                 int k;
2165
2166                                 g_assert (sreg == dest_sreg);
2167
2168                                 for (k = 0; k < num_sregs; ++k) {
2169                                         if (k != j)
2170                                                 g_assert (sregs [k] != dest_sreg);
2171                                 }
2172                         }
2173                 }
2174
2175                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2176                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2177                         mono_regstate_free_int (rs, ins->sreg1);
2178                 }
2179                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2180                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2181                         mono_regstate_free_int (rs, ins->sreg2);
2182                 }*/
2183
2184                 DEBUG (mono_print_ins_index (i, ins));
2185         }
2186
2187         // FIXME: Set MAX_FREGS to 8
2188         // FIXME: Optimize generated code
2189 #if MONO_ARCH_USE_FPSTACK
2190         /*
2191          * Make a forward pass over the code, simulating the fp stack, making sure the
2192          * arguments required by the fp opcodes are at the top of the stack.
2193          */
2194         if (has_fp) {
2195                 MonoInst *prev = NULL;
2196                 MonoInst *fxch;
2197                 int tmp;
2198
2199                 g_assert (num_sregs <= 2);
2200
2201                 for (ins = bb->code; ins; ins = ins->next) {
2202                         spec = ins_get_spec (ins->opcode);
2203
2204                         DEBUG (printf ("processing:"));
2205                         DEBUG (mono_print_ins_index (0, ins));
2206
2207                         if (ins->opcode == OP_FMOVE) {
2208                                 /* Do it by renaming the source to the destination on the stack */
2209                                 // FIXME: Is this correct ?
2210                                 for (i = 0; i < sp; ++i)
2211                                         if (fpstack [i] == ins->sreg1)
2212                                                 fpstack [i] = ins->dreg;
2213                                 prev = ins;
2214                                 continue;
2215                         }
2216
2217                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2218                                 /* Arg1 must be in %st(1) */
2219                                 g_assert (prev);
2220
2221                                 i = 0;
2222                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2223                                         i ++;
2224                                 g_assert (i < sp);
2225
2226                                 if (sp - 1 - i > 0) {
2227                                         /* First move it to %st(0) */
2228                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2229
2230                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2231                                         fxch->inst_imm = sp - 1 - i;
2232
2233                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2234                                         prev = fxch;
2235
2236                                         tmp = fpstack [sp - 1];
2237                                         fpstack [sp - 1] = fpstack [i];
2238                                         fpstack [i] = tmp;
2239                                 }
2240
2241                                 /* Then move it to %st(1) */
2242                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2243
2244                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2245                                 fxch->inst_imm = 1;
2246
2247                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2248                                 prev = fxch;
2249
2250                                 tmp = fpstack [sp - 1];
2251                                 fpstack [sp - 1] = fpstack [sp - 2];
2252                                 fpstack [sp - 2] = tmp;
2253                         }
2254
2255                         if (sreg2_is_fp (spec)) {
2256                                 g_assert (sp > 0);
2257
2258                                 if (fpstack [sp - 1] != ins->sreg2) {
2259                                         g_assert (prev);
2260
2261                                         i = 0;
2262                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2263                                                 i ++;
2264                                         g_assert (i < sp);
2265
2266                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2267
2268                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2269                                         fxch->inst_imm = sp - 1 - i;
2270
2271                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2272                                         prev = fxch;
2273
2274                                         tmp = fpstack [sp - 1];
2275                                         fpstack [sp - 1] = fpstack [i];
2276                                         fpstack [i] = tmp;
2277                                 }
2278
2279                                 sp --;
2280                         }
2281
2282                         if (sreg1_is_fp (spec)) {
2283                                 g_assert (sp > 0);
2284
2285                                 if (fpstack [sp - 1] != ins->sreg1) {
2286                                         g_assert (prev);
2287
2288                                         i = 0;
2289                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2290                                                 i ++;
2291                                         g_assert (i < sp);
2292
2293                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2294
2295                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2296                                         fxch->inst_imm = sp - 1 - i;
2297
2298                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2299                                         prev = fxch;
2300
2301                                         tmp = fpstack [sp - 1];
2302                                         fpstack [sp - 1] = fpstack [i];
2303                                         fpstack [i] = tmp;
2304                                 }
2305
2306                                 sp --;
2307                         }
2308
2309                         if (dreg_is_fp (spec)) {
2310                                 g_assert (sp < 8);
2311                                 fpstack [sp ++] = ins->dreg;
2312                         }
2313
2314                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2315                                 printf ("\t[");
2316                                 for (i = 0; i < sp; ++i)
2317                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2318                                 printf ("]\n");
2319                         }
2320
2321                         prev = ins;
2322                 }
2323
2324                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2325                         /* Remove remaining items from the fp stack */
2326                         /*
2327                          * These can remain for example as a result of a dead fmove like in
2328                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2329                          */
2330                         while (sp) {
2331                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2332                                 mono_add_ins_to_end (bb, ins);
2333                                 sp --;
2334                         }
2335                 }
2336         }
2337 #endif
2338 }
2339
2340 CompRelation
2341 mono_opcode_to_cond (int opcode)
2342 {
2343         switch (opcode) {
2344         case OP_CEQ:
2345         case OP_IBEQ:
2346         case OP_ICEQ:
2347         case OP_LBEQ:
2348         case OP_LCEQ:
2349         case OP_FBEQ:
2350         case OP_FCEQ:
2351         case OP_COND_EXC_EQ:
2352         case OP_COND_EXC_IEQ:
2353         case OP_CMOV_IEQ:
2354         case OP_CMOV_LEQ:
2355                 return CMP_EQ;
2356         case OP_FCNEQ:
2357         case OP_ICNEQ:
2358         case OP_IBNE_UN:
2359         case OP_LBNE_UN:
2360         case OP_FBNE_UN:
2361         case OP_COND_EXC_NE_UN:
2362         case OP_COND_EXC_INE_UN:
2363         case OP_CMOV_INE_UN:
2364         case OP_CMOV_LNE_UN:
2365                 return CMP_NE;
2366         case OP_FCLE:
2367         case OP_ICLE:
2368         case OP_IBLE:
2369         case OP_LBLE:
2370         case OP_FBLE:
2371         case OP_CMOV_ILE:
2372         case OP_CMOV_LLE:
2373                 return CMP_LE;
2374         case OP_FCGE:
2375         case OP_ICGE:
2376         case OP_IBGE:
2377         case OP_LBGE:
2378         case OP_FBGE:
2379         case OP_CMOV_IGE:
2380         case OP_CMOV_LGE:
2381                 return CMP_GE;
2382         case OP_CLT:
2383         case OP_IBLT:
2384         case OP_ICLT:
2385         case OP_LBLT:
2386         case OP_LCLT:
2387         case OP_FBLT:
2388         case OP_FCLT:
2389         case OP_COND_EXC_LT:
2390         case OP_COND_EXC_ILT:
2391         case OP_CMOV_ILT:
2392         case OP_CMOV_LLT:
2393                 return CMP_LT;
2394         case OP_CGT:
2395         case OP_IBGT:
2396         case OP_ICGT:
2397         case OP_LBGT:
2398         case OP_LCGT:
2399         case OP_FBGT:
2400         case OP_FCGT:
2401         case OP_COND_EXC_GT:
2402         case OP_COND_EXC_IGT:
2403         case OP_CMOV_IGT:
2404         case OP_CMOV_LGT:
2405                 return CMP_GT;
2406
2407         case OP_ICLE_UN:
2408         case OP_IBLE_UN:
2409         case OP_LBLE_UN:
2410         case OP_FBLE_UN:
2411         case OP_COND_EXC_LE_UN:
2412         case OP_COND_EXC_ILE_UN:
2413         case OP_CMOV_ILE_UN:
2414         case OP_CMOV_LLE_UN:
2415                 return CMP_LE_UN;
2416
2417         case OP_ICGE_UN:
2418         case OP_IBGE_UN:
2419         case OP_LBGE_UN:
2420         case OP_FBGE_UN:
2421         case OP_CMOV_IGE_UN:
2422         case OP_CMOV_LGE_UN:
2423                 return CMP_GE_UN;
2424         case OP_CLT_UN:
2425         case OP_IBLT_UN:
2426         case OP_ICLT_UN:
2427         case OP_LBLT_UN:
2428         case OP_LCLT_UN:
2429         case OP_FBLT_UN:
2430         case OP_FCLT_UN:
2431         case OP_COND_EXC_LT_UN:
2432         case OP_COND_EXC_ILT_UN:
2433         case OP_CMOV_ILT_UN:
2434         case OP_CMOV_LLT_UN:
2435                 return CMP_LT_UN;
2436         case OP_CGT_UN:
2437         case OP_IBGT_UN:
2438         case OP_ICGT_UN:
2439         case OP_LBGT_UN:
2440         case OP_LCGT_UN:
2441         case OP_FCGT_UN:
2442         case OP_FBGT_UN:
2443         case OP_COND_EXC_GT_UN:
2444         case OP_COND_EXC_IGT_UN:
2445         case OP_CMOV_IGT_UN:
2446         case OP_CMOV_LGT_UN:
2447                 return CMP_GT_UN;
2448         default:
2449                 printf ("%s\n", mono_inst_name (opcode));
2450                 g_assert_not_reached ();
2451                 return 0;
2452         }
2453 }
2454
2455 CompRelation
2456 mono_negate_cond (CompRelation cond)
2457 {
2458         switch (cond) {
2459         case CMP_EQ:
2460                 return CMP_NE;
2461         case CMP_NE:
2462                 return CMP_EQ;
2463         case CMP_LE:
2464                 return CMP_GT;
2465         case CMP_GE:
2466                 return CMP_LT;
2467         case CMP_LT:
2468                 return CMP_GE;
2469         case CMP_GT:
2470                 return CMP_LE;
2471         case CMP_LE_UN:
2472                 return CMP_GT_UN;
2473         case CMP_GE_UN:
2474                 return CMP_LT_UN;
2475         case CMP_LT_UN:
2476                 return CMP_GE_UN;
2477         case CMP_GT_UN:
2478                 return CMP_LE_UN;
2479         default:
2480                 g_assert_not_reached ();
2481         }
2482 }
2483
2484 CompType
2485 mono_opcode_to_type (int opcode, int cmp_opcode)
2486 {
2487         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2488                 return CMP_TYPE_L;
2489         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2490                 return CMP_TYPE_I;
2491         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2492                 return CMP_TYPE_I;
2493         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2494                 return CMP_TYPE_L;
2495         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2496                 return CMP_TYPE_L;
2497         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2498                 return CMP_TYPE_F;
2499         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2500                 return CMP_TYPE_F;
2501         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2502                 return CMP_TYPE_I;
2503         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2504                 switch (cmp_opcode) {
2505                 case OP_ICOMPARE:
2506                 case OP_ICOMPARE_IMM:
2507                         return CMP_TYPE_I;
2508                 default:
2509                         return CMP_TYPE_L;
2510                 }
2511         } else {
2512                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2513                 return 0;
2514         }
2515 }
2516
2517 #endif /* DISABLE_JIT */
2518
2519 gboolean
2520 mono_is_regsize_var (MonoType *t)
2521 {
2522         if (t->byref)
2523                 return TRUE;
2524         t = mono_type_get_underlying_type (t);
2525         switch (t->type) {
2526         case MONO_TYPE_BOOLEAN:
2527         case MONO_TYPE_CHAR:
2528         case MONO_TYPE_I1:
2529         case MONO_TYPE_U1:
2530         case MONO_TYPE_I2:
2531         case MONO_TYPE_U2:
2532         case MONO_TYPE_I4:
2533         case MONO_TYPE_U4:
2534         case MONO_TYPE_I:
2535         case MONO_TYPE_U:
2536         case MONO_TYPE_PTR:
2537         case MONO_TYPE_FNPTR:
2538 #if SIZEOF_REGISTER == 8
2539         case MONO_TYPE_I8:
2540         case MONO_TYPE_U8:
2541 #endif
2542                 return TRUE;
2543         case MONO_TYPE_OBJECT:
2544         case MONO_TYPE_STRING:
2545         case MONO_TYPE_CLASS:
2546         case MONO_TYPE_SZARRAY:
2547         case MONO_TYPE_ARRAY:
2548                 return TRUE;
2549         case MONO_TYPE_GENERICINST:
2550                 if (!mono_type_generic_inst_is_valuetype (t))
2551                         return TRUE;
2552                 return FALSE;
2553         case MONO_TYPE_VALUETYPE:
2554                 return FALSE;
2555         default:
2556                 return FALSE;
2557         }
2558 }
2559
2560 #ifndef DISABLE_JIT
2561
2562 /*
2563  * mono_peephole_ins:
2564  *
2565  *   Perform some architecture independent peephole optimizations.
2566  */
2567 void
2568 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2569 {
2570         MonoInst *last_ins = ins->prev;
2571
2572         switch (ins->opcode) {
2573         case OP_MUL_IMM:
2574                 /* remove unnecessary multiplication with 1 */
2575                 if (ins->inst_imm == 1) {
2576                         if (ins->dreg != ins->sreg1)
2577                                 ins->opcode = OP_MOVE;
2578                         else
2579                                 MONO_DELETE_INS (bb, ins);
2580                 }
2581                 break;
2582         case OP_LOAD_MEMBASE:
2583         case OP_LOADI4_MEMBASE:
2584                 /*
2585                  * Note: if reg1 = reg2 the load op is removed
2586                  *
2587                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2588                  * OP_LOAD_MEMBASE offset(basereg), reg2
2589                  * -->
2590                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2591                  * OP_MOVE reg1, reg2
2592                  */
2593                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2594                         last_ins = last_ins->prev;
2595                 if (last_ins &&
2596                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2597                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2598                         ins->inst_basereg == last_ins->inst_destbasereg &&
2599                         ins->inst_offset == last_ins->inst_offset) {
2600                         if (ins->dreg == last_ins->sreg1) {
2601                                 MONO_DELETE_INS (bb, ins);
2602                                 break;
2603                         } else {
2604                                 ins->opcode = OP_MOVE;
2605                                 ins->sreg1 = last_ins->sreg1;
2606                         }
2607
2608                         /*
2609                          * Note: reg1 must be different from the basereg in the second load
2610                          * Note: if reg1 = reg2 is equal then second load is removed
2611                          *
2612                          * OP_LOAD_MEMBASE offset(basereg), reg1
2613                          * OP_LOAD_MEMBASE offset(basereg), reg2
2614                          * -->
2615                          * OP_LOAD_MEMBASE offset(basereg), reg1
2616                          * OP_MOVE reg1, reg2
2617                          */
2618                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2619                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2620                           ins->inst_basereg != last_ins->dreg &&
2621                           ins->inst_basereg == last_ins->inst_basereg &&
2622                           ins->inst_offset == last_ins->inst_offset) {
2623
2624                         if (ins->dreg == last_ins->dreg) {
2625                                 MONO_DELETE_INS (bb, ins);
2626                         } else {
2627                                 ins->opcode = OP_MOVE;
2628                                 ins->sreg1 = last_ins->dreg;
2629                         }
2630
2631                         //g_assert_not_reached ();
2632
2633 #if 0
2634                         /*
2635                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2636                          * OP_LOAD_MEMBASE offset(basereg), reg
2637                          * -->
2638                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2639                          * OP_ICONST reg, imm
2640                          */
2641                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2642                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2643                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2644                                    ins->inst_offset == last_ins->inst_offset) {
2645                         ins->opcode = OP_ICONST;
2646                         ins->inst_c0 = last_ins->inst_imm;
2647                         g_assert_not_reached (); // check this rule
2648 #endif
2649                 }
2650                 break;
2651         case OP_LOADI1_MEMBASE:
2652         case OP_LOADU1_MEMBASE:
2653                 /*
2654                  * Note: if reg1 = reg2 the load op is removed
2655                  *
2656                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2657                  * OP_LOAD_MEMBASE offset(basereg), reg2
2658                  * -->
2659                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2660                  * OP_MOVE reg1, reg2
2661                  */
2662                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2663                         ins->inst_basereg == last_ins->inst_destbasereg &&
2664                         ins->inst_offset == last_ins->inst_offset) {
2665                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2666                         ins->sreg1 = last_ins->sreg1;
2667                 }
2668                 break;
2669         case OP_LOADI2_MEMBASE:
2670         case OP_LOADU2_MEMBASE:
2671                 /*
2672                  * Note: if reg1 = reg2 the load op is removed
2673                  *
2674                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2675                  * OP_LOAD_MEMBASE offset(basereg), reg2
2676                  * -->
2677                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2678                  * OP_MOVE reg1, reg2
2679                  */
2680                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2681                         ins->inst_basereg == last_ins->inst_destbasereg &&
2682                         ins->inst_offset == last_ins->inst_offset) {
2683 #if SIZEOF_REGISTER == 8
2684                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2685 #else
2686                         /* The definition of OP_PCONV_TO_U2 is wrong */
2687                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2688 #endif
2689                         ins->sreg1 = last_ins->sreg1;
2690                 }
2691                 break;
2692         case OP_MOVE:
2693         case OP_FMOVE:
2694                 /*
2695                  * Removes:
2696                  *
2697                  * OP_MOVE reg, reg
2698                  */
2699                 if (ins->dreg == ins->sreg1) {
2700                         MONO_DELETE_INS (bb, ins);
2701                         break;
2702                 }
2703                 /*
2704                  * Removes:
2705                  *
2706                  * OP_MOVE sreg, dreg
2707                  * OP_MOVE dreg, sreg
2708                  */
2709                 if (last_ins && last_ins->opcode == ins->opcode &&
2710                         ins->sreg1 == last_ins->dreg &&
2711                         ins->dreg == last_ins->sreg1) {
2712                         MONO_DELETE_INS (bb, ins);
2713                 }
2714                 break;
2715         case OP_NOP:
2716                 MONO_DELETE_INS (bb, ins);
2717                 break;
2718         }
2719 }
2720
2721 int
2722 mini_exception_id_by_name (const char *name)
2723 {
2724         if (strcmp (name, "IndexOutOfRangeException") == 0)
2725                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2726         if (strcmp (name, "OverflowException") == 0)
2727                 return MONO_EXC_OVERFLOW;
2728         if (strcmp (name, "ArithmeticException") == 0)
2729                 return MONO_EXC_ARITHMETIC;
2730         if (strcmp (name, "DivideByZeroException") == 0)
2731                 return MONO_EXC_DIVIDE_BY_ZERO;
2732         if (strcmp (name, "InvalidCastException") == 0)
2733                 return MONO_EXC_INVALID_CAST;
2734         if (strcmp (name, "NullReferenceException") == 0)
2735                 return MONO_EXC_NULL_REF;
2736         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2737                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2738         if (strcmp (name, "ArgumentException") == 0)
2739                 return MONO_EXC_ARGUMENT;
2740         g_error ("Unknown intrinsic exception %s\n", name);
2741         return -1;
2742 }
2743
2744 #endif /* DISABLE_JIT */