mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583                 printf (" [%d]", (int)ins->inst_imm);
 584                 break;
 585         case OP_ADD_IMM:
 586         case OP_LADD_IMM:
 587                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 588                 break;
 589         case OP_I8CONST:
 590                 printf (" [%lld]", (long long)ins->inst_l);
 591                 break;
 592         case OP_R8CONST:
 593                 printf (" [%f]", *(double*)ins->inst_p0);
 594                 break;
 595         case OP_R4CONST:
 596                 printf (" [%f]", *(float*)ins->inst_p0);
 597                 break;
 598         case OP_CALL:
 599         case OP_CALL_MEMBASE:
 600         case OP_CALL_REG:
 601         case OP_FCALL:
 602         case OP_LCALL:
 603         case OP_VCALL:
 604         case OP_VCALL_REG:
 605         case OP_VCALL_MEMBASE:
 606         case OP_VCALL2:
 607         case OP_VCALL2_REG:
 608         case OP_VCALL2_MEMBASE:
 609         case OP_VOIDCALL:
 610         case OP_VOIDCALL_MEMBASE:
 611         case OP_TAILCALL: {
 612                 MonoCallInst *call = (MonoCallInst*)ins;
 613                 GSList *list;
 614
 615                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 616                         /*
 617                          * These are lowered opcodes, but they are in the .md files since the old
 618                          * JIT passes them to backends.
 619                          */
 620                         if (ins->dreg != -1)
 621                                 printf (" R%d <-", ins->dreg);
 622                 }
 623
 624                 if (call->method) {
 625                         char *full_name = mono_method_full_name (call->method, TRUE);
 626                         printf (" [%s]", full_name);
 627                         g_free (full_name);
 628                 } else if (call->fptr_is_patch) {
 629                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 630
 631                         printf (" ");
 632                         mono_print_ji (ji);
 633                 } else if (call->fptr) {
 634                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 635                         if (info)
 636                                 printf (" [%s]", info->name);
 637                 }
 638
 639                 list = call->out_ireg_args;
 640                 while (list) {
 641                         guint32 regpair;
 642                         int reg, hreg;
 643
 644                         regpair = (guint32)(gssize)(list->data);
 645                         hreg = regpair >> 24;
 646                         reg = regpair & 0xffffff;
 647
 648                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 649
 650                         list = g_slist_next (list);
 651                 }
 652                 break;
 653         }
 654         case OP_BR:
 655         case OP_CALL_HANDLER:
 656                 printf (" [B%d]", ins->inst_target_bb->block_num);
 657                 break;
 658         case OP_IBNE_UN:
 659         case OP_IBEQ:
 660         case OP_IBLT:
 661         case OP_IBLT_UN:
 662         case OP_IBGT:
 663         case OP_IBGT_UN:
 664         case OP_IBGE:
 665         case OP_IBGE_UN:
 666         case OP_IBLE:
 667         case OP_IBLE_UN:
 668         case OP_LBNE_UN:
 669         case OP_LBEQ:
 670         case OP_LBLT:
 671         case OP_LBLT_UN:
 672         case OP_LBGT:
 673         case OP_LBGT_UN:
 674         case OP_LBGE:
 675         case OP_LBGE_UN:
 676         case OP_LBLE:
 677         case OP_LBLE_UN:
 678                 if (!ins->inst_false_bb)
 679                         printf (" [B%d]", ins->inst_true_bb->block_num);
 680                 else
 681                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 682                 break;
 683         case OP_LIVERANGE_START:
 684         case OP_LIVERANGE_END:
 685         case OP_GC_LIVENESS_DEF:
 686         case OP_GC_LIVENESS_USE:
 687                 printf (" R%d", (int)ins->inst_c1);
 688                 break;
 689         case OP_SEQ_POINT:
 690                 printf (" il: %x", (int)ins->inst_imm);
 691                 break;
 692         default:
 693                 break;
 694         }
 695
 696         if (spec [MONO_INST_CLOB])
 697                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 698         printf ("\n");
 699 }
 700
 701 static void
 702 print_regtrack (RegTrack *t, int num)
 703 {
 704         int i;
 705         char buf [32];
 706         const char *r;
 707
 708         for (i = 0; i < num; ++i) {
 709                 if (!t [i].born_in)
 710                         continue;
 711                 if (i >= MONO_MAX_IREGS) {
 712                         g_snprintf (buf, sizeof(buf), "R%d", i);
 713                         r = buf;
 714                 } else
 715                         r = mono_arch_regname (i);
 716                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 717         }
 718 }
 719 #else
 720
 721 void
 722 mono_print_ji (const MonoJumpInfo *ji)
 723 {
 724 }
 725
 726 void
 727 mono_print_ins_index (int i, MonoInst *ins)
 728 {
 729 }
 730 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 731
 732 void
 733 mono_print_ins (MonoInst *ins)
 734 {
 735         mono_print_ins_index (-1, ins);
 736 }
 737
 738 static inline void
 739 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 740 {
 741         /*
 742          * If this function is called multiple times, the new instructions are inserted
 743          * in the proper order.
 744          */
 745         mono_bblock_insert_before_ins (bb, ins, to_insert);
 746 }
 747
 748 static inline void
 749 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 750 {
 751         /*
 752          * If this function is called multiple times, the new instructions are inserted in
 753          * proper order.
 754          */
 755         mono_bblock_insert_after_ins (bb, *last, to_insert);
 756
 757         *last = to_insert;
 758 }
 759
 760 static inline int
 761 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 762 {
 763         if (vreg_is_ref (cfg, reg))
 764                 return MONO_REG_INT_REF;
 765         else if (vreg_is_mp (cfg, reg))
 766                 return MONO_REG_INT_MP;
 767         else
 768                 return bank;
 769 }
 770
 771 /*
 772  * Force the spilling of the variable in the symbolic register 'reg', and free
 773  * the hreg it was assigned to.
 774  */
 775 static void
 776 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 777 {
 778         MonoInst *load;
 779         int i, sel, spill;
 780         int *symbolic;
 781         MonoRegState *rs = cfg->rs;
 782
 783         symbolic = rs->symbolic [bank];
 784         sel = rs->vassign [reg];
 785
 786         /* the vreg we need to spill lives in another logical reg bank */
 787         bank = translate_bank (cfg->rs, bank, sel);
 788
 789         /*i = rs->isymbolic [sel];
 790         g_assert (i == reg);*/
 791         i = reg;
 792         spill = ++cfg->spill_count;
 793         rs->vassign [i] = -spill - 1;
 794         if (G_UNLIKELY (bank))
 795                 mono_regstate_free_general (rs, sel, bank);
 796         else
 797                 mono_regstate_free_int (rs, sel);
 798         /* we need to create a spill var and insert a load to sel after the current instruction */
 799         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 800         load->dreg = sel;
 801         load->inst_basereg = cfg->frame_reg;
 802         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 803         insert_after_ins (bb, ins, last, load);
 804         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 805         if (G_UNLIKELY (bank))
 806                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 807         else
 808                 i = mono_regstate_alloc_int (rs, regmask (sel));
 809         g_assert (i == sel);
 810
 811         if (G_UNLIKELY (bank))
 812                 mono_regstate_free_general (rs, sel, bank);
 813         else
 814                 mono_regstate_free_int (rs, sel);
 815 }
 816
 817 /* This isn't defined on older glib versions and on some platforms */
 818 #ifndef G_GUINT64_FORMAT
 819 #define G_GUINT64_FORMAT "ul"
 820 #endif
 821
 822 static int
 823 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 824 {
 825         MonoInst *load;
 826         int i, sel, spill, num_sregs;
 827         int sregs [MONO_MAX_SRC_REGS];
 828         int *symbolic;
 829         MonoRegState *rs = cfg->rs;
 830
 831         symbolic = rs->symbolic [bank];
 832
 833         g_assert (bank < MONO_NUM_REGBANKS);
 834
 835         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 836         /* exclude the registers in the current instruction */
 837         num_sregs = mono_inst_get_src_registers (ins, sregs);
 838         for (i = 0; i < num_sregs; ++i) {
 839                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 840                         if (is_soft_reg (sregs [i], bank))
 841                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 842                         else
 843                                 regmask &= ~ (regmask (sregs [i]));
 844                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 845                 }
 846         }
 847         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 848                 regmask &= ~ (regmask (ins->dreg));
 849                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 850         }
 851
 852         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 853         g_assert (regmask); /* need at least a register we can free */
 854         sel = 0;
 855         /* we should track prev_use and spill the register that's farther */
 856         if (G_UNLIKELY (bank)) {
 857                 for (i = 0; i < regbank_size [bank]; ++i) {
 858                         if (regmask & (regmask (i))) {
 859                                 sel = i;
 860
 861                                 /* the vreg we need to load lives in another logical bank */
 862                                 bank = translate_bank (cfg->rs, bank, sel);
 863
 864                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 865                                 break;
 866                         }
 867                 }
 868
 869                 i = rs->symbolic [bank] [sel];
 870                 spill = ++cfg->spill_count;
 871                 rs->vassign [i] = -spill - 1;
 872                 mono_regstate_free_general (rs, sel, bank);
 873         }
 874         else {
 875                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 876                         if (regmask & (regmask (i))) {
 877                                 sel = i;
 878                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 879                                 break;
 880                         }
 881                 }
 882
 883                 i = rs->isymbolic [sel];
 884                 spill = ++cfg->spill_count;
 885                 rs->vassign [i] = -spill - 1;
 886                 mono_regstate_free_int (rs, sel);
 887         }
 888
 889         /* we need to create a spill var and insert a load to sel after the current instruction */
 890         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 891         load->dreg = sel;
 892         load->inst_basereg = cfg->frame_reg;
 893         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 894         insert_after_ins (bb, ins, last, load);
 895         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 896         if (G_UNLIKELY (bank))
 897                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 898         else
 899                 i = mono_regstate_alloc_int (rs, regmask (sel));
 900         g_assert (i == sel);
 901
 902         return sel;
 903 }
 904
 905 /*
 906  * free_up_hreg:
 907  *
 908  *   Free up the hreg HREG by spilling the vreg allocated to it.
 909  */
 910 static void
 911 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 912 {
 913         if (G_UNLIKELY (bank)) {
 914                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 915                         bank = translate_bank (cfg->rs, bank, hreg);
 916                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 917                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 918                 }
 919         }
 920         else {
 921                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 922                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 923                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 924                 }
 925         }
 926 }
 927
 928 static MonoInst*
 929 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 930 {
 931         MonoInst *copy;
 932
 933         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 934
 935         copy->dreg = dest;
 936         copy->sreg1 = src;
 937         copy->cil_code = ip;
 938         if (ins) {
 939                 mono_bblock_insert_after_ins (bb, ins, copy);
 940                 *last = copy;
 941         }
 942         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 943         return copy;
 944 }
 945
 946 static inline const char*
 947 regbank_to_string (int bank)
 948 {
 949         if (bank == MONO_REG_INT_REF)
 950                 return "REF ";
 951         else if (bank == MONO_REG_INT_MP)
 952                 return "MP ";
 953         else
 954                 return "";
 955 }
 956
 957 static void
 958 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 959 {
 960         MonoInst *store, *def;
 961
 962         bank = get_vreg_bank (cfg, prev_reg, bank);
 963
 964         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 965         store->sreg1 = reg;
 966         store->inst_destbasereg = cfg->frame_reg;
 967         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 968         if (ins) {
 969                 mono_bblock_insert_after_ins (bb, ins, store);
 970                 *last = store;
 971         } else if (insert_before) {
 972                 insert_before_ins (bb, insert_before, store);
 973         } else {
 974                 g_assert_not_reached ();
 975         }
 976         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 977
 978         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 979                 g_assert (prev_reg != -1);
 980                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 981                 def->inst_c0 = spill;
 982                 def->inst_c1 = bank;
 983                 mono_bblock_insert_after_ins (bb, store, def);
 984         }
 985 }
 986
 987 /* flags used in reginfo->flags */
 988 enum {
 989         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 990         MONO_FP_NEEDS_SPILL                     = regmask (1),
 991         MONO_FP_NEEDS_LOAD                      = regmask (2)
 992 };
 993
 994 static inline int
 995 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 996 {
 997         int val;
 998
 999         if (info && info->preferred_mask) {
1000                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1001                 if (val >= 0) {
1002                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1003                         return val;
1004                 }
1005         }
1006
1007         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1008         if (val < 0)
1009                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1010
1011         return val;
1012 }
1013
1014 static inline int
1015 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1016 {
1017         int val;
1018
1019         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1020
1021         if (val < 0)
1022                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1023
1024         return val;
1025 }
1026
1027 static inline int
1028 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1029 {
1030         if (G_UNLIKELY (bank))
1031                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1032         else
1033                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1034 }
1035
1036 static inline void
1037 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1038 {
1039         if (G_UNLIKELY (bank)) {
1040                 int mirrored_bank;
1041
1042                 g_assert (reg >= regbank_size [bank]);
1043                 g_assert (hreg < regbank_size [bank]);
1044                 g_assert (! is_global_freg (hreg));
1045
1046                 rs->vassign [reg] = hreg;
1047                 rs->symbolic [bank] [hreg] = reg;
1048                 rs->free_mask [bank] &= ~ (regmask (hreg));
1049
1050                 mirrored_bank = get_mirrored_bank (bank);
1051                 if (mirrored_bank == -1)
1052                         return;
1053
1054                 /* Make sure the other logical reg bank that this bank shares
1055                  * a single hard reg bank knows that this hard reg is not free.
1056                  */
1057                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1058
1059                 /* Mark the other logical bank that the this bank shares
1060                  * a single hard reg bank with as mirrored.
1061                  */
1062                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1063
1064         }
1065         else {
1066                 g_assert (reg >= MONO_MAX_IREGS);
1067                 g_assert (hreg < MONO_MAX_IREGS);
1068 #ifndef TARGET_ARM
1069                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1070                 g_assert (! is_global_ireg (hreg));
1071 #endif
1072
1073                 rs->vassign [reg] = hreg;
1074                 rs->isymbolic [hreg] = reg;
1075                 rs->ifree_mask &= ~ (regmask (hreg));
1076         }
1077 }
1078
1079 static inline regmask_t
1080 get_callee_mask (const char spec)
1081 {
1082         if (G_UNLIKELY (reg_bank (spec)))
1083                 return regbank_callee_regs [reg_bank (spec)];
1084         return MONO_ARCH_CALLEE_REGS;
1085 }
1086
1087 static gint8 desc_to_fixed_reg [256];
1088 static gboolean desc_to_fixed_reg_inited = FALSE;
1089
1090 #ifndef DISABLE_JIT
1091
1092 /*
1093  * Local register allocation.
1094  * We first scan the list of instructions and we save the liveness info of
1095  * each register (when the register is first used, when it's value is set etc.).
1096  * We also reverse the list of instructions because assigning registers backwards allows
1097  * for more tricks to be used.
1098  */
1099 void
1100 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1101 {
1102         MonoInst *ins, *prev, *last;
1103         MonoInst **tmp;
1104         MonoRegState *rs = cfg->rs;
1105         int i, j, val, max;
1106         RegTrack *reginfo;
1107         const char *spec;
1108         unsigned char spec_src1, spec_dest;
1109         int bank = 0;
1110 #if MONO_ARCH_USE_FPSTACK
1111         gboolean has_fp = FALSE;
1112         int fpstack [8];
1113         int sp = 0;
1114 #endif
1115         int num_sregs = 0;
1116         int sregs [MONO_MAX_SRC_REGS];
1117
1118         if (!bb->code)
1119                 return;
1120
1121         if (!desc_to_fixed_reg_inited) {
1122                 for (i = 0; i < 256; ++i)
1123                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1124                 desc_to_fixed_reg_inited = TRUE;
1125
1126                 /* Validate the cpu description against the info in mini-ops.h */
1127 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1128                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1129                         const char *ispec;
1130
1131                         spec = ins_get_spec (i);
1132                         ispec = INS_INFO (i);
1133
1134                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1135                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1136                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1137                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1138                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1139                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1140                 }
1141 #endif
1142         }
1143
1144         rs->next_vreg = bb->max_vreg;
1145         mono_regstate_assign (rs);
1146
1147         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1148         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1149                 rs->free_mask [i] = regbank_callee_regs [i];
1150
1151         max = rs->next_vreg;
1152
1153         if (cfg->reginfo && cfg->reginfo_len < max)
1154                 cfg->reginfo = NULL;
1155
1156         reginfo = cfg->reginfo;
1157         if (!reginfo) {
1158                 cfg->reginfo_len = MAX (1024, max * 2);
1159                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1160         }
1161         else
1162                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1163
1164         if (cfg->verbose_level > 1) {
1165                 /* print_regtrack reads the info of all variables */
1166                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1167         }
1168
1169         /*
1170          * For large methods, next_vreg can be very large, so g_malloc0 time can
1171          * be prohibitive. So we manually init the reginfo entries used by the
1172          * bblock.
1173          */
1174         for (ins = bb->code; ins; ins = ins->next) {
1175                 spec = ins_get_spec (ins->opcode);
1176
1177                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1178                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1179 #if SIZEOF_REGISTER == 4
1180                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1181                                 /**
1182                                  * In the new IR, the two vregs of the regpair do not alias the
1183                                  * original long vreg. shift the vreg here so the rest of the
1184                                  * allocator doesn't have to care about it.
1185                                  */
1186                                 ins->dreg ++;
1187                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1188                         }
1189 #endif
1190                 }
1191
1192                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1193                 for (j = 0; j < num_sregs; ++j) {
1194                         g_assert (sregs [j] != -1);
1195                         if (sregs [j] < max) {
1196                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1197 #if SIZEOF_REGISTER == 4
1198                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1199                                         sregs [j]++;
1200                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1201                                 }
1202 #endif
1203                         }
1204                 }
1205                 mono_inst_set_src_registers (ins, sregs);
1206         }
1207
1208         /*if (cfg->opt & MONO_OPT_COPYPROP)
1209                 local_copy_prop (cfg, ins);*/
1210
1211         i = 1;
1212         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1213         /* forward pass on the instructions to collect register liveness info */
1214         MONO_BB_FOR_EACH_INS (bb, ins) {
1215                 spec = ins_get_spec (ins->opcode);
1216                 spec_dest = spec [MONO_INST_DEST];
1217
1218                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1219                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1220                 }
1221
1222                 DEBUG (mono_print_ins_index (i, ins));
1223
1224                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1225
1226 #if MONO_ARCH_USE_FPSTACK
1227                 if (dreg_is_fp (spec)) {
1228                         has_fp = TRUE;
1229                 } else {
1230                         for (j = 0; j < num_sregs; ++j) {
1231                                 if (sreg_is_fp (j, spec))
1232                                         has_fp = TRUE;
1233                         }
1234                 }
1235 #endif
1236
1237                 for (j = 0; j < num_sregs; ++j) {
1238                         int sreg = sregs [j];
1239                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1240                         if (sreg_spec) {
1241                                 bank = sreg_bank (j, spec);
1242                                 g_assert (sreg != -1);
1243                                 if (is_soft_reg (sreg, bank))
1244                                         /* This means the vreg is not local to this bb */
1245                                         g_assert (reginfo [sreg].born_in > 0);
1246                                 rs->vassign [sreg] = -1;
1247                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1248                                 //reginfo [ins->sreg2].last_use = i;
1249                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1250                                         /* The virtual register is allocated sequentially */
1251                                         rs->vassign [sreg + 1] = -1;
1252                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1253                                         //reginfo [ins->sreg2 + 1].last_use = i;
1254                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1255                                                 reginfo [sreg + 1].born_in = i;
1256                                 }
1257                         } else {
1258                                 sregs [j] = -1;
1259                         }
1260                 }
1261                 mono_inst_set_src_registers (ins, sregs);
1262
1263                 if (spec_dest) {
1264                         int dest_dreg;
1265
1266                         bank = dreg_bank (spec);
1267                         if (spec_dest != 'b') /* it's not just a base register */
1268                                 reginfo [ins->dreg].killed_in = i;
1269                         g_assert (ins->dreg != -1);
1270                         rs->vassign [ins->dreg] = -1;
1271                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1272                         //reginfo [ins->dreg].last_use = i;
1273                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1274                                 reginfo [ins->dreg].born_in = i;
1275
1276                         dest_dreg = desc_to_fixed_reg [spec_dest];
1277                         if (dest_dreg != -1)
1278                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1279
1280 #ifdef MONO_ARCH_INST_FIXED_MASK
1281                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1282 #endif
1283
1284                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1285                                 /* The virtual register is allocated sequentially */
1286                                 rs->vassign [ins->dreg + 1] = -1;
1287                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1288                                 //reginfo [ins->dreg + 1].last_use = i;
1289                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1290                                         reginfo [ins->dreg + 1].born_in = i;
1291                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1292                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1293                         }
1294                 } else {
1295                         ins->dreg = -1;
1296                 }
1297
1298                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1299                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1300
1301                         MonoCallInst *call = (MonoCallInst*)ins;
1302                         GSList *list;
1303
1304                         list = call->out_ireg_args;
1305                         if (list) {
1306                                 while (list) {
1307                                         guint32 regpair;
1308                                         int reg, hreg;
1309
1310                                         regpair = (guint32)(gssize)(list->data);
1311                                         hreg = regpair >> 24;
1312                                         reg = regpair & 0xffffff;
1313
1314                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1315                                         //reginfo [reg].last_use = i;
1316
1317                                         list = g_slist_next (list);
1318                                 }
1319                         }
1320
1321                         list = call->out_freg_args;
1322                         if (list) {
1323                                 while (list) {
1324                                         guint32 regpair;
1325                                         int reg, hreg;
1326
1327                                         regpair = (guint32)(gssize)(list->data);
1328                                         hreg = regpair >> 24;
1329                                         reg = regpair & 0xffffff;
1330
1331                                         list = g_slist_next (list);
1332                                 }
1333                         }
1334                 }
1335
1336                 ++i;
1337         }
1338
1339         tmp = &last;
1340
1341         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1342         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1343                 int prev_dreg, clob_dreg;
1344                 int dest_dreg, clob_reg;
1345                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1346                 int dreg_high, sreg1_high;
1347                 regmask_t dreg_mask, mask;
1348                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1349                 regmask_t dreg_fixed_mask;
1350                 const unsigned char *ip;
1351                 --i;
1352                 spec = ins_get_spec (ins->opcode);
1353                 spec_src1 = spec [MONO_INST_SRC1];
1354                 spec_dest = spec [MONO_INST_DEST];
1355                 prev_dreg = -1;
1356                 clob_dreg = -1;
1357                 clob_reg = -1;
1358                 dest_dreg = -1;
1359                 dreg_high = -1;
1360                 sreg1_high = -1;
1361                 dreg_mask = get_callee_mask (spec_dest);
1362                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1363                         prev_sregs [j] = -1;
1364                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1365                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1366 #ifdef MONO_ARCH_INST_FIXED_MASK
1367                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1368 #else
1369                         sreg_fixed_masks [j] = 0;
1370 #endif
1371                 }
1372
1373                 DEBUG (printf ("processing:"));
1374                 DEBUG (mono_print_ins_index (i, ins));
1375
1376                 ip = ins->cil_code;
1377
1378                 last = ins;
1379
1380                 /*
1381                  * FIXED REGS
1382                  */
1383                 dest_dreg = desc_to_fixed_reg [spec_dest];
1384                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1385                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1386
1387 #ifdef MONO_ARCH_INST_FIXED_MASK
1388                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1389 #else
1390                 dreg_fixed_mask = 0;
1391 #endif
1392
1393                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1394
1395                 /*
1396                  * TRACK FIXED SREG2, 3, ...
1397                  */
1398                 for (j = 1; j < num_sregs; ++j) {
1399                         int sreg = sregs [j];
1400                         int dest_sreg = dest_sregs [j];
1401
1402                         if (dest_sreg == -1)
1403                                 continue;
1404
1405                         if (j == 2) {
1406                                 int k;
1407
1408                                 /*
1409                                  * CAS.
1410                                  * We need to special case this, since on x86, there are only 3
1411                                  * free registers, and the code below assigns one of them to
1412                                  * sreg, so we can run out of registers when trying to assign
1413                                  * dreg. Instead, we just set up the register masks, and let the
1414                                  * normal sreg2 assignment code handle this. It would be nice to
1415                                  * do this for all the fixed reg cases too, but there is too much
1416                                  * risk of breakage.
1417                                  */
1418
1419                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1420                                 sreg_masks [j] = regmask (dest_sreg);
1421                                 for (k = 0; k < num_sregs; ++k) {
1422                                         if (k != j)
1423                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1424                                 }
1425
1426                                 /*
1427                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1428                                  */
1429                                 for (k = 0; k < num_sregs; ++k) {
1430                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1431                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1432                                 }
1433
1434                                 /*
1435                                  * We can also run out of registers while processing sreg2 if sreg3 is
1436                                  * assigned to another hreg, so spill sreg3 now.
1437                                  */
1438                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1439                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1440                                 }
1441                                 continue;
1442                         }
1443
1444                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1445                                 if (is_global_ireg (sreg)) {
1446                                         int k;
1447                                         /* Argument already in hard reg, need to copy */
1448                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1449                                         insert_before_ins (bb, ins, copy);
1450                                         for (k = 0; k < num_sregs; ++k) {
1451                                                 if (k != j)
1452                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1453                                         }
1454                                 } else {
1455                                         val = rs->vassign [sreg];
1456                                         if (val == -1) {
1457                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1458                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1459                                         } else if (val < -1) {
1460                                                 /* FIXME: */
1461                                                 g_assert_not_reached ();
1462                                         } else {
1463                                                 /* Argument already in hard reg, need to copy */
1464                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1465                                                 int k;
1466
1467                                                 insert_before_ins (bb, ins, copy);
1468                                                 for (k = 0; k < num_sregs; ++k) {
1469                                                         if (k != j)
1470                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1471                                                 }
1472                                                 /*
1473                                                  * Prevent the dreg from being allocate to dest_sreg
1474                                                  * too, since it could force sreg1 to be allocated to
1475                                                  * the same reg on x86.
1476                                                  */
1477                                                 dreg_mask &= ~ (regmask (dest_sreg));
1478                                         }
1479                                 }
1480                         } else {
1481                                 gboolean need_spill = TRUE;
1482                                 gboolean need_assign = TRUE;
1483                                 int k;
1484
1485                                 dreg_mask &= ~ (regmask (dest_sreg));
1486                                 for (k = 0; k < num_sregs; ++k) {
1487                                         if (k != j)
1488                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1489                                 }
1490
1491                                 /*
1492                                  * First check if dreg is assigned to dest_sreg2, since we
1493                                  * can't spill a dreg.
1494                                  */
1495                                 if (spec [MONO_INST_DEST])
1496                                         val = rs->vassign [ins->dreg];
1497                                 else
1498                                         val = -1;
1499                                 if (val == dest_sreg && ins->dreg != sreg) {
1500                                         /*
1501                                          * the destination register is already assigned to
1502                                          * dest_sreg2: we need to allocate another register for it
1503                                          * and then copy from this to dest_sreg2.
1504                                          */
1505                                         int new_dest;
1506                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1507                                         g_assert (new_dest >= 0);
1508                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1509
1510                                         prev_dreg = ins->dreg;
1511                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1512                                         clob_dreg = ins->dreg;
1513                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1514                                         mono_regstate_free_int (rs, dest_sreg);
1515                                         need_spill = FALSE;
1516                                 }
1517
1518                                 if (is_global_ireg (sreg)) {
1519                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1520                                         insert_before_ins (bb, ins, copy);
1521                                         need_assign = FALSE;
1522                                 }
1523                                 else {
1524                                         val = rs->vassign [sreg];
1525                                         if (val == dest_sreg) {
1526                                                 /* sreg2 is already assigned to the correct register */
1527                                                 need_spill = FALSE;
1528                                         } else if (val < -1) {
1529                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1530                                         } else if (val >= 0) {
1531                                                 /* sreg2 already assigned to another register */
1532                                                 /*
1533                                                  * We couldn't emit a copy from val to dest_sreg2, because
1534                                                  * val might be spilled later while processing this
1535                                                  * instruction. So we spill sreg2 so it can be allocated to
1536                                                  * dest_sreg2.
1537                                                  */
1538                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1539                                         }
1540                                 }
1541
1542                                 if (need_spill) {
1543                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1544                                 }
1545
1546                                 if (need_assign) {
1547                                         if (rs->vassign [sreg] < -1) {
1548                                                 int spill;
1549
1550                                                 /* Need to emit a spill store */
1551                                                 spill = - rs->vassign [sreg] - 1;
1552                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1553                                         }
1554                                         /* force-set sreg2 */
1555                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1556                                 }
1557                         }
1558                         sregs [j] = dest_sreg;
1559                 }
1560                 mono_inst_set_src_registers (ins, sregs);
1561
1562                 /*
1563                  * TRACK DREG
1564                  */
1565                 bank = dreg_bank (spec);
1566                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1567                         prev_dreg = ins->dreg;
1568                 }
1569
1570                 if (spec_dest == 'b') {
1571                         /*
1572                          * The dest reg is read by the instruction, not written, so
1573                          * avoid allocating sreg1/sreg2 to the same reg.
1574                          */
1575                         if (dest_sregs [0] != -1)
1576                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1577                         for (j = 1; j < num_sregs; ++j) {
1578                                 if (dest_sregs [j] != -1)
1579                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1580                         }
1581
1582                         val = rs->vassign [ins->dreg];
1583                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1584                                 /* DREG is already allocated to a register needed for sreg1 */
1585                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1586                         }
1587                 }
1588
1589                 /*
1590                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1591                  * various complex situations.
1592                  */
1593                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1594                         guint32 dreg2, dest_dreg2;
1595
1596                         g_assert (is_soft_reg (ins->dreg, bank));
1597
1598                         if (dest_dreg != -1) {
1599                                 if (rs->vassign [ins->dreg] != dest_dreg)
1600                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1601
1602                                 dreg2 = ins->dreg + 1;
1603                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1604                                 if (dest_dreg2 != -1) {
1605                                         if (rs->vassign [dreg2] != dest_dreg2)
1606                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1607                                 }
1608                         }
1609                 }
1610
1611                 if (dreg_fixed_mask) {
1612                         g_assert (!bank);
1613                         if (is_global_ireg (ins->dreg)) {
1614                                 /*
1615                                  * The argument is already in a hard reg, but that reg is
1616                                  * not usable by this instruction, so allocate a new one.
1617                                  */
1618                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1619                                 if (val < 0)
1620                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1621                                 mono_regstate_free_int (rs, val);
1622                                 dest_dreg = val;
1623
1624                                 /* Fall through */
1625                         }
1626                         else
1627                                 dreg_mask &= dreg_fixed_mask;
1628                 }
1629
1630                 if (is_soft_reg (ins->dreg, bank)) {
1631                         val = rs->vassign [ins->dreg];
1632
1633                         if (val < 0) {
1634                                 int spill = 0;
1635                                 if (val < -1) {
1636                                         /* the register gets spilled after this inst */
1637                                         spill = -val -1;
1638                                 }
1639                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1640                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1641                                 if (spill)
1642                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1643                         }
1644
1645                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1646                         ins->dreg = val;
1647                 }
1648
1649                 /* Handle regpairs */
1650                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1651                         int reg2 = prev_dreg + 1;
1652
1653                         g_assert (!bank);
1654                         g_assert (prev_dreg > -1);
1655                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1656                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1657 #ifdef TARGET_X86
1658                         /* bug #80489 */
1659                         mask &= ~regmask (X86_ECX);
1660 #endif
1661                         val = rs->vassign [reg2];
1662                         if (val < 0) {
1663                                 int spill = 0;
1664                                 if (val < -1) {
1665                                         /* the register gets spilled after this inst */
1666                                         spill = -val -1;
1667                                 }
1668                                 val = mono_regstate_alloc_int (rs, mask);
1669                                 if (val < 0)
1670                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1671                                 if (spill)
1672                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1673                         }
1674                         else {
1675                                 if (! (mask & (regmask (val)))) {
1676                                         val = mono_regstate_alloc_int (rs, mask);
1677                                         if (val < 0)
1678                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1679
1680                                         /* Reallocate hreg to the correct register */
1681                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1682
1683                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1684                                 }
1685                         }
1686
1687                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1688                         assign_reg (cfg, rs, reg2, val, bank);
1689
1690                         dreg_high = val;
1691                         ins->backend.reg3 = val;
1692
1693                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1694                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1695                                 mono_regstate_free_int (rs, val);
1696                         }
1697                 }
1698
1699                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1700                         /*
1701                          * In theory, we could free up the hreg even if the vreg is alive,
1702                          * but branches inside bblocks force us to assign the same hreg
1703                          * to a vreg every time it is encountered.
1704                          */
1705                         int dreg = rs->vassign [prev_dreg];
1706                         g_assert (dreg >= 0);
1707                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1708                         if (G_UNLIKELY (bank))
1709                                 mono_regstate_free_general (rs, dreg, bank);
1710                         else
1711                                 mono_regstate_free_int (rs, dreg);
1712                         rs->vassign [prev_dreg] = -1;
1713                 }
1714
1715                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1716                         /* this instruction only outputs to dest_dreg, need to copy */
1717                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1718                         ins->dreg = dest_dreg;
1719
1720                         if (G_UNLIKELY (bank)) {
1721                                 /* the register we need to free up may be used in another logical regbank
1722                                  * so do a translate just in case.
1723                                  */
1724                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1725                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1726                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1727                         }
1728                         else {
1729                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1730                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1731                         }
1732                 }
1733
1734                 if (spec_dest == 'b') {
1735                         /*
1736                          * The dest reg is read by the instruction, not written, so
1737                          * avoid allocating sreg1/sreg2 to the same reg.
1738                          */
1739                         for (j = 0; j < num_sregs; ++j)
1740                                 if (!sreg_bank (j, spec))
1741                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1742                 }
1743
1744                 /*
1745                  * TRACK CLOBBERING
1746                  */
1747                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1748                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1749                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1750                 }
1751
1752                 if (spec [MONO_INST_CLOB] == 'c') {
1753                         int j, s, dreg, dreg2, cur_bank;
1754                         guint64 clob_mask;
1755
1756                         clob_mask = MONO_ARCH_CALLEE_REGS;
1757
1758                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1759                                 /*
1760                                  * Need to avoid spilling the dreg since the dreg is not really
1761                                  * clobbered by the call.
1762                                  */
1763                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1764                                         dreg = rs->vassign [prev_dreg];
1765                                 else
1766                                         dreg = -1;
1767
1768                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1769                                         dreg2 = rs->vassign [prev_dreg + 1];
1770                                 else
1771                                         dreg2 = -1;
1772
1773                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1774                                         s = regmask (j);
1775                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1776                                                 if ((j != dreg) && (j != dreg2))
1777                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1778                                                 else if (rs->isymbolic [j])
1779                                                         /* The hreg is assigned to the dreg of this instruction */
1780                                                         rs->vassign [rs->isymbolic [j]] = -1;
1781                                                 mono_regstate_free_int (rs, j);
1782                                         }
1783                                 }
1784                         }
1785
1786                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1787                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1788                                         clob_mask = regbank_callee_regs [cur_bank];
1789                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1790                                                 dreg = rs->vassign [prev_dreg];
1791                                         else
1792                                                 dreg = -1;
1793
1794                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1795
1796                                                 /* we are looping though the banks in the outer loop
1797                                                  * so, we don't need to deal with mirrored hregs
1798                                                  * because we will get them in one of the other bank passes.
1799                                                  */
1800                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1801                                                         continue;
1802
1803                                                 s = regmask (j);
1804                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1805                                                         if (j != dreg)
1806                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1807                                                         else if (rs->symbolic [cur_bank] [j])
1808                                                                 /* The hreg is assigned to the dreg of this instruction */
1809                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1810                                                         mono_regstate_free_general (rs, j, cur_bank);
1811                                                 }
1812                                         }
1813                                 }
1814                         }
1815                 }
1816
1817                 /*
1818                  * TRACK ARGUMENT REGS
1819                  */
1820                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1821                         MonoCallInst *call = (MonoCallInst*)ins;
1822                         GSList *list;
1823
1824                         /*
1825                          * This needs to be done before assigning sreg1, so sreg1 will
1826                          * not be assigned one of the argument regs.
1827                          */
1828
1829                         /*
1830                          * Assign all registers in call->out_reg_args to the proper
1831                          * argument registers.
1832                          */
1833
1834                         list = call->out_ireg_args;
1835                         if (list) {
1836                                 while (list) {
1837                                         guint32 regpair;
1838                                         int reg, hreg;
1839
1840                                         regpair = (guint32)(gssize)(list->data);
1841                                         hreg = regpair >> 24;
1842                                         reg = regpair & 0xffffff;
1843
1844                                         assign_reg (cfg, rs, reg, hreg, 0);
1845
1846                                         sreg_masks [0] &= ~(regmask (hreg));
1847
1848                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1849
1850                                         list = g_slist_next (list);
1851                                 }
1852                         }
1853
1854                         list = call->out_freg_args;
1855                         if (list) {
1856                                 while (list) {
1857                                         guint32 regpair;
1858                                         int reg, hreg;
1859
1860                                         regpair = (guint32)(gssize)(list->data);
1861                                         hreg = regpair >> 24;
1862                                         reg = regpair & 0xffffff;
1863
1864                                         assign_reg (cfg, rs, reg, hreg, 1);
1865
1866                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1867
1868                                         list = g_slist_next (list);
1869                                 }
1870                         }
1871                 }
1872
1873                 /*
1874                  * TRACK SREG1
1875                  */
1876                 bank = sreg1_bank (spec);
1877                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1878                         int sreg1 = sregs [0];
1879                         int dest_sreg1 = dest_sregs [0];
1880
1881                         g_assert (is_soft_reg (sreg1, bank));
1882
1883                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1884                         if (dest_sreg1 != -1)
1885                                 g_assert (dest_sreg1 == ins->dreg);
1886                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1887                         g_assert (val >= 0);
1888
1889                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1890                                 // FIXME:
1891                                 g_assert_not_reached ();
1892
1893                         assign_reg (cfg, rs, sreg1, val, bank);
1894
1895                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1896
1897                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1898                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1899                         g_assert (val >= 0);
1900
1901                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1902                                 // FIXME:
1903                                 g_assert_not_reached ();
1904
1905                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1906
1907                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1908
1909                         /* Skip rest of this section */
1910                         dest_sregs [0] = -1;
1911                 }
1912
1913                 if (sreg_fixed_masks [0]) {
1914                         g_assert (!bank);
1915                         if (is_global_ireg (sregs [0])) {
1916                                 /*
1917                                  * The argument is already in a hard reg, but that reg is
1918                                  * not usable by this instruction, so allocate a new one.
1919                                  */
1920                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1921                                 if (val < 0)
1922                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1923                                 mono_regstate_free_int (rs, val);
1924                                 dest_sregs [0] = val;
1925
1926                                 /* Fall through to the dest_sreg1 != -1 case */
1927                         }
1928                         else
1929                                 sreg_masks [0] &= sreg_fixed_masks [0];
1930                 }
1931
1932                 if (dest_sregs [0] != -1) {
1933                         sreg_masks [0] = regmask (dest_sregs [0]);
1934
1935                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1936                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1937                         }
1938                         if (is_global_ireg (sregs [0])) {
1939                                 /* The argument is already in a hard reg, need to copy */
1940                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1941                                 insert_before_ins (bb, ins, copy);
1942                                 sregs [0] = dest_sregs [0];
1943                         }
1944                 }
1945
1946                 if (is_soft_reg (sregs [0], bank)) {
1947                         val = rs->vassign [sregs [0]];
1948                         prev_sregs [0] = sregs [0];
1949                         if (val < 0) {
1950                                 int spill = 0;
1951                                 if (val < -1) {
1952                                         /* the register gets spilled after this inst */
1953                                         spill = -val -1;
1954                                 }
1955
1956                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1957                                         /*
1958                                          * Allocate the same hreg to sreg1 as well so the
1959                                          * peephole can get rid of the move.
1960                                          */
1961                                         sreg_masks [0] = regmask (ins->dreg);
1962                                 }
1963
1964                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1965                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1966                                         sreg_masks [0] = regmask (ins->dreg);
1967
1968                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1969                                 assign_reg (cfg, rs, sregs [0], val, bank);
1970                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1971
1972                                 if (spill) {
1973                                         /*
1974                                          * Need to insert before the instruction since it can
1975                                          * overwrite sreg1.
1976                                          */
1977                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1978                                 }
1979                         }
1980                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1981                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1982                                 insert_before_ins (bb, ins, copy);
1983                                 for (j = 1; j < num_sregs; ++j)
1984                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1985                                 val = dest_sregs [0];
1986                         }
1987
1988                         sregs [0] = val;
1989                 }
1990                 else {
1991                         prev_sregs [0] = -1;
1992                 }
1993                 mono_inst_set_src_registers (ins, sregs);
1994
1995                 for (j = 1; j < num_sregs; ++j)
1996                         sreg_masks [j] &= ~(regmask (sregs [0]));
1997
1998                 /* Handle the case when sreg1 is a regpair but dreg is not */
1999                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
2000                         int reg2 = prev_sregs [0] + 1;
2001
2002                         g_assert (!bank);
2003                         g_assert (prev_sregs [0] > -1);
2004                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
2005                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
2006                         val = rs->vassign [reg2];
2007                         if (val < 0) {
2008                                 int spill = 0;
2009                                 if (val < -1) {
2010                                         /* the register gets spilled after this inst */
2011                                         spill = -val -1;
2012                                 }
2013                                 val = mono_regstate_alloc_int (rs, mask);
2014                                 if (val < 0)
2015                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2016                                 if (spill)
2017                                         g_assert_not_reached ();
2018                         }
2019                         else {
2020                                 if (! (mask & (regmask (val)))) {
2021                                         /* The vreg is already allocated to a wrong hreg */
2022                                         /* FIXME: */
2023                                         g_assert_not_reached ();
2024 #if 0
2025                                         val = mono_regstate_alloc_int (rs, mask);
2026                                         if (val < 0)
2027                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2028
2029                                         /* Reallocate hreg to the correct register */
2030                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2031
2032                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2033 #endif
2034                                 }
2035                         }
2036
2037                         sreg1_high = val;
2038                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2039                         assign_reg (cfg, rs, reg2, val, bank);
2040                 }
2041
2042                 /* Handle dreg==sreg1 */
2043                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2044                         MonoInst *sreg2_copy = NULL;
2045                         MonoInst *copy;
2046                         int bank = reg_bank (spec_src1);
2047
2048                         if (ins->dreg == sregs [1]) {
2049                                 /*
2050                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2051                                  * register for it.
2052                                  */
2053                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2054
2055                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2056                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2057                                 prev_sregs [1] = sregs [1] = reg2;
2058
2059                                 if (G_UNLIKELY (bank))
2060                                         mono_regstate_free_general (rs, reg2, bank);
2061                                 else
2062                                         mono_regstate_free_int (rs, reg2);
2063                         }
2064
2065                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2066                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2067                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2068                                         /* FIXME: */
2069                                         g_assert_not_reached ();
2070
2071                                 /*
2072                                  * sreg1 and dest are already allocated to the same regpair by the
2073                                  * SREG1 allocation code.
2074                                  */
2075                                 g_assert (sregs [0] == ins->dreg);
2076                                 g_assert (dreg_high == sreg1_high);
2077                         }
2078
2079                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2080                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2081                         insert_before_ins (bb, ins, copy);
2082
2083                         if (sreg2_copy)
2084                                 insert_before_ins (bb, copy, sreg2_copy);
2085
2086                         /*
2087                          * Need to prevent sreg2 to be allocated to sreg1, since that
2088                          * would screw up the previous copy.
2089                          */
2090                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2091                         /* we set sreg1 to dest as well */
2092                         prev_sregs [0] = sregs [0] = ins->dreg;
2093                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2094                 }
2095                 mono_inst_set_src_registers (ins, sregs);
2096
2097                 /*
2098                  * TRACK SREG2, 3, ...
2099                  */
2100                 for (j = 1; j < num_sregs; ++j) {
2101                         int k;
2102
2103                         bank = sreg_bank (j, spec);
2104                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2105                                 g_assert_not_reached ();
2106
2107                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2108                                 /*
2109                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2110                                  * allocating it to the fixed reg.
2111                                  */
2112                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2113                                 insert_before_ins (bb, ins, copy);
2114                                 sregs [j] = dest_sregs [j];
2115                         } else if (is_soft_reg (sregs [j], bank)) {
2116                                 val = rs->vassign [sregs [j]];
2117
2118                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2119                                         /*
2120                                          * The sreg is already allocated to a hreg, but not to the fixed
2121                                          * reg required by the instruction. Spill the sreg, so it can be
2122                                          * allocated to the fixed reg by the code below.
2123                                          */
2124                                         /* Currently, this code should only be hit for CAS */
2125                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2126                                         val = rs->vassign [sregs [j]];
2127                                 }
2128
2129                                 if (val < 0) {
2130                                         int spill = 0;
2131                                         if (val < -1) {
2132                                                 /* the register gets spilled after this inst */
2133                                                 spill = -val -1;
2134                                         }
2135                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2136                                         assign_reg (cfg, rs, sregs [j], val, bank);
2137                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2138                                         if (spill) {
2139                                                 /*
2140                                                  * Need to insert before the instruction since it can
2141                                                  * overwrite sreg2.
2142                                                  */
2143                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2144                                         }
2145                                 }
2146                                 sregs [j] = val;
2147                                 for (k = j + 1; k < num_sregs; ++k)
2148                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2149                         }
2150                         else {
2151                                 prev_sregs [j] = -1;
2152                         }
2153                 }
2154                 mono_inst_set_src_registers (ins, sregs);
2155
2156                 /* Sanity check */
2157                 /* Do this only for CAS for now */
2158                 for (j = 1; j < num_sregs; ++j) {
2159                         int sreg = sregs [j];
2160                         int dest_sreg = dest_sregs [j];
2161
2162                         if (j == 2 && dest_sreg != -1) {
2163                                 int k;
2164
2165                                 g_assert (sreg == dest_sreg);
2166
2167                                 for (k = 0; k < num_sregs; ++k) {
2168                                         if (k != j)
2169                                                 g_assert (sregs [k] != dest_sreg);
2170                                 }
2171                         }
2172                 }
2173
2174                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2175                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2176                         mono_regstate_free_int (rs, ins->sreg1);
2177                 }
2178                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2179                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2180                         mono_regstate_free_int (rs, ins->sreg2);
2181                 }*/
2182
2183                 DEBUG (mono_print_ins_index (i, ins));
2184         }
2185
2186         // FIXME: Set MAX_FREGS to 8
2187         // FIXME: Optimize generated code
2188 #if MONO_ARCH_USE_FPSTACK
2189         /*
2190          * Make a forward pass over the code, simulating the fp stack, making sure the
2191          * arguments required by the fp opcodes are at the top of the stack.
2192          */
2193         if (has_fp) {
2194                 MonoInst *prev = NULL;
2195                 MonoInst *fxch;
2196                 int tmp;
2197
2198                 g_assert (num_sregs <= 2);
2199
2200                 for (ins = bb->code; ins; ins = ins->next) {
2201                         spec = ins_get_spec (ins->opcode);
2202
2203                         DEBUG (printf ("processing:"));
2204                         DEBUG (mono_print_ins_index (0, ins));
2205
2206                         if (ins->opcode == OP_FMOVE) {
2207                                 /* Do it by renaming the source to the destination on the stack */
2208                                 // FIXME: Is this correct ?
2209                                 for (i = 0; i < sp; ++i)
2210                                         if (fpstack [i] == ins->sreg1)
2211                                                 fpstack [i] = ins->dreg;
2212                                 prev = ins;
2213                                 continue;
2214                         }
2215
2216                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2217                                 /* Arg1 must be in %st(1) */
2218                                 g_assert (prev);
2219
2220                                 i = 0;
2221                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2222                                         i ++;
2223                                 g_assert (i < sp);
2224
2225                                 if (sp - 1 - i > 0) {
2226                                         /* First move it to %st(0) */
2227                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2228
2229                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2230                                         fxch->inst_imm = sp - 1 - i;
2231
2232                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2233                                         prev = fxch;
2234
2235                                         tmp = fpstack [sp - 1];
2236                                         fpstack [sp - 1] = fpstack [i];
2237                                         fpstack [i] = tmp;
2238                                 }
2239
2240                                 /* Then move it to %st(1) */
2241                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2242
2243                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2244                                 fxch->inst_imm = 1;
2245
2246                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2247                                 prev = fxch;
2248
2249                                 tmp = fpstack [sp - 1];
2250                                 fpstack [sp - 1] = fpstack [sp - 2];
2251                                 fpstack [sp - 2] = tmp;
2252                         }
2253
2254                         if (sreg2_is_fp (spec)) {
2255                                 g_assert (sp > 0);
2256
2257                                 if (fpstack [sp - 1] != ins->sreg2) {
2258                                         g_assert (prev);
2259
2260                                         i = 0;
2261                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2262                                                 i ++;
2263                                         g_assert (i < sp);
2264
2265                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2266
2267                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2268                                         fxch->inst_imm = sp - 1 - i;
2269
2270                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2271                                         prev = fxch;
2272
2273                                         tmp = fpstack [sp - 1];
2274                                         fpstack [sp - 1] = fpstack [i];
2275                                         fpstack [i] = tmp;
2276                                 }
2277
2278                                 sp --;
2279                         }
2280
2281                         if (sreg1_is_fp (spec)) {
2282                                 g_assert (sp > 0);
2283
2284                                 if (fpstack [sp - 1] != ins->sreg1) {
2285                                         g_assert (prev);
2286
2287                                         i = 0;
2288                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2289                                                 i ++;
2290                                         g_assert (i < sp);
2291
2292                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2293
2294                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2295                                         fxch->inst_imm = sp - 1 - i;
2296
2297                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2298                                         prev = fxch;
2299
2300                                         tmp = fpstack [sp - 1];
2301                                         fpstack [sp - 1] = fpstack [i];
2302                                         fpstack [i] = tmp;
2303                                 }
2304
2305                                 sp --;
2306                         }
2307
2308                         if (dreg_is_fp (spec)) {
2309                                 g_assert (sp < 8);
2310                                 fpstack [sp ++] = ins->dreg;
2311                         }
2312
2313                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2314                                 printf ("\t[");
2315                                 for (i = 0; i < sp; ++i)
2316                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2317                                 printf ("]\n");
2318                         }
2319
2320                         prev = ins;
2321                 }
2322
2323                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2324                         /* Remove remaining items from the fp stack */
2325                         /*
2326                          * These can remain for example as a result of a dead fmove like in
2327                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2328                          */
2329                         while (sp) {
2330                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2331                                 mono_add_ins_to_end (bb, ins);
2332                                 sp --;
2333                         }
2334                 }
2335         }
2336 #endif
2337 }
2338
2339 CompRelation
2340 mono_opcode_to_cond (int opcode)
2341 {
2342         switch (opcode) {
2343         case OP_CEQ:
2344         case OP_IBEQ:
2345         case OP_ICEQ:
2346         case OP_LBEQ:
2347         case OP_LCEQ:
2348         case OP_FBEQ:
2349         case OP_FCEQ:
2350         case OP_COND_EXC_EQ:
2351         case OP_COND_EXC_IEQ:
2352         case OP_CMOV_IEQ:
2353         case OP_CMOV_LEQ:
2354                 return CMP_EQ;
2355         case OP_FCNEQ:
2356         case OP_ICNEQ:
2357         case OP_IBNE_UN:
2358         case OP_LBNE_UN:
2359         case OP_FBNE_UN:
2360         case OP_COND_EXC_NE_UN:
2361         case OP_COND_EXC_INE_UN:
2362         case OP_CMOV_INE_UN:
2363         case OP_CMOV_LNE_UN:
2364                 return CMP_NE;
2365         case OP_FCLE:
2366         case OP_ICLE:
2367         case OP_IBLE:
2368         case OP_LBLE:
2369         case OP_FBLE:
2370         case OP_CMOV_ILE:
2371         case OP_CMOV_LLE:
2372                 return CMP_LE;
2373         case OP_FCGE:
2374         case OP_ICGE:
2375         case OP_IBGE:
2376         case OP_LBGE:
2377         case OP_FBGE:
2378         case OP_CMOV_IGE:
2379         case OP_CMOV_LGE:
2380                 return CMP_GE;
2381         case OP_CLT:
2382         case OP_IBLT:
2383         case OP_ICLT:
2384         case OP_LBLT:
2385         case OP_LCLT:
2386         case OP_FBLT:
2387         case OP_FCLT:
2388         case OP_COND_EXC_LT:
2389         case OP_COND_EXC_ILT:
2390         case OP_CMOV_ILT:
2391         case OP_CMOV_LLT:
2392                 return CMP_LT;
2393         case OP_CGT:
2394         case OP_IBGT:
2395         case OP_ICGT:
2396         case OP_LBGT:
2397         case OP_LCGT:
2398         case OP_FBGT:
2399         case OP_FCGT:
2400         case OP_COND_EXC_GT:
2401         case OP_COND_EXC_IGT:
2402         case OP_CMOV_IGT:
2403         case OP_CMOV_LGT:
2404                 return CMP_GT;
2405
2406         case OP_ICLE_UN:
2407         case OP_IBLE_UN:
2408         case OP_LBLE_UN:
2409         case OP_FBLE_UN:
2410         case OP_COND_EXC_LE_UN:
2411         case OP_COND_EXC_ILE_UN:
2412         case OP_CMOV_ILE_UN:
2413         case OP_CMOV_LLE_UN:
2414                 return CMP_LE_UN;
2415
2416         case OP_ICGE_UN:
2417         case OP_IBGE_UN:
2418         case OP_LBGE_UN:
2419         case OP_FBGE_UN:
2420         case OP_CMOV_IGE_UN:
2421         case OP_CMOV_LGE_UN:
2422                 return CMP_GE_UN;
2423         case OP_CLT_UN:
2424         case OP_IBLT_UN:
2425         case OP_ICLT_UN:
2426         case OP_LBLT_UN:
2427         case OP_LCLT_UN:
2428         case OP_FBLT_UN:
2429         case OP_FCLT_UN:
2430         case OP_COND_EXC_LT_UN:
2431         case OP_COND_EXC_ILT_UN:
2432         case OP_CMOV_ILT_UN:
2433         case OP_CMOV_LLT_UN:
2434                 return CMP_LT_UN;
2435         case OP_CGT_UN:
2436         case OP_IBGT_UN:
2437         case OP_ICGT_UN:
2438         case OP_LBGT_UN:
2439         case OP_LCGT_UN:
2440         case OP_FCGT_UN:
2441         case OP_FBGT_UN:
2442         case OP_COND_EXC_GT_UN:
2443         case OP_COND_EXC_IGT_UN:
2444         case OP_CMOV_IGT_UN:
2445         case OP_CMOV_LGT_UN:
2446                 return CMP_GT_UN;
2447         default:
2448                 printf ("%s\n", mono_inst_name (opcode));
2449                 g_assert_not_reached ();
2450                 return 0;
2451         }
2452 }
2453
2454 CompRelation
2455 mono_negate_cond (CompRelation cond)
2456 {
2457         switch (cond) {
2458         case CMP_EQ:
2459                 return CMP_NE;
2460         case CMP_NE:
2461                 return CMP_EQ;
2462         case CMP_LE:
2463                 return CMP_GT;
2464         case CMP_GE:
2465                 return CMP_LT;
2466         case CMP_LT:
2467                 return CMP_GE;
2468         case CMP_GT:
2469                 return CMP_LE;
2470         case CMP_LE_UN:
2471                 return CMP_GT_UN;
2472         case CMP_GE_UN:
2473                 return CMP_LT_UN;
2474         case CMP_LT_UN:
2475                 return CMP_GE_UN;
2476         case CMP_GT_UN:
2477                 return CMP_LE_UN;
2478         default:
2479                 g_assert_not_reached ();
2480         }
2481 }
2482
2483 CompType
2484 mono_opcode_to_type (int opcode, int cmp_opcode)
2485 {
2486         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2487                 return CMP_TYPE_L;
2488         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2489                 return CMP_TYPE_I;
2490         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2491                 return CMP_TYPE_I;
2492         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2493                 return CMP_TYPE_L;
2494         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2495                 return CMP_TYPE_L;
2496         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2497                 return CMP_TYPE_F;
2498         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2499                 return CMP_TYPE_F;
2500         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2501                 return CMP_TYPE_I;
2502         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2503                 switch (cmp_opcode) {
2504                 case OP_ICOMPARE:
2505                 case OP_ICOMPARE_IMM:
2506                         return CMP_TYPE_I;
2507                 default:
2508                         return CMP_TYPE_L;
2509                 }
2510         } else {
2511                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2512                 return 0;
2513         }
2514 }
2515
2516 #endif /* DISABLE_JIT */
2517
2518 gboolean
2519 mono_is_regsize_var (MonoType *t)
2520 {
2521         if (t->byref)
2522                 return TRUE;
2523         t = mono_type_get_underlying_type (t);
2524         switch (t->type) {
2525         case MONO_TYPE_BOOLEAN:
2526         case MONO_TYPE_CHAR:
2527         case MONO_TYPE_I1:
2528         case MONO_TYPE_U1:
2529         case MONO_TYPE_I2:
2530         case MONO_TYPE_U2:
2531         case MONO_TYPE_I4:
2532         case MONO_TYPE_U4:
2533         case MONO_TYPE_I:
2534         case MONO_TYPE_U:
2535         case MONO_TYPE_PTR:
2536         case MONO_TYPE_FNPTR:
2537 #if SIZEOF_REGISTER == 8
2538         case MONO_TYPE_I8:
2539         case MONO_TYPE_U8:
2540 #endif
2541                 return TRUE;
2542         case MONO_TYPE_OBJECT:
2543         case MONO_TYPE_STRING:
2544         case MONO_TYPE_CLASS:
2545         case MONO_TYPE_SZARRAY:
2546         case MONO_TYPE_ARRAY:
2547                 return TRUE;
2548         case MONO_TYPE_GENERICINST:
2549                 if (!mono_type_generic_inst_is_valuetype (t))
2550                         return TRUE;
2551                 return FALSE;
2552         case MONO_TYPE_VALUETYPE:
2553                 return FALSE;
2554         default:
2555                 return FALSE;
2556         }
2557 }
2558
2559 #ifndef DISABLE_JIT
2560
2561 /*
2562  * mono_peephole_ins:
2563  *
2564  *   Perform some architecture independent peephole optimizations.
2565  */
2566 void
2567 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2568 {
2569         MonoInst *last_ins = ins->prev;
2570
2571         switch (ins->opcode) {
2572         case OP_MUL_IMM:
2573                 /* remove unnecessary multiplication with 1 */
2574                 if (ins->inst_imm == 1) {
2575                         if (ins->dreg != ins->sreg1)
2576                                 ins->opcode = OP_MOVE;
2577                         else
2578                                 MONO_DELETE_INS (bb, ins);
2579                 }
2580                 break;
2581         case OP_LOAD_MEMBASE:
2582         case OP_LOADI4_MEMBASE:
2583                 /*
2584                  * Note: if reg1 = reg2 the load op is removed
2585                  *
2586                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2587                  * OP_LOAD_MEMBASE offset(basereg), reg2
2588                  * -->
2589                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2590                  * OP_MOVE reg1, reg2
2591                  */
2592                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2593                         last_ins = last_ins->prev;
2594                 if (last_ins &&
2595                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2596                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2597                         ins->inst_basereg == last_ins->inst_destbasereg &&
2598                         ins->inst_offset == last_ins->inst_offset) {
2599                         if (ins->dreg == last_ins->sreg1) {
2600                                 MONO_DELETE_INS (bb, ins);
2601                                 break;
2602                         } else {
2603                                 ins->opcode = OP_MOVE;
2604                                 ins->sreg1 = last_ins->sreg1;
2605                         }
2606
2607                         /*
2608                          * Note: reg1 must be different from the basereg in the second load
2609                          * Note: if reg1 = reg2 is equal then second load is removed
2610                          *
2611                          * OP_LOAD_MEMBASE offset(basereg), reg1
2612                          * OP_LOAD_MEMBASE offset(basereg), reg2
2613                          * -->
2614                          * OP_LOAD_MEMBASE offset(basereg), reg1
2615                          * OP_MOVE reg1, reg2
2616                          */
2617                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2618                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2619                           ins->inst_basereg != last_ins->dreg &&
2620                           ins->inst_basereg == last_ins->inst_basereg &&
2621                           ins->inst_offset == last_ins->inst_offset) {
2622
2623                         if (ins->dreg == last_ins->dreg) {
2624                                 MONO_DELETE_INS (bb, ins);
2625                         } else {
2626                                 ins->opcode = OP_MOVE;
2627                                 ins->sreg1 = last_ins->dreg;
2628                         }
2629
2630                         //g_assert_not_reached ();
2631
2632 #if 0
2633                         /*
2634                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2635                          * OP_LOAD_MEMBASE offset(basereg), reg
2636                          * -->
2637                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2638                          * OP_ICONST reg, imm
2639                          */
2640                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2641                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2642                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2643                                    ins->inst_offset == last_ins->inst_offset) {
2644                         ins->opcode = OP_ICONST;
2645                         ins->inst_c0 = last_ins->inst_imm;
2646                         g_assert_not_reached (); // check this rule
2647 #endif
2648                 }
2649                 break;
2650         case OP_LOADI1_MEMBASE:
2651         case OP_LOADU1_MEMBASE:
2652                 /*
2653                  * Note: if reg1 = reg2 the load op is removed
2654                  *
2655                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2656                  * OP_LOAD_MEMBASE offset(basereg), reg2
2657                  * -->
2658                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2659                  * OP_MOVE reg1, reg2
2660                  */
2661                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2662                         ins->inst_basereg == last_ins->inst_destbasereg &&
2663                         ins->inst_offset == last_ins->inst_offset) {
2664                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2665                         ins->sreg1 = last_ins->sreg1;
2666                 }
2667                 break;
2668         case OP_LOADI2_MEMBASE:
2669         case OP_LOADU2_MEMBASE:
2670                 /*
2671                  * Note: if reg1 = reg2 the load op is removed
2672                  *
2673                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2674                  * OP_LOAD_MEMBASE offset(basereg), reg2
2675                  * -->
2676                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2677                  * OP_MOVE reg1, reg2
2678                  */
2679                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2680                         ins->inst_basereg == last_ins->inst_destbasereg &&
2681                         ins->inst_offset == last_ins->inst_offset) {
2682 #if SIZEOF_REGISTER == 8
2683                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2684 #else
2685                         /* The definition of OP_PCONV_TO_U2 is wrong */
2686                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2687 #endif
2688                         ins->sreg1 = last_ins->sreg1;
2689                 }
2690                 break;
2691         case OP_MOVE:
2692         case OP_FMOVE:
2693                 /*
2694                  * Removes:
2695                  *
2696                  * OP_MOVE reg, reg
2697                  */
2698                 if (ins->dreg == ins->sreg1) {
2699                         MONO_DELETE_INS (bb, ins);
2700                         break;
2701                 }
2702                 /*
2703                  * Removes:
2704                  *
2705                  * OP_MOVE sreg, dreg
2706                  * OP_MOVE dreg, sreg
2707                  */
2708                 if (last_ins && last_ins->opcode == ins->opcode &&
2709                         ins->sreg1 == last_ins->dreg &&
2710                         ins->dreg == last_ins->sreg1) {
2711                         MONO_DELETE_INS (bb, ins);
2712                 }
2713                 break;
2714         case OP_NOP:
2715                 MONO_DELETE_INS (bb, ins);
2716                 break;
2717         }
2718 }
2719
2720 int
2721 mini_exception_id_by_name (const char *name)
2722 {
2723         if (strcmp (name, "IndexOutOfRangeException") == 0)
2724                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2725         if (strcmp (name, "OverflowException") == 0)
2726                 return MONO_EXC_OVERFLOW;
2727         if (strcmp (name, "ArithmeticException") == 0)
2728                 return MONO_EXC_ARITHMETIC;
2729         if (strcmp (name, "DivideByZeroException") == 0)
2730                 return MONO_EXC_DIVIDE_BY_ZERO;
2731         if (strcmp (name, "InvalidCastException") == 0)
2732                 return MONO_EXC_INVALID_CAST;
2733         if (strcmp (name, "NullReferenceException") == 0)
2734                 return MONO_EXC_NULL_REF;
2735         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2736                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2737         if (strcmp (name, "ArgumentException") == 0)
2738                 return MONO_EXC_ARGUMENT;
2739         g_error ("Unknown intrinsic exception %s\n", name);
2740         return -1;
2741 }
2742
2743 #endif /* DISABLE_JIT */