mono/mini/mini-codegen.c

   1 /**
   2  * \file
   3  * Arch independent code generation functionality
   4  *
   5  * (C) 2003 Ximian, Inc.
   6  */
   7
   8 #include "config.h"
   9
  10 #include <string.h>
  11 #include <math.h>
  12 #ifdef HAVE_UNISTD_H
  13 #include <unistd.h>
  14 #endif
  15
  16 #include <mono/metadata/appdomain.h>
  17 #include <mono/metadata/debug-helpers.h>
  18 #include <mono/metadata/threads.h>
  19 #include <mono/metadata/profiler-private.h>
  20 #include <mono/metadata/mempool-internals.h>
  21 #include <mono/utils/mono-math.h>
  22
  23 #include "mini.h"
  24 #include "trace.h"
  25 #include "mini-arch.h"
  26
  27 #ifndef DISABLE_JIT
  28
  29 #ifndef MONO_MAX_XREGS
  30
  31 #define MONO_MAX_XREGS 0
  32 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  33 #define MONO_ARCH_CALLEE_XREGS 0
  34
  35 #endif
  36
  37 #define MONO_ARCH_BANK_MIRRORED -2
  38
  39 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  40
  41 #ifndef MONO_ARCH_NEED_SIMD_BANK
  42 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  43 #endif
  44
  45 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  46
  47 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  48
  49
  50 #else
  51
  52
  53 #define get_mirrored_bank(bank) (-1)
  54
  55 #define is_hreg_mirrored(rs, bank, hreg) (0)
  56
  57 #endif
  58
  59
  60 /* If the bank is mirrored return the true logical bank that the register in the
  61  * physical register bank is allocated to.
  62  */
  63 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  64         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  65 }
  66
  67 /*
  68  * Every hardware register belongs to a register type or register bank. bank 0
  69  * contains the int registers, bank 1 contains the fp registers.
  70  * int registers are used 99% of the time, so they are special cased in a lot of
  71  * places.
  72  */
  73
  74 static const int regbank_size [] = {
  75         MONO_MAX_IREGS,
  76         MONO_MAX_FREGS,
  77         MONO_MAX_IREGS,
  78         MONO_MAX_IREGS,
  79         MONO_MAX_XREGS
  80 };
  81
  82 static const int regbank_load_ops [] = {
  83         OP_LOADR_MEMBASE,
  84         OP_LOADR8_MEMBASE,
  85         OP_LOADR_MEMBASE,
  86         OP_LOADR_MEMBASE,
  87         OP_LOADX_MEMBASE
  88 };
  89
  90 static const int regbank_store_ops [] = {
  91         OP_STORER_MEMBASE_REG,
  92         OP_STORER8_MEMBASE_REG,
  93         OP_STORER_MEMBASE_REG,
  94         OP_STORER_MEMBASE_REG,
  95         OP_STOREX_MEMBASE
  96 };
  97
  98 static const int regbank_move_ops [] = {
  99         OP_MOVE,
 100         OP_FMOVE,
 101         OP_MOVE,
 102         OP_MOVE,
 103         OP_XMOVE
 104 };
 105
 106 #define regmask(reg) (((regmask_t)1) << (reg))
 107
 108 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 109 static const regmask_t regbank_callee_saved_regs [] = {
 110         MONO_ARCH_CALLEE_SAVED_REGS,
 111         MONO_ARCH_CALLEE_SAVED_FREGS,
 112         MONO_ARCH_CALLEE_SAVED_REGS,
 113         MONO_ARCH_CALLEE_SAVED_REGS,
 114         MONO_ARCH_CALLEE_SAVED_XREGS,
 115 };
 116 #endif
 117
 118 static const regmask_t regbank_callee_regs [] = {
 119         MONO_ARCH_CALLEE_REGS,
 120         MONO_ARCH_CALLEE_FREGS,
 121         MONO_ARCH_CALLEE_REGS,
 122         MONO_ARCH_CALLEE_REGS,
 123         MONO_ARCH_CALLEE_XREGS,
 124 };
 125
 126 static const int regbank_spill_var_size[] = {
 127         sizeof (mgreg_t),
 128         sizeof (double),
 129         sizeof (mgreg_t),
 130         sizeof (mgreg_t),
 131         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 132 };
 133
 134 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 135
 136 static inline void
 137 mono_regstate_assign (MonoRegState *rs)
 138 {
 139 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 140         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 141          * if the values here are not the same.
 142          */
 143         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 144         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 145         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 146 #endif
 147
 148         if (rs->next_vreg > rs->vassign_size) {
 149                 g_free (rs->vassign);
 150                 rs->vassign_size = MAX (rs->next_vreg, 256);
 151                 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
 152         }
 153
 154         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 155         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 156
 157         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 158         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 159
 160 #ifdef MONO_ARCH_NEED_SIMD_BANK
 161         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 162         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 163 #endif
 164 }
 165
 166 static inline int
 167 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 168 {
 169         regmask_t mask = allow & rs->ifree_mask;
 170
 171 #if defined(__x86_64__) && defined(__GNUC__)
 172  {
 173         guint64 i;
 174
 175         if (mask == 0)
 176                 return -1;
 177
 178         __asm__("bsfq %1,%0\n\t"
 179                         : "=r" (i) : "rm" (mask));
 180
 181         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 182         return i;
 183  }
 184 #else
 185         int i;
 186
 187         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 188                 if (mask & ((regmask_t)1 << i)) {
 189                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 190                         return i;
 191                 }
 192         }
 193         return -1;
 194 #endif
 195 }
 196
 197 static inline void
 198 mono_regstate_free_int (MonoRegState *rs, int reg)
 199 {
 200         if (reg >= 0) {
 201                 rs->ifree_mask |= (regmask_t)1 << reg;
 202                 rs->isymbolic [reg] = 0;
 203         }
 204 }
 205
 206 static inline int
 207 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 208 {
 209         int i;
 210         int mirrored_bank;
 211         regmask_t mask = allow & rs->free_mask [bank];
 212         for (i = 0; i < regbank_size [bank]; ++i) {
 213                 if (mask & ((regmask_t)1 << i)) {
 214                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 215
 216                         mirrored_bank = get_mirrored_bank (bank);
 217                         if (mirrored_bank == -1)
 218                                 return i;
 219
 220                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 221                         return i;
 222                 }
 223         }
 224         return -1;
 225 }
 226
 227 static inline void
 228 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 229 {
 230         int mirrored_bank;
 231
 232         if (reg >= 0) {
 233                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 234                 rs->symbolic [bank][reg] = 0;
 235
 236                 mirrored_bank = get_mirrored_bank (bank);
 237                 if (mirrored_bank == -1)
 238                         return;
 239                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 240                 rs->symbolic [mirrored_bank][reg] = 0;
 241         }
 242 }
 243
 244 const char*
 245 mono_regname_full (int reg, int bank)
 246 {
 247         if (G_UNLIKELY (bank)) {
 248 #if MONO_ARCH_NEED_SIMD_BANK
 249                 if (bank == MONO_REG_SIMD)
 250                         return mono_arch_xregname (reg);
 251 #endif
 252                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 253                         return mono_arch_regname (reg);
 254                 g_assert (bank == MONO_REG_DOUBLE);
 255                 return mono_arch_fregname (reg);
 256         } else {
 257                 return mono_arch_regname (reg);
 258         }
 259 }
 260
 261 void
 262 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 263 {
 264         guint32 regpair;
 265
 266         regpair = (((guint32)hreg) << 24) + vreg;
 267         if (G_UNLIKELY (bank)) {
 268                 g_assert (vreg >= regbank_size [bank]);
 269                 g_assert (hreg < regbank_size [bank]);
 270                 call->used_fregs |= 1 << hreg;
 271                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 272         } else {
 273                 g_assert (vreg >= MONO_MAX_IREGS);
 274                 g_assert (hreg < MONO_MAX_IREGS);
 275                 call->used_iregs |= 1 << hreg;
 276                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 277         }
 278 }
 279
 280 /*
 281  * mono_call_inst_add_outarg_vt:
 282  *
 283  *   Register OUTARG_VT as belonging to CALL.
 284  */
 285 void
 286 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 287 {
 288         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 289 }
 290
 291 static void
 292 resize_spill_info (MonoCompile *cfg, int bank)
 293 {
 294         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 295         int orig_len = cfg->spill_info_len [bank];
 296         int new_len = orig_len ? orig_len * 2 : 16;
 297         MonoSpillInfo *new_info;
 298         int i;
 299
 300         g_assert (bank < MONO_NUM_REGBANKS);
 301
 302         new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 303         if (orig_info)
 304                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 305         for (i = orig_len; i < new_len; ++i)
 306                 new_info [i].offset = -1;
 307
 308         cfg->spill_info [bank] = new_info;
 309         cfg->spill_info_len [bank] = new_len;
 310 }
 311
 312 /*
 313  * returns the offset used by spillvar. It allocates a new
 314  * spill variable if necessary.
 315  */
 316 static inline int
 317 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 318 {
 319         MonoSpillInfo *info;
 320         int size;
 321
 322         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 323                 while (spillvar >= cfg->spill_info_len [bank])
 324                         resize_spill_info (cfg, bank);
 325         }
 326
 327         /*
 328          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 329          */
 330         info = &cfg->spill_info [bank][spillvar];
 331         if (info->offset == -1) {
 332                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 333                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 334
 335                 g_assert (bank < MONO_NUM_REGBANKS);
 336                 if (G_UNLIKELY (bank))
 337                         size = regbank_spill_var_size [bank];
 338                 else
 339                         size = sizeof (mgreg_t);
 340
 341                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 342                         cfg->stack_offset += size - 1;
 343                         cfg->stack_offset &= ~(size - 1);
 344                         info->offset = cfg->stack_offset;
 345                         cfg->stack_offset += size;
 346                 } else {
 347                         cfg->stack_offset += size - 1;
 348                         cfg->stack_offset &= ~(size - 1);
 349                         cfg->stack_offset += size;
 350                         info->offset = - cfg->stack_offset;
 351                 }
 352         }
 353
 354         return info->offset;
 355 }
 356
 357 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 358 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 359 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 360 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 361 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 362 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 363
 364 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 365 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 366 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 367 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 368 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 369
 370 #ifndef MONO_ARCH_INST_IS_FLOAT
 371 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 372 #endif
 373
 374 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 375 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 376 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 377 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 378 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 379
 380 #define reg_is_simd(desc) ((desc) == 'x')
 381
 382 #ifdef MONO_ARCH_NEED_SIMD_BANK
 383
 384 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 385
 386 #else
 387
 388 #define reg_bank(desc) reg_is_fp ((desc))
 389
 390 #endif
 391
 392 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 393 #define sreg1_bank(spec) sreg_bank (0, (spec))
 394 #define sreg2_bank(spec) sreg_bank (1, (spec))
 395 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 396
 397 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 398 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 399 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 400 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 401
 402 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 403
 404 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 405 #undef is_global_ireg
 406 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 407 #endif
 408
 409 typedef struct {
 410         int born_in;
 411         int killed_in;
 412         /* Not (yet) used */
 413         //int last_use;
 414         //int prev_use;
 415         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 416 } RegTrack;
 417
 418 #if !defined(DISABLE_LOGGING)
 419
 420 void
 421 mono_print_ins_index (int i, MonoInst *ins)
 422 {
 423         GString *buf = mono_print_ins_index_strbuf (i, ins);
 424         printf ("%s\n", buf->str);
 425         g_string_free (buf, TRUE);
 426 }
 427
 428 GString *
 429 mono_print_ins_index_strbuf (int i, MonoInst *ins)
 430 {
 431         const char *spec = ins_get_spec (ins->opcode);
 432         GString *sbuf = g_string_new (NULL);
 433         int num_sregs, j;
 434         int sregs [MONO_MAX_SRC_REGS];
 435
 436         if (i != -1)
 437                 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
 438         else
 439                 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
 440         if (spec == MONO_ARCH_CPU_SPEC) {
 441                 gboolean dest_base = FALSE;
 442                 switch (ins->opcode) {
 443                 case OP_STOREV_MEMBASE:
 444                         dest_base = TRUE;
 445                         break;
 446                 default:
 447                         break;
 448                 }
 449
 450                 /* This is a lowered opcode */
 451                 if (ins->dreg != -1) {
 452                         if (dest_base)
 453                                 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 454                         else
 455                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 456                 }
 457                 if (ins->sreg1 != -1)
 458                         g_string_append_printf (sbuf, " R%d", ins->sreg1);
 459                 if (ins->sreg2 != -1)
 460                         g_string_append_printf (sbuf, " R%d", ins->sreg2);
 461                 if (ins->sreg3 != -1)
 462                         g_string_append_printf (sbuf, " R%d", ins->sreg3);
 463
 464                 switch (ins->opcode) {
 465                 case OP_LBNE_UN:
 466                 case OP_LBEQ:
 467                 case OP_LBLT:
 468                 case OP_LBLT_UN:
 469                 case OP_LBGT:
 470                 case OP_LBGT_UN:
 471                 case OP_LBGE:
 472                 case OP_LBGE_UN:
 473                 case OP_LBLE:
 474                 case OP_LBLE_UN:
 475                         if (!ins->inst_false_bb)
 476                                 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 477                         else
 478                                 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 479                         break;
 480                 case OP_PHI:
 481                 case OP_VPHI:
 482                 case OP_XPHI:
 483                 case OP_FPHI: {
 484                         int i;
 485                         g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
 486                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 487                                 if (i)
 488                                         g_string_append_printf (sbuf, ", ");
 489                                 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
 490                         }
 491                         g_string_append_printf (sbuf, ")]");
 492                         break;
 493                 }
 494                 case OP_LDADDR:
 495                 case OP_OUTARG_VTRETADDR:
 496                         g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
 497                         break;
 498                 case OP_REGOFFSET:
 499                 case OP_GSHAREDVT_ARG_REGOFFSET:
 500                         g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
 501                         break;
 502                 case OP_ISINST:
 503                 case OP_CASTCLASS:
 504                         g_string_append_printf (sbuf, " %s", ins->klass->name);
 505                         break;
 506                 default:
 507                         break;
 508                 }
 509
 510                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 511                 return sbuf;
 512         }
 513
 514         if (spec [MONO_INST_DEST]) {
 515                 int bank = dreg_bank (spec);
 516                 if (is_soft_reg (ins->dreg, bank)) {
 517                         if (spec [MONO_INST_DEST] == 'b') {
 518                                 if (ins->inst_offset == 0)
 519                                         g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
 520                                 else
 521                                         g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 522                         }
 523                         else
 524                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 525                 } else if (spec [MONO_INST_DEST] == 'b') {
 526                         if (ins->inst_offset == 0)
 527                                 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
 528                         else
 529                                 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 530                 } else
 531                         g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
 532         }
 533         if (spec [MONO_INST_SRC1]) {
 534                 int bank = sreg1_bank (spec);
 535                 if (is_soft_reg (ins->sreg1, bank)) {
 536                         if (spec [MONO_INST_SRC1] == 'b')
 537                                 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 538                         else
 539                                 g_string_append_printf (sbuf, " R%d", ins->sreg1);
 540                 } else if (spec [MONO_INST_SRC1] == 'b')
 541                         g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 542                 else
 543                         g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
 544         }
 545         num_sregs = mono_inst_get_src_registers (ins, sregs);
 546         for (j = 1; j < num_sregs; ++j) {
 547                 int bank = sreg_bank (j, spec);
 548                 if (is_soft_reg (sregs [j], bank))
 549                         g_string_append_printf (sbuf, " R%d", sregs [j]);
 550                 else
 551                         g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
 552         }
 553
 554         switch (ins->opcode) {
 555         case OP_ICONST:
 556                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
 557                 break;
 558 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 559         case OP_X86_PUSH_IMM:
 560 #endif
 561         case OP_ICOMPARE_IMM:
 562         case OP_COMPARE_IMM:
 563         case OP_IADD_IMM:
 564         case OP_ISUB_IMM:
 565         case OP_IAND_IMM:
 566         case OP_IOR_IMM:
 567         case OP_IXOR_IMM:
 568         case OP_SUB_IMM:
 569         case OP_STORE_MEMBASE_IMM:
 570                 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
 571                 break;
 572         case OP_ADD_IMM:
 573         case OP_LADD_IMM:
 574                 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
 575                 break;
 576         case OP_I8CONST:
 577                 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
 578                 break;
 579         case OP_R8CONST:
 580                 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
 581                 break;
 582         case OP_R4CONST:
 583                 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
 584                 break;
 585         case OP_CALL:
 586         case OP_CALL_MEMBASE:
 587         case OP_CALL_REG:
 588         case OP_FCALL:
 589         case OP_LCALL:
 590         case OP_VCALL:
 591         case OP_VCALL_REG:
 592         case OP_VCALL_MEMBASE:
 593         case OP_VCALL2:
 594         case OP_VCALL2_REG:
 595         case OP_VCALL2_MEMBASE:
 596         case OP_VOIDCALL:
 597         case OP_VOIDCALL_MEMBASE:
 598         case OP_TAILCALL: {
 599                 MonoCallInst *call = (MonoCallInst*)ins;
 600                 GSList *list;
 601
 602                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 603                         /*
 604                          * These are lowered opcodes, but they are in the .md files since the old
 605                          * JIT passes them to backends.
 606                          */
 607                         if (ins->dreg != -1)
 608                                 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
 609                 }
 610
 611                 if (call->method) {
 612                         char *full_name = mono_method_full_name (call->method, TRUE);
 613                         g_string_append_printf (sbuf, " [%s]", full_name);
 614                         g_free (full_name);
 615                 } else if (call->fptr_is_patch) {
 616                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 617
 618                         g_string_append_printf (sbuf, " ");
 619                         mono_print_ji (ji);
 620                 } else if (call->fptr) {
 621                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 622                         if (info)
 623                                 g_string_append_printf (sbuf, " [%s]", info->name);
 624                 }
 625
 626                 list = call->out_ireg_args;
 627                 while (list) {
 628                         guint32 regpair;
 629                         int reg, hreg;
 630
 631                         regpair = (guint32)(gssize)(list->data);
 632                         hreg = regpair >> 24;
 633                         reg = regpair & 0xffffff;
 634
 635                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
 636
 637                         list = g_slist_next (list);
 638                 }
 639                 list = call->out_freg_args;
 640                 while (list) {
 641                         guint32 regpair;
 642                         int reg, hreg;
 643
 644                         regpair = (guint32)(gssize)(list->data);
 645                         hreg = regpair >> 24;
 646                         reg = regpair & 0xffffff;
 647
 648                         g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
 649
 650                         list = g_slist_next (list);
 651                 }
 652                 break;
 653         }
 654         case OP_BR:
 655         case OP_CALL_HANDLER:
 656                 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
 657                 break;
 658         case OP_IBNE_UN:
 659         case OP_IBEQ:
 660         case OP_IBLT:
 661         case OP_IBLT_UN:
 662         case OP_IBGT:
 663         case OP_IBGT_UN:
 664         case OP_IBGE:
 665         case OP_IBGE_UN:
 666         case OP_IBLE:
 667         case OP_IBLE_UN:
 668         case OP_LBNE_UN:
 669         case OP_LBEQ:
 670         case OP_LBLT:
 671         case OP_LBLT_UN:
 672         case OP_LBGT:
 673         case OP_LBGT_UN:
 674         case OP_LBGE:
 675         case OP_LBGE_UN:
 676         case OP_LBLE:
 677         case OP_LBLE_UN:
 678                 if (!ins->inst_false_bb)
 679                         g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 680                 else
 681                         g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 682                 break;
 683         case OP_LIVERANGE_START:
 684         case OP_LIVERANGE_END:
 685         case OP_GC_LIVENESS_DEF:
 686         case OP_GC_LIVENESS_USE:
 687                 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
 688                 break;
 689         case OP_IL_SEQ_POINT:
 690         case OP_SEQ_POINT:
 691                 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
 692                 break;
 693         case OP_COND_EXC_EQ:
 694         case OP_COND_EXC_GE:
 695         case OP_COND_EXC_GT:
 696         case OP_COND_EXC_LE:
 697         case OP_COND_EXC_LT:
 698         case OP_COND_EXC_NE_UN:
 699         case OP_COND_EXC_GE_UN:
 700         case OP_COND_EXC_GT_UN:
 701         case OP_COND_EXC_LE_UN:
 702         case OP_COND_EXC_LT_UN:
 703         case OP_COND_EXC_OV:
 704         case OP_COND_EXC_NO:
 705         case OP_COND_EXC_C:
 706         case OP_COND_EXC_NC:
 707         case OP_COND_EXC_IEQ:
 708         case OP_COND_EXC_IGE:
 709         case OP_COND_EXC_IGT:
 710         case OP_COND_EXC_ILE:
 711         case OP_COND_EXC_ILT:
 712         case OP_COND_EXC_INE_UN:
 713         case OP_COND_EXC_IGE_UN:
 714         case OP_COND_EXC_IGT_UN:
 715         case OP_COND_EXC_ILE_UN:
 716         case OP_COND_EXC_ILT_UN:
 717         case OP_COND_EXC_IOV:
 718         case OP_COND_EXC_INO:
 719         case OP_COND_EXC_IC:
 720         case OP_COND_EXC_INC:
 721                 g_string_append_printf (sbuf, " %s", ins->inst_p1);
 722                 break;
 723         default:
 724                 break;
 725         }
 726
 727         if (spec [MONO_INST_CLOB])
 728                 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
 729         return sbuf;
 730 }
 731
 732 static void
 733 print_regtrack (RegTrack *t, int num)
 734 {
 735         int i;
 736         char buf [32];
 737         const char *r;
 738
 739         for (i = 0; i < num; ++i) {
 740                 if (!t [i].born_in)
 741                         continue;
 742                 if (i >= MONO_MAX_IREGS) {
 743                         g_snprintf (buf, sizeof(buf), "R%d", i);
 744                         r = buf;
 745                 } else
 746                         r = mono_arch_regname (i);
 747                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 748         }
 749 }
 750 #else
 751
 752 void
 753 mono_print_ins_index (int i, MonoInst *ins)
 754 {
 755 }
 756 #endif /* !defined(DISABLE_LOGGING) */
 757
 758 void
 759 mono_print_ins (MonoInst *ins)
 760 {
 761         mono_print_ins_index (-1, ins);
 762 }
 763
 764 static inline void
 765 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 766 {
 767         /*
 768          * If this function is called multiple times, the new instructions are inserted
 769          * in the proper order.
 770          */
 771         mono_bblock_insert_before_ins (bb, ins, to_insert);
 772 }
 773
 774 static inline void
 775 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 776 {
 777         /*
 778          * If this function is called multiple times, the new instructions are inserted in
 779          * proper order.
 780          */
 781         mono_bblock_insert_after_ins (bb, *last, to_insert);
 782
 783         *last = to_insert;
 784 }
 785
 786 static inline int
 787 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 788 {
 789         if (vreg_is_ref (cfg, reg))
 790                 return MONO_REG_INT_REF;
 791         else if (vreg_is_mp (cfg, reg))
 792                 return MONO_REG_INT_MP;
 793         else
 794                 return bank;
 795 }
 796
 797 /*
 798  * Force the spilling of the variable in the symbolic register 'reg', and free
 799  * the hreg it was assigned to.
 800  */
 801 static void
 802 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 803 {
 804         MonoInst *load;
 805         int i, sel, spill;
 806         MonoRegState *rs = cfg->rs;
 807
 808         sel = rs->vassign [reg];
 809
 810         /* the vreg we need to spill lives in another logical reg bank */
 811         bank = translate_bank (cfg->rs, bank, sel);
 812
 813         /*i = rs->isymbolic [sel];
 814         g_assert (i == reg);*/
 815         i = reg;
 816         spill = ++cfg->spill_count;
 817         rs->vassign [i] = -spill - 1;
 818         if (G_UNLIKELY (bank))
 819                 mono_regstate_free_general (rs, sel, bank);
 820         else
 821                 mono_regstate_free_int (rs, sel);
 822         /* we need to create a spill var and insert a load to sel after the current instruction */
 823         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 824         load->dreg = sel;
 825         load->inst_basereg = cfg->frame_reg;
 826         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 827         insert_after_ins (bb, ins, last, load);
 828         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 829         if (G_UNLIKELY (bank))
 830                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 831         else
 832                 i = mono_regstate_alloc_int (rs, regmask (sel));
 833         g_assert (i == sel);
 834
 835         if (G_UNLIKELY (bank))
 836                 mono_regstate_free_general (rs, sel, bank);
 837         else
 838                 mono_regstate_free_int (rs, sel);
 839 }
 840
 841 static int
 842 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 843 {
 844         MonoInst *load;
 845         int i, sel, spill, num_sregs;
 846         int sregs [MONO_MAX_SRC_REGS];
 847         MonoRegState *rs = cfg->rs;
 848
 849         g_assert (bank < MONO_NUM_REGBANKS);
 850
 851         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 852         /* exclude the registers in the current instruction */
 853         num_sregs = mono_inst_get_src_registers (ins, sregs);
 854         for (i = 0; i < num_sregs; ++i) {
 855                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 856                         if (is_soft_reg (sregs [i], bank))
 857                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 858                         else
 859                                 regmask &= ~ (regmask (sregs [i]));
 860                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 861                 }
 862         }
 863         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 864                 regmask &= ~ (regmask (ins->dreg));
 865                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 866         }
 867
 868         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 869         g_assert (regmask); /* need at least a register we can free */
 870         sel = 0;
 871         /* we should track prev_use and spill the register that's farther */
 872         if (G_UNLIKELY (bank)) {
 873                 for (i = 0; i < regbank_size [bank]; ++i) {
 874                         if (regmask & (regmask (i))) {
 875                                 sel = i;
 876
 877                                 /* the vreg we need to load lives in another logical bank */
 878                                 bank = translate_bank (cfg->rs, bank, sel);
 879
 880                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 881                                 break;
 882                         }
 883                 }
 884
 885                 i = rs->symbolic [bank] [sel];
 886                 spill = ++cfg->spill_count;
 887                 rs->vassign [i] = -spill - 1;
 888                 mono_regstate_free_general (rs, sel, bank);
 889         }
 890         else {
 891                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 892                         if (regmask & (regmask (i))) {
 893                                 sel = i;
 894                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 895                                 break;
 896                         }
 897                 }
 898
 899                 i = rs->isymbolic [sel];
 900                 spill = ++cfg->spill_count;
 901                 rs->vassign [i] = -spill - 1;
 902                 mono_regstate_free_int (rs, sel);
 903         }
 904
 905         /* we need to create a spill var and insert a load to sel after the current instruction */
 906         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 907         load->dreg = sel;
 908         load->inst_basereg = cfg->frame_reg;
 909         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 910         insert_after_ins (bb, ins, last, load);
 911         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 912         if (G_UNLIKELY (bank))
 913                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 914         else
 915                 i = mono_regstate_alloc_int (rs, regmask (sel));
 916         g_assert (i == sel);
 917
 918         return sel;
 919 }
 920
 921 /*
 922  * free_up_hreg:
 923  *
 924  *   Free up the hreg HREG by spilling the vreg allocated to it.
 925  */
 926 static void
 927 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 928 {
 929         if (G_UNLIKELY (bank)) {
 930                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 931                         bank = translate_bank (cfg->rs, bank, hreg);
 932                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 933                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 934                 }
 935         }
 936         else {
 937                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 938                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 939                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 940                 }
 941         }
 942 }
 943
 944 static MonoInst*
 945 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 946 {
 947         MonoInst *copy;
 948
 949         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 950
 951         copy->dreg = dest;
 952         copy->sreg1 = src;
 953         copy->cil_code = ip;
 954         if (ins) {
 955                 mono_bblock_insert_after_ins (bb, ins, copy);
 956                 *last = copy;
 957         }
 958         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 959         return copy;
 960 }
 961
 962 static inline const char*
 963 regbank_to_string (int bank)
 964 {
 965         if (bank == MONO_REG_INT_REF)
 966                 return "REF ";
 967         else if (bank == MONO_REG_INT_MP)
 968                 return "MP ";
 969         else
 970                 return "";
 971 }
 972
 973 static void
 974 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 975 {
 976         MonoInst *store, *def;
 977
 978         bank = get_vreg_bank (cfg, prev_reg, bank);
 979
 980         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 981         store->sreg1 = reg;
 982         store->inst_destbasereg = cfg->frame_reg;
 983         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 984         if (ins) {
 985                 mono_bblock_insert_after_ins (bb, ins, store);
 986                 *last = store;
 987         } else if (insert_before) {
 988                 insert_before_ins (bb, insert_before, store);
 989         } else {
 990                 g_assert_not_reached ();
 991         }
 992         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 993
 994         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 995                 g_assert (prev_reg != -1);
 996                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 997                 def->inst_c0 = spill;
 998                 def->inst_c1 = bank;
 999                 mono_bblock_insert_after_ins (bb, store, def);
1000         }
1001 }
1002
1003 /* flags used in reginfo->flags */
1004 enum {
1005         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
1006         MONO_FP_NEEDS_SPILL                     = regmask (1),
1007         MONO_FP_NEEDS_LOAD                      = regmask (2)
1008 };
1009
1010 static inline int
1011 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1012 {
1013         int val;
1014
1015         if (info && info->preferred_mask) {
1016                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1017                 if (val >= 0) {
1018                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1019                         return val;
1020                 }
1021         }
1022
1023         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1024         if (val < 0)
1025                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1026
1027         return val;
1028 }
1029
1030 static inline int
1031 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1032 {
1033         int val;
1034
1035         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1036
1037         if (val < 0)
1038                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1039
1040         return val;
1041 }
1042
1043 static inline int
1044 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1045 {
1046         if (G_UNLIKELY (bank))
1047                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1048         else
1049                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1050 }
1051
1052 static inline void
1053 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1054 {
1055         if (G_UNLIKELY (bank)) {
1056                 int mirrored_bank;
1057
1058                 g_assert (reg >= regbank_size [bank]);
1059                 g_assert (hreg < regbank_size [bank]);
1060                 g_assert (! is_global_freg (hreg));
1061
1062                 rs->vassign [reg] = hreg;
1063                 rs->symbolic [bank] [hreg] = reg;
1064                 rs->free_mask [bank] &= ~ (regmask (hreg));
1065
1066                 mirrored_bank = get_mirrored_bank (bank);
1067                 if (mirrored_bank == -1)
1068                         return;
1069
1070                 /* Make sure the other logical reg bank that this bank shares
1071                  * a single hard reg bank knows that this hard reg is not free.
1072                  */
1073                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1074
1075                 /* Mark the other logical bank that the this bank shares
1076                  * a single hard reg bank with as mirrored.
1077                  */
1078                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1079
1080         }
1081         else {
1082                 g_assert (reg >= MONO_MAX_IREGS);
1083                 g_assert (hreg < MONO_MAX_IREGS);
1084 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1085                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1086                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1087                 g_assert (! is_global_ireg (hreg));
1088 #endif
1089
1090                 rs->vassign [reg] = hreg;
1091                 rs->isymbolic [hreg] = reg;
1092                 rs->ifree_mask &= ~ (regmask (hreg));
1093         }
1094 }
1095
1096 static inline regmask_t
1097 get_callee_mask (const char spec)
1098 {
1099         if (G_UNLIKELY (reg_bank (spec)))
1100                 return regbank_callee_regs [reg_bank (spec)];
1101         return MONO_ARCH_CALLEE_REGS;
1102 }
1103
1104 static gint8 desc_to_fixed_reg [256];
1105 static gboolean desc_to_fixed_reg_inited = FALSE;
1106
1107 /*
1108  * Local register allocation.
1109  * We first scan the list of instructions and we save the liveness info of
1110  * each register (when the register is first used, when it's value is set etc.).
1111  * We also reverse the list of instructions because assigning registers backwards allows
1112  * for more tricks to be used.
1113  */
1114 void
1115 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1116 {
1117         MonoInst *ins, *prev, *last;
1118         MonoInst **tmp;
1119         MonoRegState *rs = cfg->rs;
1120         int i, j, val, max;
1121         RegTrack *reginfo;
1122         const char *spec;
1123         unsigned char spec_src1, spec_dest;
1124         int bank = 0;
1125 #if MONO_ARCH_USE_FPSTACK
1126         gboolean has_fp = FALSE;
1127         int fpstack [8];
1128         int sp = 0;
1129 #endif
1130         int num_sregs = 0;
1131         int sregs [MONO_MAX_SRC_REGS];
1132
1133         if (!bb->code)
1134                 return;
1135
1136         if (!desc_to_fixed_reg_inited) {
1137                 for (i = 0; i < 256; ++i)
1138                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1139                 desc_to_fixed_reg_inited = TRUE;
1140
1141                 /* Validate the cpu description against the info in mini-ops.h */
1142 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1143                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1144                         const char *ispec;
1145
1146                         spec = ins_get_spec (i);
1147                         ispec = INS_INFO (i);
1148
1149                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1150                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1151                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1152                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1153                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1154                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1155                 }
1156 #endif
1157         }
1158
1159         rs->next_vreg = bb->max_vreg;
1160         mono_regstate_assign (rs);
1161
1162         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1163         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1164                 rs->free_mask [i] = regbank_callee_regs [i];
1165
1166         max = rs->next_vreg;
1167
1168         if (cfg->reginfo && cfg->reginfo_len < max)
1169                 cfg->reginfo = NULL;
1170
1171         reginfo = (RegTrack *)cfg->reginfo;
1172         if (!reginfo) {
1173                 cfg->reginfo_len = MAX (1024, max * 2);
1174                 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1175                 cfg->reginfo = reginfo;
1176         }
1177         else
1178                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1179
1180         if (cfg->verbose_level > 1) {
1181                 /* print_regtrack reads the info of all variables */
1182                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1183         }
1184
1185         /*
1186          * For large methods, next_vreg can be very large, so g_malloc0 time can
1187          * be prohibitive. So we manually init the reginfo entries used by the
1188          * bblock.
1189          */
1190         for (ins = bb->code; ins; ins = ins->next) {
1191                 gboolean modify = FALSE;
1192
1193                 spec = ins_get_spec (ins->opcode);
1194
1195                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1196                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1197 #if SIZEOF_REGISTER == 4
1198                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1199                                 /**
1200                                  * In the new IR, the two vregs of the regpair do not alias the
1201                                  * original long vreg. shift the vreg here so the rest of the
1202                                  * allocator doesn't have to care about it.
1203                                  */
1204                                 ins->dreg ++;
1205                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1206                         }
1207 #endif
1208                 }
1209
1210                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1211                 for (j = 0; j < num_sregs; ++j) {
1212                         g_assert (sregs [j] != -1);
1213                         if (sregs [j] < max) {
1214                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1215 #if SIZEOF_REGISTER == 4
1216                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1217                                         sregs [j]++;
1218                                         modify = TRUE;
1219                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1220                                 }
1221 #endif
1222                         }
1223                 }
1224                 if (modify)
1225                         mono_inst_set_src_registers (ins, sregs);
1226         }
1227
1228         /*if (cfg->opt & MONO_OPT_COPYPROP)
1229                 local_copy_prop (cfg, ins);*/
1230
1231         i = 1;
1232         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1233         /* forward pass on the instructions to collect register liveness info */
1234         MONO_BB_FOR_EACH_INS (bb, ins) {
1235                 spec = ins_get_spec (ins->opcode);
1236                 spec_dest = spec [MONO_INST_DEST];
1237
1238                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1239                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1240                 }
1241
1242                 DEBUG (mono_print_ins_index (i, ins));
1243
1244                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1245
1246 #if MONO_ARCH_USE_FPSTACK
1247                 if (dreg_is_fp (spec)) {
1248                         has_fp = TRUE;
1249                 } else {
1250                         for (j = 0; j < num_sregs; ++j) {
1251                                 if (sreg_is_fp (j, spec))
1252                                         has_fp = TRUE;
1253                         }
1254                 }
1255 #endif
1256
1257                 for (j = 0; j < num_sregs; ++j) {
1258                         int sreg = sregs [j];
1259                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1260                         if (sreg_spec) {
1261                                 bank = sreg_bank (j, spec);
1262                                 g_assert (sreg != -1);
1263                                 if (is_soft_reg (sreg, bank))
1264                                         /* This means the vreg is not local to this bb */
1265                                         g_assert (reginfo [sreg].born_in > 0);
1266                                 rs->vassign [sreg] = -1;
1267                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1268                                 //reginfo [ins->sreg2].last_use = i;
1269                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1270                                         /* The virtual register is allocated sequentially */
1271                                         rs->vassign [sreg + 1] = -1;
1272                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1273                                         //reginfo [ins->sreg2 + 1].last_use = i;
1274                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1275                                                 reginfo [sreg + 1].born_in = i;
1276                                 }
1277                         } else {
1278                                 sregs [j] = -1;
1279                         }
1280                 }
1281                 mono_inst_set_src_registers (ins, sregs);
1282
1283                 if (spec_dest) {
1284                         int dest_dreg;
1285
1286                         bank = dreg_bank (spec);
1287                         if (spec_dest != 'b') /* it's not just a base register */
1288                                 reginfo [ins->dreg].killed_in = i;
1289                         g_assert (ins->dreg != -1);
1290                         rs->vassign [ins->dreg] = -1;
1291                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1292                         //reginfo [ins->dreg].last_use = i;
1293                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1294                                 reginfo [ins->dreg].born_in = i;
1295
1296                         dest_dreg = desc_to_fixed_reg [spec_dest];
1297                         if (dest_dreg != -1)
1298                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1299
1300 #ifdef MONO_ARCH_INST_FIXED_MASK
1301                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1302 #endif
1303
1304                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1305                                 /* The virtual register is allocated sequentially */
1306                                 rs->vassign [ins->dreg + 1] = -1;
1307                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1308                                 //reginfo [ins->dreg + 1].last_use = i;
1309                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1310                                         reginfo [ins->dreg + 1].born_in = i;
1311                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1312                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1313                         }
1314                 } else {
1315                         ins->dreg = -1;
1316                 }
1317
1318                 ++i;
1319         }
1320
1321         tmp = &last;
1322
1323         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1324         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1325                 int prev_dreg;
1326                 int dest_dreg, clob_reg;
1327                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1328                 int dreg_high, sreg1_high;
1329                 regmask_t dreg_mask, mask;
1330                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1331                 regmask_t dreg_fixed_mask;
1332                 const unsigned char *ip;
1333                 --i;
1334                 spec = ins_get_spec (ins->opcode);
1335                 spec_src1 = spec [MONO_INST_SRC1];
1336                 spec_dest = spec [MONO_INST_DEST];
1337                 prev_dreg = -1;
1338                 clob_reg = -1;
1339                 dest_dreg = -1;
1340                 dreg_high = -1;
1341                 sreg1_high = -1;
1342                 dreg_mask = get_callee_mask (spec_dest);
1343                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1344                         prev_sregs [j] = -1;
1345                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1346                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1347 #ifdef MONO_ARCH_INST_FIXED_MASK
1348                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1349 #else
1350                         sreg_fixed_masks [j] = 0;
1351 #endif
1352                 }
1353
1354                 DEBUG (printf ("processing:"));
1355                 DEBUG (mono_print_ins_index (i, ins));
1356
1357                 ip = ins->cil_code;
1358
1359                 last = ins;
1360
1361                 /*
1362                  * FIXED REGS
1363                  */
1364                 dest_dreg = desc_to_fixed_reg [spec_dest];
1365                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1366                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1367
1368 #ifdef MONO_ARCH_INST_FIXED_MASK
1369                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1370 #else
1371                 dreg_fixed_mask = 0;
1372 #endif
1373
1374                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1375
1376                 /*
1377                  * TRACK FIXED SREG2, 3, ...
1378                  */
1379                 for (j = 1; j < num_sregs; ++j) {
1380                         int sreg = sregs [j];
1381                         int dest_sreg = dest_sregs [j];
1382
1383                         if (dest_sreg == -1)
1384                                 continue;
1385
1386                         if (j == 2) {
1387                                 int k;
1388
1389                                 /*
1390                                  * CAS.
1391                                  * We need to special case this, since on x86, there are only 3
1392                                  * free registers, and the code below assigns one of them to
1393                                  * sreg, so we can run out of registers when trying to assign
1394                                  * dreg. Instead, we just set up the register masks, and let the
1395                                  * normal sreg2 assignment code handle this. It would be nice to
1396                                  * do this for all the fixed reg cases too, but there is too much
1397                                  * risk of breakage.
1398                                  */
1399
1400                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1401                                 sreg_masks [j] = regmask (dest_sreg);
1402                                 for (k = 0; k < num_sregs; ++k) {
1403                                         if (k != j)
1404                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1405                                 }
1406
1407                                 /*
1408                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1409                                  */
1410                                 for (k = 0; k < num_sregs; ++k) {
1411                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1412                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1413                                 }
1414
1415                                 /*
1416                                  * We can also run out of registers while processing sreg2 if sreg3 is
1417                                  * assigned to another hreg, so spill sreg3 now.
1418                                  */
1419                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1420                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1421                                 }
1422                                 continue;
1423                         }
1424
1425                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1426                                 if (is_global_ireg (sreg)) {
1427                                         int k;
1428                                         /* Argument already in hard reg, need to copy */
1429                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1430                                         insert_before_ins (bb, ins, copy);
1431                                         for (k = 0; k < num_sregs; ++k) {
1432                                                 if (k != j)
1433                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1434                                         }
1435                                         /* See below */
1436                                         dreg_mask &= ~ (regmask (dest_sreg));
1437                                 } else {
1438                                         val = rs->vassign [sreg];
1439                                         if (val == -1) {
1440                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1441                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1442                                         } else if (val < -1) {
1443                                                 /* FIXME: */
1444                                                 g_assert_not_reached ();
1445                                         } else {
1446                                                 /* Argument already in hard reg, need to copy */
1447                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1448                                                 int k;
1449
1450                                                 insert_before_ins (bb, ins, copy);
1451                                                 for (k = 0; k < num_sregs; ++k) {
1452                                                         if (k != j)
1453                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1454                                                 }
1455                                                 /*
1456                                                  * Prevent the dreg from being allocated to dest_sreg
1457                                                  * too, since it could force sreg1 to be allocated to
1458                                                  * the same reg on x86.
1459                                                  */
1460                                                 dreg_mask &= ~ (regmask (dest_sreg));
1461                                         }
1462                                 }
1463                         } else {
1464                                 gboolean need_spill = TRUE;
1465                                 gboolean need_assign = TRUE;
1466                                 int k;
1467
1468                                 dreg_mask &= ~ (regmask (dest_sreg));
1469                                 for (k = 0; k < num_sregs; ++k) {
1470                                         if (k != j)
1471                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1472                                 }
1473
1474                                 /*
1475                                  * First check if dreg is assigned to dest_sreg2, since we
1476                                  * can't spill a dreg.
1477                                  */
1478                                 if (spec [MONO_INST_DEST])
1479                                         val = rs->vassign [ins->dreg];
1480                                 else
1481                                         val = -1;
1482                                 if (val == dest_sreg && ins->dreg != sreg) {
1483                                         /*
1484                                          * the destination register is already assigned to
1485                                          * dest_sreg2: we need to allocate another register for it
1486                                          * and then copy from this to dest_sreg2.
1487                                          */
1488                                         int new_dest;
1489                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1490                                         g_assert (new_dest >= 0);
1491                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1492
1493                                         prev_dreg = ins->dreg;
1494                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1495                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1496                                         mono_regstate_free_int (rs, dest_sreg);
1497                                         need_spill = FALSE;
1498                                 }
1499
1500                                 if (is_global_ireg (sreg)) {
1501                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1502                                         insert_before_ins (bb, ins, copy);
1503                                         need_assign = FALSE;
1504                                 }
1505                                 else {
1506                                         val = rs->vassign [sreg];
1507                                         if (val == dest_sreg) {
1508                                                 /* sreg2 is already assigned to the correct register */
1509                                                 need_spill = FALSE;
1510                                         } else if (val < -1) {
1511                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1512                                         } else if (val >= 0) {
1513                                                 /* sreg2 already assigned to another register */
1514                                                 /*
1515                                                  * We couldn't emit a copy from val to dest_sreg2, because
1516                                                  * val might be spilled later while processing this
1517                                                  * instruction. So we spill sreg2 so it can be allocated to
1518                                                  * dest_sreg2.
1519                                                  */
1520                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1521                                         }
1522                                 }
1523
1524                                 if (need_spill) {
1525                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1526                                 }
1527
1528                                 if (need_assign) {
1529                                         if (rs->vassign [sreg] < -1) {
1530                                                 int spill;
1531
1532                                                 /* Need to emit a spill store */
1533                                                 spill = - rs->vassign [sreg] - 1;
1534                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1535                                         }
1536                                         /* force-set sreg2 */
1537                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1538                                 }
1539                         }
1540                         sregs [j] = dest_sreg;
1541                 }
1542                 mono_inst_set_src_registers (ins, sregs);
1543
1544                 /*
1545                  * TRACK DREG
1546                  */
1547                 bank = dreg_bank (spec);
1548                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1549                         prev_dreg = ins->dreg;
1550                 }
1551
1552                 if (spec_dest == 'b') {
1553                         /*
1554                          * The dest reg is read by the instruction, not written, so
1555                          * avoid allocating sreg1/sreg2 to the same reg.
1556                          */
1557                         if (dest_sregs [0] != -1)
1558                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1559                         for (j = 1; j < num_sregs; ++j) {
1560                                 if (dest_sregs [j] != -1)
1561                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1562                         }
1563
1564                         val = rs->vassign [ins->dreg];
1565                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1566                                 /* DREG is already allocated to a register needed for sreg1 */
1567                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1568                         }
1569                 }
1570
1571                 /*
1572                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1573                  * various complex situations.
1574                  */
1575                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1576                         guint32 dreg2, dest_dreg2;
1577
1578                         g_assert (is_soft_reg (ins->dreg, bank));
1579
1580                         if (dest_dreg != -1) {
1581                                 if (rs->vassign [ins->dreg] != dest_dreg)
1582                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1583
1584                                 dreg2 = ins->dreg + 1;
1585                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1586                                 if (dest_dreg2 != -1) {
1587                                         if (rs->vassign [dreg2] != dest_dreg2)
1588                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1589                                 }
1590                         }
1591                 }
1592
1593                 if (dreg_fixed_mask) {
1594                         g_assert (!bank);
1595                         if (is_global_ireg (ins->dreg)) {
1596                                 /*
1597                                  * The argument is already in a hard reg, but that reg is
1598                                  * not usable by this instruction, so allocate a new one.
1599                                  */
1600                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1601                                 if (val < 0)
1602                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1603                                 mono_regstate_free_int (rs, val);
1604                                 dest_dreg = val;
1605
1606                                 /* Fall through */
1607                         }
1608                         else
1609                                 dreg_mask &= dreg_fixed_mask;
1610                 }
1611
1612                 if (is_soft_reg (ins->dreg, bank)) {
1613                         val = rs->vassign [ins->dreg];
1614
1615                         if (val < 0) {
1616                                 int spill = 0;
1617                                 if (val < -1) {
1618                                         /* the register gets spilled after this inst */
1619                                         spill = -val -1;
1620                                 }
1621                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1622                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1623                                 if (spill)
1624                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1625                         }
1626
1627                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1628                         ins->dreg = val;
1629                 }
1630
1631                 /* Handle regpairs */
1632                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1633                         int reg2 = prev_dreg + 1;
1634
1635                         g_assert (!bank);
1636                         g_assert (prev_dreg > -1);
1637                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1638                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1639 #ifdef TARGET_X86
1640                         /* bug #80489 */
1641                         mask &= ~regmask (X86_ECX);
1642 #endif
1643                         val = rs->vassign [reg2];
1644                         if (val < 0) {
1645                                 int spill = 0;
1646                                 if (val < -1) {
1647                                         /* the register gets spilled after this inst */
1648                                         spill = -val -1;
1649                                 }
1650                                 val = mono_regstate_alloc_int (rs, mask);
1651                                 if (val < 0)
1652                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1653                                 if (spill)
1654                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1655                         }
1656                         else {
1657                                 if (! (mask & (regmask (val)))) {
1658                                         val = mono_regstate_alloc_int (rs, mask);
1659                                         if (val < 0)
1660                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1661
1662                                         /* Reallocate hreg to the correct register */
1663                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1664
1665                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1666                                 }
1667                         }
1668
1669                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1670                         assign_reg (cfg, rs, reg2, val, bank);
1671
1672                         dreg_high = val;
1673                         ins->backend.reg3 = val;
1674
1675                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1676                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1677                                 mono_regstate_free_int (rs, val);
1678                         }
1679                 }
1680
1681                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1682                         /*
1683                          * In theory, we could free up the hreg even if the vreg is alive,
1684                          * but branches inside bblocks force us to assign the same hreg
1685                          * to a vreg every time it is encountered.
1686                          */
1687                         int dreg = rs->vassign [prev_dreg];
1688                         g_assert (dreg >= 0);
1689                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1690                         if (G_UNLIKELY (bank))
1691                                 mono_regstate_free_general (rs, dreg, bank);
1692                         else
1693                                 mono_regstate_free_int (rs, dreg);
1694                         rs->vassign [prev_dreg] = -1;
1695                 }
1696
1697                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1698                         /* this instruction only outputs to dest_dreg, need to copy */
1699                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1700                         ins->dreg = dest_dreg;
1701
1702                         if (G_UNLIKELY (bank)) {
1703                                 /* the register we need to free up may be used in another logical regbank
1704                                  * so do a translate just in case.
1705                                  */
1706                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1707                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1708                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1709                         }
1710                         else {
1711                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1712                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1713                         }
1714                 }
1715
1716                 if (spec_dest == 'b') {
1717                         /*
1718                          * The dest reg is read by the instruction, not written, so
1719                          * avoid allocating sreg1/sreg2 to the same reg.
1720                          */
1721                         for (j = 0; j < num_sregs; ++j)
1722                                 if (!sreg_bank (j, spec))
1723                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1724                 }
1725
1726                 /*
1727                  * TRACK CLOBBERING
1728                  */
1729                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1730                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1731                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1732                 }
1733
1734                 if (spec [MONO_INST_CLOB] == 'c') {
1735                         int j, s, dreg, dreg2, cur_bank;
1736                         guint64 clob_mask;
1737
1738                         clob_mask = MONO_ARCH_CALLEE_REGS;
1739
1740                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1741                                 /*
1742                                  * Need to avoid spilling the dreg since the dreg is not really
1743                                  * clobbered by the call.
1744                                  */
1745                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1746                                         dreg = rs->vassign [prev_dreg];
1747                                 else
1748                                         dreg = -1;
1749
1750                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1751                                         dreg2 = rs->vassign [prev_dreg + 1];
1752                                 else
1753                                         dreg2 = -1;
1754
1755                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1756                                         s = regmask (j);
1757                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1758                                                 if ((j != dreg) && (j != dreg2))
1759                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1760                                                 else if (rs->isymbolic [j])
1761                                                         /* The hreg is assigned to the dreg of this instruction */
1762                                                         rs->vassign [rs->isymbolic [j]] = -1;
1763                                                 mono_regstate_free_int (rs, j);
1764                                         }
1765                                 }
1766                         }
1767
1768                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1769                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1770                                         clob_mask = regbank_callee_regs [cur_bank];
1771                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1772                                                 dreg = rs->vassign [prev_dreg];
1773                                         else
1774                                                 dreg = -1;
1775
1776                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1777
1778                                                 /* we are looping though the banks in the outer loop
1779                                                  * so, we don't need to deal with mirrored hregs
1780                                                  * because we will get them in one of the other bank passes.
1781                                                  */
1782                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1783                                                         continue;
1784
1785                                                 s = regmask (j);
1786                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1787                                                         if (j != dreg)
1788                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1789                                                         else if (rs->symbolic [cur_bank] [j])
1790                                                                 /* The hreg is assigned to the dreg of this instruction */
1791                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1792                                                         mono_regstate_free_general (rs, j, cur_bank);
1793                                                 }
1794                                         }
1795                                 }
1796                         }
1797                 }
1798
1799                 /*
1800                  * TRACK ARGUMENT REGS
1801                  */
1802                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1803                         MonoCallInst *call = (MonoCallInst*)ins;
1804                         GSList *list;
1805
1806                         /*
1807                          * This needs to be done before assigning sreg1, so sreg1 will
1808                          * not be assigned one of the argument regs.
1809                          */
1810
1811                         /*
1812                          * Assign all registers in call->out_reg_args to the proper
1813                          * argument registers.
1814                          */
1815
1816                         list = call->out_ireg_args;
1817                         if (list) {
1818                                 while (list) {
1819                                         guint32 regpair;
1820                                         int reg, hreg;
1821
1822                                         regpair = (guint32)(gssize)(list->data);
1823                                         hreg = regpair >> 24;
1824                                         reg = regpair & 0xffffff;
1825
1826                                         assign_reg (cfg, rs, reg, hreg, 0);
1827
1828                                         sreg_masks [0] &= ~(regmask (hreg));
1829
1830                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1831
1832                                         list = g_slist_next (list);
1833                                 }
1834                         }
1835
1836                         list = call->out_freg_args;
1837                         if (list) {
1838                                 while (list) {
1839                                         guint32 regpair;
1840                                         int reg, hreg;
1841
1842                                         regpair = (guint32)(gssize)(list->data);
1843                                         hreg = regpair >> 24;
1844                                         reg = regpair & 0xffffff;
1845
1846                                         assign_reg (cfg, rs, reg, hreg, 1);
1847
1848                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1849
1850                                         list = g_slist_next (list);
1851                                 }
1852                         }
1853                 }
1854
1855                 /*
1856                  * TRACK SREG1
1857                  */
1858                 bank = sreg1_bank (spec);
1859                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1860                         int sreg1 = sregs [0];
1861                         int dest_sreg1 = dest_sregs [0];
1862
1863                         g_assert (is_soft_reg (sreg1, bank));
1864
1865                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1866                         if (dest_sreg1 != -1)
1867                                 g_assert (dest_sreg1 == ins->dreg);
1868                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1869                         g_assert (val >= 0);
1870
1871                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1872                                 // FIXME:
1873                                 g_assert_not_reached ();
1874
1875                         assign_reg (cfg, rs, sreg1, val, bank);
1876
1877                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1878
1879                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1880                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1881                         g_assert (val >= 0);
1882
1883                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1884                                 // FIXME:
1885                                 g_assert_not_reached ();
1886
1887                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1888
1889                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1890
1891                         /* Skip rest of this section */
1892                         dest_sregs [0] = -1;
1893                 }
1894
1895                 if (sreg_fixed_masks [0]) {
1896                         g_assert (!bank);
1897                         if (is_global_ireg (sregs [0])) {
1898                                 /*
1899                                  * The argument is already in a hard reg, but that reg is
1900                                  * not usable by this instruction, so allocate a new one.
1901                                  */
1902                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1903                                 if (val < 0)
1904                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1905                                 mono_regstate_free_int (rs, val);
1906                                 dest_sregs [0] = val;
1907
1908                                 /* Fall through to the dest_sreg1 != -1 case */
1909                         }
1910                         else
1911                                 sreg_masks [0] &= sreg_fixed_masks [0];
1912                 }
1913
1914                 if (dest_sregs [0] != -1) {
1915                         sreg_masks [0] = regmask (dest_sregs [0]);
1916
1917                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1918                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1919                         }
1920                         if (is_global_ireg (sregs [0])) {
1921                                 /* The argument is already in a hard reg, need to copy */
1922                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1923                                 insert_before_ins (bb, ins, copy);
1924                                 sregs [0] = dest_sregs [0];
1925                         }
1926                 }
1927
1928                 if (is_soft_reg (sregs [0], bank)) {
1929                         val = rs->vassign [sregs [0]];
1930                         prev_sregs [0] = sregs [0];
1931                         if (val < 0) {
1932                                 int spill = 0;
1933                                 if (val < -1) {
1934                                         /* the register gets spilled after this inst */
1935                                         spill = -val -1;
1936                                 }
1937
1938                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1939                                         /*
1940                                          * Allocate the same hreg to sreg1 as well so the
1941                                          * peephole can get rid of the move.
1942                                          */
1943                                         sreg_masks [0] = regmask (ins->dreg);
1944                                 }
1945
1946                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1947                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1948                                         sreg_masks [0] = regmask (ins->dreg);
1949
1950                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1951                                 assign_reg (cfg, rs, sregs [0], val, bank);
1952                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1953
1954                                 if (spill) {
1955                                         /*
1956                                          * Need to insert before the instruction since it can
1957                                          * overwrite sreg1.
1958                                          */
1959                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1960                                 }
1961                         }
1962                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1963                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1964                                 insert_before_ins (bb, ins, copy);
1965                                 for (j = 1; j < num_sregs; ++j)
1966                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1967                                 val = dest_sregs [0];
1968                         }
1969
1970                         sregs [0] = val;
1971                 }
1972                 else {
1973                         prev_sregs [0] = -1;
1974                 }
1975                 mono_inst_set_src_registers (ins, sregs);
1976
1977                 for (j = 1; j < num_sregs; ++j)
1978                         sreg_masks [j] &= ~(regmask (sregs [0]));
1979
1980                 /* Handle the case when sreg1 is a regpair but dreg is not */
1981                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1982                         int reg2 = prev_sregs [0] + 1;
1983
1984                         g_assert (!bank);
1985                         g_assert (prev_sregs [0] > -1);
1986                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1987                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1988                         val = rs->vassign [reg2];
1989                         if (val < 0) {
1990                                 int spill = 0;
1991                                 if (val < -1) {
1992                                         /* the register gets spilled after this inst */
1993                                         spill = -val -1;
1994                                 }
1995                                 val = mono_regstate_alloc_int (rs, mask);
1996                                 if (val < 0)
1997                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1998                                 if (spill)
1999                                         g_assert_not_reached ();
2000                         }
2001                         else {
2002                                 if (! (mask & (regmask (val)))) {
2003                                         /* The vreg is already allocated to a wrong hreg */
2004                                         /* FIXME: */
2005                                         g_assert_not_reached ();
2006 #if 0
2007                                         val = mono_regstate_alloc_int (rs, mask);
2008                                         if (val < 0)
2009                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2010
2011                                         /* Reallocate hreg to the correct register */
2012                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2013
2014                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
2015 #endif
2016                                 }
2017                         }
2018
2019                         sreg1_high = val;
2020                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2021                         assign_reg (cfg, rs, reg2, val, bank);
2022                 }
2023
2024                 /* Handle dreg==sreg1 */
2025                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2026                         MonoInst *sreg2_copy = NULL;
2027                         MonoInst *copy;
2028                         int bank = reg_bank (spec_src1);
2029
2030                         if (ins->dreg == sregs [1]) {
2031                                 /*
2032                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2033                                  * register for it.
2034                                  */
2035                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2036
2037                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2038                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2039                                 prev_sregs [1] = sregs [1] = reg2;
2040
2041                                 if (G_UNLIKELY (bank))
2042                                         mono_regstate_free_general (rs, reg2, bank);
2043                                 else
2044                                         mono_regstate_free_int (rs, reg2);
2045                         }
2046
2047                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2048                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2049                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2050                                         /* FIXME: */
2051                                         g_assert_not_reached ();
2052
2053                                 /*
2054                                  * sreg1 and dest are already allocated to the same regpair by the
2055                                  * SREG1 allocation code.
2056                                  */
2057                                 g_assert (sregs [0] == ins->dreg);
2058                                 g_assert (dreg_high == sreg1_high);
2059                         }
2060
2061                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2062                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2063                         insert_before_ins (bb, ins, copy);
2064
2065                         if (sreg2_copy)
2066                                 insert_before_ins (bb, copy, sreg2_copy);
2067
2068                         /*
2069                          * Need to prevent sreg2 to be allocated to sreg1, since that
2070                          * would screw up the previous copy.
2071                          */
2072                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2073                         /* we set sreg1 to dest as well */
2074                         prev_sregs [0] = sregs [0] = ins->dreg;
2075                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2076                 }
2077                 mono_inst_set_src_registers (ins, sregs);
2078
2079                 /*
2080                  * TRACK SREG2, 3, ...
2081                  */
2082                 for (j = 1; j < num_sregs; ++j) {
2083                         int k;
2084
2085                         bank = sreg_bank (j, spec);
2086                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2087                                 g_assert_not_reached ();
2088
2089                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2090                                 /*
2091                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2092                                  * allocating it to the fixed reg.
2093                                  */
2094                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2095                                 insert_before_ins (bb, ins, copy);
2096                                 sregs [j] = dest_sregs [j];
2097                         } else if (is_soft_reg (sregs [j], bank)) {
2098                                 val = rs->vassign [sregs [j]];
2099
2100                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2101                                         /*
2102                                          * The sreg is already allocated to a hreg, but not to the fixed
2103                                          * reg required by the instruction. Spill the sreg, so it can be
2104                                          * allocated to the fixed reg by the code below.
2105                                          */
2106                                         /* Currently, this code should only be hit for CAS */
2107                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2108                                         val = rs->vassign [sregs [j]];
2109                                 }
2110
2111                                 if (val < 0) {
2112                                         int spill = 0;
2113                                         if (val < -1) {
2114                                                 /* the register gets spilled after this inst */
2115                                                 spill = -val -1;
2116                                         }
2117                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2118                                         assign_reg (cfg, rs, sregs [j], val, bank);
2119                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2120                                         if (spill) {
2121                                                 /*
2122                                                  * Need to insert before the instruction since it can
2123                                                  * overwrite sreg2.
2124                                                  */
2125                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2126                                         }
2127                                 }
2128                                 sregs [j] = val;
2129                                 for (k = j + 1; k < num_sregs; ++k)
2130                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2131                         }
2132                         else {
2133                                 prev_sregs [j] = -1;
2134                         }
2135                 }
2136                 mono_inst_set_src_registers (ins, sregs);
2137
2138                 /* Sanity check */
2139                 /* Do this only for CAS for now */
2140                 for (j = 1; j < num_sregs; ++j) {
2141                         int sreg = sregs [j];
2142                         int dest_sreg = dest_sregs [j];
2143
2144                         if (j == 2 && dest_sreg != -1) {
2145                                 int k;
2146
2147                                 g_assert (sreg == dest_sreg);
2148
2149                                 for (k = 0; k < num_sregs; ++k) {
2150                                         if (k != j)
2151                                                 g_assert (sregs [k] != dest_sreg);
2152                                 }
2153                         }
2154                 }
2155
2156                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2157                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2158                         mono_regstate_free_int (rs, ins->sreg1);
2159                 }
2160                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2161                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2162                         mono_regstate_free_int (rs, ins->sreg2);
2163                 }*/
2164
2165                 DEBUG (mono_print_ins_index (i, ins));
2166         }
2167
2168         // FIXME: Set MAX_FREGS to 8
2169         // FIXME: Optimize generated code
2170 #if MONO_ARCH_USE_FPSTACK
2171         /*
2172          * Make a forward pass over the code, simulating the fp stack, making sure the
2173          * arguments required by the fp opcodes are at the top of the stack.
2174          */
2175         if (has_fp) {
2176                 MonoInst *prev = NULL;
2177                 MonoInst *fxch;
2178                 int tmp;
2179
2180                 g_assert (num_sregs <= 2);
2181
2182                 for (ins = bb->code; ins; ins = ins->next) {
2183                         spec = ins_get_spec (ins->opcode);
2184
2185                         DEBUG (printf ("processing:"));
2186                         DEBUG (mono_print_ins_index (0, ins));
2187
2188                         if (ins->opcode == OP_FMOVE) {
2189                                 /* Do it by renaming the source to the destination on the stack */
2190                                 // FIXME: Is this correct ?
2191                                 for (i = 0; i < sp; ++i)
2192                                         if (fpstack [i] == ins->sreg1)
2193                                                 fpstack [i] = ins->dreg;
2194                                 prev = ins;
2195                                 continue;
2196                         }
2197
2198                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2199                                 /* Arg1 must be in %st(1) */
2200                                 g_assert (prev);
2201
2202                                 i = 0;
2203                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2204                                         i ++;
2205                                 g_assert (i < sp);
2206
2207                                 if (sp - 1 - i > 0) {
2208                                         /* First move it to %st(0) */
2209                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2210
2211                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2212                                         fxch->inst_imm = sp - 1 - i;
2213
2214                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2215                                         prev = fxch;
2216
2217                                         tmp = fpstack [sp - 1];
2218                                         fpstack [sp - 1] = fpstack [i];
2219                                         fpstack [i] = tmp;
2220                                 }
2221
2222                                 /* Then move it to %st(1) */
2223                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2224
2225                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2226                                 fxch->inst_imm = 1;
2227
2228                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2229                                 prev = fxch;
2230
2231                                 tmp = fpstack [sp - 1];
2232                                 fpstack [sp - 1] = fpstack [sp - 2];
2233                                 fpstack [sp - 2] = tmp;
2234                         }
2235
2236                         if (sreg2_is_fp (spec)) {
2237                                 g_assert (sp > 0);
2238
2239                                 if (fpstack [sp - 1] != ins->sreg2) {
2240                                         g_assert (prev);
2241
2242                                         i = 0;
2243                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2244                                                 i ++;
2245                                         g_assert (i < sp);
2246
2247                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2248
2249                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2250                                         fxch->inst_imm = sp - 1 - i;
2251
2252                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2253                                         prev = fxch;
2254
2255                                         tmp = fpstack [sp - 1];
2256                                         fpstack [sp - 1] = fpstack [i];
2257                                         fpstack [i] = tmp;
2258                                 }
2259
2260                                 sp --;
2261                         }
2262
2263                         if (sreg1_is_fp (spec)) {
2264                                 g_assert (sp > 0);
2265
2266                                 if (fpstack [sp - 1] != ins->sreg1) {
2267                                         g_assert (prev);
2268
2269                                         i = 0;
2270                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2271                                                 i ++;
2272                                         g_assert (i < sp);
2273
2274                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2275
2276                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2277                                         fxch->inst_imm = sp - 1 - i;
2278
2279                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2280                                         prev = fxch;
2281
2282                                         tmp = fpstack [sp - 1];
2283                                         fpstack [sp - 1] = fpstack [i];
2284                                         fpstack [i] = tmp;
2285                                 }
2286
2287                                 sp --;
2288                         }
2289
2290                         if (dreg_is_fp (spec)) {
2291                                 g_assert (sp < 8);
2292                                 fpstack [sp ++] = ins->dreg;
2293                         }
2294
2295                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2296                                 printf ("\t[");
2297                                 for (i = 0; i < sp; ++i)
2298                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2299                                 printf ("]\n");
2300                         }
2301
2302                         prev = ins;
2303                 }
2304
2305                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2306                         /* Remove remaining items from the fp stack */
2307                         /*
2308                          * These can remain for example as a result of a dead fmove like in
2309                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2310                          */
2311                         while (sp) {
2312                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2313                                 mono_add_ins_to_end (bb, ins);
2314                                 sp --;
2315                         }
2316                 }
2317         }
2318 #endif
2319 }
2320
2321 CompRelation
2322 mono_opcode_to_cond (int opcode)
2323 {
2324         switch (opcode) {
2325         case OP_CEQ:
2326         case OP_IBEQ:
2327         case OP_ICEQ:
2328         case OP_LBEQ:
2329         case OP_LCEQ:
2330         case OP_FBEQ:
2331         case OP_FCEQ:
2332         case OP_RBEQ:
2333         case OP_RCEQ:
2334         case OP_COND_EXC_EQ:
2335         case OP_COND_EXC_IEQ:
2336         case OP_CMOV_IEQ:
2337         case OP_CMOV_LEQ:
2338                 return CMP_EQ;
2339         case OP_FCNEQ:
2340         case OP_ICNEQ:
2341         case OP_IBNE_UN:
2342         case OP_LBNE_UN:
2343         case OP_FBNE_UN:
2344         case OP_COND_EXC_NE_UN:
2345         case OP_COND_EXC_INE_UN:
2346         case OP_CMOV_INE_UN:
2347         case OP_CMOV_LNE_UN:
2348                 return CMP_NE;
2349         case OP_FCLE:
2350         case OP_ICLE:
2351         case OP_IBLE:
2352         case OP_LBLE:
2353         case OP_FBLE:
2354         case OP_CMOV_ILE:
2355         case OP_CMOV_LLE:
2356                 return CMP_LE;
2357         case OP_FCGE:
2358         case OP_ICGE:
2359         case OP_IBGE:
2360         case OP_LBGE:
2361         case OP_FBGE:
2362         case OP_CMOV_IGE:
2363         case OP_CMOV_LGE:
2364                 return CMP_GE;
2365         case OP_CLT:
2366         case OP_IBLT:
2367         case OP_ICLT:
2368         case OP_LBLT:
2369         case OP_LCLT:
2370         case OP_FBLT:
2371         case OP_FCLT:
2372         case OP_RBLT:
2373         case OP_RCLT:
2374         case OP_COND_EXC_LT:
2375         case OP_COND_EXC_ILT:
2376         case OP_CMOV_ILT:
2377         case OP_CMOV_LLT:
2378                 return CMP_LT;
2379         case OP_CGT:
2380         case OP_IBGT:
2381         case OP_ICGT:
2382         case OP_LBGT:
2383         case OP_LCGT:
2384         case OP_FBGT:
2385         case OP_FCGT:
2386         case OP_RBGT:
2387         case OP_RCGT:
2388         case OP_COND_EXC_GT:
2389         case OP_COND_EXC_IGT:
2390         case OP_CMOV_IGT:
2391         case OP_CMOV_LGT:
2392                 return CMP_GT;
2393
2394         case OP_ICLE_UN:
2395         case OP_IBLE_UN:
2396         case OP_LBLE_UN:
2397         case OP_FBLE_UN:
2398         case OP_COND_EXC_LE_UN:
2399         case OP_COND_EXC_ILE_UN:
2400         case OP_CMOV_ILE_UN:
2401         case OP_CMOV_LLE_UN:
2402                 return CMP_LE_UN;
2403
2404         case OP_ICGE_UN:
2405         case OP_IBGE_UN:
2406         case OP_LBGE_UN:
2407         case OP_FBGE_UN:
2408         case OP_CMOV_IGE_UN:
2409         case OP_CMOV_LGE_UN:
2410                 return CMP_GE_UN;
2411         case OP_CLT_UN:
2412         case OP_IBLT_UN:
2413         case OP_ICLT_UN:
2414         case OP_LBLT_UN:
2415         case OP_LCLT_UN:
2416         case OP_FBLT_UN:
2417         case OP_FCLT_UN:
2418         case OP_RBLT_UN:
2419         case OP_RCLT_UN:
2420         case OP_COND_EXC_LT_UN:
2421         case OP_COND_EXC_ILT_UN:
2422         case OP_CMOV_ILT_UN:
2423         case OP_CMOV_LLT_UN:
2424                 return CMP_LT_UN;
2425         case OP_CGT_UN:
2426         case OP_IBGT_UN:
2427         case OP_ICGT_UN:
2428         case OP_LBGT_UN:
2429         case OP_LCGT_UN:
2430         case OP_FCGT_UN:
2431         case OP_FBGT_UN:
2432         case OP_RCGT_UN:
2433         case OP_RBGT_UN:
2434         case OP_COND_EXC_GT_UN:
2435         case OP_COND_EXC_IGT_UN:
2436         case OP_CMOV_IGT_UN:
2437         case OP_CMOV_LGT_UN:
2438                 return CMP_GT_UN;
2439         default:
2440                 printf ("%s\n", mono_inst_name (opcode));
2441                 g_assert_not_reached ();
2442                 return (CompRelation)0;
2443         }
2444 }
2445
2446 CompRelation
2447 mono_negate_cond (CompRelation cond)
2448 {
2449         switch (cond) {
2450         case CMP_EQ:
2451                 return CMP_NE;
2452         case CMP_NE:
2453                 return CMP_EQ;
2454         case CMP_LE:
2455                 return CMP_GT;
2456         case CMP_GE:
2457                 return CMP_LT;
2458         case CMP_LT:
2459                 return CMP_GE;
2460         case CMP_GT:
2461                 return CMP_LE;
2462         case CMP_LE_UN:
2463                 return CMP_GT_UN;
2464         case CMP_GE_UN:
2465                 return CMP_LT_UN;
2466         case CMP_LT_UN:
2467                 return CMP_GE_UN;
2468         case CMP_GT_UN:
2469                 return CMP_LE_UN;
2470         default:
2471                 g_assert_not_reached ();
2472         }
2473 }
2474
2475 CompType
2476 mono_opcode_to_type (int opcode, int cmp_opcode)
2477 {
2478         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2479                 return CMP_TYPE_L;
2480         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2481                 return CMP_TYPE_I;
2482         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2483                 return CMP_TYPE_I;
2484         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2485                 return CMP_TYPE_L;
2486         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2487                 return CMP_TYPE_L;
2488         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2489                 return CMP_TYPE_F;
2490         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2491                 return CMP_TYPE_F;
2492         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2493                 return CMP_TYPE_I;
2494         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2495                 switch (cmp_opcode) {
2496                 case OP_ICOMPARE:
2497                 case OP_ICOMPARE_IMM:
2498                         return CMP_TYPE_I;
2499                 default:
2500                         return CMP_TYPE_L;
2501                 }
2502         } else {
2503                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2504                 return (CompType)0;
2505         }
2506 }
2507
2508 /*
2509  * mono_peephole_ins:
2510  *
2511  *   Perform some architecture independent peephole optimizations.
2512  */
2513 void
2514 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2515 {
2516         int filter = FILTER_IL_SEQ_POINT;
2517         MonoInst *last_ins = mono_inst_prev (ins, filter);
2518
2519         switch (ins->opcode) {
2520         case OP_MUL_IMM:
2521                 /* remove unnecessary multiplication with 1 */
2522                 if (ins->inst_imm == 1) {
2523                         if (ins->dreg != ins->sreg1)
2524                                 ins->opcode = OP_MOVE;
2525                         else
2526                                 MONO_DELETE_INS (bb, ins);
2527                 }
2528                 break;
2529         case OP_LOAD_MEMBASE:
2530         case OP_LOADI4_MEMBASE:
2531                 /*
2532                  * Note: if reg1 = reg2 the load op is removed
2533                  *
2534                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2535                  * OP_LOAD_MEMBASE offset(basereg), reg2
2536                  * -->
2537                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2538                  * OP_MOVE reg1, reg2
2539                  */
2540                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2541                         last_ins = mono_inst_prev (ins, filter);
2542                 if (last_ins &&
2543                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2544                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2545                         ins->inst_basereg == last_ins->inst_destbasereg &&
2546                         ins->inst_offset == last_ins->inst_offset) {
2547                         if (ins->dreg == last_ins->sreg1) {
2548                                 MONO_DELETE_INS (bb, ins);
2549                                 break;
2550                         } else {
2551                                 ins->opcode = OP_MOVE;
2552                                 ins->sreg1 = last_ins->sreg1;
2553                         }
2554
2555                         /*
2556                          * Note: reg1 must be different from the basereg in the second load
2557                          * Note: if reg1 = reg2 is equal then second load is removed
2558                          *
2559                          * OP_LOAD_MEMBASE offset(basereg), reg1
2560                          * OP_LOAD_MEMBASE offset(basereg), reg2
2561                          * -->
2562                          * OP_LOAD_MEMBASE offset(basereg), reg1
2563                          * OP_MOVE reg1, reg2
2564                          */
2565                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2566                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2567                           ins->inst_basereg != last_ins->dreg &&
2568                           ins->inst_basereg == last_ins->inst_basereg &&
2569                           ins->inst_offset == last_ins->inst_offset) {
2570
2571                         if (ins->dreg == last_ins->dreg) {
2572                                 MONO_DELETE_INS (bb, ins);
2573                         } else {
2574                                 ins->opcode = OP_MOVE;
2575                                 ins->sreg1 = last_ins->dreg;
2576                         }
2577
2578                         //g_assert_not_reached ();
2579
2580 #if 0
2581                         /*
2582                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2583                          * OP_LOAD_MEMBASE offset(basereg), reg
2584                          * -->
2585                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2586                          * OP_ICONST reg, imm
2587                          */
2588                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2589                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2590                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2591                                    ins->inst_offset == last_ins->inst_offset) {
2592                         ins->opcode = OP_ICONST;
2593                         ins->inst_c0 = last_ins->inst_imm;
2594                         g_assert_not_reached (); // check this rule
2595 #endif
2596                 }
2597                 break;
2598         case OP_LOADI1_MEMBASE:
2599         case OP_LOADU1_MEMBASE:
2600                 /*
2601                  * Note: if reg1 = reg2 the load op is removed
2602                  *
2603                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2604                  * OP_LOAD_MEMBASE offset(basereg), reg2
2605                  * -->
2606                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2607                  * OP_MOVE reg1, reg2
2608                  */
2609                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2610                         ins->inst_basereg == last_ins->inst_destbasereg &&
2611                         ins->inst_offset == last_ins->inst_offset) {
2612                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2613                         ins->sreg1 = last_ins->sreg1;
2614                 }
2615                 break;
2616         case OP_LOADI2_MEMBASE:
2617         case OP_LOADU2_MEMBASE:
2618                 /*
2619                  * Note: if reg1 = reg2 the load op is removed
2620                  *
2621                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2622                  * OP_LOAD_MEMBASE offset(basereg), reg2
2623                  * -->
2624                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2625                  * OP_MOVE reg1, reg2
2626                  */
2627                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2628                         ins->inst_basereg == last_ins->inst_destbasereg &&
2629                         ins->inst_offset == last_ins->inst_offset) {
2630 #if SIZEOF_REGISTER == 8
2631                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2632 #else
2633                         /* The definition of OP_PCONV_TO_U2 is wrong */
2634                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2635 #endif
2636                         ins->sreg1 = last_ins->sreg1;
2637                 }
2638                 break;
2639         case OP_LOADX_MEMBASE:
2640                 if (last_ins && last_ins->opcode == OP_STOREX_MEMBASE &&
2641                         ins->inst_basereg == last_ins->inst_destbasereg &&
2642                         ins->inst_offset == last_ins->inst_offset) {
2643                         if (ins->dreg == last_ins->sreg1) {
2644                                 MONO_DELETE_INS (bb, ins);
2645                                 break;
2646                         } else {
2647                                 ins->opcode = OP_XMOVE;
2648                                 ins->sreg1 = last_ins->sreg1;
2649                         }
2650                 }
2651                 break;
2652         case OP_MOVE:
2653         case OP_FMOVE:
2654                 /*
2655                  * Removes:
2656                  *
2657                  * OP_MOVE reg, reg
2658                  */
2659                 if (ins->dreg == ins->sreg1) {
2660                         MONO_DELETE_INS (bb, ins);
2661                         break;
2662                 }
2663                 /*
2664                  * Removes:
2665                  *
2666                  * OP_MOVE sreg, dreg
2667                  * OP_MOVE dreg, sreg
2668                  */
2669                 if (last_ins && last_ins->opcode == ins->opcode &&
2670                         ins->sreg1 == last_ins->dreg &&
2671                         ins->dreg == last_ins->sreg1) {
2672                         MONO_DELETE_INS (bb, ins);
2673                 }
2674                 break;
2675         case OP_NOP:
2676                 MONO_DELETE_INS (bb, ins);
2677                 break;
2678         }
2679 }
2680
2681 int
2682 mini_exception_id_by_name (const char *name)
2683 {
2684         if (strcmp (name, "IndexOutOfRangeException") == 0)
2685                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2686         if (strcmp (name, "OverflowException") == 0)
2687                 return MONO_EXC_OVERFLOW;
2688         if (strcmp (name, "ArithmeticException") == 0)
2689                 return MONO_EXC_ARITHMETIC;
2690         if (strcmp (name, "DivideByZeroException") == 0)
2691                 return MONO_EXC_DIVIDE_BY_ZERO;
2692         if (strcmp (name, "InvalidCastException") == 0)
2693                 return MONO_EXC_INVALID_CAST;
2694         if (strcmp (name, "NullReferenceException") == 0)
2695                 return MONO_EXC_NULL_REF;
2696         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2697                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2698         if (strcmp (name, "ArgumentException") == 0)
2699                 return MONO_EXC_ARGUMENT;
2700         g_error ("Unknown intrinsic exception %s\n", name);
2701         return -1;
2702 }
2703
2704 gboolean
2705 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2706 {
2707         MonoClass *klass;
2708         gpointer iter;
2709         MonoClassField *field;
2710         MonoType *ftype, *prev_ftype = NULL;
2711         int nfields = 0;
2712
2713         klass = mono_class_from_mono_type (t);
2714         iter = NULL;
2715         while ((field = mono_class_get_fields (klass, &iter))) {
2716                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2717                         continue;
2718                 ftype = mono_field_get_type (field);
2719                 ftype = mini_native_type_replace_type (ftype);
2720
2721                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2722                         int nested_nfields, nested_esize;
2723
2724                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2725                                 return FALSE;
2726                         if (nested_esize == 4)
2727                                 ftype = &mono_defaults.single_class->byval_arg;
2728                         else
2729                                 ftype = &mono_defaults.double_class->byval_arg;
2730                         if (prev_ftype && prev_ftype->type != ftype->type)
2731                                 return FALSE;
2732                         prev_ftype = ftype;
2733                         nfields += nested_nfields;
2734                 } else {
2735                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2736                                 return FALSE;
2737                         if (prev_ftype && prev_ftype->type != ftype->type)
2738                                 return FALSE;
2739                         prev_ftype = ftype;
2740                         nfields ++;
2741                 }
2742         }
2743         if (nfields == 0)
2744                 return FALSE;
2745         *out_nfields = nfields;
2746         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2747         return TRUE;
2748 }
2749
2750 MonoRegState*
2751 mono_regstate_new (void)
2752 {
2753         MonoRegState* rs = g_new0 (MonoRegState, 1);
2754
2755         rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2756 #ifdef MONO_ARCH_NEED_SIMD_BANK
2757         rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2758 #endif
2759
2760         return rs;
2761 }
2762
2763 void
2764 mono_regstate_free (MonoRegState *rs) {
2765         g_free (rs->vassign);
2766         g_free (rs);
2767 }
2768
2769 #endif /* DISABLE_JIT */
2770
2771 gboolean
2772 mono_is_regsize_var (MonoType *t)
2773 {
2774         t = mini_get_underlying_type (t);
2775         switch (t->type) {
2776         case MONO_TYPE_I1:
2777         case MONO_TYPE_U1:
2778         case MONO_TYPE_I2:
2779         case MONO_TYPE_U2:
2780         case MONO_TYPE_I4:
2781         case MONO_TYPE_U4:
2782         case MONO_TYPE_I:
2783         case MONO_TYPE_U:
2784         case MONO_TYPE_PTR:
2785         case MONO_TYPE_FNPTR:
2786 #if SIZEOF_REGISTER == 8
2787         case MONO_TYPE_I8:
2788         case MONO_TYPE_U8:
2789 #endif
2790                 return TRUE;
2791         case MONO_TYPE_OBJECT:
2792         case MONO_TYPE_STRING:
2793         case MONO_TYPE_CLASS:
2794         case MONO_TYPE_SZARRAY:
2795         case MONO_TYPE_ARRAY:
2796                 return TRUE;
2797         case MONO_TYPE_GENERICINST:
2798                 if (!mono_type_generic_inst_is_valuetype (t))
2799                         return TRUE;
2800                 return FALSE;
2801         case MONO_TYPE_VALUETYPE:
2802                 return FALSE;
2803         default:
2804                 return FALSE;
2805         }
2806 }