3 * Arch independent code generation functionality
5 * (C) 2003 Ximian, Inc.
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/debug-helpers.h>
18 #include <mono/metadata/threads.h>
19 #include <mono/metadata/profiler-private.h>
20 #include <mono/metadata/mempool-internals.h>
21 #include <mono/utils/mono-math.h>
25 #include "mini-arch.h"
29 #ifndef MONO_MAX_XREGS
31 #define MONO_MAX_XREGS 0
32 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
33 #define MONO_ARCH_CALLEE_XREGS 0
37 #define MONO_ARCH_BANK_MIRRORED -2
39 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
41 #ifndef MONO_ARCH_NEED_SIMD_BANK
42 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
45 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
47 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
53 #define get_mirrored_bank(bank) (-1)
55 #define is_hreg_mirrored(rs, bank, hreg) (0)
60 /* If the bank is mirrored return the true logical bank that the register in the
61 * physical register bank is allocated to.
63 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
64 return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
68 * Every hardware register belongs to a register type or register bank. bank 0
69 * contains the int registers, bank 1 contains the fp registers.
70 * int registers are used 99% of the time, so they are special cased in a lot of
74 static const int regbank_size [] = {
82 static const int regbank_load_ops [] = {
90 static const int regbank_store_ops [] = {
91 OP_STORER_MEMBASE_REG,
92 OP_STORER8_MEMBASE_REG,
93 OP_STORER_MEMBASE_REG,
94 OP_STORER_MEMBASE_REG,
98 static const int regbank_move_ops [] = {
106 #define regmask(reg) (((regmask_t)1) << (reg))
108 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
109 static const regmask_t regbank_callee_saved_regs [] = {
110 MONO_ARCH_CALLEE_SAVED_REGS,
111 MONO_ARCH_CALLEE_SAVED_FREGS,
112 MONO_ARCH_CALLEE_SAVED_REGS,
113 MONO_ARCH_CALLEE_SAVED_REGS,
114 MONO_ARCH_CALLEE_SAVED_XREGS,
118 static const regmask_t regbank_callee_regs [] = {
119 MONO_ARCH_CALLEE_REGS,
120 MONO_ARCH_CALLEE_FREGS,
121 MONO_ARCH_CALLEE_REGS,
122 MONO_ARCH_CALLEE_REGS,
123 MONO_ARCH_CALLEE_XREGS,
126 static const int regbank_spill_var_size[] = {
131 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
134 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
137 mono_regstate_assign (MonoRegState *rs)
139 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
140 /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
141 * if the values here are not the same.
143 g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
144 g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
145 g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
148 if (rs->next_vreg > rs->vassign_size) {
149 g_free (rs->vassign);
150 rs->vassign_size = MAX (rs->next_vreg, 256);
151 rs->vassign = (gint32 *)g_malloc (rs->vassign_size * sizeof (gint32));
154 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
155 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
157 rs->symbolic [MONO_REG_INT] = rs->isymbolic;
158 rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
160 #ifdef MONO_ARCH_NEED_SIMD_BANK
161 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
162 rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
167 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
169 regmask_t mask = allow & rs->ifree_mask;
171 #if defined(__x86_64__) && defined(__GNUC__)
178 __asm__("bsfq %1,%0\n\t"
179 : "=r" (i) : "rm" (mask));
181 rs->ifree_mask &= ~ ((regmask_t)1 << i);
187 for (i = 0; i < MONO_MAX_IREGS; ++i) {
188 if (mask & ((regmask_t)1 << i)) {
189 rs->ifree_mask &= ~ ((regmask_t)1 << i);
198 mono_regstate_free_int (MonoRegState *rs, int reg)
201 rs->ifree_mask |= (regmask_t)1 << reg;
202 rs->isymbolic [reg] = 0;
207 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
211 regmask_t mask = allow & rs->free_mask [bank];
212 for (i = 0; i < regbank_size [bank]; ++i) {
213 if (mask & ((regmask_t)1 << i)) {
214 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
216 mirrored_bank = get_mirrored_bank (bank);
217 if (mirrored_bank == -1)
220 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
228 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
233 rs->free_mask [bank] |= (regmask_t)1 << reg;
234 rs->symbolic [bank][reg] = 0;
236 mirrored_bank = get_mirrored_bank (bank);
237 if (mirrored_bank == -1)
239 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
240 rs->symbolic [mirrored_bank][reg] = 0;
245 mono_regname_full (int reg, int bank)
247 if (G_UNLIKELY (bank)) {
248 #if MONO_ARCH_NEED_SIMD_BANK
249 if (bank == MONO_REG_SIMD)
250 return mono_arch_xregname (reg);
252 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
253 return mono_arch_regname (reg);
254 g_assert (bank == MONO_REG_DOUBLE);
255 return mono_arch_fregname (reg);
257 return mono_arch_regname (reg);
262 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
266 regpair = (((guint32)hreg) << 24) + vreg;
267 if (G_UNLIKELY (bank)) {
268 g_assert (vreg >= regbank_size [bank]);
269 g_assert (hreg < regbank_size [bank]);
270 call->used_fregs |= 1 << hreg;
271 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
273 g_assert (vreg >= MONO_MAX_IREGS);
274 g_assert (hreg < MONO_MAX_IREGS);
275 call->used_iregs |= 1 << hreg;
276 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
281 * mono_call_inst_add_outarg_vt:
283 * Register OUTARG_VT as belonging to CALL.
286 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
288 call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
292 resize_spill_info (MonoCompile *cfg, int bank)
294 MonoSpillInfo *orig_info = cfg->spill_info [bank];
295 int orig_len = cfg->spill_info_len [bank];
296 int new_len = orig_len ? orig_len * 2 : 16;
297 MonoSpillInfo *new_info;
300 g_assert (bank < MONO_NUM_REGBANKS);
302 new_info = (MonoSpillInfo *)mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
304 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
305 for (i = orig_len; i < new_len; ++i)
306 new_info [i].offset = -1;
308 cfg->spill_info [bank] = new_info;
309 cfg->spill_info_len [bank] = new_len;
313 * returns the offset used by spillvar. It allocates a new
314 * spill variable if necessary.
317 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
322 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
323 while (spillvar >= cfg->spill_info_len [bank])
324 resize_spill_info (cfg, bank);
328 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
330 info = &cfg->spill_info [bank][spillvar];
331 if (info->offset == -1) {
332 cfg->stack_offset += sizeof (mgreg_t) - 1;
333 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
335 g_assert (bank < MONO_NUM_REGBANKS);
336 if (G_UNLIKELY (bank))
337 size = regbank_spill_var_size [bank];
339 size = sizeof (mgreg_t);
341 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
342 cfg->stack_offset += size - 1;
343 cfg->stack_offset &= ~(size - 1);
344 info->offset = cfg->stack_offset;
345 cfg->stack_offset += size;
347 cfg->stack_offset += size - 1;
348 cfg->stack_offset &= ~(size - 1);
349 cfg->stack_offset += size;
350 info->offset = - cfg->stack_offset;
357 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
358 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
359 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
360 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
361 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
362 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
364 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
365 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
366 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
367 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
368 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
370 #ifndef MONO_ARCH_INST_IS_FLOAT
371 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
374 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
375 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
376 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
377 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
378 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
380 #define reg_is_simd(desc) ((desc) == 'x')
382 #ifdef MONO_ARCH_NEED_SIMD_BANK
384 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
388 #define reg_bank(desc) reg_is_fp ((desc))
392 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
393 #define sreg1_bank(spec) sreg_bank (0, (spec))
394 #define sreg2_bank(spec) sreg_bank (1, (spec))
395 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
397 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
398 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
399 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
400 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
402 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
404 #ifdef MONO_ARCH_IS_GLOBAL_IREG
405 #undef is_global_ireg
406 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
415 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
418 #if !defined(DISABLE_LOGGING)
421 mono_print_ins_index (int i, MonoInst *ins)
423 GString *buf = mono_print_ins_index_strbuf (i, ins);
424 printf ("%s\n", buf->str);
425 g_string_free (buf, TRUE);
429 mono_print_ins_index_strbuf (int i, MonoInst *ins)
431 const char *spec = ins_get_spec (ins->opcode);
432 GString *sbuf = g_string_new (NULL);
434 int sregs [MONO_MAX_SRC_REGS];
437 g_string_append_printf (sbuf, "\t%-2d %s", i, mono_inst_name (ins->opcode));
439 g_string_append_printf (sbuf, " %s", mono_inst_name (ins->opcode));
440 if (spec == MONO_ARCH_CPU_SPEC) {
441 gboolean dest_base = FALSE;
442 switch (ins->opcode) {
443 case OP_STOREV_MEMBASE:
450 /* This is a lowered opcode */
451 if (ins->dreg != -1) {
453 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
455 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
457 if (ins->sreg1 != -1)
458 g_string_append_printf (sbuf, " R%d", ins->sreg1);
459 if (ins->sreg2 != -1)
460 g_string_append_printf (sbuf, " R%d", ins->sreg2);
461 if (ins->sreg3 != -1)
462 g_string_append_printf (sbuf, " R%d", ins->sreg3);
464 switch (ins->opcode) {
475 if (!ins->inst_false_bb)
476 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
478 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
485 g_string_append_printf (sbuf, " [%d (", (int)ins->inst_c0);
486 for (i = 0; i < ins->inst_phi_args [0]; i++) {
488 g_string_append_printf (sbuf, ", ");
489 g_string_append_printf (sbuf, "R%d", ins->inst_phi_args [i + 1]);
491 g_string_append_printf (sbuf, ")]");
495 case OP_OUTARG_VTRETADDR:
496 g_string_append_printf (sbuf, " R%d", ((MonoInst*)ins->inst_p0)->dreg);
499 case OP_GSHAREDVT_ARG_REGOFFSET:
500 g_string_append_printf (sbuf, " + 0x%lx", (long)ins->inst_offset);
504 g_string_append_printf (sbuf, " %s", ins->klass->name);
510 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
514 if (spec [MONO_INST_DEST]) {
515 int bank = dreg_bank (spec);
516 if (is_soft_reg (ins->dreg, bank)) {
517 if (spec [MONO_INST_DEST] == 'b') {
518 if (ins->inst_offset == 0)
519 g_string_append_printf (sbuf, " [R%d] <-", ins->dreg);
521 g_string_append_printf (sbuf, " [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
524 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
525 } else if (spec [MONO_INST_DEST] == 'b') {
526 if (ins->inst_offset == 0)
527 g_string_append_printf (sbuf, " [%s] <-", mono_arch_regname (ins->dreg));
529 g_string_append_printf (sbuf, " [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
531 g_string_append_printf (sbuf, " %s <-", mono_regname_full (ins->dreg, bank));
533 if (spec [MONO_INST_SRC1]) {
534 int bank = sreg1_bank (spec);
535 if (is_soft_reg (ins->sreg1, bank)) {
536 if (spec [MONO_INST_SRC1] == 'b')
537 g_string_append_printf (sbuf, " [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
539 g_string_append_printf (sbuf, " R%d", ins->sreg1);
540 } else if (spec [MONO_INST_SRC1] == 'b')
541 g_string_append_printf (sbuf, " [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
543 g_string_append_printf (sbuf, " %s", mono_regname_full (ins->sreg1, bank));
545 num_sregs = mono_inst_get_src_registers (ins, sregs);
546 for (j = 1; j < num_sregs; ++j) {
547 int bank = sreg_bank (j, spec);
548 if (is_soft_reg (sregs [j], bank))
549 g_string_append_printf (sbuf, " R%d", sregs [j]);
551 g_string_append_printf (sbuf, " %s", mono_regname_full (sregs [j], bank));
554 switch (ins->opcode) {
556 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_c0);
558 #if defined(TARGET_X86) || defined(TARGET_AMD64)
559 case OP_X86_PUSH_IMM:
561 case OP_ICOMPARE_IMM:
569 case OP_STORE_MEMBASE_IMM:
570 g_string_append_printf (sbuf, " [%d]", (int)ins->inst_imm);
574 g_string_append_printf (sbuf, " [%d]", (int)(gssize)ins->inst_p1);
577 g_string_append_printf (sbuf, " [%lld]", (long long)ins->inst_l);
580 g_string_append_printf (sbuf, " [%f]", *(double*)ins->inst_p0);
583 g_string_append_printf (sbuf, " [%f]", *(float*)ins->inst_p0);
586 case OP_CALL_MEMBASE:
592 case OP_VCALL_MEMBASE:
595 case OP_VCALL2_MEMBASE:
597 case OP_VOIDCALL_MEMBASE:
599 MonoCallInst *call = (MonoCallInst*)ins;
602 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
604 * These are lowered opcodes, but they are in the .md files since the old
605 * JIT passes them to backends.
608 g_string_append_printf (sbuf, " R%d <-", ins->dreg);
612 char *full_name = mono_method_full_name (call->method, TRUE);
613 g_string_append_printf (sbuf, " [%s]", full_name);
615 } else if (call->fptr_is_patch) {
616 MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
618 g_string_append_printf (sbuf, " ");
620 } else if (call->fptr) {
621 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
623 g_string_append_printf (sbuf, " [%s]", info->name);
626 list = call->out_ireg_args;
631 regpair = (guint32)(gssize)(list->data);
632 hreg = regpair >> 24;
633 reg = regpair & 0xffffff;
635 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_regname (hreg), reg);
637 list = g_slist_next (list);
639 list = call->out_freg_args;
644 regpair = (guint32)(gssize)(list->data);
645 hreg = regpair >> 24;
646 reg = regpair & 0xffffff;
648 g_string_append_printf (sbuf, " [%s <- R%d]", mono_arch_fregname (hreg), reg);
650 list = g_slist_next (list);
655 case OP_CALL_HANDLER:
656 g_string_append_printf (sbuf, " [B%d]", ins->inst_target_bb->block_num);
678 if (!ins->inst_false_bb)
679 g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
681 g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
683 case OP_LIVERANGE_START:
684 case OP_LIVERANGE_END:
685 case OP_GC_LIVENESS_DEF:
686 case OP_GC_LIVENESS_USE:
687 g_string_append_printf (sbuf, " R%d", (int)ins->inst_c1);
689 case OP_IL_SEQ_POINT:
691 g_string_append_printf (sbuf, " il: 0x%x%s", (int)ins->inst_imm, ins->flags & MONO_INST_NONEMPTY_STACK ? ", nonempty-stack" : "");
698 case OP_COND_EXC_NE_UN:
699 case OP_COND_EXC_GE_UN:
700 case OP_COND_EXC_GT_UN:
701 case OP_COND_EXC_LE_UN:
702 case OP_COND_EXC_LT_UN:
707 case OP_COND_EXC_IEQ:
708 case OP_COND_EXC_IGE:
709 case OP_COND_EXC_IGT:
710 case OP_COND_EXC_ILE:
711 case OP_COND_EXC_ILT:
712 case OP_COND_EXC_INE_UN:
713 case OP_COND_EXC_IGE_UN:
714 case OP_COND_EXC_IGT_UN:
715 case OP_COND_EXC_ILE_UN:
716 case OP_COND_EXC_ILT_UN:
717 case OP_COND_EXC_IOV:
718 case OP_COND_EXC_INO:
720 case OP_COND_EXC_INC:
721 g_string_append_printf (sbuf, " %s", ins->inst_p1);
727 if (spec [MONO_INST_CLOB])
728 g_string_append_printf (sbuf, " clobbers: %c", spec [MONO_INST_CLOB]);
733 print_regtrack (RegTrack *t, int num)
739 for (i = 0; i < num; ++i) {
742 if (i >= MONO_MAX_IREGS) {
743 g_snprintf (buf, sizeof(buf), "R%d", i);
746 r = mono_arch_regname (i);
747 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
753 mono_print_ins_index (int i, MonoInst *ins)
756 #endif /* !defined(DISABLE_LOGGING) */
759 mono_print_ins (MonoInst *ins)
761 mono_print_ins_index (-1, ins);
765 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
768 * If this function is called multiple times, the new instructions are inserted
769 * in the proper order.
771 mono_bblock_insert_before_ins (bb, ins, to_insert);
775 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
778 * If this function is called multiple times, the new instructions are inserted in
781 mono_bblock_insert_after_ins (bb, *last, to_insert);
787 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
789 if (vreg_is_ref (cfg, reg))
790 return MONO_REG_INT_REF;
791 else if (vreg_is_mp (cfg, reg))
792 return MONO_REG_INT_MP;
798 * Force the spilling of the variable in the symbolic register 'reg', and free
799 * the hreg it was assigned to.
802 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
806 MonoRegState *rs = cfg->rs;
808 sel = rs->vassign [reg];
810 /* the vreg we need to spill lives in another logical reg bank */
811 bank = translate_bank (cfg->rs, bank, sel);
813 /*i = rs->isymbolic [sel];
814 g_assert (i == reg);*/
816 spill = ++cfg->spill_count;
817 rs->vassign [i] = -spill - 1;
818 if (G_UNLIKELY (bank))
819 mono_regstate_free_general (rs, sel, bank);
821 mono_regstate_free_int (rs, sel);
822 /* we need to create a spill var and insert a load to sel after the current instruction */
823 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
825 load->inst_basereg = cfg->frame_reg;
826 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
827 insert_after_ins (bb, ins, last, load);
828 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
829 if (G_UNLIKELY (bank))
830 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
832 i = mono_regstate_alloc_int (rs, regmask (sel));
835 if (G_UNLIKELY (bank))
836 mono_regstate_free_general (rs, sel, bank);
838 mono_regstate_free_int (rs, sel);
842 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
845 int i, sel, spill, num_sregs;
846 int sregs [MONO_MAX_SRC_REGS];
847 MonoRegState *rs = cfg->rs;
849 g_assert (bank < MONO_NUM_REGBANKS);
851 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
852 /* exclude the registers in the current instruction */
853 num_sregs = mono_inst_get_src_registers (ins, sregs);
854 for (i = 0; i < num_sregs; ++i) {
855 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
856 if (is_soft_reg (sregs [i], bank))
857 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
859 regmask &= ~ (regmask (sregs [i]));
860 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
863 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
864 regmask &= ~ (regmask (ins->dreg));
865 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
868 DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
869 g_assert (regmask); /* need at least a register we can free */
871 /* we should track prev_use and spill the register that's farther */
872 if (G_UNLIKELY (bank)) {
873 for (i = 0; i < regbank_size [bank]; ++i) {
874 if (regmask & (regmask (i))) {
877 /* the vreg we need to load lives in another logical bank */
878 bank = translate_bank (cfg->rs, bank, sel);
880 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
885 i = rs->symbolic [bank] [sel];
886 spill = ++cfg->spill_count;
887 rs->vassign [i] = -spill - 1;
888 mono_regstate_free_general (rs, sel, bank);
891 for (i = 0; i < MONO_MAX_IREGS; ++i) {
892 if (regmask & (regmask (i))) {
894 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
899 i = rs->isymbolic [sel];
900 spill = ++cfg->spill_count;
901 rs->vassign [i] = -spill - 1;
902 mono_regstate_free_int (rs, sel);
905 /* we need to create a spill var and insert a load to sel after the current instruction */
906 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
908 load->inst_basereg = cfg->frame_reg;
909 load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
910 insert_after_ins (bb, ins, last, load);
911 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
912 if (G_UNLIKELY (bank))
913 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
915 i = mono_regstate_alloc_int (rs, regmask (sel));
924 * Free up the hreg HREG by spilling the vreg allocated to it.
927 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
929 if (G_UNLIKELY (bank)) {
930 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
931 bank = translate_bank (cfg->rs, bank, hreg);
932 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
933 spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
937 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
938 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
939 spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
945 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
949 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
955 mono_bblock_insert_after_ins (bb, ins, copy);
958 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
962 static inline const char*
963 regbank_to_string (int bank)
965 if (bank == MONO_REG_INT_REF)
967 else if (bank == MONO_REG_INT_MP)
974 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
976 MonoInst *store, *def;
978 bank = get_vreg_bank (cfg, prev_reg, bank);
980 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
982 store->inst_destbasereg = cfg->frame_reg;
983 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
985 mono_bblock_insert_after_ins (bb, ins, store);
987 } else if (insert_before) {
988 insert_before_ins (bb, insert_before, store);
990 g_assert_not_reached ();
992 DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
994 if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
995 g_assert (prev_reg != -1);
996 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
997 def->inst_c0 = spill;
999 mono_bblock_insert_after_ins (bb, store, def);
1003 /* flags used in reginfo->flags */
1005 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
1006 MONO_FP_NEEDS_SPILL = regmask (1),
1007 MONO_FP_NEEDS_LOAD = regmask (2)
1011 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
1015 if (info && info->preferred_mask) {
1016 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
1018 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1023 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1025 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1031 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1035 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1038 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1044 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1046 if (G_UNLIKELY (bank))
1047 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1049 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1053 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1055 if (G_UNLIKELY (bank)) {
1058 g_assert (reg >= regbank_size [bank]);
1059 g_assert (hreg < regbank_size [bank]);
1060 g_assert (! is_global_freg (hreg));
1062 rs->vassign [reg] = hreg;
1063 rs->symbolic [bank] [hreg] = reg;
1064 rs->free_mask [bank] &= ~ (regmask (hreg));
1066 mirrored_bank = get_mirrored_bank (bank);
1067 if (mirrored_bank == -1)
1070 /* Make sure the other logical reg bank that this bank shares
1071 * a single hard reg bank knows that this hard reg is not free.
1073 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1075 /* Mark the other logical bank that the this bank shares
1076 * a single hard reg bank with as mirrored.
1078 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1082 g_assert (reg >= MONO_MAX_IREGS);
1083 g_assert (hreg < MONO_MAX_IREGS);
1084 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1085 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1086 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1087 g_assert (! is_global_ireg (hreg));
1090 rs->vassign [reg] = hreg;
1091 rs->isymbolic [hreg] = reg;
1092 rs->ifree_mask &= ~ (regmask (hreg));
1096 static inline regmask_t
1097 get_callee_mask (const char spec)
1099 if (G_UNLIKELY (reg_bank (spec)))
1100 return regbank_callee_regs [reg_bank (spec)];
1101 return MONO_ARCH_CALLEE_REGS;
1104 static gint8 desc_to_fixed_reg [256];
1105 static gboolean desc_to_fixed_reg_inited = FALSE;
1108 * Local register allocation.
1109 * We first scan the list of instructions and we save the liveness info of
1110 * each register (when the register is first used, when it's value is set etc.).
1111 * We also reverse the list of instructions because assigning registers backwards allows
1112 * for more tricks to be used.
1115 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1117 MonoInst *ins, *prev, *last;
1119 MonoRegState *rs = cfg->rs;
1123 unsigned char spec_src1, spec_dest;
1125 #if MONO_ARCH_USE_FPSTACK
1126 gboolean has_fp = FALSE;
1131 int sregs [MONO_MAX_SRC_REGS];
1136 if (!desc_to_fixed_reg_inited) {
1137 for (i = 0; i < 256; ++i)
1138 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1139 desc_to_fixed_reg_inited = TRUE;
1141 /* Validate the cpu description against the info in mini-ops.h */
1142 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1143 for (i = OP_LOAD; i < OP_LAST; ++i) {
1146 spec = ins_get_spec (i);
1147 ispec = INS_INFO (i);
1149 if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1150 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1151 if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1152 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1153 if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1154 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1159 rs->next_vreg = bb->max_vreg;
1160 mono_regstate_assign (rs);
1162 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1163 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1164 rs->free_mask [i] = regbank_callee_regs [i];
1166 max = rs->next_vreg;
1168 if (cfg->reginfo && cfg->reginfo_len < max)
1169 cfg->reginfo = NULL;
1171 reginfo = (RegTrack *)cfg->reginfo;
1173 cfg->reginfo_len = MAX (1024, max * 2);
1174 reginfo = (RegTrack *)mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1175 cfg->reginfo = reginfo;
1178 g_assert (cfg->reginfo_len >= rs->next_vreg);
1180 if (cfg->verbose_level > 1) {
1181 /* print_regtrack reads the info of all variables */
1182 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1186 * For large methods, next_vreg can be very large, so g_malloc0 time can
1187 * be prohibitive. So we manually init the reginfo entries used by the
1190 for (ins = bb->code; ins; ins = ins->next) {
1191 gboolean modify = FALSE;
1193 spec = ins_get_spec (ins->opcode);
1195 if ((ins->dreg != -1) && (ins->dreg < max)) {
1196 memset (®info [ins->dreg], 0, sizeof (RegTrack));
1197 #if SIZEOF_REGISTER == 4
1198 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1200 * In the new IR, the two vregs of the regpair do not alias the
1201 * original long vreg. shift the vreg here so the rest of the
1202 * allocator doesn't have to care about it.
1205 memset (®info [ins->dreg + 1], 0, sizeof (RegTrack));
1210 num_sregs = mono_inst_get_src_registers (ins, sregs);
1211 for (j = 0; j < num_sregs; ++j) {
1212 g_assert (sregs [j] != -1);
1213 if (sregs [j] < max) {
1214 memset (®info [sregs [j]], 0, sizeof (RegTrack));
1215 #if SIZEOF_REGISTER == 4
1216 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1219 memset (®info [sregs [j] + 1], 0, sizeof (RegTrack));
1225 mono_inst_set_src_registers (ins, sregs);
1228 /*if (cfg->opt & MONO_OPT_COPYPROP)
1229 local_copy_prop (cfg, ins);*/
1232 DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1233 /* forward pass on the instructions to collect register liveness info */
1234 MONO_BB_FOR_EACH_INS (bb, ins) {
1235 spec = ins_get_spec (ins->opcode);
1236 spec_dest = spec [MONO_INST_DEST];
1238 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1239 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1242 DEBUG (mono_print_ins_index (i, ins));
1244 num_sregs = mono_inst_get_src_registers (ins, sregs);
1246 #if MONO_ARCH_USE_FPSTACK
1247 if (dreg_is_fp (spec)) {
1250 for (j = 0; j < num_sregs; ++j) {
1251 if (sreg_is_fp (j, spec))
1257 for (j = 0; j < num_sregs; ++j) {
1258 int sreg = sregs [j];
1259 int sreg_spec = spec [MONO_INST_SRC1 + j];
1261 bank = sreg_bank (j, spec);
1262 g_assert (sreg != -1);
1263 if (is_soft_reg (sreg, bank))
1264 /* This means the vreg is not local to this bb */
1265 g_assert (reginfo [sreg].born_in > 0);
1266 rs->vassign [sreg] = -1;
1267 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1268 //reginfo [ins->sreg2].last_use = i;
1269 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1270 /* The virtual register is allocated sequentially */
1271 rs->vassign [sreg + 1] = -1;
1272 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1273 //reginfo [ins->sreg2 + 1].last_use = i;
1274 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1275 reginfo [sreg + 1].born_in = i;
1281 mono_inst_set_src_registers (ins, sregs);
1286 bank = dreg_bank (spec);
1287 if (spec_dest != 'b') /* it's not just a base register */
1288 reginfo [ins->dreg].killed_in = i;
1289 g_assert (ins->dreg != -1);
1290 rs->vassign [ins->dreg] = -1;
1291 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1292 //reginfo [ins->dreg].last_use = i;
1293 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1294 reginfo [ins->dreg].born_in = i;
1296 dest_dreg = desc_to_fixed_reg [spec_dest];
1297 if (dest_dreg != -1)
1298 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1300 #ifdef MONO_ARCH_INST_FIXED_MASK
1301 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1304 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1305 /* The virtual register is allocated sequentially */
1306 rs->vassign [ins->dreg + 1] = -1;
1307 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1308 //reginfo [ins->dreg + 1].last_use = i;
1309 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1310 reginfo [ins->dreg + 1].born_in = i;
1311 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1312 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1323 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1324 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1326 int dest_dreg, clob_reg;
1327 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1328 int dreg_high, sreg1_high;
1329 regmask_t dreg_mask, mask;
1330 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1331 regmask_t dreg_fixed_mask;
1332 const unsigned char *ip;
1334 spec = ins_get_spec (ins->opcode);
1335 spec_src1 = spec [MONO_INST_SRC1];
1336 spec_dest = spec [MONO_INST_DEST];
1342 dreg_mask = get_callee_mask (spec_dest);
1343 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1344 prev_sregs [j] = -1;
1345 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1346 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1347 #ifdef MONO_ARCH_INST_FIXED_MASK
1348 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1350 sreg_fixed_masks [j] = 0;
1354 DEBUG (printf ("processing:"));
1355 DEBUG (mono_print_ins_index (i, ins));
1364 dest_dreg = desc_to_fixed_reg [spec_dest];
1365 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1366 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1368 #ifdef MONO_ARCH_INST_FIXED_MASK
1369 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1371 dreg_fixed_mask = 0;
1374 num_sregs = mono_inst_get_src_registers (ins, sregs);
1377 * TRACK FIXED SREG2, 3, ...
1379 for (j = 1; j < num_sregs; ++j) {
1380 int sreg = sregs [j];
1381 int dest_sreg = dest_sregs [j];
1383 if (dest_sreg == -1)
1391 * We need to special case this, since on x86, there are only 3
1392 * free registers, and the code below assigns one of them to
1393 * sreg, so we can run out of registers when trying to assign
1394 * dreg. Instead, we just set up the register masks, and let the
1395 * normal sreg2 assignment code handle this. It would be nice to
1396 * do this for all the fixed reg cases too, but there is too much
1400 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1401 sreg_masks [j] = regmask (dest_sreg);
1402 for (k = 0; k < num_sregs; ++k) {
1404 sreg_masks [k] &= ~ (regmask (dest_sreg));
1408 * Spill sreg1/2 if they are assigned to dest_sreg.
1410 for (k = 0; k < num_sregs; ++k) {
1411 if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1412 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1416 * We can also run out of registers while processing sreg2 if sreg3 is
1417 * assigned to another hreg, so spill sreg3 now.
1419 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1420 spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1425 if (rs->ifree_mask & (regmask (dest_sreg))) {
1426 if (is_global_ireg (sreg)) {
1428 /* Argument already in hard reg, need to copy */
1429 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1430 insert_before_ins (bb, ins, copy);
1431 for (k = 0; k < num_sregs; ++k) {
1433 sreg_masks [k] &= ~ (regmask (dest_sreg));
1436 dreg_mask &= ~ (regmask (dest_sreg));
1438 val = rs->vassign [sreg];
1440 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1441 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1442 } else if (val < -1) {
1444 g_assert_not_reached ();
1446 /* Argument already in hard reg, need to copy */
1447 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1450 insert_before_ins (bb, ins, copy);
1451 for (k = 0; k < num_sregs; ++k) {
1453 sreg_masks [k] &= ~ (regmask (dest_sreg));
1456 * Prevent the dreg from being allocated to dest_sreg
1457 * too, since it could force sreg1 to be allocated to
1458 * the same reg on x86.
1460 dreg_mask &= ~ (regmask (dest_sreg));
1464 gboolean need_spill = TRUE;
1465 gboolean need_assign = TRUE;
1468 dreg_mask &= ~ (regmask (dest_sreg));
1469 for (k = 0; k < num_sregs; ++k) {
1471 sreg_masks [k] &= ~ (regmask (dest_sreg));
1475 * First check if dreg is assigned to dest_sreg2, since we
1476 * can't spill a dreg.
1478 if (spec [MONO_INST_DEST])
1479 val = rs->vassign [ins->dreg];
1482 if (val == dest_sreg && ins->dreg != sreg) {
1484 * the destination register is already assigned to
1485 * dest_sreg2: we need to allocate another register for it
1486 * and then copy from this to dest_sreg2.
1489 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
1490 g_assert (new_dest >= 0);
1491 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1493 prev_dreg = ins->dreg;
1494 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1495 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1496 mono_regstate_free_int (rs, dest_sreg);
1500 if (is_global_ireg (sreg)) {
1501 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1502 insert_before_ins (bb, ins, copy);
1503 need_assign = FALSE;
1506 val = rs->vassign [sreg];
1507 if (val == dest_sreg) {
1508 /* sreg2 is already assigned to the correct register */
1510 } else if (val < -1) {
1511 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1512 } else if (val >= 0) {
1513 /* sreg2 already assigned to another register */
1515 * We couldn't emit a copy from val to dest_sreg2, because
1516 * val might be spilled later while processing this
1517 * instruction. So we spill sreg2 so it can be allocated to
1520 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1525 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1529 if (rs->vassign [sreg] < -1) {
1532 /* Need to emit a spill store */
1533 spill = - rs->vassign [sreg] - 1;
1534 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1536 /* force-set sreg2 */
1537 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1540 sregs [j] = dest_sreg;
1542 mono_inst_set_src_registers (ins, sregs);
1547 bank = dreg_bank (spec);
1548 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1549 prev_dreg = ins->dreg;
1552 if (spec_dest == 'b') {
1554 * The dest reg is read by the instruction, not written, so
1555 * avoid allocating sreg1/sreg2 to the same reg.
1557 if (dest_sregs [0] != -1)
1558 dreg_mask &= ~ (regmask (dest_sregs [0]));
1559 for (j = 1; j < num_sregs; ++j) {
1560 if (dest_sregs [j] != -1)
1561 dreg_mask &= ~ (regmask (dest_sregs [j]));
1564 val = rs->vassign [ins->dreg];
1565 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1566 /* DREG is already allocated to a register needed for sreg1 */
1567 spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1572 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1573 * various complex situations.
1575 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1576 guint32 dreg2, dest_dreg2;
1578 g_assert (is_soft_reg (ins->dreg, bank));
1580 if (dest_dreg != -1) {
1581 if (rs->vassign [ins->dreg] != dest_dreg)
1582 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1584 dreg2 = ins->dreg + 1;
1585 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1586 if (dest_dreg2 != -1) {
1587 if (rs->vassign [dreg2] != dest_dreg2)
1588 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1593 if (dreg_fixed_mask) {
1595 if (is_global_ireg (ins->dreg)) {
1597 * The argument is already in a hard reg, but that reg is
1598 * not usable by this instruction, so allocate a new one.
1600 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1602 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1603 mono_regstate_free_int (rs, val);
1609 dreg_mask &= dreg_fixed_mask;
1612 if (is_soft_reg (ins->dreg, bank)) {
1613 val = rs->vassign [ins->dreg];
1618 /* the register gets spilled after this inst */
1621 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
1622 assign_reg (cfg, rs, ins->dreg, val, bank);
1624 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1627 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1631 /* Handle regpairs */
1632 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1633 int reg2 = prev_dreg + 1;
1636 g_assert (prev_dreg > -1);
1637 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1638 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1641 mask &= ~regmask (X86_ECX);
1643 val = rs->vassign [reg2];
1647 /* the register gets spilled after this inst */
1650 val = mono_regstate_alloc_int (rs, mask);
1652 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1654 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1657 if (! (mask & (regmask (val)))) {
1658 val = mono_regstate_alloc_int (rs, mask);
1660 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1662 /* Reallocate hreg to the correct register */
1663 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1665 mono_regstate_free_int (rs, rs->vassign [reg2]);
1669 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1670 assign_reg (cfg, rs, reg2, val, bank);
1673 ins->backend.reg3 = val;
1675 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1676 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1677 mono_regstate_free_int (rs, val);
1681 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1683 * In theory, we could free up the hreg even if the vreg is alive,
1684 * but branches inside bblocks force us to assign the same hreg
1685 * to a vreg every time it is encountered.
1687 int dreg = rs->vassign [prev_dreg];
1688 g_assert (dreg >= 0);
1689 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1690 if (G_UNLIKELY (bank))
1691 mono_regstate_free_general (rs, dreg, bank);
1693 mono_regstate_free_int (rs, dreg);
1694 rs->vassign [prev_dreg] = -1;
1697 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1698 /* this instruction only outputs to dest_dreg, need to copy */
1699 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1700 ins->dreg = dest_dreg;
1702 if (G_UNLIKELY (bank)) {
1703 /* the register we need to free up may be used in another logical regbank
1704 * so do a translate just in case.
1706 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1707 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1708 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1711 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1712 free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1716 if (spec_dest == 'b') {
1718 * The dest reg is read by the instruction, not written, so
1719 * avoid allocating sreg1/sreg2 to the same reg.
1721 for (j = 0; j < num_sregs; ++j)
1722 if (!sreg_bank (j, spec))
1723 sreg_masks [j] &= ~ (regmask (ins->dreg));
1729 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1730 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1731 free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1734 if (spec [MONO_INST_CLOB] == 'c') {
1735 int j, s, dreg, dreg2, cur_bank;
1738 clob_mask = MONO_ARCH_CALLEE_REGS;
1740 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1742 * Need to avoid spilling the dreg since the dreg is not really
1743 * clobbered by the call.
1745 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1746 dreg = rs->vassign [prev_dreg];
1750 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1751 dreg2 = rs->vassign [prev_dreg + 1];
1755 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1757 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1758 if ((j != dreg) && (j != dreg2))
1759 free_up_hreg (cfg, bb, tmp, ins, j, 0);
1760 else if (rs->isymbolic [j])
1761 /* The hreg is assigned to the dreg of this instruction */
1762 rs->vassign [rs->isymbolic [j]] = -1;
1763 mono_regstate_free_int (rs, j);
1768 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1769 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1770 clob_mask = regbank_callee_regs [cur_bank];
1771 if ((prev_dreg != -1) && reg_bank (spec_dest))
1772 dreg = rs->vassign [prev_dreg];
1776 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1778 /* we are looping though the banks in the outer loop
1779 * so, we don't need to deal with mirrored hregs
1780 * because we will get them in one of the other bank passes.
1782 if (is_hreg_mirrored (rs, cur_bank, j))
1786 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1788 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1789 else if (rs->symbolic [cur_bank] [j])
1790 /* The hreg is assigned to the dreg of this instruction */
1791 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1792 mono_regstate_free_general (rs, j, cur_bank);
1800 * TRACK ARGUMENT REGS
1802 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1803 MonoCallInst *call = (MonoCallInst*)ins;
1807 * This needs to be done before assigning sreg1, so sreg1 will
1808 * not be assigned one of the argument regs.
1812 * Assign all registers in call->out_reg_args to the proper
1813 * argument registers.
1816 list = call->out_ireg_args;
1822 regpair = (guint32)(gssize)(list->data);
1823 hreg = regpair >> 24;
1824 reg = regpair & 0xffffff;
1826 assign_reg (cfg, rs, reg, hreg, 0);
1828 sreg_masks [0] &= ~(regmask (hreg));
1830 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1832 list = g_slist_next (list);
1836 list = call->out_freg_args;
1842 regpair = (guint32)(gssize)(list->data);
1843 hreg = regpair >> 24;
1844 reg = regpair & 0xffffff;
1846 assign_reg (cfg, rs, reg, hreg, 1);
1848 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1850 list = g_slist_next (list);
1858 bank = sreg1_bank (spec);
1859 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1860 int sreg1 = sregs [0];
1861 int dest_sreg1 = dest_sregs [0];
1863 g_assert (is_soft_reg (sreg1, bank));
1865 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1866 if (dest_sreg1 != -1)
1867 g_assert (dest_sreg1 == ins->dreg);
1868 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1869 g_assert (val >= 0);
1871 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1873 g_assert_not_reached ();
1875 assign_reg (cfg, rs, sreg1, val, bank);
1877 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1879 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1880 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1881 g_assert (val >= 0);
1883 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1885 g_assert_not_reached ();
1887 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1889 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1891 /* Skip rest of this section */
1892 dest_sregs [0] = -1;
1895 if (sreg_fixed_masks [0]) {
1897 if (is_global_ireg (sregs [0])) {
1899 * The argument is already in a hard reg, but that reg is
1900 * not usable by this instruction, so allocate a new one.
1902 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1904 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1905 mono_regstate_free_int (rs, val);
1906 dest_sregs [0] = val;
1908 /* Fall through to the dest_sreg1 != -1 case */
1911 sreg_masks [0] &= sreg_fixed_masks [0];
1914 if (dest_sregs [0] != -1) {
1915 sreg_masks [0] = regmask (dest_sregs [0]);
1917 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1918 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1920 if (is_global_ireg (sregs [0])) {
1921 /* The argument is already in a hard reg, need to copy */
1922 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1923 insert_before_ins (bb, ins, copy);
1924 sregs [0] = dest_sregs [0];
1928 if (is_soft_reg (sregs [0], bank)) {
1929 val = rs->vassign [sregs [0]];
1930 prev_sregs [0] = sregs [0];
1934 /* the register gets spilled after this inst */
1938 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1940 * Allocate the same hreg to sreg1 as well so the
1941 * peephole can get rid of the move.
1943 sreg_masks [0] = regmask (ins->dreg);
1946 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1947 /* Allocate the same reg to sreg1 to avoid a copy later */
1948 sreg_masks [0] = regmask (ins->dreg);
1950 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], ®info [sregs [0]], bank);
1951 assign_reg (cfg, rs, sregs [0], val, bank);
1952 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1956 * Need to insert before the instruction since it can
1959 create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1962 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1963 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1964 insert_before_ins (bb, ins, copy);
1965 for (j = 1; j < num_sregs; ++j)
1966 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1967 val = dest_sregs [0];
1973 prev_sregs [0] = -1;
1975 mono_inst_set_src_registers (ins, sregs);
1977 for (j = 1; j < num_sregs; ++j)
1978 sreg_masks [j] &= ~(regmask (sregs [0]));
1980 /* Handle the case when sreg1 is a regpair but dreg is not */
1981 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1982 int reg2 = prev_sregs [0] + 1;
1985 g_assert (prev_sregs [0] > -1);
1986 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1987 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1988 val = rs->vassign [reg2];
1992 /* the register gets spilled after this inst */
1995 val = mono_regstate_alloc_int (rs, mask);
1997 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1999 g_assert_not_reached ();
2002 if (! (mask & (regmask (val)))) {
2003 /* The vreg is already allocated to a wrong hreg */
2005 g_assert_not_reached ();
2007 val = mono_regstate_alloc_int (rs, mask);
2009 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
2011 /* Reallocate hreg to the correct register */
2012 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
2014 mono_regstate_free_int (rs, rs->vassign [reg2]);
2020 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2021 assign_reg (cfg, rs, reg2, val, bank);
2024 /* Handle dreg==sreg1 */
2025 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2026 MonoInst *sreg2_copy = NULL;
2028 int bank = reg_bank (spec_src1);
2030 if (ins->dreg == sregs [1]) {
2032 * copying sreg1 to dreg could clobber sreg2, so allocate a new
2035 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2037 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2038 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2039 prev_sregs [1] = sregs [1] = reg2;
2041 if (G_UNLIKELY (bank))
2042 mono_regstate_free_general (rs, reg2, bank);
2044 mono_regstate_free_int (rs, reg2);
2047 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2048 /* Copying sreg1_high to dreg could also clobber sreg2 */
2049 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2051 g_assert_not_reached ();
2054 * sreg1 and dest are already allocated to the same regpair by the
2055 * SREG1 allocation code.
2057 g_assert (sregs [0] == ins->dreg);
2058 g_assert (dreg_high == sreg1_high);
2061 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2062 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2063 insert_before_ins (bb, ins, copy);
2066 insert_before_ins (bb, copy, sreg2_copy);
2069 * Need to prevent sreg2 to be allocated to sreg1, since that
2070 * would screw up the previous copy.
2072 sreg_masks [1] &= ~ (regmask (sregs [0]));
2073 /* we set sreg1 to dest as well */
2074 prev_sregs [0] = sregs [0] = ins->dreg;
2075 sreg_masks [1] &= ~ (regmask (ins->dreg));
2077 mono_inst_set_src_registers (ins, sregs);
2080 * TRACK SREG2, 3, ...
2082 for (j = 1; j < num_sregs; ++j) {
2085 bank = sreg_bank (j, spec);
2086 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2087 g_assert_not_reached ();
2089 if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2091 * Argument already in a global hard reg, copy it to the fixed reg, without
2092 * allocating it to the fixed reg.
2094 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2095 insert_before_ins (bb, ins, copy);
2096 sregs [j] = dest_sregs [j];
2097 } else if (is_soft_reg (sregs [j], bank)) {
2098 val = rs->vassign [sregs [j]];
2100 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2102 * The sreg is already allocated to a hreg, but not to the fixed
2103 * reg required by the instruction. Spill the sreg, so it can be
2104 * allocated to the fixed reg by the code below.
2106 /* Currently, this code should only be hit for CAS */
2107 spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2108 val = rs->vassign [sregs [j]];
2114 /* the register gets spilled after this inst */
2117 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], ®info [sregs [j]], bank);
2118 assign_reg (cfg, rs, sregs [j], val, bank);
2119 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2122 * Need to insert before the instruction since it can
2125 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2129 for (k = j + 1; k < num_sregs; ++k)
2130 sreg_masks [k] &= ~ (regmask (sregs [j]));
2133 prev_sregs [j] = -1;
2136 mono_inst_set_src_registers (ins, sregs);
2139 /* Do this only for CAS for now */
2140 for (j = 1; j < num_sregs; ++j) {
2141 int sreg = sregs [j];
2142 int dest_sreg = dest_sregs [j];
2144 if (j == 2 && dest_sreg != -1) {
2147 g_assert (sreg == dest_sreg);
2149 for (k = 0; k < num_sregs; ++k) {
2151 g_assert (sregs [k] != dest_sreg);
2156 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2157 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2158 mono_regstate_free_int (rs, ins->sreg1);
2160 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2161 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2162 mono_regstate_free_int (rs, ins->sreg2);
2165 DEBUG (mono_print_ins_index (i, ins));
2168 // FIXME: Set MAX_FREGS to 8
2169 // FIXME: Optimize generated code
2170 #if MONO_ARCH_USE_FPSTACK
2172 * Make a forward pass over the code, simulating the fp stack, making sure the
2173 * arguments required by the fp opcodes are at the top of the stack.
2176 MonoInst *prev = NULL;
2180 g_assert (num_sregs <= 2);
2182 for (ins = bb->code; ins; ins = ins->next) {
2183 spec = ins_get_spec (ins->opcode);
2185 DEBUG (printf ("processing:"));
2186 DEBUG (mono_print_ins_index (0, ins));
2188 if (ins->opcode == OP_FMOVE) {
2189 /* Do it by renaming the source to the destination on the stack */
2190 // FIXME: Is this correct ?
2191 for (i = 0; i < sp; ++i)
2192 if (fpstack [i] == ins->sreg1)
2193 fpstack [i] = ins->dreg;
2198 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2199 /* Arg1 must be in %st(1) */
2203 while ((i < sp) && (fpstack [i] != ins->sreg1))
2207 if (sp - 1 - i > 0) {
2208 /* First move it to %st(0) */
2209 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2211 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2212 fxch->inst_imm = sp - 1 - i;
2214 mono_bblock_insert_after_ins (bb, prev, fxch);
2217 tmp = fpstack [sp - 1];
2218 fpstack [sp - 1] = fpstack [i];
2222 /* Then move it to %st(1) */
2223 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2225 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2228 mono_bblock_insert_after_ins (bb, prev, fxch);
2231 tmp = fpstack [sp - 1];
2232 fpstack [sp - 1] = fpstack [sp - 2];
2233 fpstack [sp - 2] = tmp;
2236 if (sreg2_is_fp (spec)) {
2239 if (fpstack [sp - 1] != ins->sreg2) {
2243 while ((i < sp) && (fpstack [i] != ins->sreg2))
2247 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2249 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2250 fxch->inst_imm = sp - 1 - i;
2252 mono_bblock_insert_after_ins (bb, prev, fxch);
2255 tmp = fpstack [sp - 1];
2256 fpstack [sp - 1] = fpstack [i];
2263 if (sreg1_is_fp (spec)) {
2266 if (fpstack [sp - 1] != ins->sreg1) {
2270 while ((i < sp) && (fpstack [i] != ins->sreg1))
2274 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2276 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2277 fxch->inst_imm = sp - 1 - i;
2279 mono_bblock_insert_after_ins (bb, prev, fxch);
2282 tmp = fpstack [sp - 1];
2283 fpstack [sp - 1] = fpstack [i];
2290 if (dreg_is_fp (spec)) {
2292 fpstack [sp ++] = ins->dreg;
2295 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2297 for (i = 0; i < sp; ++i)
2298 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2305 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2306 /* Remove remaining items from the fp stack */
2308 * These can remain for example as a result of a dead fmove like in
2309 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2312 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2313 mono_add_ins_to_end (bb, ins);
2322 mono_opcode_to_cond (int opcode)
2334 case OP_COND_EXC_EQ:
2335 case OP_COND_EXC_IEQ:
2344 case OP_COND_EXC_NE_UN:
2345 case OP_COND_EXC_INE_UN:
2346 case OP_CMOV_INE_UN:
2347 case OP_CMOV_LNE_UN:
2374 case OP_COND_EXC_LT:
2375 case OP_COND_EXC_ILT:
2388 case OP_COND_EXC_GT:
2389 case OP_COND_EXC_IGT:
2398 case OP_COND_EXC_LE_UN:
2399 case OP_COND_EXC_ILE_UN:
2400 case OP_CMOV_ILE_UN:
2401 case OP_CMOV_LLE_UN:
2408 case OP_CMOV_IGE_UN:
2409 case OP_CMOV_LGE_UN:
2420 case OP_COND_EXC_LT_UN:
2421 case OP_COND_EXC_ILT_UN:
2422 case OP_CMOV_ILT_UN:
2423 case OP_CMOV_LLT_UN:
2434 case OP_COND_EXC_GT_UN:
2435 case OP_COND_EXC_IGT_UN:
2436 case OP_CMOV_IGT_UN:
2437 case OP_CMOV_LGT_UN:
2440 printf ("%s\n", mono_inst_name (opcode));
2441 g_assert_not_reached ();
2442 return (CompRelation)0;
2447 mono_negate_cond (CompRelation cond)
2471 g_assert_not_reached ();
2476 mono_opcode_to_type (int opcode, int cmp_opcode)
2478 if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2480 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2482 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2484 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2486 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2488 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2490 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2492 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2494 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2495 switch (cmp_opcode) {
2497 case OP_ICOMPARE_IMM:
2503 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2509 * mono_peephole_ins:
2511 * Perform some architecture independent peephole optimizations.
2514 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2516 int filter = FILTER_IL_SEQ_POINT;
2517 MonoInst *last_ins = mono_inst_prev (ins, filter);
2519 switch (ins->opcode) {
2521 /* remove unnecessary multiplication with 1 */
2522 if (ins->inst_imm == 1) {
2523 if (ins->dreg != ins->sreg1)
2524 ins->opcode = OP_MOVE;
2526 MONO_DELETE_INS (bb, ins);
2529 case OP_LOAD_MEMBASE:
2530 case OP_LOADI4_MEMBASE:
2532 * Note: if reg1 = reg2 the load op is removed
2534 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2535 * OP_LOAD_MEMBASE offset(basereg), reg2
2537 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2538 * OP_MOVE reg1, reg2
2540 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2541 last_ins = mono_inst_prev (ins, filter);
2543 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2544 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2545 ins->inst_basereg == last_ins->inst_destbasereg &&
2546 ins->inst_offset == last_ins->inst_offset) {
2547 if (ins->dreg == last_ins->sreg1) {
2548 MONO_DELETE_INS (bb, ins);
2551 ins->opcode = OP_MOVE;
2552 ins->sreg1 = last_ins->sreg1;
2556 * Note: reg1 must be different from the basereg in the second load
2557 * Note: if reg1 = reg2 is equal then second load is removed
2559 * OP_LOAD_MEMBASE offset(basereg), reg1
2560 * OP_LOAD_MEMBASE offset(basereg), reg2
2562 * OP_LOAD_MEMBASE offset(basereg), reg1
2563 * OP_MOVE reg1, reg2
2565 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2566 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2567 ins->inst_basereg != last_ins->dreg &&
2568 ins->inst_basereg == last_ins->inst_basereg &&
2569 ins->inst_offset == last_ins->inst_offset) {
2571 if (ins->dreg == last_ins->dreg) {
2572 MONO_DELETE_INS (bb, ins);
2574 ins->opcode = OP_MOVE;
2575 ins->sreg1 = last_ins->dreg;
2578 //g_assert_not_reached ();
2582 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2583 * OP_LOAD_MEMBASE offset(basereg), reg
2585 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2586 * OP_ICONST reg, imm
2588 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2589 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2590 ins->inst_basereg == last_ins->inst_destbasereg &&
2591 ins->inst_offset == last_ins->inst_offset) {
2592 ins->opcode = OP_ICONST;
2593 ins->inst_c0 = last_ins->inst_imm;
2594 g_assert_not_reached (); // check this rule
2598 case OP_LOADI1_MEMBASE:
2599 case OP_LOADU1_MEMBASE:
2601 * Note: if reg1 = reg2 the load op is removed
2603 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2604 * OP_LOAD_MEMBASE offset(basereg), reg2
2606 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2607 * OP_MOVE reg1, reg2
2609 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2610 ins->inst_basereg == last_ins->inst_destbasereg &&
2611 ins->inst_offset == last_ins->inst_offset) {
2612 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2613 ins->sreg1 = last_ins->sreg1;
2616 case OP_LOADI2_MEMBASE:
2617 case OP_LOADU2_MEMBASE:
2619 * Note: if reg1 = reg2 the load op is removed
2621 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2622 * OP_LOAD_MEMBASE offset(basereg), reg2
2624 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2625 * OP_MOVE reg1, reg2
2627 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2628 ins->inst_basereg == last_ins->inst_destbasereg &&
2629 ins->inst_offset == last_ins->inst_offset) {
2630 #if SIZEOF_REGISTER == 8
2631 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2633 /* The definition of OP_PCONV_TO_U2 is wrong */
2634 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2636 ins->sreg1 = last_ins->sreg1;
2639 case OP_LOADX_MEMBASE:
2640 if (last_ins && last_ins->opcode == OP_STOREX_MEMBASE &&
2641 ins->inst_basereg == last_ins->inst_destbasereg &&
2642 ins->inst_offset == last_ins->inst_offset) {
2643 if (ins->dreg == last_ins->sreg1) {
2644 MONO_DELETE_INS (bb, ins);
2647 ins->opcode = OP_XMOVE;
2648 ins->sreg1 = last_ins->sreg1;
2659 if (ins->dreg == ins->sreg1) {
2660 MONO_DELETE_INS (bb, ins);
2666 * OP_MOVE sreg, dreg
2667 * OP_MOVE dreg, sreg
2669 if (last_ins && last_ins->opcode == ins->opcode &&
2670 ins->sreg1 == last_ins->dreg &&
2671 ins->dreg == last_ins->sreg1) {
2672 MONO_DELETE_INS (bb, ins);
2676 MONO_DELETE_INS (bb, ins);
2682 mini_exception_id_by_name (const char *name)
2684 if (strcmp (name, "IndexOutOfRangeException") == 0)
2685 return MONO_EXC_INDEX_OUT_OF_RANGE;
2686 if (strcmp (name, "OverflowException") == 0)
2687 return MONO_EXC_OVERFLOW;
2688 if (strcmp (name, "ArithmeticException") == 0)
2689 return MONO_EXC_ARITHMETIC;
2690 if (strcmp (name, "DivideByZeroException") == 0)
2691 return MONO_EXC_DIVIDE_BY_ZERO;
2692 if (strcmp (name, "InvalidCastException") == 0)
2693 return MONO_EXC_INVALID_CAST;
2694 if (strcmp (name, "NullReferenceException") == 0)
2695 return MONO_EXC_NULL_REF;
2696 if (strcmp (name, "ArrayTypeMismatchException") == 0)
2697 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2698 if (strcmp (name, "ArgumentException") == 0)
2699 return MONO_EXC_ARGUMENT;
2700 g_error ("Unknown intrinsic exception %s\n", name);
2705 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2709 MonoClassField *field;
2710 MonoType *ftype, *prev_ftype = NULL;
2713 klass = mono_class_from_mono_type (t);
2715 while ((field = mono_class_get_fields (klass, &iter))) {
2716 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2718 ftype = mono_field_get_type (field);
2719 ftype = mini_native_type_replace_type (ftype);
2721 if (MONO_TYPE_ISSTRUCT (ftype)) {
2722 int nested_nfields, nested_esize;
2724 if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2726 if (nested_esize == 4)
2727 ftype = &mono_defaults.single_class->byval_arg;
2729 ftype = &mono_defaults.double_class->byval_arg;
2730 if (prev_ftype && prev_ftype->type != ftype->type)
2733 nfields += nested_nfields;
2735 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2737 if (prev_ftype && prev_ftype->type != ftype->type)
2745 *out_nfields = nfields;
2746 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2751 mono_regstate_new (void)
2753 MonoRegState* rs = g_new0 (MonoRegState, 1);
2755 rs->next_vreg = MAX (MONO_MAX_IREGS, MONO_MAX_FREGS);
2756 #ifdef MONO_ARCH_NEED_SIMD_BANK
2757 rs->next_vreg = MAX (rs->next_vreg, MONO_MAX_XREGS);
2764 mono_regstate_free (MonoRegState *rs) {
2765 g_free (rs->vassign);
2769 #endif /* DISABLE_JIT */
2772 mono_is_regsize_var (MonoType *t)
2774 t = mini_get_underlying_type (t);
2785 case MONO_TYPE_FNPTR:
2786 #if SIZEOF_REGISTER == 8
2791 case MONO_TYPE_OBJECT:
2792 case MONO_TYPE_STRING:
2793 case MONO_TYPE_CLASS:
2794 case MONO_TYPE_SZARRAY:
2795 case MONO_TYPE_ARRAY:
2797 case MONO_TYPE_GENERICINST:
2798 if (!mono_type_generic_inst_is_valuetype (t))
2801 case MONO_TYPE_VALUETYPE: