2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
11 #include <mono/metadata/appdomain.h>
12 #include <mono/metadata/debug-helpers.h>
13 #include <mono/metadata/threads.h>
14 #include <mono/metadata/profiler-private.h>
15 #include <mono/utils/mono-math.h>
20 #include "mini-arch.h"
22 #define DEBUG(a) if (cfg->verbose_level > 1) a
24 #if defined(__x86_64__)
25 const char * const amd64_desc [OP_LAST];
26 static const char*const * ins_spec = amd64_desc;
27 #elif defined(__sparc__) || defined(sparc)
28 const char * const sparc_desc [OP_LAST];
29 static const char*const * ins_spec = sparc_desc;
30 #elif defined(__i386__)
32 extern const char * const pentium_desc [OP_LAST];
34 const char * const pentium_desc [OP_LAST];
36 static const char*const * ins_spec = pentium_desc;
37 #elif defined(__ia64__)
38 const char * const ia64_desc [OP_LAST];
39 static const char*const * ins_spec = ia64_desc;
40 #elif defined(__arm__)
41 const char * const arm_cpu_desc [OP_LAST];
42 static const char*const * ins_spec = arm_cpu_desc;
44 #error "Not implemented"
47 #define use_fpstack MONO_ARCH_USE_FPSTACK
50 mono_regname_full (int reg, gboolean fp)
53 return mono_arch_fregname (reg);
55 return mono_arch_regname (reg);
59 mono_call_inst_add_outarg_reg (MonoCallInst *call, int vreg, int hreg, gboolean fp)
63 regpair = (((guint32)hreg) << 24) + vreg;
65 call->out_freg_args = g_slist_append (call->out_freg_args, (gpointer)(gssize)(regpair));
67 call->out_ireg_args = g_slist_append (call->out_ireg_args, (gpointer)(gssize)(regpair));
71 * returns the offset used by spillvar. It allocates a new
72 * spill variable if necessary.
75 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
77 MonoSpillInfo **si, *info;
80 si = &cfg->spill_info;
82 while (i <= spillvar) {
85 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
87 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
88 info->offset = cfg->stack_offset;
89 cfg->stack_offset += sizeof (gpointer);
91 cfg->stack_offset += sizeof (gpointer);
92 info->offset = - cfg->stack_offset;
103 g_assert_not_reached ();
108 * returns the offset used by spillvar. It allocates a new
109 * spill float variable if necessary.
110 * (same as mono_spillvar_offset but for float)
113 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
115 MonoSpillInfo **si, *info;
118 si = &cfg->spill_info_float;
120 while (i <= spillvar) {
123 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
125 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
126 cfg->stack_offset += 7;
127 cfg->stack_offset &= ~7;
128 info->offset = cfg->stack_offset;
129 cfg->stack_offset += sizeof (double);
132 cfg->stack_offset += sizeof (double);
133 info->offset = - cfg->stack_offset;
138 return (*si)->offset;
144 g_assert_not_reached ();
149 * Creates a store for spilled floating point items
152 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
155 MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
157 store->inst_destbasereg = cfg->frame_reg;
158 store->inst_offset = mono_spillvar_offset_float (cfg, spill);
160 DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)store->inst_offset, reg));
165 * Creates a load for spilled floating point items
168 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
171 MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
173 load->inst_basereg = cfg->frame_reg;
174 load->inst_offset = mono_spillvar_offset_float (cfg, spill);
176 DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)load->inst_offset, reg));
180 #define regmask(reg) (((regmask_t)1) << (reg))
182 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
183 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
184 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
185 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
186 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
187 #define is_local_freg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
188 #define ireg_is_freeable(r) is_local_ireg ((r))
189 #define freg_is_freeable(r) is_hard_freg ((r))
191 #define reg_is_freeable(r,fp) ((fp) ? freg_is_freeable ((r)) : ireg_is_freeable ((r)))
192 #define is_hard_reg(r,fp) ((fp) ? ((r) < MONO_MAX_FREGS) : ((r) < MONO_MAX_IREGS))
193 #define is_soft_reg(r,fp) (!is_hard_reg((r),(fp)))
194 #define rassign(cfg,reg,fp) ((fp) ? (cfg)->rs->fassign [(reg)] : (cfg)->rs->iassign [(reg)])
195 #define sreg1_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC1] == 'f')
196 #define sreg2_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC2] == 'f')
198 #ifdef MONO_ARCH_INST_IS_FLOAT
199 #define dreg_is_fp(ins) (MONO_ARCH_INST_IS_FLOAT (ins_spec [(ins)->opcode] [MONO_INST_DEST]))
201 #define dreg_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_DEST] == 'f')
204 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
206 #ifdef MONO_ARCH_IS_GLOBAL_IREG
207 #undef is_global_ireg
208 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
216 int flags; /* used to track fp spill/load */
217 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
221 print_ins (int i, MonoInst *ins)
223 const char *spec = ins_spec [ins->opcode];
224 g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
226 g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
228 if (spec [MONO_INST_DEST]) {
229 gboolean fp = dreg_is_fp (ins);
230 if (is_soft_reg (ins->dreg, fp)) {
231 if (spec [MONO_INST_DEST] == 'b') {
232 if (ins->inst_offset == 0)
233 g_print (" [R%d] <-", ins->dreg);
235 g_print (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
238 g_print (" R%d <-", ins->dreg);
239 } else if (spec [MONO_INST_DEST] == 'b') {
240 if (ins->inst_offset == 0)
241 g_print (" [%s] <-", mono_arch_regname (ins->dreg));
243 g_print (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
245 g_print (" %s <-", mono_regname_full (ins->dreg, fp));
247 if (spec [MONO_INST_SRC1]) {
248 gboolean fp = (spec [MONO_INST_SRC1] == 'f');
249 if (is_soft_reg (ins->sreg1, fp))
250 g_print (" R%d", ins->sreg1);
251 else if (spec [MONO_INST_SRC1] == 'b')
252 g_print (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
254 g_print (" %s", mono_regname_full (ins->sreg1, fp));
256 if (spec [MONO_INST_SRC2]) {
257 gboolean fp = (spec [MONO_INST_SRC2] == 'f');
258 if (is_soft_reg (ins->sreg2, fp))
259 g_print (" R%d", ins->sreg2);
261 g_print (" %s", mono_regname_full (ins->sreg2, fp));
263 if (spec [MONO_INST_CLOB])
264 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
269 print_regtrack (RegTrack *t, int num)
275 for (i = 0; i < num; ++i) {
278 if (i >= MONO_MAX_IREGS) {
279 g_snprintf (buf, sizeof(buf), "R%d", i);
282 r = mono_arch_regname (i);
283 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
287 typedef struct InstList InstList;
295 static inline InstList*
296 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
298 InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
308 * Force the spilling of the variable in the symbolic register 'reg'.
311 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg, gboolean fp)
315 int *assign, *symbolic;
318 assign = cfg->rs->fassign;
319 symbolic = cfg->rs->fsymbolic;
322 assign = cfg->rs->iassign;
323 symbolic = cfg->rs->isymbolic;
327 /*i = cfg->rs->isymbolic [sel];
328 g_assert (i == reg);*/
330 spill = ++cfg->spill_count;
331 assign [i] = -spill - 1;
333 mono_regstate_free_float (cfg->rs, sel);
335 mono_regstate_free_int (cfg->rs, sel);
336 /* we need to create a spill var and insert a load to sel after the current instruction */
338 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
340 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
342 load->inst_basereg = cfg->frame_reg;
343 load->inst_offset = mono_spillvar_offset (cfg, spill);
345 while (ins->next != item->prev->data)
348 load->next = ins->next;
350 DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
352 i = mono_regstate_alloc_float (cfg->rs, regmask (sel));
354 i = mono_regstate_alloc_int (cfg->rs, regmask (sel));
361 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, regmask_t regmask, int reg, gboolean fp)
365 int *assign, *symbolic;
368 assign = cfg->rs->fassign;
369 symbolic = cfg->rs->fsymbolic;
372 assign = cfg->rs->iassign;
373 symbolic = cfg->rs->isymbolic;
376 DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08lx (R%d <- R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2));
377 /* exclude the registers in the current instruction */
378 if ((sreg1_is_fp (ins) == fp) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, fp) || (is_soft_reg (ins->sreg1, fp) && rassign (cfg, ins->sreg1, fp) >= 0))) {
379 if (is_soft_reg (ins->sreg1, fp))
380 regmask &= ~ (regmask (rassign (cfg, ins->sreg1, fp)));
382 regmask &= ~ (regmask (ins->sreg1));
383 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_regname_full (ins->sreg1, fp)));
385 if ((sreg2_is_fp (ins) == fp) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, fp) || (is_soft_reg (ins->sreg2, fp) && rassign (cfg, ins->sreg2, fp) >= 0))) {
386 if (is_soft_reg (ins->sreg2, fp))
387 regmask &= ~ (regmask (rassign (cfg, ins->sreg2, fp)));
389 regmask &= ~ (regmask (ins->sreg2));
390 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_regname_full (ins->sreg2, fp), ins->sreg2));
392 if ((dreg_is_fp (ins) == fp) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, fp)) {
393 regmask &= ~ (regmask (ins->dreg));
394 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, fp)));
397 DEBUG (g_print ("\t\tavailable regmask: 0x%08lx\n", (guint64)regmask));
398 g_assert (regmask); /* need at least a register we can free */
400 /* we should track prev_use and spill the register that's farther */
402 for (i = 0; i < MONO_MAX_FREGS; ++i) {
403 if (regmask & (regmask (i))) {
405 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_fregname (sel), cfg->rs->fsymbolic [sel]));
410 i = cfg->rs->fsymbolic [sel];
411 spill = ++cfg->spill_count;
412 cfg->rs->fassign [i] = -spill - 1;
413 mono_regstate_free_float (cfg->rs, sel);
416 for (i = 0; i < MONO_MAX_IREGS; ++i) {
417 if (regmask & (regmask (i))) {
419 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->isymbolic [sel]));
424 i = cfg->rs->isymbolic [sel];
425 spill = ++cfg->spill_count;
426 cfg->rs->iassign [i] = -spill - 1;
427 mono_regstate_free_int (cfg->rs, sel);
430 /* we need to create a spill var and insert a load to sel after the current instruction */
431 MONO_INST_NEW (cfg, load, fp ? OP_LOADR8_MEMBASE : OP_LOAD_MEMBASE);
433 load->inst_basereg = cfg->frame_reg;
434 load->inst_offset = mono_spillvar_offset (cfg, spill);
436 while (ins->next != item->prev->data)
439 load->next = ins->next;
441 DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
443 i = mono_regstate_alloc_float (cfg->rs, regmask (sel));
445 i = mono_regstate_alloc_int (cfg->rs, regmask (sel));
452 free_up_ireg (MonoCompile *cfg, InstList *item, MonoInst *ins, int hreg)
454 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
455 DEBUG (g_print ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
456 get_register_force_spilling (cfg, item, ins, cfg->rs->isymbolic [hreg], FALSE);
457 mono_regstate_free_int (cfg->rs, hreg);
462 free_up_reg (MonoCompile *cfg, InstList *item, MonoInst *ins, int hreg, gboolean fp)
465 if (!(cfg->rs->ffree_mask & (regmask (hreg)))) {
466 DEBUG (g_print ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
467 get_register_force_spilling (cfg, item, ins, cfg->rs->isymbolic [hreg], fp);
468 mono_regstate_free_float (cfg->rs, hreg);
472 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
473 DEBUG (g_print ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
474 get_register_force_spilling (cfg, item, ins, cfg->rs->isymbolic [hreg], fp);
475 mono_regstate_free_int (cfg->rs, hreg);
481 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins, const unsigned char *ip, gboolean fp)
486 MONO_INST_NEW (cfg, copy, OP_FMOVE);
488 MONO_INST_NEW (cfg, copy, OP_MOVE);
494 copy->next = ins->next;
495 copy->cil_code = ins->cil_code;
498 DEBUG (g_print ("\tforced copy from %s to %s\n", mono_regname_full (src, fp), mono_regname_full (dest, fp)));
503 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins, gboolean fp)
506 MONO_INST_NEW (cfg, store, fp ? OP_STORER8_MEMBASE_REG : OP_STORE_MEMBASE_REG);
508 store->inst_destbasereg = cfg->frame_reg;
509 store->inst_offset = mono_spillvar_offset (cfg, spill);
511 store->next = ins->next;
514 DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, fp)));
519 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
523 prev = item->next->data;
525 while (prev->next != ins)
527 to_insert->next = ins;
528 prev->next = to_insert;
530 to_insert->next = ins;
533 * needed otherwise in the next instruction we can add an ins to the
534 * end and that would get past this instruction.
536 item->data = to_insert;
539 /* flags used in reginfo->flags */
541 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
542 MONO_FP_NEEDS_SPILL = regmask (1),
543 MONO_FP_NEEDS_LOAD = regmask (2)
547 alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
551 if (info && info->preferred_mask) {
552 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
554 DEBUG (g_print ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
559 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
561 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, FALSE);
567 alloc_float_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t dest_mask, int sym_reg)
571 val = mono_regstate_alloc_float (cfg->rs, dest_mask);
574 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, TRUE);
581 alloc_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, gboolean fp)
584 return alloc_float_reg (cfg, tmp, ins, dest_mask, sym_reg);
586 return alloc_int_reg (cfg, tmp, ins, dest_mask, sym_reg, info);
590 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, gboolean fp)
593 g_assert (reg >= MONO_MAX_FREGS);
594 g_assert (hreg < MONO_MAX_FREGS);
595 g_assert (! is_global_freg (hreg));
597 rs->fassign [reg] = hreg;
598 rs->fsymbolic [hreg] = reg;
599 rs->ffree_mask &= ~ (regmask (hreg));
602 g_assert (reg >= MONO_MAX_IREGS);
603 g_assert (hreg < MONO_MAX_IREGS);
604 g_assert (! is_global_ireg (hreg));
606 rs->iassign [reg] = hreg;
607 rs->isymbolic [hreg] = reg;
608 rs->ifree_mask &= ~ (regmask (hreg));
613 assign_ireg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg)
615 assign_reg (cfg, rs, reg, hreg, FALSE);
619 * Local register allocation.
620 * We first scan the list of instructions and we save the liveness info of
621 * each register (when the register is first used, when it's value is set etc.).
622 * We also reverse the list of instructions (in the InstList list) because assigning
623 * registers backwards allows for more tricks to be used.
626 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
629 MonoRegState *rs = cfg->rs;
631 RegTrack *reginfo, *reginfof;
632 RegTrack *reginfo1, *reginfo2, *reginfod;
633 InstList *tmp, *reversed = NULL;
635 GList *fspill_list = NULL;
642 rs->next_vireg = bb->max_ireg;
643 rs->next_vfreg = bb->max_freg;
644 mono_regstate_assign (rs);
645 reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
646 reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
647 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
648 rs->ffree_mask = MONO_ARCH_CALLEE_FREGS;
651 rs->ffree_mask = 0xff & ~(regmask (MONO_ARCH_FPSTACK_SIZE));
655 /*if (cfg->opt & MONO_OPT_COPYPROP)
656 local_copy_prop (cfg, ins);*/
660 DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
661 /* forward pass on the instructions to collect register liveness info */
663 spec = ins_spec [ins->opcode];
666 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
669 DEBUG (print_ins (i, ins));
677 if (spec [MONO_INST_SRC1] == 'f') {
678 spill = g_list_first (fspill_list);
679 if (spill && fpcount < MONO_ARCH_FPSTACK_SIZE) {
680 reginfof [ins->sreg1].flags |= MONO_FP_NEEDS_LOAD;
681 fspill_list = g_list_remove (fspill_list, spill->data);
686 if (spec [MONO_INST_SRC2] == 'f') {
687 spill = g_list_first (fspill_list);
689 reginfof [ins->sreg2].flags |= MONO_FP_NEEDS_LOAD;
690 fspill_list = g_list_remove (fspill_list, spill->data);
691 if (fpcount >= MONO_ARCH_FPSTACK_SIZE) {
693 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
694 reginfof [ins->sreg2].flags |= MONO_FP_NEEDS_LOAD_SPILL;
700 if (dreg_is_fp (ins)) {
701 if (use_fpstack && (spec [MONO_INST_CLOB] != 'm')) {
702 if (fpcount >= MONO_ARCH_FPSTACK_SIZE) {
703 reginfof [ins->dreg].flags |= MONO_FP_NEEDS_SPILL;
705 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
713 if (spec [MONO_INST_SRC1]) {
714 if (spec [MONO_INST_SRC1] == 'f')
718 reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
719 reginfo1 [ins->sreg1].last_use = i;
720 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
721 /* The virtual register is allocated sequentially */
722 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
723 reginfo1 [ins->sreg1 + 1].last_use = i;
724 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
725 reginfo1 [ins->sreg1 + 1].born_in = i;
730 if (spec [MONO_INST_SRC2]) {
731 if (spec [MONO_INST_SRC2] == 'f')
735 reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
736 reginfo2 [ins->sreg2].last_use = i;
737 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
738 /* The virtual register is allocated sequentially */
739 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
740 reginfo2 [ins->sreg2 + 1].last_use = i;
741 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
742 reginfo2 [ins->sreg2 + 1].born_in = i;
747 if (spec [MONO_INST_DEST]) {
750 if (dreg_is_fp (ins))
754 if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
755 reginfod [ins->dreg].killed_in = i;
756 reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
757 reginfod [ins->dreg].last_use = i;
758 if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
759 reginfod [ins->dreg].born_in = i;
761 dest_dreg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_DEST]);
763 reginfod [ins->dreg].preferred_mask = (regmask (dest_dreg));
765 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
766 /* The virtual register is allocated sequentially */
767 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
768 reginfod [ins->dreg + 1].last_use = i;
769 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
770 reginfod [ins->dreg + 1].born_in = i;
771 if (MONO_ARCH_INST_REGPAIR_REG2 (spec [MONO_INST_DEST], -1) != -1)
772 reginfod [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec [MONO_INST_DEST], -1);
778 if (spec [MONO_INST_CLOB] == 'c') {
779 /* A call instruction implicitly uses all registers in call->out_ireg_args */
781 MonoCallInst *call = (MonoCallInst*)ins;
784 list = call->out_ireg_args;
790 regpair = (guint32)(gssize)(list->data);
791 hreg = regpair >> 24;
792 reg = regpair & 0xffffff;
794 reginfo [reg].prev_use = reginfo [reg].last_use;
795 reginfo [reg].last_use = i;
797 list = g_slist_next (list);
801 list = call->out_freg_args;
802 if (!use_fpstack && list) {
807 regpair = (guint32)(gssize)(list->data);
808 hreg = regpair >> 24;
809 reg = regpair & 0xffffff;
811 reginfof [reg].prev_use = reginfof [reg].last_use;
812 reginfof [reg].last_use = i;
814 list = g_slist_next (list);
819 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
824 // todo: check if we have anything left on fp stack, in verify mode?
827 DEBUG (print_regtrack (reginfo, rs->next_vireg));
828 DEBUG (print_regtrack (reginfof, rs->next_vfreg));
831 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
832 int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
833 int dreg_high, sreg1_high;
834 regmask_t dreg_mask, sreg1_mask, sreg2_mask, mask;
835 const unsigned char *ip;
838 spec = ins_spec [ins->opcode];
846 dreg_mask = dreg_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
847 sreg1_mask = sreg1_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
848 sreg2_mask = sreg2_is_fp (ins) ? MONO_ARCH_CALLEE_FREGS : MONO_ARCH_CALLEE_REGS;
850 DEBUG (g_print ("processing:"));
851 DEBUG (print_ins (i, ins));
858 dest_sreg1 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC1]);
859 dest_sreg2 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC2]);
860 dest_dreg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_DEST]);
861 clob_reg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_CLOB]);
862 sreg2_mask &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
867 if (use_fpstack && (spec [MONO_INST_CLOB] != 'm')) {
868 if (dreg_is_fp (ins)) {
869 if (reginfof [ins->dreg].flags & MONO_FP_NEEDS_SPILL) {
872 spill_node = g_list_first (fspill_list);
873 g_assert (spill_node);
875 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
876 insert_before_ins (ins, tmp, store);
877 fspill_list = g_list_remove (fspill_list, spill_node->data);
882 if (spec [MONO_INST_SRC1] == 'f') {
883 if (reginfof [ins->sreg1].flags & MONO_FP_NEEDS_LOAD) {
885 MonoInst *store = NULL;
887 if (reginfof [ins->sreg1].flags & MONO_FP_NEEDS_LOAD_SPILL) {
889 spill_node = g_list_first (fspill_list);
890 g_assert (spill_node);
892 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
893 fspill_list = g_list_remove (fspill_list, spill_node->data);
897 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
898 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
899 insert_before_ins (ins, tmp, load);
901 insert_before_ins (load, tmp, store);
905 if (spec [MONO_INST_SRC2] == 'f') {
906 if (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD) {
908 MonoInst *store = NULL;
910 if (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD_SPILL) {
913 spill_node = g_list_first (fspill_list);
914 g_assert (spill_node);
915 if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg2].flags & MONO_FP_NEEDS_LOAD_SPILL))
916 spill_node = g_list_next (spill_node);
918 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
919 fspill_list = g_list_remove (fspill_list, spill_node->data);
923 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
924 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
925 insert_before_ins (ins, tmp, load);
927 insert_before_ins (load, tmp, store);
935 if (dest_sreg2 != -1) {
936 if (rs->ifree_mask & (regmask (dest_sreg2))) {
937 if (is_global_ireg (ins->sreg2)) {
938 /* Argument already in hard reg, need to copy */
939 MonoInst *copy = create_copy_ins (cfg, dest_sreg2, ins->sreg2, NULL, ip, FALSE);
940 insert_before_ins (ins, tmp, copy);
943 DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
944 assign_ireg (cfg, rs, ins->sreg2, dest_sreg2);
947 int need_spill = TRUE;
949 dreg_mask &= ~ (regmask (dest_sreg2));
950 sreg1_mask &= ~ (regmask (dest_sreg2));
953 * First check if dreg is assigned to dest_sreg2, since we
954 * can't spill a dreg.
956 val = rs->iassign [ins->dreg];
957 if (val == dest_sreg2 && ins->dreg != ins->sreg2) {
959 * the destination register is already assigned to
960 * dest_sreg2: we need to allocate another register for it
961 * and then copy from this to dest_sreg2.
964 new_dest = alloc_int_reg (cfg, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
965 g_assert (new_dest >= 0);
966 DEBUG (g_print ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg2)));
968 prev_dreg = ins->dreg;
969 assign_ireg (cfg, rs, ins->dreg, new_dest);
970 clob_dreg = ins->dreg;
971 create_copy_ins (cfg, dest_sreg2, new_dest, ins, ip, FALSE);
975 if (is_global_ireg (ins->sreg2)) {
976 MonoInst *copy = create_copy_ins (cfg, dest_sreg2, ins->sreg2, NULL, ip, FALSE);
977 insert_before_ins (ins, tmp, copy);
980 val = rs->iassign [ins->sreg2];
981 if (val == dest_sreg2) {
982 /* sreg2 is already assigned to the correct register */
985 else if ((val >= 0) || (val < -1)) {
986 /* FIXME: sreg2 already assigned to another register */
987 g_assert_not_reached ();
992 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg2]));
993 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_sreg2], FALSE);
994 mono_regstate_free_int (rs, dest_sreg2);
997 if (!is_global_ireg (ins->sreg2))
998 /* force-set sreg2 */
999 assign_ireg (cfg, rs, ins->sreg2, dest_sreg2);
1001 ins->sreg2 = dest_sreg2;
1007 fp = dreg_is_fp (ins);
1008 if (spec [MONO_INST_DEST] && (!fp || (fp && !use_fpstack)) && is_soft_reg (ins->dreg, fp))
1009 prev_dreg = ins->dreg;
1011 if (spec [MONO_INST_DEST] == 'b') {
1013 * The dest reg is read by the instruction, not written, so
1014 * avoid allocating sreg1/sreg2 to the same reg.
1016 if (dest_sreg1 != -1)
1017 dreg_mask &= ~ (regmask (dest_sreg1));
1018 if (dest_sreg2 != -1)
1019 dreg_mask &= ~ (regmask (dest_sreg2));
1023 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1024 * various complex situations.
1026 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1027 guint32 dreg2, dest_dreg2;
1029 g_assert (is_soft_reg (ins->dreg, fp));
1031 if (dest_dreg != -1) {
1032 if (rs->iassign [ins->dreg] != dest_dreg)
1033 free_up_ireg (cfg, tmp, ins, dest_dreg);
1035 dreg2 = ins->dreg + 1;
1036 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec [MONO_INST_DEST], dest_dreg);
1037 if (dest_dreg2 != -1) {
1038 if (rs->iassign [dreg2] != dest_dreg2)
1039 free_up_ireg (cfg, tmp, ins, dest_dreg2);
1044 if ((!fp || (fp && !use_fpstack)) && (is_soft_reg (ins->dreg, fp))) {
1045 if (dest_dreg != -1)
1046 dreg_mask = (regmask (dest_dreg));
1048 val = rassign (cfg, ins->dreg, fp);
1053 /* the register gets spilled after this inst */
1056 val = alloc_reg (cfg, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], fp);
1057 assign_reg (cfg, rs, ins->dreg, val, fp);
1059 create_spilled_store (cfg, spill, val, prev_dreg, ins, fp);
1062 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, fp), ins->dreg));
1066 /* Handle regpairs */
1067 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1068 int reg2 = prev_dreg + 1;
1071 g_assert (prev_dreg > -1);
1072 g_assert (!is_global_ireg (rs->iassign [prev_dreg]));
1073 mask = regpair_reg2_mask (spec [MONO_INST_DEST], rs->iassign [prev_dreg]);
1074 val = rs->iassign [reg2];
1078 /* the register gets spilled after this inst */
1081 val = mono_regstate_alloc_int (rs, mask);
1083 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1085 create_spilled_store (cfg, spill, val, reg2, ins, fp);
1088 if (! (mask & (regmask (val)))) {
1089 val = mono_regstate_alloc_int (rs, mask);
1091 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1093 /* Reallocate hreg to the correct register */
1094 create_copy_ins (cfg, rs->iassign [reg2], val, ins, ip, fp);
1096 mono_regstate_free_int (rs, rs->iassign [reg2]);
1100 DEBUG (g_print ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1101 assign_reg (cfg, rs, reg2, val, fp);
1106 if (reg_is_freeable (val, fp) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1107 DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1108 mono_regstate_free_int (rs, val);
1112 if ((!fp || (fp && !use_fpstack)) && prev_dreg >= 0 && is_soft_reg (prev_dreg, fp) && (fp ? reginfof : reginfo) [prev_dreg].born_in >= i) {
1114 * In theory, we could free up the hreg even if the vreg is alive,
1115 * but branches inside bblocks force us to assign the same hreg
1116 * to a vreg every time it is encountered.
1118 int dreg = rassign (cfg, prev_dreg, fp);
1119 g_assert (dreg >= 0);
1120 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, fp), prev_dreg, (fp ? reginfof : reginfo) [prev_dreg].born_in));
1122 mono_regstate_free_float (rs, dreg);
1124 mono_regstate_free_int (rs, dreg);
1127 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1128 /* this instruction only outputs to dest_dreg, need to copy */
1129 create_copy_ins (cfg, ins->dreg, dest_dreg, ins, ip, fp);
1130 ins->dreg = dest_dreg;
1133 if (rs->fsymbolic [dest_dreg] >= MONO_MAX_FREGS)
1134 free_up_reg (cfg, tmp, ins, dest_dreg, fp);
1137 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1138 free_up_reg (cfg, tmp, ins, dest_dreg, fp);
1142 if (spec [MONO_INST_DEST] == 'b') {
1144 * The dest reg is read by the instruction, not written, so
1145 * avoid allocating sreg1/sreg2 to the same reg.
1147 sreg1_mask &= ~ (regmask (ins->dreg));
1148 sreg2_mask &= ~ (regmask (ins->dreg));
1154 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1155 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1156 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg], FALSE);
1157 mono_regstate_free_int (rs, clob_reg);
1160 if (spec [MONO_INST_CLOB] == 'c') {
1161 int j, s, dreg, dreg2;
1164 clob_mask = MONO_ARCH_CALLEE_REGS;
1167 * Need to avoid spilling the dreg since the dreg is not really
1168 * clobbered by the call.
1170 if ((prev_dreg != -1) && !dreg_is_fp (ins))
1171 dreg = rassign (cfg, prev_dreg, dreg_is_fp (ins));
1175 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST]))
1176 dreg2 = rassign (cfg, prev_dreg + 1, dreg_is_fp (ins));
1180 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1182 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1) && (j != dreg) && (j != dreg2)) {
1183 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [j], FALSE);
1184 mono_regstate_free_int (rs, j);
1189 clob_mask = MONO_ARCH_CALLEE_FREGS;
1190 if ((prev_dreg != -1) && dreg_is_fp (ins))
1191 dreg = rassign (cfg, prev_dreg, dreg_is_fp (ins));
1195 for (j = 0; j < MONO_MAX_FREGS; ++j) {
1197 if ((clob_mask & s) && !(rs->ffree_mask & s) && (j != ins->sreg1) && (j != dreg)) {
1198 get_register_force_spilling (cfg, tmp, ins, rs->fsymbolic [j], TRUE);
1199 mono_regstate_free_float (rs, j);
1206 * TRACK ARGUMENT REGS
1208 if (spec [MONO_INST_CLOB] == 'c') {
1209 MonoCallInst *call = (MonoCallInst*)ins;
1213 * This needs to be done before assigning sreg1, so sreg1 will
1214 * not be assigned one of the argument regs.
1218 * Assign all registers in call->out_reg_args to the proper
1219 * argument registers.
1222 list = call->out_ireg_args;
1228 regpair = (guint32)(gssize)(list->data);
1229 hreg = regpair >> 24;
1230 reg = regpair & 0xffffff;
1232 assign_reg (cfg, rs, reg, hreg, FALSE);
1234 sreg1_mask &= ~(regmask (hreg));
1236 DEBUG (g_print ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1238 list = g_slist_next (list);
1240 g_slist_free (call->out_ireg_args);
1243 list = call->out_freg_args;
1244 if (list && !use_fpstack) {
1249 regpair = (guint32)(gssize)(list->data);
1250 hreg = regpair >> 24;
1251 reg = regpair & 0xffffff;
1253 assign_reg (cfg, rs, reg, hreg, TRUE);
1255 DEBUG (g_print ("\tassigned arg reg %s to R%d\n", mono_arch_fregname (hreg), reg));
1257 list = g_slist_next (list);
1260 if (call->out_freg_args)
1261 g_slist_free (call->out_freg_args);
1267 fp = sreg1_is_fp (ins);
1268 if ((!fp || (fp && !use_fpstack))) {
1269 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST]) && (spec [MONO_INST_CLOB] == '1')) {
1270 g_assert (is_soft_reg (ins->sreg1, fp));
1272 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1273 if (dest_sreg1 != -1)
1274 g_assert (dest_sreg1 == ins->dreg);
1275 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1276 g_assert (val >= 0);
1277 assign_reg (cfg, rs, ins->sreg1, val, fp);
1279 DEBUG (g_print ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, fp), ins->sreg1));
1281 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec [MONO_INST_SRC1], ins->dreg));
1282 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1283 g_assert (val >= 0);
1284 assign_reg (cfg, rs, ins->sreg1 + 1, val, fp);
1286 DEBUG (g_print ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, fp), ins->sreg1 + 1));
1288 /* Skip rest of this section */
1292 if (dest_sreg1 != -1) {
1293 sreg1_mask = regmask (dest_sreg1);
1295 if (!(rs->ifree_mask & (regmask (dest_sreg1)))) {
1296 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg1]));
1297 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_sreg1], FALSE);
1298 mono_regstate_free_int (rs, dest_sreg1);
1300 if (is_global_ireg (ins->sreg1)) {
1301 /* The argument is already in a hard reg, need to copy */
1302 MonoInst *copy = create_copy_ins (cfg, dest_sreg1, ins->sreg1, NULL, ip, FALSE);
1303 insert_before_ins (ins, tmp, copy);
1304 ins->sreg1 = dest_sreg1;
1308 if (is_soft_reg (ins->sreg1, fp)) {
1309 val = rassign (cfg, ins->sreg1, fp);
1310 prev_sreg1 = ins->sreg1;
1314 /* the register gets spilled after this inst */
1318 if (((ins->opcode == OP_MOVE) || (ins->opcode == OP_SETREG)) && !spill && !fp && (!is_global_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg))))) {
1320 * Allocate the same hreg to sreg1 as well so the
1321 * peephole can get rid of the move.
1323 sreg1_mask = regmask (ins->dreg);
1326 val = alloc_reg (cfg, tmp, ins, sreg1_mask, ins->sreg1, ®info [ins->sreg1], fp);
1327 assign_reg (cfg, rs, ins->sreg1, val, fp);
1328 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, fp), ins->sreg1));
1331 MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL, fp);
1333 * Need to insert before the instruction since it can
1336 insert_before_ins (ins, tmp, store);
1339 else if ((dest_sreg1 != -1) && (dest_sreg1 != val)) {
1340 g_assert_not_reached ();
1348 sreg2_mask &= ~(regmask (ins->sreg1));
1351 /* Handle the case when sreg1 is a regpair but dreg is not */
1352 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1]) && (spec [MONO_INST_CLOB] != '1')) {
1353 int reg2 = prev_sreg1 + 1;
1356 g_assert (prev_sreg1 > -1);
1357 g_assert (!is_global_ireg (rs->iassign [prev_sreg1]));
1358 mask = regpair_reg2_mask (spec [MONO_INST_SRC1], rs->iassign [prev_sreg1]);
1359 val = rs->iassign [reg2];
1363 /* the register gets spilled after this inst */
1366 val = mono_regstate_alloc_int (rs, mask);
1368 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1370 g_assert_not_reached ();
1373 if (! (mask & (regmask (val)))) {
1374 /* The vreg is already allocated to a wrong hreg */
1376 g_assert_not_reached ();
1378 val = mono_regstate_alloc_int (rs, mask);
1380 val = get_register_spilling (cfg, tmp, ins, mask, reg2, fp);
1382 /* Reallocate hreg to the correct register */
1383 create_copy_ins (cfg, rs->iassign [reg2], val, ins, ip, fp);
1385 mono_regstate_free_int (rs, rs->iassign [reg2]);
1391 DEBUG (g_print ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1392 assign_reg (cfg, rs, reg2, val, fp);
1395 /* Handle dreg==sreg1 */
1396 if (((dreg_is_fp (ins) && spec [MONO_INST_SRC1] == 'f' && !use_fpstack) || spec [MONO_INST_CLOB] == '1') && ins->dreg != ins->sreg1) {
1397 MonoInst *sreg2_copy = NULL;
1399 gboolean fp = (spec [MONO_INST_SRC1] == 'f');
1401 if (ins->dreg == ins->sreg2) {
1403 * copying sreg1 to dreg could clobber sreg2, so allocate a new
1406 int reg2 = alloc_reg (cfg, tmp, ins, dreg_mask, ins->sreg2, NULL, fp);
1408 DEBUG (g_print ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (ins->sreg2, fp), mono_regname_full (reg2, fp)));
1409 sreg2_copy = create_copy_ins (cfg, reg2, ins->sreg2, NULL, ip, fp);
1410 prev_sreg2 = ins->sreg2 = reg2;
1413 mono_regstate_free_float (rs, reg2);
1415 mono_regstate_free_int (rs, reg2);
1418 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1])) {
1419 /* Copying sreg1_high to dreg could also clobber sreg2 */
1420 if (rs->iassign [prev_sreg1 + 1] == ins->sreg2)
1422 g_assert_not_reached ();
1425 * sreg1 and dest are already allocated to the same regpair by the
1426 * SREG1 allocation code.
1428 g_assert (ins->sreg1 == ins->dreg);
1429 g_assert (dreg_high == sreg1_high);
1432 DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (ins->sreg1, fp), mono_regname_full (ins->dreg, fp)));
1433 copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL, ip, fp);
1434 insert_before_ins (ins, tmp, copy);
1437 insert_before_ins (copy, tmp, sreg2_copy);
1440 * Need to prevent sreg2 to be allocated to sreg1, since that
1441 * would screw up the previous copy.
1443 sreg2_mask &= ~ (regmask (ins->sreg1));
1444 /* we set sreg1 to dest as well */
1445 prev_sreg1 = ins->sreg1 = ins->dreg;
1446 sreg2_mask &= ~ (regmask (ins->dreg));
1452 fp = sreg2_is_fp (ins);
1453 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2]))
1454 g_assert_not_reached ();
1455 if ((!fp || (fp && !use_fpstack)) && (is_soft_reg (ins->sreg2, fp))) {
1456 val = rassign (cfg, ins->sreg2, fp);
1461 /* the register gets spilled after this inst */
1464 val = alloc_reg (cfg, tmp, ins, sreg2_mask, ins->sreg2, ®info [ins->sreg2], fp);
1465 assign_reg (cfg, rs, ins->sreg2, val, fp);
1466 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_regname_full (val, fp), ins->sreg2));
1468 create_spilled_store (cfg, spill, val, prev_sreg2, ins, fp);
1476 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1477 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1478 mono_regstate_free_int (rs, ins->sreg1);
1480 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1481 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1482 mono_regstate_free_int (rs, ins->sreg2);
1485 DEBUG (print_ins (i, ins));
1486 /* this may result from a insert_before call */
1488 bb->code = tmp->data;
1494 g_list_free (fspill_list);