mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 105 static const regmask_t regbank_callee_saved_regs [] = {
 106         MONO_ARCH_CALLEE_SAVED_REGS,
 107         MONO_ARCH_CALLEE_SAVED_FREGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_REGS,
 110         MONO_ARCH_CALLEE_SAVED_XREGS,
 111 };
 112 #endif
 113
 114 static const regmask_t regbank_callee_regs [] = {
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_FREGS,
 117         MONO_ARCH_CALLEE_REGS,
 118         MONO_ARCH_CALLEE_REGS,
 119         MONO_ARCH_CALLEE_XREGS,
 120 };
 121
 122 static const int regbank_spill_var_size[] = {
 123         sizeof (mgreg_t),
 124         sizeof (double),
 125         sizeof (mgreg_t),
 126         sizeof (mgreg_t),
 127         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 128 };
 129
 130 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 131
 132 static inline void
 133 mono_regstate_assign (MonoRegState *rs)
 134 {
 135 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 136         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 137          * if the values here are not the same.
 138          */
 139         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 140         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 141         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 142 #endif
 143
 144         if (rs->next_vreg > rs->vassign_size) {
 145                 g_free (rs->vassign);
 146                 rs->vassign_size = MAX (rs->next_vreg, 256);
 147                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 148         }
 149
 150         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 151         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 152
 153         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 154         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 155
 156 #ifdef MONO_ARCH_NEED_SIMD_BANK
 157         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 158         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 159 #endif
 160 }
 161
 162 static inline int
 163 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 164 {
 165         regmask_t mask = allow & rs->ifree_mask;
 166
 167 #if defined(__x86_64__) && defined(__GNUC__)
 168  {
 169         guint64 i;
 170
 171         if (mask == 0)
 172                 return -1;
 173
 174         __asm__("bsfq %1,%0\n\t"
 175                         : "=r" (i) : "rm" (mask));
 176
 177         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 178         return i;
 179  }
 180 #else
 181         int i;
 182
 183         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 184                 if (mask & ((regmask_t)1 << i)) {
 185                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 186                         return i;
 187                 }
 188         }
 189         return -1;
 190 #endif
 191 }
 192
 193 static inline void
 194 mono_regstate_free_int (MonoRegState *rs, int reg)
 195 {
 196         if (reg >= 0) {
 197                 rs->ifree_mask |= (regmask_t)1 << reg;
 198                 rs->isymbolic [reg] = 0;
 199         }
 200 }
 201
 202 static inline int
 203 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 204 {
 205         int i;
 206         int mirrored_bank;
 207         regmask_t mask = allow & rs->free_mask [bank];
 208         for (i = 0; i < regbank_size [bank]; ++i) {
 209                 if (mask & ((regmask_t)1 << i)) {
 210                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 211
 212                         mirrored_bank = get_mirrored_bank (bank);
 213                         if (mirrored_bank == -1)
 214                                 return i;
 215
 216                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 217                         return i;
 218                 }
 219         }
 220         return -1;
 221 }
 222
 223 static inline void
 224 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 225 {
 226         int mirrored_bank;
 227
 228         if (reg >= 0) {
 229                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 230                 rs->symbolic [bank][reg] = 0;
 231
 232                 mirrored_bank = get_mirrored_bank (bank);
 233                 if (mirrored_bank == -1)
 234                         return;
 235                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 236                 rs->symbolic [mirrored_bank][reg] = 0;
 237         }
 238 }
 239
 240 const char*
 241 mono_regname_full (int reg, int bank)
 242 {
 243         if (G_UNLIKELY (bank)) {
 244 #if MONO_ARCH_NEED_SIMD_BANK
 245                 if (bank == MONO_REG_SIMD)
 246                         return mono_arch_xregname (reg);
 247 #endif
 248                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 249                         return mono_arch_regname (reg);
 250                 g_assert (bank == MONO_REG_DOUBLE);
 251                 return mono_arch_fregname (reg);
 252         } else {
 253                 return mono_arch_regname (reg);
 254         }
 255 }
 256
 257 void
 258 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 259 {
 260         guint32 regpair;
 261
 262         regpair = (((guint32)hreg) << 24) + vreg;
 263         if (G_UNLIKELY (bank)) {
 264                 g_assert (vreg >= regbank_size [bank]);
 265                 g_assert (hreg < regbank_size [bank]);
 266                 call->used_fregs |= 1 << hreg;
 267                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 268         } else {
 269                 g_assert (vreg >= MONO_MAX_IREGS);
 270                 g_assert (hreg < MONO_MAX_IREGS);
 271                 call->used_iregs |= 1 << hreg;
 272                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 273         }
 274 }
 275
 276 /*
 277  * mono_call_inst_add_outarg_vt:
 278  *
 279  *   Register OUTARG_VT as belonging to CALL.
 280  */
 281 void
 282 mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
 283 {
 284         call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
 285 }
 286
 287 static void
 288 resize_spill_info (MonoCompile *cfg, int bank)
 289 {
 290         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 291         int orig_len = cfg->spill_info_len [bank];
 292         int new_len = orig_len ? orig_len * 2 : 16;
 293         MonoSpillInfo *new_info;
 294         int i;
 295
 296         g_assert (bank < MONO_NUM_REGBANKS);
 297
 298         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 299         if (orig_info)
 300                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 301         for (i = orig_len; i < new_len; ++i)
 302                 new_info [i].offset = -1;
 303
 304         cfg->spill_info [bank] = new_info;
 305         cfg->spill_info_len [bank] = new_len;
 306 }
 307
 308 /*
 309  * returns the offset used by spillvar. It allocates a new
 310  * spill variable if necessary.
 311  */
 312 static inline int
 313 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 314 {
 315         MonoSpillInfo *info;
 316         int size;
 317
 318         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 319                 while (spillvar >= cfg->spill_info_len [bank])
 320                         resize_spill_info (cfg, bank);
 321         }
 322
 323         /*
 324          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 325          */
 326         info = &cfg->spill_info [bank][spillvar];
 327         if (info->offset == -1) {
 328                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 329                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 330
 331                 g_assert (bank < MONO_NUM_REGBANKS);
 332                 if (G_UNLIKELY (bank))
 333                         size = regbank_spill_var_size [bank];
 334                 else
 335                         size = sizeof (mgreg_t);
 336
 337                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 338                         cfg->stack_offset += size - 1;
 339                         cfg->stack_offset &= ~(size - 1);
 340                         info->offset = cfg->stack_offset;
 341                         cfg->stack_offset += size;
 342                 } else {
 343                         cfg->stack_offset += size - 1;
 344                         cfg->stack_offset &= ~(size - 1);
 345                         cfg->stack_offset += size;
 346                         info->offset = - cfg->stack_offset;
 347                 }
 348         }
 349
 350         return info->offset;
 351 }
 352
 353 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 354 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 355 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 356 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 357 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 358 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 359
 360 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 361 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 362 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 363 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 364 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 365
 366 #ifndef MONO_ARCH_INST_IS_FLOAT
 367 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 368 #endif
 369
 370 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 371 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 372 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 373 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 374 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 375
 376 #define reg_is_simd(desc) ((desc) == 'x')
 377
 378 #ifdef MONO_ARCH_NEED_SIMD_BANK
 379
 380 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 381
 382 #else
 383
 384 #define reg_bank(desc) reg_is_fp ((desc))
 385
 386 #endif
 387
 388 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 389 #define sreg1_bank(spec) sreg_bank (0, (spec))
 390 #define sreg2_bank(spec) sreg_bank (1, (spec))
 391 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 392
 393 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 394 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 395 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 396 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 397
 398 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 399
 400 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 401 #undef is_global_ireg
 402 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 403 #endif
 404
 405 typedef struct {
 406         int born_in;
 407         int killed_in;
 408         /* Not (yet) used */
 409         //int last_use;
 410         //int prev_use;
 411         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 412 } RegTrack;
 413
 414 #if !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT)
 415
 416 static const char* const patch_info_str[] = {
 417 #define PATCH_INFO(a,b) "" #a,
 418 #include "patch-info.h"
 419 #undef PATCH_INFO
 420 };
 421
 422 void
 423 mono_print_ji (const MonoJumpInfo *ji)
 424 {
 425         switch (ji->type) {
 426         case MONO_PATCH_INFO_RGCTX_FETCH: {
 427                 MonoJumpInfoRgctxEntry *entry = ji->data.rgctx_entry;
 428
 429                 printf ("[RGCTX_FETCH ");
 430                 mono_print_ji (entry->data);
 431                 printf (" - %s]", mono_rgctx_info_type_to_str (entry->info_type));
 432                 break;
 433         }
 434         case MONO_PATCH_INFO_METHODCONST: {
 435                 char *s = mono_method_full_name (ji->data.method, TRUE);
 436                 printf ("[METHODCONST - %s]", s);
 437                 g_free (s);
 438                 break;
 439         }
 440         default:
 441                 printf ("[%s]", patch_info_str [ji->type]);
 442                 break;
 443         }
 444 }
 445
 446 void
 447 mono_print_ins_index (int i, MonoInst *ins)
 448 {
 449         const char *spec = ins_get_spec (ins->opcode);
 450         int num_sregs, j;
 451         int sregs [MONO_MAX_SRC_REGS];
 452
 453         if (i != -1)
 454                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 455         else
 456                 printf (" %s", mono_inst_name (ins->opcode));
 457         if (spec == MONO_ARCH_CPU_SPEC) {
 458                 gboolean dest_base = FALSE;
 459                 switch (ins->opcode) {
 460                 case OP_STOREV_MEMBASE:
 461                         dest_base = TRUE;
 462                         break;
 463                 default:
 464                         break;
 465                 }
 466
 467                 /* This is a lowered opcode */
 468                 if (ins->dreg != -1) {
 469                         if (dest_base)
 470                                 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 471                         else
 472                                 printf (" R%d <-", ins->dreg);
 473                 }
 474                 if (ins->sreg1 != -1)
 475                         printf (" R%d", ins->sreg1);
 476                 if (ins->sreg2 != -1)
 477                         printf (" R%d", ins->sreg2);
 478                 if (ins->sreg3 != -1)
 479                         printf (" R%d", ins->sreg3);
 480
 481                 switch (ins->opcode) {
 482                 case OP_LBNE_UN:
 483                 case OP_LBEQ:
 484                 case OP_LBLT:
 485                 case OP_LBLT_UN:
 486                 case OP_LBGT:
 487                 case OP_LBGT_UN:
 488                 case OP_LBGE:
 489                 case OP_LBGE_UN:
 490                 case OP_LBLE:
 491                 case OP_LBLE_UN:
 492                         if (!ins->inst_false_bb)
 493                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 494                         else
 495                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 496                         break;
 497                 case OP_PHI:
 498                 case OP_VPHI:
 499                 case OP_XPHI:
 500                 case OP_FPHI: {
 501                         int i;
 502                         printf (" [%d (", (int)ins->inst_c0);
 503                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 504                                 if (i)
 505                                         printf (", ");
 506                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 507                         }
 508                         printf (")]");
 509                         break;
 510                 }
 511                 case OP_LDADDR:
 512                 case OP_OUTARG_VTRETADDR:
 513                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 514                         break;
 515                 case OP_REGOFFSET:
 516                 case OP_GSHAREDVT_ARG_REGOFFSET:
 517                         printf (" + 0x%lx", (long)ins->inst_offset);
 518                         break;
 519                 default:
 520                         break;
 521                 }
 522
 523                 printf ("\n");
 524                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 525                 return;
 526         }
 527
 528         if (spec [MONO_INST_DEST]) {
 529                 int bank = dreg_bank (spec);
 530                 if (is_soft_reg (ins->dreg, bank)) {
 531                         if (spec [MONO_INST_DEST] == 'b') {
 532                                 if (ins->inst_offset == 0)
 533                                         printf (" [R%d] <-", ins->dreg);
 534                                 else
 535                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 536                         }
 537                         else
 538                                 printf (" R%d <-", ins->dreg);
 539                 } else if (spec [MONO_INST_DEST] == 'b') {
 540                         if (ins->inst_offset == 0)
 541                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 542                         else
 543                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 544                 } else
 545                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 546         }
 547         if (spec [MONO_INST_SRC1]) {
 548                 int bank = sreg1_bank (spec);
 549                 if (is_soft_reg (ins->sreg1, bank)) {
 550                         if (spec [MONO_INST_SRC1] == 'b')
 551                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 552                         else
 553                                 printf (" R%d", ins->sreg1);
 554                 } else if (spec [MONO_INST_SRC1] == 'b')
 555                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 556                 else
 557                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 558         }
 559         num_sregs = mono_inst_get_src_registers (ins, sregs);
 560         for (j = 1; j < num_sregs; ++j) {
 561                 int bank = sreg_bank (j, spec);
 562                 if (is_soft_reg (sregs [j], bank))
 563                         printf (" R%d", sregs [j]);
 564                 else
 565                         printf (" %s", mono_regname_full (sregs [j], bank));
 566         }
 567
 568         switch (ins->opcode) {
 569         case OP_ICONST:
 570                 printf (" [%d]", (int)ins->inst_c0);
 571                 break;
 572 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 573         case OP_X86_PUSH_IMM:
 574 #endif
 575         case OP_ICOMPARE_IMM:
 576         case OP_COMPARE_IMM:
 577         case OP_IADD_IMM:
 578         case OP_ISUB_IMM:
 579         case OP_IAND_IMM:
 580         case OP_IOR_IMM:
 581         case OP_IXOR_IMM:
 582         case OP_SUB_IMM:
 583         case OP_STORE_MEMBASE_IMM:
 584                 printf (" [%d]", (int)ins->inst_imm);
 585                 break;
 586         case OP_ADD_IMM:
 587         case OP_LADD_IMM:
 588                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 589                 break;
 590         case OP_I8CONST:
 591                 printf (" [%lld]", (long long)ins->inst_l);
 592                 break;
 593         case OP_R8CONST:
 594                 printf (" [%f]", *(double*)ins->inst_p0);
 595                 break;
 596         case OP_R4CONST:
 597                 printf (" [%f]", *(float*)ins->inst_p0);
 598                 break;
 599         case OP_CALL:
 600         case OP_CALL_MEMBASE:
 601         case OP_CALL_REG:
 602         case OP_FCALL:
 603         case OP_LCALL:
 604         case OP_VCALL:
 605         case OP_VCALL_REG:
 606         case OP_VCALL_MEMBASE:
 607         case OP_VCALL2:
 608         case OP_VCALL2_REG:
 609         case OP_VCALL2_MEMBASE:
 610         case OP_VOIDCALL:
 611         case OP_VOIDCALL_MEMBASE:
 612         case OP_TAILCALL: {
 613                 MonoCallInst *call = (MonoCallInst*)ins;
 614                 GSList *list;
 615
 616                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 617                         /*
 618                          * These are lowered opcodes, but they are in the .md files since the old
 619                          * JIT passes them to backends.
 620                          */
 621                         if (ins->dreg != -1)
 622                                 printf (" R%d <-", ins->dreg);
 623                 }
 624
 625                 if (call->method) {
 626                         char *full_name = mono_method_full_name (call->method, TRUE);
 627                         printf (" [%s]", full_name);
 628                         g_free (full_name);
 629                 } else if (call->fptr_is_patch) {
 630                         MonoJumpInfo *ji = (MonoJumpInfo*)call->fptr;
 631
 632                         printf (" ");
 633                         mono_print_ji (ji);
 634                 } else if (call->fptr) {
 635                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 636                         if (info)
 637                                 printf (" [%s]", info->name);
 638                 }
 639
 640                 list = call->out_ireg_args;
 641                 while (list) {
 642                         guint32 regpair;
 643                         int reg, hreg;
 644
 645                         regpair = (guint32)(gssize)(list->data);
 646                         hreg = regpair >> 24;
 647                         reg = regpair & 0xffffff;
 648
 649                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 650
 651                         list = g_slist_next (list);
 652                 }
 653                 break;
 654         }
 655         case OP_BR:
 656         case OP_CALL_HANDLER:
 657                 printf (" [B%d]", ins->inst_target_bb->block_num);
 658                 break;
 659         case OP_IBNE_UN:
 660         case OP_IBEQ:
 661         case OP_IBLT:
 662         case OP_IBLT_UN:
 663         case OP_IBGT:
 664         case OP_IBGT_UN:
 665         case OP_IBGE:
 666         case OP_IBGE_UN:
 667         case OP_IBLE:
 668         case OP_IBLE_UN:
 669         case OP_LBNE_UN:
 670         case OP_LBEQ:
 671         case OP_LBLT:
 672         case OP_LBLT_UN:
 673         case OP_LBGT:
 674         case OP_LBGT_UN:
 675         case OP_LBGE:
 676         case OP_LBGE_UN:
 677         case OP_LBLE:
 678         case OP_LBLE_UN:
 679                 if (!ins->inst_false_bb)
 680                         printf (" [B%d]", ins->inst_true_bb->block_num);
 681                 else
 682                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 683                 break;
 684         case OP_LIVERANGE_START:
 685         case OP_LIVERANGE_END:
 686         case OP_GC_LIVENESS_DEF:
 687         case OP_GC_LIVENESS_USE:
 688                 printf (" R%d", (int)ins->inst_c1);
 689                 break;
 690         case OP_IL_SEQ_POINT:
 691         case OP_SEQ_POINT:
 692                 printf (" il: %x", (int)ins->inst_imm);
 693                 break;
 694         default:
 695                 break;
 696         }
 697
 698         if (spec [MONO_INST_CLOB])
 699                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 700         printf ("\n");
 701 }
 702
 703 static void
 704 print_regtrack (RegTrack *t, int num)
 705 {
 706         int i;
 707         char buf [32];
 708         const char *r;
 709
 710         for (i = 0; i < num; ++i) {
 711                 if (!t [i].born_in)
 712                         continue;
 713                 if (i >= MONO_MAX_IREGS) {
 714                         g_snprintf (buf, sizeof(buf), "R%d", i);
 715                         r = buf;
 716                 } else
 717                         r = mono_arch_regname (i);
 718                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 719         }
 720 }
 721 #else
 722
 723 void
 724 mono_print_ji (const MonoJumpInfo *ji)
 725 {
 726 }
 727
 728 void
 729 mono_print_ins_index (int i, MonoInst *ins)
 730 {
 731 }
 732 #endif /* !defined(DISABLE_LOGGING) && !defined(DISABLE_JIT) */
 733
 734 void
 735 mono_print_ins (MonoInst *ins)
 736 {
 737         mono_print_ins_index (-1, ins);
 738 }
 739
 740 static inline void
 741 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 742 {
 743         /*
 744          * If this function is called multiple times, the new instructions are inserted
 745          * in the proper order.
 746          */
 747         mono_bblock_insert_before_ins (bb, ins, to_insert);
 748 }
 749
 750 static inline void
 751 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 752 {
 753         /*
 754          * If this function is called multiple times, the new instructions are inserted in
 755          * proper order.
 756          */
 757         mono_bblock_insert_after_ins (bb, *last, to_insert);
 758
 759         *last = to_insert;
 760 }
 761
 762 static inline int
 763 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 764 {
 765         if (vreg_is_ref (cfg, reg))
 766                 return MONO_REG_INT_REF;
 767         else if (vreg_is_mp (cfg, reg))
 768                 return MONO_REG_INT_MP;
 769         else
 770                 return bank;
 771 }
 772
 773 /*
 774  * Force the spilling of the variable in the symbolic register 'reg', and free
 775  * the hreg it was assigned to.
 776  */
 777 static void
 778 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 779 {
 780         MonoInst *load;
 781         int i, sel, spill;
 782         MonoRegState *rs = cfg->rs;
 783
 784         sel = rs->vassign [reg];
 785
 786         /* the vreg we need to spill lives in another logical reg bank */
 787         bank = translate_bank (cfg->rs, bank, sel);
 788
 789         /*i = rs->isymbolic [sel];
 790         g_assert (i == reg);*/
 791         i = reg;
 792         spill = ++cfg->spill_count;
 793         rs->vassign [i] = -spill - 1;
 794         if (G_UNLIKELY (bank))
 795                 mono_regstate_free_general (rs, sel, bank);
 796         else
 797                 mono_regstate_free_int (rs, sel);
 798         /* we need to create a spill var and insert a load to sel after the current instruction */
 799         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 800         load->dreg = sel;
 801         load->inst_basereg = cfg->frame_reg;
 802         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 803         insert_after_ins (bb, ins, last, load);
 804         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 805         if (G_UNLIKELY (bank))
 806                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 807         else
 808                 i = mono_regstate_alloc_int (rs, regmask (sel));
 809         g_assert (i == sel);
 810
 811         if (G_UNLIKELY (bank))
 812                 mono_regstate_free_general (rs, sel, bank);
 813         else
 814                 mono_regstate_free_int (rs, sel);
 815 }
 816
 817 /* This isn't defined on older glib versions and on some platforms */
 818 #ifndef G_GUINT64_FORMAT
 819 #define G_GUINT64_FORMAT "ul"
 820 #endif
 821
 822 static int
 823 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 824 {
 825         MonoInst *load;
 826         int i, sel, spill, num_sregs;
 827         int sregs [MONO_MAX_SRC_REGS];
 828         MonoRegState *rs = cfg->rs;
 829
 830         g_assert (bank < MONO_NUM_REGBANKS);
 831
 832         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08llu (R%d <- R%d R%d R%d)\n", reg, (unsigned long long)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 833         /* exclude the registers in the current instruction */
 834         num_sregs = mono_inst_get_src_registers (ins, sregs);
 835         for (i = 0; i < num_sregs; ++i) {
 836                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 837                         if (is_soft_reg (sregs [i], bank))
 838                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 839                         else
 840                                 regmask &= ~ (regmask (sregs [i]));
 841                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 842                 }
 843         }
 844         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 845                 regmask &= ~ (regmask (ins->dreg));
 846                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 847         }
 848
 849         DEBUG (printf ("\t\tavailable regmask: 0x%08llu\n", (unsigned long long)regmask));
 850         g_assert (regmask); /* need at least a register we can free */
 851         sel = 0;
 852         /* we should track prev_use and spill the register that's farther */
 853         if (G_UNLIKELY (bank)) {
 854                 for (i = 0; i < regbank_size [bank]; ++i) {
 855                         if (regmask & (regmask (i))) {
 856                                 sel = i;
 857
 858                                 /* the vreg we need to load lives in another logical bank */
 859                                 bank = translate_bank (cfg->rs, bank, sel);
 860
 861                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 862                                 break;
 863                         }
 864                 }
 865
 866                 i = rs->symbolic [bank] [sel];
 867                 spill = ++cfg->spill_count;
 868                 rs->vassign [i] = -spill - 1;
 869                 mono_regstate_free_general (rs, sel, bank);
 870         }
 871         else {
 872                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 873                         if (regmask & (regmask (i))) {
 874                                 sel = i;
 875                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 876                                 break;
 877                         }
 878                 }
 879
 880                 i = rs->isymbolic [sel];
 881                 spill = ++cfg->spill_count;
 882                 rs->vassign [i] = -spill - 1;
 883                 mono_regstate_free_int (rs, sel);
 884         }
 885
 886         /* we need to create a spill var and insert a load to sel after the current instruction */
 887         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 888         load->dreg = sel;
 889         load->inst_basereg = cfg->frame_reg;
 890         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 891         insert_after_ins (bb, ins, last, load);
 892         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 893         if (G_UNLIKELY (bank))
 894                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 895         else
 896                 i = mono_regstate_alloc_int (rs, regmask (sel));
 897         g_assert (i == sel);
 898
 899         return sel;
 900 }
 901
 902 /*
 903  * free_up_hreg:
 904  *
 905  *   Free up the hreg HREG by spilling the vreg allocated to it.
 906  */
 907 static void
 908 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 909 {
 910         if (G_UNLIKELY (bank)) {
 911                 if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
 912                         bank = translate_bank (cfg->rs, bank, hreg);
 913                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 914                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 915                 }
 916         }
 917         else {
 918                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 919                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 920                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 921                 }
 922         }
 923 }
 924
 925 static MonoInst*
 926 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 927 {
 928         MonoInst *copy;
 929
 930         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 931
 932         copy->dreg = dest;
 933         copy->sreg1 = src;
 934         copy->cil_code = ip;
 935         if (ins) {
 936                 mono_bblock_insert_after_ins (bb, ins, copy);
 937                 *last = copy;
 938         }
 939         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 940         return copy;
 941 }
 942
 943 static inline const char*
 944 regbank_to_string (int bank)
 945 {
 946         if (bank == MONO_REG_INT_REF)
 947                 return "REF ";
 948         else if (bank == MONO_REG_INT_MP)
 949                 return "MP ";
 950         else
 951                 return "";
 952 }
 953
 954 static void
 955 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 956 {
 957         MonoInst *store, *def;
 958
 959         bank = get_vreg_bank (cfg, prev_reg, bank);
 960
 961         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 962         store->sreg1 = reg;
 963         store->inst_destbasereg = cfg->frame_reg;
 964         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 965         if (ins) {
 966                 mono_bblock_insert_after_ins (bb, ins, store);
 967                 *last = store;
 968         } else if (insert_before) {
 969                 insert_before_ins (bb, insert_before, store);
 970         } else {
 971                 g_assert_not_reached ();
 972         }
 973         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 974
 975         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 976                 g_assert (prev_reg != -1);
 977                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 978                 def->inst_c0 = spill;
 979                 def->inst_c1 = bank;
 980                 mono_bblock_insert_after_ins (bb, store, def);
 981         }
 982 }
 983
 984 /* flags used in reginfo->flags */
 985 enum {
 986         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 987         MONO_FP_NEEDS_SPILL                     = regmask (1),
 988         MONO_FP_NEEDS_LOAD                      = regmask (2)
 989 };
 990
 991 static inline int
 992 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 993 {
 994         int val;
 995
 996         if (info && info->preferred_mask) {
 997                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 998                 if (val >= 0) {
 999                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
1000                         return val;
1001                 }
1002         }
1003
1004         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1005         if (val < 0)
1006                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
1007
1008         return val;
1009 }
1010
1011 static inline int
1012 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
1013 {
1014         int val;
1015
1016         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
1017
1018         if (val < 0)
1019                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1020
1021         return val;
1022 }
1023
1024 static inline int
1025 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
1026 {
1027         if (G_UNLIKELY (bank))
1028                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
1029         else
1030                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
1031 }
1032
1033 static inline void
1034 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
1035 {
1036         if (G_UNLIKELY (bank)) {
1037                 int mirrored_bank;
1038
1039                 g_assert (reg >= regbank_size [bank]);
1040                 g_assert (hreg < regbank_size [bank]);
1041                 g_assert (! is_global_freg (hreg));
1042
1043                 rs->vassign [reg] = hreg;
1044                 rs->symbolic [bank] [hreg] = reg;
1045                 rs->free_mask [bank] &= ~ (regmask (hreg));
1046
1047                 mirrored_bank = get_mirrored_bank (bank);
1048                 if (mirrored_bank == -1)
1049                         return;
1050
1051                 /* Make sure the other logical reg bank that this bank shares
1052                  * a single hard reg bank knows that this hard reg is not free.
1053                  */
1054                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
1055
1056                 /* Mark the other logical bank that the this bank shares
1057                  * a single hard reg bank with as mirrored.
1058                  */
1059                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
1060
1061         }
1062         else {
1063                 g_assert (reg >= MONO_MAX_IREGS);
1064                 g_assert (hreg < MONO_MAX_IREGS);
1065 #if !defined(TARGET_ARM) && !defined(TARGET_ARM64)
1066                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1067                 /* On arm64, rgctx_reg is a global hreg, and it is used to pass an argument */
1068                 g_assert (! is_global_ireg (hreg));
1069 #endif
1070
1071                 rs->vassign [reg] = hreg;
1072                 rs->isymbolic [hreg] = reg;
1073                 rs->ifree_mask &= ~ (regmask (hreg));
1074         }
1075 }
1076
1077 static inline regmask_t
1078 get_callee_mask (const char spec)
1079 {
1080         if (G_UNLIKELY (reg_bank (spec)))
1081                 return regbank_callee_regs [reg_bank (spec)];
1082         return MONO_ARCH_CALLEE_REGS;
1083 }
1084
1085 static gint8 desc_to_fixed_reg [256];
1086 static gboolean desc_to_fixed_reg_inited = FALSE;
1087
1088 #ifndef DISABLE_JIT
1089
1090 /*
1091  * Local register allocation.
1092  * We first scan the list of instructions and we save the liveness info of
1093  * each register (when the register is first used, when it's value is set etc.).
1094  * We also reverse the list of instructions because assigning registers backwards allows
1095  * for more tricks to be used.
1096  */
1097 void
1098 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1099 {
1100         MonoInst *ins, *prev, *last;
1101         MonoInst **tmp;
1102         MonoRegState *rs = cfg->rs;
1103         int i, j, val, max;
1104         RegTrack *reginfo;
1105         const char *spec;
1106         unsigned char spec_src1, spec_dest;
1107         int bank = 0;
1108 #if MONO_ARCH_USE_FPSTACK
1109         gboolean has_fp = FALSE;
1110         int fpstack [8];
1111         int sp = 0;
1112 #endif
1113         int num_sregs = 0;
1114         int sregs [MONO_MAX_SRC_REGS];
1115
1116         if (!bb->code)
1117                 return;
1118
1119         if (!desc_to_fixed_reg_inited) {
1120                 for (i = 0; i < 256; ++i)
1121                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1122                 desc_to_fixed_reg_inited = TRUE;
1123
1124                 /* Validate the cpu description against the info in mini-ops.h */
1125 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM) || defined(TARGET_ARM64)
1126                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1127                         const char *ispec;
1128
1129                         spec = ins_get_spec (i);
1130                         ispec = INS_INFO (i);
1131
1132                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1133                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1134                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1135                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1136                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1137                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1138                 }
1139 #endif
1140         }
1141
1142         rs->next_vreg = bb->max_vreg;
1143         mono_regstate_assign (rs);
1144
1145         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1146         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1147                 rs->free_mask [i] = regbank_callee_regs [i];
1148
1149         max = rs->next_vreg;
1150
1151         if (cfg->reginfo && cfg->reginfo_len < max)
1152                 cfg->reginfo = NULL;
1153
1154         reginfo = cfg->reginfo;
1155         if (!reginfo) {
1156                 cfg->reginfo_len = MAX (1024, max * 2);
1157                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1158         }
1159         else
1160                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1161
1162         if (cfg->verbose_level > 1) {
1163                 /* print_regtrack reads the info of all variables */
1164                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1165         }
1166
1167         /*
1168          * For large methods, next_vreg can be very large, so g_malloc0 time can
1169          * be prohibitive. So we manually init the reginfo entries used by the
1170          * bblock.
1171          */
1172         for (ins = bb->code; ins; ins = ins->next) {
1173                 gboolean modify = FALSE;
1174
1175                 spec = ins_get_spec (ins->opcode);
1176
1177                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1178                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1179 #if SIZEOF_REGISTER == 4
1180                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1181                                 /**
1182                                  * In the new IR, the two vregs of the regpair do not alias the
1183                                  * original long vreg. shift the vreg here so the rest of the
1184                                  * allocator doesn't have to care about it.
1185                                  */
1186                                 ins->dreg ++;
1187                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1188                         }
1189 #endif
1190                 }
1191
1192                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1193                 for (j = 0; j < num_sregs; ++j) {
1194                         g_assert (sregs [j] != -1);
1195                         if (sregs [j] < max) {
1196                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1197 #if SIZEOF_REGISTER == 4
1198                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1199                                         sregs [j]++;
1200                                         modify = TRUE;
1201                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1202                                 }
1203 #endif
1204                         }
1205                 }
1206                 if (modify)
1207                         mono_inst_set_src_registers (ins, sregs);
1208         }
1209
1210         /*if (cfg->opt & MONO_OPT_COPYPROP)
1211                 local_copy_prop (cfg, ins);*/
1212
1213         i = 1;
1214         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1215         /* forward pass on the instructions to collect register liveness info */
1216         MONO_BB_FOR_EACH_INS (bb, ins) {
1217                 spec = ins_get_spec (ins->opcode);
1218                 spec_dest = spec [MONO_INST_DEST];
1219
1220                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1221                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1222                 }
1223
1224                 DEBUG (mono_print_ins_index (i, ins));
1225
1226                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1227
1228 #if MONO_ARCH_USE_FPSTACK
1229                 if (dreg_is_fp (spec)) {
1230                         has_fp = TRUE;
1231                 } else {
1232                         for (j = 0; j < num_sregs; ++j) {
1233                                 if (sreg_is_fp (j, spec))
1234                                         has_fp = TRUE;
1235                         }
1236                 }
1237 #endif
1238
1239                 for (j = 0; j < num_sregs; ++j) {
1240                         int sreg = sregs [j];
1241                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1242                         if (sreg_spec) {
1243                                 bank = sreg_bank (j, spec);
1244                                 g_assert (sreg != -1);
1245                                 if (is_soft_reg (sreg, bank))
1246                                         /* This means the vreg is not local to this bb */
1247                                         g_assert (reginfo [sreg].born_in > 0);
1248                                 rs->vassign [sreg] = -1;
1249                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1250                                 //reginfo [ins->sreg2].last_use = i;
1251                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1252                                         /* The virtual register is allocated sequentially */
1253                                         rs->vassign [sreg + 1] = -1;
1254                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1255                                         //reginfo [ins->sreg2 + 1].last_use = i;
1256                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1257                                                 reginfo [sreg + 1].born_in = i;
1258                                 }
1259                         } else {
1260                                 sregs [j] = -1;
1261                         }
1262                 }
1263                 mono_inst_set_src_registers (ins, sregs);
1264
1265                 if (spec_dest) {
1266                         int dest_dreg;
1267
1268                         bank = dreg_bank (spec);
1269                         if (spec_dest != 'b') /* it's not just a base register */
1270                                 reginfo [ins->dreg].killed_in = i;
1271                         g_assert (ins->dreg != -1);
1272                         rs->vassign [ins->dreg] = -1;
1273                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1274                         //reginfo [ins->dreg].last_use = i;
1275                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1276                                 reginfo [ins->dreg].born_in = i;
1277
1278                         dest_dreg = desc_to_fixed_reg [spec_dest];
1279                         if (dest_dreg != -1)
1280                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1281
1282 #ifdef MONO_ARCH_INST_FIXED_MASK
1283                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1284 #endif
1285
1286                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1287                                 /* The virtual register is allocated sequentially */
1288                                 rs->vassign [ins->dreg + 1] = -1;
1289                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1290                                 //reginfo [ins->dreg + 1].last_use = i;
1291                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1292                                         reginfo [ins->dreg + 1].born_in = i;
1293                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1294                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1295                         }
1296                 } else {
1297                         ins->dreg = -1;
1298                 }
1299
1300                 ++i;
1301         }
1302
1303         tmp = &last;
1304
1305         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1306         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1307                 int prev_dreg;
1308                 int dest_dreg, clob_reg;
1309                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1310                 int dreg_high, sreg1_high;
1311                 regmask_t dreg_mask, mask;
1312                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1313                 regmask_t dreg_fixed_mask;
1314                 const unsigned char *ip;
1315                 --i;
1316                 spec = ins_get_spec (ins->opcode);
1317                 spec_src1 = spec [MONO_INST_SRC1];
1318                 spec_dest = spec [MONO_INST_DEST];
1319                 prev_dreg = -1;
1320                 clob_reg = -1;
1321                 dest_dreg = -1;
1322                 dreg_high = -1;
1323                 sreg1_high = -1;
1324                 dreg_mask = get_callee_mask (spec_dest);
1325                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1326                         prev_sregs [j] = -1;
1327                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1328                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1329 #ifdef MONO_ARCH_INST_FIXED_MASK
1330                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1331 #else
1332                         sreg_fixed_masks [j] = 0;
1333 #endif
1334                 }
1335
1336                 DEBUG (printf ("processing:"));
1337                 DEBUG (mono_print_ins_index (i, ins));
1338
1339                 ip = ins->cil_code;
1340
1341                 last = ins;
1342
1343                 /*
1344                  * FIXED REGS
1345                  */
1346                 dest_dreg = desc_to_fixed_reg [spec_dest];
1347                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1348                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1349
1350 #ifdef MONO_ARCH_INST_FIXED_MASK
1351                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1352 #else
1353                 dreg_fixed_mask = 0;
1354 #endif
1355
1356                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1357
1358                 /*
1359                  * TRACK FIXED SREG2, 3, ...
1360                  */
1361                 for (j = 1; j < num_sregs; ++j) {
1362                         int sreg = sregs [j];
1363                         int dest_sreg = dest_sregs [j];
1364
1365                         if (dest_sreg == -1)
1366                                 continue;
1367
1368                         if (j == 2) {
1369                                 int k;
1370
1371                                 /*
1372                                  * CAS.
1373                                  * We need to special case this, since on x86, there are only 3
1374                                  * free registers, and the code below assigns one of them to
1375                                  * sreg, so we can run out of registers when trying to assign
1376                                  * dreg. Instead, we just set up the register masks, and let the
1377                                  * normal sreg2 assignment code handle this. It would be nice to
1378                                  * do this for all the fixed reg cases too, but there is too much
1379                                  * risk of breakage.
1380                                  */
1381
1382                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1383                                 sreg_masks [j] = regmask (dest_sreg);
1384                                 for (k = 0; k < num_sregs; ++k) {
1385                                         if (k != j)
1386                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1387                                 }
1388
1389                                 /*
1390                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1391                                  */
1392                                 for (k = 0; k < num_sregs; ++k) {
1393                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1394                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1395                                 }
1396
1397                                 /*
1398                                  * We can also run out of registers while processing sreg2 if sreg3 is
1399                                  * assigned to another hreg, so spill sreg3 now.
1400                                  */
1401                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1402                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1403                                 }
1404                                 continue;
1405                         }
1406
1407                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1408                                 if (is_global_ireg (sreg)) {
1409                                         int k;
1410                                         /* Argument already in hard reg, need to copy */
1411                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1412                                         insert_before_ins (bb, ins, copy);
1413                                         for (k = 0; k < num_sregs; ++k) {
1414                                                 if (k != j)
1415                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1416                                         }
1417                                         /* See below */
1418                                         dreg_mask &= ~ (regmask (dest_sreg));
1419                                 } else {
1420                                         val = rs->vassign [sreg];
1421                                         if (val == -1) {
1422                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1423                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1424                                         } else if (val < -1) {
1425                                                 /* FIXME: */
1426                                                 g_assert_not_reached ();
1427                                         } else {
1428                                                 /* Argument already in hard reg, need to copy */
1429                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1430                                                 int k;
1431
1432                                                 insert_before_ins (bb, ins, copy);
1433                                                 for (k = 0; k < num_sregs; ++k) {
1434                                                         if (k != j)
1435                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1436                                                 }
1437                                                 /*
1438                                                  * Prevent the dreg from being allocated to dest_sreg
1439                                                  * too, since it could force sreg1 to be allocated to
1440                                                  * the same reg on x86.
1441                                                  */
1442                                                 dreg_mask &= ~ (regmask (dest_sreg));
1443                                         }
1444                                 }
1445                         } else {
1446                                 gboolean need_spill = TRUE;
1447                                 gboolean need_assign = TRUE;
1448                                 int k;
1449
1450                                 dreg_mask &= ~ (regmask (dest_sreg));
1451                                 for (k = 0; k < num_sregs; ++k) {
1452                                         if (k != j)
1453                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1454                                 }
1455
1456                                 /*
1457                                  * First check if dreg is assigned to dest_sreg2, since we
1458                                  * can't spill a dreg.
1459                                  */
1460                                 if (spec [MONO_INST_DEST])
1461                                         val = rs->vassign [ins->dreg];
1462                                 else
1463                                         val = -1;
1464                                 if (val == dest_sreg && ins->dreg != sreg) {
1465                                         /*
1466                                          * the destination register is already assigned to
1467                                          * dest_sreg2: we need to allocate another register for it
1468                                          * and then copy from this to dest_sreg2.
1469                                          */
1470                                         int new_dest;
1471                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1472                                         g_assert (new_dest >= 0);
1473                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1474
1475                                         prev_dreg = ins->dreg;
1476                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1477                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1478                                         mono_regstate_free_int (rs, dest_sreg);
1479                                         need_spill = FALSE;
1480                                 }
1481
1482                                 if (is_global_ireg (sreg)) {
1483                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1484                                         insert_before_ins (bb, ins, copy);
1485                                         need_assign = FALSE;
1486                                 }
1487                                 else {
1488                                         val = rs->vassign [sreg];
1489                                         if (val == dest_sreg) {
1490                                                 /* sreg2 is already assigned to the correct register */
1491                                                 need_spill = FALSE;
1492                                         } else if (val < -1) {
1493                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1494                                         } else if (val >= 0) {
1495                                                 /* sreg2 already assigned to another register */
1496                                                 /*
1497                                                  * We couldn't emit a copy from val to dest_sreg2, because
1498                                                  * val might be spilled later while processing this
1499                                                  * instruction. So we spill sreg2 so it can be allocated to
1500                                                  * dest_sreg2.
1501                                                  */
1502                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1503                                         }
1504                                 }
1505
1506                                 if (need_spill) {
1507                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1508                                 }
1509
1510                                 if (need_assign) {
1511                                         if (rs->vassign [sreg] < -1) {
1512                                                 int spill;
1513
1514                                                 /* Need to emit a spill store */
1515                                                 spill = - rs->vassign [sreg] - 1;
1516                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1517                                         }
1518                                         /* force-set sreg2 */
1519                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1520                                 }
1521                         }
1522                         sregs [j] = dest_sreg;
1523                 }
1524                 mono_inst_set_src_registers (ins, sregs);
1525
1526                 /*
1527                  * TRACK DREG
1528                  */
1529                 bank = dreg_bank (spec);
1530                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1531                         prev_dreg = ins->dreg;
1532                 }
1533
1534                 if (spec_dest == 'b') {
1535                         /*
1536                          * The dest reg is read by the instruction, not written, so
1537                          * avoid allocating sreg1/sreg2 to the same reg.
1538                          */
1539                         if (dest_sregs [0] != -1)
1540                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1541                         for (j = 1; j < num_sregs; ++j) {
1542                                 if (dest_sregs [j] != -1)
1543                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1544                         }
1545
1546                         val = rs->vassign [ins->dreg];
1547                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1548                                 /* DREG is already allocated to a register needed for sreg1 */
1549                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1550                         }
1551                 }
1552
1553                 /*
1554                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1555                  * various complex situations.
1556                  */
1557                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1558                         guint32 dreg2, dest_dreg2;
1559
1560                         g_assert (is_soft_reg (ins->dreg, bank));
1561
1562                         if (dest_dreg != -1) {
1563                                 if (rs->vassign [ins->dreg] != dest_dreg)
1564                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1565
1566                                 dreg2 = ins->dreg + 1;
1567                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1568                                 if (dest_dreg2 != -1) {
1569                                         if (rs->vassign [dreg2] != dest_dreg2)
1570                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1571                                 }
1572                         }
1573                 }
1574
1575                 if (dreg_fixed_mask) {
1576                         g_assert (!bank);
1577                         if (is_global_ireg (ins->dreg)) {
1578                                 /*
1579                                  * The argument is already in a hard reg, but that reg is
1580                                  * not usable by this instruction, so allocate a new one.
1581                                  */
1582                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1583                                 if (val < 0)
1584                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1585                                 mono_regstate_free_int (rs, val);
1586                                 dest_dreg = val;
1587
1588                                 /* Fall through */
1589                         }
1590                         else
1591                                 dreg_mask &= dreg_fixed_mask;
1592                 }
1593
1594                 if (is_soft_reg (ins->dreg, bank)) {
1595                         val = rs->vassign [ins->dreg];
1596
1597                         if (val < 0) {
1598                                 int spill = 0;
1599                                 if (val < -1) {
1600                                         /* the register gets spilled after this inst */
1601                                         spill = -val -1;
1602                                 }
1603                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1604                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1605                                 if (spill)
1606                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1607                         }
1608
1609                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1610                         ins->dreg = val;
1611                 }
1612
1613                 /* Handle regpairs */
1614                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1615                         int reg2 = prev_dreg + 1;
1616
1617                         g_assert (!bank);
1618                         g_assert (prev_dreg > -1);
1619                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1620                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1621 #ifdef TARGET_X86
1622                         /* bug #80489 */
1623                         mask &= ~regmask (X86_ECX);
1624 #endif
1625                         val = rs->vassign [reg2];
1626                         if (val < 0) {
1627                                 int spill = 0;
1628                                 if (val < -1) {
1629                                         /* the register gets spilled after this inst */
1630                                         spill = -val -1;
1631                                 }
1632                                 val = mono_regstate_alloc_int (rs, mask);
1633                                 if (val < 0)
1634                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1635                                 if (spill)
1636                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1637                         }
1638                         else {
1639                                 if (! (mask & (regmask (val)))) {
1640                                         val = mono_regstate_alloc_int (rs, mask);
1641                                         if (val < 0)
1642                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1643
1644                                         /* Reallocate hreg to the correct register */
1645                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1646
1647                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1648                                 }
1649                         }
1650
1651                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1652                         assign_reg (cfg, rs, reg2, val, bank);
1653
1654                         dreg_high = val;
1655                         ins->backend.reg3 = val;
1656
1657                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1658                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1659                                 mono_regstate_free_int (rs, val);
1660                         }
1661                 }
1662
1663                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1664                         /*
1665                          * In theory, we could free up the hreg even if the vreg is alive,
1666                          * but branches inside bblocks force us to assign the same hreg
1667                          * to a vreg every time it is encountered.
1668                          */
1669                         int dreg = rs->vassign [prev_dreg];
1670                         g_assert (dreg >= 0);
1671                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1672                         if (G_UNLIKELY (bank))
1673                                 mono_regstate_free_general (rs, dreg, bank);
1674                         else
1675                                 mono_regstate_free_int (rs, dreg);
1676                         rs->vassign [prev_dreg] = -1;
1677                 }
1678
1679                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1680                         /* this instruction only outputs to dest_dreg, need to copy */
1681                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1682                         ins->dreg = dest_dreg;
1683
1684                         if (G_UNLIKELY (bank)) {
1685                                 /* the register we need to free up may be used in another logical regbank
1686                                  * so do a translate just in case.
1687                                  */
1688                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1689                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1690                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1691                         }
1692                         else {
1693                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1694                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1695                         }
1696                 }
1697
1698                 if (spec_dest == 'b') {
1699                         /*
1700                          * The dest reg is read by the instruction, not written, so
1701                          * avoid allocating sreg1/sreg2 to the same reg.
1702                          */
1703                         for (j = 0; j < num_sregs; ++j)
1704                                 if (!sreg_bank (j, spec))
1705                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1706                 }
1707
1708                 /*
1709                  * TRACK CLOBBERING
1710                  */
1711                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1712                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1713                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1714                 }
1715
1716                 if (spec [MONO_INST_CLOB] == 'c') {
1717                         int j, s, dreg, dreg2, cur_bank;
1718                         guint64 clob_mask;
1719
1720                         clob_mask = MONO_ARCH_CALLEE_REGS;
1721
1722                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1723                                 /*
1724                                  * Need to avoid spilling the dreg since the dreg is not really
1725                                  * clobbered by the call.
1726                                  */
1727                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1728                                         dreg = rs->vassign [prev_dreg];
1729                                 else
1730                                         dreg = -1;
1731
1732                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1733                                         dreg2 = rs->vassign [prev_dreg + 1];
1734                                 else
1735                                         dreg2 = -1;
1736
1737                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1738                                         s = regmask (j);
1739                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1740                                                 if ((j != dreg) && (j != dreg2))
1741                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1742                                                 else if (rs->isymbolic [j])
1743                                                         /* The hreg is assigned to the dreg of this instruction */
1744                                                         rs->vassign [rs->isymbolic [j]] = -1;
1745                                                 mono_regstate_free_int (rs, j);
1746                                         }
1747                                 }
1748                         }
1749
1750                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1751                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1752                                         clob_mask = regbank_callee_regs [cur_bank];
1753                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1754                                                 dreg = rs->vassign [prev_dreg];
1755                                         else
1756                                                 dreg = -1;
1757
1758                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1759
1760                                                 /* we are looping though the banks in the outer loop
1761                                                  * so, we don't need to deal with mirrored hregs
1762                                                  * because we will get them in one of the other bank passes.
1763                                                  */
1764                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1765                                                         continue;
1766
1767                                                 s = regmask (j);
1768                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s)) {
1769                                                         if (j != dreg)
1770                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1771                                                         else if (rs->symbolic [cur_bank] [j])
1772                                                                 /* The hreg is assigned to the dreg of this instruction */
1773                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1774                                                         mono_regstate_free_general (rs, j, cur_bank);
1775                                                 }
1776                                         }
1777                                 }
1778                         }
1779                 }
1780
1781                 /*
1782                  * TRACK ARGUMENT REGS
1783                  */
1784                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1785                         MonoCallInst *call = (MonoCallInst*)ins;
1786                         GSList *list;
1787
1788                         /*
1789                          * This needs to be done before assigning sreg1, so sreg1 will
1790                          * not be assigned one of the argument regs.
1791                          */
1792
1793                         /*
1794                          * Assign all registers in call->out_reg_args to the proper
1795                          * argument registers.
1796                          */
1797
1798                         list = call->out_ireg_args;
1799                         if (list) {
1800                                 while (list) {
1801                                         guint32 regpair;
1802                                         int reg, hreg;
1803
1804                                         regpair = (guint32)(gssize)(list->data);
1805                                         hreg = regpair >> 24;
1806                                         reg = regpair & 0xffffff;
1807
1808                                         assign_reg (cfg, rs, reg, hreg, 0);
1809
1810                                         sreg_masks [0] &= ~(regmask (hreg));
1811
1812                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1813
1814                                         list = g_slist_next (list);
1815                                 }
1816                         }
1817
1818                         list = call->out_freg_args;
1819                         if (list) {
1820                                 while (list) {
1821                                         guint32 regpair;
1822                                         int reg, hreg;
1823
1824                                         regpair = (guint32)(gssize)(list->data);
1825                                         hreg = regpair >> 24;
1826                                         reg = regpair & 0xffffff;
1827
1828                                         assign_reg (cfg, rs, reg, hreg, 1);
1829
1830                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1831
1832                                         list = g_slist_next (list);
1833                                 }
1834                         }
1835                 }
1836
1837                 /*
1838                  * TRACK SREG1
1839                  */
1840                 bank = sreg1_bank (spec);
1841                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1842                         int sreg1 = sregs [0];
1843                         int dest_sreg1 = dest_sregs [0];
1844
1845                         g_assert (is_soft_reg (sreg1, bank));
1846
1847                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1848                         if (dest_sreg1 != -1)
1849                                 g_assert (dest_sreg1 == ins->dreg);
1850                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1851                         g_assert (val >= 0);
1852
1853                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1854                                 // FIXME:
1855                                 g_assert_not_reached ();
1856
1857                         assign_reg (cfg, rs, sreg1, val, bank);
1858
1859                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1860
1861                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1862                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1863                         g_assert (val >= 0);
1864
1865                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1866                                 // FIXME:
1867                                 g_assert_not_reached ();
1868
1869                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1870
1871                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1872
1873                         /* Skip rest of this section */
1874                         dest_sregs [0] = -1;
1875                 }
1876
1877                 if (sreg_fixed_masks [0]) {
1878                         g_assert (!bank);
1879                         if (is_global_ireg (sregs [0])) {
1880                                 /*
1881                                  * The argument is already in a hard reg, but that reg is
1882                                  * not usable by this instruction, so allocate a new one.
1883                                  */
1884                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1885                                 if (val < 0)
1886                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1887                                 mono_regstate_free_int (rs, val);
1888                                 dest_sregs [0] = val;
1889
1890                                 /* Fall through to the dest_sreg1 != -1 case */
1891                         }
1892                         else
1893                                 sreg_masks [0] &= sreg_fixed_masks [0];
1894                 }
1895
1896                 if (dest_sregs [0] != -1) {
1897                         sreg_masks [0] = regmask (dest_sregs [0]);
1898
1899                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1900                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1901                         }
1902                         if (is_global_ireg (sregs [0])) {
1903                                 /* The argument is already in a hard reg, need to copy */
1904                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1905                                 insert_before_ins (bb, ins, copy);
1906                                 sregs [0] = dest_sregs [0];
1907                         }
1908                 }
1909
1910                 if (is_soft_reg (sregs [0], bank)) {
1911                         val = rs->vassign [sregs [0]];
1912                         prev_sregs [0] = sregs [0];
1913                         if (val < 0) {
1914                                 int spill = 0;
1915                                 if (val < -1) {
1916                                         /* the register gets spilled after this inst */
1917                                         spill = -val -1;
1918                                 }
1919
1920                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1921                                         /*
1922                                          * Allocate the same hreg to sreg1 as well so the
1923                                          * peephole can get rid of the move.
1924                                          */
1925                                         sreg_masks [0] = regmask (ins->dreg);
1926                                 }
1927
1928                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1929                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1930                                         sreg_masks [0] = regmask (ins->dreg);
1931
1932                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1933                                 assign_reg (cfg, rs, sregs [0], val, bank);
1934                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1935
1936                                 if (spill) {
1937                                         /*
1938                                          * Need to insert before the instruction since it can
1939                                          * overwrite sreg1.
1940                                          */
1941                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1942                                 }
1943                         }
1944                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1945                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1946                                 insert_before_ins (bb, ins, copy);
1947                                 for (j = 1; j < num_sregs; ++j)
1948                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1949                                 val = dest_sregs [0];
1950                         }
1951
1952                         sregs [0] = val;
1953                 }
1954                 else {
1955                         prev_sregs [0] = -1;
1956                 }
1957                 mono_inst_set_src_registers (ins, sregs);
1958
1959                 for (j = 1; j < num_sregs; ++j)
1960                         sreg_masks [j] &= ~(regmask (sregs [0]));
1961
1962                 /* Handle the case when sreg1 is a regpair but dreg is not */
1963                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1964                         int reg2 = prev_sregs [0] + 1;
1965
1966                         g_assert (!bank);
1967                         g_assert (prev_sregs [0] > -1);
1968                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1969                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1970                         val = rs->vassign [reg2];
1971                         if (val < 0) {
1972                                 int spill = 0;
1973                                 if (val < -1) {
1974                                         /* the register gets spilled after this inst */
1975                                         spill = -val -1;
1976                                 }
1977                                 val = mono_regstate_alloc_int (rs, mask);
1978                                 if (val < 0)
1979                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1980                                 if (spill)
1981                                         g_assert_not_reached ();
1982                         }
1983                         else {
1984                                 if (! (mask & (regmask (val)))) {
1985                                         /* The vreg is already allocated to a wrong hreg */
1986                                         /* FIXME: */
1987                                         g_assert_not_reached ();
1988 #if 0
1989                                         val = mono_regstate_alloc_int (rs, mask);
1990                                         if (val < 0)
1991                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1992
1993                                         /* Reallocate hreg to the correct register */
1994                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1995
1996                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1997 #endif
1998                                 }
1999                         }
2000
2001                         sreg1_high = val;
2002                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
2003                         assign_reg (cfg, rs, reg2, val, bank);
2004                 }
2005
2006                 /* Handle dreg==sreg1 */
2007                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
2008                         MonoInst *sreg2_copy = NULL;
2009                         MonoInst *copy;
2010                         int bank = reg_bank (spec_src1);
2011
2012                         if (ins->dreg == sregs [1]) {
2013                                 /*
2014                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2015                                  * register for it.
2016                                  */
2017                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
2018
2019                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
2020                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
2021                                 prev_sregs [1] = sregs [1] = reg2;
2022
2023                                 if (G_UNLIKELY (bank))
2024                                         mono_regstate_free_general (rs, reg2, bank);
2025                                 else
2026                                         mono_regstate_free_int (rs, reg2);
2027                         }
2028
2029                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
2030                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
2031                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
2032                                         /* FIXME: */
2033                                         g_assert_not_reached ();
2034
2035                                 /*
2036                                  * sreg1 and dest are already allocated to the same regpair by the
2037                                  * SREG1 allocation code.
2038                                  */
2039                                 g_assert (sregs [0] == ins->dreg);
2040                                 g_assert (dreg_high == sreg1_high);
2041                         }
2042
2043                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2044                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2045                         insert_before_ins (bb, ins, copy);
2046
2047                         if (sreg2_copy)
2048                                 insert_before_ins (bb, copy, sreg2_copy);
2049
2050                         /*
2051                          * Need to prevent sreg2 to be allocated to sreg1, since that
2052                          * would screw up the previous copy.
2053                          */
2054                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2055                         /* we set sreg1 to dest as well */
2056                         prev_sregs [0] = sregs [0] = ins->dreg;
2057                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2058                 }
2059                 mono_inst_set_src_registers (ins, sregs);
2060
2061                 /*
2062                  * TRACK SREG2, 3, ...
2063                  */
2064                 for (j = 1; j < num_sregs; ++j) {
2065                         int k;
2066
2067                         bank = sreg_bank (j, spec);
2068                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2069                                 g_assert_not_reached ();
2070
2071                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2072                                 /*
2073                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2074                                  * allocating it to the fixed reg.
2075                                  */
2076                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2077                                 insert_before_ins (bb, ins, copy);
2078                                 sregs [j] = dest_sregs [j];
2079                         } else if (is_soft_reg (sregs [j], bank)) {
2080                                 val = rs->vassign [sregs [j]];
2081
2082                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2083                                         /*
2084                                          * The sreg is already allocated to a hreg, but not to the fixed
2085                                          * reg required by the instruction. Spill the sreg, so it can be
2086                                          * allocated to the fixed reg by the code below.
2087                                          */
2088                                         /* Currently, this code should only be hit for CAS */
2089                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2090                                         val = rs->vassign [sregs [j]];
2091                                 }
2092
2093                                 if (val < 0) {
2094                                         int spill = 0;
2095                                         if (val < -1) {
2096                                                 /* the register gets spilled after this inst */
2097                                                 spill = -val -1;
2098                                         }
2099                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2100                                         assign_reg (cfg, rs, sregs [j], val, bank);
2101                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2102                                         if (spill) {
2103                                                 /*
2104                                                  * Need to insert before the instruction since it can
2105                                                  * overwrite sreg2.
2106                                                  */
2107                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2108                                         }
2109                                 }
2110                                 sregs [j] = val;
2111                                 for (k = j + 1; k < num_sregs; ++k)
2112                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2113                         }
2114                         else {
2115                                 prev_sregs [j] = -1;
2116                         }
2117                 }
2118                 mono_inst_set_src_registers (ins, sregs);
2119
2120                 /* Sanity check */
2121                 /* Do this only for CAS for now */
2122                 for (j = 1; j < num_sregs; ++j) {
2123                         int sreg = sregs [j];
2124                         int dest_sreg = dest_sregs [j];
2125
2126                         if (j == 2 && dest_sreg != -1) {
2127                                 int k;
2128
2129                                 g_assert (sreg == dest_sreg);
2130
2131                                 for (k = 0; k < num_sregs; ++k) {
2132                                         if (k != j)
2133                                                 g_assert (sregs [k] != dest_sreg);
2134                                 }
2135                         }
2136                 }
2137
2138                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2139                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2140                         mono_regstate_free_int (rs, ins->sreg1);
2141                 }
2142                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2143                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2144                         mono_regstate_free_int (rs, ins->sreg2);
2145                 }*/
2146
2147                 DEBUG (mono_print_ins_index (i, ins));
2148         }
2149
2150         // FIXME: Set MAX_FREGS to 8
2151         // FIXME: Optimize generated code
2152 #if MONO_ARCH_USE_FPSTACK
2153         /*
2154          * Make a forward pass over the code, simulating the fp stack, making sure the
2155          * arguments required by the fp opcodes are at the top of the stack.
2156          */
2157         if (has_fp) {
2158                 MonoInst *prev = NULL;
2159                 MonoInst *fxch;
2160                 int tmp;
2161
2162                 g_assert (num_sregs <= 2);
2163
2164                 for (ins = bb->code; ins; ins = ins->next) {
2165                         spec = ins_get_spec (ins->opcode);
2166
2167                         DEBUG (printf ("processing:"));
2168                         DEBUG (mono_print_ins_index (0, ins));
2169
2170                         if (ins->opcode == OP_FMOVE) {
2171                                 /* Do it by renaming the source to the destination on the stack */
2172                                 // FIXME: Is this correct ?
2173                                 for (i = 0; i < sp; ++i)
2174                                         if (fpstack [i] == ins->sreg1)
2175                                                 fpstack [i] = ins->dreg;
2176                                 prev = ins;
2177                                 continue;
2178                         }
2179
2180                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2181                                 /* Arg1 must be in %st(1) */
2182                                 g_assert (prev);
2183
2184                                 i = 0;
2185                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2186                                         i ++;
2187                                 g_assert (i < sp);
2188
2189                                 if (sp - 1 - i > 0) {
2190                                         /* First move it to %st(0) */
2191                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2192
2193                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2194                                         fxch->inst_imm = sp - 1 - i;
2195
2196                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2197                                         prev = fxch;
2198
2199                                         tmp = fpstack [sp - 1];
2200                                         fpstack [sp - 1] = fpstack [i];
2201                                         fpstack [i] = tmp;
2202                                 }
2203
2204                                 /* Then move it to %st(1) */
2205                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2206
2207                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2208                                 fxch->inst_imm = 1;
2209
2210                                 mono_bblock_insert_after_ins (bb, prev, fxch);
2211                                 prev = fxch;
2212
2213                                 tmp = fpstack [sp - 1];
2214                                 fpstack [sp - 1] = fpstack [sp - 2];
2215                                 fpstack [sp - 2] = tmp;
2216                         }
2217
2218                         if (sreg2_is_fp (spec)) {
2219                                 g_assert (sp > 0);
2220
2221                                 if (fpstack [sp - 1] != ins->sreg2) {
2222                                         g_assert (prev);
2223
2224                                         i = 0;
2225                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2226                                                 i ++;
2227                                         g_assert (i < sp);
2228
2229                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2230
2231                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2232                                         fxch->inst_imm = sp - 1 - i;
2233
2234                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2235                                         prev = fxch;
2236
2237                                         tmp = fpstack [sp - 1];
2238                                         fpstack [sp - 1] = fpstack [i];
2239                                         fpstack [i] = tmp;
2240                                 }
2241
2242                                 sp --;
2243                         }
2244
2245                         if (sreg1_is_fp (spec)) {
2246                                 g_assert (sp > 0);
2247
2248                                 if (fpstack [sp - 1] != ins->sreg1) {
2249                                         g_assert (prev);
2250
2251                                         i = 0;
2252                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2253                                                 i ++;
2254                                         g_assert (i < sp);
2255
2256                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2257
2258                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2259                                         fxch->inst_imm = sp - 1 - i;
2260
2261                                         mono_bblock_insert_after_ins (bb, prev, fxch);
2262                                         prev = fxch;
2263
2264                                         tmp = fpstack [sp - 1];
2265                                         fpstack [sp - 1] = fpstack [i];
2266                                         fpstack [i] = tmp;
2267                                 }
2268
2269                                 sp --;
2270                         }
2271
2272                         if (dreg_is_fp (spec)) {
2273                                 g_assert (sp < 8);
2274                                 fpstack [sp ++] = ins->dreg;
2275                         }
2276
2277                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2278                                 printf ("\t[");
2279                                 for (i = 0; i < sp; ++i)
2280                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2281                                 printf ("]\n");
2282                         }
2283
2284                         prev = ins;
2285                 }
2286
2287                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2288                         /* Remove remaining items from the fp stack */
2289                         /*
2290                          * These can remain for example as a result of a dead fmove like in
2291                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2292                          */
2293                         while (sp) {
2294                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2295                                 mono_add_ins_to_end (bb, ins);
2296                                 sp --;
2297                         }
2298                 }
2299         }
2300 #endif
2301 }
2302
2303 CompRelation
2304 mono_opcode_to_cond (int opcode)
2305 {
2306         switch (opcode) {
2307         case OP_CEQ:
2308         case OP_IBEQ:
2309         case OP_ICEQ:
2310         case OP_LBEQ:
2311         case OP_LCEQ:
2312         case OP_FBEQ:
2313         case OP_FCEQ:
2314         case OP_RBEQ:
2315         case OP_RCEQ:
2316         case OP_COND_EXC_EQ:
2317         case OP_COND_EXC_IEQ:
2318         case OP_CMOV_IEQ:
2319         case OP_CMOV_LEQ:
2320                 return CMP_EQ;
2321         case OP_FCNEQ:
2322         case OP_ICNEQ:
2323         case OP_IBNE_UN:
2324         case OP_LBNE_UN:
2325         case OP_FBNE_UN:
2326         case OP_COND_EXC_NE_UN:
2327         case OP_COND_EXC_INE_UN:
2328         case OP_CMOV_INE_UN:
2329         case OP_CMOV_LNE_UN:
2330                 return CMP_NE;
2331         case OP_FCLE:
2332         case OP_ICLE:
2333         case OP_IBLE:
2334         case OP_LBLE:
2335         case OP_FBLE:
2336         case OP_CMOV_ILE:
2337         case OP_CMOV_LLE:
2338                 return CMP_LE;
2339         case OP_FCGE:
2340         case OP_ICGE:
2341         case OP_IBGE:
2342         case OP_LBGE:
2343         case OP_FBGE:
2344         case OP_CMOV_IGE:
2345         case OP_CMOV_LGE:
2346                 return CMP_GE;
2347         case OP_CLT:
2348         case OP_IBLT:
2349         case OP_ICLT:
2350         case OP_LBLT:
2351         case OP_LCLT:
2352         case OP_FBLT:
2353         case OP_FCLT:
2354         case OP_RBLT:
2355         case OP_RCLT:
2356         case OP_COND_EXC_LT:
2357         case OP_COND_EXC_ILT:
2358         case OP_CMOV_ILT:
2359         case OP_CMOV_LLT:
2360                 return CMP_LT;
2361         case OP_CGT:
2362         case OP_IBGT:
2363         case OP_ICGT:
2364         case OP_LBGT:
2365         case OP_LCGT:
2366         case OP_FBGT:
2367         case OP_FCGT:
2368         case OP_RBGT:
2369         case OP_RCGT:
2370         case OP_COND_EXC_GT:
2371         case OP_COND_EXC_IGT:
2372         case OP_CMOV_IGT:
2373         case OP_CMOV_LGT:
2374                 return CMP_GT;
2375
2376         case OP_ICLE_UN:
2377         case OP_IBLE_UN:
2378         case OP_LBLE_UN:
2379         case OP_FBLE_UN:
2380         case OP_COND_EXC_LE_UN:
2381         case OP_COND_EXC_ILE_UN:
2382         case OP_CMOV_ILE_UN:
2383         case OP_CMOV_LLE_UN:
2384                 return CMP_LE_UN;
2385
2386         case OP_ICGE_UN:
2387         case OP_IBGE_UN:
2388         case OP_LBGE_UN:
2389         case OP_FBGE_UN:
2390         case OP_CMOV_IGE_UN:
2391         case OP_CMOV_LGE_UN:
2392                 return CMP_GE_UN;
2393         case OP_CLT_UN:
2394         case OP_IBLT_UN:
2395         case OP_ICLT_UN:
2396         case OP_LBLT_UN:
2397         case OP_LCLT_UN:
2398         case OP_FBLT_UN:
2399         case OP_FCLT_UN:
2400         case OP_RBLT_UN:
2401         case OP_RCLT_UN:
2402         case OP_COND_EXC_LT_UN:
2403         case OP_COND_EXC_ILT_UN:
2404         case OP_CMOV_ILT_UN:
2405         case OP_CMOV_LLT_UN:
2406                 return CMP_LT_UN;
2407         case OP_CGT_UN:
2408         case OP_IBGT_UN:
2409         case OP_ICGT_UN:
2410         case OP_LBGT_UN:
2411         case OP_LCGT_UN:
2412         case OP_FCGT_UN:
2413         case OP_FBGT_UN:
2414         case OP_RCGT_UN:
2415         case OP_RBGT_UN:
2416         case OP_COND_EXC_GT_UN:
2417         case OP_COND_EXC_IGT_UN:
2418         case OP_CMOV_IGT_UN:
2419         case OP_CMOV_LGT_UN:
2420                 return CMP_GT_UN;
2421         default:
2422                 printf ("%s\n", mono_inst_name (opcode));
2423                 g_assert_not_reached ();
2424                 return 0;
2425         }
2426 }
2427
2428 CompRelation
2429 mono_negate_cond (CompRelation cond)
2430 {
2431         switch (cond) {
2432         case CMP_EQ:
2433                 return CMP_NE;
2434         case CMP_NE:
2435                 return CMP_EQ;
2436         case CMP_LE:
2437                 return CMP_GT;
2438         case CMP_GE:
2439                 return CMP_LT;
2440         case CMP_LT:
2441                 return CMP_GE;
2442         case CMP_GT:
2443                 return CMP_LE;
2444         case CMP_LE_UN:
2445                 return CMP_GT_UN;
2446         case CMP_GE_UN:
2447                 return CMP_LT_UN;
2448         case CMP_LT_UN:
2449                 return CMP_GE_UN;
2450         case CMP_GT_UN:
2451                 return CMP_LE_UN;
2452         default:
2453                 g_assert_not_reached ();
2454         }
2455 }
2456
2457 CompType
2458 mono_opcode_to_type (int opcode, int cmp_opcode)
2459 {
2460         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2461                 return CMP_TYPE_L;
2462         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2463                 return CMP_TYPE_I;
2464         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2465                 return CMP_TYPE_I;
2466         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2467                 return CMP_TYPE_L;
2468         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2469                 return CMP_TYPE_L;
2470         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2471                 return CMP_TYPE_F;
2472         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2473                 return CMP_TYPE_F;
2474         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2475                 return CMP_TYPE_I;
2476         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2477                 switch (cmp_opcode) {
2478                 case OP_ICOMPARE:
2479                 case OP_ICOMPARE_IMM:
2480                         return CMP_TYPE_I;
2481                 default:
2482                         return CMP_TYPE_L;
2483                 }
2484         } else {
2485                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2486                 return 0;
2487         }
2488 }
2489
2490 #endif /* DISABLE_JIT */
2491
2492 gboolean
2493 mono_is_regsize_var (MonoType *t)
2494 {
2495         if (t->byref)
2496                 return TRUE;
2497         t = mono_type_get_underlying_type (t);
2498         switch (t->type) {
2499         case MONO_TYPE_BOOLEAN:
2500         case MONO_TYPE_CHAR:
2501         case MONO_TYPE_I1:
2502         case MONO_TYPE_U1:
2503         case MONO_TYPE_I2:
2504         case MONO_TYPE_U2:
2505         case MONO_TYPE_I4:
2506         case MONO_TYPE_U4:
2507         case MONO_TYPE_I:
2508         case MONO_TYPE_U:
2509         case MONO_TYPE_PTR:
2510         case MONO_TYPE_FNPTR:
2511 #if SIZEOF_REGISTER == 8
2512         case MONO_TYPE_I8:
2513         case MONO_TYPE_U8:
2514 #endif
2515                 return TRUE;
2516         case MONO_TYPE_OBJECT:
2517         case MONO_TYPE_STRING:
2518         case MONO_TYPE_CLASS:
2519         case MONO_TYPE_SZARRAY:
2520         case MONO_TYPE_ARRAY:
2521                 return TRUE;
2522         case MONO_TYPE_GENERICINST:
2523                 if (!mono_type_generic_inst_is_valuetype (t))
2524                         return TRUE;
2525                 return FALSE;
2526         case MONO_TYPE_VALUETYPE:
2527                 return FALSE;
2528         default:
2529                 return FALSE;
2530         }
2531 }
2532
2533 #ifndef DISABLE_JIT
2534
2535 /*
2536  * mono_peephole_ins:
2537  *
2538  *   Perform some architecture independent peephole optimizations.
2539  */
2540 void
2541 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2542 {
2543         int filter = FILTER_IL_SEQ_POINT;
2544         MonoInst *last_ins = mono_inst_prev (ins, filter);
2545
2546         switch (ins->opcode) {
2547         case OP_MUL_IMM:
2548                 /* remove unnecessary multiplication with 1 */
2549                 if (ins->inst_imm == 1) {
2550                         if (ins->dreg != ins->sreg1)
2551                                 ins->opcode = OP_MOVE;
2552                         else
2553                                 MONO_DELETE_INS (bb, ins);
2554                 }
2555                 break;
2556         case OP_LOAD_MEMBASE:
2557         case OP_LOADI4_MEMBASE:
2558                 /*
2559                  * Note: if reg1 = reg2 the load op is removed
2560                  *
2561                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2562                  * OP_LOAD_MEMBASE offset(basereg), reg2
2563                  * -->
2564                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2565                  * OP_MOVE reg1, reg2
2566                  */
2567                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2568                         last_ins = mono_inst_prev (ins, filter);
2569                 if (last_ins &&
2570                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2571                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2572                         ins->inst_basereg == last_ins->inst_destbasereg &&
2573                         ins->inst_offset == last_ins->inst_offset) {
2574                         if (ins->dreg == last_ins->sreg1) {
2575                                 MONO_DELETE_INS (bb, ins);
2576                                 break;
2577                         } else {
2578                                 ins->opcode = OP_MOVE;
2579                                 ins->sreg1 = last_ins->sreg1;
2580                         }
2581
2582                         /*
2583                          * Note: reg1 must be different from the basereg in the second load
2584                          * Note: if reg1 = reg2 is equal then second load is removed
2585                          *
2586                          * OP_LOAD_MEMBASE offset(basereg), reg1
2587                          * OP_LOAD_MEMBASE offset(basereg), reg2
2588                          * -->
2589                          * OP_LOAD_MEMBASE offset(basereg), reg1
2590                          * OP_MOVE reg1, reg2
2591                          */
2592                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2593                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2594                           ins->inst_basereg != last_ins->dreg &&
2595                           ins->inst_basereg == last_ins->inst_basereg &&
2596                           ins->inst_offset == last_ins->inst_offset) {
2597
2598                         if (ins->dreg == last_ins->dreg) {
2599                                 MONO_DELETE_INS (bb, ins);
2600                         } else {
2601                                 ins->opcode = OP_MOVE;
2602                                 ins->sreg1 = last_ins->dreg;
2603                         }
2604
2605                         //g_assert_not_reached ();
2606
2607 #if 0
2608                         /*
2609                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2610                          * OP_LOAD_MEMBASE offset(basereg), reg
2611                          * -->
2612                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2613                          * OP_ICONST reg, imm
2614                          */
2615                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2616                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2617                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2618                                    ins->inst_offset == last_ins->inst_offset) {
2619                         ins->opcode = OP_ICONST;
2620                         ins->inst_c0 = last_ins->inst_imm;
2621                         g_assert_not_reached (); // check this rule
2622 #endif
2623                 }
2624                 break;
2625         case OP_LOADI1_MEMBASE:
2626         case OP_LOADU1_MEMBASE:
2627                 /*
2628                  * Note: if reg1 = reg2 the load op is removed
2629                  *
2630                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2631                  * OP_LOAD_MEMBASE offset(basereg), reg2
2632                  * -->
2633                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2634                  * OP_MOVE reg1, reg2
2635                  */
2636                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2637                         ins->inst_basereg == last_ins->inst_destbasereg &&
2638                         ins->inst_offset == last_ins->inst_offset) {
2639                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2640                         ins->sreg1 = last_ins->sreg1;
2641                 }
2642                 break;
2643         case OP_LOADI2_MEMBASE:
2644         case OP_LOADU2_MEMBASE:
2645                 /*
2646                  * Note: if reg1 = reg2 the load op is removed
2647                  *
2648                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2649                  * OP_LOAD_MEMBASE offset(basereg), reg2
2650                  * -->
2651                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2652                  * OP_MOVE reg1, reg2
2653                  */
2654                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2655                         ins->inst_basereg == last_ins->inst_destbasereg &&
2656                         ins->inst_offset == last_ins->inst_offset) {
2657 #if SIZEOF_REGISTER == 8
2658                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2659 #else
2660                         /* The definition of OP_PCONV_TO_U2 is wrong */
2661                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2662 #endif
2663                         ins->sreg1 = last_ins->sreg1;
2664                 }
2665                 break;
2666         case OP_MOVE:
2667         case OP_FMOVE:
2668                 /*
2669                  * Removes:
2670                  *
2671                  * OP_MOVE reg, reg
2672                  */
2673                 if (ins->dreg == ins->sreg1) {
2674                         MONO_DELETE_INS (bb, ins);
2675                         break;
2676                 }
2677                 /*
2678                  * Removes:
2679                  *
2680                  * OP_MOVE sreg, dreg
2681                  * OP_MOVE dreg, sreg
2682                  */
2683                 if (last_ins && last_ins->opcode == ins->opcode &&
2684                         ins->sreg1 == last_ins->dreg &&
2685                         ins->dreg == last_ins->sreg1) {
2686                         MONO_DELETE_INS (bb, ins);
2687                 }
2688                 break;
2689         case OP_NOP:
2690                 MONO_DELETE_INS (bb, ins);
2691                 break;
2692         }
2693 }
2694
2695 int
2696 mini_exception_id_by_name (const char *name)
2697 {
2698         if (strcmp (name, "IndexOutOfRangeException") == 0)
2699                 return MONO_EXC_INDEX_OUT_OF_RANGE;
2700         if (strcmp (name, "OverflowException") == 0)
2701                 return MONO_EXC_OVERFLOW;
2702         if (strcmp (name, "ArithmeticException") == 0)
2703                 return MONO_EXC_ARITHMETIC;
2704         if (strcmp (name, "DivideByZeroException") == 0)
2705                 return MONO_EXC_DIVIDE_BY_ZERO;
2706         if (strcmp (name, "InvalidCastException") == 0)
2707                 return MONO_EXC_INVALID_CAST;
2708         if (strcmp (name, "NullReferenceException") == 0)
2709                 return MONO_EXC_NULL_REF;
2710         if (strcmp (name, "ArrayTypeMismatchException") == 0)
2711                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
2712         if (strcmp (name, "ArgumentException") == 0)
2713                 return MONO_EXC_ARGUMENT;
2714         g_error ("Unknown intrinsic exception %s\n", name);
2715         return -1;
2716 }
2717
2718 gboolean
2719 mini_type_is_hfa (MonoType *t, int *out_nfields, int *out_esize)
2720 {
2721         MonoClass *klass;
2722         gpointer iter;
2723         MonoClassField *field;
2724         MonoType *ftype, *prev_ftype = NULL;
2725         int nfields = 0;
2726
2727         klass = mono_class_from_mono_type (t);
2728         iter = NULL;
2729         while ((field = mono_class_get_fields (klass, &iter))) {
2730                 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
2731                         continue;
2732                 ftype = mono_field_get_type (field);
2733                 ftype = mini_native_type_replace_type (ftype);
2734
2735                 if (MONO_TYPE_ISSTRUCT (ftype)) {
2736                         int nested_nfields, nested_esize;
2737
2738                         if (!mini_type_is_hfa (ftype, &nested_nfields, &nested_esize))
2739                                 return FALSE;
2740                         if (nested_esize == 4)
2741                                 ftype = &mono_defaults.single_class->byval_arg;
2742                         else
2743                                 ftype = &mono_defaults.double_class->byval_arg;
2744                         if (prev_ftype && prev_ftype->type != ftype->type)
2745                                 return FALSE;
2746                         prev_ftype = ftype;
2747                         nfields += nested_nfields;
2748                         // FIXME: Nested float structs are aligned to 8 bytes
2749                         if (ftype->type == MONO_TYPE_R4)
2750                                 return FALSE;
2751                 } else {
2752                         if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
2753                                 return FALSE;
2754                         if (prev_ftype && prev_ftype->type != ftype->type)
2755                                 return FALSE;
2756                         prev_ftype = ftype;
2757                         nfields ++;
2758                 }
2759         }
2760         if (nfields == 0 || nfields > 4)
2761                 return FALSE;
2762         *out_nfields = nfields;
2763         *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
2764         return TRUE;
2765 }
2766
2767 #endif /* DISABLE_JIT */