mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/metadata/mempool-internals.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "mini.h"
  21 #include "trace.h"
  22 #include "mini-arch.h"
  23
  24 #ifndef MONO_MAX_XREGS
  25
  26 #define MONO_MAX_XREGS 0
  27 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  28 #define MONO_ARCH_CALLEE_XREGS 0
  29
  30 #endif
  31
  32
  33 #define MONO_ARCH_BANK_MIRRORED -2
  34
  35 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
  36
  37 #ifndef MONO_ARCH_NEED_SIMD_BANK
  38 #error "MONO_ARCH_USE_SHARED_FP_SIMD_BANK needs MONO_ARCH_NEED_SIMD_BANK to work"
  39 #endif
  40
  41 #define get_mirrored_bank(bank) (((bank) == MONO_REG_SIMD ) ? MONO_REG_DOUBLE : (((bank) == MONO_REG_DOUBLE ) ? MONO_REG_SIMD : -1))
  42
  43 #define is_hreg_mirrored(rs, bank, hreg) ((rs)->symbolic [(bank)] [(hreg)] == MONO_ARCH_BANK_MIRRORED)
  44
  45
  46 #else
  47
  48
  49 #define get_mirrored_bank(bank) (-1)
  50
  51 #define is_hreg_mirrored(rs, bank, hreg) (0)
  52
  53 #endif
  54
  55
  56 /* If the bank is mirrored return the true logical bank that the register in the
  57  * physical register bank is allocated to.
  58  */
  59 static inline int translate_bank (MonoRegState *rs, int bank, int hreg) {
  60         return is_hreg_mirrored (rs, bank, hreg) ? get_mirrored_bank (bank) : bank;
  61 }
  62
  63 /*
  64  * Every hardware register belongs to a register type or register bank. bank 0
  65  * contains the int registers, bank 1 contains the fp registers.
  66  * int registers are used 99% of the time, so they are special cased in a lot of
  67  * places.
  68  */
  69
  70 static const int regbank_size [] = {
  71         MONO_MAX_IREGS,
  72         MONO_MAX_FREGS,
  73         MONO_MAX_IREGS,
  74         MONO_MAX_IREGS,
  75         MONO_MAX_XREGS
  76 };
  77
  78 static const int regbank_load_ops [] = {
  79         OP_LOADR_MEMBASE,
  80         OP_LOADR8_MEMBASE,
  81         OP_LOADR_MEMBASE,
  82         OP_LOADR_MEMBASE,
  83         OP_LOADX_MEMBASE
  84 };
  85
  86 static const int regbank_store_ops [] = {
  87         OP_STORER_MEMBASE_REG,
  88         OP_STORER8_MEMBASE_REG,
  89         OP_STORER_MEMBASE_REG,
  90         OP_STORER_MEMBASE_REG,
  91         OP_STOREX_MEMBASE
  92 };
  93
  94 static const int regbank_move_ops [] = {
  95         OP_MOVE,
  96         OP_FMOVE,
  97         OP_MOVE,
  98         OP_MOVE,
  99         OP_XMOVE
 100 };
 101
 102 #define regmask(reg) (((regmask_t)1) << (reg))
 103
 104 static const regmask_t regbank_callee_saved_regs [] = {
 105         MONO_ARCH_CALLEE_SAVED_REGS,
 106         MONO_ARCH_CALLEE_SAVED_FREGS,
 107         MONO_ARCH_CALLEE_SAVED_REGS,
 108         MONO_ARCH_CALLEE_SAVED_REGS,
 109         MONO_ARCH_CALLEE_SAVED_XREGS,
 110 };
 111
 112 static const regmask_t regbank_callee_regs [] = {
 113         MONO_ARCH_CALLEE_REGS,
 114         MONO_ARCH_CALLEE_FREGS,
 115         MONO_ARCH_CALLEE_REGS,
 116         MONO_ARCH_CALLEE_REGS,
 117         MONO_ARCH_CALLEE_XREGS,
 118 };
 119
 120 static const int regbank_spill_var_size[] = {
 121         sizeof (mgreg_t),
 122         sizeof (double),
 123         sizeof (mgreg_t),
 124         sizeof (mgreg_t),
 125         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
 126 };
 127
 128 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
 129
 130 static inline void
 131 mono_regstate_assign (MonoRegState *rs)
 132 {
 133 #ifdef MONO_ARCH_USE_SHARED_FP_SIMD_BANK
 134         /* The regalloc may fail if fp and simd logical regbanks share the same physical reg bank and
 135          * if the values here are not the same.
 136          */
 137         g_assert(regbank_callee_regs [MONO_REG_SIMD] == regbank_callee_regs [MONO_REG_DOUBLE]);
 138         g_assert(regbank_callee_saved_regs [MONO_REG_SIMD] == regbank_callee_saved_regs [MONO_REG_DOUBLE]);
 139         g_assert(regbank_size [MONO_REG_SIMD] == regbank_size [MONO_REG_DOUBLE]);
 140 #endif
 141
 142         if (rs->next_vreg > rs->vassign_size) {
 143                 g_free (rs->vassign);
 144                 rs->vassign_size = MAX (rs->next_vreg, 256);
 145                 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
 146         }
 147
 148         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 149         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 150
 151         rs->symbolic [MONO_REG_INT] = rs->isymbolic;
 152         rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
 153
 154 #ifdef MONO_ARCH_NEED_SIMD_BANK
 155         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 156         rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
 157 #endif
 158 }
 159
 160 static inline int
 161 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 162 {
 163         regmask_t mask = allow & rs->ifree_mask;
 164
 165 #if defined(__x86_64__) && defined(__GNUC__)
 166  {
 167         guint64 i;
 168
 169         if (mask == 0)
 170                 return -1;
 171
 172         __asm__("bsfq %1,%0\n\t"
 173                         : "=r" (i) : "rm" (mask));
 174
 175         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 176         return i;
 177  }
 178 #else
 179         int i;
 180
 181         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 182                 if (mask & ((regmask_t)1 << i)) {
 183                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 184                         return i;
 185                 }
 186         }
 187         return -1;
 188 #endif
 189 }
 190
 191 static inline void
 192 mono_regstate_free_int (MonoRegState *rs, int reg)
 193 {
 194         if (reg >= 0) {
 195                 rs->ifree_mask |= (regmask_t)1 << reg;
 196                 rs->isymbolic [reg] = 0;
 197         }
 198 }
 199
 200 static inline int
 201 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 202 {
 203         int i;
 204         int mirrored_bank;
 205         regmask_t mask = allow & rs->free_mask [bank];
 206         for (i = 0; i < regbank_size [bank]; ++i) {
 207                 if (mask & ((regmask_t)1 << i)) {
 208                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 209
 210                         mirrored_bank = get_mirrored_bank (bank);
 211                         if (mirrored_bank == -1)
 212                                 return i;
 213
 214                         rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 215                         return i;
 216                 }
 217         }
 218         return -1;
 219 }
 220
 221 static inline void
 222 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 223 {
 224         int mirrored_bank;
 225
 226         if (reg >= 0) {
 227                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 228                 rs->symbolic [bank][reg] = 0;
 229
 230                 mirrored_bank = get_mirrored_bank (bank);
 231                 if (mirrored_bank == -1)
 232                         return;
 233                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 234                 rs->symbolic [mirrored_bank][reg] = 0;
 235         }
 236 }
 237
 238 const char*
 239 mono_regname_full (int reg, int bank)
 240 {
 241         if (G_UNLIKELY (bank)) {
 242 #if MONO_ARCH_NEED_SIMD_BANK
 243                 if (bank == MONO_REG_SIMD)
 244                         return mono_arch_xregname (reg);
 245 #endif
 246                 if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
 247                         return mono_arch_regname (reg);
 248                 g_assert (bank == MONO_REG_DOUBLE);
 249                 return mono_arch_fregname (reg);
 250         } else {
 251                 return mono_arch_regname (reg);
 252         }
 253 }
 254
 255 void
 256 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 257 {
 258         guint32 regpair;
 259
 260         regpair = (((guint32)hreg) << 24) + vreg;
 261         if (G_UNLIKELY (bank)) {
 262                 g_assert (vreg >= regbank_size [bank]);
 263                 g_assert (hreg < regbank_size [bank]);
 264                 call->used_fregs |= 1 << hreg;
 265                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 266         } else {
 267                 g_assert (vreg >= MONO_MAX_IREGS);
 268                 g_assert (hreg < MONO_MAX_IREGS);
 269                 call->used_iregs |= 1 << hreg;
 270                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 271         }
 272 }
 273
 274 static void
 275 resize_spill_info (MonoCompile *cfg, int bank)
 276 {
 277         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 278         int orig_len = cfg->spill_info_len [bank];
 279         int new_len = orig_len ? orig_len * 2 : 16;
 280         MonoSpillInfo *new_info;
 281         int i;
 282
 283         g_assert (bank < MONO_NUM_REGBANKS);
 284
 285         new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 286         if (orig_info)
 287                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 288         for (i = orig_len; i < new_len; ++i)
 289                 new_info [i].offset = -1;
 290
 291         cfg->spill_info [bank] = new_info;
 292         cfg->spill_info_len [bank] = new_len;
 293 }
 294
 295 /*
 296  * returns the offset used by spillvar. It allocates a new
 297  * spill variable if necessary.
 298  */
 299 static inline int
 300 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 301 {
 302         MonoSpillInfo *info;
 303         int size;
 304
 305         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 306                 while (spillvar >= cfg->spill_info_len [bank])
 307                         resize_spill_info (cfg, bank);
 308         }
 309
 310         /*
 311          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 312          */
 313         info = &cfg->spill_info [bank][spillvar];
 314         if (info->offset == -1) {
 315                 cfg->stack_offset += sizeof (mgreg_t) - 1;
 316                 cfg->stack_offset &= ~(sizeof (mgreg_t) - 1);
 317
 318                 g_assert (bank < MONO_NUM_REGBANKS);
 319                 if (G_UNLIKELY (bank))
 320                         size = regbank_spill_var_size [bank];
 321                 else
 322                         size = sizeof (mgreg_t);
 323
 324                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 325                         cfg->stack_offset += size - 1;
 326                         cfg->stack_offset &= ~(size - 1);
 327                         info->offset = cfg->stack_offset;
 328                         cfg->stack_offset += size;
 329                 } else {
 330                         cfg->stack_offset += size - 1;
 331                         cfg->stack_offset &= ~(size - 1);
 332                         cfg->stack_offset += size;
 333                         info->offset = - cfg->stack_offset;
 334                 }
 335         }
 336
 337         return info->offset;
 338 }
 339
 340 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 341 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 342 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 343 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 344 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 345 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 346
 347 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 348 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 349 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 350 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 351 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 352
 353 #ifndef MONO_ARCH_INST_IS_FLOAT
 354 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 355 #endif
 356
 357 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 358 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 359 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
 360 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
 361 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
 362
 363 #define reg_is_simd(desc) ((desc) == 'x')
 364
 365 #ifdef MONO_ARCH_NEED_SIMD_BANK
 366
 367 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 368
 369 #else
 370
 371 #define reg_bank(desc) reg_is_fp ((desc))
 372
 373 #endif
 374
 375 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
 376 #define sreg1_bank(spec) sreg_bank (0, (spec))
 377 #define sreg2_bank(spec) sreg_bank (1, (spec))
 378 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 379
 380 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
 381 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
 382 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
 383 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 384
 385 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 386
 387 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 388 #undef is_global_ireg
 389 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 390 #endif
 391
 392 typedef struct {
 393         int born_in;
 394         int killed_in;
 395         /* Not (yet) used */
 396         //int last_use;
 397         //int prev_use;
 398         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 399 } RegTrack;
 400
 401 #ifndef DISABLE_LOGGING
 402 void
 403 mono_print_ins_index (int i, MonoInst *ins)
 404 {
 405         const char *spec = ins_get_spec (ins->opcode);
 406         int num_sregs, j;
 407         int sregs [MONO_MAX_SRC_REGS];
 408
 409         if (i != -1)
 410                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 411         else
 412                 printf (" %s", mono_inst_name (ins->opcode));
 413         if (spec == MONO_ARCH_CPU_SPEC) {
 414                 /* This is a lowered opcode */
 415                 if (ins->dreg != -1)
 416                         printf (" R%d <-", ins->dreg);
 417                 if (ins->sreg1 != -1)
 418                         printf (" R%d", ins->sreg1);
 419                 if (ins->sreg2 != -1)
 420                         printf (" R%d", ins->sreg2);
 421                 if (ins->sreg3 != -1)
 422                         printf (" R%d", ins->sreg3);
 423
 424                 switch (ins->opcode) {
 425                 case OP_LBNE_UN:
 426                 case OP_LBEQ:
 427                 case OP_LBLT:
 428                 case OP_LBLT_UN:
 429                 case OP_LBGT:
 430                 case OP_LBGT_UN:
 431                 case OP_LBGE:
 432                 case OP_LBGE_UN:
 433                 case OP_LBLE:
 434                 case OP_LBLE_UN:
 435                         if (!ins->inst_false_bb)
 436                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 437                         else
 438                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 439                         break;
 440                 case OP_PHI:
 441                 case OP_VPHI:
 442                 case OP_XPHI:
 443                 case OP_FPHI: {
 444                         int i;
 445                         printf (" [%d (", (int)ins->inst_c0);
 446                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 447                                 if (i)
 448                                         printf (", ");
 449                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 450                         }
 451                         printf (")]");
 452                         break;
 453                 }
 454                 case OP_LDADDR:
 455                 case OP_OUTARG_VTRETADDR:
 456                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 457                         break;
 458                 case OP_REGOFFSET:
 459                         printf (" + 0x%lx", (long)ins->inst_offset);
 460                         break;
 461                 default:
 462                         break;
 463                 }
 464
 465                 printf ("\n");
 466                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 467                 return;
 468         }
 469
 470         if (spec [MONO_INST_DEST]) {
 471                 int bank = dreg_bank (spec);
 472                 if (is_soft_reg (ins->dreg, bank)) {
 473                         if (spec [MONO_INST_DEST] == 'b') {
 474                                 if (ins->inst_offset == 0)
 475                                         printf (" [R%d] <-", ins->dreg);
 476                                 else
 477                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 478                         }
 479                         else
 480                                 printf (" R%d <-", ins->dreg);
 481                 } else if (spec [MONO_INST_DEST] == 'b') {
 482                         if (ins->inst_offset == 0)
 483                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 484                         else
 485                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 486                 } else
 487                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 488         }
 489         if (spec [MONO_INST_SRC1]) {
 490                 int bank = sreg1_bank (spec);
 491                 if (is_soft_reg (ins->sreg1, bank)) {
 492                         if (spec [MONO_INST_SRC1] == 'b')
 493                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 494                         else
 495                                 printf (" R%d", ins->sreg1);
 496                 } else if (spec [MONO_INST_SRC1] == 'b')
 497                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 498                 else
 499                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 500         }
 501         num_sregs = mono_inst_get_src_registers (ins, sregs);
 502         for (j = 1; j < num_sregs; ++j) {
 503                 int bank = sreg_bank (j, spec);
 504                 if (is_soft_reg (sregs [j], bank))
 505                         printf (" R%d", sregs [j]);
 506                 else
 507                         printf (" %s", mono_regname_full (sregs [j], bank));
 508         }
 509
 510         switch (ins->opcode) {
 511         case OP_ICONST:
 512                 printf (" [%d]", (int)ins->inst_c0);
 513                 break;
 514 #if defined(TARGET_X86) || defined(TARGET_AMD64)
 515         case OP_X86_PUSH_IMM:
 516 #endif
 517         case OP_ICOMPARE_IMM:
 518         case OP_COMPARE_IMM:
 519         case OP_IADD_IMM:
 520         case OP_ISUB_IMM:
 521         case OP_IAND_IMM:
 522         case OP_IOR_IMM:
 523         case OP_IXOR_IMM:
 524                 printf (" [%d]", (int)ins->inst_imm);
 525                 break;
 526         case OP_ADD_IMM:
 527         case OP_LADD_IMM:
 528                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 529                 break;
 530         case OP_I8CONST:
 531                 printf (" [%lld]", (long long)ins->inst_l);
 532                 break;
 533         case OP_R8CONST:
 534                 printf (" [%f]", *(double*)ins->inst_p0);
 535                 break;
 536         case OP_R4CONST:
 537                 printf (" [%f]", *(float*)ins->inst_p0);
 538                 break;
 539         case OP_CALL:
 540         case OP_CALL_MEMBASE:
 541         case OP_CALL_REG:
 542         case OP_FCALL:
 543         case OP_FCALLVIRT:
 544         case OP_LCALL:
 545         case OP_LCALLVIRT:
 546         case OP_VCALL:
 547         case OP_VCALLVIRT:
 548         case OP_VCALL_REG:
 549         case OP_VCALL_MEMBASE:
 550         case OP_VCALL2:
 551         case OP_VCALL2_REG:
 552         case OP_VCALL2_MEMBASE:
 553         case OP_VOIDCALL:
 554         case OP_VOIDCALL_MEMBASE:
 555         case OP_VOIDCALLVIRT: {
 556                 MonoCallInst *call = (MonoCallInst*)ins;
 557                 GSList *list;
 558
 559                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 560                         /*
 561                          * These are lowered opcodes, but they are in the .md files since the old
 562                          * JIT passes them to backends.
 563                          */
 564                         if (ins->dreg != -1)
 565                                 printf (" R%d <-", ins->dreg);
 566                 }
 567
 568                 if (call->method) {
 569                         char *full_name = mono_method_full_name (call->method, TRUE);
 570                         printf (" [%s]", full_name);
 571                         g_free (full_name);
 572                 } else if (call->fptr) {
 573                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 574                         if (info)
 575                                 printf (" [%s]", info->name);
 576                 }
 577
 578                 list = call->out_ireg_args;
 579                 while (list) {
 580                         guint32 regpair;
 581                         int reg, hreg;
 582
 583                         regpair = (guint32)(gssize)(list->data);
 584                         hreg = regpair >> 24;
 585                         reg = regpair & 0xffffff;
 586
 587                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 588
 589                         list = g_slist_next (list);
 590                 }
 591                 break;
 592         }
 593         case OP_BR:
 594         case OP_CALL_HANDLER:
 595                 printf (" [B%d]", ins->inst_target_bb->block_num);
 596                 break;
 597         case OP_IBNE_UN:
 598         case OP_IBEQ:
 599         case OP_IBLT:
 600         case OP_IBLT_UN:
 601         case OP_IBGT:
 602         case OP_IBGT_UN:
 603         case OP_IBGE:
 604         case OP_IBGE_UN:
 605         case OP_IBLE:
 606         case OP_IBLE_UN:
 607         case OP_LBNE_UN:
 608         case OP_LBEQ:
 609         case OP_LBLT:
 610         case OP_LBLT_UN:
 611         case OP_LBGT:
 612         case OP_LBGT_UN:
 613         case OP_LBGE:
 614         case OP_LBGE_UN:
 615         case OP_LBLE:
 616         case OP_LBLE_UN:
 617                 if (!ins->inst_false_bb)
 618                         printf (" [B%d]", ins->inst_true_bb->block_num);
 619                 else
 620                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 621                 break;
 622         case OP_LIVERANGE_START:
 623         case OP_LIVERANGE_END:
 624         case OP_GC_LIVENESS_DEF:
 625         case OP_GC_LIVENESS_USE:
 626                 printf (" R%d", (int)ins->inst_c1);
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         if (spec [MONO_INST_CLOB])
 633                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 634         printf ("\n");
 635 }
 636
 637 static void
 638 print_regtrack (RegTrack *t, int num)
 639 {
 640         int i;
 641         char buf [32];
 642         const char *r;
 643
 644         for (i = 0; i < num; ++i) {
 645                 if (!t [i].born_in)
 646                         continue;
 647                 if (i >= MONO_MAX_IREGS) {
 648                         g_snprintf (buf, sizeof(buf), "R%d", i);
 649                         r = buf;
 650                 } else
 651                         r = mono_arch_regname (i);
 652                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 653         }
 654 }
 655 #else
 656 void
 657 mono_print_ins_index (int i, MonoInst *ins)
 658 {
 659 }
 660 #endif /* DISABLE_LOGGING */
 661
 662 void
 663 mono_print_ins (MonoInst *ins)
 664 {
 665         mono_print_ins_index (-1, ins);
 666 }
 667
 668 static inline void
 669 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 670 {
 671         /*
 672          * If this function is called multiple times, the new instructions are inserted
 673          * in the proper order.
 674          */
 675         mono_bblock_insert_before_ins (bb, ins, to_insert);
 676 }
 677
 678 static inline void
 679 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 680 {
 681         /*
 682          * If this function is called multiple times, the new instructions are inserted in
 683          * proper order.
 684          */
 685         mono_bblock_insert_after_ins (bb, *last, to_insert);
 686
 687         *last = to_insert;
 688 }
 689
 690 static inline int
 691 get_vreg_bank (MonoCompile *cfg, int reg, int bank)
 692 {
 693         if (vreg_is_ref (cfg, reg))
 694                 return MONO_REG_INT_REF;
 695         else if (vreg_is_mp (cfg, reg))
 696                 return MONO_REG_INT_MP;
 697         else
 698                 return bank;
 699 }
 700
 701 /*
 702  * Force the spilling of the variable in the symbolic register 'reg', and free
 703  * the hreg it was assigned to.
 704  */
 705 static void
 706 spill_vreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 707 {
 708         MonoInst *load;
 709         int i, sel, spill;
 710         int *symbolic;
 711         MonoRegState *rs = cfg->rs;
 712
 713         symbolic = rs->symbolic [bank];
 714         sel = rs->vassign [reg];
 715
 716         /* the vreg we need to spill lives in another logical reg bank */
 717         bank = translate_bank (cfg->rs, bank, sel);
 718
 719         /*i = rs->isymbolic [sel];
 720         g_assert (i == reg);*/
 721         i = reg;
 722         spill = ++cfg->spill_count;
 723         rs->vassign [i] = -spill - 1;
 724         if (G_UNLIKELY (bank))
 725                 mono_regstate_free_general (rs, sel, bank);
 726         else
 727                 mono_regstate_free_int (rs, sel);
 728         /* we need to create a spill var and insert a load to sel after the current instruction */
 729         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 730         load->dreg = sel;
 731         load->inst_basereg = cfg->frame_reg;
 732         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
 733         insert_after_ins (bb, ins, last, load);
 734         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 735         if (G_UNLIKELY (bank))
 736                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 737         else
 738                 i = mono_regstate_alloc_int (rs, regmask (sel));
 739         g_assert (i == sel);
 740
 741         if (G_UNLIKELY (bank))
 742                 mono_regstate_free_general (rs, sel, bank);
 743         else
 744                 mono_regstate_free_int (rs, sel);
 745 }
 746
 747 /* This isn't defined on older glib versions and on some platforms */
 748 #ifndef G_GUINT64_FORMAT
 749 #define G_GUINT64_FORMAT "ul"
 750 #endif
 751
 752 static int
 753 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 754 {
 755         MonoInst *load;
 756         int i, sel, spill, num_sregs;
 757         int sregs [MONO_MAX_SRC_REGS];
 758         int *symbolic;
 759         MonoRegState *rs = cfg->rs;
 760
 761         symbolic = rs->symbolic [bank];
 762
 763         g_assert (bank < MONO_NUM_REGBANKS);
 764
 765         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
 766         /* exclude the registers in the current instruction */
 767         num_sregs = mono_inst_get_src_registers (ins, sregs);
 768         for (i = 0; i < num_sregs; ++i) {
 769                 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
 770                         if (is_soft_reg (sregs [i], bank))
 771                                 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
 772                         else
 773                                 regmask &= ~ (regmask (sregs [i]));
 774                         DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
 775                 }
 776         }
 777         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 778                 regmask &= ~ (regmask (ins->dreg));
 779                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 780         }
 781
 782         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 783         g_assert (regmask); /* need at least a register we can free */
 784         sel = 0;
 785         /* we should track prev_use and spill the register that's farther */
 786         if (G_UNLIKELY (bank)) {
 787                 for (i = 0; i < regbank_size [bank]; ++i) {
 788                         if (regmask & (regmask (i))) {
 789                                 sel = i;
 790
 791                                 /* the vreg we need to load lives in another logical bank */
 792                                 bank = translate_bank (cfg->rs, bank, sel);
 793
 794                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 795                                 break;
 796                         }
 797                 }
 798
 799                 i = rs->symbolic [bank] [sel];
 800                 spill = ++cfg->spill_count;
 801                 rs->vassign [i] = -spill - 1;
 802                 mono_regstate_free_general (rs, sel, bank);
 803         }
 804         else {
 805                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 806                         if (regmask & (regmask (i))) {
 807                                 sel = i;
 808                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 809                                 break;
 810                         }
 811                 }
 812
 813                 i = rs->isymbolic [sel];
 814                 spill = ++cfg->spill_count;
 815                 rs->vassign [i] = -spill - 1;
 816                 mono_regstate_free_int (rs, sel);
 817         }
 818
 819         /* we need to create a spill var and insert a load to sel after the current instruction */
 820         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 821         load->dreg = sel;
 822         load->inst_basereg = cfg->frame_reg;
 823         load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
 824         insert_after_ins (bb, ins, last, load);
 825         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 826         if (G_UNLIKELY (bank))
 827                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 828         else
 829                 i = mono_regstate_alloc_int (rs, regmask (sel));
 830         g_assert (i == sel);
 831
 832         return sel;
 833 }
 834
 835 /*
 836  * free_up_hreg:
 837  *
 838  *   Free up the hreg HREG by spilling the vreg allocated to it.
 839  */
 840 static void
 841 free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 842 {
 843         if (G_UNLIKELY (bank)) {
 844                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 845                         bank = translate_bank (cfg->rs, bank, hreg);
 846                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 847                         spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 848                 }
 849         }
 850         else {
 851                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 852                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 853                         spill_vreg (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 854                 }
 855         }
 856 }
 857
 858 static MonoInst*
 859 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 860 {
 861         MonoInst *copy;
 862
 863         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 864
 865         copy->dreg = dest;
 866         copy->sreg1 = src;
 867         copy->cil_code = ip;
 868         if (ins) {
 869                 mono_bblock_insert_after_ins (bb, ins, copy);
 870                 *last = copy;
 871         }
 872         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 873         return copy;
 874 }
 875
 876 static inline const char*
 877 regbank_to_string (int bank)
 878 {
 879         if (bank == MONO_REG_INT_REF)
 880                 return "REF ";
 881         else if (bank == MONO_REG_INT_MP)
 882                 return "MP ";
 883         else
 884                 return "";
 885 }
 886
 887 static void
 888 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
 889 {
 890         MonoInst *store, *def;
 891
 892         bank = get_vreg_bank (cfg, prev_reg, bank);
 893
 894         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 895         store->sreg1 = reg;
 896         store->inst_destbasereg = cfg->frame_reg;
 897         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 898         if (ins) {
 899                 mono_bblock_insert_after_ins (bb, ins, store);
 900                 *last = store;
 901         } else if (insert_before) {
 902                 insert_before_ins (bb, insert_before, store);
 903         } else {
 904                 g_assert_not_reached ();
 905         }
 906         DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 907
 908         if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
 909                 g_assert (prev_reg != -1);
 910                 MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
 911                 def->inst_c0 = spill;
 912                 def->inst_c1 = bank;
 913                 mono_bblock_insert_after_ins (bb, store, def);
 914                 *last = def;
 915         }
 916 }
 917
 918 /* flags used in reginfo->flags */
 919 enum {
 920         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 921         MONO_FP_NEEDS_SPILL                     = regmask (1),
 922         MONO_FP_NEEDS_LOAD                      = regmask (2)
 923 };
 924
 925 static inline int
 926 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 927 {
 928         int val;
 929
 930         if (info && info->preferred_mask) {
 931                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 932                 if (val >= 0) {
 933                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 934                         return val;
 935                 }
 936         }
 937
 938         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 939         if (val < 0)
 940                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 941
 942         return val;
 943 }
 944
 945 static inline int
 946 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 947 {
 948         int val;
 949
 950         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 951
 952         if (val < 0)
 953                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 954
 955         return val;
 956 }
 957
 958 static inline int
 959 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 960 {
 961         if (G_UNLIKELY (bank))
 962                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 963         else
 964                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 965 }
 966
 967 static inline void
 968 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 969 {
 970         if (G_UNLIKELY (bank)) {
 971                 int mirrored_bank;
 972
 973                 g_assert (reg >= regbank_size [bank]);
 974                 g_assert (hreg < regbank_size [bank]);
 975                 g_assert (! is_global_freg (hreg));
 976
 977                 rs->vassign [reg] = hreg;
 978                 rs->symbolic [bank] [hreg] = reg;
 979                 rs->free_mask [bank] &= ~ (regmask (hreg));
 980
 981                 mirrored_bank = get_mirrored_bank (bank);
 982                 if (mirrored_bank == -1)
 983                         return;
 984
 985                 /* Make sure the other logical reg bank that this bank shares
 986                  * a single hard reg bank knows that this hard reg is not free.
 987                  */
 988                 rs->free_mask [mirrored_bank] = rs->free_mask [bank];
 989
 990                 /* Mark the other logical bank that the this bank shares
 991                  * a single hard reg bank with as mirrored.
 992                  */
 993                 rs->symbolic [mirrored_bank] [hreg] = MONO_ARCH_BANK_MIRRORED;
 994
 995         }
 996         else {
 997                 g_assert (reg >= MONO_MAX_IREGS);
 998                 g_assert (hreg < MONO_MAX_IREGS);
 999 #ifndef TARGET_ARM
1000                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
1001                 g_assert (! is_global_ireg (hreg));
1002 #endif
1003
1004                 rs->vassign [reg] = hreg;
1005                 rs->isymbolic [hreg] = reg;
1006                 rs->ifree_mask &= ~ (regmask (hreg));
1007         }
1008 }
1009
1010 static inline regmask_t
1011 get_callee_mask (const char spec)
1012 {
1013         if (G_UNLIKELY (reg_bank (spec)))
1014                 return regbank_callee_regs [reg_bank (spec)];
1015         return MONO_ARCH_CALLEE_REGS;
1016 }
1017
1018 static gint8 desc_to_fixed_reg [256];
1019 static gboolean desc_to_fixed_reg_inited = FALSE;
1020
1021 #ifndef DISABLE_JIT
1022
1023 /*
1024  * Local register allocation.
1025  * We first scan the list of instructions and we save the liveness info of
1026  * each register (when the register is first used, when it's value is set etc.).
1027  * We also reverse the list of instructions because assigning registers backwards allows
1028  * for more tricks to be used.
1029  */
1030 void
1031 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1032 {
1033         MonoInst *ins, *prev, *last;
1034         MonoInst **tmp;
1035         MonoRegState *rs = cfg->rs;
1036         int i, j, val, max;
1037         RegTrack *reginfo;
1038         const char *spec;
1039         unsigned char spec_src1, spec_dest;
1040         int bank = 0;
1041 #if MONO_ARCH_USE_FPSTACK
1042         gboolean has_fp = FALSE;
1043         int fpstack [8];
1044         int sp = 0;
1045 #endif
1046         int num_sregs;
1047         int sregs [MONO_MAX_SRC_REGS];
1048
1049         if (!bb->code)
1050                 return;
1051
1052         if (!desc_to_fixed_reg_inited) {
1053                 for (i = 0; i < 256; ++i)
1054                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
1055                 desc_to_fixed_reg_inited = TRUE;
1056
1057                 /* Validate the cpu description against the info in mini-ops.h */
1058 #if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
1059                 for (i = OP_LOAD; i < OP_LAST; ++i) {
1060                         const char *ispec;
1061
1062                         spec = ins_get_spec (i);
1063                         ispec = INS_INFO (i);
1064
1065                         if ((spec [MONO_INST_DEST] && (ispec [MONO_INST_DEST] == ' ')))
1066                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1067                         if ((spec [MONO_INST_SRC1] && (ispec [MONO_INST_SRC1] == ' ')))
1068                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1069                         if ((spec [MONO_INST_SRC2] && (ispec [MONO_INST_SRC2] == ' ')))
1070                                 printf ("Instruction metadata for %s inconsistent.\n", mono_inst_name (i));
1071                 }
1072 #endif
1073         }
1074
1075         rs->next_vreg = bb->max_vreg;
1076         mono_regstate_assign (rs);
1077
1078         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
1079         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
1080                 rs->free_mask [i] = regbank_callee_regs [i];
1081
1082         max = rs->next_vreg;
1083
1084         if (cfg->reginfo && cfg->reginfo_len < max)
1085                 cfg->reginfo = NULL;
1086
1087         reginfo = cfg->reginfo;
1088         if (!reginfo) {
1089                 cfg->reginfo_len = MAX (1024, max * 2);
1090                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
1091         }
1092         else
1093                 g_assert (cfg->reginfo_len >= rs->next_vreg);
1094
1095         if (cfg->verbose_level > 1) {
1096                 /* print_regtrack reads the info of all variables */
1097                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
1098         }
1099
1100         /*
1101          * For large methods, next_vreg can be very large, so g_malloc0 time can
1102          * be prohibitive. So we manually init the reginfo entries used by the
1103          * bblock.
1104          */
1105         for (ins = bb->code; ins; ins = ins->next) {
1106                 spec = ins_get_spec (ins->opcode);
1107
1108                 if ((ins->dreg != -1) && (ins->dreg < max)) {
1109                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
1110 #if SIZEOF_REGISTER == 4
1111                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
1112                                 /**
1113                                  * In the new IR, the two vregs of the regpair do not alias the
1114                                  * original long vreg. shift the vreg here so the rest of the
1115                                  * allocator doesn't have to care about it.
1116                                  */
1117                                 ins->dreg ++;
1118                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
1119                         }
1120 #endif
1121                 }
1122
1123                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1124                 for (j = 0; j < num_sregs; ++j) {
1125                         g_assert (sregs [j] != -1);
1126                         if (sregs [j] < max) {
1127                                 memset (&reginfo [sregs [j]], 0, sizeof (RegTrack));
1128 #if SIZEOF_REGISTER == 4
1129                                 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1130                                         sregs [j]++;
1131                                         memset (&reginfo [sregs [j] + 1], 0, sizeof (RegTrack));
1132                                 }
1133 #endif
1134                         }
1135                 }
1136                 mono_inst_set_src_registers (ins, sregs);
1137         }
1138
1139         /*if (cfg->opt & MONO_OPT_COPYPROP)
1140                 local_copy_prop (cfg, ins);*/
1141
1142         i = 1;
1143         DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
1144         /* forward pass on the instructions to collect register liveness info */
1145         MONO_BB_FOR_EACH_INS (bb, ins) {
1146                 spec = ins_get_spec (ins->opcode);
1147                 spec_dest = spec [MONO_INST_DEST];
1148
1149                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1150                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1151                 }
1152
1153                 DEBUG (mono_print_ins_index (i, ins));
1154
1155                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1156
1157 #if MONO_ARCH_USE_FPSTACK
1158                 if (dreg_is_fp (spec)) {
1159                         has_fp = TRUE;
1160                 } else {
1161                         for (j = 0; j < num_sregs; ++j) {
1162                                 if (sreg_is_fp (j, spec))
1163                                         has_fp = TRUE;
1164                         }
1165                 }
1166 #endif
1167
1168                 for (j = 0; j < num_sregs; ++j) {
1169                         int sreg = sregs [j];
1170                         int sreg_spec = spec [MONO_INST_SRC1 + j];
1171                         if (sreg_spec) {
1172                                 bank = sreg_bank (j, spec);
1173                                 g_assert (sreg != -1);
1174                                 if (is_soft_reg (sreg, bank))
1175                                         /* This means the vreg is not local to this bb */
1176                                         g_assert (reginfo [sreg].born_in > 0);
1177                                 rs->vassign [sreg] = -1;
1178                                 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1179                                 //reginfo [ins->sreg2].last_use = i;
1180                                 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1181                                         /* The virtual register is allocated sequentially */
1182                                         rs->vassign [sreg + 1] = -1;
1183                                         //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1184                                         //reginfo [ins->sreg2 + 1].last_use = i;
1185                                         if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1186                                                 reginfo [sreg + 1].born_in = i;
1187                                 }
1188                         } else {
1189                                 sregs [j] = -1;
1190                         }
1191                 }
1192                 mono_inst_set_src_registers (ins, sregs);
1193
1194                 if (spec_dest) {
1195                         int dest_dreg;
1196
1197                         bank = dreg_bank (spec);
1198                         if (spec_dest != 'b') /* it's not just a base register */
1199                                 reginfo [ins->dreg].killed_in = i;
1200                         g_assert (ins->dreg != -1);
1201                         rs->vassign [ins->dreg] = -1;
1202                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1203                         //reginfo [ins->dreg].last_use = i;
1204                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1205                                 reginfo [ins->dreg].born_in = i;
1206
1207                         dest_dreg = desc_to_fixed_reg [spec_dest];
1208                         if (dest_dreg != -1)
1209                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1210
1211 #ifdef MONO_ARCH_INST_FIXED_MASK
1212                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1213 #endif
1214
1215                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1216                                 /* The virtual register is allocated sequentially */
1217                                 rs->vassign [ins->dreg + 1] = -1;
1218                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1219                                 //reginfo [ins->dreg + 1].last_use = i;
1220                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1221                                         reginfo [ins->dreg + 1].born_in = i;
1222                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1223                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1224                         }
1225                 } else {
1226                         ins->dreg = -1;
1227                 }
1228
1229                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1230                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1231
1232                         MonoCallInst *call = (MonoCallInst*)ins;
1233                         GSList *list;
1234
1235                         list = call->out_ireg_args;
1236                         if (list) {
1237                                 while (list) {
1238                                         guint32 regpair;
1239                                         int reg, hreg;
1240
1241                                         regpair = (guint32)(gssize)(list->data);
1242                                         hreg = regpair >> 24;
1243                                         reg = regpair & 0xffffff;
1244
1245                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1246                                         //reginfo [reg].last_use = i;
1247
1248                                         list = g_slist_next (list);
1249                                 }
1250                         }
1251
1252                         list = call->out_freg_args;
1253                         if (list) {
1254                                 while (list) {
1255                                         guint32 regpair;
1256                                         int reg, hreg;
1257
1258                                         regpair = (guint32)(gssize)(list->data);
1259                                         hreg = regpair >> 24;
1260                                         reg = regpair & 0xffffff;
1261
1262                                         list = g_slist_next (list);
1263                                 }
1264                         }
1265                 }
1266
1267                 ++i;
1268         }
1269
1270         tmp = &last;
1271
1272         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1273         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1274                 int prev_dreg, clob_dreg;
1275                 int dest_dreg, clob_reg;
1276                 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1277                 int dreg_high, sreg1_high;
1278                 regmask_t dreg_mask, mask;
1279                 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1280                 regmask_t dreg_fixed_mask;
1281                 const unsigned char *ip;
1282                 --i;
1283                 spec = ins_get_spec (ins->opcode);
1284                 spec_src1 = spec [MONO_INST_SRC1];
1285                 spec_dest = spec [MONO_INST_DEST];
1286                 prev_dreg = -1;
1287                 clob_dreg = -1;
1288                 clob_reg = -1;
1289                 dest_dreg = -1;
1290                 dreg_high = -1;
1291                 sreg1_high = -1;
1292                 dreg_mask = get_callee_mask (spec_dest);
1293                 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1294                         prev_sregs [j] = -1;
1295                         sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1296                         dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1297 #ifdef MONO_ARCH_INST_FIXED_MASK
1298                         sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1299 #else
1300                         sreg_fixed_masks [j] = 0;
1301 #endif
1302                 }
1303
1304                 DEBUG (printf ("processing:"));
1305                 DEBUG (mono_print_ins_index (i, ins));
1306
1307                 ip = ins->cil_code;
1308
1309                 last = ins;
1310
1311                 /*
1312                  * FIXED REGS
1313                  */
1314                 dest_dreg = desc_to_fixed_reg [spec_dest];
1315                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1316                 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1317
1318 #ifdef MONO_ARCH_INST_FIXED_MASK
1319                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1320 #else
1321                 dreg_fixed_mask = 0;
1322 #endif
1323
1324                 num_sregs = mono_inst_get_src_registers (ins, sregs);
1325
1326                 /*
1327                  * TRACK FIXED SREG2, 3, ...
1328                  */
1329                 for (j = 1; j < num_sregs; ++j) {
1330                         int sreg = sregs [j];
1331                         int dest_sreg = dest_sregs [j];
1332
1333                         if (dest_sreg == -1)
1334                                 continue;
1335
1336                         if (j == 2) {
1337                                 int k;
1338
1339                                 /*
1340                                  * CAS.
1341                                  * We need to special case this, since on x86, there are only 3
1342                                  * free registers, and the code below assigns one of them to
1343                                  * sreg, so we can run out of registers when trying to assign
1344                                  * dreg. Instead, we just set up the register masks, and let the
1345                                  * normal sreg2 assignment code handle this. It would be nice to
1346                                  * do this for all the fixed reg cases too, but there is too much
1347                                  * risk of breakage.
1348                                  */
1349
1350                                 /* Make sure sreg will be assigned to dest_sreg, and the other sregs won't */
1351                                 sreg_masks [j] = regmask (dest_sreg);
1352                                 for (k = 0; k < num_sregs; ++k) {
1353                                         if (k != j)
1354                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1355                                 }
1356
1357                                 /*
1358                                  * Spill sreg1/2 if they are assigned to dest_sreg.
1359                                  */
1360                                 for (k = 0; k < num_sregs; ++k) {
1361                                         if (k != j && is_soft_reg (sregs [k], 0) && rs->vassign [sregs [k]] == dest_sreg)
1362                                                 free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1363                                 }
1364
1365                                 /*
1366                                  * We can also run out of registers while processing sreg2 if sreg3 is
1367                                  * assigned to another hreg, so spill sreg3 now.
1368                                  */
1369                                 if (is_soft_reg (sreg, 0) && rs->vassign [sreg] >= 0 && rs->vassign [sreg] != dest_sreg) {
1370                                         spill_vreg (cfg, bb, tmp, ins, sreg, 0);
1371                                 }
1372                                 continue;
1373                         }
1374
1375                         if (rs->ifree_mask & (regmask (dest_sreg))) {
1376                                 if (is_global_ireg (sreg)) {
1377                                         int k;
1378                                         /* Argument already in hard reg, need to copy */
1379                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1380                                         insert_before_ins (bb, ins, copy);
1381                                         for (k = 0; k < num_sregs; ++k) {
1382                                                 if (k != j)
1383                                                         sreg_masks [k] &= ~ (regmask (dest_sreg));
1384                                         }
1385                                 } else {
1386                                         val = rs->vassign [sreg];
1387                                         if (val == -1) {
1388                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1389                                                 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1390                                         } else if (val < -1) {
1391                                                 /* FIXME: */
1392                                                 g_assert_not_reached ();
1393                                         } else {
1394                                                 /* Argument already in hard reg, need to copy */
1395                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1396                                                 int k;
1397
1398                                                 insert_before_ins (bb, ins, copy);
1399                                                 for (k = 0; k < num_sregs; ++k) {
1400                                                         if (k != j)
1401                                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1402                                                 }
1403                                                 /*
1404                                                  * Prevent the dreg from being allocate to dest_sreg
1405                                                  * too, since it could force sreg1 to be allocated to
1406                                                  * the same reg on x86.
1407                                                  */
1408                                                 dreg_mask &= ~ (regmask (dest_sreg));
1409                                         }
1410                                 }
1411                         } else {
1412                                 gboolean need_spill = TRUE;
1413                                 gboolean need_assign = TRUE;
1414                                 int k;
1415
1416                                 dreg_mask &= ~ (regmask (dest_sreg));
1417                                 for (k = 0; k < num_sregs; ++k) {
1418                                         if (k != j)
1419                                                 sreg_masks [k] &= ~ (regmask (dest_sreg));
1420                                 }
1421
1422                                 /*
1423                                  * First check if dreg is assigned to dest_sreg2, since we
1424                                  * can't spill a dreg.
1425                                  */
1426                                 if (spec [MONO_INST_DEST])
1427                                         val = rs->vassign [ins->dreg];
1428                                 else
1429                                         val = -1;
1430                                 if (val == dest_sreg && ins->dreg != sreg) {
1431                                         /*
1432                                          * the destination register is already assigned to
1433                                          * dest_sreg2: we need to allocate another register for it
1434                                          * and then copy from this to dest_sreg2.
1435                                          */
1436                                         int new_dest;
1437                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1438                                         g_assert (new_dest >= 0);
1439                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1440
1441                                         prev_dreg = ins->dreg;
1442                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1443                                         clob_dreg = ins->dreg;
1444                                         create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1445                                         mono_regstate_free_int (rs, dest_sreg);
1446                                         need_spill = FALSE;
1447                                 }
1448
1449                                 if (is_global_ireg (sreg)) {
1450                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1451                                         insert_before_ins (bb, ins, copy);
1452                                         need_assign = FALSE;
1453                                 }
1454                                 else {
1455                                         val = rs->vassign [sreg];
1456                                         if (val == dest_sreg) {
1457                                                 /* sreg2 is already assigned to the correct register */
1458                                                 need_spill = FALSE;
1459                                         } else if (val < -1) {
1460                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1461                                         } else if (val >= 0) {
1462                                                 /* sreg2 already assigned to another register */
1463                                                 /*
1464                                                  * We couldn't emit a copy from val to dest_sreg2, because
1465                                                  * val might be spilled later while processing this
1466                                                  * instruction. So we spill sreg2 so it can be allocated to
1467                                                  * dest_sreg2.
1468                                                  */
1469                                                 free_up_hreg (cfg, bb, tmp, ins, val, 0);
1470                                         }
1471                                 }
1472
1473                                 if (need_spill) {
1474                                         free_up_hreg (cfg, bb, tmp, ins, dest_sreg, 0);
1475                                 }
1476
1477                                 if (need_assign) {
1478                                         if (rs->vassign [sreg] < -1) {
1479                                                 int spill;
1480
1481                                                 /* Need to emit a spill store */
1482                                                 spill = - rs->vassign [sreg] - 1;
1483                                                 create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
1484                                         }
1485                                         /* force-set sreg2 */
1486                                         assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1487                                 }
1488                         }
1489                         sregs [j] = dest_sreg;
1490                 }
1491                 mono_inst_set_src_registers (ins, sregs);
1492
1493                 /*
1494                  * TRACK DREG
1495                  */
1496                 bank = dreg_bank (spec);
1497                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1498                         prev_dreg = ins->dreg;
1499                 }
1500
1501                 if (spec_dest == 'b') {
1502                         /*
1503                          * The dest reg is read by the instruction, not written, so
1504                          * avoid allocating sreg1/sreg2 to the same reg.
1505                          */
1506                         if (dest_sregs [0] != -1)
1507                                 dreg_mask &= ~ (regmask (dest_sregs [0]));
1508                         for (j = 1; j < num_sregs; ++j) {
1509                                 if (dest_sregs [j] != -1)
1510                                         dreg_mask &= ~ (regmask (dest_sregs [j]));
1511                         }
1512
1513                         val = rs->vassign [ins->dreg];
1514                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1515                                 /* DREG is already allocated to a register needed for sreg1 */
1516                             spill_vreg (cfg, bb, tmp, ins, ins->dreg, 0);
1517                         }
1518                 }
1519
1520                 /*
1521                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1522                  * various complex situations.
1523                  */
1524                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1525                         guint32 dreg2, dest_dreg2;
1526
1527                         g_assert (is_soft_reg (ins->dreg, bank));
1528
1529                         if (dest_dreg != -1) {
1530                                 if (rs->vassign [ins->dreg] != dest_dreg)
1531                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, 0);
1532
1533                                 dreg2 = ins->dreg + 1;
1534                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1535                                 if (dest_dreg2 != -1) {
1536                                         if (rs->vassign [dreg2] != dest_dreg2)
1537                                                 free_up_hreg (cfg, bb, tmp, ins, dest_dreg2, 0);
1538                                 }
1539                         }
1540                 }
1541
1542                 if (dreg_fixed_mask) {
1543                         g_assert (!bank);
1544                         if (is_global_ireg (ins->dreg)) {
1545                                 /*
1546                                  * The argument is already in a hard reg, but that reg is
1547                                  * not usable by this instruction, so allocate a new one.
1548                                  */
1549                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1550                                 if (val < 0)
1551                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1552                                 mono_regstate_free_int (rs, val);
1553                                 dest_dreg = val;
1554
1555                                 /* Fall through */
1556                         }
1557                         else
1558                                 dreg_mask &= dreg_fixed_mask;
1559                 }
1560
1561                 if (is_soft_reg (ins->dreg, bank)) {
1562                         val = rs->vassign [ins->dreg];
1563
1564                         if (val < 0) {
1565                                 int spill = 0;
1566                                 if (val < -1) {
1567                                         /* the register gets spilled after this inst */
1568                                         spill = -val -1;
1569                                 }
1570                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1571                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1572                                 if (spill)
1573                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
1574                         }
1575
1576                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1577                         ins->dreg = val;
1578                 }
1579
1580                 /* Handle regpairs */
1581                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1582                         int reg2 = prev_dreg + 1;
1583
1584                         g_assert (!bank);
1585                         g_assert (prev_dreg > -1);
1586                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1587                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1588 #ifdef TARGET_X86
1589                         /* bug #80489 */
1590                         mask &= ~regmask (X86_ECX);
1591 #endif
1592                         val = rs->vassign [reg2];
1593                         if (val < 0) {
1594                                 int spill = 0;
1595                                 if (val < -1) {
1596                                         /* the register gets spilled after this inst */
1597                                         spill = -val -1;
1598                                 }
1599                                 val = mono_regstate_alloc_int (rs, mask);
1600                                 if (val < 0)
1601                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1602                                 if (spill)
1603                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
1604                         }
1605                         else {
1606                                 if (! (mask & (regmask (val)))) {
1607                                         val = mono_regstate_alloc_int (rs, mask);
1608                                         if (val < 0)
1609                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1610
1611                                         /* Reallocate hreg to the correct register */
1612                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1613
1614                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1615                                 }
1616                         }
1617
1618                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1619                         assign_reg (cfg, rs, reg2, val, bank);
1620
1621                         dreg_high = val;
1622                         ins->backend.reg3 = val;
1623
1624                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1625                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1626                                 mono_regstate_free_int (rs, val);
1627                         }
1628                 }
1629
1630                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1631                         /*
1632                          * In theory, we could free up the hreg even if the vreg is alive,
1633                          * but branches inside bblocks force us to assign the same hreg
1634                          * to a vreg every time it is encountered.
1635                          */
1636                         int dreg = rs->vassign [prev_dreg];
1637                         g_assert (dreg >= 0);
1638                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1639                         if (G_UNLIKELY (bank))
1640                                 mono_regstate_free_general (rs, dreg, bank);
1641                         else
1642                                 mono_regstate_free_int (rs, dreg);
1643                         rs->vassign [prev_dreg] = -1;
1644                 }
1645
1646                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1647                         /* this instruction only outputs to dest_dreg, need to copy */
1648                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1649                         ins->dreg = dest_dreg;
1650
1651                         if (G_UNLIKELY (bank)) {
1652                                 /* the register we need to free up may be used in another logical regbank
1653                                  * so do a translate just in case.
1654                                  */
1655                                 int translated_bank = translate_bank (cfg->rs, bank, dest_dreg);
1656                                 if (rs->symbolic [translated_bank] [dest_dreg] >= regbank_size [translated_bank])
1657                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, translated_bank);
1658                         }
1659                         else {
1660                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1661                                         free_up_hreg (cfg, bb, tmp, ins, dest_dreg, bank);
1662                         }
1663                 }
1664
1665                 if (spec_dest == 'b') {
1666                         /*
1667                          * The dest reg is read by the instruction, not written, so
1668                          * avoid allocating sreg1/sreg2 to the same reg.
1669                          */
1670                         for (j = 0; j < num_sregs; ++j)
1671                                 if (!sreg_bank (j, spec))
1672                                         sreg_masks [j] &= ~ (regmask (ins->dreg));
1673                 }
1674
1675                 /*
1676                  * TRACK CLOBBERING
1677                  */
1678                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1679                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1680                         free_up_hreg (cfg, bb, tmp, ins, clob_reg, 0);
1681                 }
1682
1683                 if (spec [MONO_INST_CLOB] == 'c') {
1684                         int j, s, dreg, dreg2, cur_bank;
1685                         guint64 clob_mask;
1686
1687                         clob_mask = MONO_ARCH_CALLEE_REGS;
1688
1689                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1690                                 /*
1691                                  * Need to avoid spilling the dreg since the dreg is not really
1692                                  * clobbered by the call.
1693                                  */
1694                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1695                                         dreg = rs->vassign [prev_dreg];
1696                                 else
1697                                         dreg = -1;
1698
1699                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1700                                         dreg2 = rs->vassign [prev_dreg + 1];
1701                                 else
1702                                         dreg2 = -1;
1703
1704                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1705                                         s = regmask (j);
1706                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1707                                                 if ((j != dreg) && (j != dreg2))
1708                                                         free_up_hreg (cfg, bb, tmp, ins, j, 0);
1709                                                 else if (rs->isymbolic [j])
1710                                                         /* The hreg is assigned to the dreg of this instruction */
1711                                                         rs->vassign [rs->isymbolic [j]] = -1;
1712                                                 mono_regstate_free_int (rs, j);
1713                                         }
1714                                 }
1715                         }
1716
1717                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1718                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1719                                         clob_mask = regbank_callee_regs [cur_bank];
1720                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1721                                                 dreg = rs->vassign [prev_dreg];
1722                                         else
1723                                                 dreg = -1;
1724
1725                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1726
1727                                                 /* we are looping though the banks in the outer loop
1728                                                  * so, we don't need to deal with mirrored hregs
1729                                                  * because we will get them in one of the other bank passes.
1730                                                  */
1731                                                 if (is_hreg_mirrored (rs, cur_bank, j))
1732                                                         continue;
1733
1734                                                 s = regmask (j);
1735                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1736                                                         if (j != dreg)
1737                                                                 free_up_hreg (cfg, bb, tmp, ins, j, cur_bank);
1738                                                         else if (rs->symbolic [cur_bank] [j])
1739                                                                 /* The hreg is assigned to the dreg of this instruction */
1740                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1741                                                         mono_regstate_free_general (rs, j, cur_bank);
1742                                                 }
1743                                         }
1744                                 }
1745                         }
1746                 }
1747
1748                 /*
1749                  * TRACK ARGUMENT REGS
1750                  */
1751                 if (spec [MONO_INST_CLOB] == 'c' && MONO_IS_CALL (ins)) {
1752                         MonoCallInst *call = (MonoCallInst*)ins;
1753                         GSList *list;
1754
1755                         /*
1756                          * This needs to be done before assigning sreg1, so sreg1 will
1757                          * not be assigned one of the argument regs.
1758                          */
1759
1760                         /*
1761                          * Assign all registers in call->out_reg_args to the proper
1762                          * argument registers.
1763                          */
1764
1765                         list = call->out_ireg_args;
1766                         if (list) {
1767                                 while (list) {
1768                                         guint32 regpair;
1769                                         int reg, hreg;
1770
1771                                         regpair = (guint32)(gssize)(list->data);
1772                                         hreg = regpair >> 24;
1773                                         reg = regpair & 0xffffff;
1774
1775                                         assign_reg (cfg, rs, reg, hreg, 0);
1776
1777                                         sreg_masks [0] &= ~(regmask (hreg));
1778
1779                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1780
1781                                         list = g_slist_next (list);
1782                                 }
1783                         }
1784
1785                         list = call->out_freg_args;
1786                         if (list) {
1787                                 while (list) {
1788                                         guint32 regpair;
1789                                         int reg, hreg;
1790
1791                                         regpair = (guint32)(gssize)(list->data);
1792                                         hreg = regpair >> 24;
1793                                         reg = regpair & 0xffffff;
1794
1795                                         assign_reg (cfg, rs, reg, hreg, 1);
1796
1797                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1798
1799                                         list = g_slist_next (list);
1800                                 }
1801                         }
1802                 }
1803
1804                 /*
1805                  * TRACK SREG1
1806                  */
1807                 bank = sreg1_bank (spec);
1808                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1809                         int sreg1 = sregs [0];
1810                         int dest_sreg1 = dest_sregs [0];
1811
1812                         g_assert (is_soft_reg (sreg1, bank));
1813
1814                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1815                         if (dest_sreg1 != -1)
1816                                 g_assert (dest_sreg1 == ins->dreg);
1817                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1818                         g_assert (val >= 0);
1819
1820                         if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1821                                 // FIXME:
1822                                 g_assert_not_reached ();
1823
1824                         assign_reg (cfg, rs, sreg1, val, bank);
1825
1826                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1827
1828                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1829                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1830                         g_assert (val >= 0);
1831
1832                         if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1833                                 // FIXME:
1834                                 g_assert_not_reached ();
1835
1836                         assign_reg (cfg, rs, sreg1 + 1, val, bank);
1837
1838                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1839
1840                         /* Skip rest of this section */
1841                         dest_sregs [0] = -1;
1842                 }
1843
1844                 if (sreg_fixed_masks [0]) {
1845                         g_assert (!bank);
1846                         if (is_global_ireg (sregs [0])) {
1847                                 /*
1848                                  * The argument is already in a hard reg, but that reg is
1849                                  * not usable by this instruction, so allocate a new one.
1850                                  */
1851                                 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1852                                 if (val < 0)
1853                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1854                                 mono_regstate_free_int (rs, val);
1855                                 dest_sregs [0] = val;
1856
1857                                 /* Fall through to the dest_sreg1 != -1 case */
1858                         }
1859                         else
1860                                 sreg_masks [0] &= sreg_fixed_masks [0];
1861                 }
1862
1863                 if (dest_sregs [0] != -1) {
1864                         sreg_masks [0] = regmask (dest_sregs [0]);
1865
1866                         if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1867                                 free_up_hreg (cfg, bb, tmp, ins, dest_sregs [0], 0);
1868                         }
1869                         if (is_global_ireg (sregs [0])) {
1870                                 /* The argument is already in a hard reg, need to copy */
1871                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1872                                 insert_before_ins (bb, ins, copy);
1873                                 sregs [0] = dest_sregs [0];
1874                         }
1875                 }
1876
1877                 if (is_soft_reg (sregs [0], bank)) {
1878                         val = rs->vassign [sregs [0]];
1879                         prev_sregs [0] = sregs [0];
1880                         if (val < 0) {
1881                                 int spill = 0;
1882                                 if (val < -1) {
1883                                         /* the register gets spilled after this inst */
1884                                         spill = -val -1;
1885                                 }
1886
1887                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1888                                         /*
1889                                          * Allocate the same hreg to sreg1 as well so the
1890                                          * peephole can get rid of the move.
1891                                          */
1892                                         sreg_masks [0] = regmask (ins->dreg);
1893                                 }
1894
1895                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1896                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1897                                         sreg_masks [0] = regmask (ins->dreg);
1898
1899                                 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], &reginfo [sregs [0]], bank);
1900                                 assign_reg (cfg, rs, sregs [0], val, bank);
1901                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1902
1903                                 if (spill) {
1904                                         /*
1905                                          * Need to insert before the instruction since it can
1906                                          * overwrite sreg1.
1907                                          */
1908                                         create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
1909                                 }
1910                         }
1911                         else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1912                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1913                                 insert_before_ins (bb, ins, copy);
1914                                 for (j = 1; j < num_sregs; ++j)
1915                                         sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1916                                 val = dest_sregs [0];
1917                         }
1918
1919                         sregs [0] = val;
1920                 }
1921                 else {
1922                         prev_sregs [0] = -1;
1923                 }
1924                 mono_inst_set_src_registers (ins, sregs);
1925
1926                 for (j = 1; j < num_sregs; ++j)
1927                         sreg_masks [j] &= ~(regmask (sregs [0]));
1928
1929                 /* Handle the case when sreg1 is a regpair but dreg is not */
1930                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1931                         int reg2 = prev_sregs [0] + 1;
1932
1933                         g_assert (!bank);
1934                         g_assert (prev_sregs [0] > -1);
1935                         g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1936                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1937                         val = rs->vassign [reg2];
1938                         if (val < 0) {
1939                                 int spill = 0;
1940                                 if (val < -1) {
1941                                         /* the register gets spilled after this inst */
1942                                         spill = -val -1;
1943                                 }
1944                                 val = mono_regstate_alloc_int (rs, mask);
1945                                 if (val < 0)
1946                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1947                                 if (spill)
1948                                         g_assert_not_reached ();
1949                         }
1950                         else {
1951                                 if (! (mask & (regmask (val)))) {
1952                                         /* The vreg is already allocated to a wrong hreg */
1953                                         /* FIXME: */
1954                                         g_assert_not_reached ();
1955 #if 0
1956                                         val = mono_regstate_alloc_int (rs, mask);
1957                                         if (val < 0)
1958                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1959
1960                                         /* Reallocate hreg to the correct register */
1961                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1962
1963                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1964 #endif
1965                                 }
1966                         }
1967
1968                         sreg1_high = val;
1969                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1970                         assign_reg (cfg, rs, reg2, val, bank);
1971                 }
1972
1973                 /* Handle dreg==sreg1 */
1974                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1975                         MonoInst *sreg2_copy = NULL;
1976                         MonoInst *copy;
1977                         int bank = reg_bank (spec_src1);
1978
1979                         if (ins->dreg == sregs [1]) {
1980                                 /*
1981                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1982                                  * register for it.
1983                                  */
1984                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1985
1986                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1987                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1988                                 prev_sregs [1] = sregs [1] = reg2;
1989
1990                                 if (G_UNLIKELY (bank))
1991                                         mono_regstate_free_general (rs, reg2, bank);
1992                                 else
1993                                         mono_regstate_free_int (rs, reg2);
1994                         }
1995
1996                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1997                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1998                                 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1999                                         /* FIXME: */
2000                                         g_assert_not_reached ();
2001
2002                                 /*
2003                                  * sreg1 and dest are already allocated to the same regpair by the
2004                                  * SREG1 allocation code.
2005                                  */
2006                                 g_assert (sregs [0] == ins->dreg);
2007                                 g_assert (dreg_high == sreg1_high);
2008                         }
2009
2010                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
2011                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
2012                         insert_before_ins (bb, ins, copy);
2013
2014                         if (sreg2_copy)
2015                                 insert_before_ins (bb, copy, sreg2_copy);
2016
2017                         /*
2018                          * Need to prevent sreg2 to be allocated to sreg1, since that
2019                          * would screw up the previous copy.
2020                          */
2021                         sreg_masks [1] &= ~ (regmask (sregs [0]));
2022                         /* we set sreg1 to dest as well */
2023                         prev_sregs [0] = sregs [0] = ins->dreg;
2024                         sreg_masks [1] &= ~ (regmask (ins->dreg));
2025                 }
2026                 mono_inst_set_src_registers (ins, sregs);
2027
2028                 /*
2029                  * TRACK SREG2, 3, ...
2030                  */
2031                 for (j = 1; j < num_sregs; ++j) {
2032                         int k;
2033
2034                         bank = sreg_bank (j, spec);
2035                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
2036                                 g_assert_not_reached ();
2037
2038                         if (dest_sregs [j] != -1 && is_global_ireg (sregs [j])) {
2039                                 /*
2040                                  * Argument already in a global hard reg, copy it to the fixed reg, without
2041                                  * allocating it to the fixed reg.
2042                                  */
2043                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [j], sregs [j], NULL, ip, 0);
2044                                 insert_before_ins (bb, ins, copy);
2045                                 sregs [j] = dest_sregs [j];
2046                         } else if (is_soft_reg (sregs [j], bank)) {
2047                                 val = rs->vassign [sregs [j]];
2048
2049                                 if (dest_sregs [j] != -1 && val >= 0 && dest_sregs [j] != val) {
2050                                         /*
2051                                          * The sreg is already allocated to a hreg, but not to the fixed
2052                                          * reg required by the instruction. Spill the sreg, so it can be
2053                                          * allocated to the fixed reg by the code below.
2054                                          */
2055                                         /* Currently, this code should only be hit for CAS */
2056                                         spill_vreg (cfg, bb, tmp, ins, sregs [j], 0);
2057                                         val = rs->vassign [sregs [j]];
2058                                 }
2059
2060                                 if (val < 0) {
2061                                         int spill = 0;
2062                                         if (val < -1) {
2063                                                 /* the register gets spilled after this inst */
2064                                                 spill = -val -1;
2065                                         }
2066                                         val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], &reginfo [sregs [j]], bank);
2067                                         assign_reg (cfg, rs, sregs [j], val, bank);
2068                                         DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
2069                                         if (spill) {
2070                                                 /*
2071                                                  * Need to insert before the instruction since it can
2072                                                  * overwrite sreg2.
2073                                                  */
2074                                                 create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
2075                                         }
2076                                 }
2077                                 sregs [j] = val;
2078                                 for (k = j + 1; k < num_sregs; ++k)
2079                                         sreg_masks [k] &= ~ (regmask (sregs [j]));
2080                         }
2081                         else {
2082                                 prev_sregs [j] = -1;
2083                         }
2084                 }
2085                 mono_inst_set_src_registers (ins, sregs);
2086
2087                 /* Sanity check */
2088                 /* Do this only for CAS for now */
2089                 for (j = 1; j < num_sregs; ++j) {
2090                         int sreg = sregs [j];
2091                         int dest_sreg = dest_sregs [j];
2092
2093                         if (j == 2 && dest_sreg != -1) {
2094                                 int k;
2095
2096                                 g_assert (sreg == dest_sreg);
2097
2098                                 for (k = 0; k < num_sregs; ++k) {
2099                                         if (k != j)
2100                                                 g_assert (sregs [k] != dest_sreg);
2101                                 }
2102                         }
2103                 }
2104
2105                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2106                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2107                         mono_regstate_free_int (rs, ins->sreg1);
2108                 }
2109                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2110                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2111                         mono_regstate_free_int (rs, ins->sreg2);
2112                 }*/
2113
2114                 DEBUG (mono_print_ins_index (i, ins));
2115         }
2116
2117         // FIXME: Set MAX_FREGS to 8
2118         // FIXME: Optimize generated code
2119 #if MONO_ARCH_USE_FPSTACK
2120         /*
2121          * Make a forward pass over the code, simulating the fp stack, making sure the
2122          * arguments required by the fp opcodes are at the top of the stack.
2123          */
2124         if (has_fp) {
2125                 MonoInst *prev = NULL;
2126                 MonoInst *fxch;
2127                 int tmp;
2128
2129                 g_assert (num_sregs <= 2);
2130
2131                 for (ins = bb->code; ins; ins = ins->next) {
2132                         spec = ins_get_spec (ins->opcode);
2133
2134                         DEBUG (printf ("processing:"));
2135                         DEBUG (mono_print_ins_index (0, ins));
2136
2137                         if (ins->opcode == OP_FMOVE) {
2138                                 /* Do it by renaming the source to the destination on the stack */
2139                                 // FIXME: Is this correct ?
2140                                 for (i = 0; i < sp; ++i)
2141                                         if (fpstack [i] == ins->sreg1)
2142                                                 fpstack [i] = ins->dreg;
2143                                 prev = ins;
2144                                 continue;
2145                         }
2146
2147                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
2148                                 /* Arg1 must be in %st(1) */
2149                                 g_assert (prev);
2150
2151                                 i = 0;
2152                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
2153                                         i ++;
2154                                 g_assert (i < sp);
2155
2156                                 if (sp - 1 - i > 0) {
2157                                         /* First move it to %st(0) */
2158                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2159
2160                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2161                                         fxch->inst_imm = sp - 1 - i;
2162
2163                                         prev->next = fxch;
2164                                         fxch->next = ins;
2165                                         prev = fxch;
2166
2167                                         tmp = fpstack [sp - 1];
2168                                         fpstack [sp - 1] = fpstack [i];
2169                                         fpstack [i] = tmp;
2170                                 }
2171
2172                                 /* Then move it to %st(1) */
2173                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
2174
2175                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2176                                 fxch->inst_imm = 1;
2177
2178                                 prev->next = fxch;
2179                                 fxch->next = ins;
2180                                 prev = fxch;
2181
2182                                 tmp = fpstack [sp - 1];
2183                                 fpstack [sp - 1] = fpstack [sp - 2];
2184                                 fpstack [sp - 2] = tmp;
2185                         }
2186
2187                         if (sreg2_is_fp (spec)) {
2188                                 g_assert (sp > 0);
2189
2190                                 if (fpstack [sp - 1] != ins->sreg2) {
2191                                         g_assert (prev);
2192
2193                                         i = 0;
2194                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
2195                                                 i ++;
2196                                         g_assert (i < sp);
2197
2198                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2199
2200                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2201                                         fxch->inst_imm = sp - 1 - i;
2202
2203                                         prev->next = fxch;
2204                                         fxch->next = ins;
2205                                         prev = fxch;
2206
2207                                         tmp = fpstack [sp - 1];
2208                                         fpstack [sp - 1] = fpstack [i];
2209                                         fpstack [i] = tmp;
2210                                 }
2211
2212                                 sp --;
2213                         }
2214
2215                         if (sreg1_is_fp (spec)) {
2216                                 g_assert (sp > 0);
2217
2218                                 if (fpstack [sp - 1] != ins->sreg1) {
2219                                         g_assert (prev);
2220
2221                                         i = 0;
2222                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
2223                                                 i ++;
2224                                         g_assert (i < sp);
2225
2226                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2227
2228                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2229                                         fxch->inst_imm = sp - 1 - i;
2230
2231                                         prev->next = fxch;
2232                                         fxch->next = ins;
2233                                         prev = fxch;
2234
2235                                         tmp = fpstack [sp - 1];
2236                                         fpstack [sp - 1] = fpstack [i];
2237                                         fpstack [i] = tmp;
2238                                 }
2239
2240                                 sp --;
2241                         }
2242
2243                         if (dreg_is_fp (spec)) {
2244                                 g_assert (sp < 8);
2245                                 fpstack [sp ++] = ins->dreg;
2246                         }
2247
2248                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2249                                 printf ("\t[");
2250                                 for (i = 0; i < sp; ++i)
2251                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2252                                 printf ("]\n");
2253                         }
2254
2255                         prev = ins;
2256                 }
2257
2258                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2259                         /* Remove remaining items from the fp stack */
2260                         /*
2261                          * These can remain for example as a result of a dead fmove like in
2262                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2263                          */
2264                         while (sp) {
2265                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2266                                 mono_add_ins_to_end (bb, ins);
2267                                 sp --;
2268                         }
2269                 }
2270         }
2271 #endif
2272 }
2273
2274 CompRelation
2275 mono_opcode_to_cond (int opcode)
2276 {
2277         switch (opcode) {
2278         case OP_CEQ:
2279         case OP_IBEQ:
2280         case OP_ICEQ:
2281         case OP_LBEQ:
2282         case OP_LCEQ:
2283         case OP_FBEQ:
2284         case OP_FCEQ:
2285         case OP_COND_EXC_EQ:
2286         case OP_COND_EXC_IEQ:
2287         case OP_CMOV_IEQ:
2288         case OP_CMOV_LEQ:
2289                 return CMP_EQ;
2290         case OP_IBNE_UN:
2291         case OP_LBNE_UN:
2292         case OP_FBNE_UN:
2293         case OP_COND_EXC_NE_UN:
2294         case OP_COND_EXC_INE_UN:
2295         case OP_CMOV_INE_UN:
2296         case OP_CMOV_LNE_UN:
2297                 return CMP_NE;
2298         case OP_IBLE:
2299         case OP_LBLE:
2300         case OP_FBLE:
2301         case OP_CMOV_ILE:
2302         case OP_CMOV_LLE:
2303                 return CMP_LE;
2304         case OP_IBGE:
2305         case OP_LBGE:
2306         case OP_FBGE:
2307         case OP_CMOV_IGE:
2308         case OP_CMOV_LGE:
2309                 return CMP_GE;
2310         case OP_CLT:
2311         case OP_IBLT:
2312         case OP_ICLT:
2313         case OP_LBLT:
2314         case OP_LCLT:
2315         case OP_FBLT:
2316         case OP_FCLT:
2317         case OP_COND_EXC_LT:
2318         case OP_COND_EXC_ILT:
2319         case OP_CMOV_ILT:
2320         case OP_CMOV_LLT:
2321                 return CMP_LT;
2322         case OP_CGT:
2323         case OP_IBGT:
2324         case OP_ICGT:
2325         case OP_LBGT:
2326         case OP_LCGT:
2327         case OP_FBGT:
2328         case OP_FCGT:
2329         case OP_COND_EXC_GT:
2330         case OP_COND_EXC_IGT:
2331         case OP_CMOV_IGT:
2332         case OP_CMOV_LGT:
2333                 return CMP_GT;
2334
2335         case OP_IBLE_UN:
2336         case OP_LBLE_UN:
2337         case OP_FBLE_UN:
2338         case OP_COND_EXC_LE_UN:
2339         case OP_COND_EXC_ILE_UN:
2340         case OP_CMOV_ILE_UN:
2341         case OP_CMOV_LLE_UN:
2342                 return CMP_LE_UN;
2343         case OP_IBGE_UN:
2344         case OP_LBGE_UN:
2345         case OP_FBGE_UN:
2346         case OP_CMOV_IGE_UN:
2347         case OP_CMOV_LGE_UN:
2348                 return CMP_GE_UN;
2349         case OP_CLT_UN:
2350         case OP_IBLT_UN:
2351         case OP_ICLT_UN:
2352         case OP_LBLT_UN:
2353         case OP_LCLT_UN:
2354         case OP_FBLT_UN:
2355         case OP_FCLT_UN:
2356         case OP_COND_EXC_LT_UN:
2357         case OP_COND_EXC_ILT_UN:
2358         case OP_CMOV_ILT_UN:
2359         case OP_CMOV_LLT_UN:
2360                 return CMP_LT_UN;
2361         case OP_CGT_UN:
2362         case OP_IBGT_UN:
2363         case OP_ICGT_UN:
2364         case OP_LBGT_UN:
2365         case OP_LCGT_UN:
2366         case OP_FCGT_UN:
2367         case OP_FBGT_UN:
2368         case OP_COND_EXC_GT_UN:
2369         case OP_COND_EXC_IGT_UN:
2370         case OP_CMOV_IGT_UN:
2371         case OP_CMOV_LGT_UN:
2372                 return CMP_GT_UN;
2373         default:
2374                 printf ("%s\n", mono_inst_name (opcode));
2375                 g_assert_not_reached ();
2376                 return 0;
2377         }
2378 }
2379
2380 CompRelation
2381 mono_negate_cond (CompRelation cond)
2382 {
2383         switch (cond) {
2384         case CMP_EQ:
2385                 return CMP_NE;
2386         case CMP_NE:
2387                 return CMP_EQ;
2388         case CMP_LE:
2389                 return CMP_GT;
2390         case CMP_GE:
2391                 return CMP_LT;
2392         case CMP_LT:
2393                 return CMP_GE;
2394         case CMP_GT:
2395                 return CMP_LE;
2396         case CMP_LE_UN:
2397                 return CMP_GT_UN;
2398         case CMP_GE_UN:
2399                 return CMP_LT_UN;
2400         case CMP_LT_UN:
2401                 return CMP_GE_UN;
2402         case CMP_GT_UN:
2403                 return CMP_LE_UN;
2404         default:
2405                 g_assert_not_reached ();
2406         }
2407 }
2408
2409 CompType
2410 mono_opcode_to_type (int opcode, int cmp_opcode)
2411 {
2412         if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2413                 return CMP_TYPE_L;
2414         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2415                 return CMP_TYPE_I;
2416         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2417                 return CMP_TYPE_I;
2418         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2419                 return CMP_TYPE_L;
2420         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2421                 return CMP_TYPE_L;
2422         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2423                 return CMP_TYPE_F;
2424         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2425                 return CMP_TYPE_F;
2426         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2427                 return CMP_TYPE_I;
2428         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2429                 switch (cmp_opcode) {
2430                 case OP_ICOMPARE:
2431                 case OP_ICOMPARE_IMM:
2432                 case OP_LCOMPARE_IMM:
2433                         return CMP_TYPE_I;
2434                 default:
2435                         return CMP_TYPE_L;
2436                 }
2437         } else {
2438                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2439                 return 0;
2440         }
2441 }
2442
2443 #endif /* DISABLE_JIT */
2444
2445 gboolean
2446 mono_is_regsize_var (MonoType *t)
2447 {
2448         if (t->byref)
2449                 return TRUE;
2450         t = mono_type_get_underlying_type (t);
2451         switch (t->type) {
2452         case MONO_TYPE_BOOLEAN:
2453         case MONO_TYPE_CHAR:
2454         case MONO_TYPE_I1:
2455         case MONO_TYPE_U1:
2456         case MONO_TYPE_I2:
2457         case MONO_TYPE_U2:
2458         case MONO_TYPE_I4:
2459         case MONO_TYPE_U4:
2460         case MONO_TYPE_I:
2461         case MONO_TYPE_U:
2462         case MONO_TYPE_PTR:
2463         case MONO_TYPE_FNPTR:
2464 #if SIZEOF_REGISTER == 8
2465         case MONO_TYPE_I8:
2466         case MONO_TYPE_U8:
2467 #endif
2468                 return TRUE;
2469         case MONO_TYPE_OBJECT:
2470         case MONO_TYPE_STRING:
2471         case MONO_TYPE_CLASS:
2472         case MONO_TYPE_SZARRAY:
2473         case MONO_TYPE_ARRAY:
2474                 return TRUE;
2475         case MONO_TYPE_GENERICINST:
2476                 if (!mono_type_generic_inst_is_valuetype (t))
2477                         return TRUE;
2478                 return FALSE;
2479         case MONO_TYPE_VALUETYPE:
2480                 return FALSE;
2481         }
2482         return FALSE;
2483 }
2484
2485 #ifndef DISABLE_JIT
2486
2487 /*
2488  * mono_peephole_ins:
2489  *
2490  *   Perform some architecture independent peephole optimizations.
2491  */
2492 void
2493 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2494 {
2495         MonoInst *last_ins = ins->prev;
2496
2497         switch (ins->opcode) {
2498         case OP_MUL_IMM:
2499                 /* remove unnecessary multiplication with 1 */
2500                 if (ins->inst_imm == 1) {
2501                         if (ins->dreg != ins->sreg1)
2502                                 ins->opcode = OP_MOVE;
2503                         else
2504                                 MONO_DELETE_INS (bb, ins);
2505                 }
2506                 break;
2507         case OP_LOAD_MEMBASE:
2508         case OP_LOADI4_MEMBASE:
2509                 /*
2510                  * Note: if reg1 = reg2 the load op is removed
2511                  *
2512                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2513                  * OP_LOAD_MEMBASE offset(basereg), reg2
2514                  * -->
2515                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2516                  * OP_MOVE reg1, reg2
2517                  */
2518                 if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
2519                         last_ins = last_ins->prev;
2520                 if (last_ins &&
2521                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2522                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2523                         ins->inst_basereg == last_ins->inst_destbasereg &&
2524                         ins->inst_offset == last_ins->inst_offset) {
2525                         if (ins->dreg == last_ins->sreg1) {
2526                                 MONO_DELETE_INS (bb, ins);
2527                                 break;
2528                         } else {
2529                                 ins->opcode = OP_MOVE;
2530                                 ins->sreg1 = last_ins->sreg1;
2531                         }
2532
2533                         /*
2534                          * Note: reg1 must be different from the basereg in the second load
2535                          * Note: if reg1 = reg2 is equal then second load is removed
2536                          *
2537                          * OP_LOAD_MEMBASE offset(basereg), reg1
2538                          * OP_LOAD_MEMBASE offset(basereg), reg2
2539                          * -->
2540                          * OP_LOAD_MEMBASE offset(basereg), reg1
2541                          * OP_MOVE reg1, reg2
2542                          */
2543                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2544                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2545                           ins->inst_basereg != last_ins->dreg &&
2546                           ins->inst_basereg == last_ins->inst_basereg &&
2547                           ins->inst_offset == last_ins->inst_offset) {
2548
2549                         if (ins->dreg == last_ins->dreg) {
2550                                 MONO_DELETE_INS (bb, ins);
2551                         } else {
2552                                 ins->opcode = OP_MOVE;
2553                                 ins->sreg1 = last_ins->dreg;
2554                         }
2555
2556                         //g_assert_not_reached ();
2557
2558 #if 0
2559                         /*
2560                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2561                          * OP_LOAD_MEMBASE offset(basereg), reg
2562                          * -->
2563                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2564                          * OP_ICONST reg, imm
2565                          */
2566                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2567                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2568                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2569                                    ins->inst_offset == last_ins->inst_offset) {
2570                         ins->opcode = OP_ICONST;
2571                         ins->inst_c0 = last_ins->inst_imm;
2572                         g_assert_not_reached (); // check this rule
2573 #endif
2574                 }
2575                 break;
2576         case OP_LOADI1_MEMBASE:
2577         case OP_LOADU1_MEMBASE:
2578                 /*
2579                  * Note: if reg1 = reg2 the load op is removed
2580                  *
2581                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2582                  * OP_LOAD_MEMBASE offset(basereg), reg2
2583                  * -->
2584                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2585                  * OP_MOVE reg1, reg2
2586                  */
2587                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2588                         ins->inst_basereg == last_ins->inst_destbasereg &&
2589                         ins->inst_offset == last_ins->inst_offset) {
2590                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2591                         ins->sreg1 = last_ins->sreg1;
2592                 }
2593                 break;
2594         case OP_LOADI2_MEMBASE:
2595         case OP_LOADU2_MEMBASE:
2596                 /*
2597                  * Note: if reg1 = reg2 the load op is removed
2598                  *
2599                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2600                  * OP_LOAD_MEMBASE offset(basereg), reg2
2601                  * -->
2602                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2603                  * OP_MOVE reg1, reg2
2604                  */
2605                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2606                         ins->inst_basereg == last_ins->inst_destbasereg &&
2607                         ins->inst_offset == last_ins->inst_offset) {
2608 #if SIZEOF_REGISTER == 8
2609                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2610 #else
2611                         /* The definition of OP_PCONV_TO_U2 is wrong */
2612                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2613 #endif
2614                         ins->sreg1 = last_ins->sreg1;
2615                 }
2616                 break;
2617         case OP_MOVE:
2618         case OP_FMOVE:
2619                 /*
2620                  * Removes:
2621                  *
2622                  * OP_MOVE reg, reg
2623                  */
2624                 if (ins->dreg == ins->sreg1) {
2625                         MONO_DELETE_INS (bb, ins);
2626                         break;
2627                 }
2628                 /*
2629                  * Removes:
2630                  *
2631                  * OP_MOVE sreg, dreg
2632                  * OP_MOVE dreg, sreg
2633                  */
2634                 if (last_ins && last_ins->opcode == ins->opcode &&
2635                         ins->sreg1 == last_ins->dreg &&
2636                         ins->dreg == last_ins->sreg1) {
2637                         MONO_DELETE_INS (bb, ins);
2638                 }
2639                 break;
2640         case OP_NOP:
2641                 MONO_DELETE_INS (bb, ins);
2642                 break;
2643         }
2644 }
2645
2646 #endif /* DISABLE_JIT */