2 * mini-codegen.c: Arch independent code generation functionality
4 * (C) 2003 Ximian, Inc.
13 #include <mono/metadata/appdomain.h>
14 #include <mono/metadata/debug-helpers.h>
15 #include <mono/metadata/threads.h>
16 #include <mono/metadata/profiler-private.h>
17 #include <mono/utils/mono-math.h>
21 #include "mini-arch.h"
23 #ifndef MONO_MAX_XREGS
25 #define MONO_MAX_XREGS 0
26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
27 #define MONO_ARCH_CALLEE_XREGS 0
31 * Every hardware register belongs to a register type or register bank. bank 0
32 * contains the int registers, bank 1 contains the fp registers.
33 * int registers are used 99% of the time, so they are special cased in a lot of
37 static const int regbank_size [] = {
43 static const int regbank_load_ops [] = {
49 static const int regbank_store_ops [] = {
51 OP_STORER8_MEMBASE_REG,
55 static const int regbank_move_ops [] = {
61 #define regmask(reg) (((regmask_t)1) << (reg))
63 static const regmask_t regbank_callee_saved_regs [] = {
64 MONO_ARCH_CALLEE_SAVED_REGS,
65 MONO_ARCH_CALLEE_SAVED_FREGS,
66 MONO_ARCH_CALLEE_SAVED_XREGS,
69 static const regmask_t regbank_callee_regs [] = {
70 MONO_ARCH_CALLEE_REGS,
71 MONO_ARCH_CALLEE_FREGS,
72 MONO_ARCH_CALLEE_XREGS,
75 static const int regbank_spill_var_size[] = {
78 16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
89 new_list = mono_mempool_alloc (mp, sizeof (GSList));
90 new_list->data = data;
91 new_list->next = NULL;
97 last->next = new_list;
105 mono_regstate_assign (MonoRegState *rs)
107 if (rs->next_vreg > rs->vassign_size) {
108 g_free (rs->vassign);
109 rs->vassign_size = MAX (rs->next_vreg, 256);
110 rs->vassign = g_malloc (rs->vassign_size * sizeof (gint32));
113 memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
114 memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
116 rs->symbolic [0] = rs->isymbolic;
117 rs->symbolic [1] = rs->fsymbolic;
119 #ifdef MONO_ARCH_NEED_SIMD_BANK
120 memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
121 rs->symbolic [2] = rs->xsymbolic;
126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
128 regmask_t mask = allow & rs->ifree_mask;
130 #if defined(__x86_64__) && defined(__GNUC__)
137 __asm__("bsfq %1,%0\n\t"
138 : "=r" (i) : "rm" (mask));
140 rs->ifree_mask &= ~ ((regmask_t)1 << i);
146 for (i = 0; i < MONO_MAX_IREGS; ++i) {
147 if (mask & ((regmask_t)1 << i)) {
148 rs->ifree_mask &= ~ ((regmask_t)1 << i);
157 mono_regstate_free_int (MonoRegState *rs, int reg)
160 rs->ifree_mask |= (regmask_t)1 << reg;
161 rs->isymbolic [reg] = 0;
166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
169 regmask_t mask = allow & rs->free_mask [bank];
170 for (i = 0; i < regbank_size [bank]; ++i) {
171 if (mask & ((regmask_t)1 << i)) {
172 rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
183 rs->free_mask [bank] |= (regmask_t)1 << reg;
184 rs->symbolic [bank][reg] = 0;
189 mono_regname_full (int reg, int bank)
191 if (G_UNLIKELY (bank)) {
192 #if MONO_ARCH_NEED_SIMD_BANK
194 return mono_arch_xregname (reg);
196 g_assert (bank == 1);
197 return mono_arch_fregname (reg);
199 return mono_arch_regname (reg);
204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
208 regpair = (((guint32)hreg) << 24) + vreg;
209 if (G_UNLIKELY (bank)) {
210 g_assert (vreg >= regbank_size [bank]);
211 g_assert (hreg < regbank_size [bank]);
212 call->used_fregs |= 1 << hreg;
213 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
215 g_assert (vreg >= MONO_MAX_IREGS);
216 g_assert (hreg < MONO_MAX_IREGS);
217 call->used_iregs |= 1 << hreg;
218 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
223 resize_spill_info (MonoCompile *cfg, int bank)
225 MonoSpillInfo *orig_info = cfg->spill_info [bank];
226 int orig_len = cfg->spill_info_len [bank];
227 int new_len = orig_len ? orig_len * 2 : 16;
228 MonoSpillInfo *new_info;
231 g_assert (bank < MONO_NUM_REGBANKS);
233 new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
235 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
236 for (i = orig_len; i < new_len; ++i)
237 new_info [i].offset = -1;
239 cfg->spill_info [bank] = new_info;
240 cfg->spill_info_len [bank] = new_len;
244 * returns the offset used by spillvar. It allocates a new
245 * spill variable if necessary.
248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
253 if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
254 while (spillvar >= cfg->spill_info_len [bank])
255 resize_spill_info (cfg, bank);
259 * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
261 info = &cfg->spill_info [bank][spillvar];
262 if (info->offset == -1) {
263 cfg->stack_offset += sizeof (gpointer) - 1;
264 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
266 g_assert (bank < MONO_NUM_REGBANKS);
267 if (G_UNLIKELY (bank))
268 size = regbank_spill_var_size [bank];
270 size = sizeof (gpointer);
272 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
273 cfg->stack_offset += size - 1;
274 cfg->stack_offset &= ~(size - 1);
275 info->offset = cfg->stack_offset;
276 cfg->stack_offset += size;
278 cfg->stack_offset += size - 1;
279 cfg->stack_offset &= ~(size - 1);
280 cfg->stack_offset += size;
281 info->offset = - cfg->stack_offset;
288 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
289 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
290 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
291 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
292 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
293 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
295 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
296 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
297 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
298 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
299 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
301 #ifndef MONO_ARCH_INST_IS_FLOAT
302 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
305 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
306 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
307 #define sreg_is_fp(n,spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1+(n)]))
308 #define sreg1_is_fp(spec) sreg_is_fp (0,(spec))
309 #define sreg2_is_fp(spec) sreg_is_fp (1,(spec))
311 #define reg_is_simd(desc) ((desc) == 'x')
313 #ifdef MONO_ARCH_NEED_SIMD_BANK
315 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
319 #define reg_bank(desc) reg_is_fp ((desc))
323 #define sreg_bank(n,spec) reg_bank ((spec)[MONO_INST_SRC1+(n)])
324 #define sreg1_bank(spec) sreg_bank (0, (spec))
325 #define sreg2_bank(spec) sreg_bank (1, (spec))
326 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
328 #define sreg_bank_ins(n,ins) sreg_bank ((n), ins_get_spec ((ins)->opcode))
329 #define sreg1_bank_ins(ins) sreg_bank_ins (0, (ins))
330 #define sreg2_bank_ins(ins) sreg_bank_ins (1, (ins))
331 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
333 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
335 #ifdef MONO_ARCH_IS_GLOBAL_IREG
336 #undef is_global_ireg
337 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
346 regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
349 #ifndef DISABLE_LOGGING
351 mono_print_ins_index (int i, MonoInst *ins)
353 const char *spec = ins_get_spec (ins->opcode);
355 int sregs [MONO_MAX_SRC_REGS];
358 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
360 printf (" %s", mono_inst_name (ins->opcode));
361 if (spec == MONO_ARCH_CPU_SPEC) {
362 /* This is a lowered opcode */
364 printf (" R%d <-", ins->dreg);
365 if (ins->sreg1 != -1)
366 printf (" R%d", ins->sreg1);
367 if (ins->sreg2 != -1)
368 printf (" R%d", ins->sreg2);
369 if (ins->sreg3 != -1)
370 printf (" R%d", ins->sreg3);
372 switch (ins->opcode) {
383 if (!(ins->flags & MONO_INST_BRLABEL)) {
384 if (!ins->inst_false_bb)
385 printf (" [B%d]", ins->inst_true_bb->block_num);
387 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
395 printf (" [%d (", (int)ins->inst_c0);
396 for (i = 0; i < ins->inst_phi_args [0]; i++) {
399 printf ("R%d", ins->inst_phi_args [i + 1]);
405 case OP_OUTARG_VTRETADDR:
406 printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
409 printf (" + 0x%lx", (long)ins->inst_offset);
416 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
420 if (spec [MONO_INST_DEST]) {
421 int bank = dreg_bank (spec);
422 if (is_soft_reg (ins->dreg, bank)) {
423 if (spec [MONO_INST_DEST] == 'b') {
424 if (ins->inst_offset == 0)
425 printf (" [R%d] <-", ins->dreg);
427 printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
430 printf (" R%d <-", ins->dreg);
431 } else if (spec [MONO_INST_DEST] == 'b') {
432 if (ins->inst_offset == 0)
433 printf (" [%s] <-", mono_arch_regname (ins->dreg));
435 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
437 printf (" %s <-", mono_regname_full (ins->dreg, bank));
439 if (spec [MONO_INST_SRC1]) {
440 int bank = sreg1_bank (spec);
441 if (is_soft_reg (ins->sreg1, bank)) {
442 if (spec [MONO_INST_SRC1] == 'b')
443 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
445 printf (" R%d", ins->sreg1);
446 } else if (spec [MONO_INST_SRC1] == 'b')
447 printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
449 printf (" %s", mono_regname_full (ins->sreg1, bank));
451 num_sregs = mono_inst_get_src_registers (ins, sregs);
452 for (j = 1; j < num_sregs; ++j) {
453 int bank = sreg_bank (j, spec);
454 if (is_soft_reg (sregs [j], bank))
455 printf (" R%d", sregs [j]);
457 printf (" %s", mono_regname_full (sregs [j], bank));
460 switch (ins->opcode) {
462 printf (" [%d]", (int)ins->inst_c0);
464 #if defined(TARGET_X86) || defined(TARGET_AMD64)
465 case OP_X86_PUSH_IMM:
467 case OP_ICOMPARE_IMM:
474 printf (" [%d]", (int)ins->inst_imm);
478 printf (" [%d]", (int)(gssize)ins->inst_p1);
481 printf (" [%lld]", (long long)ins->inst_l);
484 printf (" [%f]", *(double*)ins->inst_p0);
487 printf (" [%f]", *(float*)ins->inst_p0);
492 case OP_CALL_MEMBASE:
501 case OP_VCALL_MEMBASE:
504 case OP_VCALL2_MEMBASE:
506 case OP_VOIDCALL_MEMBASE:
507 case OP_VOIDCALLVIRT: {
508 MonoCallInst *call = (MonoCallInst*)ins;
511 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
513 * These are lowered opcodes, but they are in the .md files since the old
514 * JIT passes them to backends.
517 printf (" R%d <-", ins->dreg);
521 char *full_name = mono_method_full_name (call->method, TRUE);
522 printf (" [%s]", full_name);
524 } else if (call->fptr) {
525 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
527 printf (" [%s]", info->name);
530 list = call->out_ireg_args;
535 regpair = (guint32)(gssize)(list->data);
536 hreg = regpair >> 24;
537 reg = regpair & 0xffffff;
539 printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
541 list = g_slist_next (list);
546 case OP_CALL_HANDLER:
547 printf (" [B%d]", ins->inst_target_bb->block_num);
579 if (!(ins->flags & MONO_INST_BRLABEL)) {
580 if (!ins->inst_false_bb)
581 printf (" [B%d]", ins->inst_true_bb->block_num);
583 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
586 case OP_LIVERANGE_START:
587 case OP_LIVERANGE_END:
588 printf (" R%d", (int)ins->inst_c1);
594 if (spec [MONO_INST_CLOB])
595 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
600 print_regtrack (RegTrack *t, int num)
606 for (i = 0; i < num; ++i) {
609 if (i >= MONO_MAX_IREGS) {
610 g_snprintf (buf, sizeof(buf), "R%d", i);
613 r = mono_arch_regname (i);
614 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
619 mono_print_ins_index (int i, MonoInst *ins)
622 #endif /* DISABLE_LOGGING */
625 mono_print_ins (MonoInst *ins)
627 mono_print_ins_index (-1, ins);
631 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
634 * If this function is called multiple times, the new instructions are inserted
635 * in the proper order.
637 mono_bblock_insert_before_ins (bb, ins, to_insert);
641 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
644 * If this function is called multiple times, the new instructions are inserted in
647 mono_bblock_insert_after_ins (bb, *last, to_insert);
653 * Force the spilling of the variable in the symbolic register 'reg'.
656 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
661 MonoRegState *rs = cfg->rs;
663 symbolic = rs->symbolic [bank];
664 sel = rs->vassign [reg];
666 /*i = rs->isymbolic [sel];
667 g_assert (i == reg);*/
669 spill = ++cfg->spill_count;
670 rs->vassign [i] = -spill - 1;
671 if (G_UNLIKELY (bank))
672 mono_regstate_free_general (rs, sel, bank);
674 mono_regstate_free_int (rs, sel);
675 /* we need to create a spill var and insert a load to sel after the current instruction */
676 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
678 load->inst_basereg = cfg->frame_reg;
679 load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
680 insert_after_ins (bb, ins, last, load);
681 DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
682 if (G_UNLIKELY (bank))
683 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
685 i = mono_regstate_alloc_int (rs, regmask (sel));
691 /* This isn't defined on older glib versions and on some platforms */
692 #ifndef G_GUINT64_FORMAT
693 #define G_GUINT64_FORMAT "ul"
697 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
700 int i, sel, spill, num_sregs;
701 int sregs [MONO_MAX_SRC_REGS];
703 MonoRegState *rs = cfg->rs;
705 symbolic = rs->symbolic [bank];
707 g_assert (bank < MONO_NUM_REGBANKS);
709 DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2, ins->sreg3));
710 /* exclude the registers in the current instruction */
711 num_sregs = mono_inst_get_src_registers (ins, sregs);
712 for (i = 0; i < num_sregs; ++i) {
713 if ((sreg_bank_ins (i, ins) == bank) && (reg != sregs [i]) && (reg_is_freeable (sregs [i], bank) || (is_soft_reg (sregs [i], bank) && rs->vassign [sregs [i]] >= 0))) {
714 if (is_soft_reg (sregs [i], bank))
715 regmask &= ~ (regmask (rs->vassign [sregs [i]]));
717 regmask &= ~ (regmask (sregs [i]));
718 DEBUG (printf ("\t\texcluding sreg%d %s %d\n", i + 1, mono_regname_full (sregs [i], bank), sregs [i]));
721 if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
722 regmask &= ~ (regmask (ins->dreg));
723 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
726 DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
727 g_assert (regmask); /* need at least a register we can free */
729 /* we should track prev_use and spill the register that's farther */
730 if (G_UNLIKELY (bank)) {
731 for (i = 0; i < regbank_size [bank]; ++i) {
732 if (regmask & (regmask (i))) {
734 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
739 i = rs->symbolic [bank] [sel];
740 spill = ++cfg->spill_count;
741 rs->vassign [i] = -spill - 1;
742 mono_regstate_free_general (rs, sel, bank);
745 for (i = 0; i < MONO_MAX_IREGS; ++i) {
746 if (regmask & (regmask (i))) {
748 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
753 i = rs->isymbolic [sel];
754 spill = ++cfg->spill_count;
755 rs->vassign [i] = -spill - 1;
756 mono_regstate_free_int (rs, sel);
759 /* we need to create a spill var and insert a load to sel after the current instruction */
760 MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
762 load->inst_basereg = cfg->frame_reg;
763 load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
764 insert_after_ins (bb, ins, last, load);
765 DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
766 if (G_UNLIKELY (bank))
767 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
769 i = mono_regstate_alloc_int (rs, regmask (sel));
776 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
778 if (G_UNLIKELY (bank)) {
779 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
780 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
781 get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
782 mono_regstate_free_general (cfg->rs, hreg, bank);
786 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
787 DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
788 get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
789 mono_regstate_free_int (cfg->rs, hreg);
795 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
799 MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
805 mono_bblock_insert_after_ins (bb, ins, copy);
808 DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
813 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
816 MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
818 store->inst_destbasereg = cfg->frame_reg;
819 store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
821 mono_bblock_insert_after_ins (bb, ins, store);
824 DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
828 /* flags used in reginfo->flags */
830 MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
831 MONO_FP_NEEDS_SPILL = regmask (1),
832 MONO_FP_NEEDS_LOAD = regmask (2)
836 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
840 if (info && info->preferred_mask) {
841 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
843 DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
848 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
850 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
856 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
860 val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
863 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
869 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
871 if (G_UNLIKELY (bank))
872 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
874 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
878 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
880 if (G_UNLIKELY (bank)) {
881 g_assert (reg >= regbank_size [bank]);
882 g_assert (hreg < regbank_size [bank]);
883 g_assert (! is_global_freg (hreg));
885 rs->vassign [reg] = hreg;
886 rs->symbolic [bank] [hreg] = reg;
887 rs->free_mask [bank] &= ~ (regmask (hreg));
890 g_assert (reg >= MONO_MAX_IREGS);
891 g_assert (hreg < MONO_MAX_IREGS);
893 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
894 g_assert (! is_global_ireg (hreg));
897 rs->vassign [reg] = hreg;
898 rs->isymbolic [hreg] = reg;
899 rs->ifree_mask &= ~ (regmask (hreg));
903 static inline regmask_t
904 get_callee_mask (const char spec)
906 if (G_UNLIKELY (reg_bank (spec)))
907 return regbank_callee_regs [reg_bank (spec)];
908 return MONO_ARCH_CALLEE_REGS;
911 static gint8 desc_to_fixed_reg [256];
912 static gboolean desc_to_fixed_reg_inited = FALSE;
915 * Local register allocation.
916 * We first scan the list of instructions and we save the liveness info of
917 * each register (when the register is first used, when it's value is set etc.).
918 * We also reverse the list of instructions because assigning registers backwards allows
919 * for more tricks to be used.
922 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
924 MonoInst *ins, *prev, *last;
926 MonoRegState *rs = cfg->rs;
930 unsigned char spec_src1, spec_dest;
932 #if MONO_ARCH_USE_FPSTACK
933 gboolean has_fp = FALSE;
938 int sregs [MONO_MAX_SRC_REGS];
943 if (!desc_to_fixed_reg_inited) {
944 for (i = 0; i < 256; ++i)
945 desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
946 desc_to_fixed_reg_inited = TRUE;
949 rs->next_vreg = bb->max_vreg;
950 mono_regstate_assign (rs);
952 rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
953 for (i = 0; i < MONO_NUM_REGBANKS; ++i)
954 rs->free_mask [i] = regbank_callee_regs [i];
958 if (cfg->reginfo && cfg->reginfo_len < max)
961 reginfo = cfg->reginfo;
963 cfg->reginfo_len = MAX (1024, max * 2);
964 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
967 g_assert (cfg->reginfo_len >= rs->next_vreg);
969 if (cfg->verbose_level > 1) {
970 /* print_regtrack reads the info of all variables */
971 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
975 * For large methods, next_vreg can be very large, so g_malloc0 time can
976 * be prohibitive. So we manually init the reginfo entries used by the
979 for (ins = bb->code; ins; ins = ins->next) {
980 spec = ins_get_spec (ins->opcode);
982 if ((ins->dreg != -1) && (ins->dreg < max)) {
983 memset (®info [ins->dreg], 0, sizeof (RegTrack));
984 #if SIZEOF_REGISTER == 4
985 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
987 * In the new IR, the two vregs of the regpair do not alias the
988 * original long vreg. shift the vreg here so the rest of the
989 * allocator doesn't have to care about it.
992 memset (®info [ins->dreg + 1], 0, sizeof (RegTrack));
997 num_sregs = mono_inst_get_src_registers (ins, sregs);
998 for (j = 0; j < num_sregs; ++j) {
999 g_assert (sregs [j] != -1);
1000 if (sregs [j] < max) {
1001 memset (®info [sregs [j]], 0, sizeof (RegTrack));
1002 #if SIZEOF_REGISTER == 4
1003 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j])) {
1005 memset (®info [sregs [j] + 1], 0, sizeof (RegTrack));
1010 mono_inst_set_src_registers (ins, sregs);
1013 /*if (cfg->opt & MONO_OPT_COPYPROP)
1014 local_copy_prop (cfg, ins);*/
1017 DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1018 /* forward pass on the instructions to collect register liveness info */
1019 MONO_BB_FOR_EACH_INS (bb, ins) {
1020 spec = ins_get_spec (ins->opcode);
1021 spec_dest = spec [MONO_INST_DEST];
1023 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1024 g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1027 DEBUG (mono_print_ins_index (i, ins));
1029 num_sregs = mono_inst_get_src_registers (ins, sregs);
1031 #if MONO_ARCH_USE_FPSTACK
1032 if (dreg_is_fp (spec)) {
1035 for (j = 0; j < num_sregs; ++j) {
1036 if (sreg_is_fp (j, spec))
1042 for (j = 0; j < num_sregs; ++j) {
1043 int sreg = sregs [j];
1044 int sreg_spec = spec [MONO_INST_SRC1 + j];
1046 bank = sreg_bank (j, spec);
1047 g_assert (sreg != -1);
1048 if (is_soft_reg (sreg, bank))
1049 /* This means the vreg is not local to this bb */
1050 g_assert (reginfo [sreg].born_in > 0);
1051 rs->vassign [sreg] = -1;
1052 //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1053 //reginfo [ins->sreg2].last_use = i;
1054 if (MONO_ARCH_INST_IS_REGPAIR (sreg_spec)) {
1055 /* The virtual register is allocated sequentially */
1056 rs->vassign [sreg + 1] = -1;
1057 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1058 //reginfo [ins->sreg2 + 1].last_use = i;
1059 if (reginfo [sreg + 1].born_in == 0 || reginfo [sreg + 1].born_in > i)
1060 reginfo [sreg + 1].born_in = i;
1066 mono_inst_set_src_registers (ins, sregs);
1071 bank = dreg_bank (spec);
1072 if (spec_dest != 'b') /* it's not just a base register */
1073 reginfo [ins->dreg].killed_in = i;
1074 g_assert (ins->dreg != -1);
1075 rs->vassign [ins->dreg] = -1;
1076 //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1077 //reginfo [ins->dreg].last_use = i;
1078 if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1079 reginfo [ins->dreg].born_in = i;
1081 dest_dreg = desc_to_fixed_reg [spec_dest];
1082 if (dest_dreg != -1)
1083 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1085 #ifdef MONO_ARCH_INST_FIXED_MASK
1086 reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1089 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1090 /* The virtual register is allocated sequentially */
1091 rs->vassign [ins->dreg + 1] = -1;
1092 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1093 //reginfo [ins->dreg + 1].last_use = i;
1094 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1095 reginfo [ins->dreg + 1].born_in = i;
1096 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1097 reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1103 if (spec [MONO_INST_CLOB] == 'c') {
1104 /* A call instruction implicitly uses all registers in call->out_ireg_args */
1106 MonoCallInst *call = (MonoCallInst*)ins;
1109 list = call->out_ireg_args;
1115 regpair = (guint32)(gssize)(list->data);
1116 hreg = regpair >> 24;
1117 reg = regpair & 0xffffff;
1119 //reginfo [reg].prev_use = reginfo [reg].last_use;
1120 //reginfo [reg].last_use = i;
1122 list = g_slist_next (list);
1126 list = call->out_freg_args;
1132 regpair = (guint32)(gssize)(list->data);
1133 hreg = regpair >> 24;
1134 reg = regpair & 0xffffff;
1136 list = g_slist_next (list);
1146 DEBUG (print_regtrack (reginfo, rs->next_vreg));
1147 MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1148 int prev_dreg, clob_dreg;
1149 int dest_dreg, clob_reg;
1150 int dest_sregs [MONO_MAX_SRC_REGS], prev_sregs [MONO_MAX_SRC_REGS];
1151 int dreg_high, sreg1_high;
1152 regmask_t dreg_mask, mask;
1153 regmask_t sreg_masks [MONO_MAX_SRC_REGS], sreg_fixed_masks [MONO_MAX_SRC_REGS];
1154 regmask_t dreg_fixed_mask;
1155 const unsigned char *ip;
1157 spec = ins_get_spec (ins->opcode);
1158 spec_src1 = spec [MONO_INST_SRC1];
1159 spec_dest = spec [MONO_INST_DEST];
1166 dreg_mask = get_callee_mask (spec_dest);
1167 for (j = 0; j < MONO_MAX_SRC_REGS; ++j) {
1168 prev_sregs [j] = -1;
1169 sreg_masks [j] = get_callee_mask (spec [MONO_INST_SRC1 + j]);
1170 dest_sregs [j] = desc_to_fixed_reg [(int)spec [MONO_INST_SRC1 + j]];
1171 #ifdef MONO_ARCH_INST_FIXED_MASK
1172 sreg_fixed_masks [j] = MONO_ARCH_INST_FIXED_MASK (spec [MONO_INST_SRC1 + j]);
1174 sreg_fixed_masks [j] = 0;
1178 DEBUG (printf ("processing:"));
1179 DEBUG (mono_print_ins_index (i, ins));
1188 dest_dreg = desc_to_fixed_reg [spec_dest];
1189 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1190 sreg_masks [1] &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1192 #ifdef MONO_ARCH_INST_FIXED_MASK
1193 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1195 dreg_fixed_mask = 0;
1198 num_sregs = mono_inst_get_src_registers (ins, sregs);
1201 * TRACK FIXED SREG2, 3, ...
1203 for (j = 1; j < num_sregs; ++j) {
1204 int sreg = sregs [j];
1205 int dest_sreg = dest_sregs [j];
1206 if (dest_sreg != -1) {
1207 if (rs->ifree_mask & (regmask (dest_sreg))) {
1208 if (is_global_ireg (sreg)) {
1210 /* Argument already in hard reg, need to copy */
1211 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1212 insert_before_ins (bb, ins, copy);
1213 for (k = 0; k < num_sregs; ++k) {
1215 sreg_masks [k] &= ~ (regmask (dest_sreg));
1219 val = rs->vassign [sreg];
1221 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", sreg, mono_arch_regname (dest_sreg)));
1222 assign_reg (cfg, rs, sreg, dest_sreg, 0);
1223 } else if (val < -1) {
1225 g_assert_not_reached ();
1227 /* Argument already in hard reg, need to copy */
1228 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, val, NULL, ip, 0);
1231 insert_before_ins (bb, ins, copy);
1232 for (k = 0; k < num_sregs; ++k) {
1234 sreg_masks [k] &= ~ (regmask (dest_sreg));
1237 * Prevent the dreg from being allocate to dest_sreg
1238 * too, since it could force sreg1 to be allocated to
1239 * the same reg on x86.
1241 dreg_mask &= ~ (regmask (dest_sreg));
1245 gboolean need_spill = TRUE;
1246 gboolean need_assign = TRUE;
1249 dreg_mask &= ~ (regmask (dest_sreg));
1250 for (k = 0; k < num_sregs; ++k) {
1252 sreg_masks [k] &= ~ (regmask (dest_sreg));
1256 * First check if dreg is assigned to dest_sreg2, since we
1257 * can't spill a dreg.
1259 val = rs->vassign [ins->dreg];
1260 if (val == dest_sreg && ins->dreg != sreg) {
1262 * the destination register is already assigned to
1263 * dest_sreg2: we need to allocate another register for it
1264 * and then copy from this to dest_sreg2.
1267 new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg]);
1268 g_assert (new_dest >= 0);
1269 DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg)));
1271 prev_dreg = ins->dreg;
1272 assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1273 clob_dreg = ins->dreg;
1274 create_copy_ins (cfg, bb, tmp, dest_sreg, new_dest, ins, ip, 0);
1275 mono_regstate_free_int (rs, dest_sreg);
1279 if (is_global_ireg (sreg)) {
1280 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg, sreg, NULL, ip, 0);
1281 insert_before_ins (bb, ins, copy);
1282 need_assign = FALSE;
1285 val = rs->vassign [sreg];
1286 if (val == dest_sreg) {
1287 /* sreg2 is already assigned to the correct register */
1289 } else if (val < -1) {
1290 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1291 } else if (val >= 0) {
1292 /* sreg2 already assigned to another register */
1294 * We couldn't emit a copy from val to dest_sreg2, because
1295 * val might be spilled later while processing this
1296 * instruction. So we spill sreg2 so it can be allocated to
1299 DEBUG (printf ("\tforced spill of R%d\n", sreg));
1300 free_up_reg (cfg, bb, tmp, ins, val, 0);
1305 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg]));
1306 free_up_reg (cfg, bb, tmp, ins, dest_sreg, 0);
1310 if (rs->vassign [sreg] < -1) {
1314 /* Need to emit a spill store */
1315 spill = - rs->vassign [sreg] - 1;
1316 store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
1317 insert_before_ins (bb, ins, store);
1319 /* force-set sreg2 */
1320 assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
1323 sregs [j] = dest_sreg;
1326 mono_inst_set_src_registers (ins, sregs);
1331 bank = dreg_bank (spec);
1332 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1333 prev_dreg = ins->dreg;
1336 if (spec_dest == 'b') {
1338 * The dest reg is read by the instruction, not written, so
1339 * avoid allocating sreg1/sreg2 to the same reg.
1341 if (dest_sregs [0] != -1)
1342 dreg_mask &= ~ (regmask (dest_sregs [0]));
1343 for (j = 1; j < num_sregs; ++j) {
1344 if (dest_sregs [j] != -1)
1345 dreg_mask &= ~ (regmask (dest_sregs [j]));
1348 val = rs->vassign [ins->dreg];
1349 if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1350 /* DREG is already allocated to a register needed for sreg1 */
1351 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1352 mono_regstate_free_int (rs, val);
1357 * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1358 * various complex situations.
1360 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1361 guint32 dreg2, dest_dreg2;
1363 g_assert (is_soft_reg (ins->dreg, bank));
1365 if (dest_dreg != -1) {
1366 if (rs->vassign [ins->dreg] != dest_dreg)
1367 free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1369 dreg2 = ins->dreg + 1;
1370 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1371 if (dest_dreg2 != -1) {
1372 if (rs->vassign [dreg2] != dest_dreg2)
1373 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1378 if (dreg_fixed_mask) {
1380 if (is_global_ireg (ins->dreg)) {
1382 * The argument is already in a hard reg, but that reg is
1383 * not usable by this instruction, so allocate a new one.
1385 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1387 val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1388 mono_regstate_free_int (rs, val);
1394 dreg_mask &= dreg_fixed_mask;
1397 if (is_soft_reg (ins->dreg, bank)) {
1398 val = rs->vassign [ins->dreg];
1403 /* the register gets spilled after this inst */
1406 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
1407 assign_reg (cfg, rs, ins->dreg, val, bank);
1409 create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1412 DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1416 /* Handle regpairs */
1417 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1418 int reg2 = prev_dreg + 1;
1421 g_assert (prev_dreg > -1);
1422 g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1423 mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1426 mask &= ~regmask (X86_ECX);
1428 val = rs->vassign [reg2];
1432 /* the register gets spilled after this inst */
1435 val = mono_regstate_alloc_int (rs, mask);
1437 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1439 create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1442 if (! (mask & (regmask (val)))) {
1443 val = mono_regstate_alloc_int (rs, mask);
1445 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1447 /* Reallocate hreg to the correct register */
1448 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1450 mono_regstate_free_int (rs, rs->vassign [reg2]);
1454 DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1455 assign_reg (cfg, rs, reg2, val, bank);
1458 ins->backend.reg3 = val;
1460 if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1461 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1462 mono_regstate_free_int (rs, val);
1466 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1468 * In theory, we could free up the hreg even if the vreg is alive,
1469 * but branches inside bblocks force us to assign the same hreg
1470 * to a vreg every time it is encountered.
1472 int dreg = rs->vassign [prev_dreg];
1473 g_assert (dreg >= 0);
1474 DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1475 if (G_UNLIKELY (bank))
1476 mono_regstate_free_general (rs, dreg, bank);
1478 mono_regstate_free_int (rs, dreg);
1479 rs->vassign [prev_dreg] = -1;
1482 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1483 /* this instruction only outputs to dest_dreg, need to copy */
1484 create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1485 ins->dreg = dest_dreg;
1487 if (G_UNLIKELY (bank)) {
1488 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1489 free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1492 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1493 free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1497 if (spec_dest == 'b') {
1499 * The dest reg is read by the instruction, not written, so
1500 * avoid allocating sreg1/sreg2 to the same reg.
1502 for (j = 0; j < num_sregs; ++j)
1503 if (!sreg_bank (j, spec))
1504 sreg_masks [j] &= ~ (regmask (ins->dreg));
1510 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1511 DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1512 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1513 mono_regstate_free_int (rs, clob_reg);
1516 if (spec [MONO_INST_CLOB] == 'c') {
1517 int j, s, dreg, dreg2, cur_bank;
1520 clob_mask = MONO_ARCH_CALLEE_REGS;
1522 if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1524 * Need to avoid spilling the dreg since the dreg is not really
1525 * clobbered by the call.
1527 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1528 dreg = rs->vassign [prev_dreg];
1532 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1533 dreg2 = rs->vassign [prev_dreg + 1];
1537 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1539 if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1540 if ((j != dreg) && (j != dreg2))
1541 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1542 else if (rs->isymbolic [j])
1543 /* The hreg is assigned to the dreg of this instruction */
1544 rs->vassign [rs->isymbolic [j]] = -1;
1545 mono_regstate_free_int (rs, j);
1550 for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1551 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1552 clob_mask = regbank_callee_regs [cur_bank];
1553 if ((prev_dreg != -1) && reg_bank (spec_dest))
1554 dreg = rs->vassign [prev_dreg];
1558 for (j = 0; j < regbank_size [cur_bank]; ++j) {
1560 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1562 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1563 else if (rs->symbolic [cur_bank] [j])
1564 /* The hreg is assigned to the dreg of this instruction */
1565 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1566 mono_regstate_free_general (rs, j, cur_bank);
1574 * TRACK ARGUMENT REGS
1576 if (spec [MONO_INST_CLOB] == 'c') {
1577 MonoCallInst *call = (MonoCallInst*)ins;
1581 * This needs to be done before assigning sreg1, so sreg1 will
1582 * not be assigned one of the argument regs.
1586 * Assign all registers in call->out_reg_args to the proper
1587 * argument registers.
1590 list = call->out_ireg_args;
1596 regpair = (guint32)(gssize)(list->data);
1597 hreg = regpair >> 24;
1598 reg = regpair & 0xffffff;
1600 assign_reg (cfg, rs, reg, hreg, 0);
1602 sreg_masks [0] &= ~(regmask (hreg));
1604 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1606 list = g_slist_next (list);
1610 list = call->out_freg_args;
1616 regpair = (guint32)(gssize)(list->data);
1617 hreg = regpair >> 24;
1618 reg = regpair & 0xffffff;
1620 assign_reg (cfg, rs, reg, hreg, 1);
1622 DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1624 list = g_slist_next (list);
1632 bank = sreg1_bank (spec);
1633 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1634 int sreg1 = sregs [0];
1635 int dest_sreg1 = dest_sregs [0];
1637 g_assert (is_soft_reg (sreg1, bank));
1639 /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1640 if (dest_sreg1 != -1)
1641 g_assert (dest_sreg1 == ins->dreg);
1642 val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1643 g_assert (val >= 0);
1645 if (rs->vassign [sreg1] >= 0 && rs->vassign [sreg1] != val)
1647 g_assert_not_reached ();
1649 assign_reg (cfg, rs, sreg1, val, bank);
1651 DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), sreg1));
1653 g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1654 val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1655 g_assert (val >= 0);
1657 if (rs->vassign [sreg1 + 1] >= 0 && rs->vassign [sreg1 + 1] != val)
1659 g_assert_not_reached ();
1661 assign_reg (cfg, rs, sreg1 + 1, val, bank);
1663 DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), sreg1 + 1));
1665 /* Skip rest of this section */
1666 dest_sregs [0] = -1;
1669 if (sreg_fixed_masks [0]) {
1671 if (is_global_ireg (sregs [0])) {
1673 * The argument is already in a hard reg, but that reg is
1674 * not usable by this instruction, so allocate a new one.
1676 val = mono_regstate_alloc_int (rs, sreg_fixed_masks [0]);
1678 val = get_register_spilling (cfg, bb, tmp, ins, sreg_fixed_masks [0], -1, bank);
1679 mono_regstate_free_int (rs, val);
1680 dest_sregs [0] = val;
1682 /* Fall through to the dest_sreg1 != -1 case */
1685 sreg_masks [0] &= sreg_fixed_masks [0];
1688 if (dest_sregs [0] != -1) {
1689 sreg_masks [0] = regmask (dest_sregs [0]);
1691 if ((rs->vassign [sregs [0]] != dest_sregs [0]) && !(rs->ifree_mask & (regmask (dest_sregs [0])))) {
1692 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sregs [0]]));
1693 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sregs [0]], 0);
1694 mono_regstate_free_int (rs, dest_sregs [0]);
1696 if (is_global_ireg (sregs [0])) {
1697 /* The argument is already in a hard reg, need to copy */
1698 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], sregs [0], NULL, ip, 0);
1699 insert_before_ins (bb, ins, copy);
1700 sregs [0] = dest_sregs [0];
1704 if (is_soft_reg (sregs [0], bank)) {
1705 val = rs->vassign [sregs [0]];
1706 prev_sregs [0] = sregs [0];
1710 /* the register gets spilled after this inst */
1714 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1716 * Allocate the same hreg to sreg1 as well so the
1717 * peephole can get rid of the move.
1719 sreg_masks [0] = regmask (ins->dreg);
1722 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1723 /* Allocate the same reg to sreg1 to avoid a copy later */
1724 sreg_masks [0] = regmask (ins->dreg);
1726 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [0], sregs [0], ®info [sregs [0]], bank);
1727 assign_reg (cfg, rs, sregs [0], val, bank);
1728 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
1731 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
1733 * Need to insert before the instruction since it can
1736 insert_before_ins (bb, ins, store);
1739 else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
1740 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sregs [0], val, NULL, ip, bank);
1741 insert_before_ins (bb, ins, copy);
1742 for (j = 1; j < num_sregs; ++j)
1743 sreg_masks [j] &= ~(regmask (dest_sregs [0]));
1744 val = dest_sregs [0];
1750 prev_sregs [0] = -1;
1752 mono_inst_set_src_registers (ins, sregs);
1754 for (j = 1; j < num_sregs; ++j)
1755 sreg_masks [j] &= ~(regmask (sregs [0]));
1757 /* Handle the case when sreg1 is a regpair but dreg is not */
1758 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1759 int reg2 = prev_sregs [0] + 1;
1762 g_assert (prev_sregs [0] > -1);
1763 g_assert (!is_global_ireg (rs->vassign [prev_sregs [0]]));
1764 mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sregs [0]]);
1765 val = rs->vassign [reg2];
1769 /* the register gets spilled after this inst */
1772 val = mono_regstate_alloc_int (rs, mask);
1774 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1776 g_assert_not_reached ();
1779 if (! (mask & (regmask (val)))) {
1780 /* The vreg is already allocated to a wrong hreg */
1782 g_assert_not_reached ();
1784 val = mono_regstate_alloc_int (rs, mask);
1786 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1788 /* Reallocate hreg to the correct register */
1789 create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1791 mono_regstate_free_int (rs, rs->vassign [reg2]);
1797 DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1798 assign_reg (cfg, rs, reg2, val, bank);
1801 /* Handle dreg==sreg1 */
1802 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != sregs [0]) {
1803 MonoInst *sreg2_copy = NULL;
1805 int bank = reg_bank (spec_src1);
1807 if (ins->dreg == sregs [1]) {
1809 * copying sreg1 to dreg could clobber sreg2, so allocate a new
1812 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, sregs [1], NULL, bank);
1814 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (sregs [1], bank), mono_regname_full (reg2, bank)));
1815 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, sregs [1], NULL, ip, bank);
1816 prev_sregs [1] = sregs [1] = reg2;
1818 if (G_UNLIKELY (bank))
1819 mono_regstate_free_general (rs, reg2, bank);
1821 mono_regstate_free_int (rs, reg2);
1824 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1825 /* Copying sreg1_high to dreg could also clobber sreg2 */
1826 if (rs->vassign [prev_sregs [0] + 1] == sregs [1])
1828 g_assert_not_reached ();
1831 * sreg1 and dest are already allocated to the same regpair by the
1832 * SREG1 allocation code.
1834 g_assert (sregs [0] == ins->dreg);
1835 g_assert (dreg_high == sreg1_high);
1838 DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (sregs [0], bank), mono_regname_full (ins->dreg, bank)));
1839 copy = create_copy_ins (cfg, bb, tmp, ins->dreg, sregs [0], NULL, ip, bank);
1840 insert_before_ins (bb, ins, copy);
1843 insert_before_ins (bb, copy, sreg2_copy);
1846 * Need to prevent sreg2 to be allocated to sreg1, since that
1847 * would screw up the previous copy.
1849 sreg_masks [1] &= ~ (regmask (sregs [0]));
1850 /* we set sreg1 to dest as well */
1851 prev_sregs [0] = sregs [0] = ins->dreg;
1852 sreg_masks [1] &= ~ (regmask (ins->dreg));
1854 mono_inst_set_src_registers (ins, sregs);
1857 * TRACK SREG2, 3, ...
1859 for (j = 1; j < num_sregs; ++j) {
1862 bank = sreg_bank (j, spec);
1863 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1 + j]))
1864 g_assert_not_reached ();
1865 if (is_soft_reg (sregs [j], bank)) {
1866 val = rs->vassign [sregs [j]];
1871 /* the register gets spilled after this inst */
1874 val = alloc_reg (cfg, bb, tmp, ins, sreg_masks [j], sregs [j], ®info [sregs [j]], bank);
1875 assign_reg (cfg, rs, sregs [j], val, bank);
1876 DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
1878 MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
1880 * Need to insert before the instruction since it can
1883 insert_before_ins (bb, ins, store);
1887 for (k = j + 1; k < num_sregs; ++k)
1888 sreg_masks [k] &= ~ (regmask (sregs [j]));
1891 prev_sregs [j] = -1;
1894 mono_inst_set_src_registers (ins, sregs);
1896 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1897 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1898 mono_regstate_free_int (rs, ins->sreg1);
1900 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1901 DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1902 mono_regstate_free_int (rs, ins->sreg2);
1905 DEBUG (mono_print_ins_index (i, ins));
1908 // FIXME: Set MAX_FREGS to 8
1909 // FIXME: Optimize generated code
1910 #if MONO_ARCH_USE_FPSTACK
1912 * Make a forward pass over the code, simulating the fp stack, making sure the
1913 * arguments required by the fp opcodes are at the top of the stack.
1916 MonoInst *prev = NULL;
1920 g_assert (num_sregs <= 2);
1922 for (ins = bb->code; ins; ins = ins->next) {
1923 spec = ins_get_spec (ins->opcode);
1925 DEBUG (printf ("processing:"));
1926 DEBUG (mono_print_ins_index (0, ins));
1928 if (ins->opcode == OP_FMOVE) {
1929 /* Do it by renaming the source to the destination on the stack */
1930 // FIXME: Is this correct ?
1931 for (i = 0; i < sp; ++i)
1932 if (fpstack [i] == ins->sreg1)
1933 fpstack [i] = ins->dreg;
1938 if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1939 /* Arg1 must be in %st(1) */
1943 while ((i < sp) && (fpstack [i] != ins->sreg1))
1947 if (sp - 1 - i > 0) {
1948 /* First move it to %st(0) */
1949 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1951 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1952 fxch->inst_imm = sp - 1 - i;
1958 tmp = fpstack [sp - 1];
1959 fpstack [sp - 1] = fpstack [i];
1963 /* Then move it to %st(1) */
1964 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1966 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1973 tmp = fpstack [sp - 1];
1974 fpstack [sp - 1] = fpstack [sp - 2];
1975 fpstack [sp - 2] = tmp;
1978 if (sreg2_is_fp (spec)) {
1981 if (fpstack [sp - 1] != ins->sreg2) {
1985 while ((i < sp) && (fpstack [i] != ins->sreg2))
1989 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1991 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1992 fxch->inst_imm = sp - 1 - i;
1998 tmp = fpstack [sp - 1];
1999 fpstack [sp - 1] = fpstack [i];
2006 if (sreg1_is_fp (spec)) {
2009 if (fpstack [sp - 1] != ins->sreg1) {
2013 while ((i < sp) && (fpstack [i] != ins->sreg1))
2017 DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
2019 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
2020 fxch->inst_imm = sp - 1 - i;
2026 tmp = fpstack [sp - 1];
2027 fpstack [sp - 1] = fpstack [i];
2034 if (dreg_is_fp (spec)) {
2036 fpstack [sp ++] = ins->dreg;
2039 if (G_UNLIKELY (cfg->verbose_level >= 2)) {
2041 for (i = 0; i < sp; ++i)
2042 printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
2049 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2050 /* Remove remaining items from the fp stack */
2052 * These can remain for example as a result of a dead fmove like in
2053 * System.Collections.Generic.EqualityComparer<double>.Equals ().
2056 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2057 mono_add_ins_to_end (bb, ins);
2066 mono_opcode_to_cond (int opcode)
2077 case OP_COND_EXC_EQ:
2078 case OP_COND_EXC_IEQ:
2086 case OP_COND_EXC_NE_UN:
2087 case OP_COND_EXC_INE_UN:
2088 case OP_CMOV_INE_UN:
2089 case OP_CMOV_LNE_UN:
2113 case OP_COND_EXC_LT:
2114 case OP_COND_EXC_ILT:
2126 case OP_COND_EXC_GT:
2127 case OP_COND_EXC_IGT:
2136 case OP_COND_EXC_LE_UN:
2137 case OP_COND_EXC_ILE_UN:
2138 case OP_CMOV_ILE_UN:
2139 case OP_CMOV_LLE_UN:
2145 case OP_CMOV_IGE_UN:
2146 case OP_CMOV_LGE_UN:
2156 case OP_COND_EXC_LT_UN:
2157 case OP_COND_EXC_ILT_UN:
2158 case OP_CMOV_ILT_UN:
2159 case OP_CMOV_LLT_UN:
2169 case OP_COND_EXC_GT_UN:
2170 case OP_COND_EXC_IGT_UN:
2171 case OP_CMOV_IGT_UN:
2172 case OP_CMOV_LGT_UN:
2175 printf ("%s\n", mono_inst_name (opcode));
2176 g_assert_not_reached ();
2182 mono_negate_cond (CompRelation cond)
2206 g_assert_not_reached ();
2211 mono_opcode_to_type (int opcode, int cmp_opcode)
2213 if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2215 else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2217 else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2219 else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2221 else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2223 else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2225 else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2227 else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2229 else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2231 else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2232 switch (cmp_opcode) {
2234 case OP_ICOMPARE_IMM:
2235 case OP_LCOMPARE_IMM:
2241 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2247 mono_is_regsize_var (MonoType *t)
2251 t = mono_type_get_underlying_type (t);
2253 case MONO_TYPE_BOOLEAN:
2254 case MONO_TYPE_CHAR:
2264 case MONO_TYPE_FNPTR:
2265 #if SIZEOF_REGISTER == 8
2270 case MONO_TYPE_OBJECT:
2271 case MONO_TYPE_STRING:
2272 case MONO_TYPE_CLASS:
2273 case MONO_TYPE_SZARRAY:
2274 case MONO_TYPE_ARRAY:
2276 case MONO_TYPE_GENERICINST:
2277 if (!mono_type_generic_inst_is_valuetype (t))
2280 case MONO_TYPE_VALUETYPE:
2287 * mono_peephole_ins:
2289 * Perform some architecture independent peephole optimizations.
2292 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2294 MonoInst *last_ins = ins->prev;
2296 switch (ins->opcode) {
2298 /* remove unnecessary multiplication with 1 */
2299 if (ins->inst_imm == 1) {
2300 if (ins->dreg != ins->sreg1)
2301 ins->opcode = OP_MOVE;
2303 MONO_DELETE_INS (bb, ins);
2306 case OP_LOAD_MEMBASE:
2307 case OP_LOADI4_MEMBASE:
2309 * Note: if reg1 = reg2 the load op is removed
2311 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2312 * OP_LOAD_MEMBASE offset(basereg), reg2
2314 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2315 * OP_MOVE reg1, reg2
2318 (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2319 ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2320 ins->inst_basereg == last_ins->inst_destbasereg &&
2321 ins->inst_offset == last_ins->inst_offset) {
2322 if (ins->dreg == last_ins->sreg1) {
2323 MONO_DELETE_INS (bb, ins);
2326 ins->opcode = OP_MOVE;
2327 ins->sreg1 = last_ins->sreg1;
2331 * Note: reg1 must be different from the basereg in the second load
2332 * Note: if reg1 = reg2 is equal then second load is removed
2334 * OP_LOAD_MEMBASE offset(basereg), reg1
2335 * OP_LOAD_MEMBASE offset(basereg), reg2
2337 * OP_LOAD_MEMBASE offset(basereg), reg1
2338 * OP_MOVE reg1, reg2
2340 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2341 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2342 ins->inst_basereg != last_ins->dreg &&
2343 ins->inst_basereg == last_ins->inst_basereg &&
2344 ins->inst_offset == last_ins->inst_offset) {
2346 if (ins->dreg == last_ins->dreg) {
2347 MONO_DELETE_INS (bb, ins);
2349 ins->opcode = OP_MOVE;
2350 ins->sreg1 = last_ins->dreg;
2353 //g_assert_not_reached ();
2357 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2358 * OP_LOAD_MEMBASE offset(basereg), reg
2360 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2361 * OP_ICONST reg, imm
2363 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2364 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2365 ins->inst_basereg == last_ins->inst_destbasereg &&
2366 ins->inst_offset == last_ins->inst_offset) {
2367 ins->opcode = OP_ICONST;
2368 ins->inst_c0 = last_ins->inst_imm;
2369 g_assert_not_reached (); // check this rule
2373 case OP_LOADI1_MEMBASE:
2374 case OP_LOADU1_MEMBASE:
2376 * Note: if reg1 = reg2 the load op is removed
2378 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2379 * OP_LOAD_MEMBASE offset(basereg), reg2
2381 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2382 * OP_MOVE reg1, reg2
2384 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2385 ins->inst_basereg == last_ins->inst_destbasereg &&
2386 ins->inst_offset == last_ins->inst_offset) {
2387 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2388 ins->sreg1 = last_ins->sreg1;
2391 case OP_LOADI2_MEMBASE:
2392 case OP_LOADU2_MEMBASE:
2394 * Note: if reg1 = reg2 the load op is removed
2396 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2397 * OP_LOAD_MEMBASE offset(basereg), reg2
2399 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2400 * OP_MOVE reg1, reg2
2402 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2403 ins->inst_basereg == last_ins->inst_destbasereg &&
2404 ins->inst_offset == last_ins->inst_offset) {
2405 #if SIZEOF_REGISTER == 8
2406 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2408 /* The definition of OP_PCONV_TO_U2 is wrong */
2409 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2411 ins->sreg1 = last_ins->sreg1;
2421 if (ins->dreg == ins->sreg1) {
2422 MONO_DELETE_INS (bb, ins);
2428 * OP_MOVE sreg, dreg
2429 * OP_MOVE dreg, sreg
2431 if (last_ins && last_ins->opcode == OP_MOVE &&
2432 ins->sreg1 == last_ins->dreg &&
2433 ins->dreg == last_ins->sreg1) {
2434 MONO_DELETE_INS (bb, ins);
2438 MONO_DELETE_INS (bb, ins);