mono/mini/mini-codegen.c

   1 /*
   2  * mini-codegen.c: Arch independent code generation functionality
   3  *
   4  * (C) 2003 Ximian, Inc.
   5  */
   6
   7 #include <string.h>
   8 #include <math.h>
   9 #ifdef HAVE_UNISTD_H
  10 #include <unistd.h>
  11 #endif
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/metadata/threads.h>
  16 #include <mono/metadata/profiler-private.h>
  17 #include <mono/utils/mono-math.h>
  18
  19 #include "mini.h"
  20 #include "trace.h"
  21 #include "mini-arch.h"
  22
  23 #ifndef MONO_MAX_XREGS
  24
  25 #define MONO_MAX_XREGS 0
  26 #define MONO_ARCH_CALLEE_SAVED_XREGS 0
  27 #define MONO_ARCH_CALLEE_XREGS 0
  28
  29 #endif
  30 /*
  31  * Every hardware register belongs to a register type or register bank. bank 0
  32  * contains the int registers, bank 1 contains the fp registers.
  33  * int registers are used 99% of the time, so they are special cased in a lot of
  34  * places.
  35  */
  36
  37 static const int regbank_size [] = {
  38         MONO_MAX_IREGS,
  39         MONO_MAX_FREGS,
  40         MONO_MAX_XREGS
  41 };
  42
  43 static const int regbank_load_ops [] = {
  44         OP_LOAD_MEMBASE,
  45         OP_LOADR8_MEMBASE,
  46         OP_LOADX_MEMBASE
  47 };
  48
  49 static const int regbank_store_ops [] = {
  50         OP_STORE_MEMBASE_REG,
  51         OP_STORER8_MEMBASE_REG,
  52         OP_STOREX_MEMBASE
  53 };
  54
  55 static const int regbank_move_ops [] = {
  56         OP_MOVE,
  57         OP_FMOVE,
  58         OP_XMOVE
  59 };
  60
  61 #define regmask(reg) (((regmask_t)1) << (reg))
  62
  63 static const regmask_t regbank_callee_saved_regs [] = {
  64         MONO_ARCH_CALLEE_SAVED_REGS,
  65         MONO_ARCH_CALLEE_SAVED_FREGS,
  66         MONO_ARCH_CALLEE_SAVED_XREGS,
  67 };
  68
  69 static const regmask_t regbank_callee_regs [] = {
  70         MONO_ARCH_CALLEE_REGS,
  71         MONO_ARCH_CALLEE_FREGS,
  72         MONO_ARCH_CALLEE_XREGS,
  73 };
  74
  75 static const int regbank_spill_var_size[] = {
  76         sizeof (gpointer),
  77         sizeof (double),
  78         16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
  79 };
  80
  81 #define DEBUG(a) MINI_DEBUG(cfg->verbose_level, 3, a;)
  82
  83 static inline GSList*
  84 g_slist_append_mempool (MonoMemPool *mp, GSList *list, gpointer data)
  85 {
  86         GSList *new_list;
  87         GSList *last;
  88
  89         new_list = mono_mempool_alloc (mp, sizeof (GSList));
  90         new_list->data = data;
  91         new_list->next = NULL;
  92
  93         if (list) {
  94                 last = list;
  95                 while (last->next)
  96                         last = last->next;
  97                 last->next = new_list;
  98
  99                 return list;
 100         } else
 101                 return new_list;
 102 }
 103
 104 static inline void
 105 mono_regstate_assign (MonoRegState *rs)
 106 {
 107         if (rs->next_vreg > rs->vassign_size) {
 108                 g_free (rs->vassign);
 109                 rs->vassign_size = MAX (rs->next_vreg, 256);
 110                 rs->vassign = g_malloc (rs->vassign_size * sizeof (int));
 111         }
 112
 113         memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
 114         memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
 115
 116         rs->symbolic [0] = rs->isymbolic;
 117         rs->symbolic [1] = rs->fsymbolic;
 118
 119 #ifdef MONO_ARCH_NEED_SIMD_BANK
 120         memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
 121         rs->symbolic [2] = rs->xsymbolic;
 122 #endif
 123 }
 124
 125 static inline int
 126 mono_regstate_alloc_int (MonoRegState *rs, regmask_t allow)
 127 {
 128         regmask_t mask = allow & rs->ifree_mask;
 129
 130 #if defined(__x86_64__) && defined(__GNUC__)
 131  {
 132         guint64 i;
 133
 134         if (mask == 0)
 135                 return -1;
 136
 137         __asm__("bsfq %1,%0\n\t"
 138                         : "=r" (i) : "rm" (mask));
 139
 140         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 141         return i;
 142  }
 143 #else
 144         int i;
 145
 146         for (i = 0; i < MONO_MAX_IREGS; ++i) {
 147                 if (mask & ((regmask_t)1 << i)) {
 148                         rs->ifree_mask &= ~ ((regmask_t)1 << i);
 149                         return i;
 150                 }
 151         }
 152         return -1;
 153 #endif
 154 }
 155
 156 static inline void
 157 mono_regstate_free_int (MonoRegState *rs, int reg)
 158 {
 159         if (reg >= 0) {
 160                 rs->ifree_mask |= (regmask_t)1 << reg;
 161                 rs->isymbolic [reg] = 0;
 162         }
 163 }
 164
 165 static inline int
 166 mono_regstate_alloc_general (MonoRegState *rs, regmask_t allow, int bank)
 167 {
 168         int i;
 169         regmask_t mask = allow & rs->free_mask [bank];
 170         for (i = 0; i < regbank_size [bank]; ++i) {
 171                 if (mask & ((regmask_t)1 << i)) {
 172                         rs->free_mask [bank] &= ~ ((regmask_t)1 << i);
 173                         return i;
 174                 }
 175         }
 176         return -1;
 177 }
 178
 179 static inline void
 180 mono_regstate_free_general (MonoRegState *rs, int reg, int bank)
 181 {
 182         if (reg >= 0) {
 183                 rs->free_mask [bank] |= (regmask_t)1 << reg;
 184                 rs->symbolic [bank][reg] = 0;
 185         }
 186 }
 187
 188 const char*
 189 mono_regname_full (int reg, int bank)
 190 {
 191         if (G_UNLIKELY (bank)) {
 192 #if MONO_ARCH_NEED_SIMD_BANK
 193                 if (bank == 2)
 194                         return mono_arch_xregname (reg);
 195 #endif
 196                 g_assert (bank == 1);
 197                 return mono_arch_fregname (reg);
 198         } else {
 199                 return mono_arch_regname (reg);
 200         }
 201 }
 202
 203 void
 204 mono_call_inst_add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, int vreg, int hreg, int bank)
 205 {
 206         guint32 regpair;
 207
 208         regpair = (((guint32)hreg) << 24) + vreg;
 209         if (G_UNLIKELY (bank)) {
 210                 g_assert (vreg >= regbank_size [bank]);
 211                 g_assert (hreg < regbank_size [bank]);
 212                 call->used_fregs |= 1 << hreg;
 213                 call->out_freg_args = g_slist_append_mempool (cfg->mempool, call->out_freg_args, (gpointer)(gssize)(regpair));
 214         } else {
 215                 g_assert (vreg >= MONO_MAX_IREGS);
 216                 g_assert (hreg < MONO_MAX_IREGS);
 217                 call->used_iregs |= 1 << hreg;
 218                 call->out_ireg_args = g_slist_append_mempool (cfg->mempool, call->out_ireg_args, (gpointer)(gssize)(regpair));
 219         }
 220 }
 221
 222 static void
 223 resize_spill_info (MonoCompile *cfg, int bank)
 224 {
 225         MonoSpillInfo *orig_info = cfg->spill_info [bank];
 226         int orig_len = cfg->spill_info_len [bank];
 227         int new_len = orig_len ? orig_len * 2 : 16;
 228         MonoSpillInfo *new_info;
 229         int i;
 230
 231         g_assert (bank < MONO_NUM_REGBANKS);
 232
 233         new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
 234         if (orig_info)
 235                 memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
 236         for (i = orig_len; i < new_len; ++i)
 237                 new_info [i].offset = -1;
 238
 239         cfg->spill_info [bank] = new_info;
 240         cfg->spill_info_len [bank] = new_len;
 241 }
 242
 243 /*
 244  * returns the offset used by spillvar. It allocates a new
 245  * spill variable if necessary.
 246  */
 247 static inline int
 248 mono_spillvar_offset (MonoCompile *cfg, int spillvar, int bank)
 249 {
 250         MonoSpillInfo *info;
 251         int size;
 252
 253 #if defined (__mips__)
 254         g_assert_not_reached();
 255 #endif
 256         if (G_UNLIKELY (spillvar >= (cfg->spill_info_len [bank]))) {
 257                 while (spillvar >= cfg->spill_info_len [bank])
 258                         resize_spill_info (cfg, bank);
 259         }
 260
 261         /*
 262          * Allocate separate spill slots for fp/non-fp variables since most processors prefer it.
 263          */
 264         info = &cfg->spill_info [bank][spillvar];
 265         if (info->offset == -1) {
 266                 cfg->stack_offset += sizeof (gpointer) - 1;
 267                 cfg->stack_offset &= ~(sizeof (gpointer) - 1);
 268
 269                 g_assert (bank < MONO_NUM_REGBANKS);
 270                 if (G_UNLIKELY (bank))
 271                         size = regbank_spill_var_size [bank];
 272                 else
 273                         size = sizeof (gpointer);
 274
 275                 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
 276                         cfg->stack_offset += size - 1;
 277                         cfg->stack_offset &= ~(size - 1);
 278                         info->offset = cfg->stack_offset;
 279                         cfg->stack_offset += size;
 280                 } else {
 281                         cfg->stack_offset += size - 1;
 282                         cfg->stack_offset &= ~(size - 1);
 283                         cfg->stack_offset += size;
 284                         info->offset = - cfg->stack_offset;
 285                 }
 286         }
 287
 288         return info->offset;
 289 }
 290
 291 #define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
 292 #define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
 293 #define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS & (regmask (r))))
 294 #define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (regmask (r))))
 295 #define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS & (regmask (r))))
 296 #define is_local_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_FREGS & (regmask (r))))
 297
 298 #define is_hard_reg(r,bank) (G_UNLIKELY (bank) ? ((r) >= 0 && (r) < regbank_size [bank]) : ((r) < MONO_MAX_IREGS))
 299 #define is_soft_reg(r,bank) (!is_hard_reg((r),(bank)))
 300 #define is_global_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_saved_regs [bank] & regmask (r))) : is_global_ireg (r))
 301 #define is_local_reg(r,bank) (G_UNLIKELY (bank) ? (is_hard_reg ((r), (bank)) && (regbank_callee_regs [bank] & regmask (r))) : is_local_ireg (r))
 302 #define reg_is_freeable(r,bank) (G_UNLIKELY (bank) ? is_local_reg ((r), (bank)) : is_local_ireg ((r)))
 303
 304 #ifndef MONO_ARCH_INST_IS_FLOAT
 305 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc) == 'f')
 306 #endif
 307
 308 #define reg_is_fp(desc) (MONO_ARCH_INST_IS_FLOAT (desc))
 309 #define dreg_is_fp(spec)  (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
 310 #define sreg1_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1]))
 311 #define sreg2_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC2]))
 312
 313 #define reg_is_simd(desc) ((desc) == 'x')
 314
 315 #ifdef MONO_ARCH_NEED_SIMD_BANK
 316
 317 #define reg_bank(desc) (G_UNLIKELY (reg_is_fp (desc)) ? MONO_REG_DOUBLE : G_UNLIKELY (reg_is_simd(desc)) ? MONO_REG_SIMD : MONO_REG_INT)
 318
 319 #else
 320
 321 #define reg_bank(desc) reg_is_fp ((desc))
 322
 323 #endif
 324
 325 #define sreg1_bank(spec) reg_bank ((spec)[MONO_INST_SRC1])
 326 #define sreg2_bank(spec) reg_bank ((spec)[MONO_INST_SRC2])
 327 #define dreg_bank(spec) reg_bank ((spec)[MONO_INST_DEST])
 328
 329 #define sreg1_bank_ins(ins) sreg1_bank (ins_get_spec ((ins)->opcode))
 330 #define sreg2_bank_ins(ins) sreg2_bank (ins_get_spec ((ins)->opcode))
 331 #define dreg_bank_ins(ins) dreg_bank (ins_get_spec ((ins)->opcode))
 332
 333 #define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) : MONO_ARCH_CALLEE_REGS)
 334
 335 #ifdef MONO_ARCH_IS_GLOBAL_IREG
 336 #undef is_global_ireg
 337 #define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
 338 #endif
 339
 340 typedef struct {
 341         int born_in;
 342         int killed_in;
 343         /* Not (yet) used */
 344         //int last_use;
 345         //int prev_use;
 346         regmask_t preferred_mask; /* the hreg where the register should be allocated, or 0 */
 347 } RegTrack;
 348
 349 #ifndef DISABLE_LOGGING
 350 void
 351 mono_print_ins_index (int i, MonoInst *ins)
 352 {
 353         const char *spec = ins_get_spec (ins->opcode);
 354
 355         if (i != -1)
 356                 printf ("\t%-2d %s", i, mono_inst_name (ins->opcode));
 357         else
 358                 printf (" %s", mono_inst_name (ins->opcode));
 359         if (spec == MONO_ARCH_CPU_SPEC) {
 360                 /* This is a lowered opcode */
 361                 if (ins->dreg != -1)
 362                         printf (" R%d <-", ins->dreg);
 363                 if (ins->sreg1 != -1)
 364                         printf (" R%d", ins->sreg1);
 365                 if (ins->sreg2 != -1)
 366                         printf (" R%d", ins->sreg2);
 367
 368                 switch (ins->opcode) {
 369                 case OP_LBNE_UN:
 370                 case OP_LBEQ:
 371                 case OP_LBLT:
 372                 case OP_LBLT_UN:
 373                 case OP_LBGT:
 374                 case OP_LBGT_UN:
 375                 case OP_LBGE:
 376                 case OP_LBGE_UN:
 377                 case OP_LBLE:
 378                 case OP_LBLE_UN:
 379                         if (!(ins->flags & MONO_INST_BRLABEL)) {
 380                                 if (!ins->inst_false_bb)
 381                                         printf (" [B%d]", ins->inst_true_bb->block_num);
 382                                 else
 383                                         printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 384                         }
 385                         break;
 386                 case OP_PHI:
 387                 case OP_FPHI: {
 388                         int i;
 389                         printf (" [%d (", (int)ins->inst_c0);
 390                         for (i = 0; i < ins->inst_phi_args [0]; i++) {
 391                                 if (i)
 392                                         printf (", ");
 393                                 printf ("R%d", ins->inst_phi_args [i + 1]);
 394                         }
 395                         printf (")]");
 396                         break;
 397                 }
 398                 case OP_LDADDR:
 399                 case OP_OUTARG_VTRETADDR:
 400                         printf (" R%d", ((MonoInst*)ins->inst_p0)->dreg);
 401                         break;
 402                 case OP_REGOFFSET:
 403                         printf (" + 0x%lx", (long)ins->inst_offset);
 404                 default:
 405                         break;
 406                 }
 407
 408                 printf ("\n");
 409                 //g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
 410                 return;
 411         }
 412
 413         if (spec [MONO_INST_DEST]) {
 414                 int bank = dreg_bank (spec);
 415                 if (is_soft_reg (ins->dreg, bank)) {
 416                         if (spec [MONO_INST_DEST] == 'b') {
 417                                 if (ins->inst_offset == 0)
 418                                         printf (" [R%d] <-", ins->dreg);
 419                                 else
 420                                         printf (" [R%d + 0x%lx] <-", ins->dreg, (long)ins->inst_offset);
 421                         }
 422                         else
 423                                 printf (" R%d <-", ins->dreg);
 424                 } else if (spec [MONO_INST_DEST] == 'b') {
 425                         if (ins->inst_offset == 0)
 426                                 printf (" [%s] <-", mono_arch_regname (ins->dreg));
 427                         else
 428                                 printf (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
 429                 } else
 430                         printf (" %s <-", mono_regname_full (ins->dreg, bank));
 431         }
 432         if (spec [MONO_INST_SRC1]) {
 433                 int bank = sreg1_bank (spec);
 434                 if (is_soft_reg (ins->sreg1, bank)) {
 435                         if (spec [MONO_INST_SRC1] == 'b')
 436                                 printf (" [R%d + 0x%lx]", ins->sreg1, (long)ins->inst_offset);
 437                         else
 438                                 printf (" R%d", ins->sreg1);
 439                 } else if (spec [MONO_INST_SRC1] == 'b')
 440                         printf (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
 441                 else
 442                         printf (" %s", mono_regname_full (ins->sreg1, bank));
 443         }
 444         if (spec [MONO_INST_SRC2]) {
 445                 int bank = sreg2_bank (spec);
 446                 if (is_soft_reg (ins->sreg2, bank))
 447                         printf (" R%d", ins->sreg2);
 448                 else
 449                         printf (" %s", mono_regname_full (ins->sreg2, bank));
 450         }
 451
 452         switch (ins->opcode) {
 453         case OP_ICONST:
 454                 printf (" [%d]", (int)ins->inst_c0);
 455                 break;
 456 #if defined(__i386__) || defined(__x86_64__)
 457         case OP_X86_PUSH_IMM:
 458 #endif
 459         case OP_ICOMPARE_IMM:
 460         case OP_COMPARE_IMM:
 461         case OP_IADD_IMM:
 462         case OP_ISUB_IMM:
 463         case OP_IAND_IMM:
 464         case OP_IOR_IMM:
 465         case OP_IXOR_IMM:
 466                 printf (" [%d]", (int)ins->inst_imm);
 467                 break;
 468         case OP_ADD_IMM:
 469         case OP_LADD_IMM:
 470                 printf (" [%d]", (int)(gssize)ins->inst_p1);
 471                 break;
 472         case OP_I8CONST:
 473                 printf (" [%lld]", (long long)ins->inst_l);
 474                 break;
 475         case OP_R8CONST:
 476                 printf (" [%f]", *(double*)ins->inst_p0);
 477                 break;
 478         case OP_R4CONST:
 479                 printf (" [%f]", *(float*)ins->inst_p0);
 480                 break;
 481         case CEE_CALL:
 482         case CEE_CALLVIRT:
 483         case OP_CALL:
 484         case OP_CALL_MEMBASE:
 485         case OP_CALL_REG:
 486         case OP_FCALL:
 487         case OP_FCALLVIRT:
 488         case OP_LCALL:
 489         case OP_LCALLVIRT:
 490         case OP_VCALL:
 491         case OP_VCALLVIRT:
 492         case OP_VCALL_REG:
 493         case OP_VCALL_MEMBASE:
 494         case OP_VCALL2:
 495         case OP_VCALL2_REG:
 496         case OP_VCALL2_MEMBASE:
 497         case OP_VOIDCALL:
 498         case OP_VOIDCALLVIRT: {
 499                 MonoCallInst *call = (MonoCallInst*)ins;
 500                 GSList *list;
 501
 502                 if (ins->opcode == OP_VCALL || ins->opcode == OP_VCALL_REG || ins->opcode == OP_VCALL_MEMBASE) {
 503                         /*
 504                          * These are lowered opcodes, but they are in the .md files since the old
 505                          * JIT passes them to backends.
 506                          */
 507                         if (ins->dreg != -1)
 508                                 printf (" R%d <-", ins->dreg);
 509                 }
 510
 511                 if (call->method) {
 512                         char *full_name = mono_method_full_name (call->method, TRUE);
 513                         printf (" [%s]", full_name);
 514                         g_free (full_name);
 515                 } else if (call->fptr) {
 516                         MonoJitICallInfo *info = mono_find_jit_icall_by_addr (call->fptr);
 517                         if (info)
 518                                 printf (" [%s]", info->name);
 519                 }
 520
 521                 list = call->out_ireg_args;
 522                 while (list) {
 523                         guint32 regpair;
 524                         int reg, hreg;
 525
 526                         regpair = (guint32)(gssize)(list->data);
 527                         hreg = regpair >> 24;
 528                         reg = regpair & 0xffffff;
 529
 530                         printf (" [%s <- R%d]", mono_arch_regname (hreg), reg);
 531
 532                         list = g_slist_next (list);
 533                 }
 534                 break;
 535         }
 536         case OP_BR:
 537         case OP_CALL_HANDLER:
 538                 printf (" [B%d]", ins->inst_target_bb->block_num);
 539                 break;
 540         case CEE_BNE_UN:
 541         case CEE_BEQ:
 542         case CEE_BLT:
 543         case CEE_BLT_UN:
 544         case CEE_BGT:
 545         case CEE_BGT_UN:
 546         case CEE_BGE:
 547         case CEE_BGE_UN:
 548         case CEE_BLE:
 549         case CEE_BLE_UN:
 550         case OP_IBNE_UN:
 551         case OP_IBEQ:
 552         case OP_IBLT:
 553         case OP_IBLT_UN:
 554         case OP_IBGT:
 555         case OP_IBGT_UN:
 556         case OP_IBGE:
 557         case OP_IBGE_UN:
 558         case OP_IBLE:
 559         case OP_IBLE_UN:
 560         case OP_LBNE_UN:
 561         case OP_LBEQ:
 562         case OP_LBLT:
 563         case OP_LBLT_UN:
 564         case OP_LBGT:
 565         case OP_LBGT_UN:
 566         case OP_LBGE:
 567         case OP_LBGE_UN:
 568         case OP_LBLE:
 569         case OP_LBLE_UN:
 570                 if (!(ins->flags & MONO_INST_BRLABEL)) {
 571                         if (!ins->inst_false_bb)
 572                                 printf (" [B%d]", ins->inst_true_bb->block_num);
 573                         else
 574                                 printf (" [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
 575                 }
 576                 break;
 577         default:
 578                 break;
 579         }
 580
 581         if (spec [MONO_INST_CLOB])
 582                 printf (" clobbers: %c", spec [MONO_INST_CLOB]);
 583         printf ("\n");
 584 }
 585
 586 static void
 587 print_regtrack (RegTrack *t, int num)
 588 {
 589         int i;
 590         char buf [32];
 591         const char *r;
 592
 593         for (i = 0; i < num; ++i) {
 594                 if (!t [i].born_in)
 595                         continue;
 596                 if (i >= MONO_MAX_IREGS) {
 597                         g_snprintf (buf, sizeof(buf), "R%d", i);
 598                         r = buf;
 599                 } else
 600                         r = mono_arch_regname (i);
 601                 printf ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].killed_in);
 602         }
 603 }
 604 #else
 605 void
 606 mono_print_ins_index (int i, MonoInst *ins)
 607 {
 608 }
 609 #endif /* DISABLE_LOGGING */
 610
 611 void
 612 mono_print_ins (MonoInst *ins)
 613 {
 614         mono_print_ins_index (-1, ins);
 615 }
 616
 617 static inline void
 618 insert_before_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst* to_insert)
 619 {
 620         /*
 621          * If this function is called multiple times, the new instructions are inserted
 622          * in the proper order.
 623          */
 624         mono_bblock_insert_before_ins (bb, ins, to_insert);
 625 }
 626
 627 static inline void
 628 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst **last, MonoInst* to_insert)
 629 {
 630         /*
 631          * If this function is called multiple times, the new instructions are inserted in
 632          * proper order.
 633          */
 634         mono_bblock_insert_after_ins (bb, *last, to_insert);
 635
 636         *last = to_insert;
 637 }
 638
 639 /*
 640  * Force the spilling of the variable in the symbolic register 'reg'.
 641  */
 642 static int
 643 get_register_force_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int reg, int bank)
 644 {
 645         MonoInst *load;
 646         int i, sel, spill;
 647         int *symbolic;
 648         MonoRegState *rs = cfg->rs;
 649
 650         symbolic = rs->symbolic [bank];
 651         sel = rs->vassign [reg];
 652
 653         /*i = rs->isymbolic [sel];
 654         g_assert (i == reg);*/
 655         i = reg;
 656         spill = ++cfg->spill_count;
 657         rs->vassign [i] = -spill - 1;
 658         if (G_UNLIKELY (bank))
 659                 mono_regstate_free_general (rs, sel, bank);
 660         else
 661                 mono_regstate_free_int (rs, sel);
 662         /* we need to create a spill var and insert a load to sel after the current instruction */
 663         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 664         load->dreg = sel;
 665         load->inst_basereg = cfg->frame_reg;
 666         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 667         insert_after_ins (bb, ins, last, load);
 668         DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 669         if (G_UNLIKELY (bank))
 670                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 671         else
 672                 i = mono_regstate_alloc_int (rs, regmask (sel));
 673         g_assert (i == sel);
 674
 675         return sel;
 676 }
 677
 678 /* This isn't defined on older glib versions and on some platforms */
 679 #ifndef G_GUINT64_FORMAT
 680 #define G_GUINT64_FORMAT "ul"
 681 #endif
 682
 683 static int
 684 get_register_spilling (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t regmask, int reg, int bank)
 685 {
 686         MonoInst *load;
 687         int i, sel, spill;
 688         int *symbolic;
 689         MonoRegState *rs = cfg->rs;
 690
 691         symbolic = rs->symbolic [bank];
 692
 693         g_assert (bank < MONO_NUM_REGBANKS);
 694
 695         DEBUG (printf ("\tstart regmask to assign R%d: 0x%08" G_GUINT64_FORMAT " (R%d <- R%d R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2));
 696         /* exclude the registers in the current instruction */
 697         if ((sreg1_bank_ins (ins) == bank) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, bank) || (is_soft_reg (ins->sreg1, bank) && rs->vassign [ins->sreg1] >= 0))) {
 698                 if (is_soft_reg (ins->sreg1, bank))
 699                         regmask &= ~ (regmask (rs->vassign [ins->sreg1]));
 700                 else
 701                         regmask &= ~ (regmask (ins->sreg1));
 702                 DEBUG (printf ("\t\texcluding sreg1 %s\n", mono_regname_full (ins->sreg1, bank)));
 703         }
 704         if ((sreg2_bank_ins (ins) == bank) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, bank) || (is_soft_reg (ins->sreg2, bank) && rs->vassign [ins->sreg2] >= 0))) {
 705                 if (is_soft_reg (ins->sreg2, bank))
 706                         regmask &= ~ (regmask (rs->vassign [ins->sreg2]));
 707                 else
 708                         regmask &= ~ (regmask (ins->sreg2));
 709                 DEBUG (printf ("\t\texcluding sreg2 %s %d\n", mono_regname_full (ins->sreg2, bank), ins->sreg2));
 710         }
 711         if ((dreg_bank_ins (ins) == bank) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, bank)) {
 712                 regmask &= ~ (regmask (ins->dreg));
 713                 DEBUG (printf ("\t\texcluding dreg %s\n", mono_regname_full (ins->dreg, bank)));
 714         }
 715
 716         DEBUG (printf ("\t\tavailable regmask: 0x%08" G_GUINT64_FORMAT "\n", (guint64)regmask));
 717         g_assert (regmask); /* need at least a register we can free */
 718         sel = 0;
 719         /* we should track prev_use and spill the register that's farther */
 720         if (G_UNLIKELY (bank)) {
 721                 for (i = 0; i < regbank_size [bank]; ++i) {
 722                         if (regmask & (regmask (i))) {
 723                                 sel = i;
 724                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_regname_full (sel, bank), rs->symbolic [bank] [sel]));
 725                                 break;
 726                         }
 727                 }
 728
 729                 i = rs->symbolic [bank] [sel];
 730                 spill = ++cfg->spill_count;
 731                 rs->vassign [i] = -spill - 1;
 732                 mono_regstate_free_general (rs, sel, bank);
 733         }
 734         else {
 735                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
 736                         if (regmask & (regmask (i))) {
 737                                 sel = i;
 738                                 DEBUG (printf ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), rs->isymbolic [sel]));
 739                                 break;
 740                         }
 741                 }
 742
 743                 i = rs->isymbolic [sel];
 744                 spill = ++cfg->spill_count;
 745                 rs->vassign [i] = -spill - 1;
 746                 mono_regstate_free_int (rs, sel);
 747         }
 748
 749         /* we need to create a spill var and insert a load to sel after the current instruction */
 750         MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
 751         load->dreg = sel;
 752         load->inst_basereg = cfg->frame_reg;
 753         load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 754         insert_after_ins (bb, ins, last, load);
 755         DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
 756         if (G_UNLIKELY (bank))
 757                 i = mono_regstate_alloc_general (rs, regmask (sel), bank);
 758         else
 759                 i = mono_regstate_alloc_int (rs, regmask (sel));
 760         g_assert (i == sel);
 761
 762         return sel;
 763 }
 764
 765 static void
 766 free_up_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
 767 {
 768         if (G_UNLIKELY (bank)) {
 769                 if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
 770                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
 771                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
 772                         mono_regstate_free_general (cfg->rs, hreg, bank);
 773                 }
 774         }
 775         else {
 776                 if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
 777                         DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->isymbolic [hreg]));
 778                         get_register_force_spilling (cfg, bb, last, ins, cfg->rs->isymbolic [hreg], bank);
 779                         mono_regstate_free_int (cfg->rs, hreg);
 780                 }
 781         }
 782 }
 783
 784 static MonoInst*
 785 create_copy_ins (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, int dest, int src, MonoInst *ins, const unsigned char *ip, int bank)
 786 {
 787         MonoInst *copy;
 788
 789         MONO_INST_NEW (cfg, copy, regbank_move_ops [bank]);
 790
 791         copy->dreg = dest;
 792         copy->sreg1 = src;
 793         copy->cil_code = ip;
 794         if (ins) {
 795                 mono_bblock_insert_after_ins (bb, ins, copy);
 796                 *last = copy;
 797         }
 798         DEBUG (printf ("\tforced copy from %s to %s\n", mono_regname_full (src, bank), mono_regname_full (dest, bank)));
 799         return copy;
 800 }
 801
 802 static MonoInst*
 803 create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
 804 {
 805         MonoInst *store;
 806         MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
 807         store->sreg1 = reg;
 808         store->inst_destbasereg = cfg->frame_reg;
 809         store->inst_offset = mono_spillvar_offset (cfg, spill, bank);
 810         if (ins) {
 811                 mono_bblock_insert_after_ins (bb, ins, store);
 812                 *last = store;
 813         }
 814         DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
 815         return store;
 816 }
 817
 818 /* flags used in reginfo->flags */
 819 enum {
 820         MONO_FP_NEEDS_LOAD_SPILL        = regmask (0),
 821         MONO_FP_NEEDS_SPILL                     = regmask (1),
 822         MONO_FP_NEEDS_LOAD                      = regmask (2)
 823 };
 824
 825 static inline int
 826 alloc_int_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info)
 827 {
 828         int val;
 829
 830         if (info && info->preferred_mask) {
 831                 val = mono_regstate_alloc_int (cfg->rs, info->preferred_mask & dest_mask);
 832                 if (val >= 0) {
 833                         DEBUG (printf ("\tallocated preferred reg R%d to %s\n", sym_reg, mono_arch_regname (val)));
 834                         return val;
 835                 }
 836         }
 837
 838         val = mono_regstate_alloc_int (cfg->rs, dest_mask);
 839         if (val < 0)
 840                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, 0);
 841
 842         return val;
 843 }
 844
 845 static inline int
 846 alloc_general_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, int bank)
 847 {
 848         int val;
 849
 850         val = mono_regstate_alloc_general (cfg->rs, dest_mask, bank);
 851
 852         if (val < 0)
 853                 val = get_register_spilling (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 854
 855         return val;
 856 }
 857
 858 static inline int
 859 alloc_reg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, regmask_t dest_mask, int sym_reg, RegTrack *info, int bank)
 860 {
 861         if (G_UNLIKELY (bank))
 862                 return alloc_general_reg (cfg, bb, last, ins, dest_mask, sym_reg, bank);
 863         else
 864                 return alloc_int_reg (cfg, bb, last, ins, dest_mask, sym_reg, info);
 865 }
 866
 867 static inline void
 868 assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, int bank)
 869 {
 870         if (G_UNLIKELY (bank)) {
 871                 g_assert (reg >= regbank_size [bank]);
 872                 g_assert (hreg < regbank_size [bank]);
 873                 g_assert (! is_global_freg (hreg));
 874
 875                 rs->vassign [reg] = hreg;
 876                 rs->symbolic [bank] [hreg] = reg;
 877                 rs->free_mask [bank] &= ~ (regmask (hreg));
 878         }
 879         else {
 880                 g_assert (reg >= MONO_MAX_IREGS);
 881                 g_assert (hreg < MONO_MAX_IREGS);
 882 #ifndef __arm__
 883                 /* this seems to trigger a gcc compilation bug sometime (hreg is 0) */
 884                 g_assert (! is_global_ireg (hreg));
 885 #endif
 886
 887                 rs->vassign [reg] = hreg;
 888                 rs->isymbolic [hreg] = reg;
 889                 rs->ifree_mask &= ~ (regmask (hreg));
 890         }
 891 }
 892
 893 static inline regmask_t
 894 get_callee_mask (const char spec)
 895 {
 896         if (G_UNLIKELY (reg_bank (spec)))
 897                 return regbank_callee_regs [reg_bank (spec)];
 898         return MONO_ARCH_CALLEE_REGS;
 899 }
 900
 901 static gint8 desc_to_fixed_reg [256];
 902 static gboolean desc_to_fixed_reg_inited = FALSE;
 903
 904 /*
 905  * Local register allocation.
 906  * We first scan the list of instructions and we save the liveness info of
 907  * each register (when the register is first used, when it's value is set etc.).
 908  * We also reverse the list of instructions because assigning registers backwards allows
 909  * for more tricks to be used.
 910  */
 911 void
 912 mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 913 {
 914         MonoInst *ins, *prev, *last;
 915         MonoInst **tmp;
 916         MonoRegState *rs = cfg->rs;
 917         int i, val, max;
 918         RegTrack *reginfo;
 919         const char *spec;
 920         unsigned char spec_src1, spec_src2, spec_dest;
 921         int bank = 0;
 922 #if MONO_ARCH_USE_FPSTACK
 923         gboolean has_fp = FALSE;
 924         int fpstack [8];
 925         int sp = 0;
 926 #endif
 927
 928         if (!bb->code)
 929                 return;
 930
 931         if (!desc_to_fixed_reg_inited) {
 932                 for (i = 0; i < 256; ++i)
 933                         desc_to_fixed_reg [i] = MONO_ARCH_INST_FIXED_REG (i);
 934                 desc_to_fixed_reg_inited = TRUE;
 935         }
 936
 937         rs->next_vreg = bb->max_vreg;
 938         mono_regstate_assign (rs);
 939
 940         rs->ifree_mask = MONO_ARCH_CALLEE_REGS;
 941         for (i = 0; i < MONO_NUM_REGBANKS; ++i)
 942                 rs->free_mask [i] = regbank_callee_regs [i];
 943
 944         max = rs->next_vreg;
 945
 946         if (cfg->reginfo && cfg->reginfo_len < max)
 947                 cfg->reginfo = NULL;
 948
 949         reginfo = cfg->reginfo;
 950         if (!reginfo) {
 951                 cfg->reginfo_len = MAX (1024, max * 2);
 952                 reginfo = cfg->reginfo = mono_mempool_alloc (cfg->mempool, sizeof (RegTrack) * cfg->reginfo_len);
 953         }
 954         else
 955                 g_assert (cfg->reginfo_len >= rs->next_vreg);
 956
 957         if (cfg->verbose_level > 1) {
 958                 /* print_regtrack reads the info of all variables */
 959                 memset (cfg->reginfo, 0, cfg->reginfo_len * sizeof (RegTrack));
 960         }
 961
 962         /*
 963          * For large methods, next_vreg can be very large, so g_malloc0 time can
 964          * be prohibitive. So we manually init the reginfo entries used by the
 965          * bblock.
 966          */
 967         for (ins = bb->code; ins; ins = ins->next) {
 968                 spec = ins_get_spec (ins->opcode);
 969
 970                 if ((ins->dreg != -1) && (ins->dreg < max)) {
 971                         memset (&reginfo [ins->dreg], 0, sizeof (RegTrack));
 972 #if SIZEOF_VOID_P == 4
 973                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
 974                                 /**
 975                                  * In the new IR, the two vregs of the regpair do not alias the
 976                                  * original long vreg. shift the vreg here so the rest of the
 977                                  * allocator doesn't have to care about it.
 978                                  */
 979                                 ins->dreg ++;
 980                                 memset (&reginfo [ins->dreg + 1], 0, sizeof (RegTrack));
 981                         }
 982 #endif
 983                 }
 984                 if ((ins->sreg1 != -1) && (ins->sreg1 < max)) {
 985                         memset (&reginfo [ins->sreg1], 0, sizeof (RegTrack));
 986 #if SIZEOF_VOID_P == 4
 987                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1])) {
 988                                 ins->sreg1 ++;
 989                                 memset (&reginfo [ins->sreg1 + 1], 0, sizeof (RegTrack));
 990                         }
 991 #endif
 992                 }
 993                 if ((ins->sreg2 != -1) && (ins->sreg2 < max)) {
 994                         memset (&reginfo [ins->sreg2], 0, sizeof (RegTrack));
 995 #if SIZEOF_VOID_P == 4
 996                         if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2])) {
 997                                 ins->sreg2 ++;
 998                                 memset (&reginfo [ins->sreg2 + 1], 0, sizeof (RegTrack));
 999                         }
1000 #endif
1001                 }
1002         }
1003
1004         /*if (cfg->opt & MONO_OPT_COPYPROP)
1005                 local_copy_prop (cfg, ins);*/
1006
1007         i = 1;
1008         DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
1009         /* forward pass on the instructions to collect register liveness info */
1010         MONO_BB_FOR_EACH_INS (bb, ins) {
1011                 spec = ins_get_spec (ins->opcode);
1012                 spec_src1 = spec [MONO_INST_SRC1];
1013                 spec_src2 = spec [MONO_INST_SRC2];
1014                 spec_dest = spec [MONO_INST_DEST];
1015
1016                 if (G_UNLIKELY (spec == MONO_ARCH_CPU_SPEC)) {
1017                         g_error ("Opcode '%s' missing from machine description file.", mono_inst_name (ins->opcode));
1018                 }
1019
1020                 DEBUG (mono_print_ins_index (i, ins));
1021
1022 #if MONO_ARCH_USE_FPSTACK
1023                 if (sreg1_is_fp (spec) || sreg2_is_fp (spec) || dreg_is_fp (spec))
1024                         has_fp = TRUE;
1025 #endif
1026
1027                 if (spec_src1) {
1028                         bank = sreg1_bank (spec);
1029                         g_assert (ins->sreg1 != -1);
1030                         if (is_soft_reg (ins->sreg1, bank))
1031                                 /* This means the vreg is not local to this bb */
1032                                 g_assert (reginfo [ins->sreg1].born_in > 0);
1033                         rs->vassign [ins->sreg1] = -1;
1034                         //reginfo [ins->sreg1].prev_use = reginfo [ins->sreg1].last_use;
1035                         //reginfo [ins->sreg1].last_use = i;
1036                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1037                                 /* The virtual register is allocated sequentially */
1038                                 rs->vassign [ins->sreg1 + 1] = -1;
1039                                 //reginfo [ins->sreg1 + 1].prev_use = reginfo [ins->sreg1 + 1].last_use;
1040                                 //reginfo [ins->sreg1 + 1].last_use = i;
1041                                 if (reginfo [ins->sreg1 + 1].born_in == 0 || reginfo [ins->sreg1 + 1].born_in > i)
1042                                         reginfo [ins->sreg1 + 1].born_in = i;
1043                         }
1044                 } else {
1045                         ins->sreg1 = -1;
1046                 }
1047                 if (spec_src2) {
1048                         bank = sreg2_bank (spec);
1049                         g_assert (ins->sreg2 != -1);
1050                         if (is_soft_reg (ins->sreg2, bank))
1051                                 /* This means the vreg is not local to this bb */
1052                                 g_assert (reginfo [ins->sreg2].born_in > 0);
1053                         rs->vassign [ins->sreg2] = -1;
1054                         //reginfo [ins->sreg2].prev_use = reginfo [ins->sreg2].last_use;
1055                         //reginfo [ins->sreg2].last_use = i;
1056                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src2)) {
1057                                 /* The virtual register is allocated sequentially */
1058                                 rs->vassign [ins->sreg2 + 1] = -1;
1059                                 //reginfo [ins->sreg2 + 1].prev_use = reginfo [ins->sreg2 + 1].last_use;
1060                                 //reginfo [ins->sreg2 + 1].last_use = i;
1061                                 if (reginfo [ins->sreg2 + 1].born_in == 0 || reginfo [ins->sreg2 + 1].born_in > i)
1062                                         reginfo [ins->sreg2 + 1].born_in = i;
1063                         }
1064                 } else {
1065                         ins->sreg2 = -1;
1066                 }
1067                 if (spec_dest) {
1068                         int dest_dreg;
1069
1070                         bank = dreg_bank (spec);
1071                         if (spec_dest != 'b') /* it's not just a base register */
1072                                 reginfo [ins->dreg].killed_in = i;
1073                         g_assert (ins->dreg != -1);
1074                         rs->vassign [ins->dreg] = -1;
1075                         //reginfo [ins->dreg].prev_use = reginfo [ins->dreg].last_use;
1076                         //reginfo [ins->dreg].last_use = i;
1077                         if (reginfo [ins->dreg].born_in == 0 || reginfo [ins->dreg].born_in > i)
1078                                 reginfo [ins->dreg].born_in = i;
1079
1080                         dest_dreg = desc_to_fixed_reg [spec_dest];
1081                         if (dest_dreg != -1)
1082                                 reginfo [ins->dreg].preferred_mask = (regmask (dest_dreg));
1083
1084 #ifdef MONO_ARCH_INST_FIXED_MASK
1085                         reginfo [ins->dreg].preferred_mask |= MONO_ARCH_INST_FIXED_MASK (spec_dest);
1086 #endif
1087
1088                         if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1089                                 /* The virtual register is allocated sequentially */
1090                                 rs->vassign [ins->dreg + 1] = -1;
1091                                 //reginfo [ins->dreg + 1].prev_use = reginfo [ins->dreg + 1].last_use;
1092                                 //reginfo [ins->dreg + 1].last_use = i;
1093                                 if (reginfo [ins->dreg + 1].born_in == 0 || reginfo [ins->dreg + 1].born_in > i)
1094                                         reginfo [ins->dreg + 1].born_in = i;
1095                                 if (MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, -1) != -1)
1096                                         reginfo [ins->dreg + 1].preferred_mask = regpair_reg2_mask (spec_dest, -1);
1097                         }
1098                 } else {
1099                         ins->dreg = -1;
1100                 }
1101
1102                 if (spec [MONO_INST_CLOB] == 'c') {
1103                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
1104
1105                         MonoCallInst *call = (MonoCallInst*)ins;
1106                         GSList *list;
1107
1108                         list = call->out_ireg_args;
1109                         if (list) {
1110                                 while (list) {
1111                                         guint32 regpair;
1112                                         int reg, hreg;
1113
1114                                         regpair = (guint32)(gssize)(list->data);
1115                                         hreg = regpair >> 24;
1116                                         reg = regpair & 0xffffff;
1117
1118                                         //reginfo [reg].prev_use = reginfo [reg].last_use;
1119                                         //reginfo [reg].last_use = i;
1120
1121                                         list = g_slist_next (list);
1122                                 }
1123                         }
1124
1125                         list = call->out_freg_args;
1126                         if (list) {
1127                                 while (list) {
1128                                         guint32 regpair;
1129                                         int reg, hreg;
1130
1131                                         regpair = (guint32)(gssize)(list->data);
1132                                         hreg = regpair >> 24;
1133                                         reg = regpair & 0xffffff;
1134
1135                                         list = g_slist_next (list);
1136                                 }
1137                         }
1138                 }
1139
1140                 ++i;
1141         }
1142
1143         tmp = &last;
1144
1145         DEBUG (print_regtrack (reginfo, rs->next_vreg));
1146         MONO_BB_FOR_EACH_INS_REVERSE_SAFE (bb, prev, ins) {
1147                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1148                 int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
1149                 int dreg_high, sreg1_high;
1150                 regmask_t dreg_mask, sreg1_mask, sreg2_mask, mask;
1151                 regmask_t dreg_fixed_mask, sreg1_fixed_mask, sreg2_fixed_mask;
1152                 const unsigned char *ip;
1153                 --i;
1154                 spec = ins_get_spec (ins->opcode);
1155                 spec_src1 = spec [MONO_INST_SRC1];
1156                 spec_src2 = spec [MONO_INST_SRC2];
1157                 spec_dest = spec [MONO_INST_DEST];
1158                 prev_dreg = -1;
1159                 prev_sreg2 = -1;
1160                 clob_dreg = -1;
1161                 clob_reg = -1;
1162                 dest_dreg = -1;
1163                 dest_sreg1 = -1;
1164                 dest_sreg2 = -1;
1165                 prev_sreg1 = -1;
1166                 dreg_high = -1;
1167                 sreg1_high = -1;
1168                 dreg_mask = get_callee_mask (spec_dest);
1169                 sreg1_mask = get_callee_mask (spec_src1);
1170                 sreg2_mask = get_callee_mask (spec_src2);
1171
1172                 DEBUG (printf ("processing:"));
1173                 DEBUG (mono_print_ins_index (i, ins));
1174
1175                 ip = ins->cil_code;
1176
1177                 last = ins;
1178
1179                 /*
1180                  * FIXED REGS
1181                  */
1182                 dest_sreg1 = desc_to_fixed_reg [spec_src1];
1183                 dest_sreg2 = desc_to_fixed_reg [spec_src2];
1184                 dest_dreg = desc_to_fixed_reg [spec_dest];
1185                 clob_reg = desc_to_fixed_reg [(int)spec [MONO_INST_CLOB]];
1186                 sreg2_mask &= ~ (MONO_ARCH_INST_SREG2_MASK (spec));
1187
1188 #ifdef MONO_ARCH_INST_FIXED_MASK
1189                 sreg1_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src1);
1190                 sreg2_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_src2);
1191                 dreg_fixed_mask = MONO_ARCH_INST_FIXED_MASK (spec_dest);
1192 #else
1193                 sreg1_fixed_mask = sreg2_fixed_mask = dreg_fixed_mask = 0;
1194 #endif
1195
1196                 /*
1197                  * TRACK FIXED SREG2
1198                  */
1199                 if (dest_sreg2 != -1) {
1200                         if (rs->ifree_mask & (regmask (dest_sreg2))) {
1201                                 if (is_global_ireg (ins->sreg2)) {
1202                                         /* Argument already in hard reg, need to copy */
1203                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1204                                         insert_before_ins (bb, ins, copy);
1205                                 }
1206                                 else {
1207                                         val = rs->vassign [ins->sreg2];
1208                                         if (val == -1) {
1209                                                 DEBUG (printf ("\tshortcut assignment of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
1210                                                 assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1211                                         } else if (val < -1) {
1212                                                 /* FIXME: */
1213                                                 g_assert_not_reached ();
1214                                         } else {
1215                                                 /* Argument already in hard reg, need to copy */
1216                                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, val, NULL, ip, 0);
1217                                                 insert_before_ins (bb, ins, copy);
1218                                         }
1219                                 }
1220                         } else {
1221                                 gboolean need_spill = TRUE;
1222                                 gboolean need_assign = TRUE;
1223
1224                                 dreg_mask &= ~ (regmask (dest_sreg2));
1225                                 sreg1_mask &= ~ (regmask (dest_sreg2));
1226
1227                                 /*
1228                                  * First check if dreg is assigned to dest_sreg2, since we
1229                                  * can't spill a dreg.
1230                                  */
1231                                 val = rs->vassign [ins->dreg];
1232                                 if (val == dest_sreg2 && ins->dreg != ins->sreg2) {
1233                                         /*
1234                                          * the destination register is already assigned to
1235                                          * dest_sreg2: we need to allocate another register for it
1236                                          * and then copy from this to dest_sreg2.
1237                                          */
1238                                         int new_dest;
1239                                         new_dest = alloc_int_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg]);
1240                                         g_assert (new_dest >= 0);
1241                                         DEBUG (printf ("\tchanging dreg R%d to %s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname (dest_sreg2)));
1242
1243                                         prev_dreg = ins->dreg;
1244                                         assign_reg (cfg, rs, ins->dreg, new_dest, 0);
1245                                         clob_dreg = ins->dreg;
1246                                         create_copy_ins (cfg, bb, tmp, dest_sreg2, new_dest, ins, ip, 0);
1247                                         mono_regstate_free_int (rs, dest_sreg2);
1248                                         need_spill = FALSE;
1249                                 }
1250
1251                                 if (is_global_ireg (ins->sreg2)) {
1252                                         MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg2, ins->sreg2, NULL, ip, 0);
1253                                         insert_before_ins (bb, ins, copy);
1254                                         need_assign = FALSE;
1255                                 }
1256                                 else {
1257                                         val = rs->vassign [ins->sreg2];
1258                                         if (val == dest_sreg2) {
1259                                                 /* sreg2 is already assigned to the correct register */
1260                                                 need_spill = FALSE;
1261                                         } else if (val < -1) {
1262                                                 /* sreg2 is spilled, it can be assigned to dest_sreg2 */
1263                                         } else if (val >= 0) {
1264                                                 /* sreg2 already assigned to another register */
1265                                                 /*
1266                                                  * We couldn't emit a copy from val to dest_sreg2, because
1267                                                  * val might be spilled later while processing this
1268                                                  * instruction. So we spill sreg2 so it can be allocated to
1269                                                  * dest_sreg2.
1270                                                  */
1271                                                 DEBUG (printf ("\tforced spill of R%d\n", ins->sreg2));
1272                                                 free_up_reg (cfg, bb, tmp, ins, val, 0);
1273                                         }
1274                                 }
1275
1276                                 if (need_spill) {
1277                                         DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg2]));
1278                                         free_up_reg (cfg, bb, tmp, ins, dest_sreg2, 0);
1279                                 }
1280
1281                                 if (need_assign) {
1282                                         if (rs->vassign [ins->sreg2] < -1) {
1283                                                 MonoInst *store;
1284                                                 int spill;
1285
1286                                                 /* Need to emit a spill store */
1287                                                 spill = - rs->vassign [ins->sreg2] - 1;
1288                                                 store = create_spilled_store (cfg, bb, spill, dest_sreg2, ins->sreg2, tmp, NULL, bank);
1289                                                 insert_before_ins (bb, ins, store);
1290                                         }
1291                                         /* force-set sreg2 */
1292                                         assign_reg (cfg, rs, ins->sreg2, dest_sreg2, 0);
1293                                 }
1294                         }
1295                         ins->sreg2 = dest_sreg2;
1296                 }
1297
1298                 /*
1299                  * TRACK DREG
1300                  */
1301                 bank = dreg_bank (spec);
1302                 if (spec_dest && is_soft_reg (ins->dreg, bank)) {
1303                         prev_dreg = ins->dreg;
1304                 }
1305
1306                 if (spec_dest == 'b') {
1307                         /*
1308                          * The dest reg is read by the instruction, not written, so
1309                          * avoid allocating sreg1/sreg2 to the same reg.
1310                          */
1311                         if (!dest_sreg1 != -1)
1312                                 dreg_mask &= ~ (regmask (dest_sreg1));
1313                         if (dest_sreg2 != -1)
1314                                 dreg_mask &= ~ (regmask (dest_sreg2));
1315
1316                         val = rs->vassign [ins->dreg];
1317                         if (is_soft_reg (ins->dreg, bank) && (val >= 0) && (!(regmask (val) & dreg_mask))) {
1318                                 /* DREG is already allocated to a register needed for sreg1 */
1319                                 get_register_force_spilling (cfg, bb, tmp, ins, ins->dreg, 0);
1320                                 mono_regstate_free_int (rs, val);
1321                         }
1322                 }
1323
1324                 /*
1325                  * If dreg is a fixed regpair, free up both of the needed hregs to avoid
1326                  * various complex situations.
1327                  */
1328                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1329                         guint32 dreg2, dest_dreg2;
1330
1331                         g_assert (is_soft_reg (ins->dreg, bank));
1332
1333                         if (dest_dreg != -1) {
1334                                 if (rs->vassign [ins->dreg] != dest_dreg)
1335                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, 0);
1336
1337                                 dreg2 = ins->dreg + 1;
1338                                 dest_dreg2 = MONO_ARCH_INST_REGPAIR_REG2 (spec_dest, dest_dreg);
1339                                 if (dest_dreg2 != -1) {
1340                                         if (rs->vassign [dreg2] != dest_dreg2)
1341                                                 free_up_reg (cfg, bb, tmp, ins, dest_dreg2, 0);
1342                                 }
1343                         }
1344                 }
1345
1346                 if (dreg_fixed_mask) {
1347                         g_assert (!bank);
1348                         if (is_global_ireg (ins->dreg)) {
1349                                 /*
1350                                  * The argument is already in a hard reg, but that reg is
1351                                  * not usable by this instruction, so allocate a new one.
1352                                  */
1353                                 val = mono_regstate_alloc_int (rs, dreg_fixed_mask);
1354                                 if (val < 0)
1355                                         val = get_register_spilling (cfg, bb, tmp, ins, dreg_fixed_mask, -1, bank);
1356                                 mono_regstate_free_int (rs, val);
1357                                 dest_dreg = val;
1358
1359                                 /* Fall through */
1360                         }
1361                         else
1362                                 dreg_mask &= dreg_fixed_mask;
1363                 }
1364
1365                 if (is_soft_reg (ins->dreg, bank)) {
1366                         val = rs->vassign [ins->dreg];
1367
1368                         if (val < 0) {
1369                                 int spill = 0;
1370                                 if (val < -1) {
1371                                         /* the register gets spilled after this inst */
1372                                         spill = -val -1;
1373                                 }
1374                                 val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, &reginfo [ins->dreg], bank);
1375                                 assign_reg (cfg, rs, ins->dreg, val, bank);
1376                                 if (spill)
1377                                         create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
1378                         }
1379
1380                         DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
1381                         ins->dreg = val;
1382                 }
1383
1384                 /* Handle regpairs */
1385                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest)) {
1386                         int reg2 = prev_dreg + 1;
1387
1388                         g_assert (!bank);
1389                         g_assert (prev_dreg > -1);
1390                         g_assert (!is_global_ireg (rs->vassign [prev_dreg]));
1391                         mask = regpair_reg2_mask (spec_dest, rs->vassign [prev_dreg]);
1392 #ifdef __i386__
1393                         /* bug #80489 */
1394                         mask &= ~regmask (X86_ECX);
1395 #endif
1396                         val = rs->vassign [reg2];
1397                         if (val < 0) {
1398                                 int spill = 0;
1399                                 if (val < -1) {
1400                                         /* the register gets spilled after this inst */
1401                                         spill = -val -1;
1402                                 }
1403                                 val = mono_regstate_alloc_int (rs, mask);
1404                                 if (val < 0)
1405                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1406                                 if (spill)
1407                                         create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
1408                         }
1409                         else {
1410                                 if (! (mask & (regmask (val)))) {
1411                                         val = mono_regstate_alloc_int (rs, mask);
1412                                         if (val < 0)
1413                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1414
1415                                         /* Reallocate hreg to the correct register */
1416                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1417
1418                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1419                                 }
1420                         }
1421
1422                         DEBUG (printf ("\tassigned dreg-high %s to dest R%d\n", mono_arch_regname (val), reg2));
1423                         assign_reg (cfg, rs, reg2, val, bank);
1424
1425                         dreg_high = val;
1426                         ins->backend.reg3 = val;
1427
1428                         if (reg_is_freeable (val, bank) && reg2 >= 0 && (reginfo [reg2].born_in >= i)) {
1429                                 DEBUG (printf ("\tfreeable %s (R%d)\n", mono_arch_regname (val), reg2));
1430                                 mono_regstate_free_int (rs, val);
1431                         }
1432                 }
1433
1434                 if (prev_dreg >= 0 && is_soft_reg (prev_dreg, bank) && (spec_dest != 'b')) {
1435                         /*
1436                          * In theory, we could free up the hreg even if the vreg is alive,
1437                          * but branches inside bblocks force us to assign the same hreg
1438                          * to a vreg every time it is encountered.
1439                          */
1440                         int dreg = rs->vassign [prev_dreg];
1441                         g_assert (dreg >= 0);
1442                         DEBUG (printf ("\tfreeable %s (R%d) (born in %d)\n", mono_regname_full (dreg, bank), prev_dreg, reginfo [prev_dreg].born_in));
1443                         if (G_UNLIKELY (bank))
1444                                 mono_regstate_free_general (rs, dreg, bank);
1445                         else
1446                                 mono_regstate_free_int (rs, dreg);
1447                         rs->vassign [prev_dreg] = -1;
1448                 }
1449
1450                 if ((dest_dreg != -1) && (ins->dreg != dest_dreg)) {
1451                         /* this instruction only outputs to dest_dreg, need to copy */
1452                         create_copy_ins (cfg, bb, tmp, ins->dreg, dest_dreg, ins, ip, bank);
1453                         ins->dreg = dest_dreg;
1454
1455                         if (G_UNLIKELY (bank)) {
1456                                 if (rs->symbolic [bank] [dest_dreg] >= regbank_size [bank])
1457                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1458                         }
1459                         else {
1460                                 if (rs->isymbolic [dest_dreg] >= MONO_MAX_IREGS)
1461                                         free_up_reg (cfg, bb, tmp, ins, dest_dreg, bank);
1462                         }
1463                 }
1464
1465                 if (spec_dest == 'b') {
1466                         /*
1467                          * The dest reg is read by the instruction, not written, so
1468                          * avoid allocating sreg1/sreg2 to the same reg.
1469                          */
1470                         if (!sreg1_bank (spec))
1471                                 sreg1_mask &= ~ (regmask (ins->dreg));
1472                         if (!sreg2_bank (spec))
1473                                 sreg2_mask &= ~ (regmask (ins->dreg));
1474                 }
1475
1476                 /*
1477                  * TRACK CLOBBERING
1478                  */
1479                 if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask (clob_reg))))) {
1480                         DEBUG (printf ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1481                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [clob_reg], 0);
1482                         mono_regstate_free_int (rs, clob_reg);
1483                 }
1484
1485                 if (spec [MONO_INST_CLOB] == 'c') {
1486                         int j, s, dreg, dreg2, cur_bank;
1487                         guint64 clob_mask;
1488
1489                         clob_mask = MONO_ARCH_CALLEE_REGS;
1490
1491                         if (rs->ifree_mask != MONO_ARCH_CALLEE_REGS) {
1492                                 /*
1493                                  * Need to avoid spilling the dreg since the dreg is not really
1494                                  * clobbered by the call.
1495                                  */
1496                                 if ((prev_dreg != -1) && !reg_bank (spec_dest))
1497                                         dreg = rs->vassign [prev_dreg];
1498                                 else
1499                                         dreg = -1;
1500
1501                                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest))
1502                                         dreg2 = rs->vassign [prev_dreg + 1];
1503                                 else
1504                                         dreg2 = -1;
1505
1506                                 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1507                                         s = regmask (j);
1508                                         if ((clob_mask & s) && !(rs->ifree_mask & s) && (j != ins->sreg1)) {
1509                                                 if ((j != dreg) && (j != dreg2))
1510                                                         get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [j], 0);
1511                                                 else if (rs->isymbolic [j])
1512                                                         /* The hreg is assigned to the dreg of this instruction */
1513                                                         rs->vassign [rs->isymbolic [j]] = -1;
1514                                                 mono_regstate_free_int (rs, j);
1515                                         }
1516                                 }
1517                         }
1518
1519                         for (cur_bank = 1; cur_bank < MONO_NUM_REGBANKS; ++ cur_bank) {
1520                                 if (rs->free_mask [cur_bank] != regbank_callee_regs [cur_bank]) {
1521                                         clob_mask = regbank_callee_regs [cur_bank];
1522                                         if ((prev_dreg != -1) && reg_bank (spec_dest))
1523                                                 dreg = rs->vassign [prev_dreg];
1524                                         else
1525                                                 dreg = -1;
1526
1527                                         for (j = 0; j < regbank_size [cur_bank]; ++j) {
1528                                                 s = regmask (j);
1529                                                 if ((clob_mask & s) && !(rs->free_mask [cur_bank] & s) && (j != ins->sreg1)) {
1530                                                         if (j != dreg)
1531                                                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->symbolic [cur_bank] [j], cur_bank);
1532                                                         else if (rs->symbolic [cur_bank] [j])
1533                                                                 /* The hreg is assigned to the dreg of this instruction */
1534                                                                 rs->vassign [rs->symbolic [cur_bank] [j]] = -1;
1535                                                         mono_regstate_free_general (rs, j, cur_bank);
1536                                                 }
1537                                         }
1538                                 }
1539                         }
1540                 }
1541
1542                 /*
1543                  * TRACK ARGUMENT REGS
1544                  */
1545                 if (spec [MONO_INST_CLOB] == 'c') {
1546                         MonoCallInst *call = (MonoCallInst*)ins;
1547                         GSList *list;
1548
1549                         /*
1550                          * This needs to be done before assigning sreg1, so sreg1 will
1551                          * not be assigned one of the argument regs.
1552                          */
1553
1554                         /*
1555                          * Assign all registers in call->out_reg_args to the proper
1556                          * argument registers.
1557                          */
1558
1559                         list = call->out_ireg_args;
1560                         if (list) {
1561                                 while (list) {
1562                                         guint32 regpair;
1563                                         int reg, hreg;
1564
1565                                         regpair = (guint32)(gssize)(list->data);
1566                                         hreg = regpair >> 24;
1567                                         reg = regpair & 0xffffff;
1568
1569                                         assign_reg (cfg, rs, reg, hreg, 0);
1570
1571                                         sreg1_mask &= ~(regmask (hreg));
1572
1573                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
1574
1575                                         list = g_slist_next (list);
1576                                 }
1577                         }
1578
1579                         list = call->out_freg_args;
1580                         if (list) {
1581                                 while (list) {
1582                                         guint32 regpair;
1583                                         int reg, hreg;
1584
1585                                         regpair = (guint32)(gssize)(list->data);
1586                                         hreg = regpair >> 24;
1587                                         reg = regpair & 0xffffff;
1588
1589                                         assign_reg (cfg, rs, reg, hreg, 1);
1590
1591                                         DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
1592
1593                                         list = g_slist_next (list);
1594                                 }
1595                         }
1596                 }
1597
1598                 /*
1599                  * TRACK SREG1
1600                  */
1601                 bank = sreg1_bank (spec);
1602                 if (MONO_ARCH_INST_IS_REGPAIR (spec_dest) && (spec [MONO_INST_CLOB] == '1')) {
1603                         g_assert (is_soft_reg (ins->sreg1, bank));
1604
1605                         /* To simplify things, we allocate the same regpair to sreg1 and dreg */
1606                         if (dest_sreg1 != -1)
1607                                 g_assert (dest_sreg1 == ins->dreg);
1608                         val = mono_regstate_alloc_int (rs, regmask (ins->dreg));
1609                         g_assert (val >= 0);
1610
1611                         if (rs->vassign [ins->sreg1] >= 0 && rs->vassign [ins->sreg1] != val)
1612                                 // FIXME:
1613                                 g_assert_not_reached ();
1614
1615                         assign_reg (cfg, rs, ins->sreg1, val, bank);
1616
1617                         DEBUG (printf ("\tassigned sreg1-low %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1618
1619                         g_assert ((regmask (dreg_high)) & regpair_reg2_mask (spec_src1, ins->dreg));
1620                         val = mono_regstate_alloc_int (rs, regmask (dreg_high));
1621                         g_assert (val >= 0);
1622
1623                         if (rs->vassign [ins->sreg1 + 1] >= 0 && rs->vassign [ins->sreg1 + 1] != val)
1624                                 // FIXME:
1625                                 g_assert_not_reached ();
1626
1627                         assign_reg (cfg, rs, ins->sreg1 + 1, val, bank);
1628
1629                         DEBUG (printf ("\tassigned sreg1-high %s to R%d\n", mono_regname_full (val, bank), ins->sreg1 + 1));
1630
1631                         /* Skip rest of this section */
1632                         dest_sreg1 = -1;
1633                 }
1634
1635                 if (sreg1_fixed_mask) {
1636                         g_assert (!bank);
1637                         if (is_global_ireg (ins->sreg1)) {
1638                                 /*
1639                                  * The argument is already in a hard reg, but that reg is
1640                                  * not usable by this instruction, so allocate a new one.
1641                                  */
1642                                 val = mono_regstate_alloc_int (rs, sreg1_fixed_mask);
1643                                 if (val < 0)
1644                                         val = get_register_spilling (cfg, bb, tmp, ins, sreg1_fixed_mask, -1, bank);
1645                                 mono_regstate_free_int (rs, val);
1646                                 dest_sreg1 = val;
1647
1648                                 /* Fall through to the dest_sreg1 != -1 case */
1649                         }
1650                         else
1651                                 sreg1_mask &= sreg1_fixed_mask;
1652                 }
1653
1654                 if (dest_sreg1 != -1) {
1655                         sreg1_mask = regmask (dest_sreg1);
1656
1657                         if ((rs->vassign [ins->sreg1] != dest_sreg1) && !(rs->ifree_mask & (regmask (dest_sreg1)))) {
1658                                 DEBUG (printf ("\tforced spill of R%d\n", rs->isymbolic [dest_sreg1]));
1659                                 get_register_force_spilling (cfg, bb, tmp, ins, rs->isymbolic [dest_sreg1], 0);
1660                                 mono_regstate_free_int (rs, dest_sreg1);
1661                         }
1662                         if (is_global_ireg (ins->sreg1)) {
1663                                 /* The argument is already in a hard reg, need to copy */
1664                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, ins->sreg1, NULL, ip, 0);
1665                                 insert_before_ins (bb, ins, copy);
1666                                 ins->sreg1 = dest_sreg1;
1667                         }
1668                 }
1669
1670                 if (is_soft_reg (ins->sreg1, bank)) {
1671                         val = rs->vassign [ins->sreg1];
1672                         prev_sreg1 = ins->sreg1;
1673                         if (val < 0) {
1674                                 int spill = 0;
1675                                 if (val < -1) {
1676                                         /* the register gets spilled after this inst */
1677                                         spill = -val -1;
1678                                 }
1679
1680                                 if ((ins->opcode == OP_MOVE) && !spill && !bank && is_local_ireg (ins->dreg) && (rs->ifree_mask & (regmask (ins->dreg)))) {
1681                                         /*
1682                                          * Allocate the same hreg to sreg1 as well so the
1683                                          * peephole can get rid of the move.
1684                                          */
1685                                         sreg1_mask = regmask (ins->dreg);
1686                                 }
1687
1688                                 if (spec [MONO_INST_CLOB] == '1' && !dreg_bank (spec) && (rs->ifree_mask & (regmask (ins->dreg))))
1689                                         /* Allocate the same reg to sreg1 to avoid a copy later */
1690                                         sreg1_mask = regmask (ins->dreg);
1691
1692                                 val = alloc_reg (cfg, bb, tmp, ins, sreg1_mask, ins->sreg1, &reginfo [ins->sreg1], bank);
1693                                 assign_reg (cfg, rs, ins->sreg1, val, bank);
1694                                 DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), ins->sreg1));
1695
1696                                 if (spill) {
1697                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg1, tmp, NULL, bank);
1698                                         /*
1699                                          * Need to insert before the instruction since it can
1700                                          * overwrite sreg1.
1701                                          */
1702                                         insert_before_ins (bb, ins, store);
1703                                 }
1704                         }
1705                         else if ((dest_sreg1 != -1) && (dest_sreg1 != val)) {
1706                                 MonoInst *copy = create_copy_ins (cfg, bb, tmp, dest_sreg1, val, NULL, ip, bank);
1707                                 insert_before_ins (bb, ins, copy);
1708                                 sreg2_mask &= ~(regmask (dest_sreg1));
1709                                 val = dest_sreg1;
1710                         }
1711
1712                         ins->sreg1 = val;
1713                 }
1714                 else {
1715                         prev_sreg1 = -1;
1716                 }
1717                 sreg2_mask &= ~(regmask (ins->sreg1));
1718
1719                 /* Handle the case when sreg1 is a regpair but dreg is not */
1720                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src1) && (spec [MONO_INST_CLOB] != '1')) {
1721                         int reg2 = prev_sreg1 + 1;
1722
1723                         g_assert (!bank);
1724                         g_assert (prev_sreg1 > -1);
1725                         g_assert (!is_global_ireg (rs->vassign [prev_sreg1]));
1726                         mask = regpair_reg2_mask (spec_src1, rs->vassign [prev_sreg1]);
1727                         val = rs->vassign [reg2];
1728                         if (val < 0) {
1729                                 int spill = 0;
1730                                 if (val < -1) {
1731                                         /* the register gets spilled after this inst */
1732                                         spill = -val -1;
1733                                 }
1734                                 val = mono_regstate_alloc_int (rs, mask);
1735                                 if (val < 0)
1736                                         val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1737                                 if (spill)
1738                                         g_assert_not_reached ();
1739                         }
1740                         else {
1741                                 if (! (mask & (regmask (val)))) {
1742                                         /* The vreg is already allocated to a wrong hreg */
1743                                         /* FIXME: */
1744                                         g_assert_not_reached ();
1745 #if 0
1746                                         val = mono_regstate_alloc_int (rs, mask);
1747                                         if (val < 0)
1748                                                 val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
1749
1750                                         /* Reallocate hreg to the correct register */
1751                                         create_copy_ins (cfg, bb, tmp, rs->vassign [reg2], val, ins, ip, bank);
1752
1753                                         mono_regstate_free_int (rs, rs->vassign [reg2]);
1754 #endif
1755                                 }
1756                         }
1757
1758                         sreg1_high = val;
1759                         DEBUG (printf ("\tassigned sreg1 hreg %s to dest R%d\n", mono_arch_regname (val), reg2));
1760                         assign_reg (cfg, rs, reg2, val, bank);
1761                 }
1762
1763                 /* Handle dreg==sreg1 */
1764                 if (((dreg_is_fp (spec) && sreg1_is_fp (spec)) || spec [MONO_INST_CLOB] == '1') && ins->dreg != ins->sreg1) {
1765                         MonoInst *sreg2_copy = NULL;
1766                         MonoInst *copy;
1767                         int bank = reg_bank (spec_src1);
1768
1769                         if (ins->dreg == ins->sreg2) {
1770                                 /*
1771                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
1772                                  * register for it.
1773                                  */
1774                                 int reg2 = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->sreg2, NULL, bank);
1775
1776                                 DEBUG (printf ("\tneed to copy sreg2 %s to reg %s\n", mono_regname_full (ins->sreg2, bank), mono_regname_full (reg2, bank)));
1777                                 sreg2_copy = create_copy_ins (cfg, bb, tmp, reg2, ins->sreg2, NULL, ip, bank);
1778                                 prev_sreg2 = ins->sreg2 = reg2;
1779
1780                                 if (G_UNLIKELY (bank))
1781                                         mono_regstate_free_general (rs, reg2, bank);
1782                                 else
1783                                         mono_regstate_free_int (rs, reg2);
1784                         }
1785
1786                         if (MONO_ARCH_INST_IS_REGPAIR (spec_src1)) {
1787                                 /* Copying sreg1_high to dreg could also clobber sreg2 */
1788                                 if (rs->vassign [prev_sreg1 + 1] == ins->sreg2)
1789                                         /* FIXME: */
1790                                         g_assert_not_reached ();
1791
1792                                 /*
1793                                  * sreg1 and dest are already allocated to the same regpair by the
1794                                  * SREG1 allocation code.
1795                                  */
1796                                 g_assert (ins->sreg1 == ins->dreg);
1797                                 g_assert (dreg_high == sreg1_high);
1798                         }
1799
1800                         DEBUG (printf ("\tneed to copy sreg1 %s to dreg %s\n", mono_regname_full (ins->sreg1, bank), mono_regname_full (ins->dreg, bank)));
1801                         copy = create_copy_ins (cfg, bb, tmp, ins->dreg, ins->sreg1, NULL, ip, bank);
1802                         insert_before_ins (bb, ins, copy);
1803
1804                         if (sreg2_copy)
1805                                 insert_before_ins (bb, copy, sreg2_copy);
1806
1807                         /*
1808                          * Need to prevent sreg2 to be allocated to sreg1, since that
1809                          * would screw up the previous copy.
1810                          */
1811                         sreg2_mask &= ~ (regmask (ins->sreg1));
1812                         /* we set sreg1 to dest as well */
1813                         prev_sreg1 = ins->sreg1 = ins->dreg;
1814                         sreg2_mask &= ~ (regmask (ins->dreg));
1815                 }
1816
1817                 /*
1818                  * TRACK SREG2
1819                  */
1820                 bank = sreg2_bank (spec);
1821                 if (MONO_ARCH_INST_IS_REGPAIR (spec_src2))
1822                         g_assert_not_reached ();
1823                 if (is_soft_reg (ins->sreg2, bank)) {
1824                         val = rs->vassign [ins->sreg2];
1825
1826                         if (val < 0) {
1827                                 int spill = 0;
1828                                 if (val < -1) {
1829                                         /* the register gets spilled after this inst */
1830                                         spill = -val -1;
1831                                 }
1832                                 val = alloc_reg (cfg, bb, tmp, ins, sreg2_mask, ins->sreg2, &reginfo [ins->sreg2], bank);
1833                                 assign_reg (cfg, rs, ins->sreg2, val, bank);
1834                                 DEBUG (printf ("\tassigned sreg2 %s to R%d\n", mono_regname_full (val, bank), ins->sreg2));
1835                                 if (spill) {
1836                                         MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sreg2, tmp, NULL, bank);
1837                                         /*
1838                                          * Need to insert before the instruction since it can
1839                                          * overwrite sreg2.
1840                                          */
1841                                         insert_before_ins (bb, ins, store);
1842                                 }
1843                         }
1844                         ins->sreg2 = val;
1845                 }
1846                 else {
1847                         prev_sreg2 = -1;
1848                 }
1849
1850                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1851                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1852                         mono_regstate_free_int (rs, ins->sreg1);
1853                 }
1854                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1855                         DEBUG (printf ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1856                         mono_regstate_free_int (rs, ins->sreg2);
1857                 }*/
1858
1859                 DEBUG (mono_print_ins_index (i, ins));
1860         }
1861
1862         // FIXME: Set MAX_FREGS to 8
1863         // FIXME: Optimize generated code
1864 #if MONO_ARCH_USE_FPSTACK
1865         /*
1866          * Make a forward pass over the code, simulating the fp stack, making sure the
1867          * arguments required by the fp opcodes are at the top of the stack.
1868          */
1869         if (has_fp) {
1870                 MonoInst *prev = NULL;
1871                 MonoInst *fxch;
1872                 int tmp;
1873
1874                 for (ins = bb->code; ins; ins = ins->next) {
1875                         spec = ins_get_spec (ins->opcode);
1876
1877                         DEBUG (printf ("processing:"));
1878                         DEBUG (mono_print_ins_index (0, ins));
1879
1880                         if (ins->opcode == OP_FMOVE) {
1881                                 /* Do it by renaming the source to the destination on the stack */
1882                                 // FIXME: Is this correct ?
1883                                 for (i = 0; i < sp; ++i)
1884                                         if (fpstack [i] == ins->sreg1)
1885                                                 fpstack [i] = ins->dreg;
1886                                 prev = ins;
1887                                 continue;
1888                         }
1889
1890                         if (sreg1_is_fp (spec) && sreg2_is_fp (spec) && (fpstack [sp - 2] != ins->sreg1)) {
1891                                 /* Arg1 must be in %st(1) */
1892                                 g_assert (prev);
1893
1894                                 i = 0;
1895                                 while ((i < sp) && (fpstack [i] != ins->sreg1))
1896                                         i ++;
1897                                 g_assert (i < sp);
1898
1899                                 if (sp - 1 - i > 0) {
1900                                         /* First move it to %st(0) */
1901                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1902
1903                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1904                                         fxch->inst_imm = sp - 1 - i;
1905
1906                                         prev->next = fxch;
1907                                         fxch->next = ins;
1908                                         prev = fxch;
1909
1910                                         tmp = fpstack [sp - 1];
1911                                         fpstack [sp - 1] = fpstack [i];
1912                                         fpstack [i] = tmp;
1913                                 }
1914
1915                                 /* Then move it to %st(1) */
1916                                 DEBUG (printf ("\tswap %%st(0) and %%st(1)\n"));
1917
1918                                 MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1919                                 fxch->inst_imm = 1;
1920
1921                                 prev->next = fxch;
1922                                 fxch->next = ins;
1923                                 prev = fxch;
1924
1925                                 tmp = fpstack [sp - 1];
1926                                 fpstack [sp - 1] = fpstack [sp - 2];
1927                                 fpstack [sp - 2] = tmp;
1928                         }
1929
1930                         if (sreg2_is_fp (spec)) {
1931                                 g_assert (sp > 0);
1932
1933                                 if (fpstack [sp - 1] != ins->sreg2) {
1934                                         g_assert (prev);
1935
1936                                         i = 0;
1937                                         while ((i < sp) && (fpstack [i] != ins->sreg2))
1938                                                 i ++;
1939                                         g_assert (i < sp);
1940
1941                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1942
1943                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1944                                         fxch->inst_imm = sp - 1 - i;
1945
1946                                         prev->next = fxch;
1947                                         fxch->next = ins;
1948                                         prev = fxch;
1949
1950                                         tmp = fpstack [sp - 1];
1951                                         fpstack [sp - 1] = fpstack [i];
1952                                         fpstack [i] = tmp;
1953                                 }
1954
1955                                 sp --;
1956                         }
1957
1958                         if (sreg1_is_fp (spec)) {
1959                                 g_assert (sp > 0);
1960
1961                                 if (fpstack [sp - 1] != ins->sreg1) {
1962                                         g_assert (prev);
1963
1964                                         i = 0;
1965                                         while ((i < sp) && (fpstack [i] != ins->sreg1))
1966                                                 i ++;
1967                                         g_assert (i < sp);
1968
1969                                         DEBUG (printf ("\tswap %%st(0) and %%st(%d)\n", sp - 1 - i));
1970
1971                                         MONO_INST_NEW (cfg, fxch, OP_X86_FXCH);
1972                                         fxch->inst_imm = sp - 1 - i;
1973
1974                                         prev->next = fxch;
1975                                         fxch->next = ins;
1976                                         prev = fxch;
1977
1978                                         tmp = fpstack [sp - 1];
1979                                         fpstack [sp - 1] = fpstack [i];
1980                                         fpstack [i] = tmp;
1981                                 }
1982
1983                                 sp --;
1984                         }
1985
1986                         if (dreg_is_fp (spec)) {
1987                                 g_assert (sp < 8);
1988                                 fpstack [sp ++] = ins->dreg;
1989                         }
1990
1991                         if (G_UNLIKELY (cfg->verbose_level >= 2)) {
1992                                 printf ("\t[");
1993                                 for (i = 0; i < sp; ++i)
1994                                         printf ("%s%%fr%d", (i > 0) ? ", " : "", fpstack [i]);
1995                                 printf ("]\n");
1996                         }
1997
1998                         prev = ins;
1999                 }
2000
2001                 if (sp && bb != cfg->bb_exit && !(bb->out_count == 1 && bb->out_bb [0] == cfg->bb_exit)) {
2002                         /* Remove remaining items from the fp stack */
2003                         /*
2004                          * These can remain for example as a result of a dead fmove like in
2005                          * System.Collections.Generic.EqualityComparer<double>.Equals ().
2006                          */
2007                         while (sp) {
2008                                 MONO_INST_NEW (cfg, ins, OP_X86_FPOP);
2009                                 mono_add_ins_to_end (bb, ins);
2010                                 sp --;
2011                         }
2012                 }
2013         }
2014 #endif
2015 }
2016
2017 CompRelation
2018 mono_opcode_to_cond (int opcode)
2019 {
2020         switch (opcode) {
2021         case CEE_BEQ:
2022         case OP_CEQ:
2023         case OP_IBEQ:
2024         case OP_ICEQ:
2025         case OP_LBEQ:
2026         case OP_LCEQ:
2027         case OP_FBEQ:
2028         case OP_FCEQ:
2029         case OP_COND_EXC_EQ:
2030         case OP_COND_EXC_IEQ:
2031         case OP_CMOV_IEQ:
2032         case OP_CMOV_LEQ:
2033                 return CMP_EQ;
2034         case CEE_BNE_UN:
2035         case OP_IBNE_UN:
2036         case OP_LBNE_UN:
2037         case OP_FBNE_UN:
2038         case OP_COND_EXC_NE_UN:
2039         case OP_COND_EXC_INE_UN:
2040         case OP_CMOV_INE_UN:
2041         case OP_CMOV_LNE_UN:
2042                 return CMP_NE;
2043         case CEE_BLE:
2044         case OP_IBLE:
2045         case OP_LBLE:
2046         case OP_FBLE:
2047         case OP_CMOV_ILE:
2048         case OP_CMOV_LLE:
2049                 return CMP_LE;
2050         case CEE_BGE:
2051         case OP_IBGE:
2052         case OP_LBGE:
2053         case OP_FBGE:
2054         case OP_CMOV_IGE:
2055         case OP_CMOV_LGE:
2056                 return CMP_GE;
2057         case CEE_BLT:
2058         case OP_CLT:
2059         case OP_IBLT:
2060         case OP_ICLT:
2061         case OP_LBLT:
2062         case OP_LCLT:
2063         case OP_FBLT:
2064         case OP_FCLT:
2065         case OP_COND_EXC_LT:
2066         case OP_COND_EXC_ILT:
2067         case OP_CMOV_ILT:
2068         case OP_CMOV_LLT:
2069                 return CMP_LT;
2070         case CEE_BGT:
2071         case OP_CGT:
2072         case OP_IBGT:
2073         case OP_ICGT:
2074         case OP_LBGT:
2075         case OP_LCGT:
2076         case OP_FBGT:
2077         case OP_FCGT:
2078         case OP_COND_EXC_GT:
2079         case OP_COND_EXC_IGT:
2080         case OP_CMOV_IGT:
2081         case OP_CMOV_LGT:
2082                 return CMP_GT;
2083
2084         case CEE_BLE_UN:
2085         case OP_IBLE_UN:
2086         case OP_LBLE_UN:
2087         case OP_FBLE_UN:
2088         case OP_COND_EXC_LE_UN:
2089         case OP_COND_EXC_ILE_UN:
2090         case OP_CMOV_ILE_UN:
2091         case OP_CMOV_LLE_UN:
2092                 return CMP_LE_UN;
2093         case CEE_BGE_UN:
2094         case OP_IBGE_UN:
2095         case OP_LBGE_UN:
2096         case OP_FBGE_UN:
2097         case OP_CMOV_IGE_UN:
2098         case OP_CMOV_LGE_UN:
2099                 return CMP_GE_UN;
2100         case CEE_BLT_UN:
2101         case OP_CLT_UN:
2102         case OP_IBLT_UN:
2103         case OP_ICLT_UN:
2104         case OP_LBLT_UN:
2105         case OP_LCLT_UN:
2106         case OP_FBLT_UN:
2107         case OP_FCLT_UN:
2108         case OP_COND_EXC_LT_UN:
2109         case OP_COND_EXC_ILT_UN:
2110         case OP_CMOV_ILT_UN:
2111         case OP_CMOV_LLT_UN:
2112                 return CMP_LT_UN;
2113         case CEE_BGT_UN:
2114         case OP_CGT_UN:
2115         case OP_IBGT_UN:
2116         case OP_ICGT_UN:
2117         case OP_LBGT_UN:
2118         case OP_LCGT_UN:
2119         case OP_FCGT_UN:
2120         case OP_FBGT_UN:
2121         case OP_COND_EXC_GT_UN:
2122         case OP_COND_EXC_IGT_UN:
2123         case OP_CMOV_IGT_UN:
2124         case OP_CMOV_LGT_UN:
2125                 return CMP_GT_UN;
2126         default:
2127                 printf ("%s\n", mono_inst_name (opcode));
2128                 g_assert_not_reached ();
2129                 return 0;
2130         }
2131 }
2132
2133 CompRelation
2134 mono_negate_cond (CompRelation cond)
2135 {
2136         switch (cond) {
2137         case CMP_EQ:
2138                 return CMP_NE;
2139         case CMP_NE:
2140                 return CMP_EQ;
2141         case CMP_LE:
2142                 return CMP_GT;
2143         case CMP_GE:
2144                 return CMP_LT;
2145         case CMP_LT:
2146                 return CMP_GE;
2147         case CMP_GT:
2148                 return CMP_LE;
2149         case CMP_LE_UN:
2150                 return CMP_GT_UN;
2151         case CMP_GE_UN:
2152                 return CMP_LT_UN;
2153         case CMP_LT_UN:
2154                 return CMP_GE_UN;
2155         case CMP_GT_UN:
2156                 return CMP_LE_UN;
2157         default:
2158                 g_assert_not_reached ();
2159         }
2160 }
2161
2162 CompType
2163 mono_opcode_to_type (int opcode, int cmp_opcode)
2164 {
2165         if ((opcode >= CEE_BEQ) && (opcode <= CEE_BLT_UN))
2166                 return CMP_TYPE_L;
2167         else if ((opcode >= OP_CEQ) && (opcode <= OP_CLT_UN))
2168                 return CMP_TYPE_L;
2169         else if ((opcode >= OP_IBEQ) && (opcode <= OP_IBLT_UN))
2170                 return CMP_TYPE_I;
2171         else if ((opcode >= OP_ICEQ) && (opcode <= OP_ICLT_UN))
2172                 return CMP_TYPE_I;
2173         else if ((opcode >= OP_LBEQ) && (opcode <= OP_LBLT_UN))
2174                 return CMP_TYPE_L;
2175         else if ((opcode >= OP_LCEQ) && (opcode <= OP_LCLT_UN))
2176                 return CMP_TYPE_L;
2177         else if ((opcode >= OP_FBEQ) && (opcode <= OP_FBLT_UN))
2178                 return CMP_TYPE_F;
2179         else if ((opcode >= OP_FCEQ) && (opcode <= OP_FCLT_UN))
2180                 return CMP_TYPE_F;
2181         else if ((opcode >= OP_COND_EXC_IEQ) && (opcode <= OP_COND_EXC_ILT_UN))
2182                 return CMP_TYPE_I;
2183         else if ((opcode >= OP_COND_EXC_EQ) && (opcode <= OP_COND_EXC_LT_UN)) {
2184                 switch (cmp_opcode) {
2185                 case OP_ICOMPARE:
2186                 case OP_ICOMPARE_IMM:
2187                 case OP_LCOMPARE_IMM:
2188                         return CMP_TYPE_I;
2189                 default:
2190                         return CMP_TYPE_L;
2191                 }
2192         } else {
2193                 g_error ("Unknown opcode '%s' in opcode_to_type", mono_inst_name (opcode));
2194                 return 0;
2195         }
2196 }
2197
2198 gboolean
2199 mono_is_regsize_var (MonoType *t)
2200 {
2201         if (t->byref)
2202                 return TRUE;
2203         t = mono_type_get_underlying_type (t);
2204         switch (t->type) {
2205         case MONO_TYPE_BOOLEAN:
2206         case MONO_TYPE_CHAR:
2207         case MONO_TYPE_I1:
2208         case MONO_TYPE_U1:
2209         case MONO_TYPE_I2:
2210         case MONO_TYPE_U2:
2211         case MONO_TYPE_I4:
2212         case MONO_TYPE_U4:
2213         case MONO_TYPE_I:
2214         case MONO_TYPE_U:
2215         case MONO_TYPE_PTR:
2216         case MONO_TYPE_FNPTR:
2217 #if SIZEOF_VOID_P == 8
2218         case MONO_TYPE_I8:
2219         case MONO_TYPE_U8:
2220 #endif
2221                 return TRUE;
2222         case MONO_TYPE_OBJECT:
2223         case MONO_TYPE_STRING:
2224         case MONO_TYPE_CLASS:
2225         case MONO_TYPE_SZARRAY:
2226         case MONO_TYPE_ARRAY:
2227                 return TRUE;
2228         case MONO_TYPE_GENERICINST:
2229                 if (!mono_type_generic_inst_is_valuetype (t))
2230                         return TRUE;
2231                 return FALSE;
2232         case MONO_TYPE_VALUETYPE:
2233                 return FALSE;
2234         }
2235         return FALSE;
2236 }
2237
2238 /*
2239  * mono_peephole_ins:
2240  *
2241  *   Perform some architecture independent peephole optimizations.
2242  */
2243 void
2244 mono_peephole_ins (MonoBasicBlock *bb, MonoInst *ins)
2245 {
2246         MonoInst *last_ins = ins->prev;
2247
2248         switch (ins->opcode) {
2249         case OP_MUL_IMM:
2250                 /* remove unnecessary multiplication with 1 */
2251                 if (ins->inst_imm == 1) {
2252                         if (ins->dreg != ins->sreg1)
2253                                 ins->opcode = OP_MOVE;
2254                         else
2255                                 MONO_DELETE_INS (bb, ins);
2256                 }
2257                 break;
2258         case OP_LOAD_MEMBASE:
2259         case OP_LOADI4_MEMBASE:
2260                 /*
2261                  * Note: if reg1 = reg2 the load op is removed
2262                  *
2263                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2264                  * OP_LOAD_MEMBASE offset(basereg), reg2
2265                  * -->
2266                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2267                  * OP_MOVE reg1, reg2
2268                  */
2269                 if (last_ins &&
2270                         (((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
2271                          ((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
2272                         ins->inst_basereg == last_ins->inst_destbasereg &&
2273                         ins->inst_offset == last_ins->inst_offset) {
2274                         if (ins->dreg == last_ins->sreg1) {
2275                                 MONO_DELETE_INS (bb, ins);
2276                                 break;
2277                         } else {
2278                                 ins->opcode = OP_MOVE;
2279                                 ins->sreg1 = last_ins->sreg1;
2280                         }
2281
2282                         /*
2283                          * Note: reg1 must be different from the basereg in the second load
2284                          * Note: if reg1 = reg2 is equal then second load is removed
2285                          *
2286                          * OP_LOAD_MEMBASE offset(basereg), reg1
2287                          * OP_LOAD_MEMBASE offset(basereg), reg2
2288                          * -->
2289                          * OP_LOAD_MEMBASE offset(basereg), reg1
2290                          * OP_MOVE reg1, reg2
2291                          */
2292                 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2293                                                    || last_ins->opcode == OP_LOAD_MEMBASE) &&
2294                           ins->inst_basereg != last_ins->dreg &&
2295                           ins->inst_basereg == last_ins->inst_basereg &&
2296                           ins->inst_offset == last_ins->inst_offset) {
2297
2298                         if (ins->dreg == last_ins->dreg) {
2299                                 MONO_DELETE_INS (bb, ins);
2300                         } else {
2301                                 ins->opcode = OP_MOVE;
2302                                 ins->sreg1 = last_ins->dreg;
2303                         }
2304
2305                         //g_assert_not_reached ();
2306
2307 #if 0
2308                         /*
2309                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2310                          * OP_LOAD_MEMBASE offset(basereg), reg
2311                          * -->
2312                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2313                          * OP_ICONST reg, imm
2314                          */
2315                 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2316                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2317                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2318                                    ins->inst_offset == last_ins->inst_offset) {
2319                         ins->opcode = OP_ICONST;
2320                         ins->inst_c0 = last_ins->inst_imm;
2321                         g_assert_not_reached (); // check this rule
2322 #endif
2323                 }
2324                 break;
2325         case OP_LOADI1_MEMBASE:
2326         case OP_LOADU1_MEMBASE:
2327                 /*
2328                  * Note: if reg1 = reg2 the load op is removed
2329                  *
2330                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2331                  * OP_LOAD_MEMBASE offset(basereg), reg2
2332                  * -->
2333                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2334                  * OP_MOVE reg1, reg2
2335                  */
2336                 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2337                         ins->inst_basereg == last_ins->inst_destbasereg &&
2338                         ins->inst_offset == last_ins->inst_offset) {
2339                         ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2340                         ins->sreg1 = last_ins->sreg1;
2341                 }
2342                 break;
2343         case OP_LOADI2_MEMBASE:
2344         case OP_LOADU2_MEMBASE:
2345                 /*
2346                  * Note: if reg1 = reg2 the load op is removed
2347                  *
2348                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2349                  * OP_LOAD_MEMBASE offset(basereg), reg2
2350                  * -->
2351                  * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2352                  * OP_MOVE reg1, reg2
2353                  */
2354                 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2355                         ins->inst_basereg == last_ins->inst_destbasereg &&
2356                         ins->inst_offset == last_ins->inst_offset) {
2357 #if SIZEOF_VOID_P == 8
2358                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2359 #else
2360                         /* The definition of OP_PCONV_TO_U2 is wrong */
2361                         ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_ICONV_TO_U2;
2362 #endif
2363                         ins->sreg1 = last_ins->sreg1;
2364                 }
2365                 break;
2366         case OP_MOVE:
2367         case OP_FMOVE:
2368                 /*
2369                  * Removes:
2370                  *
2371                  * OP_MOVE reg, reg
2372                  */
2373                 if (ins->dreg == ins->sreg1) {
2374                         MONO_DELETE_INS (bb, ins);
2375                         break;
2376                 }
2377                 /*
2378                  * Removes:
2379                  *
2380                  * OP_MOVE sreg, dreg
2381                  * OP_MOVE dreg, sreg
2382                  */
2383                 if (last_ins && last_ins->opcode == OP_MOVE &&
2384                         ins->sreg1 == last_ins->dreg &&
2385                         ins->dreg == last_ins->sreg1) {
2386                         MONO_DELETE_INS (bb, ins);
2387                 }
2388                 break;
2389         case OP_NOP:
2390                 MONO_DELETE_INS (bb, ins);
2391                 break;
2392         }
2393 }
2394