2 * mini-arm64.c: ARM64 backend for the Mono code generator
4 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
9 * Paolo Molaro (lupus@ximian.com)
10 * Dietmar Maurer (dietmar@ximian.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
19 #include "cpu-arm64.h"
22 #include <mono/arch/arm64/arm64-codegen.h>
23 #include <mono/utils/mono-mmap.h>
24 #include <mono/utils/mono-memory-model.h>
25 #include <mono/metadata/abi-details.h>
30 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
31 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
32 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
35 * - ip0/ip1/lr are used as temporary registers
36 * - r27 is used as the rgctx/imt register
37 * - r28 is used to access arguments passed on the stack
38 * - d15/d16 are used as fp temporary registers
41 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
43 #define FP_TEMP_REG ARMREG_D16
44 #define FP_TEMP_REG2 ARMREG_D17
46 #define THUNK_SIZE (4 * 4)
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 static gboolean ios_abi;
56 static __attribute__((warn_unused_result)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
59 mono_arch_regname (int reg)
61 static const char * rnames[] = {
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
63 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
64 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
67 if (reg >= 0 && reg < 32)
73 mono_arch_fregname (int reg)
75 static const char * rnames[] = {
76 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
77 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
78 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
81 if (reg >= 0 && reg < 32)
87 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
93 #define MAX_ARCH_DELEGATE_PARAMS 7
96 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
101 start = code = mono_global_codeman_reserve (12);
103 /* Replace the this argument with the target */
104 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
105 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
106 arm_brx (code, ARMREG_IP0);
108 g_assert ((code - start) <= 12);
110 mono_arch_flush_icache (start, 12);
114 size = 8 + param_count * 4;
115 start = code = mono_global_codeman_reserve (size);
117 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
118 /* slide down the arguments */
119 for (i = 0; i < param_count; ++i)
120 arm_movx (code, i, i + 1);
121 arm_brx (code, ARMREG_IP0);
123 g_assert ((code - start) <= size);
125 mono_arch_flush_icache (start, size);
129 *code_size = code - start;
135 * mono_arch_get_delegate_invoke_impls:
137 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
141 mono_arch_get_delegate_invoke_impls (void)
149 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
150 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
152 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
153 code = get_delegate_invoke_impl (FALSE, i, &code_len);
154 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
155 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
165 guint8 *code, *start;
168 * vtypes are returned in registers, or using the dedicated r8 register, so
169 * they can be supported by delegate invokes.
173 static guint8* cached = NULL;
179 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
181 start = get_delegate_invoke_impl (TRUE, 0, NULL);
182 mono_memory_barrier ();
186 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
189 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
191 for (i = 0; i < sig->param_count; ++i)
192 if (!mono_is_regsize_var (sig->params [i]))
195 code = cache [sig->param_count];
200 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
201 start = mono_aot_get_trampoline (name);
204 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
206 mono_memory_barrier ();
207 cache [sig->param_count] = start;
215 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
221 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
223 return (gpointer)regs [ARMREG_R0];
227 mono_arch_cpu_init (void)
232 mono_arch_init (void)
234 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
235 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
238 bp_trampoline = mini_get_breakpoint_trampoline ();
240 mono_arm_gsharedvt_init ();
242 #if defined(TARGET_IOS)
248 mono_arch_cleanup (void)
253 mono_arch_cpu_optimizations (guint32 *exclude_mask)
260 mono_arch_cpu_enumerate_simd_versions (void)
266 mono_arch_register_lowlevel_calls (void)
271 mono_arch_finish_init (void)
275 /* The maximum length is 2 instructions */
277 emit_imm (guint8 *code, int dreg, int imm)
279 // FIXME: Optimize this
282 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
283 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
285 arm_movzx (code, dreg, imm & 0xffff, 0);
287 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
293 /* The maximum length is 4 instructions */
295 emit_imm64 (guint8 *code, int dreg, guint64 imm)
297 // FIXME: Optimize this
298 arm_movzx (code, dreg, imm & 0xffff, 0);
299 if ((imm >> 16) & 0xffff)
300 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
301 if ((imm >> 32) & 0xffff)
302 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
303 if ((imm >> 48) & 0xffff)
304 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
310 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
312 return emit_imm64 (code, dreg, imm);
318 * Emit a patchable code sequence for constructing a 64 bit immediate.
321 emit_imm64_template (guint8 *code, int dreg)
323 arm_movzx (code, dreg, 0, 0);
324 arm_movkx (code, dreg, 0, 16);
325 arm_movkx (code, dreg, 0, 32);
326 arm_movkx (code, dreg, 0, 48);
331 static inline __attribute__((warn_unused_result)) guint8*
332 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
334 if (!arm_is_arith_imm (imm)) {
335 code = emit_imm (code, ARMREG_LR, imm);
336 arm_addw (code, dreg, sreg, ARMREG_LR);
338 arm_addw_imm (code, dreg, sreg, imm);
343 static inline __attribute__((warn_unused_result)) guint8*
344 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
346 if (!arm_is_arith_imm (imm)) {
347 code = emit_imm (code, ARMREG_LR, imm);
348 arm_addx (code, dreg, sreg, ARMREG_LR);
350 arm_addx_imm (code, dreg, sreg, imm);
355 static inline __attribute__((warn_unused_result)) guint8*
356 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
358 if (!arm_is_arith_imm (imm)) {
359 code = emit_imm (code, ARMREG_LR, imm);
360 arm_subw (code, dreg, sreg, ARMREG_LR);
362 arm_subw_imm (code, dreg, sreg, imm);
367 static inline __attribute__((warn_unused_result)) guint8*
368 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
370 if (!arm_is_arith_imm (imm)) {
371 code = emit_imm (code, ARMREG_LR, imm);
372 arm_subx (code, dreg, sreg, ARMREG_LR);
374 arm_subx_imm (code, dreg, sreg, imm);
379 /* Emit sp+=imm. Clobbers ip0/ip1 */
380 static inline __attribute__((warn_unused_result)) guint8*
381 emit_addx_sp_imm (guint8 *code, int imm)
383 code = emit_imm (code, ARMREG_IP0, imm);
384 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
385 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
386 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
390 /* Emit sp-=imm. Clobbers ip0/ip1 */
391 static inline __attribute__((warn_unused_result)) guint8*
392 emit_subx_sp_imm (guint8 *code, int imm)
394 code = emit_imm (code, ARMREG_IP0, imm);
395 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
396 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
397 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
401 static inline __attribute__((warn_unused_result)) guint8*
402 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
405 code = emit_imm (code, ARMREG_LR, imm);
406 arm_andw (code, dreg, sreg, ARMREG_LR);
411 static inline __attribute__((warn_unused_result)) guint8*
412 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
415 code = emit_imm (code, ARMREG_LR, imm);
416 arm_andx (code, dreg, sreg, ARMREG_LR);
421 static inline __attribute__((warn_unused_result)) guint8*
422 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
425 code = emit_imm (code, ARMREG_LR, imm);
426 arm_orrw (code, dreg, sreg, ARMREG_LR);
431 static inline __attribute__((warn_unused_result)) guint8*
432 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
435 code = emit_imm (code, ARMREG_LR, imm);
436 arm_orrx (code, dreg, sreg, ARMREG_LR);
441 static inline __attribute__((warn_unused_result)) guint8*
442 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
445 code = emit_imm (code, ARMREG_LR, imm);
446 arm_eorw (code, dreg, sreg, ARMREG_LR);
451 static inline __attribute__((warn_unused_result)) guint8*
452 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
455 code = emit_imm (code, ARMREG_LR, imm);
456 arm_eorx (code, dreg, sreg, ARMREG_LR);
461 static inline __attribute__((warn_unused_result)) guint8*
462 emit_cmpw_imm (guint8 *code, int sreg, int imm)
465 arm_cmpw (code, sreg, ARMREG_RZR);
468 code = emit_imm (code, ARMREG_LR, imm);
469 arm_cmpw (code, sreg, ARMREG_LR);
475 static inline __attribute__((warn_unused_result)) guint8*
476 emit_cmpx_imm (guint8 *code, int sreg, int imm)
479 arm_cmpx (code, sreg, ARMREG_RZR);
482 code = emit_imm (code, ARMREG_LR, imm);
483 arm_cmpx (code, sreg, ARMREG_LR);
489 static inline __attribute__((warn_unused_result)) guint8*
490 emit_strb (guint8 *code, int rt, int rn, int imm)
492 if (arm_is_strb_imm (imm)) {
493 arm_strb (code, rt, rn, imm);
495 g_assert (rt != ARMREG_IP0);
496 g_assert (rn != ARMREG_IP0);
497 code = emit_imm (code, ARMREG_IP0, imm);
498 arm_strb_reg (code, rt, rn, ARMREG_IP0);
503 static inline __attribute__((warn_unused_result)) guint8*
504 emit_strh (guint8 *code, int rt, int rn, int imm)
506 if (arm_is_strh_imm (imm)) {
507 arm_strh (code, rt, rn, imm);
509 g_assert (rt != ARMREG_IP0);
510 g_assert (rn != ARMREG_IP0);
511 code = emit_imm (code, ARMREG_IP0, imm);
512 arm_strh_reg (code, rt, rn, ARMREG_IP0);
517 static inline __attribute__((warn_unused_result)) guint8*
518 emit_strw (guint8 *code, int rt, int rn, int imm)
520 if (arm_is_strw_imm (imm)) {
521 arm_strw (code, rt, rn, imm);
523 g_assert (rt != ARMREG_IP0);
524 g_assert (rn != ARMREG_IP0);
525 code = emit_imm (code, ARMREG_IP0, imm);
526 arm_strw_reg (code, rt, rn, ARMREG_IP0);
531 static inline __attribute__((warn_unused_result)) guint8*
532 emit_strfpw (guint8 *code, int rt, int rn, int imm)
534 if (arm_is_strw_imm (imm)) {
535 arm_strfpw (code, rt, rn, imm);
537 g_assert (rn != ARMREG_IP0);
538 code = emit_imm (code, ARMREG_IP0, imm);
539 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
540 arm_strfpw (code, rt, ARMREG_IP0, 0);
545 static inline __attribute__((warn_unused_result)) guint8*
546 emit_strfpx (guint8 *code, int rt, int rn, int imm)
548 if (arm_is_strx_imm (imm)) {
549 arm_strfpx (code, rt, rn, imm);
551 g_assert (rn != ARMREG_IP0);
552 code = emit_imm (code, ARMREG_IP0, imm);
553 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
554 arm_strfpx (code, rt, ARMREG_IP0, 0);
559 static inline __attribute__((warn_unused_result)) guint8*
560 emit_strx (guint8 *code, int rt, int rn, int imm)
562 if (arm_is_strx_imm (imm)) {
563 arm_strx (code, rt, rn, imm);
565 g_assert (rt != ARMREG_IP0);
566 g_assert (rn != ARMREG_IP0);
567 code = emit_imm (code, ARMREG_IP0, imm);
568 arm_strx_reg (code, rt, rn, ARMREG_IP0);
573 static inline __attribute__((warn_unused_result)) guint8*
574 emit_ldrb (guint8 *code, int rt, int rn, int imm)
576 if (arm_is_pimm12_scaled (imm, 1)) {
577 arm_ldrb (code, rt, rn, imm);
579 g_assert (rt != ARMREG_IP0);
580 g_assert (rn != ARMREG_IP0);
581 code = emit_imm (code, ARMREG_IP0, imm);
582 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
587 static inline __attribute__((warn_unused_result)) guint8*
588 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
590 if (arm_is_pimm12_scaled (imm, 1)) {
591 arm_ldrsbx (code, rt, rn, imm);
593 g_assert (rt != ARMREG_IP0);
594 g_assert (rn != ARMREG_IP0);
595 code = emit_imm (code, ARMREG_IP0, imm);
596 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
601 static inline __attribute__((warn_unused_result)) guint8*
602 emit_ldrh (guint8 *code, int rt, int rn, int imm)
604 if (arm_is_pimm12_scaled (imm, 2)) {
605 arm_ldrh (code, rt, rn, imm);
607 g_assert (rt != ARMREG_IP0);
608 g_assert (rn != ARMREG_IP0);
609 code = emit_imm (code, ARMREG_IP0, imm);
610 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
615 static inline __attribute__((warn_unused_result)) guint8*
616 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
618 if (arm_is_pimm12_scaled (imm, 2)) {
619 arm_ldrshx (code, rt, rn, imm);
621 g_assert (rt != ARMREG_IP0);
622 g_assert (rn != ARMREG_IP0);
623 code = emit_imm (code, ARMREG_IP0, imm);
624 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
629 static inline __attribute__((warn_unused_result)) guint8*
630 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
632 if (arm_is_pimm12_scaled (imm, 4)) {
633 arm_ldrswx (code, rt, rn, imm);
635 g_assert (rt != ARMREG_IP0);
636 g_assert (rn != ARMREG_IP0);
637 code = emit_imm (code, ARMREG_IP0, imm);
638 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
643 static inline __attribute__((warn_unused_result)) guint8*
644 emit_ldrw (guint8 *code, int rt, int rn, int imm)
646 if (arm_is_pimm12_scaled (imm, 4)) {
647 arm_ldrw (code, rt, rn, imm);
649 g_assert (rn != ARMREG_IP0);
650 code = emit_imm (code, ARMREG_IP0, imm);
651 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
656 static inline __attribute__((warn_unused_result)) guint8*
657 emit_ldrx (guint8 *code, int rt, int rn, int imm)
659 if (arm_is_pimm12_scaled (imm, 8)) {
660 arm_ldrx (code, rt, rn, imm);
662 g_assert (rn != ARMREG_IP0);
663 code = emit_imm (code, ARMREG_IP0, imm);
664 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
669 static inline __attribute__((warn_unused_result)) guint8*
670 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
672 if (arm_is_pimm12_scaled (imm, 4)) {
673 arm_ldrfpw (code, rt, rn, imm);
675 g_assert (rn != ARMREG_IP0);
676 code = emit_imm (code, ARMREG_IP0, imm);
677 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
678 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
683 static inline __attribute__((warn_unused_result)) guint8*
684 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
686 if (arm_is_pimm12_scaled (imm, 8)) {
687 arm_ldrfpx (code, rt, rn, imm);
689 g_assert (rn != ARMREG_IP0);
690 code = emit_imm (code, ARMREG_IP0, imm);
691 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
692 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
698 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
700 return emit_ldrx (code, rt, rn, imm);
704 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
707 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
708 code = emit_imm64_template (code, ARMREG_LR);
709 arm_blrx (code, ARMREG_LR);
711 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
713 cfg->thunk_area += THUNK_SIZE;
718 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
721 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
723 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
724 /* See arch_emit_got_access () in aot-compiler.c */
725 arm_ldrx_lit (code, dreg, 0);
732 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
734 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
738 * mono_arm_emit_aotconst:
740 * Emit code to load an AOT constant into DREG. Usable from trampolines.
743 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
745 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
749 emit_tls_get (guint8 *code, int dreg, int tls_offset)
751 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
752 if (tls_offset < 256) {
753 arm_ldrx (code, dreg, dreg, tls_offset);
755 code = emit_addx_imm (code, dreg, dreg, tls_offset);
756 arm_ldrx (code, dreg, dreg, 0);
762 emit_tls_get_reg (guint8 *code, int dreg, int offset_reg)
764 g_assert (offset_reg != ARMREG_IP0);
765 arm_mrs (code, ARMREG_IP0, ARM_MRS_REG_TPIDR_EL0);
766 arm_ldrx_reg (code, dreg, ARMREG_IP0, offset_reg);
771 emit_tls_set (guint8 *code, int sreg, int tls_offset)
773 int tmpreg = ARMREG_IP0;
775 g_assert (sreg != tmpreg);
776 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
777 if (tls_offset < 256) {
778 arm_strx (code, sreg, tmpreg, tls_offset);
780 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
781 arm_strx (code, sreg, tmpreg, 0);
788 emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
790 int tmpreg = ARMREG_IP0;
792 g_assert (sreg != tmpreg);
793 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
794 arm_strx_reg (code, sreg, tmpreg, offset_reg);
801 * - ldrp [fp, lr], [sp], !stack_offfset
802 * Clobbers TEMP_REGS.
804 __attribute__((warn_unused_result)) guint8*
805 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
807 arm_movspx (code, ARMREG_SP, ARMREG_FP);
809 if (arm_is_ldpx_imm (stack_offset)) {
810 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
812 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
813 /* sp += stack_offset */
814 g_assert (temp_regs & (1 << ARMREG_IP0));
815 if (temp_regs & (1 << ARMREG_IP1)) {
816 code = emit_addx_sp_imm (code, stack_offset);
818 int imm = stack_offset;
820 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
821 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
823 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
826 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
832 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
835 emit_thunk (guint8 *code, gconstpointer target)
839 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
840 arm_brx (code, ARMREG_IP0);
841 *(guint64*)code = (guint64)target;
842 code += sizeof (guint64);
844 mono_arch_flush_icache (p, code - p);
849 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
852 MonoThunkJitInfo *info;
856 guint8 *target_thunk;
859 domain = mono_domain_get ();
863 * This can be called multiple times during JITting,
864 * save the current position in cfg->arch to avoid
865 * doing a O(n^2) search.
867 if (!cfg->arch.thunks) {
868 cfg->arch.thunks = cfg->thunks;
869 cfg->arch.thunks_size = cfg->thunk_area;
871 thunks = cfg->arch.thunks;
872 thunks_size = cfg->arch.thunks_size;
874 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
875 g_assert_not_reached ();
878 g_assert (*(guint32*)thunks == 0);
879 emit_thunk (thunks, target);
881 cfg->arch.thunks += THUNK_SIZE;
882 cfg->arch.thunks_size -= THUNK_SIZE;
886 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
888 info = mono_jit_info_get_thunk_info (ji);
891 thunks = (guint8*)ji->code_start + info->thunks_offset;
892 thunks_size = info->thunks_size;
894 orig_target = mono_arch_get_call_target (code + 4);
896 mono_domain_lock (domain);
899 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
900 /* The call already points to a thunk, because of trampolines etc. */
901 target_thunk = orig_target;
903 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
904 if (((guint32*)p) [0] == 0) {
908 } else if (((guint64*)p) [1] == (guint64)target) {
909 /* Thunk already points to target */
916 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
919 mono_domain_unlock (domain);
920 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
921 g_assert_not_reached ();
924 emit_thunk (target_thunk, target);
926 mono_domain_unlock (domain);
933 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
935 switch (relocation) {
937 if (arm_is_bl_disp (code, target)) {
938 arm_b (code, target);
942 thunk = create_thunk (cfg, domain, code, target);
943 g_assert (arm_is_bl_disp (code, thunk));
947 case MONO_R_ARM64_BCC: {
950 cond = arm_get_bcc_cond (code);
951 arm_bcc (code, cond, target);
954 case MONO_R_ARM64_CBZ:
955 arm_set_cbz_target (code, target);
957 case MONO_R_ARM64_IMM: {
958 guint64 imm = (guint64)target;
961 /* emit_imm64_template () */
962 dreg = arm_get_movzx_rd (code);
963 arm_movzx (code, dreg, imm & 0xffff, 0);
964 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
965 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
966 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
969 case MONO_R_ARM64_BL:
970 if (arm_is_bl_disp (code, target)) {
971 arm_bl (code, target);
975 thunk = create_thunk (cfg, domain, code, target);
976 g_assert (arm_is_bl_disp (code, thunk));
977 arm_bl (code, thunk);
981 g_assert_not_reached ();
986 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
988 arm_patch_full (NULL, NULL, code, target, relocation);
992 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
994 arm_patch_rel (code, target, relocation);
998 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
1002 ip = ji->ip.i + code;
1005 case MONO_PATCH_INFO_METHOD_JUMP:
1006 /* ji->relocation is not set by the caller */
1007 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1010 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1016 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1021 mono_arch_flush_register_windows (void)
1026 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1028 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1032 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1034 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1038 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1040 return ctx->regs [reg];
1044 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1046 ctx->regs [reg] = val;
1050 * mono_arch_set_target:
1052 * Set the target architecture the JIT backend should generate code for, in the form
1053 * of a GNU target triplet. Only used in AOT mode.
1056 mono_arch_set_target (char *mtriple)
1058 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1064 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1066 if (cinfo->gr >= PARAM_REGS) {
1067 ainfo->storage = ArgOnStack;
1069 /* Assume size == align */
1070 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1071 ainfo->offset = cinfo->stack_usage;
1072 ainfo->slot_size = size;
1074 cinfo->stack_usage += size;
1076 ainfo->offset = cinfo->stack_usage;
1077 ainfo->slot_size = 8;
1078 ainfo->sign = FALSE;
1079 /* Put arguments into 8 byte aligned stack slots */
1080 cinfo->stack_usage += 8;
1083 ainfo->storage = ArgInIReg;
1084 ainfo->reg = cinfo->gr;
1090 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1092 int size = single ? 4 : 8;
1094 if (cinfo->fr >= FP_PARAM_REGS) {
1095 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1097 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1098 ainfo->offset = cinfo->stack_usage;
1099 ainfo->slot_size = size;
1100 cinfo->stack_usage += size;
1102 ainfo->offset = cinfo->stack_usage;
1103 ainfo->slot_size = 8;
1104 /* Put arguments into 8 byte aligned stack slots */
1105 cinfo->stack_usage += 8;
1109 ainfo->storage = ArgInFRegR4;
1111 ainfo->storage = ArgInFReg;
1112 ainfo->reg = cinfo->fr;
1118 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1122 MonoClassField *field;
1123 MonoType *ftype, *prev_ftype = NULL;
1126 klass = mono_class_from_mono_type (t);
1128 while ((field = mono_class_get_fields (klass, &iter))) {
1129 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1131 ftype = mono_field_get_type (field);
1132 ftype = mini_get_underlying_type (ftype);
1134 if (MONO_TYPE_ISSTRUCT (ftype)) {
1135 int nested_nfields, nested_esize;
1136 int nested_field_offsets [16];
1138 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1140 if (nested_esize == 4)
1141 ftype = &mono_defaults.single_class->byval_arg;
1143 ftype = &mono_defaults.double_class->byval_arg;
1144 if (prev_ftype && prev_ftype->type != ftype->type)
1147 for (i = 0; i < nested_nfields; ++i) {
1148 if (nfields + i < 4)
1149 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1151 nfields += nested_nfields;
1153 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1155 if (prev_ftype && prev_ftype->type != ftype->type)
1159 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1163 if (nfields == 0 || nfields > 4)
1165 *out_nfields = nfields;
1166 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1171 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1173 int i, size, align_size, nregs, nfields, esize;
1174 int field_offsets [16];
1177 size = mini_type_stack_size_full (t, &align, cinfo->pinvoke);
1178 align_size = ALIGN_TO (size, 8);
1180 nregs = align_size / 8;
1181 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1183 * The struct might include nested float structs aligned at 8,
1184 * so need to keep track of the offsets of the individual fields.
1186 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1187 ainfo->storage = ArgHFA;
1188 ainfo->reg = cinfo->fr;
1189 ainfo->nregs = nfields;
1191 ainfo->esize = esize;
1192 for (i = 0; i < nfields; ++i)
1193 ainfo->foffsets [i] = field_offsets [i];
1194 cinfo->fr += ainfo->nregs;
1196 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1197 cinfo->fr = FP_PARAM_REGS;
1198 size = ALIGN_TO (size, 8);
1199 ainfo->storage = ArgVtypeOnStack;
1200 ainfo->offset = cinfo->stack_usage;
1203 ainfo->nregs = nfields;
1204 ainfo->esize = esize;
1205 cinfo->stack_usage += size;
1210 if (align_size > 16) {
1211 ainfo->storage = ArgVtypeByRef;
1216 if (cinfo->gr + nregs > PARAM_REGS) {
1217 size = ALIGN_TO (size, 8);
1218 ainfo->storage = ArgVtypeOnStack;
1219 ainfo->offset = cinfo->stack_usage;
1221 cinfo->stack_usage += size;
1222 cinfo->gr = PARAM_REGS;
1224 ainfo->storage = ArgVtypeInIRegs;
1225 ainfo->reg = cinfo->gr;
1226 ainfo->nregs = nregs;
1233 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1237 ptype = mini_get_underlying_type (t);
1238 switch (ptype->type) {
1240 add_general (cinfo, ainfo, 1, TRUE);
1242 case MONO_TYPE_BOOLEAN:
1244 add_general (cinfo, ainfo, 1, FALSE);
1247 add_general (cinfo, ainfo, 2, TRUE);
1250 case MONO_TYPE_CHAR:
1251 add_general (cinfo, ainfo, 2, FALSE);
1254 add_general (cinfo, ainfo, 4, TRUE);
1257 add_general (cinfo, ainfo, 4, FALSE);
1262 case MONO_TYPE_FNPTR:
1263 case MONO_TYPE_CLASS:
1264 case MONO_TYPE_OBJECT:
1265 case MONO_TYPE_SZARRAY:
1266 case MONO_TYPE_ARRAY:
1267 case MONO_TYPE_STRING:
1270 add_general (cinfo, ainfo, 8, FALSE);
1273 add_fp (cinfo, ainfo, FALSE);
1276 add_fp (cinfo, ainfo, TRUE);
1278 case MONO_TYPE_VALUETYPE:
1279 case MONO_TYPE_TYPEDBYREF:
1280 add_valuetype (cinfo, ainfo, ptype);
1282 case MONO_TYPE_VOID:
1283 ainfo->storage = ArgNone;
1285 case MONO_TYPE_GENERICINST:
1286 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1287 add_general (cinfo, ainfo, 8, FALSE);
1288 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1290 * Treat gsharedvt arguments as large vtypes
1292 ainfo->storage = ArgVtypeByRef;
1293 ainfo->gsharedvt = TRUE;
1295 add_valuetype (cinfo, ainfo, ptype);
1299 case MONO_TYPE_MVAR:
1300 g_assert (mini_is_gsharedvt_type (ptype));
1301 ainfo->storage = ArgVtypeByRef;
1302 ainfo->gsharedvt = TRUE;
1305 g_assert_not_reached ();
1313 * Obtain information about a call according to the calling convention.
1316 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1320 int n, pstart, pindex;
1322 n = sig->hasthis + sig->param_count;
1325 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1327 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1330 cinfo->pinvoke = sig->pinvoke;
1333 add_param (cinfo, &cinfo->ret, sig->ret);
1334 if (cinfo->ret.storage == ArgVtypeByRef)
1335 cinfo->ret.reg = ARMREG_R8;
1339 cinfo->stack_usage = 0;
1343 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1345 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1346 ainfo = cinfo->args + sig->hasthis + pindex;
1348 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1349 /* Prevent implicit arguments and sig_cookie from
1350 being passed in registers */
1351 cinfo->gr = PARAM_REGS;
1352 cinfo->fr = FP_PARAM_REGS;
1353 /* Emit the signature cookie just before the implicit arguments */
1354 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1357 add_param (cinfo, ainfo, sig->params [pindex]);
1358 if (ainfo->storage == ArgVtypeByRef) {
1359 /* Pass the argument address in the next register */
1360 if (cinfo->gr >= PARAM_REGS) {
1361 ainfo->storage = ArgVtypeByRefOnStack;
1362 ainfo->offset = cinfo->stack_usage;
1363 cinfo->stack_usage += 8;
1365 ainfo->reg = cinfo->gr;
1371 /* Handle the case where there are no implicit arguments */
1372 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1373 /* Prevent implicit arguments and sig_cookie from
1374 being passed in registers */
1375 cinfo->gr = PARAM_REGS;
1376 cinfo->fr = FP_PARAM_REGS;
1377 /* Emit the signature cookie just before the implicit arguments */
1378 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1381 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1387 MonoMethodSignature *sig;
1390 MonoType **param_types;
1391 int n_fpargs, n_fpret;
1395 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1399 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1402 // FIXME: Add more cases
1403 switch (cinfo->ret.storage) {
1410 case ArgVtypeInIRegs:
1411 if (cinfo->ret.nregs > 2)
1420 for (i = 0; i < cinfo->nargs; ++i) {
1421 ArgInfo *ainfo = &cinfo->args [i];
1423 switch (ainfo->storage) {
1425 case ArgVtypeInIRegs:
1432 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1444 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1446 ArchDynCallInfo *info;
1450 cinfo = get_call_info (NULL, sig);
1452 if (!dyn_call_supported (cinfo, sig)) {
1457 info = g_new0 (ArchDynCallInfo, 1);
1458 // FIXME: Preprocess the info to speed up start_dyn_call ()
1460 info->cinfo = cinfo;
1461 info->rtype = mini_get_underlying_type (sig->ret);
1462 info->param_types = g_new0 (MonoType*, sig->param_count);
1463 for (i = 0; i < sig->param_count; ++i)
1464 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1466 switch (cinfo->ret.storage) {
1472 info->n_fpret = cinfo->ret.nregs;
1478 return (MonoDynCallInfo*)info;
1482 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1484 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1486 g_free (ainfo->cinfo);
1487 g_free (ainfo->param_types);
1492 bitcast_r4_to_r8 (float f)
1500 bitcast_r8_to_r4 (double f)
1508 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1510 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1511 DynCallArgs *p = (DynCallArgs*)buf;
1512 int aindex, arg_index, greg, i, pindex;
1513 MonoMethodSignature *sig = dinfo->sig;
1514 CallInfo *cinfo = dinfo->cinfo;
1515 int buffer_offset = 0;
1517 g_assert (buf_len >= sizeof (DynCallArgs));
1521 p->n_fpargs = dinfo->n_fpargs;
1522 p->n_fpret = dinfo->n_fpret;
1529 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1531 if (cinfo->ret.storage == ArgVtypeByRef)
1532 p->regs [ARMREG_R8] = (mgreg_t)ret;
1534 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1535 MonoType *t = dinfo->param_types [aindex];
1536 gpointer *arg = args [arg_index ++];
1537 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1540 if (ainfo->storage == ArgOnStack) {
1541 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1547 p->regs [slot] = (mgreg_t)*arg;
1551 if (ios_abi && ainfo->storage == ArgOnStack) {
1552 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1553 gboolean handled = TRUE;
1555 /* Special case arguments smaller than 1 machine word */
1557 case MONO_TYPE_BOOLEAN:
1559 *(guint8*)stack_arg = *(guint8*)arg;
1562 *(gint8*)stack_arg = *(gint8*)arg;
1565 case MONO_TYPE_CHAR:
1566 *(guint16*)stack_arg = *(guint16*)arg;
1569 *(gint16*)stack_arg = *(gint16*)arg;
1572 *(gint32*)stack_arg = *(gint32*)arg;
1575 *(guint32*)stack_arg = *(guint32*)arg;
1586 case MONO_TYPE_STRING:
1587 case MONO_TYPE_CLASS:
1588 case MONO_TYPE_ARRAY:
1589 case MONO_TYPE_SZARRAY:
1590 case MONO_TYPE_OBJECT:
1596 p->regs [slot] = (mgreg_t)*arg;
1598 case MONO_TYPE_BOOLEAN:
1600 p->regs [slot] = *(guint8*)arg;
1603 p->regs [slot] = *(gint8*)arg;
1606 p->regs [slot] = *(gint16*)arg;
1609 case MONO_TYPE_CHAR:
1610 p->regs [slot] = *(guint16*)arg;
1613 p->regs [slot] = *(gint32*)arg;
1616 p->regs [slot] = *(guint32*)arg;
1619 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1623 p->fpregs [ainfo->reg] = *(double*)arg;
1626 case MONO_TYPE_GENERICINST:
1627 if (MONO_TYPE_IS_REFERENCE (t)) {
1628 p->regs [slot] = (mgreg_t)*arg;
1631 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1632 MonoClass *klass = mono_class_from_mono_type (t);
1633 guint8 *nullable_buf;
1637 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1638 * if the nullable param is passed by ref.
1640 size = mono_class_value_size (klass, NULL);
1641 nullable_buf = p->buffer + buffer_offset;
1642 buffer_offset += size;
1643 g_assert (buffer_offset <= 256);
1645 /* The argument pointed to by arg is either a boxed vtype or null */
1646 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1648 arg = (gpointer*)nullable_buf;
1654 case MONO_TYPE_VALUETYPE:
1655 switch (ainfo->storage) {
1656 case ArgVtypeInIRegs:
1657 for (i = 0; i < ainfo->nregs; ++i)
1658 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1661 if (ainfo->esize == 4) {
1662 for (i = 0; i < ainfo->nregs; ++i)
1663 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1665 for (i = 0; i < ainfo->nregs; ++i)
1666 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1668 p->n_fpargs += ainfo->nregs;
1671 p->regs [slot] = (mgreg_t)arg;
1674 g_assert_not_reached ();
1679 g_assert_not_reached ();
1685 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1687 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1688 CallInfo *cinfo = ainfo->cinfo;
1689 DynCallArgs *args = (DynCallArgs*)buf;
1690 MonoType *ptype = ainfo->rtype;
1691 guint8 *ret = args->ret;
1692 mgreg_t res = args->res;
1693 mgreg_t res2 = args->res2;
1696 if (cinfo->ret.storage == ArgVtypeByRef)
1699 switch (ptype->type) {
1700 case MONO_TYPE_VOID:
1701 *(gpointer*)ret = NULL;
1703 case MONO_TYPE_STRING:
1704 case MONO_TYPE_CLASS:
1705 case MONO_TYPE_ARRAY:
1706 case MONO_TYPE_SZARRAY:
1707 case MONO_TYPE_OBJECT:
1711 *(gpointer*)ret = (gpointer)res;
1717 case MONO_TYPE_BOOLEAN:
1718 *(guint8*)ret = res;
1721 *(gint16*)ret = res;
1724 case MONO_TYPE_CHAR:
1725 *(guint16*)ret = res;
1728 *(gint32*)ret = res;
1731 *(guint32*)ret = res;
1735 *(guint64*)ret = res;
1738 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1741 *(double*)ret = args->fpregs [0];
1743 case MONO_TYPE_GENERICINST:
1744 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1745 *(gpointer*)ret = (gpointer)res;
1750 case MONO_TYPE_VALUETYPE:
1751 switch (ainfo->cinfo->ret.storage) {
1752 case ArgVtypeInIRegs:
1753 *(mgreg_t*)ret = res;
1754 if (ainfo->cinfo->ret.nregs > 1)
1755 ((mgreg_t*)ret) [1] = res2;
1758 /* Use the same area for returning fp values */
1759 if (cinfo->ret.esize == 4) {
1760 for (i = 0; i < cinfo->ret.nregs; ++i)
1761 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1763 for (i = 0; i < cinfo->ret.nregs; ++i)
1764 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1768 g_assert_not_reached ();
1773 g_assert_not_reached ();
1778 void sys_icache_invalidate (void *start, size_t len);
1782 mono_arch_flush_icache (guint8 *code, gint size)
1784 #ifndef MONO_CROSS_COMPILE
1786 sys_icache_invalidate (code, size);
1788 /* Don't rely on GCC's __clear_cache implementation, as it caches
1789 * icache/dcache cache line sizes, that can vary between cores on
1790 * big.LITTLE architectures. */
1791 guint64 end = (guint64) (code + size);
1793 /* always go with cacheline size of 4 bytes as this code isn't perf critical
1794 * anyway. Reading the cache line size from a machine register can be racy
1795 * on a big.LITTLE architecture if the cores don't have the same cache line
1797 const size_t icache_line_size = 4;
1798 const size_t dcache_line_size = 4;
1800 addr = (guint64) code & ~(guint64) (dcache_line_size - 1);
1801 for (; addr < end; addr += dcache_line_size)
1802 asm volatile("dc civac, %0" : : "r" (addr) : "memory");
1803 asm volatile("dsb ish" : : : "memory");
1805 addr = (guint64) code & ~(guint64) (icache_line_size - 1);
1806 for (; addr < end; addr += icache_line_size)
1807 asm volatile("ic ivau, %0" : : "r" (addr) : "memory");
1809 asm volatile ("dsb ish" : : : "memory");
1810 asm volatile ("isb" : : : "memory");
1818 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1825 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1830 for (i = 0; i < cfg->num_varinfo; i++) {
1831 MonoInst *ins = cfg->varinfo [i];
1832 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1835 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1838 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1839 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1842 if (mono_is_regsize_var (ins->inst_vtype)) {
1843 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1844 g_assert (i == vmv->idx);
1845 vars = g_list_prepend (vars, vmv);
1849 vars = mono_varlist_sort (cfg, vars, 0);
1855 mono_arch_get_global_int_regs (MonoCompile *cfg)
1860 /* r28 is reserved for cfg->arch.args_reg */
1861 /* r27 is reserved for the imt argument */
1862 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1863 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1869 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1871 MonoInst *ins = cfg->varinfo [vmv->idx];
1873 if (ins->opcode == OP_ARG)
1880 mono_arch_create_vars (MonoCompile *cfg)
1882 MonoMethodSignature *sig;
1885 sig = mono_method_signature (cfg->method);
1886 if (!cfg->arch.cinfo)
1887 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1888 cinfo = cfg->arch.cinfo;
1890 if (cinfo->ret.storage == ArgVtypeByRef) {
1891 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1892 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1895 if (cfg->gen_sdb_seq_points) {
1898 if (cfg->compile_aot) {
1899 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1900 ins->flags |= MONO_INST_VOLATILE;
1901 cfg->arch.seq_point_info_var = ins;
1904 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1905 ins->flags |= MONO_INST_VOLATILE;
1906 cfg->arch.ss_tramp_var = ins;
1908 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1909 ins->flags |= MONO_INST_VOLATILE;
1910 cfg->arch.bp_tramp_var = ins;
1913 if (cfg->method->save_lmf) {
1914 cfg->create_lmf_var = TRUE;
1917 cfg->lmf_ir_mono_lmf = TRUE;
1923 mono_arch_allocate_vars (MonoCompile *cfg)
1925 MonoMethodSignature *sig;
1929 int i, offset, size, align;
1930 guint32 locals_stack_size, locals_stack_align;
1934 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1935 * Compute cfg->stack_offset and update cfg->used_int_regs.
1938 sig = mono_method_signature (cfg->method);
1940 if (!cfg->arch.cinfo)
1941 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1942 cinfo = cfg->arch.cinfo;
1945 * The ARM64 ABI always uses a frame pointer.
1946 * The instruction set prefers positive offsets, so fp points to the bottom of the
1947 * frame, and stack slots are at positive offsets.
1948 * If some arguments are received on the stack, their offsets relative to fp can
1949 * not be computed right now because the stack frame might grow due to spilling
1950 * done by the local register allocator. To solve this, we reserve a register
1951 * which points to them.
1952 * The stack frame looks like this:
1953 * args_reg -> <bottom of parent frame>
1955 * fp -> <saved fp+lr>
1956 * sp -> <localloc/params area>
1958 cfg->frame_reg = ARMREG_FP;
1959 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1965 if (cinfo->stack_usage) {
1966 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1967 cfg->arch.args_reg = ARMREG_R28;
1968 cfg->used_int_regs |= 1 << ARMREG_R28;
1971 if (cfg->method->save_lmf) {
1972 /* The LMF var is allocated normally */
1974 /* Callee saved regs */
1975 cfg->arch.saved_gregs_offset = offset;
1976 for (i = 0; i < 32; ++i)
1977 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1982 switch (cinfo->ret.storage) {
1988 cfg->ret->opcode = OP_REGVAR;
1989 cfg->ret->dreg = cinfo->ret.reg;
1991 case ArgVtypeInIRegs:
1993 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1994 cfg->ret->opcode = OP_REGOFFSET;
1995 cfg->ret->inst_basereg = cfg->frame_reg;
1996 cfg->ret->inst_offset = offset;
1997 if (cinfo->ret.storage == ArgHFA)
2004 /* This variable will be initalized in the prolog from R8 */
2005 cfg->vret_addr->opcode = OP_REGOFFSET;
2006 cfg->vret_addr->inst_basereg = cfg->frame_reg;
2007 cfg->vret_addr->inst_offset = offset;
2009 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2010 printf ("vret_addr =");
2011 mono_print_ins (cfg->vret_addr);
2015 g_assert_not_reached ();
2020 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2021 ainfo = cinfo->args + i;
2023 ins = cfg->args [i];
2024 if (ins->opcode == OP_REGVAR)
2027 ins->opcode = OP_REGOFFSET;
2028 ins->inst_basereg = cfg->frame_reg;
2030 switch (ainfo->storage) {
2034 // FIXME: Use nregs/size
2035 /* These will be copied to the stack in the prolog */
2036 ins->inst_offset = offset;
2042 case ArgVtypeOnStack:
2043 /* These are in the parent frame */
2044 g_assert (cfg->arch.args_reg);
2045 ins->inst_basereg = cfg->arch.args_reg;
2046 ins->inst_offset = ainfo->offset;
2048 case ArgVtypeInIRegs:
2050 ins->opcode = OP_REGOFFSET;
2051 ins->inst_basereg = cfg->frame_reg;
2052 /* These arguments are saved to the stack in the prolog */
2053 ins->inst_offset = offset;
2054 if (cfg->verbose_level >= 2)
2055 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2056 if (ainfo->storage == ArgHFA)
2062 case ArgVtypeByRefOnStack: {
2065 if (ainfo->gsharedvt) {
2066 ins->opcode = OP_REGOFFSET;
2067 ins->inst_basereg = cfg->arch.args_reg;
2068 ins->inst_offset = ainfo->offset;
2072 /* The vtype address is in the parent frame */
2073 g_assert (cfg->arch.args_reg);
2074 MONO_INST_NEW (cfg, vtaddr, 0);
2075 vtaddr->opcode = OP_REGOFFSET;
2076 vtaddr->inst_basereg = cfg->arch.args_reg;
2077 vtaddr->inst_offset = ainfo->offset;
2079 /* Need an indirection */
2080 ins->opcode = OP_VTARG_ADDR;
2081 ins->inst_left = vtaddr;
2084 case ArgVtypeByRef: {
2087 if (ainfo->gsharedvt) {
2088 ins->opcode = OP_REGOFFSET;
2089 ins->inst_basereg = cfg->frame_reg;
2090 ins->inst_offset = offset;
2095 /* The vtype address is in a register, will be copied to the stack in the prolog */
2096 MONO_INST_NEW (cfg, vtaddr, 0);
2097 vtaddr->opcode = OP_REGOFFSET;
2098 vtaddr->inst_basereg = cfg->frame_reg;
2099 vtaddr->inst_offset = offset;
2102 /* Need an indirection */
2103 ins->opcode = OP_VTARG_ADDR;
2104 ins->inst_left = vtaddr;
2108 g_assert_not_reached ();
2113 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2114 // FIXME: Allocate these to registers
2115 ins = cfg->arch.seq_point_info_var;
2119 offset += align - 1;
2120 offset &= ~(align - 1);
2121 ins->opcode = OP_REGOFFSET;
2122 ins->inst_basereg = cfg->frame_reg;
2123 ins->inst_offset = offset;
2126 ins = cfg->arch.ss_tramp_var;
2130 offset += align - 1;
2131 offset &= ~(align - 1);
2132 ins->opcode = OP_REGOFFSET;
2133 ins->inst_basereg = cfg->frame_reg;
2134 ins->inst_offset = offset;
2137 ins = cfg->arch.bp_tramp_var;
2141 offset += align - 1;
2142 offset &= ~(align - 1);
2143 ins->opcode = OP_REGOFFSET;
2144 ins->inst_basereg = cfg->frame_reg;
2145 ins->inst_offset = offset;
2150 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2151 if (locals_stack_align)
2152 offset = ALIGN_TO (offset, locals_stack_align);
2154 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2155 if (offsets [i] != -1) {
2156 ins = cfg->varinfo [i];
2157 ins->opcode = OP_REGOFFSET;
2158 ins->inst_basereg = cfg->frame_reg;
2159 ins->inst_offset = offset + offsets [i];
2160 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2163 offset += locals_stack_size;
2165 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2167 cfg->stack_offset = offset;
2172 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2177 LLVMCallInfo *linfo;
2179 n = sig->param_count + sig->hasthis;
2181 cinfo = get_call_info (cfg->mempool, sig);
2183 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2185 switch (cinfo->ret.storage) {
2192 linfo->ret.storage = LLVMArgVtypeByRef;
2195 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2196 // array which is returned in int regs
2199 linfo->ret.storage = LLVMArgFpStruct;
2200 linfo->ret.nslots = cinfo->ret.nregs;
2201 linfo->ret.esize = cinfo->ret.esize;
2203 case ArgVtypeInIRegs:
2204 /* LLVM models this by returning an int */
2205 linfo->ret.storage = LLVMArgVtypeAsScalar;
2206 linfo->ret.nslots = cinfo->ret.nregs;
2207 linfo->ret.esize = cinfo->ret.esize;
2210 g_assert_not_reached ();
2214 for (i = 0; i < n; ++i) {
2215 LLVMArgInfo *lainfo = &linfo->args [i];
2217 ainfo = cinfo->args + i;
2219 lainfo->storage = LLVMArgNone;
2221 switch (ainfo->storage) {
2228 lainfo->storage = LLVMArgNormal;
2231 case ArgVtypeByRefOnStack:
2232 lainfo->storage = LLVMArgVtypeByRef;
2237 lainfo->storage = LLVMArgAsFpArgs;
2238 lainfo->nslots = ainfo->nregs;
2239 lainfo->esize = ainfo->esize;
2240 for (j = 0; j < ainfo->nregs; ++j)
2241 lainfo->pair_storage [j] = LLVMArgInFPReg;
2244 case ArgVtypeInIRegs:
2245 lainfo->storage = LLVMArgAsIArgs;
2246 lainfo->nslots = ainfo->nregs;
2248 case ArgVtypeOnStack:
2252 lainfo->storage = LLVMArgAsFpArgs;
2253 lainfo->nslots = ainfo->nregs;
2254 lainfo->esize = ainfo->esize;
2255 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2256 for (j = 0; j < ainfo->nregs; ++j)
2257 lainfo->pair_storage [j] = LLVMArgInFPReg;
2259 lainfo->storage = LLVMArgAsIArgs;
2260 lainfo->nslots = ainfo->size / 8;
2264 g_assert_not_reached ();
2274 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2280 MONO_INST_NEW (cfg, ins, OP_MOVE);
2281 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2282 ins->sreg1 = arg->dreg;
2283 MONO_ADD_INS (cfg->cbb, ins);
2284 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2287 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2288 ins->dreg = mono_alloc_freg (cfg);
2289 ins->sreg1 = arg->dreg;
2290 MONO_ADD_INS (cfg->cbb, ins);
2291 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2294 if (COMPILE_LLVM (cfg))
2295 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2297 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2299 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2300 ins->dreg = mono_alloc_freg (cfg);
2301 ins->sreg1 = arg->dreg;
2302 MONO_ADD_INS (cfg->cbb, ins);
2303 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2306 g_assert_not_reached ();
2312 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2314 MonoMethodSignature *tmp_sig;
2317 if (call->tail_call)
2320 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2323 * mono_ArgIterator_Setup assumes the signature cookie is
2324 * passed first and all the arguments which were before it are
2325 * passed on the stack after the signature. So compensate by
2326 * passing a different signature.
2328 tmp_sig = mono_metadata_signature_dup (call->signature);
2329 tmp_sig->param_count -= call->signature->sentinelpos;
2330 tmp_sig->sentinelpos = 0;
2331 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2333 sig_reg = mono_alloc_ireg (cfg);
2334 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2336 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2340 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2342 MonoMethodSignature *sig;
2343 MonoInst *arg, *vtarg;
2348 sig = call->signature;
2350 cinfo = get_call_info (cfg->mempool, sig);
2352 switch (cinfo->ret.storage) {
2353 case ArgVtypeInIRegs:
2356 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2357 * the location pointed to by it after call in emit_move_return_value ().
2359 if (!cfg->arch.vret_addr_loc) {
2360 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2361 /* Prevent it from being register allocated or optimized away */
2362 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2365 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2368 /* Pass the vtype return address in R8 */
2369 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2370 vtarg->sreg1 = call->vret_var->dreg;
2371 vtarg->dreg = mono_alloc_preg (cfg);
2372 MONO_ADD_INS (cfg->cbb, vtarg);
2374 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2380 for (i = 0; i < cinfo->nargs; ++i) {
2381 ainfo = cinfo->args + i;
2382 arg = call->args [i];
2384 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2385 /* Emit the signature cookie just before the implicit arguments */
2386 emit_sig_cookie (cfg, call, cinfo);
2389 switch (ainfo->storage) {
2393 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2396 switch (ainfo->slot_size) {
2398 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2401 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2407 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2410 g_assert_not_reached ();
2415 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2418 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2420 case ArgVtypeInIRegs:
2422 case ArgVtypeByRefOnStack:
2423 case ArgVtypeOnStack:
2429 size = mono_class_value_size (arg->klass, &align);
2431 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2432 ins->sreg1 = arg->dreg;
2433 ins->klass = arg->klass;
2434 ins->backend.size = size;
2435 ins->inst_p0 = call;
2436 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2437 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2438 MONO_ADD_INS (cfg->cbb, ins);
2442 g_assert_not_reached ();
2447 /* Handle the case where there are no implicit arguments */
2448 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2449 emit_sig_cookie (cfg, call, cinfo);
2451 call->call_info = cinfo;
2452 call->stack_usage = cinfo->stack_usage;
2456 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2458 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459 ArgInfo *ainfo = ins->inst_p1;
2463 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2466 switch (ainfo->storage) {
2467 case ArgVtypeInIRegs:
2468 for (i = 0; i < ainfo->nregs; ++i) {
2469 // FIXME: Smaller sizes
2470 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2471 load->dreg = mono_alloc_ireg (cfg);
2472 load->inst_basereg = src->dreg;
2473 load->inst_offset = i * sizeof(mgreg_t);
2474 MONO_ADD_INS (cfg->cbb, load);
2475 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2479 for (i = 0; i < ainfo->nregs; ++i) {
2480 if (ainfo->esize == 4)
2481 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2483 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2484 load->dreg = mono_alloc_freg (cfg);
2485 load->inst_basereg = src->dreg;
2486 load->inst_offset = ainfo->foffsets [i];
2487 MONO_ADD_INS (cfg->cbb, load);
2488 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2492 case ArgVtypeByRefOnStack: {
2493 MonoInst *vtaddr, *load, *arg;
2495 /* Pass the vtype address in a reg/on the stack */
2496 if (ainfo->gsharedvt) {
2499 /* Make a copy of the argument */
2500 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2502 MONO_INST_NEW (cfg, load, OP_LDADDR);
2503 load->inst_p0 = vtaddr;
2504 vtaddr->flags |= MONO_INST_INDIRECT;
2505 load->type = STACK_MP;
2506 load->klass = vtaddr->klass;
2507 load->dreg = mono_alloc_ireg (cfg);
2508 MONO_ADD_INS (cfg->cbb, load);
2509 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2512 if (ainfo->storage == ArgVtypeByRef) {
2513 MONO_INST_NEW (cfg, arg, OP_MOVE);
2514 arg->dreg = mono_alloc_preg (cfg);
2515 arg->sreg1 = load->dreg;
2516 MONO_ADD_INS (cfg->cbb, arg);
2517 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2519 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2523 case ArgVtypeOnStack:
2524 for (i = 0; i < ainfo->size / 8; ++i) {
2525 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2526 load->dreg = mono_alloc_ireg (cfg);
2527 load->inst_basereg = src->dreg;
2528 load->inst_offset = i * 8;
2529 MONO_ADD_INS (cfg->cbb, load);
2530 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2534 g_assert_not_reached ();
2540 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2542 MonoMethodSignature *sig;
2545 sig = mono_method_signature (cfg->method);
2546 if (!cfg->arch.cinfo)
2547 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2548 cinfo = cfg->arch.cinfo;
2550 switch (cinfo->ret.storage) {
2554 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2557 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2560 if (COMPILE_LLVM (cfg))
2561 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2563 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2565 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2568 g_assert_not_reached ();
2574 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2579 if (cfg->compile_aot && !cfg->full_aot)
2580 /* OP_TAILCALL doesn't work with AOT */
2583 c1 = get_call_info (NULL, caller_sig);
2584 c2 = get_call_info (NULL, callee_sig);
2586 // FIXME: Relax these restrictions
2587 if (c1->stack_usage != 0)
2589 if (c1->stack_usage != c2->stack_usage)
2591 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2601 mono_arch_is_inst_imm (gint64 imm)
2603 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2607 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2614 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2621 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2627 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2632 #define ADD_NEW_INS(cfg,dest,op) do { \
2633 MONO_INST_NEW ((cfg), (dest), (op)); \
2634 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2638 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2640 MonoInst *ins, *temp, *last_ins = NULL;
2642 MONO_BB_FOR_EACH_INS (bb, ins) {
2643 switch (ins->opcode) {
2648 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2649 /* ARM sets the C flag to 1 if there was _no_ overflow */
2650 ins->next->opcode = OP_COND_EXC_NC;
2654 case OP_IDIV_UN_IMM:
2655 case OP_IREM_UN_IMM:
2657 mono_decompose_op_imm (cfg, bb, ins);
2659 case OP_LOCALLOC_IMM:
2660 if (ins->inst_imm > 32) {
2661 ADD_NEW_INS (cfg, temp, OP_ICONST);
2662 temp->inst_c0 = ins->inst_imm;
2663 temp->dreg = mono_alloc_ireg (cfg);
2664 ins->sreg1 = temp->dreg;
2665 ins->opcode = mono_op_imm_to_op (ins->opcode);
2668 case OP_ICOMPARE_IMM:
2669 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2670 ins->next->opcode = OP_ARM64_CBZW;
2671 ins->next->sreg1 = ins->sreg1;
2673 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2674 ins->next->opcode = OP_ARM64_CBNZW;
2675 ins->next->sreg1 = ins->sreg1;
2679 case OP_LCOMPARE_IMM:
2680 case OP_COMPARE_IMM:
2681 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2682 ins->next->opcode = OP_ARM64_CBZX;
2683 ins->next->sreg1 = ins->sreg1;
2685 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2686 ins->next->opcode = OP_ARM64_CBNZX;
2687 ins->next->sreg1 = ins->sreg1;
2692 gboolean swap = FALSE;
2696 /* Optimized away */
2702 * FP compares with unordered operands set the flags
2703 * to NZCV=0011, which matches some non-unordered compares
2704 * as well, like LE, so have to swap the operands.
2706 switch (ins->next->opcode) {
2708 ins->next->opcode = OP_FBGT;
2712 ins->next->opcode = OP_FBGE;
2720 ins->sreg1 = ins->sreg2;
2731 bb->last_ins = last_ins;
2732 bb->max_vreg = cfg->next_vreg;
2736 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2741 opcode_to_armcond (int opcode)
2752 case OP_COND_EXC_IEQ:
2753 case OP_COND_EXC_EQ:
2770 case OP_COND_EXC_IGT:
2771 case OP_COND_EXC_GT:
2786 case OP_COND_EXC_ILT:
2787 case OP_COND_EXC_LT:
2795 case OP_COND_EXC_INE_UN:
2796 case OP_COND_EXC_NE_UN:
2802 case OP_COND_EXC_IGE_UN:
2803 case OP_COND_EXC_GE_UN:
2813 case OP_COND_EXC_IGT_UN:
2814 case OP_COND_EXC_GT_UN:
2820 case OP_COND_EXC_ILE_UN:
2821 case OP_COND_EXC_LE_UN:
2829 case OP_COND_EXC_ILT_UN:
2830 case OP_COND_EXC_LT_UN:
2833 * FCMP sets the NZCV condition bits as follows:
2838 * ARMCOND_LT is N!=V, so it matches unordered too, so
2839 * fclt and fclt_un need to be special cased.
2849 case OP_COND_EXC_IC:
2851 case OP_COND_EXC_OV:
2852 case OP_COND_EXC_IOV:
2854 case OP_COND_EXC_NC:
2855 case OP_COND_EXC_INC:
2857 case OP_COND_EXC_NO:
2858 case OP_COND_EXC_INO:
2861 printf ("%s\n", mono_inst_name (opcode));
2862 g_assert_not_reached ();
2867 /* This clobbers LR */
2868 static inline __attribute__((warn_unused_result)) guint8*
2869 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2873 cond = opcode_to_armcond (opcode);
2875 arm_adrx (code, ARMREG_IP1, code);
2876 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2877 arm_bcc (code, cond, 0);
2882 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2887 call = (MonoCallInst*)ins;
2888 cinfo = call->call_info;
2890 switch (cinfo->ret.storage) {
2894 /* LLVM compiled code might only set the bottom bits */
2895 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2896 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2897 else if (call->inst.dreg != cinfo->ret.reg)
2898 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2901 if (call->inst.dreg != cinfo->ret.reg)
2902 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2906 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2908 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2910 case ArgVtypeInIRegs: {
2911 MonoInst *loc = cfg->arch.vret_addr_loc;
2914 /* Load the destination address */
2915 g_assert (loc && loc->opcode == OP_REGOFFSET);
2916 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2917 for (i = 0; i < cinfo->ret.nregs; ++i)
2918 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2922 MonoInst *loc = cfg->arch.vret_addr_loc;
2925 /* Load the destination address */
2926 g_assert (loc && loc->opcode == OP_REGOFFSET);
2927 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2928 for (i = 0; i < cinfo->ret.nregs; ++i) {
2929 if (cinfo->ret.esize == 4)
2930 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2932 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2939 g_assert_not_reached ();
2946 * emit_branch_island:
2948 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2951 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2954 int offset, island_size;
2956 /* Iterate over the patch infos added so far by this bb */
2958 for (ji = cfg->patch_info; ji; ji = ji->next) {
2959 if (ji->ip.i < start_offset)
2960 /* The patch infos are in reverse order, so this means the end */
2962 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2967 offset = code - cfg->native_code;
2968 if (offset > (cfg->code_size - island_size - 16)) {
2969 cfg->code_size *= 2;
2970 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2971 code = cfg->native_code + offset;
2974 /* Branch over the island */
2975 arm_b (code, code + 4 + island_size);
2977 for (ji = cfg->patch_info; ji; ji = ji->next) {
2978 if (ji->ip.i < start_offset)
2980 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2981 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2982 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2983 /* Rewrite the patch so it points to the unconditional branch */
2984 ji->ip.i = code - cfg->native_code;
2985 ji->relocation = MONO_R_ARM64_B;
2994 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2999 guint8 *code = cfg->native_code + cfg->code_len;
3000 int start_offset, max_len, dreg, sreg1, sreg2;
3003 if (cfg->verbose_level > 2)
3004 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3006 start_offset = code - cfg->native_code;
3008 MONO_BB_FOR_EACH_INS (bb, ins) {
3009 offset = code - cfg->native_code;
3011 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3013 if (offset > (cfg->code_size - max_len - 16)) {
3014 cfg->code_size *= 2;
3015 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3016 code = cfg->native_code + offset;
3019 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
3020 /* Emit a branch island for large basic blocks */
3021 code = emit_branch_island (cfg, code, start_offset);
3022 offset = code - cfg->native_code;
3023 start_offset = offset;
3026 mono_debug_record_line_number (cfg, ins, offset);
3031 imm = ins->inst_imm;
3033 switch (ins->opcode) {
3035 code = emit_imm (code, dreg, ins->inst_c0);
3038 code = emit_imm64 (code, dreg, ins->inst_c0);
3042 arm_movx (code, dreg, sreg1);
3045 case OP_RELAXED_NOP:
3048 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3049 code = emit_imm64_template (code, dreg);
3053 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3054 * So instead of emitting a trap, we emit a call a C function and place a
3057 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3062 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3063 // FIXME: andx_imm doesn't work yet
3064 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3065 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3066 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3067 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3068 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3069 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3072 /* ip1 = pointer, ip0 = end */
3073 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3075 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3077 arm_bcc (code, ARMCOND_EQ, 0);
3078 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3079 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3080 arm_b (code, buf [0]);
3081 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3083 arm_movspx (code, dreg, ARMREG_SP);
3084 if (cfg->param_area)
3085 code = emit_subx_sp_imm (code, cfg->param_area);
3088 case OP_LOCALLOC_IMM: {
3091 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3092 g_assert (arm_is_arith_imm (imm));
3093 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3096 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3098 while (offset < imm) {
3099 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3102 arm_movspx (code, dreg, ARMREG_SP);
3103 if (cfg->param_area)
3104 code = emit_subx_sp_imm (code, cfg->param_area);
3108 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3110 case OP_OBJC_GET_SELECTOR:
3111 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3112 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3113 arm_ldrx_lit (code, ins->dreg, 0);
3117 case OP_SEQ_POINT: {
3118 MonoInst *info_var = cfg->arch.seq_point_info_var;
3121 * For AOT, we use one got slot per method, which will point to a
3122 * SeqPointInfo structure, containing all the information required
3123 * by the code below.
3125 if (cfg->compile_aot) {
3126 g_assert (info_var);
3127 g_assert (info_var->opcode == OP_REGOFFSET);
3130 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3131 MonoInst *var = cfg->arch.ss_tramp_var;
3134 g_assert (var->opcode == OP_REGOFFSET);
3135 /* Load ss_tramp_var */
3136 /* This is equal to &ss_trampoline */
3137 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3138 /* Load the trampoline address */
3139 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3140 /* Call it if it is non-null */
3141 arm_cbzx (code, ARMREG_IP1, code + 8);
3142 arm_blrx (code, ARMREG_IP1);
3145 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3147 if (cfg->compile_aot) {
3148 guint32 offset = code - cfg->native_code;
3151 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3152 /* Add the offset */
3153 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3154 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3155 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3156 /* Skip the load if its 0 */
3157 arm_cbzx (code, ARMREG_IP1, code + 8);
3158 /* Call the breakpoint trampoline */
3159 arm_blrx (code, ARMREG_IP1);
3161 MonoInst *var = cfg->arch.bp_tramp_var;
3164 g_assert (var->opcode == OP_REGOFFSET);
3165 /* Load the address of the bp trampoline into IP0 */
3166 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3168 * A placeholder for a possible breakpoint inserted by
3169 * mono_arch_set_breakpoint ().
3178 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3182 arm_brx (code, sreg1);
3214 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3215 cond = opcode_to_armcond (ins->opcode);
3216 arm_bcc (code, cond, 0);
3220 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3221 /* For fp compares, ARMCOND_LT is lt or unordered */
3222 arm_bcc (code, ARMCOND_LT, 0);
3225 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3226 arm_bcc (code, ARMCOND_EQ, 0);
3227 offset = code - cfg->native_code;
3228 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3229 /* For fp compares, ARMCOND_LT is lt or unordered */
3230 arm_bcc (code, ARMCOND_LT, 0);
3233 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3234 arm_cbzw (code, sreg1, 0);
3237 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3238 arm_cbzx (code, sreg1, 0);
3240 case OP_ARM64_CBNZW:
3241 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3242 arm_cbnzw (code, sreg1, 0);
3244 case OP_ARM64_CBNZX:
3245 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3246 arm_cbnzx (code, sreg1, 0);
3250 arm_addw (code, dreg, sreg1, sreg2);
3253 arm_addx (code, dreg, sreg1, sreg2);
3256 arm_subw (code, dreg, sreg1, sreg2);
3259 arm_subx (code, dreg, sreg1, sreg2);
3262 arm_andw (code, dreg, sreg1, sreg2);
3265 arm_andx (code, dreg, sreg1, sreg2);
3268 arm_orrw (code, dreg, sreg1, sreg2);
3271 arm_orrx (code, dreg, sreg1, sreg2);
3274 arm_eorw (code, dreg, sreg1, sreg2);
3277 arm_eorx (code, dreg, sreg1, sreg2);
3280 arm_negw (code, dreg, sreg1);
3283 arm_negx (code, dreg, sreg1);
3286 arm_mvnw (code, dreg, sreg1);
3289 arm_mvnx (code, dreg, sreg1);
3292 arm_addsw (code, dreg, sreg1, sreg2);
3296 arm_addsx (code, dreg, sreg1, sreg2);
3299 arm_subsw (code, dreg, sreg1, sreg2);
3303 arm_subsx (code, dreg, sreg1, sreg2);
3306 arm_cmpw (code, sreg1, sreg2);
3310 arm_cmpx (code, sreg1, sreg2);
3313 code = emit_addw_imm (code, dreg, sreg1, imm);
3317 code = emit_addx_imm (code, dreg, sreg1, imm);
3320 code = emit_subw_imm (code, dreg, sreg1, imm);
3323 code = emit_subx_imm (code, dreg, sreg1, imm);
3326 code = emit_andw_imm (code, dreg, sreg1, imm);
3330 code = emit_andx_imm (code, dreg, sreg1, imm);
3333 code = emit_orrw_imm (code, dreg, sreg1, imm);
3336 code = emit_orrx_imm (code, dreg, sreg1, imm);
3339 code = emit_eorw_imm (code, dreg, sreg1, imm);
3342 code = emit_eorx_imm (code, dreg, sreg1, imm);
3344 case OP_ICOMPARE_IMM:
3345 code = emit_cmpw_imm (code, sreg1, imm);
3347 case OP_LCOMPARE_IMM:
3348 case OP_COMPARE_IMM:
3350 arm_cmpx (code, sreg1, ARMREG_RZR);
3352 // FIXME: 32 vs 64 bit issues for 0xffffffff
3353 code = emit_imm64 (code, ARMREG_LR, imm);
3354 arm_cmpx (code, sreg1, ARMREG_LR);
3358 arm_lslvw (code, dreg, sreg1, sreg2);
3361 arm_lslvx (code, dreg, sreg1, sreg2);
3364 arm_asrvw (code, dreg, sreg1, sreg2);
3367 arm_asrvx (code, dreg, sreg1, sreg2);
3370 arm_lsrvw (code, dreg, sreg1, sreg2);
3373 arm_lsrvx (code, dreg, sreg1, sreg2);
3377 arm_movx (code, dreg, sreg1);
3379 arm_lslw (code, dreg, sreg1, imm);
3383 arm_movx (code, dreg, sreg1);
3385 arm_lslx (code, dreg, sreg1, imm);
3389 arm_movx (code, dreg, sreg1);
3391 arm_asrw (code, dreg, sreg1, imm);
3396 arm_movx (code, dreg, sreg1);
3398 arm_asrx (code, dreg, sreg1, imm);
3400 case OP_ISHR_UN_IMM:
3402 arm_movx (code, dreg, sreg1);
3404 arm_lsrw (code, dreg, sreg1, imm);
3407 case OP_LSHR_UN_IMM:
3409 arm_movx (code, dreg, sreg1);
3411 arm_lsrx (code, dreg, sreg1, imm);
3416 arm_sxtwx (code, dreg, sreg1);
3419 /* Clean out the upper word */
3420 arm_movw (code, dreg, sreg1);
3423 arm_lslx (code, dreg, sreg1, imm);
3426 /* MULTIPLY/DIVISION */
3429 // FIXME: Optimize this
3430 /* Check for zero */
3431 arm_cmpx_imm (code, sreg2, 0);
3432 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3433 /* Check for INT_MIN/-1 */
3434 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3435 arm_cmpx (code, sreg1, ARMREG_IP0);
3436 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3437 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3438 arm_cmpx (code, sreg2, ARMREG_IP0);
3439 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3440 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3441 arm_cmpx_imm (code, ARMREG_IP0, 1);
3442 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3443 if (ins->opcode == OP_IREM) {
3444 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3445 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3447 arm_sdivw (code, dreg, sreg1, sreg2);
3451 arm_cmpx_imm (code, sreg2, 0);
3452 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3453 arm_udivw (code, dreg, sreg1, sreg2);
3456 arm_cmpx_imm (code, sreg2, 0);
3457 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3458 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3459 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3463 // FIXME: Optimize this
3464 /* Check for zero */
3465 arm_cmpx_imm (code, sreg2, 0);
3466 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3467 /* Check for INT64_MIN/-1 */
3468 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3469 arm_cmpx (code, sreg1, ARMREG_IP0);
3470 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3471 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3472 arm_cmpx (code, sreg2, ARMREG_IP0);
3473 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3474 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3475 arm_cmpx_imm (code, ARMREG_IP0, 1);
3476 /* 64 bit uses ArithmeticException */
3477 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3478 if (ins->opcode == OP_LREM) {
3479 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3480 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3482 arm_sdivx (code, dreg, sreg1, sreg2);
3486 arm_cmpx_imm (code, sreg2, 0);
3487 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3488 arm_udivx (code, dreg, sreg1, sreg2);
3491 arm_cmpx_imm (code, sreg2, 0);
3492 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3493 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3494 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3497 arm_mulw (code, dreg, sreg1, sreg2);
3500 arm_mulx (code, dreg, sreg1, sreg2);
3503 code = emit_imm (code, ARMREG_LR, imm);
3504 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3508 code = emit_imm (code, ARMREG_LR, imm);
3509 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3513 case OP_ICONV_TO_I1:
3514 case OP_LCONV_TO_I1:
3515 arm_sxtbx (code, dreg, sreg1);
3517 case OP_ICONV_TO_I2:
3518 case OP_LCONV_TO_I2:
3519 arm_sxthx (code, dreg, sreg1);
3521 case OP_ICONV_TO_U1:
3522 case OP_LCONV_TO_U1:
3523 arm_uxtbw (code, dreg, sreg1);
3525 case OP_ICONV_TO_U2:
3526 case OP_LCONV_TO_U2:
3527 arm_uxthw (code, dreg, sreg1);
3553 cond = opcode_to_armcond (ins->opcode);
3554 arm_cset (code, cond, dreg);
3567 cond = opcode_to_armcond (ins->opcode);
3568 arm_fcmpd (code, sreg1, sreg2);
3569 arm_cset (code, cond, dreg);
3574 case OP_LOADI1_MEMBASE:
3575 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3577 case OP_LOADU1_MEMBASE:
3578 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3580 case OP_LOADI2_MEMBASE:
3581 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3583 case OP_LOADU2_MEMBASE:
3584 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3586 case OP_LOADI4_MEMBASE:
3587 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3589 case OP_LOADU4_MEMBASE:
3590 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3592 case OP_LOAD_MEMBASE:
3593 case OP_LOADI8_MEMBASE:
3594 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3596 case OP_STOREI1_MEMBASE_IMM:
3597 case OP_STOREI2_MEMBASE_IMM:
3598 case OP_STOREI4_MEMBASE_IMM:
3599 case OP_STORE_MEMBASE_IMM:
3600 case OP_STOREI8_MEMBASE_IMM: {
3604 code = emit_imm (code, ARMREG_LR, imm);
3607 immreg = ARMREG_RZR;
3610 switch (ins->opcode) {
3611 case OP_STOREI1_MEMBASE_IMM:
3612 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3614 case OP_STOREI2_MEMBASE_IMM:
3615 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3617 case OP_STOREI4_MEMBASE_IMM:
3618 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3620 case OP_STORE_MEMBASE_IMM:
3621 case OP_STOREI8_MEMBASE_IMM:
3622 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3625 g_assert_not_reached ();
3630 case OP_STOREI1_MEMBASE_REG:
3631 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3633 case OP_STOREI2_MEMBASE_REG:
3634 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3636 case OP_STOREI4_MEMBASE_REG:
3637 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3639 case OP_STORE_MEMBASE_REG:
3640 case OP_STOREI8_MEMBASE_REG:
3641 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3645 code = emit_tls_get (code, dreg, ins->inst_offset);
3647 case OP_TLS_GET_REG:
3648 code = emit_tls_get_reg (code, dreg, sreg1);
3651 code = emit_tls_set (code, sreg1, ins->inst_offset);
3653 case OP_TLS_SET_REG:
3654 code = emit_tls_set_reg (code, sreg1, sreg2);
3658 case OP_MEMORY_BARRIER:
3661 case OP_ATOMIC_ADD_I4: {
3665 arm_ldxrw (code, ARMREG_IP0, sreg1);
3666 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3667 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3668 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3671 arm_movx (code, dreg, ARMREG_IP0);
3674 case OP_ATOMIC_ADD_I8: {
3678 arm_ldxrx (code, ARMREG_IP0, sreg1);
3679 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3680 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3681 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3684 arm_movx (code, dreg, ARMREG_IP0);
3687 case OP_ATOMIC_EXCHANGE_I4: {
3691 arm_ldxrw (code, ARMREG_IP0, sreg1);
3692 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3693 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3696 arm_movx (code, dreg, ARMREG_IP0);
3699 case OP_ATOMIC_EXCHANGE_I8: {
3703 arm_ldxrx (code, ARMREG_IP0, sreg1);
3704 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3705 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3708 arm_movx (code, dreg, ARMREG_IP0);
3711 case OP_ATOMIC_CAS_I4: {
3714 /* sreg2 is the value, sreg3 is the comparand */
3716 arm_ldxrw (code, ARMREG_IP0, sreg1);
3717 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3719 arm_bcc (code, ARMCOND_NE, 0);
3720 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3721 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3722 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3725 arm_movx (code, dreg, ARMREG_IP0);
3728 case OP_ATOMIC_CAS_I8: {
3732 arm_ldxrx (code, ARMREG_IP0, sreg1);
3733 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3735 arm_bcc (code, ARMCOND_NE, 0);
3736 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3737 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3738 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3741 arm_movx (code, dreg, ARMREG_IP0);
3744 case OP_ATOMIC_LOAD_I1: {
3745 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3746 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3748 arm_ldarb (code, ins->dreg, ARMREG_LR);
3749 arm_sxtbx (code, ins->dreg, ins->dreg);
3752 case OP_ATOMIC_LOAD_U1: {
3753 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3754 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3756 arm_ldarb (code, ins->dreg, ARMREG_LR);
3757 arm_uxtbx (code, ins->dreg, ins->dreg);
3760 case OP_ATOMIC_LOAD_I2: {
3761 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3762 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3764 arm_ldarh (code, ins->dreg, ARMREG_LR);
3765 arm_sxthx (code, ins->dreg, ins->dreg);
3768 case OP_ATOMIC_LOAD_U2: {
3769 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3770 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3772 arm_ldarh (code, ins->dreg, ARMREG_LR);
3773 arm_uxthx (code, ins->dreg, ins->dreg);
3776 case OP_ATOMIC_LOAD_I4: {
3777 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3778 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3780 arm_ldarw (code, ins->dreg, ARMREG_LR);
3781 arm_sxtwx (code, ins->dreg, ins->dreg);
3784 case OP_ATOMIC_LOAD_U4: {
3785 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3786 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3788 arm_ldarw (code, ins->dreg, ARMREG_LR);
3789 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3792 case OP_ATOMIC_LOAD_I8:
3793 case OP_ATOMIC_LOAD_U8: {
3794 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3795 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3797 arm_ldarx (code, ins->dreg, ARMREG_LR);
3800 case OP_ATOMIC_LOAD_R4: {
3801 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3802 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3805 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3806 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3808 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3809 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3810 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3814 case OP_ATOMIC_LOAD_R8: {
3815 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3816 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3818 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3819 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3822 case OP_ATOMIC_STORE_I1:
3823 case OP_ATOMIC_STORE_U1: {
3824 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3825 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3826 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3830 case OP_ATOMIC_STORE_I2:
3831 case OP_ATOMIC_STORE_U2: {
3832 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3833 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3834 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3838 case OP_ATOMIC_STORE_I4:
3839 case OP_ATOMIC_STORE_U4: {
3840 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3841 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3842 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3846 case OP_ATOMIC_STORE_I8:
3847 case OP_ATOMIC_STORE_U8: {
3848 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3849 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3850 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3854 case OP_ATOMIC_STORE_R4: {
3855 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3857 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3858 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3860 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3861 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3862 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3864 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3868 case OP_ATOMIC_STORE_R8: {
3869 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3870 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3871 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3872 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3879 guint64 imm = *(guint64*)ins->inst_p0;
3882 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3884 code = emit_imm64 (code, ARMREG_LR, imm);
3885 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3890 guint64 imm = *(guint32*)ins->inst_p0;
3892 code = emit_imm64 (code, ARMREG_LR, imm);
3894 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3896 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3897 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3901 case OP_LOADR8_MEMBASE:
3902 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3904 case OP_LOADR4_MEMBASE:
3906 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3908 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3909 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3912 case OP_STORER8_MEMBASE_REG:
3913 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3915 case OP_STORER4_MEMBASE_REG:
3917 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3919 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3920 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3925 arm_fmovd (code, dreg, sreg1);
3929 arm_fmovs (code, dreg, sreg1);
3931 case OP_MOVE_F_TO_I4:
3933 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3935 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3936 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3939 case OP_MOVE_I4_TO_F:
3941 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3943 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3944 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3947 case OP_MOVE_F_TO_I8:
3948 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3950 case OP_MOVE_I8_TO_F:
3951 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3954 arm_fcmpd (code, sreg1, sreg2);
3957 arm_fcmps (code, sreg1, sreg2);
3959 case OP_FCONV_TO_I1:
3960 arm_fcvtzs_dx (code, dreg, sreg1);
3961 arm_sxtbx (code, dreg, dreg);
3963 case OP_FCONV_TO_U1:
3964 arm_fcvtzu_dx (code, dreg, sreg1);
3965 arm_uxtbw (code, dreg, dreg);
3967 case OP_FCONV_TO_I2:
3968 arm_fcvtzs_dx (code, dreg, sreg1);
3969 arm_sxthx (code, dreg, dreg);
3971 case OP_FCONV_TO_U2:
3972 arm_fcvtzu_dx (code, dreg, sreg1);
3973 arm_uxthw (code, dreg, dreg);
3975 case OP_FCONV_TO_I4:
3976 arm_fcvtzs_dx (code, dreg, sreg1);
3977 arm_sxtwx (code, dreg, dreg);
3979 case OP_FCONV_TO_U4:
3980 arm_fcvtzu_dx (code, dreg, sreg1);
3982 case OP_FCONV_TO_I8:
3983 arm_fcvtzs_dx (code, dreg, sreg1);
3985 case OP_FCONV_TO_U8:
3986 arm_fcvtzu_dx (code, dreg, sreg1);
3988 case OP_FCONV_TO_R4:
3990 arm_fcvt_ds (code, dreg, sreg1);
3992 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3993 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3996 case OP_ICONV_TO_R4:
3998 arm_scvtf_rw_to_s (code, dreg, sreg1);
4000 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
4001 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
4004 case OP_LCONV_TO_R4:
4006 arm_scvtf_rx_to_s (code, dreg, sreg1);
4008 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
4009 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
4012 case OP_ICONV_TO_R8:
4013 arm_scvtf_rw_to_d (code, dreg, sreg1);
4015 case OP_LCONV_TO_R8:
4016 arm_scvtf_rx_to_d (code, dreg, sreg1);
4018 case OP_ICONV_TO_R_UN:
4019 arm_ucvtf_rw_to_d (code, dreg, sreg1);
4021 case OP_LCONV_TO_R_UN:
4022 arm_ucvtf_rx_to_d (code, dreg, sreg1);
4025 arm_fadd_d (code, dreg, sreg1, sreg2);
4028 arm_fsub_d (code, dreg, sreg1, sreg2);
4031 arm_fmul_d (code, dreg, sreg1, sreg2);
4034 arm_fdiv_d (code, dreg, sreg1, sreg2);
4038 g_assert_not_reached ();
4041 arm_fneg_d (code, dreg, sreg1);
4043 case OP_ARM_SETFREG_R4:
4044 arm_fcvt_ds (code, dreg, sreg1);
4047 /* Check for infinity */
4048 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
4049 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
4050 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
4051 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
4052 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
4053 /* Check for nans */
4054 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
4055 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
4056 arm_fmovd (code, dreg, sreg1);
4061 arm_fadd_s (code, dreg, sreg1, sreg2);
4064 arm_fsub_s (code, dreg, sreg1, sreg2);
4067 arm_fmul_s (code, dreg, sreg1, sreg2);
4070 arm_fdiv_s (code, dreg, sreg1, sreg2);
4073 arm_fneg_s (code, dreg, sreg1);
4075 case OP_RCONV_TO_I1:
4076 arm_fcvtzs_sx (code, dreg, sreg1);
4077 arm_sxtbx (code, dreg, dreg);
4079 case OP_RCONV_TO_U1:
4080 arm_fcvtzu_sx (code, dreg, sreg1);
4081 arm_uxtbw (code, dreg, dreg);
4083 case OP_RCONV_TO_I2:
4084 arm_fcvtzs_sx (code, dreg, sreg1);
4085 arm_sxthx (code, dreg, dreg);
4087 case OP_RCONV_TO_U2:
4088 arm_fcvtzu_sx (code, dreg, sreg1);
4089 arm_uxthw (code, dreg, dreg);
4091 case OP_RCONV_TO_I4:
4092 arm_fcvtzs_sx (code, dreg, sreg1);
4093 arm_sxtwx (code, dreg, dreg);
4095 case OP_RCONV_TO_U4:
4096 arm_fcvtzu_sx (code, dreg, sreg1);
4098 case OP_RCONV_TO_I8:
4099 arm_fcvtzs_sx (code, dreg, sreg1);
4101 case OP_RCONV_TO_U8:
4102 arm_fcvtzu_sx (code, dreg, sreg1);
4104 case OP_RCONV_TO_R8:
4105 arm_fcvt_sd (code, dreg, sreg1);
4107 case OP_RCONV_TO_R4:
4109 arm_fmovs (code, dreg, sreg1);
4121 cond = opcode_to_armcond (ins->opcode);
4122 arm_fcmps (code, sreg1, sreg2);
4123 arm_cset (code, cond, dreg);
4134 call = (MonoCallInst*)ins;
4135 if (ins->flags & MONO_INST_HAS_METHOD)
4136 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4138 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4139 code = emit_move_return_value (cfg, code, ins);
4141 case OP_VOIDCALL_REG:
4147 arm_blrx (code, sreg1);
4148 code = emit_move_return_value (cfg, code, ins);
4150 case OP_VOIDCALL_MEMBASE:
4151 case OP_CALL_MEMBASE:
4152 case OP_LCALL_MEMBASE:
4153 case OP_FCALL_MEMBASE:
4154 case OP_RCALL_MEMBASE:
4155 case OP_VCALL2_MEMBASE:
4156 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4157 arm_blrx (code, ARMREG_IP0);
4158 code = emit_move_return_value (cfg, code, ins);
4161 MonoCallInst *call = (MonoCallInst*)ins;
4163 g_assert (!cfg->method->save_lmf);
4165 // FIXME: Copy stack arguments
4167 /* Restore registers */
4168 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4171 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4173 if (cfg->compile_aot) {
4174 /* This is not a PLT patch */
4175 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4176 arm_brx (code, ARMREG_IP0);
4178 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4181 ins->flags |= MONO_INST_GC_CALLSITE;
4182 ins->backend.pc_offset = code - cfg->native_code;
4186 g_assert (cfg->arch.cinfo);
4187 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4188 arm_strx (code, ARMREG_IP0, sreg1, 0);
4191 MonoInst *var = cfg->dyn_call_var;
4192 guint8 *labels [16];
4196 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4197 * sreg2 is the function to call.
4200 g_assert (var->opcode == OP_REGOFFSET);
4202 arm_movx (code, ARMREG_LR, sreg1);
4203 arm_movx (code, ARMREG_IP1, sreg2);
4205 /* Save args buffer */
4206 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4208 /* Set fp argument regs */
4209 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4210 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4212 arm_bcc (code, ARMCOND_EQ, 0);
4213 for (i = 0; i < 8; ++i)
4214 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4215 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4217 /* Set stack args */
4218 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4219 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4220 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4223 /* Set argument registers + r8 */
4224 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4227 arm_blrx (code, ARMREG_IP1);
4230 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4231 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4232 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4233 /* Save fp result */
4234 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4235 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4237 arm_bcc (code, ARMCOND_EQ, 0);
4238 for (i = 0; i < 8; ++i)
4239 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4240 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4244 case OP_GENERIC_CLASS_INIT: {
4245 static int byte_offset = -1;
4246 static guint8 bitmask;
4249 if (byte_offset < 0)
4250 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4252 /* Load vtable->initialized */
4253 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4254 // FIXME: No andx_imm yet */
4255 code = mono_arm_emit_imm64 (code, ARMREG_IP1, bitmask);
4256 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
4258 arm_cbnzx (code, ARMREG_IP0, 0);
4261 g_assert (sreg1 == ARMREG_R0);
4262 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4263 (gpointer)"mono_generic_class_init");
4265 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4270 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4273 case OP_NOT_REACHED:
4276 case OP_IL_SEQ_POINT:
4277 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4282 case OP_COND_EXC_IC:
4283 case OP_COND_EXC_OV:
4284 case OP_COND_EXC_IOV:
4285 case OP_COND_EXC_NC:
4286 case OP_COND_EXC_INC:
4287 case OP_COND_EXC_NO:
4288 case OP_COND_EXC_INO:
4289 case OP_COND_EXC_EQ:
4290 case OP_COND_EXC_IEQ:
4291 case OP_COND_EXC_NE_UN:
4292 case OP_COND_EXC_INE_UN:
4293 case OP_COND_EXC_ILT:
4294 case OP_COND_EXC_LT:
4295 case OP_COND_EXC_ILT_UN:
4296 case OP_COND_EXC_LT_UN:
4297 case OP_COND_EXC_IGT:
4298 case OP_COND_EXC_GT:
4299 case OP_COND_EXC_IGT_UN:
4300 case OP_COND_EXC_GT_UN:
4301 case OP_COND_EXC_IGE:
4302 case OP_COND_EXC_GE:
4303 case OP_COND_EXC_IGE_UN:
4304 case OP_COND_EXC_GE_UN:
4305 case OP_COND_EXC_ILE:
4306 case OP_COND_EXC_LE:
4307 case OP_COND_EXC_ILE_UN:
4308 case OP_COND_EXC_LE_UN:
4309 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4312 if (sreg1 != ARMREG_R0)
4313 arm_movx (code, ARMREG_R0, sreg1);
4314 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4315 (gpointer)"mono_arch_throw_exception");
4318 if (sreg1 != ARMREG_R0)
4319 arm_movx (code, ARMREG_R0, sreg1);
4320 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4321 (gpointer)"mono_arch_rethrow_exception");
4323 case OP_CALL_HANDLER:
4324 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4326 cfg->thunk_area += THUNK_SIZE;
4328 case OP_START_HANDLER: {
4329 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4331 /* Save caller address */
4332 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4335 * Reserve a param area, see test_0_finally_param_area ().
4336 * This is needed because the param area is not set up when
4337 * we are called from EH code.
4339 if (cfg->param_area)
4340 code = emit_subx_sp_imm (code, cfg->param_area);
4344 case OP_ENDFILTER: {
4345 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4347 if (cfg->param_area)
4348 code = emit_addx_sp_imm (code, cfg->param_area);
4350 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4351 arm_movx (code, ARMREG_R0, sreg1);
4353 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4354 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4355 arm_brx (code, ARMREG_LR);
4359 if (ins->dreg != ARMREG_R0)
4360 arm_movx (code, ins->dreg, ARMREG_R0);
4362 case OP_GC_SAFE_POINT: {
4363 #if defined (USE_COOP_GC)
4366 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4367 /* Call it if it is non-null */
4369 arm_cbzx (code, ARMREG_IP1, 0);
4370 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4371 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4377 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4378 g_assert_not_reached ();
4381 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4382 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4383 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4384 g_assert_not_reached ();
4389 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4390 * insert branch islands between/inside basic blocks.
4392 if (cfg->arch.cond_branch_islands)
4393 code = emit_branch_island (cfg, code, start_offset);
4395 cfg->code_len = code - cfg->native_code;
4399 emit_move_args (MonoCompile *cfg, guint8 *code)
4406 cinfo = cfg->arch.cinfo;
4408 for (i = 0; i < cinfo->nargs; ++i) {
4409 ainfo = cinfo->args + i;
4410 ins = cfg->args [i];
4412 if (ins->opcode == OP_REGVAR) {
4413 switch (ainfo->storage) {
4415 arm_movx (code, ins->dreg, ainfo->reg);
4418 switch (ainfo->slot_size) {
4421 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4423 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4427 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4429 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4433 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4435 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4438 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4443 g_assert_not_reached ();
4447 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4448 g_assert (ins->opcode == OP_REGOFFSET);
4450 switch (ainfo->storage) {
4452 /* Stack slots for arguments have size 8 */
4453 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4456 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4459 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4464 case ArgVtypeByRefOnStack:
4465 case ArgVtypeOnStack:
4467 case ArgVtypeByRef: {
4468 MonoInst *addr_arg = ins->inst_left;
4470 if (ainfo->gsharedvt) {
4471 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4472 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4474 g_assert (ins->opcode == OP_VTARG_ADDR);
4475 g_assert (addr_arg->opcode == OP_REGOFFSET);
4476 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4480 case ArgVtypeInIRegs:
4481 for (part = 0; part < ainfo->nregs; part ++) {
4482 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4486 for (part = 0; part < ainfo->nregs; part ++) {
4487 if (ainfo->esize == 4)
4488 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4490 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4494 g_assert_not_reached ();
4504 * emit_store_regarray:
4506 * Emit code to store the registers in REGS into the appropriate elements of
4507 * the register array at BASEREG+OFFSET.
4509 static __attribute__((warn_unused_result)) guint8*
4510 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4514 for (i = 0; i < 32; ++i) {
4515 if (regs & (1 << i)) {
4516 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4517 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4519 } else if (i == ARMREG_SP) {
4520 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4521 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4523 arm_strx (code, i, basereg, offset + (i * 8));
4531 * emit_load_regarray:
4533 * Emit code to load the registers in REGS from the appropriate elements of
4534 * the register array at BASEREG+OFFSET.
4536 static __attribute__((warn_unused_result)) guint8*
4537 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4541 for (i = 0; i < 32; ++i) {
4542 if (regs & (1 << i)) {
4543 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4544 if (offset + (i * 8) < 500)
4545 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4547 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4548 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4551 } else if (i == ARMREG_SP) {
4552 g_assert_not_reached ();
4554 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4562 * emit_store_regset:
4564 * Emit code to store the registers in REGS into consecutive memory locations starting
4565 * at BASEREG+OFFSET.
4567 static __attribute__((warn_unused_result)) guint8*
4568 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4573 for (i = 0; i < 32; ++i) {
4574 if (regs & (1 << i)) {
4575 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4576 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4579 } else if (i == ARMREG_SP) {
4580 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4581 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4583 arm_strx (code, i, basereg, offset + (pos * 8));
4594 * Emit code to load the registers in REGS from consecutive memory locations starting
4595 * at BASEREG+OFFSET.
4597 static __attribute__((warn_unused_result)) guint8*
4598 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4603 for (i = 0; i < 32; ++i) {
4604 if (regs & (1 << i)) {
4605 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4606 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4609 } else if (i == ARMREG_SP) {
4610 g_assert_not_reached ();
4612 arm_ldrx (code, i, basereg, offset + (pos * 8));
4620 __attribute__((warn_unused_result)) guint8*
4621 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4623 return emit_load_regarray (code, regs, basereg, offset);
4626 __attribute__((warn_unused_result)) guint8*
4627 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4629 return emit_store_regarray (code, regs, basereg, offset);
4632 __attribute__((warn_unused_result)) guint8*
4633 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4635 return emit_store_regset (code, regs, basereg, offset);
4638 /* Same as emit_store_regset, but emit unwind info too */
4639 /* CFA_OFFSET is the offset between the CFA and basereg */
4640 static __attribute__((warn_unused_result)) guint8*
4641 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4643 int i, j, pos, nregs;
4644 guint32 cfa_regset = regs & ~no_cfa_regset;
4647 for (i = 0; i < 32; ++i) {
4649 if (regs & (1 << i)) {
4650 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4652 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4654 code = emit_strx (code, i, basereg, offset + (pos * 8));
4655 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4658 } else if (i == ARMREG_SP) {
4659 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4660 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4662 code = emit_strx (code, i, basereg, offset + (pos * 8));
4665 for (j = 0; j < nregs; ++j) {
4666 if (cfa_regset & (1 << (i + j)))
4667 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4680 * Emit code to initialize an LMF structure at LMF_OFFSET.
4684 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4687 * The LMF should contain all the state required to be able to reconstruct the machine state
4688 * at the current point of execution. Since the LMF is only read during EH, only callee
4689 * saved etc. registers need to be saved.
4690 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4691 * need to be restored during EH.
4695 arm_adrx (code, ARMREG_LR, code);
4696 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4697 /* gregs + fp + sp */
4698 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4699 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4705 mono_arch_emit_prolog (MonoCompile *cfg)
4707 MonoMethod *method = cfg->method;
4708 MonoMethodSignature *sig;
4711 int cfa_offset, max_offset;
4713 sig = mono_method_signature (method);
4714 cfg->code_size = 256 + sig->param_count * 64;
4715 code = cfg->native_code = g_malloc (cfg->code_size);
4717 /* This can be unaligned */
4718 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4724 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4727 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4728 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4730 /* sp -= cfg->stack_offset */
4731 /* This clobbers ip0/ip1 */
4732 code = emit_subx_sp_imm (code, cfg->stack_offset);
4733 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4735 cfa_offset += cfg->stack_offset;
4736 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4737 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4738 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4739 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4740 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4741 if (cfg->param_area) {
4742 /* The param area is below the frame pointer */
4743 code = emit_subx_sp_imm (code, cfg->param_area);
4746 if (cfg->method->save_lmf) {
4747 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4750 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4753 /* Setup args reg */
4754 if (cfg->arch.args_reg) {
4755 /* The register was already saved above */
4756 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4759 /* Save return area addr received in R8 */
4760 if (cfg->vret_addr) {
4761 MonoInst *ins = cfg->vret_addr;
4763 g_assert (ins->opcode == OP_REGOFFSET);
4764 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4767 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4768 if (cfg->rgctx_var) {
4769 MonoInst *ins = cfg->rgctx_var;
4771 g_assert (ins->opcode == OP_REGOFFSET);
4773 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4777 * Move arguments to their registers/stack locations.
4779 code = emit_move_args (cfg, code);
4781 /* Initialize seq_point_info_var */
4782 if (cfg->arch.seq_point_info_var) {
4783 MonoInst *ins = cfg->arch.seq_point_info_var;
4785 /* Initialize the variable from a GOT slot */
4786 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4787 g_assert (ins->opcode == OP_REGOFFSET);
4788 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4790 /* Initialize ss_tramp_var */
4791 ins = cfg->arch.ss_tramp_var;
4792 g_assert (ins->opcode == OP_REGOFFSET);
4794 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4795 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4799 if (cfg->arch.ss_tramp_var) {
4800 /* Initialize ss_tramp_var */
4801 ins = cfg->arch.ss_tramp_var;
4802 g_assert (ins->opcode == OP_REGOFFSET);
4804 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4805 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4808 if (cfg->arch.bp_tramp_var) {
4809 /* Initialize bp_tramp_var */
4810 ins = cfg->arch.bp_tramp_var;
4811 g_assert (ins->opcode == OP_REGOFFSET);
4813 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4814 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4819 if (cfg->opt & MONO_OPT_BRANCH) {
4820 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4822 bb->max_offset = max_offset;
4824 MONO_BB_FOR_EACH_INS (bb, ins) {
4825 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4829 if (max_offset > 0x3ffff * 4)
4830 cfg->arch.cond_branch_islands = TRUE;
4836 realloc_code (MonoCompile *cfg, int size)
4838 while (cfg->code_len + size > (cfg->code_size - 16)) {
4839 cfg->code_size *= 2;
4840 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4841 cfg->stat_code_reallocs++;
4843 return cfg->native_code + cfg->code_len;
4847 mono_arch_emit_epilog (MonoCompile *cfg)
4850 int max_epilog_size;
4854 max_epilog_size = 16 + 20*4;
4855 code = realloc_code (cfg, max_epilog_size);
4857 if (cfg->method->save_lmf) {
4858 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4861 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4864 /* Load returned vtypes into registers if needed */
4865 cinfo = cfg->arch.cinfo;
4866 switch (cinfo->ret.storage) {
4867 case ArgVtypeInIRegs: {
4868 MonoInst *ins = cfg->ret;
4870 for (i = 0; i < cinfo->ret.nregs; ++i)
4871 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4875 MonoInst *ins = cfg->ret;
4877 for (i = 0; i < cinfo->ret.nregs; ++i) {
4878 if (cinfo->ret.esize == 4)
4879 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4881 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4890 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4892 arm_retx (code, ARMREG_LR);
4894 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4896 cfg->code_len = code - cfg->native_code;
4900 mono_arch_emit_exceptions (MonoCompile *cfg)
4903 MonoClass *exc_class;
4905 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4906 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4907 int i, id, size = 0;
4909 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4910 exc_throw_pos [i] = NULL;
4911 exc_throw_found [i] = 0;
4914 for (ji = cfg->patch_info; ji; ji = ji->next) {
4915 if (ji->type == MONO_PATCH_INFO_EXC) {
4916 i = mini_exception_id_by_name (ji->data.target);
4917 if (!exc_throw_found [i]) {
4919 exc_throw_found [i] = TRUE;
4924 code = realloc_code (cfg, size);
4926 /* Emit code to raise corlib exceptions */
4927 for (ji = cfg->patch_info; ji; ji = ji->next) {
4928 if (ji->type != MONO_PATCH_INFO_EXC)
4931 ip = cfg->native_code + ji->ip.i;
4933 id = mini_exception_id_by_name (ji->data.target);
4935 if (exc_throw_pos [id]) {
4936 /* ip points to the bcc () in OP_COND_EXC_... */
4937 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4938 ji->type = MONO_PATCH_INFO_NONE;
4942 exc_throw_pos [id] = code;
4943 arm_patch_rel (ip, code, ji->relocation);
4945 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4947 /* r0 = type token */
4948 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4949 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4951 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4952 /* Branch to the corlib exception throwing trampoline */
4953 ji->ip.i = code - cfg->native_code;
4954 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4955 ji->data.name = "mono_arch_throw_corlib_exception";
4956 ji->relocation = MONO_R_ARM64_BL;
4958 cfg->thunk_area += THUNK_SIZE;
4961 cfg->code_len = code - cfg->native_code;
4963 g_assert (cfg->code_len < cfg->code_size);
4967 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4973 mono_arch_print_tree (MonoInst *tree, int arity)
4979 mono_arch_get_patch_offset (guint8 *code)
4985 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4986 gpointer fail_tramp)
4988 int i, buf_len, imt_reg;
4992 printf ("building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4993 for (i = 0; i < count; ++i) {
4994 MonoIMTCheckItem *item = imt_entries [i];
4995 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5000 for (i = 0; i < count; ++i) {
5001 MonoIMTCheckItem *item = imt_entries [i];
5002 if (item->is_equals) {
5003 gboolean fail_case = !item->check_target_idx && fail_tramp;
5005 if (item->check_target_idx || fail_case) {
5006 if (!item->compare_done || fail_case) {
5007 buf_len += 4 * 4 + 4;
5010 if (item->has_target_code) {
5027 buf = mono_method_alloc_generic_virtual_trampoline (domain, buf_len);
5029 buf = mono_domain_code_reserve (domain, buf_len);
5033 * We are called by JITted code, which passes in the IMT argument in
5034 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
5037 imt_reg = MONO_ARCH_RGCTX_REG;
5038 for (i = 0; i < count; ++i) {
5039 MonoIMTCheckItem *item = imt_entries [i];
5041 item->code_target = code;
5043 if (item->is_equals) {
5045 * Check the imt argument against item->key, if equals, jump to either
5046 * item->value.target_code or to vtable [item->value.vtable_slot].
5047 * If fail_tramp is set, jump to it if not-equals.
5049 gboolean fail_case = !item->check_target_idx && fail_tramp;
5051 if (item->check_target_idx || fail_case) {
5052 /* Compare imt_reg with item->key */
5053 if (!item->compare_done || fail_case) {
5054 // FIXME: Optimize this
5055 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5056 arm_cmpx (code, imt_reg, ARMREG_IP0);
5058 item->jmp_code = code;
5059 arm_bcc (code, ARMCOND_NE, 0);
5060 /* Jump to target if equals */
5061 if (item->has_target_code) {
5062 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
5063 arm_brx (code, ARMREG_IP0);
5065 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5067 code = emit_imm64 (code, ARMREG_IP0, imm);
5068 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5069 arm_brx (code, ARMREG_IP0);
5073 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5074 item->jmp_code = NULL;
5075 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5076 arm_brx (code, ARMREG_IP0);
5079 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5081 code = emit_imm64 (code, ARMREG_IP0, imm);
5082 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5083 arm_brx (code, ARMREG_IP0);
5086 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5087 arm_cmpx (code, imt_reg, ARMREG_IP0);
5088 item->jmp_code = code;
5089 arm_bcc (code, ARMCOND_HS, 0);
5092 /* Patch the branches */
5093 for (i = 0; i < count; ++i) {
5094 MonoIMTCheckItem *item = imt_entries [i];
5095 if (item->jmp_code && item->check_target_idx)
5096 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5099 g_assert ((code - buf) < buf_len);
5101 mono_arch_flush_icache (buf, code - buf);
5107 mono_arch_get_trampolines (gboolean aot)
5109 return mono_arm_get_exception_trampolines (aot);
5112 #else /* DISABLE_JIT */
5115 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5116 gpointer fail_tramp)
5118 g_assert_not_reached ();
5122 #endif /* !DISABLE_JIT */
5124 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5127 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5130 guint32 native_offset = ip - (guint8*)ji->code_start;
5133 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5135 g_assert (native_offset % 4 == 0);
5136 g_assert (info->bp_addrs [native_offset / 4] == 0);
5137 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5139 /* ip points to an ldrx */
5141 arm_blrx (code, ARMREG_IP0);
5142 mono_arch_flush_icache (ip, code - ip);
5147 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5152 guint32 native_offset = ip - (guint8*)ji->code_start;
5153 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5155 g_assert (native_offset % 4 == 0);
5156 info->bp_addrs [native_offset / 4] = NULL;
5158 /* ip points to an ldrx */
5161 mono_arch_flush_icache (ip, code - ip);
5166 mono_arch_start_single_stepping (void)
5168 ss_trampoline = mini_get_single_step_trampoline ();
5172 mono_arch_stop_single_stepping (void)
5174 ss_trampoline = NULL;
5178 mono_arch_is_single_step_event (void *info, void *sigctx)
5180 /* We use soft breakpoints on arm64 */
5185 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5187 /* We use soft breakpoints on arm64 */
5192 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5194 g_assert_not_reached ();
5198 mono_arch_skip_single_step (MonoContext *ctx)
5200 g_assert_not_reached ();
5204 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5209 // FIXME: Add a free function
5211 mono_domain_lock (domain);
5212 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5214 mono_domain_unlock (domain);
5217 ji = mono_jit_info_table_find (domain, (char*)code);
5220 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5222 info->ss_tramp_addr = &ss_trampoline;
5224 mono_domain_lock (domain);
5225 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5227 mono_domain_unlock (domain);
5234 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5236 ext->lmf.previous_lmf = prev_lmf;
5237 /* Mark that this is a MonoLMFExt */
5238 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5239 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5242 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5245 mono_arch_opcode_supported (int opcode)
5248 case OP_ATOMIC_ADD_I4:
5249 case OP_ATOMIC_ADD_I8:
5250 case OP_ATOMIC_EXCHANGE_I4:
5251 case OP_ATOMIC_EXCHANGE_I8:
5252 case OP_ATOMIC_CAS_I4:
5253 case OP_ATOMIC_CAS_I8:
5254 case OP_ATOMIC_LOAD_I1:
5255 case OP_ATOMIC_LOAD_I2:
5256 case OP_ATOMIC_LOAD_I4:
5257 case OP_ATOMIC_LOAD_I8:
5258 case OP_ATOMIC_LOAD_U1:
5259 case OP_ATOMIC_LOAD_U2:
5260 case OP_ATOMIC_LOAD_U4:
5261 case OP_ATOMIC_LOAD_U8:
5262 case OP_ATOMIC_LOAD_R4:
5263 case OP_ATOMIC_LOAD_R8:
5264 case OP_ATOMIC_STORE_I1:
5265 case OP_ATOMIC_STORE_I2:
5266 case OP_ATOMIC_STORE_I4:
5267 case OP_ATOMIC_STORE_I8:
5268 case OP_ATOMIC_STORE_U1:
5269 case OP_ATOMIC_STORE_U2:
5270 case OP_ATOMIC_STORE_U4:
5271 case OP_ATOMIC_STORE_U8:
5272 case OP_ATOMIC_STORE_R4:
5273 case OP_ATOMIC_STORE_R8:
5281 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5283 return get_call_info (mp, sig);
5287 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
5294 bp = MONO_CONTEXT_GET_BP (ctx);
5295 lr_loc = (gpointer*)(bp + clause->exvar_offset);
5297 old_value = *lr_loc;
5298 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
5301 *lr_loc = new_value;