3 * ARM64 backend for the Mono code generator
5 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
10 * Paolo Molaro (lupus@ximian.com)
11 * Dietmar Maurer (dietmar@ximian.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
20 #include "cpu-arm64.h"
23 #include <mono/arch/arm64/arm64-codegen.h>
24 #include <mono/utils/mono-mmap.h>
25 #include <mono/utils/mono-memory-model.h>
26 #include <mono/metadata/abi-details.h>
31 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
32 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
33 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
36 * - ip0/ip1/lr are used as temporary registers
37 * - r27 is used as the rgctx/imt register
38 * - r28 is used to access arguments passed on the stack
39 * - d15/d16 are used as fp temporary registers
42 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
44 #define FP_TEMP_REG ARMREG_D16
45 #define FP_TEMP_REG2 ARMREG_D17
47 #define THUNK_SIZE (4 * 4)
49 /* The single step trampoline */
50 static gpointer ss_trampoline;
52 /* The breakpoint trampoline */
53 static gpointer bp_trampoline;
55 static gboolean ios_abi;
57 static __attribute__ ((__warn_unused_result__)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
60 mono_arch_regname (int reg)
62 static const char * rnames[] = {
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
64 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
65 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
68 if (reg >= 0 && reg < 32)
74 mono_arch_fregname (int reg)
76 static const char * rnames[] = {
77 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
78 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
79 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
82 if (reg >= 0 && reg < 32)
88 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
94 #define MAX_ARCH_DELEGATE_PARAMS 7
97 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
102 start = code = mono_global_codeman_reserve (12);
104 /* Replace the this argument with the target */
105 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
106 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
107 arm_brx (code, ARMREG_IP0);
109 g_assert ((code - start) <= 12);
111 mono_arch_flush_icache (start, 12);
115 size = 8 + param_count * 4;
116 start = code = mono_global_codeman_reserve (size);
118 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
119 /* slide down the arguments */
120 for (i = 0; i < param_count; ++i)
121 arm_movx (code, i, i + 1);
122 arm_brx (code, ARMREG_IP0);
124 g_assert ((code - start) <= size);
126 mono_arch_flush_icache (start, size);
130 *code_size = code - start;
136 * mono_arch_get_delegate_invoke_impls:
138 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
142 mono_arch_get_delegate_invoke_impls (void)
150 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
151 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
153 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
154 code = get_delegate_invoke_impl (FALSE, i, &code_len);
155 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
156 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
164 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
166 guint8 *code, *start;
169 * vtypes are returned in registers, or using the dedicated r8 register, so
170 * they can be supported by delegate invokes.
174 static guint8* cached = NULL;
180 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
182 start = get_delegate_invoke_impl (TRUE, 0, NULL);
183 mono_memory_barrier ();
187 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
190 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
192 for (i = 0; i < sig->param_count; ++i)
193 if (!mono_is_regsize_var (sig->params [i]))
196 code = cache [sig->param_count];
201 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
202 start = mono_aot_get_trampoline (name);
205 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
207 mono_memory_barrier ();
208 cache [sig->param_count] = start;
216 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
222 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
224 return (gpointer)regs [ARMREG_R0];
228 mono_arch_cpu_init (void)
233 mono_arch_init (void)
235 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
236 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
237 mono_aot_register_jit_icall ("mono_arm_handler_block_trampoline_helper", mono_arm_handler_block_trampoline_helper);
240 bp_trampoline = mini_get_breakpoint_trampoline ();
242 mono_arm_gsharedvt_init ();
244 #if defined(TARGET_IOS)
250 mono_arch_cleanup (void)
255 mono_arch_cpu_optimizations (guint32 *exclude_mask)
262 mono_arch_cpu_enumerate_simd_versions (void)
268 mono_arch_register_lowlevel_calls (void)
273 mono_arch_finish_init (void)
277 /* The maximum length is 2 instructions */
279 emit_imm (guint8 *code, int dreg, int imm)
281 // FIXME: Optimize this
284 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
285 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
287 arm_movzx (code, dreg, imm & 0xffff, 0);
289 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
295 /* The maximum length is 4 instructions */
297 emit_imm64 (guint8 *code, int dreg, guint64 imm)
299 // FIXME: Optimize this
300 arm_movzx (code, dreg, imm & 0xffff, 0);
301 if ((imm >> 16) & 0xffff)
302 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
303 if ((imm >> 32) & 0xffff)
304 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
305 if ((imm >> 48) & 0xffff)
306 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
312 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
314 return emit_imm64 (code, dreg, imm);
320 * Emit a patchable code sequence for constructing a 64 bit immediate.
323 emit_imm64_template (guint8 *code, int dreg)
325 arm_movzx (code, dreg, 0, 0);
326 arm_movkx (code, dreg, 0, 16);
327 arm_movkx (code, dreg, 0, 32);
328 arm_movkx (code, dreg, 0, 48);
333 static inline __attribute__ ((__warn_unused_result__)) guint8*
334 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
336 if (!arm_is_arith_imm (imm)) {
337 code = emit_imm (code, ARMREG_LR, imm);
338 arm_addw (code, dreg, sreg, ARMREG_LR);
340 arm_addw_imm (code, dreg, sreg, imm);
345 static inline __attribute__ ((__warn_unused_result__)) guint8*
346 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
348 if (!arm_is_arith_imm (imm)) {
349 code = emit_imm (code, ARMREG_LR, imm);
350 arm_addx (code, dreg, sreg, ARMREG_LR);
352 arm_addx_imm (code, dreg, sreg, imm);
357 static inline __attribute__ ((__warn_unused_result__)) guint8*
358 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
360 if (!arm_is_arith_imm (imm)) {
361 code = emit_imm (code, ARMREG_LR, imm);
362 arm_subw (code, dreg, sreg, ARMREG_LR);
364 arm_subw_imm (code, dreg, sreg, imm);
369 static inline __attribute__ ((__warn_unused_result__)) guint8*
370 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
372 if (!arm_is_arith_imm (imm)) {
373 code = emit_imm (code, ARMREG_LR, imm);
374 arm_subx (code, dreg, sreg, ARMREG_LR);
376 arm_subx_imm (code, dreg, sreg, imm);
381 /* Emit sp+=imm. Clobbers ip0/ip1 */
382 static inline __attribute__ ((__warn_unused_result__)) guint8*
383 emit_addx_sp_imm (guint8 *code, int imm)
385 code = emit_imm (code, ARMREG_IP0, imm);
386 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
387 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
388 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
392 /* Emit sp-=imm. Clobbers ip0/ip1 */
393 static inline __attribute__ ((__warn_unused_result__)) guint8*
394 emit_subx_sp_imm (guint8 *code, int imm)
396 code = emit_imm (code, ARMREG_IP0, imm);
397 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
398 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
399 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
403 static inline __attribute__ ((__warn_unused_result__)) guint8*
404 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
407 code = emit_imm (code, ARMREG_LR, imm);
408 arm_andw (code, dreg, sreg, ARMREG_LR);
413 static inline __attribute__ ((__warn_unused_result__)) guint8*
414 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
417 code = emit_imm (code, ARMREG_LR, imm);
418 arm_andx (code, dreg, sreg, ARMREG_LR);
423 static inline __attribute__ ((__warn_unused_result__)) guint8*
424 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
427 code = emit_imm (code, ARMREG_LR, imm);
428 arm_orrw (code, dreg, sreg, ARMREG_LR);
433 static inline __attribute__ ((__warn_unused_result__)) guint8*
434 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
437 code = emit_imm (code, ARMREG_LR, imm);
438 arm_orrx (code, dreg, sreg, ARMREG_LR);
443 static inline __attribute__ ((__warn_unused_result__)) guint8*
444 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
447 code = emit_imm (code, ARMREG_LR, imm);
448 arm_eorw (code, dreg, sreg, ARMREG_LR);
453 static inline __attribute__ ((__warn_unused_result__)) guint8*
454 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
457 code = emit_imm (code, ARMREG_LR, imm);
458 arm_eorx (code, dreg, sreg, ARMREG_LR);
463 static inline __attribute__ ((__warn_unused_result__)) guint8*
464 emit_cmpw_imm (guint8 *code, int sreg, int imm)
467 arm_cmpw (code, sreg, ARMREG_RZR);
470 code = emit_imm (code, ARMREG_LR, imm);
471 arm_cmpw (code, sreg, ARMREG_LR);
477 static inline __attribute__ ((__warn_unused_result__)) guint8*
478 emit_cmpx_imm (guint8 *code, int sreg, int imm)
481 arm_cmpx (code, sreg, ARMREG_RZR);
484 code = emit_imm (code, ARMREG_LR, imm);
485 arm_cmpx (code, sreg, ARMREG_LR);
491 static inline __attribute__ ((__warn_unused_result__)) guint8*
492 emit_strb (guint8 *code, int rt, int rn, int imm)
494 if (arm_is_strb_imm (imm)) {
495 arm_strb (code, rt, rn, imm);
497 g_assert (rt != ARMREG_IP0);
498 g_assert (rn != ARMREG_IP0);
499 code = emit_imm (code, ARMREG_IP0, imm);
500 arm_strb_reg (code, rt, rn, ARMREG_IP0);
505 static inline __attribute__ ((__warn_unused_result__)) guint8*
506 emit_strh (guint8 *code, int rt, int rn, int imm)
508 if (arm_is_strh_imm (imm)) {
509 arm_strh (code, rt, rn, imm);
511 g_assert (rt != ARMREG_IP0);
512 g_assert (rn != ARMREG_IP0);
513 code = emit_imm (code, ARMREG_IP0, imm);
514 arm_strh_reg (code, rt, rn, ARMREG_IP0);
519 static inline __attribute__ ((__warn_unused_result__)) guint8*
520 emit_strw (guint8 *code, int rt, int rn, int imm)
522 if (arm_is_strw_imm (imm)) {
523 arm_strw (code, rt, rn, imm);
525 g_assert (rt != ARMREG_IP0);
526 g_assert (rn != ARMREG_IP0);
527 code = emit_imm (code, ARMREG_IP0, imm);
528 arm_strw_reg (code, rt, rn, ARMREG_IP0);
533 static inline __attribute__ ((__warn_unused_result__)) guint8*
534 emit_strfpw (guint8 *code, int rt, int rn, int imm)
536 if (arm_is_strw_imm (imm)) {
537 arm_strfpw (code, rt, rn, imm);
539 g_assert (rn != ARMREG_IP0);
540 code = emit_imm (code, ARMREG_IP0, imm);
541 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
542 arm_strfpw (code, rt, ARMREG_IP0, 0);
547 static inline __attribute__ ((__warn_unused_result__)) guint8*
548 emit_strfpx (guint8 *code, int rt, int rn, int imm)
550 if (arm_is_strx_imm (imm)) {
551 arm_strfpx (code, rt, rn, imm);
553 g_assert (rn != ARMREG_IP0);
554 code = emit_imm (code, ARMREG_IP0, imm);
555 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
556 arm_strfpx (code, rt, ARMREG_IP0, 0);
561 static inline __attribute__ ((__warn_unused_result__)) guint8*
562 emit_strx (guint8 *code, int rt, int rn, int imm)
564 if (arm_is_strx_imm (imm)) {
565 arm_strx (code, rt, rn, imm);
567 g_assert (rt != ARMREG_IP0);
568 g_assert (rn != ARMREG_IP0);
569 code = emit_imm (code, ARMREG_IP0, imm);
570 arm_strx_reg (code, rt, rn, ARMREG_IP0);
575 static inline __attribute__ ((__warn_unused_result__)) guint8*
576 emit_ldrb (guint8 *code, int rt, int rn, int imm)
578 if (arm_is_pimm12_scaled (imm, 1)) {
579 arm_ldrb (code, rt, rn, imm);
581 g_assert (rt != ARMREG_IP0);
582 g_assert (rn != ARMREG_IP0);
583 code = emit_imm (code, ARMREG_IP0, imm);
584 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
589 static inline __attribute__ ((__warn_unused_result__)) guint8*
590 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
592 if (arm_is_pimm12_scaled (imm, 1)) {
593 arm_ldrsbx (code, rt, rn, imm);
595 g_assert (rt != ARMREG_IP0);
596 g_assert (rn != ARMREG_IP0);
597 code = emit_imm (code, ARMREG_IP0, imm);
598 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
603 static inline __attribute__ ((__warn_unused_result__)) guint8*
604 emit_ldrh (guint8 *code, int rt, int rn, int imm)
606 if (arm_is_pimm12_scaled (imm, 2)) {
607 arm_ldrh (code, rt, rn, imm);
609 g_assert (rt != ARMREG_IP0);
610 g_assert (rn != ARMREG_IP0);
611 code = emit_imm (code, ARMREG_IP0, imm);
612 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
617 static inline __attribute__ ((__warn_unused_result__)) guint8*
618 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
620 if (arm_is_pimm12_scaled (imm, 2)) {
621 arm_ldrshx (code, rt, rn, imm);
623 g_assert (rt != ARMREG_IP0);
624 g_assert (rn != ARMREG_IP0);
625 code = emit_imm (code, ARMREG_IP0, imm);
626 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
631 static inline __attribute__ ((__warn_unused_result__)) guint8*
632 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
634 if (arm_is_pimm12_scaled (imm, 4)) {
635 arm_ldrswx (code, rt, rn, imm);
637 g_assert (rt != ARMREG_IP0);
638 g_assert (rn != ARMREG_IP0);
639 code = emit_imm (code, ARMREG_IP0, imm);
640 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
645 static inline __attribute__ ((__warn_unused_result__)) guint8*
646 emit_ldrw (guint8 *code, int rt, int rn, int imm)
648 if (arm_is_pimm12_scaled (imm, 4)) {
649 arm_ldrw (code, rt, rn, imm);
651 g_assert (rn != ARMREG_IP0);
652 code = emit_imm (code, ARMREG_IP0, imm);
653 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
658 static inline __attribute__ ((__warn_unused_result__)) guint8*
659 emit_ldrx (guint8 *code, int rt, int rn, int imm)
661 if (arm_is_pimm12_scaled (imm, 8)) {
662 arm_ldrx (code, rt, rn, imm);
664 g_assert (rn != ARMREG_IP0);
665 code = emit_imm (code, ARMREG_IP0, imm);
666 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
671 static inline __attribute__ ((__warn_unused_result__)) guint8*
672 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
674 if (arm_is_pimm12_scaled (imm, 4)) {
675 arm_ldrfpw (code, rt, rn, imm);
677 g_assert (rn != ARMREG_IP0);
678 code = emit_imm (code, ARMREG_IP0, imm);
679 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
680 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
685 static inline __attribute__ ((__warn_unused_result__)) guint8*
686 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
688 if (arm_is_pimm12_scaled (imm, 8)) {
689 arm_ldrfpx (code, rt, rn, imm);
691 g_assert (rn != ARMREG_IP0);
692 code = emit_imm (code, ARMREG_IP0, imm);
693 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
694 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
700 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
702 return emit_ldrx (code, rt, rn, imm);
706 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
709 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
710 code = emit_imm64_template (code, ARMREG_LR);
711 arm_blrx (code, ARMREG_LR);
713 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
715 cfg->thunk_area += THUNK_SIZE;
720 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
723 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
725 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
726 /* See arch_emit_got_access () in aot-compiler.c */
727 arm_ldrx_lit (code, dreg, 0);
734 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
736 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
740 * mono_arm_emit_aotconst:
742 * Emit code to load an AOT constant into DREG. Usable from trampolines.
745 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
747 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
751 mono_arch_have_fast_tls (void)
761 emit_tls_get (guint8 *code, int dreg, int tls_offset)
763 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
764 if (tls_offset < 256) {
765 arm_ldrx (code, dreg, dreg, tls_offset);
767 code = emit_addx_imm (code, dreg, dreg, tls_offset);
768 arm_ldrx (code, dreg, dreg, 0);
774 emit_tls_set (guint8 *code, int sreg, int tls_offset)
776 int tmpreg = ARMREG_IP0;
778 g_assert (sreg != tmpreg);
779 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
780 if (tls_offset < 256) {
781 arm_strx (code, sreg, tmpreg, tls_offset);
783 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
784 arm_strx (code, sreg, tmpreg, 0);
792 * - ldrp [fp, lr], [sp], !stack_offfset
793 * Clobbers TEMP_REGS.
795 __attribute__ ((__warn_unused_result__)) guint8*
796 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
798 arm_movspx (code, ARMREG_SP, ARMREG_FP);
800 if (arm_is_ldpx_imm (stack_offset)) {
801 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
803 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
804 /* sp += stack_offset */
805 g_assert (temp_regs & (1 << ARMREG_IP0));
806 if (temp_regs & (1 << ARMREG_IP1)) {
807 code = emit_addx_sp_imm (code, stack_offset);
809 int imm = stack_offset;
811 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
812 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
814 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
817 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
823 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
826 emit_thunk (guint8 *code, gconstpointer target)
830 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
831 arm_brx (code, ARMREG_IP0);
832 *(guint64*)code = (guint64)target;
833 code += sizeof (guint64);
835 mono_arch_flush_icache (p, code - p);
840 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
843 MonoThunkJitInfo *info;
847 guint8 *target_thunk;
850 domain = mono_domain_get ();
854 * This can be called multiple times during JITting,
855 * save the current position in cfg->arch to avoid
856 * doing a O(n^2) search.
858 if (!cfg->arch.thunks) {
859 cfg->arch.thunks = cfg->thunks;
860 cfg->arch.thunks_size = cfg->thunk_area;
862 thunks = cfg->arch.thunks;
863 thunks_size = cfg->arch.thunks_size;
865 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
866 g_assert_not_reached ();
869 g_assert (*(guint32*)thunks == 0);
870 emit_thunk (thunks, target);
872 cfg->arch.thunks += THUNK_SIZE;
873 cfg->arch.thunks_size -= THUNK_SIZE;
877 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
879 info = mono_jit_info_get_thunk_info (ji);
882 thunks = (guint8*)ji->code_start + info->thunks_offset;
883 thunks_size = info->thunks_size;
885 orig_target = mono_arch_get_call_target (code + 4);
887 mono_domain_lock (domain);
890 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
891 /* The call already points to a thunk, because of trampolines etc. */
892 target_thunk = orig_target;
894 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
895 if (((guint32*)p) [0] == 0) {
899 } else if (((guint64*)p) [1] == (guint64)target) {
900 /* Thunk already points to target */
907 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
910 mono_domain_unlock (domain);
911 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
912 g_assert_not_reached ();
915 emit_thunk (target_thunk, target);
917 mono_domain_unlock (domain);
924 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
926 switch (relocation) {
928 if (arm_is_bl_disp (code, target)) {
929 arm_b (code, target);
933 thunk = create_thunk (cfg, domain, code, target);
934 g_assert (arm_is_bl_disp (code, thunk));
938 case MONO_R_ARM64_BCC: {
941 cond = arm_get_bcc_cond (code);
942 arm_bcc (code, cond, target);
945 case MONO_R_ARM64_CBZ:
946 arm_set_cbz_target (code, target);
948 case MONO_R_ARM64_IMM: {
949 guint64 imm = (guint64)target;
952 /* emit_imm64_template () */
953 dreg = arm_get_movzx_rd (code);
954 arm_movzx (code, dreg, imm & 0xffff, 0);
955 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
956 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
957 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
960 case MONO_R_ARM64_BL:
961 if (arm_is_bl_disp (code, target)) {
962 arm_bl (code, target);
966 thunk = create_thunk (cfg, domain, code, target);
967 g_assert (arm_is_bl_disp (code, thunk));
968 arm_bl (code, thunk);
972 g_assert_not_reached ();
977 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
979 arm_patch_full (NULL, NULL, code, target, relocation);
983 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
985 arm_patch_rel (code, target, relocation);
989 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
993 ip = ji->ip.i + code;
996 case MONO_PATCH_INFO_METHOD_JUMP:
997 /* ji->relocation is not set by the caller */
998 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1001 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1007 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1012 mono_arch_flush_register_windows (void)
1017 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1019 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1023 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1025 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1029 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1031 return ctx->regs [reg];
1035 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1037 ctx->regs [reg] = val;
1041 * mono_arch_set_target:
1043 * Set the target architecture the JIT backend should generate code for, in the form
1044 * of a GNU target triplet. Only used in AOT mode.
1047 mono_arch_set_target (char *mtriple)
1049 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1055 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1057 if (cinfo->gr >= PARAM_REGS) {
1058 ainfo->storage = ArgOnStack;
1060 /* Assume size == align */
1061 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1062 ainfo->offset = cinfo->stack_usage;
1063 ainfo->slot_size = size;
1065 cinfo->stack_usage += size;
1067 ainfo->offset = cinfo->stack_usage;
1068 ainfo->slot_size = 8;
1069 ainfo->sign = FALSE;
1070 /* Put arguments into 8 byte aligned stack slots */
1071 cinfo->stack_usage += 8;
1074 ainfo->storage = ArgInIReg;
1075 ainfo->reg = cinfo->gr;
1081 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1083 int size = single ? 4 : 8;
1085 if (cinfo->fr >= FP_PARAM_REGS) {
1086 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1088 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1089 ainfo->offset = cinfo->stack_usage;
1090 ainfo->slot_size = size;
1091 cinfo->stack_usage += size;
1093 ainfo->offset = cinfo->stack_usage;
1094 ainfo->slot_size = 8;
1095 /* Put arguments into 8 byte aligned stack slots */
1096 cinfo->stack_usage += 8;
1100 ainfo->storage = ArgInFRegR4;
1102 ainfo->storage = ArgInFReg;
1103 ainfo->reg = cinfo->fr;
1109 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1113 MonoClassField *field;
1114 MonoType *ftype, *prev_ftype = NULL;
1117 klass = mono_class_from_mono_type (t);
1119 while ((field = mono_class_get_fields (klass, &iter))) {
1120 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1122 ftype = mono_field_get_type (field);
1123 ftype = mini_get_underlying_type (ftype);
1125 if (MONO_TYPE_ISSTRUCT (ftype)) {
1126 int nested_nfields, nested_esize;
1127 int nested_field_offsets [16];
1129 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1131 if (nested_esize == 4)
1132 ftype = &mono_defaults.single_class->byval_arg;
1134 ftype = &mono_defaults.double_class->byval_arg;
1135 if (prev_ftype && prev_ftype->type != ftype->type)
1138 for (i = 0; i < nested_nfields; ++i) {
1139 if (nfields + i < 4)
1140 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1142 nfields += nested_nfields;
1144 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1146 if (prev_ftype && prev_ftype->type != ftype->type)
1150 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1154 if (nfields == 0 || nfields > 4)
1156 *out_nfields = nfields;
1157 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1162 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1164 int i, size, align_size, nregs, nfields, esize;
1165 int field_offsets [16];
1168 size = mini_type_stack_size_full (t, &align, cinfo->pinvoke);
1169 align_size = ALIGN_TO (size, 8);
1171 nregs = align_size / 8;
1172 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1174 * The struct might include nested float structs aligned at 8,
1175 * so need to keep track of the offsets of the individual fields.
1177 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1178 ainfo->storage = ArgHFA;
1179 ainfo->reg = cinfo->fr;
1180 ainfo->nregs = nfields;
1182 ainfo->esize = esize;
1183 for (i = 0; i < nfields; ++i)
1184 ainfo->foffsets [i] = field_offsets [i];
1185 cinfo->fr += ainfo->nregs;
1187 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1188 cinfo->fr = FP_PARAM_REGS;
1189 size = ALIGN_TO (size, 8);
1190 ainfo->storage = ArgVtypeOnStack;
1191 ainfo->offset = cinfo->stack_usage;
1194 ainfo->nregs = nfields;
1195 ainfo->esize = esize;
1196 cinfo->stack_usage += size;
1201 if (align_size > 16) {
1202 ainfo->storage = ArgVtypeByRef;
1207 if (cinfo->gr + nregs > PARAM_REGS) {
1208 size = ALIGN_TO (size, 8);
1209 ainfo->storage = ArgVtypeOnStack;
1210 ainfo->offset = cinfo->stack_usage;
1212 cinfo->stack_usage += size;
1213 cinfo->gr = PARAM_REGS;
1215 ainfo->storage = ArgVtypeInIRegs;
1216 ainfo->reg = cinfo->gr;
1217 ainfo->nregs = nregs;
1224 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1228 ptype = mini_get_underlying_type (t);
1229 switch (ptype->type) {
1231 add_general (cinfo, ainfo, 1, TRUE);
1233 case MONO_TYPE_BOOLEAN:
1235 add_general (cinfo, ainfo, 1, FALSE);
1238 add_general (cinfo, ainfo, 2, TRUE);
1241 case MONO_TYPE_CHAR:
1242 add_general (cinfo, ainfo, 2, FALSE);
1245 add_general (cinfo, ainfo, 4, TRUE);
1248 add_general (cinfo, ainfo, 4, FALSE);
1253 case MONO_TYPE_FNPTR:
1254 case MONO_TYPE_CLASS:
1255 case MONO_TYPE_OBJECT:
1256 case MONO_TYPE_SZARRAY:
1257 case MONO_TYPE_ARRAY:
1258 case MONO_TYPE_STRING:
1261 add_general (cinfo, ainfo, 8, FALSE);
1264 add_fp (cinfo, ainfo, FALSE);
1267 add_fp (cinfo, ainfo, TRUE);
1269 case MONO_TYPE_VALUETYPE:
1270 case MONO_TYPE_TYPEDBYREF:
1271 add_valuetype (cinfo, ainfo, ptype);
1273 case MONO_TYPE_VOID:
1274 ainfo->storage = ArgNone;
1276 case MONO_TYPE_GENERICINST:
1277 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1278 add_general (cinfo, ainfo, 8, FALSE);
1279 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1281 * Treat gsharedvt arguments as large vtypes
1283 ainfo->storage = ArgVtypeByRef;
1284 ainfo->gsharedvt = TRUE;
1286 add_valuetype (cinfo, ainfo, ptype);
1290 case MONO_TYPE_MVAR:
1291 g_assert (mini_is_gsharedvt_type (ptype));
1292 ainfo->storage = ArgVtypeByRef;
1293 ainfo->gsharedvt = TRUE;
1296 g_assert_not_reached ();
1304 * Obtain information about a call according to the calling convention.
1307 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1311 int n, pstart, pindex;
1313 n = sig->hasthis + sig->param_count;
1316 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1318 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1321 cinfo->pinvoke = sig->pinvoke;
1324 add_param (cinfo, &cinfo->ret, sig->ret);
1325 if (cinfo->ret.storage == ArgVtypeByRef)
1326 cinfo->ret.reg = ARMREG_R8;
1330 cinfo->stack_usage = 0;
1334 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1336 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1337 ainfo = cinfo->args + sig->hasthis + pindex;
1339 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1340 /* Prevent implicit arguments and sig_cookie from
1341 being passed in registers */
1342 cinfo->gr = PARAM_REGS;
1343 cinfo->fr = FP_PARAM_REGS;
1344 /* Emit the signature cookie just before the implicit arguments */
1345 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1348 add_param (cinfo, ainfo, sig->params [pindex]);
1349 if (ainfo->storage == ArgVtypeByRef) {
1350 /* Pass the argument address in the next register */
1351 if (cinfo->gr >= PARAM_REGS) {
1352 ainfo->storage = ArgVtypeByRefOnStack;
1353 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, 8);
1354 ainfo->offset = cinfo->stack_usage;
1355 cinfo->stack_usage += 8;
1357 ainfo->reg = cinfo->gr;
1363 /* Handle the case where there are no implicit arguments */
1364 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1365 /* Prevent implicit arguments and sig_cookie from
1366 being passed in registers */
1367 cinfo->gr = PARAM_REGS;
1368 cinfo->fr = FP_PARAM_REGS;
1369 /* Emit the signature cookie just before the implicit arguments */
1370 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1373 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1379 MonoMethodSignature *sig;
1382 MonoType **param_types;
1383 int n_fpargs, n_fpret;
1387 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1391 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1394 // FIXME: Add more cases
1395 switch (cinfo->ret.storage) {
1402 case ArgVtypeInIRegs:
1403 if (cinfo->ret.nregs > 2)
1412 for (i = 0; i < cinfo->nargs; ++i) {
1413 ArgInfo *ainfo = &cinfo->args [i];
1415 switch (ainfo->storage) {
1417 case ArgVtypeInIRegs:
1424 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1436 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1438 ArchDynCallInfo *info;
1442 cinfo = get_call_info (NULL, sig);
1444 if (!dyn_call_supported (cinfo, sig)) {
1449 info = g_new0 (ArchDynCallInfo, 1);
1450 // FIXME: Preprocess the info to speed up start_dyn_call ()
1452 info->cinfo = cinfo;
1453 info->rtype = mini_get_underlying_type (sig->ret);
1454 info->param_types = g_new0 (MonoType*, sig->param_count);
1455 for (i = 0; i < sig->param_count; ++i)
1456 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1458 switch (cinfo->ret.storage) {
1464 info->n_fpret = cinfo->ret.nregs;
1470 return (MonoDynCallInfo*)info;
1474 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1476 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1478 g_free (ainfo->cinfo);
1479 g_free (ainfo->param_types);
1484 bitcast_r4_to_r8 (float f)
1492 bitcast_r8_to_r4 (double f)
1500 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1502 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1503 DynCallArgs *p = (DynCallArgs*)buf;
1504 int aindex, arg_index, greg, i, pindex;
1505 MonoMethodSignature *sig = dinfo->sig;
1506 CallInfo *cinfo = dinfo->cinfo;
1507 int buffer_offset = 0;
1509 g_assert (buf_len >= sizeof (DynCallArgs));
1513 p->n_fpargs = dinfo->n_fpargs;
1514 p->n_fpret = dinfo->n_fpret;
1521 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1523 if (cinfo->ret.storage == ArgVtypeByRef)
1524 p->regs [ARMREG_R8] = (mgreg_t)ret;
1526 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1527 MonoType *t = dinfo->param_types [aindex];
1528 gpointer *arg = args [arg_index ++];
1529 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1532 if (ainfo->storage == ArgOnStack) {
1533 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1539 p->regs [slot] = (mgreg_t)*arg;
1543 if (ios_abi && ainfo->storage == ArgOnStack) {
1544 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1545 gboolean handled = TRUE;
1547 /* Special case arguments smaller than 1 machine word */
1549 case MONO_TYPE_BOOLEAN:
1551 *(guint8*)stack_arg = *(guint8*)arg;
1554 *(gint8*)stack_arg = *(gint8*)arg;
1557 case MONO_TYPE_CHAR:
1558 *(guint16*)stack_arg = *(guint16*)arg;
1561 *(gint16*)stack_arg = *(gint16*)arg;
1564 *(gint32*)stack_arg = *(gint32*)arg;
1567 *(guint32*)stack_arg = *(guint32*)arg;
1578 case MONO_TYPE_STRING:
1579 case MONO_TYPE_CLASS:
1580 case MONO_TYPE_ARRAY:
1581 case MONO_TYPE_SZARRAY:
1582 case MONO_TYPE_OBJECT:
1588 p->regs [slot] = (mgreg_t)*arg;
1590 case MONO_TYPE_BOOLEAN:
1592 p->regs [slot] = *(guint8*)arg;
1595 p->regs [slot] = *(gint8*)arg;
1598 p->regs [slot] = *(gint16*)arg;
1601 case MONO_TYPE_CHAR:
1602 p->regs [slot] = *(guint16*)arg;
1605 p->regs [slot] = *(gint32*)arg;
1608 p->regs [slot] = *(guint32*)arg;
1611 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1615 p->fpregs [ainfo->reg] = *(double*)arg;
1618 case MONO_TYPE_GENERICINST:
1619 if (MONO_TYPE_IS_REFERENCE (t)) {
1620 p->regs [slot] = (mgreg_t)*arg;
1623 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1624 MonoClass *klass = mono_class_from_mono_type (t);
1625 guint8 *nullable_buf;
1629 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1630 * if the nullable param is passed by ref.
1632 size = mono_class_value_size (klass, NULL);
1633 nullable_buf = p->buffer + buffer_offset;
1634 buffer_offset += size;
1635 g_assert (buffer_offset <= 256);
1637 /* The argument pointed to by arg is either a boxed vtype or null */
1638 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1640 arg = (gpointer*)nullable_buf;
1646 case MONO_TYPE_VALUETYPE:
1647 switch (ainfo->storage) {
1648 case ArgVtypeInIRegs:
1649 for (i = 0; i < ainfo->nregs; ++i)
1650 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1653 if (ainfo->esize == 4) {
1654 for (i = 0; i < ainfo->nregs; ++i)
1655 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1657 for (i = 0; i < ainfo->nregs; ++i)
1658 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1660 p->n_fpargs += ainfo->nregs;
1663 p->regs [slot] = (mgreg_t)arg;
1666 g_assert_not_reached ();
1671 g_assert_not_reached ();
1677 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1679 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1680 CallInfo *cinfo = ainfo->cinfo;
1681 DynCallArgs *args = (DynCallArgs*)buf;
1682 MonoType *ptype = ainfo->rtype;
1683 guint8 *ret = args->ret;
1684 mgreg_t res = args->res;
1685 mgreg_t res2 = args->res2;
1688 if (cinfo->ret.storage == ArgVtypeByRef)
1691 switch (ptype->type) {
1692 case MONO_TYPE_VOID:
1693 *(gpointer*)ret = NULL;
1695 case MONO_TYPE_STRING:
1696 case MONO_TYPE_CLASS:
1697 case MONO_TYPE_ARRAY:
1698 case MONO_TYPE_SZARRAY:
1699 case MONO_TYPE_OBJECT:
1703 *(gpointer*)ret = (gpointer)res;
1709 case MONO_TYPE_BOOLEAN:
1710 *(guint8*)ret = res;
1713 *(gint16*)ret = res;
1716 case MONO_TYPE_CHAR:
1717 *(guint16*)ret = res;
1720 *(gint32*)ret = res;
1723 *(guint32*)ret = res;
1727 *(guint64*)ret = res;
1730 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1733 *(double*)ret = args->fpregs [0];
1735 case MONO_TYPE_GENERICINST:
1736 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1737 *(gpointer*)ret = (gpointer)res;
1742 case MONO_TYPE_VALUETYPE:
1743 switch (ainfo->cinfo->ret.storage) {
1744 case ArgVtypeInIRegs:
1745 *(mgreg_t*)ret = res;
1746 if (ainfo->cinfo->ret.nregs > 1)
1747 ((mgreg_t*)ret) [1] = res2;
1750 /* Use the same area for returning fp values */
1751 if (cinfo->ret.esize == 4) {
1752 for (i = 0; i < cinfo->ret.nregs; ++i)
1753 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1755 for (i = 0; i < cinfo->ret.nregs; ++i)
1756 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1760 g_assert_not_reached ();
1765 g_assert_not_reached ();
1770 void sys_icache_invalidate (void *start, size_t len);
1774 mono_arch_flush_icache (guint8 *code, gint size)
1776 #ifndef MONO_CROSS_COMPILE
1778 sys_icache_invalidate (code, size);
1780 /* Don't rely on GCC's __clear_cache implementation, as it caches
1781 * icache/dcache cache line sizes, that can vary between cores on
1782 * big.LITTLE architectures. */
1783 guint64 end = (guint64) (code + size);
1785 /* always go with cacheline size of 4 bytes as this code isn't perf critical
1786 * anyway. Reading the cache line size from a machine register can be racy
1787 * on a big.LITTLE architecture if the cores don't have the same cache line
1789 const size_t icache_line_size = 4;
1790 const size_t dcache_line_size = 4;
1792 addr = (guint64) code & ~(guint64) (dcache_line_size - 1);
1793 for (; addr < end; addr += dcache_line_size)
1794 asm volatile("dc civac, %0" : : "r" (addr) : "memory");
1795 asm volatile("dsb ish" : : : "memory");
1797 addr = (guint64) code & ~(guint64) (icache_line_size - 1);
1798 for (; addr < end; addr += icache_line_size)
1799 asm volatile("ic ivau, %0" : : "r" (addr) : "memory");
1801 asm volatile ("dsb ish" : : : "memory");
1802 asm volatile ("isb" : : : "memory");
1810 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1817 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1822 for (i = 0; i < cfg->num_varinfo; i++) {
1823 MonoInst *ins = cfg->varinfo [i];
1824 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1827 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1830 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1831 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1834 if (mono_is_regsize_var (ins->inst_vtype)) {
1835 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1836 g_assert (i == vmv->idx);
1837 vars = g_list_prepend (vars, vmv);
1841 vars = mono_varlist_sort (cfg, vars, 0);
1847 mono_arch_get_global_int_regs (MonoCompile *cfg)
1852 /* r28 is reserved for cfg->arch.args_reg */
1853 /* r27 is reserved for the imt argument */
1854 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1855 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1861 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1863 MonoInst *ins = cfg->varinfo [vmv->idx];
1865 if (ins->opcode == OP_ARG)
1872 mono_arch_create_vars (MonoCompile *cfg)
1874 MonoMethodSignature *sig;
1877 sig = mono_method_signature (cfg->method);
1878 if (!cfg->arch.cinfo)
1879 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1880 cinfo = cfg->arch.cinfo;
1882 if (cinfo->ret.storage == ArgVtypeByRef) {
1883 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1884 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1887 if (cfg->gen_sdb_seq_points) {
1890 if (cfg->compile_aot) {
1891 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1892 ins->flags |= MONO_INST_VOLATILE;
1893 cfg->arch.seq_point_info_var = ins;
1896 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1897 ins->flags |= MONO_INST_VOLATILE;
1898 cfg->arch.ss_tramp_var = ins;
1900 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1901 ins->flags |= MONO_INST_VOLATILE;
1902 cfg->arch.bp_tramp_var = ins;
1905 if (cfg->method->save_lmf) {
1906 cfg->create_lmf_var = TRUE;
1912 mono_arch_allocate_vars (MonoCompile *cfg)
1914 MonoMethodSignature *sig;
1918 int i, offset, size, align;
1919 guint32 locals_stack_size, locals_stack_align;
1923 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1924 * Compute cfg->stack_offset and update cfg->used_int_regs.
1927 sig = mono_method_signature (cfg->method);
1929 if (!cfg->arch.cinfo)
1930 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1931 cinfo = cfg->arch.cinfo;
1934 * The ARM64 ABI always uses a frame pointer.
1935 * The instruction set prefers positive offsets, so fp points to the bottom of the
1936 * frame, and stack slots are at positive offsets.
1937 * If some arguments are received on the stack, their offsets relative to fp can
1938 * not be computed right now because the stack frame might grow due to spilling
1939 * done by the local register allocator. To solve this, we reserve a register
1940 * which points to them.
1941 * The stack frame looks like this:
1942 * args_reg -> <bottom of parent frame>
1944 * fp -> <saved fp+lr>
1945 * sp -> <localloc/params area>
1947 cfg->frame_reg = ARMREG_FP;
1948 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1954 if (cinfo->stack_usage) {
1955 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1956 cfg->arch.args_reg = ARMREG_R28;
1957 cfg->used_int_regs |= 1 << ARMREG_R28;
1960 if (cfg->method->save_lmf) {
1961 /* The LMF var is allocated normally */
1963 /* Callee saved regs */
1964 cfg->arch.saved_gregs_offset = offset;
1965 for (i = 0; i < 32; ++i)
1966 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1971 switch (cinfo->ret.storage) {
1977 cfg->ret->opcode = OP_REGVAR;
1978 cfg->ret->dreg = cinfo->ret.reg;
1980 case ArgVtypeInIRegs:
1982 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1983 cfg->ret->opcode = OP_REGOFFSET;
1984 cfg->ret->inst_basereg = cfg->frame_reg;
1985 cfg->ret->inst_offset = offset;
1986 if (cinfo->ret.storage == ArgHFA)
1993 /* This variable will be initalized in the prolog from R8 */
1994 cfg->vret_addr->opcode = OP_REGOFFSET;
1995 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1996 cfg->vret_addr->inst_offset = offset;
1998 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1999 printf ("vret_addr =");
2000 mono_print_ins (cfg->vret_addr);
2004 g_assert_not_reached ();
2009 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2010 ainfo = cinfo->args + i;
2012 ins = cfg->args [i];
2013 if (ins->opcode == OP_REGVAR)
2016 ins->opcode = OP_REGOFFSET;
2017 ins->inst_basereg = cfg->frame_reg;
2019 switch (ainfo->storage) {
2023 // FIXME: Use nregs/size
2024 /* These will be copied to the stack in the prolog */
2025 ins->inst_offset = offset;
2031 case ArgVtypeOnStack:
2032 /* These are in the parent frame */
2033 g_assert (cfg->arch.args_reg);
2034 ins->inst_basereg = cfg->arch.args_reg;
2035 ins->inst_offset = ainfo->offset;
2037 case ArgVtypeInIRegs:
2039 ins->opcode = OP_REGOFFSET;
2040 ins->inst_basereg = cfg->frame_reg;
2041 /* These arguments are saved to the stack in the prolog */
2042 ins->inst_offset = offset;
2043 if (cfg->verbose_level >= 2)
2044 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2045 if (ainfo->storage == ArgHFA)
2051 case ArgVtypeByRefOnStack: {
2054 if (ainfo->gsharedvt) {
2055 ins->opcode = OP_REGOFFSET;
2056 ins->inst_basereg = cfg->arch.args_reg;
2057 ins->inst_offset = ainfo->offset;
2061 /* The vtype address is in the parent frame */
2062 g_assert (cfg->arch.args_reg);
2063 MONO_INST_NEW (cfg, vtaddr, 0);
2064 vtaddr->opcode = OP_REGOFFSET;
2065 vtaddr->inst_basereg = cfg->arch.args_reg;
2066 vtaddr->inst_offset = ainfo->offset;
2068 /* Need an indirection */
2069 ins->opcode = OP_VTARG_ADDR;
2070 ins->inst_left = vtaddr;
2073 case ArgVtypeByRef: {
2076 if (ainfo->gsharedvt) {
2077 ins->opcode = OP_REGOFFSET;
2078 ins->inst_basereg = cfg->frame_reg;
2079 ins->inst_offset = offset;
2084 /* The vtype address is in a register, will be copied to the stack in the prolog */
2085 MONO_INST_NEW (cfg, vtaddr, 0);
2086 vtaddr->opcode = OP_REGOFFSET;
2087 vtaddr->inst_basereg = cfg->frame_reg;
2088 vtaddr->inst_offset = offset;
2091 /* Need an indirection */
2092 ins->opcode = OP_VTARG_ADDR;
2093 ins->inst_left = vtaddr;
2097 g_assert_not_reached ();
2102 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2103 // FIXME: Allocate these to registers
2104 ins = cfg->arch.seq_point_info_var;
2108 offset += align - 1;
2109 offset &= ~(align - 1);
2110 ins->opcode = OP_REGOFFSET;
2111 ins->inst_basereg = cfg->frame_reg;
2112 ins->inst_offset = offset;
2115 ins = cfg->arch.ss_tramp_var;
2119 offset += align - 1;
2120 offset &= ~(align - 1);
2121 ins->opcode = OP_REGOFFSET;
2122 ins->inst_basereg = cfg->frame_reg;
2123 ins->inst_offset = offset;
2126 ins = cfg->arch.bp_tramp_var;
2130 offset += align - 1;
2131 offset &= ~(align - 1);
2132 ins->opcode = OP_REGOFFSET;
2133 ins->inst_basereg = cfg->frame_reg;
2134 ins->inst_offset = offset;
2139 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2140 if (locals_stack_align)
2141 offset = ALIGN_TO (offset, locals_stack_align);
2143 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2144 if (offsets [i] != -1) {
2145 ins = cfg->varinfo [i];
2146 ins->opcode = OP_REGOFFSET;
2147 ins->inst_basereg = cfg->frame_reg;
2148 ins->inst_offset = offset + offsets [i];
2149 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2152 offset += locals_stack_size;
2154 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2156 cfg->stack_offset = offset;
2161 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2166 LLVMCallInfo *linfo;
2168 n = sig->param_count + sig->hasthis;
2170 cinfo = get_call_info (cfg->mempool, sig);
2172 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2174 switch (cinfo->ret.storage) {
2181 linfo->ret.storage = LLVMArgVtypeByRef;
2184 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2185 // array which is returned in int regs
2188 linfo->ret.storage = LLVMArgFpStruct;
2189 linfo->ret.nslots = cinfo->ret.nregs;
2190 linfo->ret.esize = cinfo->ret.esize;
2192 case ArgVtypeInIRegs:
2193 /* LLVM models this by returning an int */
2194 linfo->ret.storage = LLVMArgVtypeAsScalar;
2195 linfo->ret.nslots = cinfo->ret.nregs;
2196 linfo->ret.esize = cinfo->ret.esize;
2199 g_assert_not_reached ();
2203 for (i = 0; i < n; ++i) {
2204 LLVMArgInfo *lainfo = &linfo->args [i];
2206 ainfo = cinfo->args + i;
2208 lainfo->storage = LLVMArgNone;
2210 switch (ainfo->storage) {
2217 lainfo->storage = LLVMArgNormal;
2220 case ArgVtypeByRefOnStack:
2221 lainfo->storage = LLVMArgVtypeByRef;
2226 lainfo->storage = LLVMArgAsFpArgs;
2227 lainfo->nslots = ainfo->nregs;
2228 lainfo->esize = ainfo->esize;
2229 for (j = 0; j < ainfo->nregs; ++j)
2230 lainfo->pair_storage [j] = LLVMArgInFPReg;
2233 case ArgVtypeInIRegs:
2234 lainfo->storage = LLVMArgAsIArgs;
2235 lainfo->nslots = ainfo->nregs;
2237 case ArgVtypeOnStack:
2241 lainfo->storage = LLVMArgAsFpArgs;
2242 lainfo->nslots = ainfo->nregs;
2243 lainfo->esize = ainfo->esize;
2244 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2245 for (j = 0; j < ainfo->nregs; ++j)
2246 lainfo->pair_storage [j] = LLVMArgInFPReg;
2248 lainfo->storage = LLVMArgAsIArgs;
2249 lainfo->nslots = ainfo->size / 8;
2253 g_assert_not_reached ();
2263 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2269 MONO_INST_NEW (cfg, ins, OP_MOVE);
2270 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2271 ins->sreg1 = arg->dreg;
2272 MONO_ADD_INS (cfg->cbb, ins);
2273 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2276 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2277 ins->dreg = mono_alloc_freg (cfg);
2278 ins->sreg1 = arg->dreg;
2279 MONO_ADD_INS (cfg->cbb, ins);
2280 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2283 if (COMPILE_LLVM (cfg))
2284 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2286 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2288 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2289 ins->dreg = mono_alloc_freg (cfg);
2290 ins->sreg1 = arg->dreg;
2291 MONO_ADD_INS (cfg->cbb, ins);
2292 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2295 g_assert_not_reached ();
2301 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2303 MonoMethodSignature *tmp_sig;
2306 if (call->tail_call)
2309 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2312 * mono_ArgIterator_Setup assumes the signature cookie is
2313 * passed first and all the arguments which were before it are
2314 * passed on the stack after the signature. So compensate by
2315 * passing a different signature.
2317 tmp_sig = mono_metadata_signature_dup (call->signature);
2318 tmp_sig->param_count -= call->signature->sentinelpos;
2319 tmp_sig->sentinelpos = 0;
2320 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2322 sig_reg = mono_alloc_ireg (cfg);
2323 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2325 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2329 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2331 MonoMethodSignature *sig;
2332 MonoInst *arg, *vtarg;
2337 sig = call->signature;
2339 cinfo = get_call_info (cfg->mempool, sig);
2341 switch (cinfo->ret.storage) {
2342 case ArgVtypeInIRegs:
2345 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2346 * the location pointed to by it after call in emit_move_return_value ().
2348 if (!cfg->arch.vret_addr_loc) {
2349 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2350 /* Prevent it from being register allocated or optimized away */
2351 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2354 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2357 /* Pass the vtype return address in R8 */
2358 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2359 vtarg->sreg1 = call->vret_var->dreg;
2360 vtarg->dreg = mono_alloc_preg (cfg);
2361 MONO_ADD_INS (cfg->cbb, vtarg);
2363 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2369 for (i = 0; i < cinfo->nargs; ++i) {
2370 ainfo = cinfo->args + i;
2371 arg = call->args [i];
2373 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2374 /* Emit the signature cookie just before the implicit arguments */
2375 emit_sig_cookie (cfg, call, cinfo);
2378 switch (ainfo->storage) {
2382 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2385 switch (ainfo->slot_size) {
2387 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2390 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2393 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2396 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2399 g_assert_not_reached ();
2404 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2407 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2409 case ArgVtypeInIRegs:
2411 case ArgVtypeByRefOnStack:
2412 case ArgVtypeOnStack:
2418 size = mono_class_value_size (arg->klass, &align);
2420 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2421 ins->sreg1 = arg->dreg;
2422 ins->klass = arg->klass;
2423 ins->backend.size = size;
2424 ins->inst_p0 = call;
2425 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2426 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2427 MONO_ADD_INS (cfg->cbb, ins);
2431 g_assert_not_reached ();
2436 /* Handle the case where there are no implicit arguments */
2437 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2438 emit_sig_cookie (cfg, call, cinfo);
2440 call->call_info = cinfo;
2441 call->stack_usage = cinfo->stack_usage;
2445 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2447 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2448 ArgInfo *ainfo = ins->inst_p1;
2452 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2455 switch (ainfo->storage) {
2456 case ArgVtypeInIRegs:
2457 for (i = 0; i < ainfo->nregs; ++i) {
2458 // FIXME: Smaller sizes
2459 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2460 load->dreg = mono_alloc_ireg (cfg);
2461 load->inst_basereg = src->dreg;
2462 load->inst_offset = i * sizeof(mgreg_t);
2463 MONO_ADD_INS (cfg->cbb, load);
2464 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2468 for (i = 0; i < ainfo->nregs; ++i) {
2469 if (ainfo->esize == 4)
2470 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2472 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2473 load->dreg = mono_alloc_freg (cfg);
2474 load->inst_basereg = src->dreg;
2475 load->inst_offset = ainfo->foffsets [i];
2476 MONO_ADD_INS (cfg->cbb, load);
2477 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2481 case ArgVtypeByRefOnStack: {
2482 MonoInst *vtaddr, *load, *arg;
2484 /* Pass the vtype address in a reg/on the stack */
2485 if (ainfo->gsharedvt) {
2488 /* Make a copy of the argument */
2489 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2491 MONO_INST_NEW (cfg, load, OP_LDADDR);
2492 load->inst_p0 = vtaddr;
2493 vtaddr->flags |= MONO_INST_INDIRECT;
2494 load->type = STACK_MP;
2495 load->klass = vtaddr->klass;
2496 load->dreg = mono_alloc_ireg (cfg);
2497 MONO_ADD_INS (cfg->cbb, load);
2498 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2501 if (ainfo->storage == ArgVtypeByRef) {
2502 MONO_INST_NEW (cfg, arg, OP_MOVE);
2503 arg->dreg = mono_alloc_preg (cfg);
2504 arg->sreg1 = load->dreg;
2505 MONO_ADD_INS (cfg->cbb, arg);
2506 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2508 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2512 case ArgVtypeOnStack:
2513 for (i = 0; i < ainfo->size / 8; ++i) {
2514 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2515 load->dreg = mono_alloc_ireg (cfg);
2516 load->inst_basereg = src->dreg;
2517 load->inst_offset = i * 8;
2518 MONO_ADD_INS (cfg->cbb, load);
2519 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2523 g_assert_not_reached ();
2529 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2531 MonoMethodSignature *sig;
2534 sig = mono_method_signature (cfg->method);
2535 if (!cfg->arch.cinfo)
2536 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2537 cinfo = cfg->arch.cinfo;
2539 switch (cinfo->ret.storage) {
2543 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2546 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2549 if (COMPILE_LLVM (cfg))
2550 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2552 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2554 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2557 g_assert_not_reached ();
2563 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2568 if (cfg->compile_aot && !cfg->full_aot)
2569 /* OP_TAILCALL doesn't work with AOT */
2572 c1 = get_call_info (NULL, caller_sig);
2573 c2 = get_call_info (NULL, callee_sig);
2575 // FIXME: Relax these restrictions
2576 if (c1->stack_usage != 0)
2578 if (c1->stack_usage != c2->stack_usage)
2580 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2590 mono_arch_is_inst_imm (gint64 imm)
2592 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2596 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2603 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2610 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2616 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2621 #define ADD_NEW_INS(cfg,dest,op) do { \
2622 MONO_INST_NEW ((cfg), (dest), (op)); \
2623 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2627 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2629 MonoInst *ins, *temp, *last_ins = NULL;
2631 MONO_BB_FOR_EACH_INS (bb, ins) {
2632 switch (ins->opcode) {
2637 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2638 /* ARM sets the C flag to 1 if there was _no_ overflow */
2639 ins->next->opcode = OP_COND_EXC_NC;
2643 case OP_IDIV_UN_IMM:
2644 case OP_IREM_UN_IMM:
2646 mono_decompose_op_imm (cfg, bb, ins);
2648 case OP_LOCALLOC_IMM:
2649 if (ins->inst_imm > 32) {
2650 ADD_NEW_INS (cfg, temp, OP_ICONST);
2651 temp->inst_c0 = ins->inst_imm;
2652 temp->dreg = mono_alloc_ireg (cfg);
2653 ins->sreg1 = temp->dreg;
2654 ins->opcode = mono_op_imm_to_op (ins->opcode);
2657 case OP_ICOMPARE_IMM:
2658 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2659 ins->next->opcode = OP_ARM64_CBZW;
2660 ins->next->sreg1 = ins->sreg1;
2662 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2663 ins->next->opcode = OP_ARM64_CBNZW;
2664 ins->next->sreg1 = ins->sreg1;
2668 case OP_LCOMPARE_IMM:
2669 case OP_COMPARE_IMM:
2670 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2671 ins->next->opcode = OP_ARM64_CBZX;
2672 ins->next->sreg1 = ins->sreg1;
2674 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2675 ins->next->opcode = OP_ARM64_CBNZX;
2676 ins->next->sreg1 = ins->sreg1;
2681 gboolean swap = FALSE;
2685 /* Optimized away */
2691 * FP compares with unordered operands set the flags
2692 * to NZCV=0011, which matches some non-unordered compares
2693 * as well, like LE, so have to swap the operands.
2695 switch (ins->next->opcode) {
2697 ins->next->opcode = OP_FBGT;
2701 ins->next->opcode = OP_FBGE;
2709 ins->sreg1 = ins->sreg2;
2720 bb->last_ins = last_ins;
2721 bb->max_vreg = cfg->next_vreg;
2725 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2730 opcode_to_armcond (int opcode)
2741 case OP_COND_EXC_IEQ:
2742 case OP_COND_EXC_EQ:
2759 case OP_COND_EXC_IGT:
2760 case OP_COND_EXC_GT:
2775 case OP_COND_EXC_ILT:
2776 case OP_COND_EXC_LT:
2784 case OP_COND_EXC_INE_UN:
2785 case OP_COND_EXC_NE_UN:
2791 case OP_COND_EXC_IGE_UN:
2792 case OP_COND_EXC_GE_UN:
2802 case OP_COND_EXC_IGT_UN:
2803 case OP_COND_EXC_GT_UN:
2809 case OP_COND_EXC_ILE_UN:
2810 case OP_COND_EXC_LE_UN:
2818 case OP_COND_EXC_ILT_UN:
2819 case OP_COND_EXC_LT_UN:
2822 * FCMP sets the NZCV condition bits as follows:
2827 * ARMCOND_LT is N!=V, so it matches unordered too, so
2828 * fclt and fclt_un need to be special cased.
2838 case OP_COND_EXC_IC:
2840 case OP_COND_EXC_OV:
2841 case OP_COND_EXC_IOV:
2843 case OP_COND_EXC_NC:
2844 case OP_COND_EXC_INC:
2846 case OP_COND_EXC_NO:
2847 case OP_COND_EXC_INO:
2850 printf ("%s\n", mono_inst_name (opcode));
2851 g_assert_not_reached ();
2856 /* This clobbers LR */
2857 static inline __attribute__ ((__warn_unused_result__)) guint8*
2858 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2862 cond = opcode_to_armcond (opcode);
2864 arm_adrx (code, ARMREG_IP1, code);
2865 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2866 arm_bcc (code, cond, 0);
2871 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2876 call = (MonoCallInst*)ins;
2877 cinfo = call->call_info;
2879 switch (cinfo->ret.storage) {
2883 /* LLVM compiled code might only set the bottom bits */
2884 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2885 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2886 else if (call->inst.dreg != cinfo->ret.reg)
2887 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2890 if (call->inst.dreg != cinfo->ret.reg)
2891 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2895 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2897 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2899 case ArgVtypeInIRegs: {
2900 MonoInst *loc = cfg->arch.vret_addr_loc;
2903 /* Load the destination address */
2904 g_assert (loc && loc->opcode == OP_REGOFFSET);
2905 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2906 for (i = 0; i < cinfo->ret.nregs; ++i)
2907 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2911 MonoInst *loc = cfg->arch.vret_addr_loc;
2914 /* Load the destination address */
2915 g_assert (loc && loc->opcode == OP_REGOFFSET);
2916 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2917 for (i = 0; i < cinfo->ret.nregs; ++i) {
2918 if (cinfo->ret.esize == 4)
2919 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2921 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2928 g_assert_not_reached ();
2935 * emit_branch_island:
2937 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2940 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2943 int offset, island_size;
2945 /* Iterate over the patch infos added so far by this bb */
2947 for (ji = cfg->patch_info; ji; ji = ji->next) {
2948 if (ji->ip.i < start_offset)
2949 /* The patch infos are in reverse order, so this means the end */
2951 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2956 offset = code - cfg->native_code;
2957 if (offset > (cfg->code_size - island_size - 16)) {
2958 cfg->code_size *= 2;
2959 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2960 code = cfg->native_code + offset;
2963 /* Branch over the island */
2964 arm_b (code, code + 4 + island_size);
2966 for (ji = cfg->patch_info; ji; ji = ji->next) {
2967 if (ji->ip.i < start_offset)
2969 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2970 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2971 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2972 /* Rewrite the patch so it points to the unconditional branch */
2973 ji->ip.i = code - cfg->native_code;
2974 ji->relocation = MONO_R_ARM64_B;
2983 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2988 guint8 *code = cfg->native_code + cfg->code_len;
2989 int start_offset, max_len, dreg, sreg1, sreg2;
2992 if (cfg->verbose_level > 2)
2993 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2995 start_offset = code - cfg->native_code;
2997 MONO_BB_FOR_EACH_INS (bb, ins) {
2998 offset = code - cfg->native_code;
3000 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3002 if (offset > (cfg->code_size - max_len - 16)) {
3003 cfg->code_size *= 2;
3004 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3005 code = cfg->native_code + offset;
3008 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
3009 /* Emit a branch island for large basic blocks */
3010 code = emit_branch_island (cfg, code, start_offset);
3011 offset = code - cfg->native_code;
3012 start_offset = offset;
3015 mono_debug_record_line_number (cfg, ins, offset);
3020 imm = ins->inst_imm;
3022 switch (ins->opcode) {
3024 code = emit_imm (code, dreg, ins->inst_c0);
3027 code = emit_imm64 (code, dreg, ins->inst_c0);
3031 arm_movx (code, dreg, sreg1);
3034 case OP_RELAXED_NOP:
3037 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3038 code = emit_imm64_template (code, dreg);
3042 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3043 * So instead of emitting a trap, we emit a call a C function and place a
3046 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3051 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3052 // FIXME: andx_imm doesn't work yet
3053 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3054 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3055 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3056 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3057 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3058 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3061 /* ip1 = pointer, ip0 = end */
3062 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3064 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3066 arm_bcc (code, ARMCOND_EQ, 0);
3067 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3068 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3069 arm_b (code, buf [0]);
3070 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3072 arm_movspx (code, dreg, ARMREG_SP);
3073 if (cfg->param_area)
3074 code = emit_subx_sp_imm (code, cfg->param_area);
3077 case OP_LOCALLOC_IMM: {
3080 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3081 g_assert (arm_is_arith_imm (imm));
3082 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3085 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3087 while (offset < imm) {
3088 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3091 arm_movspx (code, dreg, ARMREG_SP);
3092 if (cfg->param_area)
3093 code = emit_subx_sp_imm (code, cfg->param_area);
3097 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3099 case OP_OBJC_GET_SELECTOR:
3100 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3101 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3102 arm_ldrx_lit (code, ins->dreg, 0);
3106 case OP_SEQ_POINT: {
3107 MonoInst *info_var = cfg->arch.seq_point_info_var;
3110 * For AOT, we use one got slot per method, which will point to a
3111 * SeqPointInfo structure, containing all the information required
3112 * by the code below.
3114 if (cfg->compile_aot) {
3115 g_assert (info_var);
3116 g_assert (info_var->opcode == OP_REGOFFSET);
3119 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3120 MonoInst *var = cfg->arch.ss_tramp_var;
3123 g_assert (var->opcode == OP_REGOFFSET);
3124 /* Load ss_tramp_var */
3125 /* This is equal to &ss_trampoline */
3126 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3127 /* Load the trampoline address */
3128 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3129 /* Call it if it is non-null */
3130 arm_cbzx (code, ARMREG_IP1, code + 8);
3131 arm_blrx (code, ARMREG_IP1);
3134 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3136 if (cfg->compile_aot) {
3137 guint32 offset = code - cfg->native_code;
3140 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3141 /* Add the offset */
3142 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3143 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3144 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3145 /* Skip the load if its 0 */
3146 arm_cbzx (code, ARMREG_IP1, code + 8);
3147 /* Call the breakpoint trampoline */
3148 arm_blrx (code, ARMREG_IP1);
3150 MonoInst *var = cfg->arch.bp_tramp_var;
3153 g_assert (var->opcode == OP_REGOFFSET);
3154 /* Load the address of the bp trampoline into IP0 */
3155 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3157 * A placeholder for a possible breakpoint inserted by
3158 * mono_arch_set_breakpoint ().
3167 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3171 arm_brx (code, sreg1);
3203 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3204 cond = opcode_to_armcond (ins->opcode);
3205 arm_bcc (code, cond, 0);
3209 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3210 /* For fp compares, ARMCOND_LT is lt or unordered */
3211 arm_bcc (code, ARMCOND_LT, 0);
3214 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3215 arm_bcc (code, ARMCOND_EQ, 0);
3216 offset = code - cfg->native_code;
3217 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3218 /* For fp compares, ARMCOND_LT is lt or unordered */
3219 arm_bcc (code, ARMCOND_LT, 0);
3222 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3223 arm_cbzw (code, sreg1, 0);
3226 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3227 arm_cbzx (code, sreg1, 0);
3229 case OP_ARM64_CBNZW:
3230 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3231 arm_cbnzw (code, sreg1, 0);
3233 case OP_ARM64_CBNZX:
3234 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3235 arm_cbnzx (code, sreg1, 0);
3239 arm_addw (code, dreg, sreg1, sreg2);
3242 arm_addx (code, dreg, sreg1, sreg2);
3245 arm_subw (code, dreg, sreg1, sreg2);
3248 arm_subx (code, dreg, sreg1, sreg2);
3251 arm_andw (code, dreg, sreg1, sreg2);
3254 arm_andx (code, dreg, sreg1, sreg2);
3257 arm_orrw (code, dreg, sreg1, sreg2);
3260 arm_orrx (code, dreg, sreg1, sreg2);
3263 arm_eorw (code, dreg, sreg1, sreg2);
3266 arm_eorx (code, dreg, sreg1, sreg2);
3269 arm_negw (code, dreg, sreg1);
3272 arm_negx (code, dreg, sreg1);
3275 arm_mvnw (code, dreg, sreg1);
3278 arm_mvnx (code, dreg, sreg1);
3281 arm_addsw (code, dreg, sreg1, sreg2);
3285 arm_addsx (code, dreg, sreg1, sreg2);
3288 arm_subsw (code, dreg, sreg1, sreg2);
3292 arm_subsx (code, dreg, sreg1, sreg2);
3295 arm_cmpw (code, sreg1, sreg2);
3299 arm_cmpx (code, sreg1, sreg2);
3302 code = emit_addw_imm (code, dreg, sreg1, imm);
3306 code = emit_addx_imm (code, dreg, sreg1, imm);
3309 code = emit_subw_imm (code, dreg, sreg1, imm);
3312 code = emit_subx_imm (code, dreg, sreg1, imm);
3315 code = emit_andw_imm (code, dreg, sreg1, imm);
3319 code = emit_andx_imm (code, dreg, sreg1, imm);
3322 code = emit_orrw_imm (code, dreg, sreg1, imm);
3325 code = emit_orrx_imm (code, dreg, sreg1, imm);
3328 code = emit_eorw_imm (code, dreg, sreg1, imm);
3331 code = emit_eorx_imm (code, dreg, sreg1, imm);
3333 case OP_ICOMPARE_IMM:
3334 code = emit_cmpw_imm (code, sreg1, imm);
3336 case OP_LCOMPARE_IMM:
3337 case OP_COMPARE_IMM:
3339 arm_cmpx (code, sreg1, ARMREG_RZR);
3341 // FIXME: 32 vs 64 bit issues for 0xffffffff
3342 code = emit_imm64 (code, ARMREG_LR, imm);
3343 arm_cmpx (code, sreg1, ARMREG_LR);
3347 arm_lslvw (code, dreg, sreg1, sreg2);
3350 arm_lslvx (code, dreg, sreg1, sreg2);
3353 arm_asrvw (code, dreg, sreg1, sreg2);
3356 arm_asrvx (code, dreg, sreg1, sreg2);
3359 arm_lsrvw (code, dreg, sreg1, sreg2);
3362 arm_lsrvx (code, dreg, sreg1, sreg2);
3366 arm_movx (code, dreg, sreg1);
3368 arm_lslw (code, dreg, sreg1, imm);
3372 arm_movx (code, dreg, sreg1);
3374 arm_lslx (code, dreg, sreg1, imm);
3378 arm_movx (code, dreg, sreg1);
3380 arm_asrw (code, dreg, sreg1, imm);
3385 arm_movx (code, dreg, sreg1);
3387 arm_asrx (code, dreg, sreg1, imm);
3389 case OP_ISHR_UN_IMM:
3391 arm_movx (code, dreg, sreg1);
3393 arm_lsrw (code, dreg, sreg1, imm);
3396 case OP_LSHR_UN_IMM:
3398 arm_movx (code, dreg, sreg1);
3400 arm_lsrx (code, dreg, sreg1, imm);
3405 arm_sxtwx (code, dreg, sreg1);
3408 /* Clean out the upper word */
3409 arm_movw (code, dreg, sreg1);
3412 arm_lslx (code, dreg, sreg1, imm);
3415 /* MULTIPLY/DIVISION */
3418 // FIXME: Optimize this
3419 /* Check for zero */
3420 arm_cmpx_imm (code, sreg2, 0);
3421 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3422 /* Check for INT_MIN/-1 */
3423 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3424 arm_cmpx (code, sreg1, ARMREG_IP0);
3425 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3426 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3427 arm_cmpx (code, sreg2, ARMREG_IP0);
3428 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3429 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3430 arm_cmpx_imm (code, ARMREG_IP0, 1);
3431 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3432 if (ins->opcode == OP_IREM) {
3433 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3434 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3436 arm_sdivw (code, dreg, sreg1, sreg2);
3440 arm_cmpx_imm (code, sreg2, 0);
3441 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3442 arm_udivw (code, dreg, sreg1, sreg2);
3445 arm_cmpx_imm (code, sreg2, 0);
3446 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3447 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3448 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3452 // FIXME: Optimize this
3453 /* Check for zero */
3454 arm_cmpx_imm (code, sreg2, 0);
3455 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3456 /* Check for INT64_MIN/-1 */
3457 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3458 arm_cmpx (code, sreg1, ARMREG_IP0);
3459 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3460 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3461 arm_cmpx (code, sreg2, ARMREG_IP0);
3462 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3463 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3464 arm_cmpx_imm (code, ARMREG_IP0, 1);
3465 /* 64 bit uses ArithmeticException */
3466 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3467 if (ins->opcode == OP_LREM) {
3468 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3469 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3471 arm_sdivx (code, dreg, sreg1, sreg2);
3475 arm_cmpx_imm (code, sreg2, 0);
3476 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3477 arm_udivx (code, dreg, sreg1, sreg2);
3480 arm_cmpx_imm (code, sreg2, 0);
3481 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3482 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3483 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3486 arm_mulw (code, dreg, sreg1, sreg2);
3489 arm_mulx (code, dreg, sreg1, sreg2);
3492 code = emit_imm (code, ARMREG_LR, imm);
3493 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3497 code = emit_imm (code, ARMREG_LR, imm);
3498 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3502 case OP_ICONV_TO_I1:
3503 case OP_LCONV_TO_I1:
3504 arm_sxtbx (code, dreg, sreg1);
3506 case OP_ICONV_TO_I2:
3507 case OP_LCONV_TO_I2:
3508 arm_sxthx (code, dreg, sreg1);
3510 case OP_ICONV_TO_U1:
3511 case OP_LCONV_TO_U1:
3512 arm_uxtbw (code, dreg, sreg1);
3514 case OP_ICONV_TO_U2:
3515 case OP_LCONV_TO_U2:
3516 arm_uxthw (code, dreg, sreg1);
3542 cond = opcode_to_armcond (ins->opcode);
3543 arm_cset (code, cond, dreg);
3556 cond = opcode_to_armcond (ins->opcode);
3557 arm_fcmpd (code, sreg1, sreg2);
3558 arm_cset (code, cond, dreg);
3563 case OP_LOADI1_MEMBASE:
3564 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3566 case OP_LOADU1_MEMBASE:
3567 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3569 case OP_LOADI2_MEMBASE:
3570 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3572 case OP_LOADU2_MEMBASE:
3573 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3575 case OP_LOADI4_MEMBASE:
3576 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3578 case OP_LOADU4_MEMBASE:
3579 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3581 case OP_LOAD_MEMBASE:
3582 case OP_LOADI8_MEMBASE:
3583 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3585 case OP_STOREI1_MEMBASE_IMM:
3586 case OP_STOREI2_MEMBASE_IMM:
3587 case OP_STOREI4_MEMBASE_IMM:
3588 case OP_STORE_MEMBASE_IMM:
3589 case OP_STOREI8_MEMBASE_IMM: {
3593 code = emit_imm (code, ARMREG_LR, imm);
3596 immreg = ARMREG_RZR;
3599 switch (ins->opcode) {
3600 case OP_STOREI1_MEMBASE_IMM:
3601 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3603 case OP_STOREI2_MEMBASE_IMM:
3604 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3606 case OP_STOREI4_MEMBASE_IMM:
3607 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3609 case OP_STORE_MEMBASE_IMM:
3610 case OP_STOREI8_MEMBASE_IMM:
3611 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3614 g_assert_not_reached ();
3619 case OP_STOREI1_MEMBASE_REG:
3620 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3622 case OP_STOREI2_MEMBASE_REG:
3623 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3625 case OP_STOREI4_MEMBASE_REG:
3626 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3628 case OP_STORE_MEMBASE_REG:
3629 case OP_STOREI8_MEMBASE_REG:
3630 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3633 code = emit_tls_get (code, dreg, ins->inst_offset);
3636 code = emit_tls_set (code, sreg1, ins->inst_offset);
3639 case OP_MEMORY_BARRIER:
3642 case OP_ATOMIC_ADD_I4: {
3646 arm_ldxrw (code, ARMREG_IP0, sreg1);
3647 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3648 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3649 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3652 arm_movx (code, dreg, ARMREG_IP0);
3655 case OP_ATOMIC_ADD_I8: {
3659 arm_ldxrx (code, ARMREG_IP0, sreg1);
3660 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3661 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3662 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3665 arm_movx (code, dreg, ARMREG_IP0);
3668 case OP_ATOMIC_EXCHANGE_I4: {
3672 arm_ldxrw (code, ARMREG_IP0, sreg1);
3673 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3674 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3677 arm_movx (code, dreg, ARMREG_IP0);
3680 case OP_ATOMIC_EXCHANGE_I8: {
3684 arm_ldxrx (code, ARMREG_IP0, sreg1);
3685 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3686 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3689 arm_movx (code, dreg, ARMREG_IP0);
3692 case OP_ATOMIC_CAS_I4: {
3695 /* sreg2 is the value, sreg3 is the comparand */
3697 arm_ldxrw (code, ARMREG_IP0, sreg1);
3698 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3700 arm_bcc (code, ARMCOND_NE, 0);
3701 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3702 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3703 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3706 arm_movx (code, dreg, ARMREG_IP0);
3709 case OP_ATOMIC_CAS_I8: {
3713 arm_ldxrx (code, ARMREG_IP0, sreg1);
3714 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3716 arm_bcc (code, ARMCOND_NE, 0);
3717 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3718 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3719 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3722 arm_movx (code, dreg, ARMREG_IP0);
3725 case OP_ATOMIC_LOAD_I1: {
3726 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3727 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3729 arm_ldarb (code, ins->dreg, ARMREG_LR);
3730 arm_sxtbx (code, ins->dreg, ins->dreg);
3733 case OP_ATOMIC_LOAD_U1: {
3734 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3735 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3737 arm_ldarb (code, ins->dreg, ARMREG_LR);
3738 arm_uxtbx (code, ins->dreg, ins->dreg);
3741 case OP_ATOMIC_LOAD_I2: {
3742 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3743 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3745 arm_ldarh (code, ins->dreg, ARMREG_LR);
3746 arm_sxthx (code, ins->dreg, ins->dreg);
3749 case OP_ATOMIC_LOAD_U2: {
3750 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3751 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3753 arm_ldarh (code, ins->dreg, ARMREG_LR);
3754 arm_uxthx (code, ins->dreg, ins->dreg);
3757 case OP_ATOMIC_LOAD_I4: {
3758 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3759 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3761 arm_ldarw (code, ins->dreg, ARMREG_LR);
3762 arm_sxtwx (code, ins->dreg, ins->dreg);
3765 case OP_ATOMIC_LOAD_U4: {
3766 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3767 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3769 arm_ldarw (code, ins->dreg, ARMREG_LR);
3770 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3773 case OP_ATOMIC_LOAD_I8:
3774 case OP_ATOMIC_LOAD_U8: {
3775 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3776 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3778 arm_ldarx (code, ins->dreg, ARMREG_LR);
3781 case OP_ATOMIC_LOAD_R4: {
3782 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3783 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3786 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3787 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3789 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3790 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3791 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3795 case OP_ATOMIC_LOAD_R8: {
3796 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3797 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3799 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3800 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3803 case OP_ATOMIC_STORE_I1:
3804 case OP_ATOMIC_STORE_U1: {
3805 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3806 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3807 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3811 case OP_ATOMIC_STORE_I2:
3812 case OP_ATOMIC_STORE_U2: {
3813 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3814 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3815 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3819 case OP_ATOMIC_STORE_I4:
3820 case OP_ATOMIC_STORE_U4: {
3821 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3822 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3823 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3827 case OP_ATOMIC_STORE_I8:
3828 case OP_ATOMIC_STORE_U8: {
3829 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3830 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3831 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3835 case OP_ATOMIC_STORE_R4: {
3836 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3838 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3839 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3841 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3842 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3843 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3845 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3849 case OP_ATOMIC_STORE_R8: {
3850 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3851 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3852 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3853 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3860 guint64 imm = *(guint64*)ins->inst_p0;
3863 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3865 code = emit_imm64 (code, ARMREG_LR, imm);
3866 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3871 guint64 imm = *(guint32*)ins->inst_p0;
3873 code = emit_imm64 (code, ARMREG_LR, imm);
3875 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3877 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3878 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3882 case OP_LOADR8_MEMBASE:
3883 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3885 case OP_LOADR4_MEMBASE:
3887 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3889 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3890 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3893 case OP_STORER8_MEMBASE_REG:
3894 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3896 case OP_STORER4_MEMBASE_REG:
3898 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3900 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3901 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3906 arm_fmovd (code, dreg, sreg1);
3910 arm_fmovs (code, dreg, sreg1);
3912 case OP_MOVE_F_TO_I4:
3914 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3916 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3917 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3920 case OP_MOVE_I4_TO_F:
3922 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3924 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3925 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3928 case OP_MOVE_F_TO_I8:
3929 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3931 case OP_MOVE_I8_TO_F:
3932 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3935 arm_fcmpd (code, sreg1, sreg2);
3938 arm_fcmps (code, sreg1, sreg2);
3940 case OP_FCONV_TO_I1:
3941 arm_fcvtzs_dx (code, dreg, sreg1);
3942 arm_sxtbx (code, dreg, dreg);
3944 case OP_FCONV_TO_U1:
3945 arm_fcvtzu_dx (code, dreg, sreg1);
3946 arm_uxtbw (code, dreg, dreg);
3948 case OP_FCONV_TO_I2:
3949 arm_fcvtzs_dx (code, dreg, sreg1);
3950 arm_sxthx (code, dreg, dreg);
3952 case OP_FCONV_TO_U2:
3953 arm_fcvtzu_dx (code, dreg, sreg1);
3954 arm_uxthw (code, dreg, dreg);
3956 case OP_FCONV_TO_I4:
3957 arm_fcvtzs_dx (code, dreg, sreg1);
3958 arm_sxtwx (code, dreg, dreg);
3960 case OP_FCONV_TO_U4:
3961 arm_fcvtzu_dx (code, dreg, sreg1);
3963 case OP_FCONV_TO_I8:
3964 arm_fcvtzs_dx (code, dreg, sreg1);
3966 case OP_FCONV_TO_U8:
3967 arm_fcvtzu_dx (code, dreg, sreg1);
3969 case OP_FCONV_TO_R4:
3971 arm_fcvt_ds (code, dreg, sreg1);
3973 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3974 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3977 case OP_ICONV_TO_R4:
3979 arm_scvtf_rw_to_s (code, dreg, sreg1);
3981 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
3982 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3985 case OP_LCONV_TO_R4:
3987 arm_scvtf_rx_to_s (code, dreg, sreg1);
3989 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
3990 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3993 case OP_ICONV_TO_R8:
3994 arm_scvtf_rw_to_d (code, dreg, sreg1);
3996 case OP_LCONV_TO_R8:
3997 arm_scvtf_rx_to_d (code, dreg, sreg1);
3999 case OP_ICONV_TO_R_UN:
4000 arm_ucvtf_rw_to_d (code, dreg, sreg1);
4002 case OP_LCONV_TO_R_UN:
4003 arm_ucvtf_rx_to_d (code, dreg, sreg1);
4006 arm_fadd_d (code, dreg, sreg1, sreg2);
4009 arm_fsub_d (code, dreg, sreg1, sreg2);
4012 arm_fmul_d (code, dreg, sreg1, sreg2);
4015 arm_fdiv_d (code, dreg, sreg1, sreg2);
4019 g_assert_not_reached ();
4022 arm_fneg_d (code, dreg, sreg1);
4024 case OP_ARM_SETFREG_R4:
4025 arm_fcvt_ds (code, dreg, sreg1);
4028 /* Check for infinity */
4029 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
4030 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
4031 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
4032 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
4033 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
4034 /* Check for nans */
4035 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
4036 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
4037 arm_fmovd (code, dreg, sreg1);
4042 arm_fadd_s (code, dreg, sreg1, sreg2);
4045 arm_fsub_s (code, dreg, sreg1, sreg2);
4048 arm_fmul_s (code, dreg, sreg1, sreg2);
4051 arm_fdiv_s (code, dreg, sreg1, sreg2);
4054 arm_fneg_s (code, dreg, sreg1);
4056 case OP_RCONV_TO_I1:
4057 arm_fcvtzs_sx (code, dreg, sreg1);
4058 arm_sxtbx (code, dreg, dreg);
4060 case OP_RCONV_TO_U1:
4061 arm_fcvtzu_sx (code, dreg, sreg1);
4062 arm_uxtbw (code, dreg, dreg);
4064 case OP_RCONV_TO_I2:
4065 arm_fcvtzs_sx (code, dreg, sreg1);
4066 arm_sxthx (code, dreg, dreg);
4068 case OP_RCONV_TO_U2:
4069 arm_fcvtzu_sx (code, dreg, sreg1);
4070 arm_uxthw (code, dreg, dreg);
4072 case OP_RCONV_TO_I4:
4073 arm_fcvtzs_sx (code, dreg, sreg1);
4074 arm_sxtwx (code, dreg, dreg);
4076 case OP_RCONV_TO_U4:
4077 arm_fcvtzu_sx (code, dreg, sreg1);
4079 case OP_RCONV_TO_I8:
4080 arm_fcvtzs_sx (code, dreg, sreg1);
4082 case OP_RCONV_TO_U8:
4083 arm_fcvtzu_sx (code, dreg, sreg1);
4085 case OP_RCONV_TO_R8:
4086 arm_fcvt_sd (code, dreg, sreg1);
4088 case OP_RCONV_TO_R4:
4090 arm_fmovs (code, dreg, sreg1);
4102 cond = opcode_to_armcond (ins->opcode);
4103 arm_fcmps (code, sreg1, sreg2);
4104 arm_cset (code, cond, dreg);
4115 call = (MonoCallInst*)ins;
4116 if (ins->flags & MONO_INST_HAS_METHOD)
4117 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4119 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4120 code = emit_move_return_value (cfg, code, ins);
4122 case OP_VOIDCALL_REG:
4128 arm_blrx (code, sreg1);
4129 code = emit_move_return_value (cfg, code, ins);
4131 case OP_VOIDCALL_MEMBASE:
4132 case OP_CALL_MEMBASE:
4133 case OP_LCALL_MEMBASE:
4134 case OP_FCALL_MEMBASE:
4135 case OP_RCALL_MEMBASE:
4136 case OP_VCALL2_MEMBASE:
4137 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4138 arm_blrx (code, ARMREG_IP0);
4139 code = emit_move_return_value (cfg, code, ins);
4142 MonoCallInst *call = (MonoCallInst*)ins;
4144 g_assert (!cfg->method->save_lmf);
4146 // FIXME: Copy stack arguments
4148 /* Restore registers */
4149 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4152 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4154 if (cfg->compile_aot) {
4155 /* This is not a PLT patch */
4156 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4157 arm_brx (code, ARMREG_IP0);
4159 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4162 ins->flags |= MONO_INST_GC_CALLSITE;
4163 ins->backend.pc_offset = code - cfg->native_code;
4167 g_assert (cfg->arch.cinfo);
4168 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4169 arm_strx (code, ARMREG_IP0, sreg1, 0);
4172 MonoInst *var = cfg->dyn_call_var;
4173 guint8 *labels [16];
4177 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4178 * sreg2 is the function to call.
4181 g_assert (var->opcode == OP_REGOFFSET);
4183 arm_movx (code, ARMREG_LR, sreg1);
4184 arm_movx (code, ARMREG_IP1, sreg2);
4186 /* Save args buffer */
4187 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4189 /* Set fp argument regs */
4190 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4191 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4193 arm_bcc (code, ARMCOND_EQ, 0);
4194 for (i = 0; i < 8; ++i)
4195 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4196 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4198 /* Set stack args */
4199 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4200 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4201 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4204 /* Set argument registers + r8 */
4205 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4208 arm_blrx (code, ARMREG_IP1);
4211 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4212 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4213 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4214 /* Save fp result */
4215 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4216 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4218 arm_bcc (code, ARMCOND_EQ, 0);
4219 for (i = 0; i < 8; ++i)
4220 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4221 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4225 case OP_GENERIC_CLASS_INIT: {
4229 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
4231 /* Load vtable->initialized */
4232 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4234 arm_cbnzx (code, ARMREG_IP0, 0);
4237 g_assert (sreg1 == ARMREG_R0);
4238 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4239 (gpointer)"mono_generic_class_init");
4241 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4246 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4249 case OP_NOT_REACHED:
4252 case OP_IL_SEQ_POINT:
4253 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4258 case OP_COND_EXC_IC:
4259 case OP_COND_EXC_OV:
4260 case OP_COND_EXC_IOV:
4261 case OP_COND_EXC_NC:
4262 case OP_COND_EXC_INC:
4263 case OP_COND_EXC_NO:
4264 case OP_COND_EXC_INO:
4265 case OP_COND_EXC_EQ:
4266 case OP_COND_EXC_IEQ:
4267 case OP_COND_EXC_NE_UN:
4268 case OP_COND_EXC_INE_UN:
4269 case OP_COND_EXC_ILT:
4270 case OP_COND_EXC_LT:
4271 case OP_COND_EXC_ILT_UN:
4272 case OP_COND_EXC_LT_UN:
4273 case OP_COND_EXC_IGT:
4274 case OP_COND_EXC_GT:
4275 case OP_COND_EXC_IGT_UN:
4276 case OP_COND_EXC_GT_UN:
4277 case OP_COND_EXC_IGE:
4278 case OP_COND_EXC_GE:
4279 case OP_COND_EXC_IGE_UN:
4280 case OP_COND_EXC_GE_UN:
4281 case OP_COND_EXC_ILE:
4282 case OP_COND_EXC_LE:
4283 case OP_COND_EXC_ILE_UN:
4284 case OP_COND_EXC_LE_UN:
4285 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4288 if (sreg1 != ARMREG_R0)
4289 arm_movx (code, ARMREG_R0, sreg1);
4290 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4291 (gpointer)"mono_arch_throw_exception");
4294 if (sreg1 != ARMREG_R0)
4295 arm_movx (code, ARMREG_R0, sreg1);
4296 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4297 (gpointer)"mono_arch_rethrow_exception");
4299 case OP_CALL_HANDLER:
4300 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4302 cfg->thunk_area += THUNK_SIZE;
4303 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4305 case OP_START_HANDLER: {
4306 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4308 /* Save caller address */
4309 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4312 * Reserve a param area, see test_0_finally_param_area ().
4313 * This is needed because the param area is not set up when
4314 * we are called from EH code.
4316 if (cfg->param_area)
4317 code = emit_subx_sp_imm (code, cfg->param_area);
4321 case OP_ENDFILTER: {
4322 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4324 if (cfg->param_area)
4325 code = emit_addx_sp_imm (code, cfg->param_area);
4327 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4328 arm_movx (code, ARMREG_R0, sreg1);
4330 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4331 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4332 arm_brx (code, ARMREG_LR);
4336 if (ins->dreg != ARMREG_R0)
4337 arm_movx (code, ins->dreg, ARMREG_R0);
4339 case OP_GC_SAFE_POINT: {
4340 #if defined (USE_COOP_GC)
4343 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4344 /* Call it if it is non-null */
4346 arm_cbzx (code, ARMREG_IP1, 0);
4347 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4348 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4354 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4355 g_assert_not_reached ();
4358 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4359 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4360 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4361 g_assert_not_reached ();
4366 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4367 * insert branch islands between/inside basic blocks.
4369 if (cfg->arch.cond_branch_islands)
4370 code = emit_branch_island (cfg, code, start_offset);
4372 cfg->code_len = code - cfg->native_code;
4376 emit_move_args (MonoCompile *cfg, guint8 *code)
4383 cinfo = cfg->arch.cinfo;
4385 for (i = 0; i < cinfo->nargs; ++i) {
4386 ainfo = cinfo->args + i;
4387 ins = cfg->args [i];
4389 if (ins->opcode == OP_REGVAR) {
4390 switch (ainfo->storage) {
4392 arm_movx (code, ins->dreg, ainfo->reg);
4395 switch (ainfo->slot_size) {
4398 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4400 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4404 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4406 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4410 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4412 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4415 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4420 g_assert_not_reached ();
4424 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4425 g_assert (ins->opcode == OP_REGOFFSET);
4427 switch (ainfo->storage) {
4429 /* Stack slots for arguments have size 8 */
4430 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4433 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4436 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4441 case ArgVtypeByRefOnStack:
4442 case ArgVtypeOnStack:
4444 case ArgVtypeByRef: {
4445 MonoInst *addr_arg = ins->inst_left;
4447 if (ainfo->gsharedvt) {
4448 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4449 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4451 g_assert (ins->opcode == OP_VTARG_ADDR);
4452 g_assert (addr_arg->opcode == OP_REGOFFSET);
4453 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4457 case ArgVtypeInIRegs:
4458 for (part = 0; part < ainfo->nregs; part ++) {
4459 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4463 for (part = 0; part < ainfo->nregs; part ++) {
4464 if (ainfo->esize == 4)
4465 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4467 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4471 g_assert_not_reached ();
4481 * emit_store_regarray:
4483 * Emit code to store the registers in REGS into the appropriate elements of
4484 * the register array at BASEREG+OFFSET.
4486 static __attribute__ ((__warn_unused_result__)) guint8*
4487 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4491 for (i = 0; i < 32; ++i) {
4492 if (regs & (1 << i)) {
4493 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4494 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4496 } else if (i == ARMREG_SP) {
4497 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4498 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4500 arm_strx (code, i, basereg, offset + (i * 8));
4508 * emit_load_regarray:
4510 * Emit code to load the registers in REGS from the appropriate elements of
4511 * the register array at BASEREG+OFFSET.
4513 static __attribute__ ((__warn_unused_result__)) guint8*
4514 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4518 for (i = 0; i < 32; ++i) {
4519 if (regs & (1 << i)) {
4520 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4521 if (offset + (i * 8) < 500)
4522 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4524 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4525 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4528 } else if (i == ARMREG_SP) {
4529 g_assert_not_reached ();
4531 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4539 * emit_store_regset:
4541 * Emit code to store the registers in REGS into consecutive memory locations starting
4542 * at BASEREG+OFFSET.
4544 static __attribute__ ((__warn_unused_result__)) guint8*
4545 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4550 for (i = 0; i < 32; ++i) {
4551 if (regs & (1 << i)) {
4552 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4553 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4556 } else if (i == ARMREG_SP) {
4557 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4558 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4560 arm_strx (code, i, basereg, offset + (pos * 8));
4571 * Emit code to load the registers in REGS from consecutive memory locations starting
4572 * at BASEREG+OFFSET.
4574 static __attribute__ ((__warn_unused_result__)) guint8*
4575 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4580 for (i = 0; i < 32; ++i) {
4581 if (regs & (1 << i)) {
4582 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4583 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4586 } else if (i == ARMREG_SP) {
4587 g_assert_not_reached ();
4589 arm_ldrx (code, i, basereg, offset + (pos * 8));
4597 __attribute__ ((__warn_unused_result__)) guint8*
4598 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4600 return emit_load_regarray (code, regs, basereg, offset);
4603 __attribute__ ((__warn_unused_result__)) guint8*
4604 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4606 return emit_store_regarray (code, regs, basereg, offset);
4609 __attribute__ ((__warn_unused_result__)) guint8*
4610 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4612 return emit_store_regset (code, regs, basereg, offset);
4615 /* Same as emit_store_regset, but emit unwind info too */
4616 /* CFA_OFFSET is the offset between the CFA and basereg */
4617 static __attribute__ ((__warn_unused_result__)) guint8*
4618 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4620 int i, j, pos, nregs;
4621 guint32 cfa_regset = regs & ~no_cfa_regset;
4624 for (i = 0; i < 32; ++i) {
4626 if (regs & (1 << i)) {
4627 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4629 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4631 code = emit_strx (code, i, basereg, offset + (pos * 8));
4632 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4635 } else if (i == ARMREG_SP) {
4636 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4637 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4639 code = emit_strx (code, i, basereg, offset + (pos * 8));
4642 for (j = 0; j < nregs; ++j) {
4643 if (cfa_regset & (1 << (i + j)))
4644 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4657 * Emit code to initialize an LMF structure at LMF_OFFSET.
4661 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4664 * The LMF should contain all the state required to be able to reconstruct the machine state
4665 * at the current point of execution. Since the LMF is only read during EH, only callee
4666 * saved etc. registers need to be saved.
4667 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4668 * need to be restored during EH.
4672 arm_adrx (code, ARMREG_LR, code);
4673 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4674 /* gregs + fp + sp */
4675 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4676 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4682 mono_arch_emit_prolog (MonoCompile *cfg)
4684 MonoMethod *method = cfg->method;
4685 MonoMethodSignature *sig;
4688 int cfa_offset, max_offset;
4690 sig = mono_method_signature (method);
4691 cfg->code_size = 256 + sig->param_count * 64;
4692 code = cfg->native_code = g_malloc (cfg->code_size);
4694 /* This can be unaligned */
4695 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4701 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4704 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4705 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4707 /* sp -= cfg->stack_offset */
4708 /* This clobbers ip0/ip1 */
4709 code = emit_subx_sp_imm (code, cfg->stack_offset);
4710 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4712 cfa_offset += cfg->stack_offset;
4713 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4714 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4715 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4716 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4717 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4718 if (cfg->param_area) {
4719 /* The param area is below the frame pointer */
4720 code = emit_subx_sp_imm (code, cfg->param_area);
4723 if (cfg->method->save_lmf) {
4724 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4727 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4730 /* Setup args reg */
4731 if (cfg->arch.args_reg) {
4732 /* The register was already saved above */
4733 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4736 /* Save return area addr received in R8 */
4737 if (cfg->vret_addr) {
4738 MonoInst *ins = cfg->vret_addr;
4740 g_assert (ins->opcode == OP_REGOFFSET);
4741 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4744 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4745 if (cfg->rgctx_var) {
4746 MonoInst *ins = cfg->rgctx_var;
4748 g_assert (ins->opcode == OP_REGOFFSET);
4750 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4754 * Move arguments to their registers/stack locations.
4756 code = emit_move_args (cfg, code);
4758 /* Initialize seq_point_info_var */
4759 if (cfg->arch.seq_point_info_var) {
4760 MonoInst *ins = cfg->arch.seq_point_info_var;
4762 /* Initialize the variable from a GOT slot */
4763 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4764 g_assert (ins->opcode == OP_REGOFFSET);
4765 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4767 /* Initialize ss_tramp_var */
4768 ins = cfg->arch.ss_tramp_var;
4769 g_assert (ins->opcode == OP_REGOFFSET);
4771 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4772 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4776 if (cfg->arch.ss_tramp_var) {
4777 /* Initialize ss_tramp_var */
4778 ins = cfg->arch.ss_tramp_var;
4779 g_assert (ins->opcode == OP_REGOFFSET);
4781 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4782 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4785 if (cfg->arch.bp_tramp_var) {
4786 /* Initialize bp_tramp_var */
4787 ins = cfg->arch.bp_tramp_var;
4788 g_assert (ins->opcode == OP_REGOFFSET);
4790 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4791 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4796 if (cfg->opt & MONO_OPT_BRANCH) {
4797 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4799 bb->max_offset = max_offset;
4801 MONO_BB_FOR_EACH_INS (bb, ins) {
4802 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4806 if (max_offset > 0x3ffff * 4)
4807 cfg->arch.cond_branch_islands = TRUE;
4813 realloc_code (MonoCompile *cfg, int size)
4815 while (cfg->code_len + size > (cfg->code_size - 16)) {
4816 cfg->code_size *= 2;
4817 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4818 cfg->stat_code_reallocs++;
4820 return cfg->native_code + cfg->code_len;
4824 mono_arch_emit_epilog (MonoCompile *cfg)
4827 int max_epilog_size;
4831 max_epilog_size = 16 + 20*4;
4832 code = realloc_code (cfg, max_epilog_size);
4834 if (cfg->method->save_lmf) {
4835 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4838 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4841 /* Load returned vtypes into registers if needed */
4842 cinfo = cfg->arch.cinfo;
4843 switch (cinfo->ret.storage) {
4844 case ArgVtypeInIRegs: {
4845 MonoInst *ins = cfg->ret;
4847 for (i = 0; i < cinfo->ret.nregs; ++i)
4848 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4852 MonoInst *ins = cfg->ret;
4854 for (i = 0; i < cinfo->ret.nregs; ++i) {
4855 if (cinfo->ret.esize == 4)
4856 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4858 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4867 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4869 arm_retx (code, ARMREG_LR);
4871 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4873 cfg->code_len = code - cfg->native_code;
4877 mono_arch_emit_exceptions (MonoCompile *cfg)
4880 MonoClass *exc_class;
4882 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4883 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4884 int i, id, size = 0;
4886 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4887 exc_throw_pos [i] = NULL;
4888 exc_throw_found [i] = 0;
4891 for (ji = cfg->patch_info; ji; ji = ji->next) {
4892 if (ji->type == MONO_PATCH_INFO_EXC) {
4893 i = mini_exception_id_by_name (ji->data.target);
4894 if (!exc_throw_found [i]) {
4896 exc_throw_found [i] = TRUE;
4901 code = realloc_code (cfg, size);
4903 /* Emit code to raise corlib exceptions */
4904 for (ji = cfg->patch_info; ji; ji = ji->next) {
4905 if (ji->type != MONO_PATCH_INFO_EXC)
4908 ip = cfg->native_code + ji->ip.i;
4910 id = mini_exception_id_by_name (ji->data.target);
4912 if (exc_throw_pos [id]) {
4913 /* ip points to the bcc () in OP_COND_EXC_... */
4914 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4915 ji->type = MONO_PATCH_INFO_NONE;
4919 exc_throw_pos [id] = code;
4920 arm_patch_rel (ip, code, ji->relocation);
4922 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4924 /* r0 = type token */
4925 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4926 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4928 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4929 /* Branch to the corlib exception throwing trampoline */
4930 ji->ip.i = code - cfg->native_code;
4931 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4932 ji->data.name = "mono_arch_throw_corlib_exception";
4933 ji->relocation = MONO_R_ARM64_BL;
4935 cfg->thunk_area += THUNK_SIZE;
4938 cfg->code_len = code - cfg->native_code;
4940 g_assert (cfg->code_len < cfg->code_size);
4944 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4950 mono_arch_print_tree (MonoInst *tree, int arity)
4956 mono_arch_get_patch_offset (guint8 *code)
4962 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4963 gpointer fail_tramp)
4965 int i, buf_len, imt_reg;
4969 printf ("building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4970 for (i = 0; i < count; ++i) {
4971 MonoIMTCheckItem *item = imt_entries [i];
4972 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
4977 for (i = 0; i < count; ++i) {
4978 MonoIMTCheckItem *item = imt_entries [i];
4979 if (item->is_equals) {
4980 gboolean fail_case = !item->check_target_idx && fail_tramp;
4982 if (item->check_target_idx || fail_case) {
4983 if (!item->compare_done || fail_case) {
4984 buf_len += 4 * 4 + 4;
4987 if (item->has_target_code) {
5004 buf = mono_method_alloc_generic_virtual_trampoline (domain, buf_len);
5006 buf = mono_domain_code_reserve (domain, buf_len);
5010 * We are called by JITted code, which passes in the IMT argument in
5011 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
5014 imt_reg = MONO_ARCH_RGCTX_REG;
5015 for (i = 0; i < count; ++i) {
5016 MonoIMTCheckItem *item = imt_entries [i];
5018 item->code_target = code;
5020 if (item->is_equals) {
5022 * Check the imt argument against item->key, if equals, jump to either
5023 * item->value.target_code or to vtable [item->value.vtable_slot].
5024 * If fail_tramp is set, jump to it if not-equals.
5026 gboolean fail_case = !item->check_target_idx && fail_tramp;
5028 if (item->check_target_idx || fail_case) {
5029 /* Compare imt_reg with item->key */
5030 if (!item->compare_done || fail_case) {
5031 // FIXME: Optimize this
5032 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5033 arm_cmpx (code, imt_reg, ARMREG_IP0);
5035 item->jmp_code = code;
5036 arm_bcc (code, ARMCOND_NE, 0);
5037 /* Jump to target if equals */
5038 if (item->has_target_code) {
5039 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
5040 arm_brx (code, ARMREG_IP0);
5042 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5044 code = emit_imm64 (code, ARMREG_IP0, imm);
5045 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5046 arm_brx (code, ARMREG_IP0);
5050 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5051 item->jmp_code = NULL;
5052 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5053 arm_brx (code, ARMREG_IP0);
5056 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5058 code = emit_imm64 (code, ARMREG_IP0, imm);
5059 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5060 arm_brx (code, ARMREG_IP0);
5063 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5064 arm_cmpx (code, imt_reg, ARMREG_IP0);
5065 item->jmp_code = code;
5066 arm_bcc (code, ARMCOND_HS, 0);
5069 /* Patch the branches */
5070 for (i = 0; i < count; ++i) {
5071 MonoIMTCheckItem *item = imt_entries [i];
5072 if (item->jmp_code && item->check_target_idx)
5073 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5076 g_assert ((code - buf) < buf_len);
5078 mono_arch_flush_icache (buf, code - buf);
5084 mono_arch_get_trampolines (gboolean aot)
5086 return mono_arm_get_exception_trampolines (aot);
5089 #else /* DISABLE_JIT */
5092 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5093 gpointer fail_tramp)
5095 g_assert_not_reached ();
5099 #endif /* !DISABLE_JIT */
5101 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5104 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5107 guint32 native_offset = ip - (guint8*)ji->code_start;
5110 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5112 g_assert (native_offset % 4 == 0);
5113 g_assert (info->bp_addrs [native_offset / 4] == 0);
5114 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5116 /* ip points to an ldrx */
5118 arm_blrx (code, ARMREG_IP0);
5119 mono_arch_flush_icache (ip, code - ip);
5124 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5129 guint32 native_offset = ip - (guint8*)ji->code_start;
5130 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5132 g_assert (native_offset % 4 == 0);
5133 info->bp_addrs [native_offset / 4] = NULL;
5135 /* ip points to an ldrx */
5138 mono_arch_flush_icache (ip, code - ip);
5143 mono_arch_start_single_stepping (void)
5145 ss_trampoline = mini_get_single_step_trampoline ();
5149 mono_arch_stop_single_stepping (void)
5151 ss_trampoline = NULL;
5155 mono_arch_is_single_step_event (void *info, void *sigctx)
5157 /* We use soft breakpoints on arm64 */
5162 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5164 /* We use soft breakpoints on arm64 */
5169 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5171 g_assert_not_reached ();
5175 mono_arch_skip_single_step (MonoContext *ctx)
5177 g_assert_not_reached ();
5181 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5186 // FIXME: Add a free function
5188 mono_domain_lock (domain);
5189 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5191 mono_domain_unlock (domain);
5194 ji = mono_jit_info_table_find (domain, (char*)code);
5197 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5199 info->ss_tramp_addr = &ss_trampoline;
5201 mono_domain_lock (domain);
5202 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5204 mono_domain_unlock (domain);
5211 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5213 ext->lmf.previous_lmf = prev_lmf;
5214 /* Mark that this is a MonoLMFExt */
5215 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5216 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5219 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5222 mono_arch_opcode_supported (int opcode)
5225 case OP_ATOMIC_ADD_I4:
5226 case OP_ATOMIC_ADD_I8:
5227 case OP_ATOMIC_EXCHANGE_I4:
5228 case OP_ATOMIC_EXCHANGE_I8:
5229 case OP_ATOMIC_CAS_I4:
5230 case OP_ATOMIC_CAS_I8:
5231 case OP_ATOMIC_LOAD_I1:
5232 case OP_ATOMIC_LOAD_I2:
5233 case OP_ATOMIC_LOAD_I4:
5234 case OP_ATOMIC_LOAD_I8:
5235 case OP_ATOMIC_LOAD_U1:
5236 case OP_ATOMIC_LOAD_U2:
5237 case OP_ATOMIC_LOAD_U4:
5238 case OP_ATOMIC_LOAD_U8:
5239 case OP_ATOMIC_LOAD_R4:
5240 case OP_ATOMIC_LOAD_R8:
5241 case OP_ATOMIC_STORE_I1:
5242 case OP_ATOMIC_STORE_I2:
5243 case OP_ATOMIC_STORE_I4:
5244 case OP_ATOMIC_STORE_I8:
5245 case OP_ATOMIC_STORE_U1:
5246 case OP_ATOMIC_STORE_U2:
5247 case OP_ATOMIC_STORE_U4:
5248 case OP_ATOMIC_STORE_U8:
5249 case OP_ATOMIC_STORE_R4:
5250 case OP_ATOMIC_STORE_R8:
5258 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5260 return get_call_info (mp, sig);
5264 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
5271 bp = MONO_CONTEXT_GET_BP (ctx);
5272 lr_loc = (gpointer*)(bp + clause->exvar_offset);
5274 old_value = *lr_loc;
5275 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
5278 *lr_loc = new_value;