2 * mini-arm64.c: ARM64 backend for the Mono code generator
4 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
9 * Paolo Molaro (lupus@ximian.com)
10 * Dietmar Maurer (dietmar@ximian.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
19 #include "cpu-arm64.h"
22 #include <mono/arch/arm64/arm64-codegen.h>
23 #include <mono/utils/mono-mmap.h>
24 #include <mono/utils/mono-memory-model.h>
25 #include <mono/metadata/abi-details.h>
30 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
31 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
32 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
35 * - ip0/ip1/lr are used as temporary registers
36 * - r27 is used as the rgctx/imt register
37 * - r28 is used to access arguments passed on the stack
38 * - d15/d16 are used as fp temporary registers
41 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
43 #define FP_TEMP_REG ARMREG_D16
44 #define FP_TEMP_REG2 ARMREG_D17
46 #define THUNK_SIZE (4 * 4)
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 static gboolean ios_abi;
56 static __attribute__((warn_unused_result)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
59 mono_arch_regname (int reg)
61 static const char * rnames[] = {
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
63 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
64 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
67 if (reg >= 0 && reg < 32)
73 mono_arch_fregname (int reg)
75 static const char * rnames[] = {
76 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
77 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
78 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
81 if (reg >= 0 && reg < 32)
87 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
93 #define MAX_ARCH_DELEGATE_PARAMS 7
96 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
101 start = code = mono_global_codeman_reserve (12);
103 /* Replace the this argument with the target */
104 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
105 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
106 arm_brx (code, ARMREG_IP0);
108 g_assert ((code - start) <= 12);
110 mono_arch_flush_icache (start, 12);
114 size = 8 + param_count * 4;
115 start = code = mono_global_codeman_reserve (size);
117 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
118 /* slide down the arguments */
119 for (i = 0; i < param_count; ++i)
120 arm_movx (code, i, i + 1);
121 arm_brx (code, ARMREG_IP0);
123 g_assert ((code - start) <= size);
125 mono_arch_flush_icache (start, size);
129 *code_size = code - start;
135 * mono_arch_get_delegate_invoke_impls:
137 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
141 mono_arch_get_delegate_invoke_impls (void)
149 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
150 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
152 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
153 code = get_delegate_invoke_impl (FALSE, i, &code_len);
154 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
155 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
165 guint8 *code, *start;
168 * vtypes are returned in registers, or using the dedicated r8 register, so
169 * they can be supported by delegate invokes.
173 static guint8* cached = NULL;
179 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
181 start = get_delegate_invoke_impl (TRUE, 0, NULL);
182 mono_memory_barrier ();
186 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
189 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
191 for (i = 0; i < sig->param_count; ++i)
192 if (!mono_is_regsize_var (sig->params [i]))
195 code = cache [sig->param_count];
200 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
201 start = mono_aot_get_trampoline (name);
204 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
206 mono_memory_barrier ();
207 cache [sig->param_count] = start;
215 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
221 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
223 return (gpointer)regs [ARMREG_R0];
227 mono_arch_cpu_init (void)
232 mono_arch_init (void)
234 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
235 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
238 bp_trampoline = mini_get_breakpoint_trampoline ();
240 mono_arm_gsharedvt_init ();
242 #if defined(TARGET_IOS)
248 mono_arch_cleanup (void)
253 mono_arch_cpu_optimizations (guint32 *exclude_mask)
260 mono_arch_cpu_enumerate_simd_versions (void)
266 mono_arch_register_lowlevel_calls (void)
271 mono_arch_finish_init (void)
275 /* The maximum length is 2 instructions */
277 emit_imm (guint8 *code, int dreg, int imm)
279 // FIXME: Optimize this
282 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
283 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
285 arm_movzx (code, dreg, imm & 0xffff, 0);
287 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
293 /* The maximum length is 4 instructions */
295 emit_imm64 (guint8 *code, int dreg, guint64 imm)
297 // FIXME: Optimize this
298 arm_movzx (code, dreg, imm & 0xffff, 0);
299 if ((imm >> 16) & 0xffff)
300 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
301 if ((imm >> 32) & 0xffff)
302 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
303 if ((imm >> 48) & 0xffff)
304 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
310 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
312 return emit_imm64 (code, dreg, imm);
318 * Emit a patchable code sequence for constructing a 64 bit immediate.
321 emit_imm64_template (guint8 *code, int dreg)
323 arm_movzx (code, dreg, 0, 0);
324 arm_movkx (code, dreg, 0, 16);
325 arm_movkx (code, dreg, 0, 32);
326 arm_movkx (code, dreg, 0, 48);
331 static inline __attribute__((warn_unused_result)) guint8*
332 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
334 if (!arm_is_arith_imm (imm)) {
335 code = emit_imm (code, ARMREG_LR, imm);
336 arm_addw (code, dreg, sreg, ARMREG_LR);
338 arm_addw_imm (code, dreg, sreg, imm);
343 static inline __attribute__((warn_unused_result)) guint8*
344 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
346 if (!arm_is_arith_imm (imm)) {
347 code = emit_imm (code, ARMREG_LR, imm);
348 arm_addx (code, dreg, sreg, ARMREG_LR);
350 arm_addx_imm (code, dreg, sreg, imm);
355 static inline __attribute__((warn_unused_result)) guint8*
356 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
358 if (!arm_is_arith_imm (imm)) {
359 code = emit_imm (code, ARMREG_LR, imm);
360 arm_subw (code, dreg, sreg, ARMREG_LR);
362 arm_subw_imm (code, dreg, sreg, imm);
367 static inline __attribute__((warn_unused_result)) guint8*
368 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
370 if (!arm_is_arith_imm (imm)) {
371 code = emit_imm (code, ARMREG_LR, imm);
372 arm_subx (code, dreg, sreg, ARMREG_LR);
374 arm_subx_imm (code, dreg, sreg, imm);
379 /* Emit sp+=imm. Clobbers ip0/ip1 */
380 static inline __attribute__((warn_unused_result)) guint8*
381 emit_addx_sp_imm (guint8 *code, int imm)
383 code = emit_imm (code, ARMREG_IP0, imm);
384 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
385 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
386 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
390 /* Emit sp-=imm. Clobbers ip0/ip1 */
391 static inline __attribute__((warn_unused_result)) guint8*
392 emit_subx_sp_imm (guint8 *code, int imm)
394 code = emit_imm (code, ARMREG_IP0, imm);
395 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
396 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
397 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
401 static inline __attribute__((warn_unused_result)) guint8*
402 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
405 code = emit_imm (code, ARMREG_LR, imm);
406 arm_andw (code, dreg, sreg, ARMREG_LR);
411 static inline __attribute__((warn_unused_result)) guint8*
412 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
415 code = emit_imm (code, ARMREG_LR, imm);
416 arm_andx (code, dreg, sreg, ARMREG_LR);
421 static inline __attribute__((warn_unused_result)) guint8*
422 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
425 code = emit_imm (code, ARMREG_LR, imm);
426 arm_orrw (code, dreg, sreg, ARMREG_LR);
431 static inline __attribute__((warn_unused_result)) guint8*
432 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
435 code = emit_imm (code, ARMREG_LR, imm);
436 arm_orrx (code, dreg, sreg, ARMREG_LR);
441 static inline __attribute__((warn_unused_result)) guint8*
442 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
445 code = emit_imm (code, ARMREG_LR, imm);
446 arm_eorw (code, dreg, sreg, ARMREG_LR);
451 static inline __attribute__((warn_unused_result)) guint8*
452 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
455 code = emit_imm (code, ARMREG_LR, imm);
456 arm_eorx (code, dreg, sreg, ARMREG_LR);
461 static inline __attribute__((warn_unused_result)) guint8*
462 emit_cmpw_imm (guint8 *code, int sreg, int imm)
465 arm_cmpw (code, sreg, ARMREG_RZR);
468 code = emit_imm (code, ARMREG_LR, imm);
469 arm_cmpw (code, sreg, ARMREG_LR);
475 static inline __attribute__((warn_unused_result)) guint8*
476 emit_cmpx_imm (guint8 *code, int sreg, int imm)
479 arm_cmpx (code, sreg, ARMREG_RZR);
482 code = emit_imm (code, ARMREG_LR, imm);
483 arm_cmpx (code, sreg, ARMREG_LR);
489 static inline __attribute__((warn_unused_result)) guint8*
490 emit_strb (guint8 *code, int rt, int rn, int imm)
492 if (arm_is_strb_imm (imm)) {
493 arm_strb (code, rt, rn, imm);
495 g_assert (rt != ARMREG_IP0);
496 g_assert (rn != ARMREG_IP0);
497 code = emit_imm (code, ARMREG_IP0, imm);
498 arm_strb_reg (code, rt, rn, ARMREG_IP0);
503 static inline __attribute__((warn_unused_result)) guint8*
504 emit_strh (guint8 *code, int rt, int rn, int imm)
506 if (arm_is_strh_imm (imm)) {
507 arm_strh (code, rt, rn, imm);
509 g_assert (rt != ARMREG_IP0);
510 g_assert (rn != ARMREG_IP0);
511 code = emit_imm (code, ARMREG_IP0, imm);
512 arm_strh_reg (code, rt, rn, ARMREG_IP0);
517 static inline __attribute__((warn_unused_result)) guint8*
518 emit_strw (guint8 *code, int rt, int rn, int imm)
520 if (arm_is_strw_imm (imm)) {
521 arm_strw (code, rt, rn, imm);
523 g_assert (rt != ARMREG_IP0);
524 g_assert (rn != ARMREG_IP0);
525 code = emit_imm (code, ARMREG_IP0, imm);
526 arm_strw_reg (code, rt, rn, ARMREG_IP0);
531 static inline __attribute__((warn_unused_result)) guint8*
532 emit_strfpw (guint8 *code, int rt, int rn, int imm)
534 if (arm_is_strw_imm (imm)) {
535 arm_strfpw (code, rt, rn, imm);
537 g_assert (rn != ARMREG_IP0);
538 code = emit_imm (code, ARMREG_IP0, imm);
539 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
540 arm_strfpw (code, rt, ARMREG_IP0, 0);
545 static inline __attribute__((warn_unused_result)) guint8*
546 emit_strfpx (guint8 *code, int rt, int rn, int imm)
548 if (arm_is_strx_imm (imm)) {
549 arm_strfpx (code, rt, rn, imm);
551 g_assert (rn != ARMREG_IP0);
552 code = emit_imm (code, ARMREG_IP0, imm);
553 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
554 arm_strfpx (code, rt, ARMREG_IP0, 0);
559 static inline __attribute__((warn_unused_result)) guint8*
560 emit_strx (guint8 *code, int rt, int rn, int imm)
562 if (arm_is_strx_imm (imm)) {
563 arm_strx (code, rt, rn, imm);
565 g_assert (rt != ARMREG_IP0);
566 g_assert (rn != ARMREG_IP0);
567 code = emit_imm (code, ARMREG_IP0, imm);
568 arm_strx_reg (code, rt, rn, ARMREG_IP0);
573 static inline __attribute__((warn_unused_result)) guint8*
574 emit_ldrb (guint8 *code, int rt, int rn, int imm)
576 if (arm_is_pimm12_scaled (imm, 1)) {
577 arm_ldrb (code, rt, rn, imm);
579 g_assert (rt != ARMREG_IP0);
580 g_assert (rn != ARMREG_IP0);
581 code = emit_imm (code, ARMREG_IP0, imm);
582 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
587 static inline __attribute__((warn_unused_result)) guint8*
588 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
590 if (arm_is_pimm12_scaled (imm, 1)) {
591 arm_ldrsbx (code, rt, rn, imm);
593 g_assert (rt != ARMREG_IP0);
594 g_assert (rn != ARMREG_IP0);
595 code = emit_imm (code, ARMREG_IP0, imm);
596 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
601 static inline __attribute__((warn_unused_result)) guint8*
602 emit_ldrh (guint8 *code, int rt, int rn, int imm)
604 if (arm_is_pimm12_scaled (imm, 2)) {
605 arm_ldrh (code, rt, rn, imm);
607 g_assert (rt != ARMREG_IP0);
608 g_assert (rn != ARMREG_IP0);
609 code = emit_imm (code, ARMREG_IP0, imm);
610 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
615 static inline __attribute__((warn_unused_result)) guint8*
616 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
618 if (arm_is_pimm12_scaled (imm, 2)) {
619 arm_ldrshx (code, rt, rn, imm);
621 g_assert (rt != ARMREG_IP0);
622 g_assert (rn != ARMREG_IP0);
623 code = emit_imm (code, ARMREG_IP0, imm);
624 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
629 static inline __attribute__((warn_unused_result)) guint8*
630 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
632 if (arm_is_pimm12_scaled (imm, 4)) {
633 arm_ldrswx (code, rt, rn, imm);
635 g_assert (rt != ARMREG_IP0);
636 g_assert (rn != ARMREG_IP0);
637 code = emit_imm (code, ARMREG_IP0, imm);
638 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
643 static inline __attribute__((warn_unused_result)) guint8*
644 emit_ldrw (guint8 *code, int rt, int rn, int imm)
646 if (arm_is_pimm12_scaled (imm, 4)) {
647 arm_ldrw (code, rt, rn, imm);
649 g_assert (rn != ARMREG_IP0);
650 code = emit_imm (code, ARMREG_IP0, imm);
651 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
656 static inline __attribute__((warn_unused_result)) guint8*
657 emit_ldrx (guint8 *code, int rt, int rn, int imm)
659 if (arm_is_pimm12_scaled (imm, 8)) {
660 arm_ldrx (code, rt, rn, imm);
662 g_assert (rn != ARMREG_IP0);
663 code = emit_imm (code, ARMREG_IP0, imm);
664 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
669 static inline __attribute__((warn_unused_result)) guint8*
670 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
672 if (arm_is_pimm12_scaled (imm, 4)) {
673 arm_ldrfpw (code, rt, rn, imm);
675 g_assert (rn != ARMREG_IP0);
676 code = emit_imm (code, ARMREG_IP0, imm);
677 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
678 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
683 static inline __attribute__((warn_unused_result)) guint8*
684 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
686 if (arm_is_pimm12_scaled (imm, 8)) {
687 arm_ldrfpx (code, rt, rn, imm);
689 g_assert (rn != ARMREG_IP0);
690 code = emit_imm (code, ARMREG_IP0, imm);
691 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
692 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
698 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
700 return emit_ldrx (code, rt, rn, imm);
704 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
707 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
708 code = emit_imm64_template (code, ARMREG_LR);
709 arm_blrx (code, ARMREG_LR);
711 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
713 cfg->thunk_area += THUNK_SIZE;
718 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
721 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
723 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
724 /* See arch_emit_got_access () in aot-compiler.c */
725 arm_ldrx_lit (code, dreg, 0);
732 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
734 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
738 * mono_arm_emit_aotconst:
740 * Emit code to load an AOT constant into DREG. Usable from trampolines.
743 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
745 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
749 emit_tls_get (guint8 *code, int dreg, int tls_offset)
751 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
752 if (tls_offset < 256) {
753 arm_ldrx (code, dreg, dreg, tls_offset);
755 code = emit_addx_imm (code, dreg, dreg, tls_offset);
756 arm_ldrx (code, dreg, dreg, 0);
762 emit_tls_get_reg (guint8 *code, int dreg, int offset_reg)
764 g_assert (offset_reg != ARMREG_IP0);
765 arm_mrs (code, ARMREG_IP0, ARM_MRS_REG_TPIDR_EL0);
766 arm_ldrx_reg (code, dreg, ARMREG_IP0, offset_reg);
771 emit_tls_set (guint8 *code, int sreg, int tls_offset)
773 int tmpreg = ARMREG_IP0;
775 g_assert (sreg != tmpreg);
776 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
777 if (tls_offset < 256) {
778 arm_strx (code, sreg, tmpreg, tls_offset);
780 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
781 arm_strx (code, sreg, tmpreg, 0);
788 emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
790 int tmpreg = ARMREG_IP0;
792 g_assert (sreg != tmpreg);
793 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
794 arm_strx_reg (code, sreg, tmpreg, offset_reg);
801 * - ldrp [fp, lr], [sp], !stack_offfset
802 * Clobbers TEMP_REGS.
804 __attribute__((warn_unused_result)) guint8*
805 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
807 arm_movspx (code, ARMREG_SP, ARMREG_FP);
809 if (arm_is_ldpx_imm (stack_offset)) {
810 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
812 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
813 /* sp += stack_offset */
814 g_assert (temp_regs & (1 << ARMREG_IP0));
815 if (temp_regs & (1 << ARMREG_IP1)) {
816 code = emit_addx_sp_imm (code, stack_offset);
818 int imm = stack_offset;
820 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
821 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
823 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
826 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
832 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
835 emit_thunk (guint8 *code, gconstpointer target)
839 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
840 arm_brx (code, ARMREG_IP0);
841 *(guint64*)code = (guint64)target;
842 code += sizeof (guint64);
844 mono_arch_flush_icache (p, code - p);
849 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
852 MonoThunkJitInfo *info;
856 guint8 *target_thunk;
859 domain = mono_domain_get ();
863 * This can be called multiple times during JITting,
864 * save the current position in cfg->arch to avoid
865 * doing a O(n^2) search.
867 if (!cfg->arch.thunks) {
868 cfg->arch.thunks = cfg->thunks;
869 cfg->arch.thunks_size = cfg->thunk_area;
871 thunks = cfg->arch.thunks;
872 thunks_size = cfg->arch.thunks_size;
874 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
875 g_assert_not_reached ();
878 g_assert (*(guint32*)thunks == 0);
879 emit_thunk (thunks, target);
881 cfg->arch.thunks += THUNK_SIZE;
882 cfg->arch.thunks_size -= THUNK_SIZE;
886 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
888 info = mono_jit_info_get_thunk_info (ji);
891 thunks = (guint8*)ji->code_start + info->thunks_offset;
892 thunks_size = info->thunks_size;
894 orig_target = mono_arch_get_call_target (code + 4);
896 mono_domain_lock (domain);
899 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
900 /* The call already points to a thunk, because of trampolines etc. */
901 target_thunk = orig_target;
903 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
904 if (((guint32*)p) [0] == 0) {
908 } else if (((guint64*)p) [1] == (guint64)target) {
909 /* Thunk already points to target */
916 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
919 mono_domain_unlock (domain);
920 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
921 g_assert_not_reached ();
924 emit_thunk (target_thunk, target);
926 mono_domain_unlock (domain);
933 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
935 switch (relocation) {
937 arm_b (code, target);
939 case MONO_R_ARM64_BCC: {
942 cond = arm_get_bcc_cond (code);
943 arm_bcc (code, cond, target);
946 case MONO_R_ARM64_CBZ:
947 arm_set_cbz_target (code, target);
949 case MONO_R_ARM64_IMM: {
950 guint64 imm = (guint64)target;
953 /* emit_imm64_template () */
954 dreg = arm_get_movzx_rd (code);
955 arm_movzx (code, dreg, imm & 0xffff, 0);
956 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
957 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
958 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
961 case MONO_R_ARM64_BL:
962 if (arm_is_bl_disp (code, target)) {
963 arm_bl (code, target);
967 thunk = create_thunk (cfg, domain, code, target);
968 g_assert (arm_is_bl_disp (code, thunk));
969 arm_bl (code, thunk);
973 g_assert_not_reached ();
978 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
980 arm_patch_full (NULL, NULL, code, target, relocation);
984 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
986 arm_patch_rel (code, target, relocation);
990 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
994 ip = ji->ip.i + code;
997 case MONO_PATCH_INFO_METHOD_JUMP:
998 /* ji->relocation is not set by the caller */
999 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1002 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1008 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1013 mono_arch_flush_register_windows (void)
1018 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1020 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1024 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1026 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1030 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1032 return ctx->regs [reg];
1036 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1038 ctx->regs [reg] = val;
1042 * mono_arch_set_target:
1044 * Set the target architecture the JIT backend should generate code for, in the form
1045 * of a GNU target triplet. Only used in AOT mode.
1048 mono_arch_set_target (char *mtriple)
1050 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1056 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1058 if (cinfo->gr >= PARAM_REGS) {
1059 ainfo->storage = ArgOnStack;
1061 /* Assume size == align */
1062 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1063 ainfo->offset = cinfo->stack_usage;
1064 ainfo->slot_size = size;
1066 cinfo->stack_usage += size;
1068 ainfo->offset = cinfo->stack_usage;
1069 ainfo->slot_size = 8;
1070 ainfo->sign = FALSE;
1071 /* Put arguments into 8 byte aligned stack slots */
1072 cinfo->stack_usage += 8;
1075 ainfo->storage = ArgInIReg;
1076 ainfo->reg = cinfo->gr;
1082 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1084 int size = single ? 4 : 8;
1086 if (cinfo->fr >= FP_PARAM_REGS) {
1087 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1089 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1090 ainfo->offset = cinfo->stack_usage;
1091 ainfo->slot_size = size;
1092 cinfo->stack_usage += size;
1094 ainfo->offset = cinfo->stack_usage;
1095 ainfo->slot_size = 8;
1096 /* Put arguments into 8 byte aligned stack slots */
1097 cinfo->stack_usage += 8;
1101 ainfo->storage = ArgInFRegR4;
1103 ainfo->storage = ArgInFReg;
1104 ainfo->reg = cinfo->fr;
1110 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1114 MonoClassField *field;
1115 MonoType *ftype, *prev_ftype = NULL;
1118 klass = mono_class_from_mono_type (t);
1120 while ((field = mono_class_get_fields (klass, &iter))) {
1121 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1123 ftype = mono_field_get_type (field);
1124 ftype = mini_get_underlying_type (ftype);
1126 if (MONO_TYPE_ISSTRUCT (ftype)) {
1127 int nested_nfields, nested_esize;
1128 int nested_field_offsets [16];
1130 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1132 if (nested_esize == 4)
1133 ftype = &mono_defaults.single_class->byval_arg;
1135 ftype = &mono_defaults.double_class->byval_arg;
1136 if (prev_ftype && prev_ftype->type != ftype->type)
1139 for (i = 0; i < nested_nfields; ++i) {
1140 if (nfields + i < 4)
1141 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1143 nfields += nested_nfields;
1145 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1147 if (prev_ftype && prev_ftype->type != ftype->type)
1151 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1155 if (nfields == 0 || nfields > 4)
1157 *out_nfields = nfields;
1158 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1163 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1165 int i, size, align_size, nregs, nfields, esize;
1166 int field_offsets [16];
1169 size = mini_type_stack_size_full (t, &align, cinfo->pinvoke);
1170 align_size = ALIGN_TO (size, 8);
1172 nregs = align_size / 8;
1173 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1175 * The struct might include nested float structs aligned at 8,
1176 * so need to keep track of the offsets of the individual fields.
1178 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1179 ainfo->storage = ArgHFA;
1180 ainfo->reg = cinfo->fr;
1181 ainfo->nregs = nfields;
1183 ainfo->esize = esize;
1184 for (i = 0; i < nfields; ++i)
1185 ainfo->foffsets [i] = field_offsets [i];
1186 cinfo->fr += ainfo->nregs;
1188 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1189 cinfo->fr = FP_PARAM_REGS;
1190 size = ALIGN_TO (size, 8);
1191 ainfo->storage = ArgVtypeOnStack;
1192 ainfo->offset = cinfo->stack_usage;
1195 ainfo->nregs = nfields;
1196 ainfo->esize = esize;
1197 cinfo->stack_usage += size;
1202 if (align_size > 16) {
1203 ainfo->storage = ArgVtypeByRef;
1208 if (cinfo->gr + nregs > PARAM_REGS) {
1209 size = ALIGN_TO (size, 8);
1210 ainfo->storage = ArgVtypeOnStack;
1211 ainfo->offset = cinfo->stack_usage;
1213 cinfo->stack_usage += size;
1214 cinfo->gr = PARAM_REGS;
1216 ainfo->storage = ArgVtypeInIRegs;
1217 ainfo->reg = cinfo->gr;
1218 ainfo->nregs = nregs;
1225 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1229 ptype = mini_get_underlying_type (t);
1230 switch (ptype->type) {
1232 add_general (cinfo, ainfo, 1, TRUE);
1234 case MONO_TYPE_BOOLEAN:
1236 add_general (cinfo, ainfo, 1, FALSE);
1239 add_general (cinfo, ainfo, 2, TRUE);
1242 case MONO_TYPE_CHAR:
1243 add_general (cinfo, ainfo, 2, FALSE);
1246 add_general (cinfo, ainfo, 4, TRUE);
1249 add_general (cinfo, ainfo, 4, FALSE);
1254 case MONO_TYPE_FNPTR:
1255 case MONO_TYPE_CLASS:
1256 case MONO_TYPE_OBJECT:
1257 case MONO_TYPE_SZARRAY:
1258 case MONO_TYPE_ARRAY:
1259 case MONO_TYPE_STRING:
1262 add_general (cinfo, ainfo, 8, FALSE);
1265 add_fp (cinfo, ainfo, FALSE);
1268 add_fp (cinfo, ainfo, TRUE);
1270 case MONO_TYPE_VALUETYPE:
1271 case MONO_TYPE_TYPEDBYREF:
1272 add_valuetype (cinfo, ainfo, ptype);
1274 case MONO_TYPE_VOID:
1275 ainfo->storage = ArgNone;
1277 case MONO_TYPE_GENERICINST:
1278 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1279 add_general (cinfo, ainfo, 8, FALSE);
1280 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1282 * Treat gsharedvt arguments as large vtypes
1284 ainfo->storage = ArgVtypeByRef;
1285 ainfo->gsharedvt = TRUE;
1287 add_valuetype (cinfo, ainfo, ptype);
1291 case MONO_TYPE_MVAR:
1292 g_assert (mini_is_gsharedvt_type (ptype));
1293 ainfo->storage = ArgVtypeByRef;
1294 ainfo->gsharedvt = TRUE;
1297 g_assert_not_reached ();
1305 * Obtain information about a call according to the calling convention.
1308 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1312 int n, pstart, pindex;
1314 n = sig->hasthis + sig->param_count;
1317 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1319 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1322 cinfo->pinvoke = sig->pinvoke;
1325 add_param (cinfo, &cinfo->ret, sig->ret);
1326 if (cinfo->ret.storage == ArgVtypeByRef)
1327 cinfo->ret.reg = ARMREG_R8;
1331 cinfo->stack_usage = 0;
1335 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1337 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1338 ainfo = cinfo->args + sig->hasthis + pindex;
1340 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1341 /* Prevent implicit arguments and sig_cookie from
1342 being passed in registers */
1343 cinfo->gr = PARAM_REGS;
1344 cinfo->fr = FP_PARAM_REGS;
1345 /* Emit the signature cookie just before the implicit arguments */
1346 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1349 add_param (cinfo, ainfo, sig->params [pindex]);
1350 if (ainfo->storage == ArgVtypeByRef) {
1351 /* Pass the argument address in the next register */
1352 if (cinfo->gr >= PARAM_REGS) {
1353 ainfo->storage = ArgVtypeByRefOnStack;
1354 ainfo->offset = cinfo->stack_usage;
1355 cinfo->stack_usage += 8;
1357 ainfo->reg = cinfo->gr;
1363 /* Handle the case where there are no implicit arguments */
1364 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1365 /* Prevent implicit arguments and sig_cookie from
1366 being passed in registers */
1367 cinfo->gr = PARAM_REGS;
1368 cinfo->fr = FP_PARAM_REGS;
1369 /* Emit the signature cookie just before the implicit arguments */
1370 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1373 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1379 MonoMethodSignature *sig;
1382 MonoType **param_types;
1383 int n_fpargs, n_fpret;
1387 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1391 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1394 // FIXME: Add more cases
1395 switch (cinfo->ret.storage) {
1402 case ArgVtypeInIRegs:
1403 if (cinfo->ret.nregs > 2)
1412 for (i = 0; i < cinfo->nargs; ++i) {
1413 ArgInfo *ainfo = &cinfo->args [i];
1415 switch (ainfo->storage) {
1417 case ArgVtypeInIRegs:
1424 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1436 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1438 ArchDynCallInfo *info;
1442 cinfo = get_call_info (NULL, sig);
1444 if (!dyn_call_supported (cinfo, sig)) {
1449 info = g_new0 (ArchDynCallInfo, 1);
1450 // FIXME: Preprocess the info to speed up start_dyn_call ()
1452 info->cinfo = cinfo;
1453 info->rtype = mini_get_underlying_type (sig->ret);
1454 info->param_types = g_new0 (MonoType*, sig->param_count);
1455 for (i = 0; i < sig->param_count; ++i)
1456 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1458 switch (cinfo->ret.storage) {
1464 info->n_fpret = cinfo->ret.nregs;
1470 return (MonoDynCallInfo*)info;
1474 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1476 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1478 g_free (ainfo->cinfo);
1479 g_free (ainfo->param_types);
1484 bitcast_r4_to_r8 (float f)
1492 bitcast_r8_to_r4 (double f)
1500 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1502 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1503 DynCallArgs *p = (DynCallArgs*)buf;
1504 int aindex, arg_index, greg, i, pindex;
1505 MonoMethodSignature *sig = dinfo->sig;
1506 CallInfo *cinfo = dinfo->cinfo;
1507 int buffer_offset = 0;
1509 g_assert (buf_len >= sizeof (DynCallArgs));
1513 p->n_fpargs = dinfo->n_fpargs;
1514 p->n_fpret = dinfo->n_fpret;
1521 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1523 if (cinfo->ret.storage == ArgVtypeByRef)
1524 p->regs [ARMREG_R8] = (mgreg_t)ret;
1526 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1527 MonoType *t = dinfo->param_types [aindex];
1528 gpointer *arg = args [arg_index ++];
1529 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1532 if (ainfo->storage == ArgOnStack) {
1533 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1539 p->regs [slot] = (mgreg_t)*arg;
1543 if (ios_abi && ainfo->storage == ArgOnStack) {
1544 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1545 gboolean handled = TRUE;
1547 /* Special case arguments smaller than 1 machine word */
1549 case MONO_TYPE_BOOLEAN:
1551 *(guint8*)stack_arg = *(guint8*)arg;
1554 *(gint8*)stack_arg = *(gint8*)arg;
1557 case MONO_TYPE_CHAR:
1558 *(guint16*)stack_arg = *(guint16*)arg;
1561 *(gint16*)stack_arg = *(gint16*)arg;
1564 *(gint32*)stack_arg = *(gint32*)arg;
1567 *(guint32*)stack_arg = *(guint32*)arg;
1578 case MONO_TYPE_STRING:
1579 case MONO_TYPE_CLASS:
1580 case MONO_TYPE_ARRAY:
1581 case MONO_TYPE_SZARRAY:
1582 case MONO_TYPE_OBJECT:
1588 p->regs [slot] = (mgreg_t)*arg;
1590 case MONO_TYPE_BOOLEAN:
1592 p->regs [slot] = *(guint8*)arg;
1595 p->regs [slot] = *(gint8*)arg;
1598 p->regs [slot] = *(gint16*)arg;
1601 case MONO_TYPE_CHAR:
1602 p->regs [slot] = *(guint16*)arg;
1605 p->regs [slot] = *(gint32*)arg;
1608 p->regs [slot] = *(guint32*)arg;
1611 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1615 p->fpregs [ainfo->reg] = *(double*)arg;
1618 case MONO_TYPE_GENERICINST:
1619 if (MONO_TYPE_IS_REFERENCE (t)) {
1620 p->regs [slot] = (mgreg_t)*arg;
1623 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1624 MonoClass *klass = mono_class_from_mono_type (t);
1625 guint8 *nullable_buf;
1629 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1630 * if the nullable param is passed by ref.
1632 size = mono_class_value_size (klass, NULL);
1633 nullable_buf = p->buffer + buffer_offset;
1634 buffer_offset += size;
1635 g_assert (buffer_offset <= 256);
1637 /* The argument pointed to by arg is either a boxed vtype or null */
1638 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1640 arg = (gpointer*)nullable_buf;
1646 case MONO_TYPE_VALUETYPE:
1647 switch (ainfo->storage) {
1648 case ArgVtypeInIRegs:
1649 for (i = 0; i < ainfo->nregs; ++i)
1650 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1653 if (ainfo->esize == 4) {
1654 for (i = 0; i < ainfo->nregs; ++i)
1655 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1657 for (i = 0; i < ainfo->nregs; ++i)
1658 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1660 p->n_fpargs += ainfo->nregs;
1663 p->regs [slot] = (mgreg_t)arg;
1666 g_assert_not_reached ();
1671 g_assert_not_reached ();
1677 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1679 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1680 CallInfo *cinfo = ainfo->cinfo;
1681 DynCallArgs *args = (DynCallArgs*)buf;
1682 MonoType *ptype = ainfo->rtype;
1683 guint8 *ret = args->ret;
1684 mgreg_t res = args->res;
1685 mgreg_t res2 = args->res2;
1688 if (cinfo->ret.storage == ArgVtypeByRef)
1691 switch (ptype->type) {
1692 case MONO_TYPE_VOID:
1693 *(gpointer*)ret = NULL;
1695 case MONO_TYPE_STRING:
1696 case MONO_TYPE_CLASS:
1697 case MONO_TYPE_ARRAY:
1698 case MONO_TYPE_SZARRAY:
1699 case MONO_TYPE_OBJECT:
1703 *(gpointer*)ret = (gpointer)res;
1709 case MONO_TYPE_BOOLEAN:
1710 *(guint8*)ret = res;
1713 *(gint16*)ret = res;
1716 case MONO_TYPE_CHAR:
1717 *(guint16*)ret = res;
1720 *(gint32*)ret = res;
1723 *(guint32*)ret = res;
1727 *(guint64*)ret = res;
1730 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1733 *(double*)ret = args->fpregs [0];
1735 case MONO_TYPE_GENERICINST:
1736 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1737 *(gpointer*)ret = (gpointer)res;
1742 case MONO_TYPE_VALUETYPE:
1743 switch (ainfo->cinfo->ret.storage) {
1744 case ArgVtypeInIRegs:
1745 *(mgreg_t*)ret = res;
1746 if (ainfo->cinfo->ret.nregs > 1)
1747 ((mgreg_t*)ret) [1] = res2;
1750 /* Use the same area for returning fp values */
1751 if (cinfo->ret.esize == 4) {
1752 for (i = 0; i < cinfo->ret.nregs; ++i)
1753 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1755 for (i = 0; i < cinfo->ret.nregs; ++i)
1756 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1760 g_assert_not_reached ();
1765 g_assert_not_reached ();
1770 void sys_icache_invalidate (void *start, size_t len);
1774 mono_arch_flush_icache (guint8 *code, gint size)
1776 #ifndef MONO_CROSS_COMPILE
1778 sys_icache_invalidate (code, size);
1780 /* Don't rely on GCC's __clear_cache implementation, as it caches
1781 * icache/dcache cache line sizes, that can vary between cores on
1782 * big.LITTLE architectures. */
1783 guint64 end = (guint64) (code + size);
1784 guint64 addr, ctr_el0;
1785 static size_t icache_line_size = 0xffff, dcache_line_size = 0xffff;
1786 size_t isize, dsize;
1788 asm volatile ("mrs %0, ctr_el0" : "=r" (ctr_el0));
1789 isize = 4 << ((ctr_el0 >> 0 ) & 0xf);
1790 dsize = 4 << ((ctr_el0 >> 16) & 0xf);
1792 /* determine the global minimum cache line size */
1793 icache_line_size = isize = MIN (icache_line_size, isize);
1794 dcache_line_size = dsize = MIN (dcache_line_size, dsize);
1796 addr = (guint64) code & ~(guint64) (dsize - 1);
1797 for (; addr < end; addr += dsize)
1798 asm volatile("dc civac, %0" : : "r" (addr) : "memory");
1799 asm volatile("dsb ish" : : : "memory");
1801 addr = (guint64) code & ~(guint64) (isize - 1);
1802 for (; addr < end; addr += isize)
1803 asm volatile("ic ivau, %0" : : "r" (addr) : "memory");
1805 asm volatile ("dsb ish" : : : "memory");
1806 asm volatile ("isb" : : : "memory");
1814 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1821 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1826 for (i = 0; i < cfg->num_varinfo; i++) {
1827 MonoInst *ins = cfg->varinfo [i];
1828 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1831 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1834 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1835 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1838 if (mono_is_regsize_var (ins->inst_vtype)) {
1839 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1840 g_assert (i == vmv->idx);
1841 vars = g_list_prepend (vars, vmv);
1845 vars = mono_varlist_sort (cfg, vars, 0);
1851 mono_arch_get_global_int_regs (MonoCompile *cfg)
1856 /* r28 is reserved for cfg->arch.args_reg */
1857 /* r27 is reserved for the imt argument */
1858 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1859 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1865 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1867 MonoInst *ins = cfg->varinfo [vmv->idx];
1869 if (ins->opcode == OP_ARG)
1876 mono_arch_create_vars (MonoCompile *cfg)
1878 MonoMethodSignature *sig;
1881 sig = mono_method_signature (cfg->method);
1882 if (!cfg->arch.cinfo)
1883 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1884 cinfo = cfg->arch.cinfo;
1886 if (cinfo->ret.storage == ArgVtypeByRef) {
1887 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1888 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1891 if (cfg->gen_sdb_seq_points) {
1894 if (cfg->compile_aot) {
1895 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1896 ins->flags |= MONO_INST_VOLATILE;
1897 cfg->arch.seq_point_info_var = ins;
1900 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1901 ins->flags |= MONO_INST_VOLATILE;
1902 cfg->arch.ss_tramp_var = ins;
1904 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1905 ins->flags |= MONO_INST_VOLATILE;
1906 cfg->arch.bp_tramp_var = ins;
1909 if (cfg->method->save_lmf) {
1910 cfg->create_lmf_var = TRUE;
1913 cfg->lmf_ir_mono_lmf = TRUE;
1919 mono_arch_allocate_vars (MonoCompile *cfg)
1921 MonoMethodSignature *sig;
1925 int i, offset, size, align;
1926 guint32 locals_stack_size, locals_stack_align;
1930 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1931 * Compute cfg->stack_offset and update cfg->used_int_regs.
1934 sig = mono_method_signature (cfg->method);
1936 if (!cfg->arch.cinfo)
1937 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1938 cinfo = cfg->arch.cinfo;
1941 * The ARM64 ABI always uses a frame pointer.
1942 * The instruction set prefers positive offsets, so fp points to the bottom of the
1943 * frame, and stack slots are at positive offsets.
1944 * If some arguments are received on the stack, their offsets relative to fp can
1945 * not be computed right now because the stack frame might grow due to spilling
1946 * done by the local register allocator. To solve this, we reserve a register
1947 * which points to them.
1948 * The stack frame looks like this:
1949 * args_reg -> <bottom of parent frame>
1951 * fp -> <saved fp+lr>
1952 * sp -> <localloc/params area>
1954 cfg->frame_reg = ARMREG_FP;
1955 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1961 if (cinfo->stack_usage) {
1962 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1963 cfg->arch.args_reg = ARMREG_R28;
1964 cfg->used_int_regs |= 1 << ARMREG_R28;
1967 if (cfg->method->save_lmf) {
1968 /* The LMF var is allocated normally */
1970 /* Callee saved regs */
1971 cfg->arch.saved_gregs_offset = offset;
1972 for (i = 0; i < 32; ++i)
1973 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1978 switch (cinfo->ret.storage) {
1984 cfg->ret->opcode = OP_REGVAR;
1985 cfg->ret->dreg = cinfo->ret.reg;
1987 case ArgVtypeInIRegs:
1989 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1990 cfg->ret->opcode = OP_REGOFFSET;
1991 cfg->ret->inst_basereg = cfg->frame_reg;
1992 cfg->ret->inst_offset = offset;
1993 if (cinfo->ret.storage == ArgHFA)
2000 /* This variable will be initalized in the prolog from R8 */
2001 cfg->vret_addr->opcode = OP_REGOFFSET;
2002 cfg->vret_addr->inst_basereg = cfg->frame_reg;
2003 cfg->vret_addr->inst_offset = offset;
2005 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2006 printf ("vret_addr =");
2007 mono_print_ins (cfg->vret_addr);
2011 g_assert_not_reached ();
2016 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2017 ainfo = cinfo->args + i;
2019 ins = cfg->args [i];
2020 if (ins->opcode == OP_REGVAR)
2023 ins->opcode = OP_REGOFFSET;
2024 ins->inst_basereg = cfg->frame_reg;
2026 switch (ainfo->storage) {
2030 // FIXME: Use nregs/size
2031 /* These will be copied to the stack in the prolog */
2032 ins->inst_offset = offset;
2038 case ArgVtypeOnStack:
2039 /* These are in the parent frame */
2040 g_assert (cfg->arch.args_reg);
2041 ins->inst_basereg = cfg->arch.args_reg;
2042 ins->inst_offset = ainfo->offset;
2044 case ArgVtypeInIRegs:
2046 ins->opcode = OP_REGOFFSET;
2047 ins->inst_basereg = cfg->frame_reg;
2048 /* These arguments are saved to the stack in the prolog */
2049 ins->inst_offset = offset;
2050 if (cfg->verbose_level >= 2)
2051 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2052 if (ainfo->storage == ArgHFA)
2058 case ArgVtypeByRefOnStack: {
2061 if (ainfo->gsharedvt) {
2062 ins->opcode = OP_REGOFFSET;
2063 ins->inst_basereg = cfg->arch.args_reg;
2064 ins->inst_offset = ainfo->offset;
2068 /* The vtype address is in the parent frame */
2069 g_assert (cfg->arch.args_reg);
2070 MONO_INST_NEW (cfg, vtaddr, 0);
2071 vtaddr->opcode = OP_REGOFFSET;
2072 vtaddr->inst_basereg = cfg->arch.args_reg;
2073 vtaddr->inst_offset = ainfo->offset;
2075 /* Need an indirection */
2076 ins->opcode = OP_VTARG_ADDR;
2077 ins->inst_left = vtaddr;
2080 case ArgVtypeByRef: {
2083 if (ainfo->gsharedvt) {
2084 ins->opcode = OP_REGOFFSET;
2085 ins->inst_basereg = cfg->frame_reg;
2086 ins->inst_offset = offset;
2091 /* The vtype address is in a register, will be copied to the stack in the prolog */
2092 MONO_INST_NEW (cfg, vtaddr, 0);
2093 vtaddr->opcode = OP_REGOFFSET;
2094 vtaddr->inst_basereg = cfg->frame_reg;
2095 vtaddr->inst_offset = offset;
2098 /* Need an indirection */
2099 ins->opcode = OP_VTARG_ADDR;
2100 ins->inst_left = vtaddr;
2104 g_assert_not_reached ();
2109 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2110 // FIXME: Allocate these to registers
2111 ins = cfg->arch.seq_point_info_var;
2115 offset += align - 1;
2116 offset &= ~(align - 1);
2117 ins->opcode = OP_REGOFFSET;
2118 ins->inst_basereg = cfg->frame_reg;
2119 ins->inst_offset = offset;
2122 ins = cfg->arch.ss_tramp_var;
2126 offset += align - 1;
2127 offset &= ~(align - 1);
2128 ins->opcode = OP_REGOFFSET;
2129 ins->inst_basereg = cfg->frame_reg;
2130 ins->inst_offset = offset;
2133 ins = cfg->arch.bp_tramp_var;
2137 offset += align - 1;
2138 offset &= ~(align - 1);
2139 ins->opcode = OP_REGOFFSET;
2140 ins->inst_basereg = cfg->frame_reg;
2141 ins->inst_offset = offset;
2146 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2147 if (locals_stack_align)
2148 offset = ALIGN_TO (offset, locals_stack_align);
2150 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2151 if (offsets [i] != -1) {
2152 ins = cfg->varinfo [i];
2153 ins->opcode = OP_REGOFFSET;
2154 ins->inst_basereg = cfg->frame_reg;
2155 ins->inst_offset = offset + offsets [i];
2156 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2159 offset += locals_stack_size;
2161 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2163 cfg->stack_offset = offset;
2168 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2173 LLVMCallInfo *linfo;
2175 n = sig->param_count + sig->hasthis;
2177 cinfo = get_call_info (cfg->mempool, sig);
2179 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2181 switch (cinfo->ret.storage) {
2188 linfo->ret.storage = LLVMArgVtypeByRef;
2191 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2192 // array which is returned in int regs
2195 linfo->ret.storage = LLVMArgFpStruct;
2196 linfo->ret.nslots = cinfo->ret.nregs;
2197 linfo->ret.esize = cinfo->ret.esize;
2199 case ArgVtypeInIRegs:
2200 /* LLVM models this by returning an int */
2201 linfo->ret.storage = LLVMArgVtypeAsScalar;
2202 linfo->ret.nslots = cinfo->ret.nregs;
2203 linfo->ret.esize = cinfo->ret.esize;
2206 g_assert_not_reached ();
2210 for (i = 0; i < n; ++i) {
2211 LLVMArgInfo *lainfo = &linfo->args [i];
2213 ainfo = cinfo->args + i;
2215 lainfo->storage = LLVMArgNone;
2217 switch (ainfo->storage) {
2224 lainfo->storage = LLVMArgNormal;
2227 case ArgVtypeByRefOnStack:
2228 lainfo->storage = LLVMArgVtypeByRef;
2233 lainfo->storage = LLVMArgAsFpArgs;
2234 lainfo->nslots = ainfo->nregs;
2235 lainfo->esize = ainfo->esize;
2236 for (j = 0; j < ainfo->nregs; ++j)
2237 lainfo->pair_storage [j] = LLVMArgInFPReg;
2240 case ArgVtypeInIRegs:
2241 lainfo->storage = LLVMArgAsIArgs;
2242 lainfo->nslots = ainfo->nregs;
2244 case ArgVtypeOnStack:
2248 lainfo->storage = LLVMArgAsFpArgs;
2249 lainfo->nslots = ainfo->nregs;
2250 lainfo->esize = ainfo->esize;
2251 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2252 for (j = 0; j < ainfo->nregs; ++j)
2253 lainfo->pair_storage [j] = LLVMArgInFPReg;
2255 lainfo->storage = LLVMArgAsIArgs;
2256 lainfo->nslots = ainfo->size / 8;
2260 g_assert_not_reached ();
2270 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2276 MONO_INST_NEW (cfg, ins, OP_MOVE);
2277 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2278 ins->sreg1 = arg->dreg;
2279 MONO_ADD_INS (cfg->cbb, ins);
2280 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2283 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2284 ins->dreg = mono_alloc_freg (cfg);
2285 ins->sreg1 = arg->dreg;
2286 MONO_ADD_INS (cfg->cbb, ins);
2287 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2290 if (COMPILE_LLVM (cfg))
2291 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2293 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2295 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2296 ins->dreg = mono_alloc_freg (cfg);
2297 ins->sreg1 = arg->dreg;
2298 MONO_ADD_INS (cfg->cbb, ins);
2299 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2302 g_assert_not_reached ();
2308 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2310 MonoMethodSignature *tmp_sig;
2313 if (call->tail_call)
2316 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2319 * mono_ArgIterator_Setup assumes the signature cookie is
2320 * passed first and all the arguments which were before it are
2321 * passed on the stack after the signature. So compensate by
2322 * passing a different signature.
2324 tmp_sig = mono_metadata_signature_dup (call->signature);
2325 tmp_sig->param_count -= call->signature->sentinelpos;
2326 tmp_sig->sentinelpos = 0;
2327 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2329 sig_reg = mono_alloc_ireg (cfg);
2330 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2332 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2336 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2338 MonoMethodSignature *sig;
2339 MonoInst *arg, *vtarg;
2344 sig = call->signature;
2346 cinfo = get_call_info (cfg->mempool, sig);
2348 switch (cinfo->ret.storage) {
2349 case ArgVtypeInIRegs:
2352 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2353 * the location pointed to by it after call in emit_move_return_value ().
2355 if (!cfg->arch.vret_addr_loc) {
2356 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2357 /* Prevent it from being register allocated or optimized away */
2358 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2361 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2364 /* Pass the vtype return address in R8 */
2365 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2366 vtarg->sreg1 = call->vret_var->dreg;
2367 vtarg->dreg = mono_alloc_preg (cfg);
2368 MONO_ADD_INS (cfg->cbb, vtarg);
2370 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2376 for (i = 0; i < cinfo->nargs; ++i) {
2377 ainfo = cinfo->args + i;
2378 arg = call->args [i];
2380 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2381 /* Emit the signature cookie just before the implicit arguments */
2382 emit_sig_cookie (cfg, call, cinfo);
2385 switch (ainfo->storage) {
2389 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2392 switch (ainfo->slot_size) {
2394 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2397 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2400 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2406 g_assert_not_reached ();
2411 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2414 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2416 case ArgVtypeInIRegs:
2418 case ArgVtypeByRefOnStack:
2419 case ArgVtypeOnStack:
2425 size = mono_class_value_size (arg->klass, &align);
2427 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2428 ins->sreg1 = arg->dreg;
2429 ins->klass = arg->klass;
2430 ins->backend.size = size;
2431 ins->inst_p0 = call;
2432 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2433 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2434 MONO_ADD_INS (cfg->cbb, ins);
2438 g_assert_not_reached ();
2443 /* Handle the case where there are no implicit arguments */
2444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2445 emit_sig_cookie (cfg, call, cinfo);
2447 call->call_info = cinfo;
2448 call->stack_usage = cinfo->stack_usage;
2452 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2454 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2455 ArgInfo *ainfo = ins->inst_p1;
2459 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2462 switch (ainfo->storage) {
2463 case ArgVtypeInIRegs:
2464 for (i = 0; i < ainfo->nregs; ++i) {
2465 // FIXME: Smaller sizes
2466 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2467 load->dreg = mono_alloc_ireg (cfg);
2468 load->inst_basereg = src->dreg;
2469 load->inst_offset = i * sizeof(mgreg_t);
2470 MONO_ADD_INS (cfg->cbb, load);
2471 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2475 for (i = 0; i < ainfo->nregs; ++i) {
2476 if (ainfo->esize == 4)
2477 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2479 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2480 load->dreg = mono_alloc_freg (cfg);
2481 load->inst_basereg = src->dreg;
2482 load->inst_offset = ainfo->foffsets [i];
2483 MONO_ADD_INS (cfg->cbb, load);
2484 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2488 case ArgVtypeByRefOnStack: {
2489 MonoInst *vtaddr, *load, *arg;
2491 /* Pass the vtype address in a reg/on the stack */
2492 if (ainfo->gsharedvt) {
2495 /* Make a copy of the argument */
2496 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2498 MONO_INST_NEW (cfg, load, OP_LDADDR);
2499 load->inst_p0 = vtaddr;
2500 vtaddr->flags |= MONO_INST_INDIRECT;
2501 load->type = STACK_MP;
2502 load->klass = vtaddr->klass;
2503 load->dreg = mono_alloc_ireg (cfg);
2504 MONO_ADD_INS (cfg->cbb, load);
2505 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2508 if (ainfo->storage == ArgVtypeByRef) {
2509 MONO_INST_NEW (cfg, arg, OP_MOVE);
2510 arg->dreg = mono_alloc_preg (cfg);
2511 arg->sreg1 = load->dreg;
2512 MONO_ADD_INS (cfg->cbb, arg);
2513 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2515 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2519 case ArgVtypeOnStack:
2520 for (i = 0; i < ainfo->size / 8; ++i) {
2521 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2522 load->dreg = mono_alloc_ireg (cfg);
2523 load->inst_basereg = src->dreg;
2524 load->inst_offset = i * 8;
2525 MONO_ADD_INS (cfg->cbb, load);
2526 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2530 g_assert_not_reached ();
2536 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2538 MonoMethodSignature *sig;
2541 sig = mono_method_signature (cfg->method);
2542 if (!cfg->arch.cinfo)
2543 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2544 cinfo = cfg->arch.cinfo;
2546 switch (cinfo->ret.storage) {
2550 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2553 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2556 if (COMPILE_LLVM (cfg))
2557 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2559 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2561 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2564 g_assert_not_reached ();
2570 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2575 if (cfg->compile_aot && !cfg->full_aot)
2576 /* OP_TAILCALL doesn't work with AOT */
2579 c1 = get_call_info (NULL, caller_sig);
2580 c2 = get_call_info (NULL, callee_sig);
2582 // FIXME: Relax these restrictions
2583 if (c1->stack_usage != 0)
2585 if (c1->stack_usage != c2->stack_usage)
2587 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2597 mono_arch_is_inst_imm (gint64 imm)
2599 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2603 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2610 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2617 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2623 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2628 #define ADD_NEW_INS(cfg,dest,op) do { \
2629 MONO_INST_NEW ((cfg), (dest), (op)); \
2630 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2634 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2636 MonoInst *ins, *temp, *last_ins = NULL;
2638 MONO_BB_FOR_EACH_INS (bb, ins) {
2639 switch (ins->opcode) {
2644 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2645 /* ARM sets the C flag to 1 if there was _no_ overflow */
2646 ins->next->opcode = OP_COND_EXC_NC;
2650 case OP_IDIV_UN_IMM:
2651 case OP_IREM_UN_IMM:
2653 mono_decompose_op_imm (cfg, bb, ins);
2655 case OP_LOCALLOC_IMM:
2656 if (ins->inst_imm > 32) {
2657 ADD_NEW_INS (cfg, temp, OP_ICONST);
2658 temp->inst_c0 = ins->inst_imm;
2659 temp->dreg = mono_alloc_ireg (cfg);
2660 ins->sreg1 = temp->dreg;
2661 ins->opcode = mono_op_imm_to_op (ins->opcode);
2664 case OP_ICOMPARE_IMM:
2665 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2666 ins->next->opcode = OP_ARM64_CBZW;
2667 ins->next->sreg1 = ins->sreg1;
2669 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2670 ins->next->opcode = OP_ARM64_CBNZW;
2671 ins->next->sreg1 = ins->sreg1;
2675 case OP_LCOMPARE_IMM:
2676 case OP_COMPARE_IMM:
2677 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2678 ins->next->opcode = OP_ARM64_CBZX;
2679 ins->next->sreg1 = ins->sreg1;
2681 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2682 ins->next->opcode = OP_ARM64_CBNZX;
2683 ins->next->sreg1 = ins->sreg1;
2688 gboolean swap = FALSE;
2692 /* Optimized away */
2698 * FP compares with unordered operands set the flags
2699 * to NZCV=0011, which matches some non-unordered compares
2700 * as well, like LE, so have to swap the operands.
2702 switch (ins->next->opcode) {
2704 ins->next->opcode = OP_FBGT;
2708 ins->next->opcode = OP_FBGE;
2716 ins->sreg1 = ins->sreg2;
2727 bb->last_ins = last_ins;
2728 bb->max_vreg = cfg->next_vreg;
2732 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2737 opcode_to_armcond (int opcode)
2748 case OP_COND_EXC_IEQ:
2749 case OP_COND_EXC_EQ:
2766 case OP_COND_EXC_IGT:
2767 case OP_COND_EXC_GT:
2782 case OP_COND_EXC_ILT:
2783 case OP_COND_EXC_LT:
2791 case OP_COND_EXC_INE_UN:
2792 case OP_COND_EXC_NE_UN:
2798 case OP_COND_EXC_IGE_UN:
2799 case OP_COND_EXC_GE_UN:
2809 case OP_COND_EXC_IGT_UN:
2810 case OP_COND_EXC_GT_UN:
2816 case OP_COND_EXC_ILE_UN:
2817 case OP_COND_EXC_LE_UN:
2825 case OP_COND_EXC_ILT_UN:
2826 case OP_COND_EXC_LT_UN:
2829 * FCMP sets the NZCV condition bits as follows:
2834 * ARMCOND_LT is N!=V, so it matches unordered too, so
2835 * fclt and fclt_un need to be special cased.
2845 case OP_COND_EXC_IC:
2847 case OP_COND_EXC_OV:
2848 case OP_COND_EXC_IOV:
2850 case OP_COND_EXC_NC:
2851 case OP_COND_EXC_INC:
2853 case OP_COND_EXC_NO:
2854 case OP_COND_EXC_INO:
2857 printf ("%s\n", mono_inst_name (opcode));
2858 g_assert_not_reached ();
2863 /* This clobbers LR */
2864 static inline __attribute__((warn_unused_result)) guint8*
2865 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2869 cond = opcode_to_armcond (opcode);
2871 arm_adrx (code, ARMREG_IP1, code);
2872 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2873 arm_bcc (code, cond, 0);
2878 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2883 call = (MonoCallInst*)ins;
2884 cinfo = call->call_info;
2886 switch (cinfo->ret.storage) {
2890 /* LLVM compiled code might only set the bottom bits */
2891 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2892 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2893 else if (call->inst.dreg != cinfo->ret.reg)
2894 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2897 if (call->inst.dreg != cinfo->ret.reg)
2898 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2902 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2904 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2906 case ArgVtypeInIRegs: {
2907 MonoInst *loc = cfg->arch.vret_addr_loc;
2910 /* Load the destination address */
2911 g_assert (loc && loc->opcode == OP_REGOFFSET);
2912 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2913 for (i = 0; i < cinfo->ret.nregs; ++i)
2914 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2918 MonoInst *loc = cfg->arch.vret_addr_loc;
2921 /* Load the destination address */
2922 g_assert (loc && loc->opcode == OP_REGOFFSET);
2923 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2924 for (i = 0; i < cinfo->ret.nregs; ++i) {
2925 if (cinfo->ret.esize == 4)
2926 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2928 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2935 g_assert_not_reached ();
2942 * emit_branch_island:
2944 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2947 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2950 int offset, island_size;
2952 /* Iterate over the patch infos added so far by this bb */
2954 for (ji = cfg->patch_info; ji; ji = ji->next) {
2955 if (ji->ip.i < start_offset)
2956 /* The patch infos are in reverse order, so this means the end */
2958 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2963 offset = code - cfg->native_code;
2964 if (offset > (cfg->code_size - island_size - 16)) {
2965 cfg->code_size *= 2;
2966 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2967 code = cfg->native_code + offset;
2970 /* Branch over the island */
2971 arm_b (code, code + 4 + island_size);
2973 for (ji = cfg->patch_info; ji; ji = ji->next) {
2974 if (ji->ip.i < start_offset)
2976 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2977 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2978 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2979 /* Rewrite the patch so it points to the unconditional branch */
2980 ji->ip.i = code - cfg->native_code;
2981 ji->relocation = MONO_R_ARM64_B;
2990 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2995 guint8 *code = cfg->native_code + cfg->code_len;
2996 int start_offset, max_len, dreg, sreg1, sreg2;
2999 if (cfg->verbose_level > 2)
3000 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3002 start_offset = code - cfg->native_code;
3004 MONO_BB_FOR_EACH_INS (bb, ins) {
3005 offset = code - cfg->native_code;
3007 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3009 if (offset > (cfg->code_size - max_len - 16)) {
3010 cfg->code_size *= 2;
3011 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3012 code = cfg->native_code + offset;
3015 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
3016 /* Emit a branch island for large basic blocks */
3017 code = emit_branch_island (cfg, code, start_offset);
3018 offset = code - cfg->native_code;
3019 start_offset = offset;
3022 mono_debug_record_line_number (cfg, ins, offset);
3027 imm = ins->inst_imm;
3029 switch (ins->opcode) {
3031 code = emit_imm (code, dreg, ins->inst_c0);
3034 code = emit_imm64 (code, dreg, ins->inst_c0);
3038 arm_movx (code, dreg, sreg1);
3041 case OP_RELAXED_NOP:
3044 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3045 code = emit_imm64_template (code, dreg);
3049 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3050 * So instead of emitting a trap, we emit a call a C function and place a
3053 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3058 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3059 // FIXME: andx_imm doesn't work yet
3060 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3061 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3062 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3063 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3064 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3065 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3068 /* ip1 = pointer, ip0 = end */
3069 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3071 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3073 arm_bcc (code, ARMCOND_EQ, 0);
3074 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3075 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3076 arm_b (code, buf [0]);
3077 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3079 arm_movspx (code, dreg, ARMREG_SP);
3080 if (cfg->param_area)
3081 code = emit_subx_sp_imm (code, cfg->param_area);
3084 case OP_LOCALLOC_IMM: {
3087 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3088 g_assert (arm_is_arith_imm (imm));
3089 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3092 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3094 while (offset < imm) {
3095 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3098 arm_movspx (code, dreg, ARMREG_SP);
3099 if (cfg->param_area)
3100 code = emit_subx_sp_imm (code, cfg->param_area);
3104 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3106 case OP_OBJC_GET_SELECTOR:
3107 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3108 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3109 arm_ldrx_lit (code, ins->dreg, 0);
3113 case OP_SEQ_POINT: {
3114 MonoInst *info_var = cfg->arch.seq_point_info_var;
3117 * For AOT, we use one got slot per method, which will point to a
3118 * SeqPointInfo structure, containing all the information required
3119 * by the code below.
3121 if (cfg->compile_aot) {
3122 g_assert (info_var);
3123 g_assert (info_var->opcode == OP_REGOFFSET);
3126 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3127 MonoInst *var = cfg->arch.ss_tramp_var;
3130 g_assert (var->opcode == OP_REGOFFSET);
3131 /* Load ss_tramp_var */
3132 /* This is equal to &ss_trampoline */
3133 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3134 /* Load the trampoline address */
3135 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3136 /* Call it if it is non-null */
3137 arm_cbzx (code, ARMREG_IP1, code + 8);
3138 arm_blrx (code, ARMREG_IP1);
3141 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3143 if (cfg->compile_aot) {
3144 guint32 offset = code - cfg->native_code;
3147 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3148 /* Add the offset */
3149 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3150 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3151 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3152 /* Skip the load if its 0 */
3153 arm_cbzx (code, ARMREG_IP1, code + 8);
3154 /* Call the breakpoint trampoline */
3155 arm_blrx (code, ARMREG_IP1);
3157 MonoInst *var = cfg->arch.bp_tramp_var;
3160 g_assert (var->opcode == OP_REGOFFSET);
3161 /* Load the address of the bp trampoline into IP0 */
3162 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3164 * A placeholder for a possible breakpoint inserted by
3165 * mono_arch_set_breakpoint ().
3174 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3178 arm_brx (code, sreg1);
3210 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3211 cond = opcode_to_armcond (ins->opcode);
3212 arm_bcc (code, cond, 0);
3216 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3217 /* For fp compares, ARMCOND_LT is lt or unordered */
3218 arm_bcc (code, ARMCOND_LT, 0);
3221 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3222 arm_bcc (code, ARMCOND_EQ, 0);
3223 offset = code - cfg->native_code;
3224 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3225 /* For fp compares, ARMCOND_LT is lt or unordered */
3226 arm_bcc (code, ARMCOND_LT, 0);
3229 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3230 arm_cbzw (code, sreg1, 0);
3233 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3234 arm_cbzx (code, sreg1, 0);
3236 case OP_ARM64_CBNZW:
3237 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3238 arm_cbnzw (code, sreg1, 0);
3240 case OP_ARM64_CBNZX:
3241 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3242 arm_cbnzx (code, sreg1, 0);
3246 arm_addw (code, dreg, sreg1, sreg2);
3249 arm_addx (code, dreg, sreg1, sreg2);
3252 arm_subw (code, dreg, sreg1, sreg2);
3255 arm_subx (code, dreg, sreg1, sreg2);
3258 arm_andw (code, dreg, sreg1, sreg2);
3261 arm_andx (code, dreg, sreg1, sreg2);
3264 arm_orrw (code, dreg, sreg1, sreg2);
3267 arm_orrx (code, dreg, sreg1, sreg2);
3270 arm_eorw (code, dreg, sreg1, sreg2);
3273 arm_eorx (code, dreg, sreg1, sreg2);
3276 arm_negw (code, dreg, sreg1);
3279 arm_negx (code, dreg, sreg1);
3282 arm_mvnw (code, dreg, sreg1);
3285 arm_mvnx (code, dreg, sreg1);
3288 arm_addsw (code, dreg, sreg1, sreg2);
3292 arm_addsx (code, dreg, sreg1, sreg2);
3295 arm_subsw (code, dreg, sreg1, sreg2);
3299 arm_subsx (code, dreg, sreg1, sreg2);
3302 arm_cmpw (code, sreg1, sreg2);
3306 arm_cmpx (code, sreg1, sreg2);
3309 code = emit_addw_imm (code, dreg, sreg1, imm);
3313 code = emit_addx_imm (code, dreg, sreg1, imm);
3316 code = emit_subw_imm (code, dreg, sreg1, imm);
3319 code = emit_subx_imm (code, dreg, sreg1, imm);
3322 code = emit_andw_imm (code, dreg, sreg1, imm);
3326 code = emit_andx_imm (code, dreg, sreg1, imm);
3329 code = emit_orrw_imm (code, dreg, sreg1, imm);
3332 code = emit_orrx_imm (code, dreg, sreg1, imm);
3335 code = emit_eorw_imm (code, dreg, sreg1, imm);
3338 code = emit_eorx_imm (code, dreg, sreg1, imm);
3340 case OP_ICOMPARE_IMM:
3341 code = emit_cmpw_imm (code, sreg1, imm);
3343 case OP_LCOMPARE_IMM:
3344 case OP_COMPARE_IMM:
3346 arm_cmpx (code, sreg1, ARMREG_RZR);
3348 // FIXME: 32 vs 64 bit issues for 0xffffffff
3349 code = emit_imm64 (code, ARMREG_LR, imm);
3350 arm_cmpx (code, sreg1, ARMREG_LR);
3354 arm_lslvw (code, dreg, sreg1, sreg2);
3357 arm_lslvx (code, dreg, sreg1, sreg2);
3360 arm_asrvw (code, dreg, sreg1, sreg2);
3363 arm_asrvx (code, dreg, sreg1, sreg2);
3366 arm_lsrvw (code, dreg, sreg1, sreg2);
3369 arm_lsrvx (code, dreg, sreg1, sreg2);
3373 arm_movx (code, dreg, sreg1);
3375 arm_lslw (code, dreg, sreg1, imm);
3379 arm_movx (code, dreg, sreg1);
3381 arm_lslx (code, dreg, sreg1, imm);
3385 arm_movx (code, dreg, sreg1);
3387 arm_asrw (code, dreg, sreg1, imm);
3392 arm_movx (code, dreg, sreg1);
3394 arm_asrx (code, dreg, sreg1, imm);
3396 case OP_ISHR_UN_IMM:
3398 arm_movx (code, dreg, sreg1);
3400 arm_lsrw (code, dreg, sreg1, imm);
3403 case OP_LSHR_UN_IMM:
3405 arm_movx (code, dreg, sreg1);
3407 arm_lsrx (code, dreg, sreg1, imm);
3412 arm_sxtwx (code, dreg, sreg1);
3415 /* Clean out the upper word */
3416 arm_movw (code, dreg, sreg1);
3419 arm_lslx (code, dreg, sreg1, imm);
3422 /* MULTIPLY/DIVISION */
3425 // FIXME: Optimize this
3426 /* Check for zero */
3427 arm_cmpx_imm (code, sreg2, 0);
3428 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3429 /* Check for INT_MIN/-1 */
3430 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3431 arm_cmpx (code, sreg1, ARMREG_IP0);
3432 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3433 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3434 arm_cmpx (code, sreg2, ARMREG_IP0);
3435 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3436 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3437 arm_cmpx_imm (code, ARMREG_IP0, 1);
3438 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3439 if (ins->opcode == OP_IREM) {
3440 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3441 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3443 arm_sdivw (code, dreg, sreg1, sreg2);
3447 arm_cmpx_imm (code, sreg2, 0);
3448 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3449 arm_udivw (code, dreg, sreg1, sreg2);
3452 arm_cmpx_imm (code, sreg2, 0);
3453 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3454 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3455 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3459 // FIXME: Optimize this
3460 /* Check for zero */
3461 arm_cmpx_imm (code, sreg2, 0);
3462 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3463 /* Check for INT64_MIN/-1 */
3464 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3465 arm_cmpx (code, sreg1, ARMREG_IP0);
3466 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3467 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3468 arm_cmpx (code, sreg2, ARMREG_IP0);
3469 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3470 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3471 arm_cmpx_imm (code, ARMREG_IP0, 1);
3472 /* 64 bit uses ArithmeticException */
3473 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3474 if (ins->opcode == OP_LREM) {
3475 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3476 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3478 arm_sdivx (code, dreg, sreg1, sreg2);
3482 arm_cmpx_imm (code, sreg2, 0);
3483 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3484 arm_udivx (code, dreg, sreg1, sreg2);
3487 arm_cmpx_imm (code, sreg2, 0);
3488 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3489 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3490 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3493 arm_mulw (code, dreg, sreg1, sreg2);
3496 arm_mulx (code, dreg, sreg1, sreg2);
3499 code = emit_imm (code, ARMREG_LR, imm);
3500 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3504 code = emit_imm (code, ARMREG_LR, imm);
3505 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3509 case OP_ICONV_TO_I1:
3510 case OP_LCONV_TO_I1:
3511 arm_sxtbx (code, dreg, sreg1);
3513 case OP_ICONV_TO_I2:
3514 case OP_LCONV_TO_I2:
3515 arm_sxthx (code, dreg, sreg1);
3517 case OP_ICONV_TO_U1:
3518 case OP_LCONV_TO_U1:
3519 arm_uxtbw (code, dreg, sreg1);
3521 case OP_ICONV_TO_U2:
3522 case OP_LCONV_TO_U2:
3523 arm_uxthw (code, dreg, sreg1);
3549 cond = opcode_to_armcond (ins->opcode);
3550 arm_cset (code, cond, dreg);
3563 cond = opcode_to_armcond (ins->opcode);
3564 arm_fcmpd (code, sreg1, sreg2);
3565 arm_cset (code, cond, dreg);
3570 case OP_LOADI1_MEMBASE:
3571 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3573 case OP_LOADU1_MEMBASE:
3574 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3576 case OP_LOADI2_MEMBASE:
3577 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3579 case OP_LOADU2_MEMBASE:
3580 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3582 case OP_LOADI4_MEMBASE:
3583 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3585 case OP_LOADU4_MEMBASE:
3586 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3588 case OP_LOAD_MEMBASE:
3589 case OP_LOADI8_MEMBASE:
3590 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3592 case OP_STOREI1_MEMBASE_IMM:
3593 case OP_STOREI2_MEMBASE_IMM:
3594 case OP_STOREI4_MEMBASE_IMM:
3595 case OP_STORE_MEMBASE_IMM:
3596 case OP_STOREI8_MEMBASE_IMM: {
3600 code = emit_imm (code, ARMREG_LR, imm);
3603 immreg = ARMREG_RZR;
3606 switch (ins->opcode) {
3607 case OP_STOREI1_MEMBASE_IMM:
3608 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3610 case OP_STOREI2_MEMBASE_IMM:
3611 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3613 case OP_STOREI4_MEMBASE_IMM:
3614 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3616 case OP_STORE_MEMBASE_IMM:
3617 case OP_STOREI8_MEMBASE_IMM:
3618 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3621 g_assert_not_reached ();
3626 case OP_STOREI1_MEMBASE_REG:
3627 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3629 case OP_STOREI2_MEMBASE_REG:
3630 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3632 case OP_STOREI4_MEMBASE_REG:
3633 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3635 case OP_STORE_MEMBASE_REG:
3636 case OP_STOREI8_MEMBASE_REG:
3637 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3641 code = emit_tls_get (code, dreg, ins->inst_offset);
3643 case OP_TLS_GET_REG:
3644 code = emit_tls_get_reg (code, dreg, sreg1);
3647 code = emit_tls_set (code, sreg1, ins->inst_offset);
3649 case OP_TLS_SET_REG:
3650 code = emit_tls_set_reg (code, sreg1, sreg2);
3654 case OP_MEMORY_BARRIER:
3657 case OP_ATOMIC_ADD_I4: {
3661 arm_ldxrw (code, ARMREG_IP0, sreg1);
3662 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3663 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3664 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3667 arm_movx (code, dreg, ARMREG_IP0);
3670 case OP_ATOMIC_ADD_I8: {
3674 arm_ldxrx (code, ARMREG_IP0, sreg1);
3675 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3676 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3677 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3680 arm_movx (code, dreg, ARMREG_IP0);
3683 case OP_ATOMIC_EXCHANGE_I4: {
3687 arm_ldxrw (code, ARMREG_IP0, sreg1);
3688 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3689 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3692 arm_movx (code, dreg, ARMREG_IP0);
3695 case OP_ATOMIC_EXCHANGE_I8: {
3699 arm_ldxrx (code, ARMREG_IP0, sreg1);
3700 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3701 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3704 arm_movx (code, dreg, ARMREG_IP0);
3707 case OP_ATOMIC_CAS_I4: {
3710 /* sreg2 is the value, sreg3 is the comparand */
3712 arm_ldxrw (code, ARMREG_IP0, sreg1);
3713 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3715 arm_bcc (code, ARMCOND_NE, 0);
3716 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3717 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3718 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3721 arm_movx (code, dreg, ARMREG_IP0);
3724 case OP_ATOMIC_CAS_I8: {
3728 arm_ldxrx (code, ARMREG_IP0, sreg1);
3729 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3731 arm_bcc (code, ARMCOND_NE, 0);
3732 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3733 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3734 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3737 arm_movx (code, dreg, ARMREG_IP0);
3740 case OP_ATOMIC_LOAD_I1: {
3741 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3742 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3744 arm_ldarb (code, ins->dreg, ARMREG_LR);
3745 arm_sxtbx (code, ins->dreg, ins->dreg);
3748 case OP_ATOMIC_LOAD_U1: {
3749 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3750 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3752 arm_ldarb (code, ins->dreg, ARMREG_LR);
3753 arm_uxtbx (code, ins->dreg, ins->dreg);
3756 case OP_ATOMIC_LOAD_I2: {
3757 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3758 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3760 arm_ldarh (code, ins->dreg, ARMREG_LR);
3761 arm_sxthx (code, ins->dreg, ins->dreg);
3764 case OP_ATOMIC_LOAD_U2: {
3765 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3766 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3768 arm_ldarh (code, ins->dreg, ARMREG_LR);
3769 arm_uxthx (code, ins->dreg, ins->dreg);
3772 case OP_ATOMIC_LOAD_I4: {
3773 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3774 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3776 arm_ldarw (code, ins->dreg, ARMREG_LR);
3777 arm_sxtwx (code, ins->dreg, ins->dreg);
3780 case OP_ATOMIC_LOAD_U4: {
3781 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3782 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3784 arm_ldarw (code, ins->dreg, ARMREG_LR);
3785 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3788 case OP_ATOMIC_LOAD_I8:
3789 case OP_ATOMIC_LOAD_U8: {
3790 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3791 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3793 arm_ldarx (code, ins->dreg, ARMREG_LR);
3796 case OP_ATOMIC_LOAD_R4: {
3797 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3798 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3801 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3802 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3804 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3805 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3806 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3810 case OP_ATOMIC_LOAD_R8: {
3811 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3812 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3814 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3815 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3818 case OP_ATOMIC_STORE_I1:
3819 case OP_ATOMIC_STORE_U1: {
3820 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3821 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3822 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3826 case OP_ATOMIC_STORE_I2:
3827 case OP_ATOMIC_STORE_U2: {
3828 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3829 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3830 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3834 case OP_ATOMIC_STORE_I4:
3835 case OP_ATOMIC_STORE_U4: {
3836 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3837 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3838 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3842 case OP_ATOMIC_STORE_I8:
3843 case OP_ATOMIC_STORE_U8: {
3844 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3845 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3846 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3850 case OP_ATOMIC_STORE_R4: {
3851 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3853 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3854 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3856 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3857 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3858 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3860 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3864 case OP_ATOMIC_STORE_R8: {
3865 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3866 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3867 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3868 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
3875 guint64 imm = *(guint64*)ins->inst_p0;
3878 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3880 code = emit_imm64 (code, ARMREG_LR, imm);
3881 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3886 guint64 imm = *(guint32*)ins->inst_p0;
3888 code = emit_imm64 (code, ARMREG_LR, imm);
3890 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3892 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3893 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3897 case OP_LOADR8_MEMBASE:
3898 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3900 case OP_LOADR4_MEMBASE:
3902 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3904 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3905 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3908 case OP_STORER8_MEMBASE_REG:
3909 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3911 case OP_STORER4_MEMBASE_REG:
3913 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3915 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3916 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3921 arm_fmovd (code, dreg, sreg1);
3925 arm_fmovs (code, dreg, sreg1);
3927 case OP_MOVE_F_TO_I4:
3929 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3931 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3932 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3935 case OP_MOVE_I4_TO_F:
3937 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3939 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3940 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3943 case OP_MOVE_F_TO_I8:
3944 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3946 case OP_MOVE_I8_TO_F:
3947 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3950 arm_fcmpd (code, sreg1, sreg2);
3953 arm_fcmps (code, sreg1, sreg2);
3955 case OP_FCONV_TO_I1:
3956 arm_fcvtzs_dx (code, dreg, sreg1);
3957 arm_sxtbx (code, dreg, dreg);
3959 case OP_FCONV_TO_U1:
3960 arm_fcvtzu_dx (code, dreg, sreg1);
3961 arm_uxtbw (code, dreg, dreg);
3963 case OP_FCONV_TO_I2:
3964 arm_fcvtzs_dx (code, dreg, sreg1);
3965 arm_sxthx (code, dreg, dreg);
3967 case OP_FCONV_TO_U2:
3968 arm_fcvtzu_dx (code, dreg, sreg1);
3969 arm_uxthw (code, dreg, dreg);
3971 case OP_FCONV_TO_I4:
3972 arm_fcvtzs_dx (code, dreg, sreg1);
3973 arm_sxtwx (code, dreg, dreg);
3975 case OP_FCONV_TO_U4:
3976 arm_fcvtzu_dx (code, dreg, sreg1);
3978 case OP_FCONV_TO_I8:
3979 arm_fcvtzs_dx (code, dreg, sreg1);
3981 case OP_FCONV_TO_U8:
3982 arm_fcvtzu_dx (code, dreg, sreg1);
3984 case OP_FCONV_TO_R4:
3986 arm_fcvt_ds (code, dreg, sreg1);
3988 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3989 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3992 case OP_ICONV_TO_R4:
3994 arm_scvtf_rw_to_s (code, dreg, sreg1);
3996 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
3997 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
4000 case OP_LCONV_TO_R4:
4002 arm_scvtf_rx_to_s (code, dreg, sreg1);
4004 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
4005 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
4008 case OP_ICONV_TO_R8:
4009 arm_scvtf_rw_to_d (code, dreg, sreg1);
4011 case OP_LCONV_TO_R8:
4012 arm_scvtf_rx_to_d (code, dreg, sreg1);
4014 case OP_ICONV_TO_R_UN:
4015 arm_ucvtf_rw_to_d (code, dreg, sreg1);
4017 case OP_LCONV_TO_R_UN:
4018 arm_ucvtf_rx_to_d (code, dreg, sreg1);
4021 arm_fadd_d (code, dreg, sreg1, sreg2);
4024 arm_fsub_d (code, dreg, sreg1, sreg2);
4027 arm_fmul_d (code, dreg, sreg1, sreg2);
4030 arm_fdiv_d (code, dreg, sreg1, sreg2);
4034 g_assert_not_reached ();
4037 arm_fneg_d (code, dreg, sreg1);
4039 case OP_ARM_SETFREG_R4:
4040 arm_fcvt_ds (code, dreg, sreg1);
4043 /* Check for infinity */
4044 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
4045 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
4046 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
4047 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
4048 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
4049 /* Check for nans */
4050 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
4051 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
4052 arm_fmovd (code, dreg, sreg1);
4057 arm_fadd_s (code, dreg, sreg1, sreg2);
4060 arm_fsub_s (code, dreg, sreg1, sreg2);
4063 arm_fmul_s (code, dreg, sreg1, sreg2);
4066 arm_fdiv_s (code, dreg, sreg1, sreg2);
4069 arm_fneg_s (code, dreg, sreg1);
4071 case OP_RCONV_TO_I1:
4072 arm_fcvtzs_sx (code, dreg, sreg1);
4073 arm_sxtbx (code, dreg, dreg);
4075 case OP_RCONV_TO_U1:
4076 arm_fcvtzu_sx (code, dreg, sreg1);
4077 arm_uxtbw (code, dreg, dreg);
4079 case OP_RCONV_TO_I2:
4080 arm_fcvtzs_sx (code, dreg, sreg1);
4081 arm_sxthx (code, dreg, dreg);
4083 case OP_RCONV_TO_U2:
4084 arm_fcvtzu_sx (code, dreg, sreg1);
4085 arm_uxthw (code, dreg, dreg);
4087 case OP_RCONV_TO_I4:
4088 arm_fcvtzs_sx (code, dreg, sreg1);
4089 arm_sxtwx (code, dreg, dreg);
4091 case OP_RCONV_TO_U4:
4092 arm_fcvtzu_sx (code, dreg, sreg1);
4094 case OP_RCONV_TO_I8:
4095 arm_fcvtzs_sx (code, dreg, sreg1);
4097 case OP_RCONV_TO_U8:
4098 arm_fcvtzu_sx (code, dreg, sreg1);
4100 case OP_RCONV_TO_R8:
4101 arm_fcvt_sd (code, dreg, sreg1);
4103 case OP_RCONV_TO_R4:
4105 arm_fmovs (code, dreg, sreg1);
4117 cond = opcode_to_armcond (ins->opcode);
4118 arm_fcmps (code, sreg1, sreg2);
4119 arm_cset (code, cond, dreg);
4130 call = (MonoCallInst*)ins;
4131 if (ins->flags & MONO_INST_HAS_METHOD)
4132 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4134 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4135 code = emit_move_return_value (cfg, code, ins);
4137 case OP_VOIDCALL_REG:
4143 arm_blrx (code, sreg1);
4144 code = emit_move_return_value (cfg, code, ins);
4146 case OP_VOIDCALL_MEMBASE:
4147 case OP_CALL_MEMBASE:
4148 case OP_LCALL_MEMBASE:
4149 case OP_FCALL_MEMBASE:
4150 case OP_RCALL_MEMBASE:
4151 case OP_VCALL2_MEMBASE:
4152 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4153 arm_blrx (code, ARMREG_IP0);
4154 code = emit_move_return_value (cfg, code, ins);
4157 MonoCallInst *call = (MonoCallInst*)ins;
4159 g_assert (!cfg->method->save_lmf);
4161 // FIXME: Copy stack arguments
4163 /* Restore registers */
4164 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4167 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4169 if (cfg->compile_aot) {
4170 /* This is not a PLT patch */
4171 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4172 arm_brx (code, ARMREG_IP0);
4174 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4177 ins->flags |= MONO_INST_GC_CALLSITE;
4178 ins->backend.pc_offset = code - cfg->native_code;
4182 g_assert (cfg->arch.cinfo);
4183 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4184 arm_strx (code, ARMREG_IP0, sreg1, 0);
4187 MonoInst *var = cfg->dyn_call_var;
4188 guint8 *labels [16];
4192 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4193 * sreg2 is the function to call.
4196 g_assert (var->opcode == OP_REGOFFSET);
4198 arm_movx (code, ARMREG_LR, sreg1);
4199 arm_movx (code, ARMREG_IP1, sreg2);
4201 /* Save args buffer */
4202 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4204 /* Set fp argument regs */
4205 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4206 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4208 arm_bcc (code, ARMCOND_EQ, 0);
4209 for (i = 0; i < 8; ++i)
4210 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4211 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4213 /* Set stack args */
4214 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4215 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4216 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4219 /* Set argument registers + r8 */
4220 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4223 arm_blrx (code, ARMREG_IP1);
4226 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4227 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4228 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4229 /* Save fp result */
4230 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4231 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4233 arm_bcc (code, ARMCOND_EQ, 0);
4234 for (i = 0; i < 8; ++i)
4235 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4236 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4240 case OP_GENERIC_CLASS_INIT: {
4241 static int byte_offset = -1;
4242 static guint8 bitmask;
4245 if (byte_offset < 0)
4246 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4248 /* Load vtable->initialized */
4249 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4250 // FIXME: No andx_imm yet */
4251 code = mono_arm_emit_imm64 (code, ARMREG_IP1, bitmask);
4252 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
4254 arm_cbnzx (code, ARMREG_IP0, 0);
4257 g_assert (sreg1 == ARMREG_R0);
4258 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4259 (gpointer)"mono_generic_class_init");
4261 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4266 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4269 case OP_NOT_REACHED:
4272 case OP_IL_SEQ_POINT:
4273 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4278 case OP_COND_EXC_IC:
4279 case OP_COND_EXC_OV:
4280 case OP_COND_EXC_IOV:
4281 case OP_COND_EXC_NC:
4282 case OP_COND_EXC_INC:
4283 case OP_COND_EXC_NO:
4284 case OP_COND_EXC_INO:
4285 case OP_COND_EXC_EQ:
4286 case OP_COND_EXC_IEQ:
4287 case OP_COND_EXC_NE_UN:
4288 case OP_COND_EXC_INE_UN:
4289 case OP_COND_EXC_ILT:
4290 case OP_COND_EXC_LT:
4291 case OP_COND_EXC_ILT_UN:
4292 case OP_COND_EXC_LT_UN:
4293 case OP_COND_EXC_IGT:
4294 case OP_COND_EXC_GT:
4295 case OP_COND_EXC_IGT_UN:
4296 case OP_COND_EXC_GT_UN:
4297 case OP_COND_EXC_IGE:
4298 case OP_COND_EXC_GE:
4299 case OP_COND_EXC_IGE_UN:
4300 case OP_COND_EXC_GE_UN:
4301 case OP_COND_EXC_ILE:
4302 case OP_COND_EXC_LE:
4303 case OP_COND_EXC_ILE_UN:
4304 case OP_COND_EXC_LE_UN:
4305 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4308 if (sreg1 != ARMREG_R0)
4309 arm_movx (code, ARMREG_R0, sreg1);
4310 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4311 (gpointer)"mono_arch_throw_exception");
4314 if (sreg1 != ARMREG_R0)
4315 arm_movx (code, ARMREG_R0, sreg1);
4316 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4317 (gpointer)"mono_arch_rethrow_exception");
4319 case OP_CALL_HANDLER:
4320 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4322 cfg->thunk_area += THUNK_SIZE;
4324 case OP_START_HANDLER: {
4325 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4327 /* Save caller address */
4328 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4331 * Reserve a param area, see test_0_finally_param_area ().
4332 * This is needed because the param area is not set up when
4333 * we are called from EH code.
4335 if (cfg->param_area)
4336 code = emit_subx_sp_imm (code, cfg->param_area);
4340 case OP_ENDFILTER: {
4341 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4343 if (cfg->param_area)
4344 code = emit_addx_sp_imm (code, cfg->param_area);
4346 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4347 arm_movx (code, ARMREG_R0, sreg1);
4349 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4350 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4351 arm_brx (code, ARMREG_LR);
4355 if (ins->dreg != ARMREG_R0)
4356 arm_movx (code, ins->dreg, ARMREG_R0);
4358 case OP_GC_SAFE_POINT: {
4359 #if defined (USE_COOP_GC)
4362 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4363 /* Call it if it is non-null */
4365 arm_cbzx (code, ARMREG_IP1, 0);
4366 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4367 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4373 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4374 g_assert_not_reached ();
4377 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4378 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4379 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4380 g_assert_not_reached ();
4385 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4386 * insert branch islands between/inside basic blocks.
4388 if (cfg->arch.cond_branch_islands)
4389 code = emit_branch_island (cfg, code, start_offset);
4391 cfg->code_len = code - cfg->native_code;
4395 emit_move_args (MonoCompile *cfg, guint8 *code)
4402 cinfo = cfg->arch.cinfo;
4404 for (i = 0; i < cinfo->nargs; ++i) {
4405 ainfo = cinfo->args + i;
4406 ins = cfg->args [i];
4408 if (ins->opcode == OP_REGVAR) {
4409 switch (ainfo->storage) {
4411 arm_movx (code, ins->dreg, ainfo->reg);
4414 switch (ainfo->slot_size) {
4417 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4419 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4423 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4425 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4429 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4431 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4434 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4439 g_assert_not_reached ();
4443 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4444 g_assert (ins->opcode == OP_REGOFFSET);
4446 switch (ainfo->storage) {
4448 /* Stack slots for arguments have size 8 */
4449 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4452 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4455 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4460 case ArgVtypeByRefOnStack:
4461 case ArgVtypeOnStack:
4463 case ArgVtypeByRef: {
4464 MonoInst *addr_arg = ins->inst_left;
4466 if (ainfo->gsharedvt) {
4467 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4468 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4470 g_assert (ins->opcode == OP_VTARG_ADDR);
4471 g_assert (addr_arg->opcode == OP_REGOFFSET);
4472 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4476 case ArgVtypeInIRegs:
4477 for (part = 0; part < ainfo->nregs; part ++) {
4478 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4482 for (part = 0; part < ainfo->nregs; part ++) {
4483 if (ainfo->esize == 4)
4484 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4486 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4490 g_assert_not_reached ();
4500 * emit_store_regarray:
4502 * Emit code to store the registers in REGS into the appropriate elements of
4503 * the register array at BASEREG+OFFSET.
4505 static __attribute__((warn_unused_result)) guint8*
4506 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4510 for (i = 0; i < 32; ++i) {
4511 if (regs & (1 << i)) {
4512 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4513 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4515 } else if (i == ARMREG_SP) {
4516 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4517 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4519 arm_strx (code, i, basereg, offset + (i * 8));
4527 * emit_load_regarray:
4529 * Emit code to load the registers in REGS from the appropriate elements of
4530 * the register array at BASEREG+OFFSET.
4532 static __attribute__((warn_unused_result)) guint8*
4533 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4537 for (i = 0; i < 32; ++i) {
4538 if (regs & (1 << i)) {
4539 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4540 if (offset + (i * 8) < 500)
4541 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4543 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4544 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4547 } else if (i == ARMREG_SP) {
4548 g_assert_not_reached ();
4550 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4558 * emit_store_regset:
4560 * Emit code to store the registers in REGS into consecutive memory locations starting
4561 * at BASEREG+OFFSET.
4563 static __attribute__((warn_unused_result)) guint8*
4564 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4569 for (i = 0; i < 32; ++i) {
4570 if (regs & (1 << i)) {
4571 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4572 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4575 } else if (i == ARMREG_SP) {
4576 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4577 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4579 arm_strx (code, i, basereg, offset + (pos * 8));
4590 * Emit code to load the registers in REGS from consecutive memory locations starting
4591 * at BASEREG+OFFSET.
4593 static __attribute__((warn_unused_result)) guint8*
4594 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4599 for (i = 0; i < 32; ++i) {
4600 if (regs & (1 << i)) {
4601 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4602 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4605 } else if (i == ARMREG_SP) {
4606 g_assert_not_reached ();
4608 arm_ldrx (code, i, basereg, offset + (pos * 8));
4616 __attribute__((warn_unused_result)) guint8*
4617 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4619 return emit_load_regarray (code, regs, basereg, offset);
4622 __attribute__((warn_unused_result)) guint8*
4623 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4625 return emit_store_regarray (code, regs, basereg, offset);
4628 __attribute__((warn_unused_result)) guint8*
4629 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4631 return emit_store_regset (code, regs, basereg, offset);
4634 /* Same as emit_store_regset, but emit unwind info too */
4635 /* CFA_OFFSET is the offset between the CFA and basereg */
4636 static __attribute__((warn_unused_result)) guint8*
4637 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4639 int i, j, pos, nregs;
4640 guint32 cfa_regset = regs & ~no_cfa_regset;
4643 for (i = 0; i < 32; ++i) {
4645 if (regs & (1 << i)) {
4646 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4648 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4650 code = emit_strx (code, i, basereg, offset + (pos * 8));
4651 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4654 } else if (i == ARMREG_SP) {
4655 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4656 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4658 code = emit_strx (code, i, basereg, offset + (pos * 8));
4661 for (j = 0; j < nregs; ++j) {
4662 if (cfa_regset & (1 << (i + j)))
4663 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4676 * Emit code to initialize an LMF structure at LMF_OFFSET.
4680 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4683 * The LMF should contain all the state required to be able to reconstruct the machine state
4684 * at the current point of execution. Since the LMF is only read during EH, only callee
4685 * saved etc. registers need to be saved.
4686 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4687 * need to be restored during EH.
4691 arm_adrx (code, ARMREG_LR, code);
4692 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4693 /* gregs + fp + sp */
4694 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4695 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4701 mono_arch_emit_prolog (MonoCompile *cfg)
4703 MonoMethod *method = cfg->method;
4704 MonoMethodSignature *sig;
4707 int cfa_offset, max_offset;
4709 sig = mono_method_signature (method);
4710 cfg->code_size = 256 + sig->param_count * 64;
4711 code = cfg->native_code = g_malloc (cfg->code_size);
4713 /* This can be unaligned */
4714 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4720 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4723 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4724 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4726 /* sp -= cfg->stack_offset */
4727 /* This clobbers ip0/ip1 */
4728 code = emit_subx_sp_imm (code, cfg->stack_offset);
4729 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4731 cfa_offset += cfg->stack_offset;
4732 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4733 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4734 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4735 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4736 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4737 if (cfg->param_area) {
4738 /* The param area is below the frame pointer */
4739 code = emit_subx_sp_imm (code, cfg->param_area);
4742 if (cfg->method->save_lmf) {
4743 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4746 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4749 /* Setup args reg */
4750 if (cfg->arch.args_reg) {
4751 /* The register was already saved above */
4752 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4755 /* Save return area addr received in R8 */
4756 if (cfg->vret_addr) {
4757 MonoInst *ins = cfg->vret_addr;
4759 g_assert (ins->opcode == OP_REGOFFSET);
4760 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4763 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4764 if (cfg->rgctx_var) {
4765 MonoInst *ins = cfg->rgctx_var;
4767 g_assert (ins->opcode == OP_REGOFFSET);
4769 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4773 * Move arguments to their registers/stack locations.
4775 code = emit_move_args (cfg, code);
4777 /* Initialize seq_point_info_var */
4778 if (cfg->arch.seq_point_info_var) {
4779 MonoInst *ins = cfg->arch.seq_point_info_var;
4781 /* Initialize the variable from a GOT slot */
4782 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4783 g_assert (ins->opcode == OP_REGOFFSET);
4784 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4786 /* Initialize ss_tramp_var */
4787 ins = cfg->arch.ss_tramp_var;
4788 g_assert (ins->opcode == OP_REGOFFSET);
4790 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4791 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4795 if (cfg->arch.ss_tramp_var) {
4796 /* Initialize ss_tramp_var */
4797 ins = cfg->arch.ss_tramp_var;
4798 g_assert (ins->opcode == OP_REGOFFSET);
4800 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4801 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4804 if (cfg->arch.bp_tramp_var) {
4805 /* Initialize bp_tramp_var */
4806 ins = cfg->arch.bp_tramp_var;
4807 g_assert (ins->opcode == OP_REGOFFSET);
4809 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4810 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4815 if (cfg->opt & MONO_OPT_BRANCH) {
4816 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4818 bb->max_offset = max_offset;
4820 MONO_BB_FOR_EACH_INS (bb, ins) {
4821 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4825 if (max_offset > 0x3ffff * 4)
4826 cfg->arch.cond_branch_islands = TRUE;
4832 realloc_code (MonoCompile *cfg, int size)
4834 while (cfg->code_len + size > (cfg->code_size - 16)) {
4835 cfg->code_size *= 2;
4836 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4837 cfg->stat_code_reallocs++;
4839 return cfg->native_code + cfg->code_len;
4843 mono_arch_emit_epilog (MonoCompile *cfg)
4846 int max_epilog_size;
4850 max_epilog_size = 16 + 20*4;
4851 code = realloc_code (cfg, max_epilog_size);
4853 if (cfg->method->save_lmf) {
4854 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4857 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4860 /* Load returned vtypes into registers if needed */
4861 cinfo = cfg->arch.cinfo;
4862 switch (cinfo->ret.storage) {
4863 case ArgVtypeInIRegs: {
4864 MonoInst *ins = cfg->ret;
4866 for (i = 0; i < cinfo->ret.nregs; ++i)
4867 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4871 MonoInst *ins = cfg->ret;
4873 for (i = 0; i < cinfo->ret.nregs; ++i) {
4874 if (cinfo->ret.esize == 4)
4875 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4877 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4886 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4888 arm_retx (code, ARMREG_LR);
4890 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4892 cfg->code_len = code - cfg->native_code;
4896 mono_arch_emit_exceptions (MonoCompile *cfg)
4899 MonoClass *exc_class;
4901 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4902 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4903 int i, id, size = 0;
4905 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4906 exc_throw_pos [i] = NULL;
4907 exc_throw_found [i] = 0;
4910 for (ji = cfg->patch_info; ji; ji = ji->next) {
4911 if (ji->type == MONO_PATCH_INFO_EXC) {
4912 i = mini_exception_id_by_name (ji->data.target);
4913 if (!exc_throw_found [i]) {
4915 exc_throw_found [i] = TRUE;
4920 code = realloc_code (cfg, size);
4922 /* Emit code to raise corlib exceptions */
4923 for (ji = cfg->patch_info; ji; ji = ji->next) {
4924 if (ji->type != MONO_PATCH_INFO_EXC)
4927 ip = cfg->native_code + ji->ip.i;
4929 id = mini_exception_id_by_name (ji->data.target);
4931 if (exc_throw_pos [id]) {
4932 /* ip points to the bcc () in OP_COND_EXC_... */
4933 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4934 ji->type = MONO_PATCH_INFO_NONE;
4938 exc_throw_pos [id] = code;
4939 arm_patch_rel (ip, code, ji->relocation);
4941 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4943 /* r0 = type token */
4944 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4945 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4947 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4948 /* Branch to the corlib exception throwing trampoline */
4949 ji->ip.i = code - cfg->native_code;
4950 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4951 ji->data.name = "mono_arch_throw_corlib_exception";
4952 ji->relocation = MONO_R_ARM64_BL;
4954 cfg->thunk_area += THUNK_SIZE;
4957 cfg->code_len = code - cfg->native_code;
4959 g_assert (cfg->code_len < cfg->code_size);
4963 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4969 mono_arch_print_tree (MonoInst *tree, int arity)
4975 mono_arch_get_patch_offset (guint8 *code)
4981 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4982 gpointer fail_tramp)
4984 int i, buf_len, imt_reg;
4988 printf ("building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4989 for (i = 0; i < count; ++i) {
4990 MonoIMTCheckItem *item = imt_entries [i];
4991 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
4996 for (i = 0; i < count; ++i) {
4997 MonoIMTCheckItem *item = imt_entries [i];
4998 if (item->is_equals) {
4999 gboolean fail_case = !item->check_target_idx && fail_tramp;
5001 if (item->check_target_idx || fail_case) {
5002 if (!item->compare_done || fail_case) {
5003 buf_len += 4 * 4 + 4;
5006 if (item->has_target_code) {
5023 buf = mono_method_alloc_generic_virtual_trampoline (domain, buf_len);
5025 buf = mono_domain_code_reserve (domain, buf_len);
5029 * We are called by JITted code, which passes in the IMT argument in
5030 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
5033 imt_reg = MONO_ARCH_RGCTX_REG;
5034 for (i = 0; i < count; ++i) {
5035 MonoIMTCheckItem *item = imt_entries [i];
5037 item->code_target = code;
5039 if (item->is_equals) {
5041 * Check the imt argument against item->key, if equals, jump to either
5042 * item->value.target_code or to vtable [item->value.vtable_slot].
5043 * If fail_tramp is set, jump to it if not-equals.
5045 gboolean fail_case = !item->check_target_idx && fail_tramp;
5047 if (item->check_target_idx || fail_case) {
5048 /* Compare imt_reg with item->key */
5049 if (!item->compare_done || fail_case) {
5050 // FIXME: Optimize this
5051 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5052 arm_cmpx (code, imt_reg, ARMREG_IP0);
5054 item->jmp_code = code;
5055 arm_bcc (code, ARMCOND_NE, 0);
5056 /* Jump to target if equals */
5057 if (item->has_target_code) {
5058 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
5059 arm_brx (code, ARMREG_IP0);
5061 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5063 code = emit_imm64 (code, ARMREG_IP0, imm);
5064 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5065 arm_brx (code, ARMREG_IP0);
5069 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5070 item->jmp_code = NULL;
5071 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5072 arm_brx (code, ARMREG_IP0);
5075 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5077 code = emit_imm64 (code, ARMREG_IP0, imm);
5078 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5079 arm_brx (code, ARMREG_IP0);
5082 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5083 arm_cmpx (code, imt_reg, ARMREG_IP0);
5084 item->jmp_code = code;
5085 arm_bcc (code, ARMCOND_HS, 0);
5088 /* Patch the branches */
5089 for (i = 0; i < count; ++i) {
5090 MonoIMTCheckItem *item = imt_entries [i];
5091 if (item->jmp_code && item->check_target_idx)
5092 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5095 g_assert ((code - buf) < buf_len);
5097 mono_arch_flush_icache (buf, code - buf);
5103 mono_arch_get_trampolines (gboolean aot)
5105 return mono_arm_get_exception_trampolines (aot);
5108 #else /* DISABLE_JIT */
5111 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5112 gpointer fail_tramp)
5114 g_assert_not_reached ();
5118 #endif /* !DISABLE_JIT */
5120 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5123 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5126 guint32 native_offset = ip - (guint8*)ji->code_start;
5129 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5131 g_assert (native_offset % 4 == 0);
5132 g_assert (info->bp_addrs [native_offset / 4] == 0);
5133 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5135 /* ip points to an ldrx */
5137 arm_blrx (code, ARMREG_IP0);
5138 mono_arch_flush_icache (ip, code - ip);
5143 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5148 guint32 native_offset = ip - (guint8*)ji->code_start;
5149 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5151 g_assert (native_offset % 4 == 0);
5152 info->bp_addrs [native_offset / 4] = NULL;
5154 /* ip points to an ldrx */
5157 mono_arch_flush_icache (ip, code - ip);
5162 mono_arch_start_single_stepping (void)
5164 ss_trampoline = mini_get_single_step_trampoline ();
5168 mono_arch_stop_single_stepping (void)
5170 ss_trampoline = NULL;
5174 mono_arch_is_single_step_event (void *info, void *sigctx)
5176 /* We use soft breakpoints on arm64 */
5181 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5183 /* We use soft breakpoints on arm64 */
5188 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5190 g_assert_not_reached ();
5194 mono_arch_skip_single_step (MonoContext *ctx)
5196 g_assert_not_reached ();
5200 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5205 // FIXME: Add a free function
5207 mono_domain_lock (domain);
5208 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5210 mono_domain_unlock (domain);
5213 ji = mono_jit_info_table_find (domain, (char*)code);
5216 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5218 info->ss_tramp_addr = &ss_trampoline;
5220 mono_domain_lock (domain);
5221 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5223 mono_domain_unlock (domain);
5230 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5232 ext->lmf.previous_lmf = prev_lmf;
5233 /* Mark that this is a MonoLMFExt */
5234 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5235 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5238 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5241 mono_arch_opcode_supported (int opcode)
5244 case OP_ATOMIC_ADD_I4:
5245 case OP_ATOMIC_ADD_I8:
5246 case OP_ATOMIC_EXCHANGE_I4:
5247 case OP_ATOMIC_EXCHANGE_I8:
5248 case OP_ATOMIC_CAS_I4:
5249 case OP_ATOMIC_CAS_I8:
5250 case OP_ATOMIC_LOAD_I1:
5251 case OP_ATOMIC_LOAD_I2:
5252 case OP_ATOMIC_LOAD_I4:
5253 case OP_ATOMIC_LOAD_I8:
5254 case OP_ATOMIC_LOAD_U1:
5255 case OP_ATOMIC_LOAD_U2:
5256 case OP_ATOMIC_LOAD_U4:
5257 case OP_ATOMIC_LOAD_U8:
5258 case OP_ATOMIC_LOAD_R4:
5259 case OP_ATOMIC_LOAD_R8:
5260 case OP_ATOMIC_STORE_I1:
5261 case OP_ATOMIC_STORE_I2:
5262 case OP_ATOMIC_STORE_I4:
5263 case OP_ATOMIC_STORE_I8:
5264 case OP_ATOMIC_STORE_U1:
5265 case OP_ATOMIC_STORE_U2:
5266 case OP_ATOMIC_STORE_U4:
5267 case OP_ATOMIC_STORE_U8:
5268 case OP_ATOMIC_STORE_R4:
5269 case OP_ATOMIC_STORE_R8:
5277 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5279 return get_call_info (mp, sig);
5283 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
5290 bp = MONO_CONTEXT_GET_BP (ctx);
5291 lr_loc = (gpointer*)(bp + clause->exvar_offset);
5293 old_value = *lr_loc;
5294 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
5297 *lr_loc = new_value;