2 * mini-arm64.c: ARM64 backend for the Mono code generator
4 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
9 * Paolo Molaro (lupus@ximian.com)
10 * Dietmar Maurer (dietmar@ximian.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
19 #include "cpu-arm64.h"
22 #include <mono/arch/arm64/arm64-codegen.h>
23 #include <mono/utils/mono-mmap.h>
24 #include <mono/utils/mono-memory-model.h>
25 #include <mono/metadata/abi-details.h>
30 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
31 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
32 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
35 * - ip0/ip1/lr are used as temporary registers
36 * - r27 is used as the rgctx/imt register
37 * - r28 is used to access arguments passed on the stack
38 * - d15/d16 are used as fp temporary registers
41 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
43 #define FP_TEMP_REG ARMREG_D16
44 #define FP_TEMP_REG2 ARMREG_D17
46 #define THUNK_SIZE (4 * 4)
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 static gboolean ios_abi;
56 static __attribute__((warn_unused_result)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
59 mono_arch_regname (int reg)
61 static const char * rnames[] = {
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
63 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
64 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
67 if (reg >= 0 && reg < 32)
73 mono_arch_fregname (int reg)
75 static const char * rnames[] = {
76 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
77 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
78 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
81 if (reg >= 0 && reg < 32)
87 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
93 #define MAX_ARCH_DELEGATE_PARAMS 7
96 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
101 start = code = mono_global_codeman_reserve (12);
103 /* Replace the this argument with the target */
104 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
105 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
106 arm_brx (code, ARMREG_IP0);
108 g_assert ((code - start) <= 12);
110 mono_arch_flush_icache (start, 12);
114 size = 8 + param_count * 4;
115 start = code = mono_global_codeman_reserve (size);
117 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
118 /* slide down the arguments */
119 for (i = 0; i < param_count; ++i)
120 arm_movx (code, i, i + 1);
121 arm_brx (code, ARMREG_IP0);
123 g_assert ((code - start) <= size);
125 mono_arch_flush_icache (start, size);
129 *code_size = code - start;
135 * mono_arch_get_delegate_invoke_impls:
137 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
141 mono_arch_get_delegate_invoke_impls (void)
149 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
150 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
152 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
153 code = get_delegate_invoke_impl (FALSE, i, &code_len);
154 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
155 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
165 guint8 *code, *start;
168 * vtypes are returned in registers, or using the dedicated r8 register, so
169 * they can be supported by delegate invokes.
173 static guint8* cached = NULL;
179 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
181 start = get_delegate_invoke_impl (TRUE, 0, NULL);
182 mono_memory_barrier ();
186 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
189 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
191 for (i = 0; i < sig->param_count; ++i)
192 if (!mono_is_regsize_var (sig->params [i]))
195 code = cache [sig->param_count];
200 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
201 start = mono_aot_get_trampoline (name);
204 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
206 mono_memory_barrier ();
207 cache [sig->param_count] = start;
215 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
221 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
223 return (gpointer)regs [ARMREG_R0];
227 mono_arch_cpu_init (void)
232 mono_arch_init (void)
234 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
235 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
238 bp_trampoline = mini_get_breakpoint_trampoline ();
240 mono_arm_gsharedvt_init ();
242 #if defined(TARGET_IOS)
248 mono_arch_cleanup (void)
253 mono_arch_cpu_optimizations (guint32 *exclude_mask)
260 mono_arch_cpu_enumerate_simd_versions (void)
266 mono_arch_register_lowlevel_calls (void)
271 mono_arch_finish_init (void)
275 /* The maximum length is 2 instructions */
277 emit_imm (guint8 *code, int dreg, int imm)
279 // FIXME: Optimize this
282 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
283 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
285 arm_movzx (code, dreg, imm & 0xffff, 0);
287 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
293 /* The maximum length is 4 instructions */
295 emit_imm64 (guint8 *code, int dreg, guint64 imm)
297 // FIXME: Optimize this
298 arm_movzx (code, dreg, imm & 0xffff, 0);
299 if ((imm >> 16) & 0xffff)
300 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
301 if ((imm >> 32) & 0xffff)
302 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
303 if ((imm >> 48) & 0xffff)
304 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
310 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
312 return emit_imm64 (code, dreg, imm);
318 * Emit a patchable code sequence for constructing a 64 bit immediate.
321 emit_imm64_template (guint8 *code, int dreg)
323 arm_movzx (code, dreg, 0, 0);
324 arm_movkx (code, dreg, 0, 16);
325 arm_movkx (code, dreg, 0, 32);
326 arm_movkx (code, dreg, 0, 48);
331 static inline __attribute__((warn_unused_result)) guint8*
332 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
334 if (!arm_is_arith_imm (imm)) {
335 code = emit_imm (code, ARMREG_LR, imm);
336 arm_addw (code, dreg, sreg, ARMREG_LR);
338 arm_addw_imm (code, dreg, sreg, imm);
343 static inline __attribute__((warn_unused_result)) guint8*
344 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
346 if (!arm_is_arith_imm (imm)) {
347 code = emit_imm (code, ARMREG_LR, imm);
348 arm_addx (code, dreg, sreg, ARMREG_LR);
350 arm_addx_imm (code, dreg, sreg, imm);
355 static inline __attribute__((warn_unused_result)) guint8*
356 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
358 if (!arm_is_arith_imm (imm)) {
359 code = emit_imm (code, ARMREG_LR, imm);
360 arm_subw (code, dreg, sreg, ARMREG_LR);
362 arm_subw_imm (code, dreg, sreg, imm);
367 static inline __attribute__((warn_unused_result)) guint8*
368 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
370 if (!arm_is_arith_imm (imm)) {
371 code = emit_imm (code, ARMREG_LR, imm);
372 arm_subx (code, dreg, sreg, ARMREG_LR);
374 arm_subx_imm (code, dreg, sreg, imm);
379 /* Emit sp+=imm. Clobbers ip0/ip1 */
380 static inline __attribute__((warn_unused_result)) guint8*
381 emit_addx_sp_imm (guint8 *code, int imm)
383 code = emit_imm (code, ARMREG_IP0, imm);
384 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
385 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
386 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
390 /* Emit sp-=imm. Clobbers ip0/ip1 */
391 static inline __attribute__((warn_unused_result)) guint8*
392 emit_subx_sp_imm (guint8 *code, int imm)
394 code = emit_imm (code, ARMREG_IP0, imm);
395 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
396 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
397 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
401 static inline __attribute__((warn_unused_result)) guint8*
402 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
405 code = emit_imm (code, ARMREG_LR, imm);
406 arm_andw (code, dreg, sreg, ARMREG_LR);
411 static inline __attribute__((warn_unused_result)) guint8*
412 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
415 code = emit_imm (code, ARMREG_LR, imm);
416 arm_andx (code, dreg, sreg, ARMREG_LR);
421 static inline __attribute__((warn_unused_result)) guint8*
422 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
425 code = emit_imm (code, ARMREG_LR, imm);
426 arm_orrw (code, dreg, sreg, ARMREG_LR);
431 static inline __attribute__((warn_unused_result)) guint8*
432 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
435 code = emit_imm (code, ARMREG_LR, imm);
436 arm_orrx (code, dreg, sreg, ARMREG_LR);
441 static inline __attribute__((warn_unused_result)) guint8*
442 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
445 code = emit_imm (code, ARMREG_LR, imm);
446 arm_eorw (code, dreg, sreg, ARMREG_LR);
451 static inline __attribute__((warn_unused_result)) guint8*
452 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
455 code = emit_imm (code, ARMREG_LR, imm);
456 arm_eorx (code, dreg, sreg, ARMREG_LR);
461 static inline __attribute__((warn_unused_result)) guint8*
462 emit_cmpw_imm (guint8 *code, int sreg, int imm)
465 arm_cmpw (code, sreg, ARMREG_RZR);
468 code = emit_imm (code, ARMREG_LR, imm);
469 arm_cmpw (code, sreg, ARMREG_LR);
475 static inline __attribute__((warn_unused_result)) guint8*
476 emit_cmpx_imm (guint8 *code, int sreg, int imm)
479 arm_cmpx (code, sreg, ARMREG_RZR);
482 code = emit_imm (code, ARMREG_LR, imm);
483 arm_cmpx (code, sreg, ARMREG_LR);
489 static inline __attribute__((warn_unused_result)) guint8*
490 emit_strb (guint8 *code, int rt, int rn, int imm)
492 if (arm_is_strb_imm (imm)) {
493 arm_strb (code, rt, rn, imm);
495 g_assert (rt != ARMREG_IP0);
496 g_assert (rn != ARMREG_IP0);
497 code = emit_imm (code, ARMREG_IP0, imm);
498 arm_strb_reg (code, rt, rn, ARMREG_IP0);
503 static inline __attribute__((warn_unused_result)) guint8*
504 emit_strh (guint8 *code, int rt, int rn, int imm)
506 if (arm_is_strh_imm (imm)) {
507 arm_strh (code, rt, rn, imm);
509 g_assert (rt != ARMREG_IP0);
510 g_assert (rn != ARMREG_IP0);
511 code = emit_imm (code, ARMREG_IP0, imm);
512 arm_strh_reg (code, rt, rn, ARMREG_IP0);
517 static inline __attribute__((warn_unused_result)) guint8*
518 emit_strw (guint8 *code, int rt, int rn, int imm)
520 if (arm_is_strw_imm (imm)) {
521 arm_strw (code, rt, rn, imm);
523 g_assert (rt != ARMREG_IP0);
524 g_assert (rn != ARMREG_IP0);
525 code = emit_imm (code, ARMREG_IP0, imm);
526 arm_strw_reg (code, rt, rn, ARMREG_IP0);
531 static inline __attribute__((warn_unused_result)) guint8*
532 emit_strfpw (guint8 *code, int rt, int rn, int imm)
534 if (arm_is_strw_imm (imm)) {
535 arm_strfpw (code, rt, rn, imm);
537 g_assert (rn != ARMREG_IP0);
538 code = emit_imm (code, ARMREG_IP0, imm);
539 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
540 arm_strfpw (code, rt, ARMREG_IP0, 0);
545 static inline __attribute__((warn_unused_result)) guint8*
546 emit_strfpx (guint8 *code, int rt, int rn, int imm)
548 if (arm_is_strx_imm (imm)) {
549 arm_strfpx (code, rt, rn, imm);
551 g_assert (rn != ARMREG_IP0);
552 code = emit_imm (code, ARMREG_IP0, imm);
553 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
554 arm_strfpx (code, rt, ARMREG_IP0, 0);
559 static inline __attribute__((warn_unused_result)) guint8*
560 emit_strx (guint8 *code, int rt, int rn, int imm)
562 if (arm_is_strx_imm (imm)) {
563 arm_strx (code, rt, rn, imm);
565 g_assert (rt != ARMREG_IP0);
566 g_assert (rn != ARMREG_IP0);
567 code = emit_imm (code, ARMREG_IP0, imm);
568 arm_strx_reg (code, rt, rn, ARMREG_IP0);
573 static inline __attribute__((warn_unused_result)) guint8*
574 emit_ldrb (guint8 *code, int rt, int rn, int imm)
576 if (arm_is_pimm12_scaled (imm, 1)) {
577 arm_ldrb (code, rt, rn, imm);
579 g_assert (rt != ARMREG_IP0);
580 g_assert (rn != ARMREG_IP0);
581 code = emit_imm (code, ARMREG_IP0, imm);
582 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
587 static inline __attribute__((warn_unused_result)) guint8*
588 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
590 if (arm_is_pimm12_scaled (imm, 1)) {
591 arm_ldrsbx (code, rt, rn, imm);
593 g_assert (rt != ARMREG_IP0);
594 g_assert (rn != ARMREG_IP0);
595 code = emit_imm (code, ARMREG_IP0, imm);
596 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
601 static inline __attribute__((warn_unused_result)) guint8*
602 emit_ldrh (guint8 *code, int rt, int rn, int imm)
604 if (arm_is_pimm12_scaled (imm, 2)) {
605 arm_ldrh (code, rt, rn, imm);
607 g_assert (rt != ARMREG_IP0);
608 g_assert (rn != ARMREG_IP0);
609 code = emit_imm (code, ARMREG_IP0, imm);
610 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
615 static inline __attribute__((warn_unused_result)) guint8*
616 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
618 if (arm_is_pimm12_scaled (imm, 2)) {
619 arm_ldrshx (code, rt, rn, imm);
621 g_assert (rt != ARMREG_IP0);
622 g_assert (rn != ARMREG_IP0);
623 code = emit_imm (code, ARMREG_IP0, imm);
624 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
629 static inline __attribute__((warn_unused_result)) guint8*
630 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
632 if (arm_is_pimm12_scaled (imm, 4)) {
633 arm_ldrswx (code, rt, rn, imm);
635 g_assert (rt != ARMREG_IP0);
636 g_assert (rn != ARMREG_IP0);
637 code = emit_imm (code, ARMREG_IP0, imm);
638 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
643 static inline __attribute__((warn_unused_result)) guint8*
644 emit_ldrw (guint8 *code, int rt, int rn, int imm)
646 if (arm_is_pimm12_scaled (imm, 4)) {
647 arm_ldrw (code, rt, rn, imm);
649 g_assert (rn != ARMREG_IP0);
650 code = emit_imm (code, ARMREG_IP0, imm);
651 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
656 static inline __attribute__((warn_unused_result)) guint8*
657 emit_ldrx (guint8 *code, int rt, int rn, int imm)
659 if (arm_is_pimm12_scaled (imm, 8)) {
660 arm_ldrx (code, rt, rn, imm);
662 g_assert (rn != ARMREG_IP0);
663 code = emit_imm (code, ARMREG_IP0, imm);
664 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
669 static inline __attribute__((warn_unused_result)) guint8*
670 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
672 if (arm_is_pimm12_scaled (imm, 4)) {
673 arm_ldrfpw (code, rt, rn, imm);
675 g_assert (rn != ARMREG_IP0);
676 code = emit_imm (code, ARMREG_IP0, imm);
677 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
678 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
683 static inline __attribute__((warn_unused_result)) guint8*
684 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
686 if (arm_is_pimm12_scaled (imm, 8)) {
687 arm_ldrfpx (code, rt, rn, imm);
689 g_assert (rn != ARMREG_IP0);
690 code = emit_imm (code, ARMREG_IP0, imm);
691 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
692 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
698 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
700 return emit_ldrx (code, rt, rn, imm);
704 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
707 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
708 code = emit_imm64_template (code, ARMREG_LR);
709 arm_blrx (code, ARMREG_LR);
711 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
713 cfg->thunk_area += THUNK_SIZE;
718 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
721 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
723 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
724 /* See arch_emit_got_access () in aot-compiler.c */
725 arm_ldrx_lit (code, dreg, 0);
732 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
734 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
738 * mono_arm_emit_aotconst:
740 * Emit code to load an AOT constant into DREG. Usable from trampolines.
743 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
745 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
749 emit_tls_get (guint8 *code, int dreg, int tls_offset)
751 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
752 if (tls_offset < 256) {
753 arm_ldrx (code, dreg, dreg, tls_offset);
755 code = emit_addx_imm (code, dreg, dreg, tls_offset);
756 arm_ldrx (code, dreg, dreg, 0);
762 emit_tls_get_reg (guint8 *code, int dreg, int offset_reg)
764 g_assert (offset_reg != ARMREG_IP0);
765 arm_mrs (code, ARMREG_IP0, ARM_MRS_REG_TPIDR_EL0);
766 arm_ldrx_reg (code, dreg, ARMREG_IP0, offset_reg);
771 emit_tls_set (guint8 *code, int sreg, int tls_offset)
773 int tmpreg = ARMREG_IP0;
775 g_assert (sreg != tmpreg);
776 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
777 if (tls_offset < 256) {
778 arm_strx (code, sreg, tmpreg, tls_offset);
780 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
781 arm_strx (code, sreg, tmpreg, 0);
788 emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
790 int tmpreg = ARMREG_IP0;
792 g_assert (sreg != tmpreg);
793 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
794 arm_strx_reg (code, sreg, tmpreg, offset_reg);
801 * - ldrp [fp, lr], [sp], !stack_offfset
802 * Clobbers TEMP_REGS.
804 __attribute__((warn_unused_result)) guint8*
805 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
807 arm_movspx (code, ARMREG_SP, ARMREG_FP);
809 if (arm_is_ldpx_imm (stack_offset)) {
810 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
812 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
813 /* sp += stack_offset */
814 g_assert (temp_regs & (1 << ARMREG_IP0));
815 if (temp_regs & (1 << ARMREG_IP1)) {
816 code = emit_addx_sp_imm (code, stack_offset);
818 int imm = stack_offset;
820 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
821 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
823 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
826 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
832 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
835 emit_thunk (guint8 *code, gconstpointer target)
839 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
840 arm_brx (code, ARMREG_IP0);
841 *(guint64*)code = (guint64)target;
843 mono_arch_flush_icache (p, code - p);
848 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
851 MonoThunkJitInfo *info;
855 guint8 *target_thunk;
858 domain = mono_domain_get ();
862 * This can be called multiple times during JITting,
863 * save the current position in cfg->arch to avoid
864 * doing a O(n^2) search.
866 if (!cfg->arch.thunks) {
867 cfg->arch.thunks = cfg->thunks;
868 cfg->arch.thunks_size = cfg->thunk_area;
870 thunks = cfg->arch.thunks;
871 thunks_size = cfg->arch.thunks_size;
873 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
874 g_assert_not_reached ();
877 g_assert (*(guint32*)thunks == 0);
878 emit_thunk (thunks, target);
880 cfg->arch.thunks += THUNK_SIZE;
881 cfg->arch.thunks_size -= THUNK_SIZE;
885 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
887 info = mono_jit_info_get_thunk_info (ji);
890 thunks = (guint8*)ji->code_start + info->thunks_offset;
891 thunks_size = info->thunks_size;
893 orig_target = mono_arch_get_call_target (code + 4);
895 mono_domain_lock (domain);
898 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
899 /* The call already points to a thunk, because of trampolines etc. */
900 target_thunk = orig_target;
902 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
903 if (((guint32*)p) [0] == 0) {
907 } else if (((guint64*)p) [1] == (guint64)target) {
908 /* Thunk already points to target */
915 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
918 mono_domain_unlock (domain);
919 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
920 g_assert_not_reached ();
923 emit_thunk (target_thunk, target);
925 mono_domain_unlock (domain);
932 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
934 switch (relocation) {
936 arm_b (code, target);
938 case MONO_R_ARM64_BCC: {
941 cond = arm_get_bcc_cond (code);
942 arm_bcc (code, cond, target);
945 case MONO_R_ARM64_CBZ:
946 arm_set_cbz_target (code, target);
948 case MONO_R_ARM64_IMM: {
949 guint64 imm = (guint64)target;
952 /* emit_imm64_template () */
953 dreg = arm_get_movzx_rd (code);
954 arm_movzx (code, dreg, imm & 0xffff, 0);
955 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
956 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
957 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
960 case MONO_R_ARM64_BL:
961 if (arm_is_bl_disp (code, target)) {
962 arm_bl (code, target);
966 thunk = create_thunk (cfg, domain, code, target);
967 g_assert (arm_is_bl_disp (code, thunk));
968 arm_bl (code, thunk);
972 g_assert_not_reached ();
977 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
979 arm_patch_full (NULL, NULL, code, target, relocation);
983 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
985 arm_patch_rel (code, target, relocation);
989 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
993 ip = ji->ip.i + code;
996 case MONO_PATCH_INFO_METHOD_JUMP:
997 /* ji->relocation is not set by the caller */
998 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1001 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1007 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1012 mono_arch_flush_register_windows (void)
1017 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1019 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1023 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1025 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1029 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1031 return ctx->regs [reg];
1035 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1037 ctx->regs [reg] = val;
1041 * mono_arch_set_target:
1043 * Set the target architecture the JIT backend should generate code for, in the form
1044 * of a GNU target triplet. Only used in AOT mode.
1047 mono_arch_set_target (char *mtriple)
1049 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1055 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1057 if (cinfo->gr >= PARAM_REGS) {
1058 ainfo->storage = ArgOnStack;
1060 /* Assume size == align */
1061 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1062 ainfo->offset = cinfo->stack_usage;
1063 ainfo->slot_size = size;
1065 cinfo->stack_usage += size;
1067 ainfo->offset = cinfo->stack_usage;
1068 ainfo->slot_size = 8;
1069 ainfo->sign = FALSE;
1070 /* Put arguments into 8 byte aligned stack slots */
1071 cinfo->stack_usage += 8;
1074 ainfo->storage = ArgInIReg;
1075 ainfo->reg = cinfo->gr;
1081 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1083 int size = single ? 4 : 8;
1085 if (cinfo->fr >= FP_PARAM_REGS) {
1086 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1088 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1089 ainfo->offset = cinfo->stack_usage;
1090 ainfo->slot_size = size;
1091 cinfo->stack_usage += size;
1093 ainfo->offset = cinfo->stack_usage;
1094 ainfo->slot_size = 8;
1095 /* Put arguments into 8 byte aligned stack slots */
1096 cinfo->stack_usage += 8;
1100 ainfo->storage = ArgInFRegR4;
1102 ainfo->storage = ArgInFReg;
1103 ainfo->reg = cinfo->fr;
1109 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1113 MonoClassField *field;
1114 MonoType *ftype, *prev_ftype = NULL;
1117 klass = mono_class_from_mono_type (t);
1119 while ((field = mono_class_get_fields (klass, &iter))) {
1120 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1122 ftype = mono_field_get_type (field);
1123 ftype = mini_get_underlying_type (ftype);
1125 if (MONO_TYPE_ISSTRUCT (ftype)) {
1126 int nested_nfields, nested_esize;
1127 int nested_field_offsets [16];
1129 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1131 if (nested_esize == 4)
1132 ftype = &mono_defaults.single_class->byval_arg;
1134 ftype = &mono_defaults.double_class->byval_arg;
1135 if (prev_ftype && prev_ftype->type != ftype->type)
1138 for (i = 0; i < nested_nfields; ++i) {
1139 if (nfields + i < 4)
1140 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1142 nfields += nested_nfields;
1144 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1146 if (prev_ftype && prev_ftype->type != ftype->type)
1150 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1154 if (nfields == 0 || nfields > 4)
1156 *out_nfields = nfields;
1157 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1162 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1164 int i, size, align_size, nregs, nfields, esize;
1165 int field_offsets [16];
1168 size = mini_type_stack_size_full (t, &align, cinfo->pinvoke);
1169 align_size = ALIGN_TO (size, 8);
1171 nregs = align_size / 8;
1172 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1174 * The struct might include nested float structs aligned at 8,
1175 * so need to keep track of the offsets of the individual fields.
1177 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1178 ainfo->storage = ArgHFA;
1179 ainfo->reg = cinfo->fr;
1180 ainfo->nregs = nfields;
1182 ainfo->esize = esize;
1183 for (i = 0; i < nfields; ++i)
1184 ainfo->foffsets [i] = field_offsets [i];
1185 cinfo->fr += ainfo->nregs;
1187 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1188 cinfo->fr = FP_PARAM_REGS;
1189 size = ALIGN_TO (size, 8);
1190 ainfo->storage = ArgVtypeOnStack;
1191 ainfo->offset = cinfo->stack_usage;
1194 ainfo->nregs = nfields;
1195 ainfo->esize = esize;
1196 cinfo->stack_usage += size;
1201 if (align_size > 16) {
1202 ainfo->storage = ArgVtypeByRef;
1207 if (cinfo->gr + nregs > PARAM_REGS) {
1208 size = ALIGN_TO (size, 8);
1209 ainfo->storage = ArgVtypeOnStack;
1210 ainfo->offset = cinfo->stack_usage;
1212 cinfo->stack_usage += size;
1213 cinfo->gr = PARAM_REGS;
1215 ainfo->storage = ArgVtypeInIRegs;
1216 ainfo->reg = cinfo->gr;
1217 ainfo->nregs = nregs;
1224 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1228 ptype = mini_get_underlying_type (t);
1229 switch (ptype->type) {
1231 add_general (cinfo, ainfo, 1, TRUE);
1233 case MONO_TYPE_BOOLEAN:
1235 add_general (cinfo, ainfo, 1, FALSE);
1238 add_general (cinfo, ainfo, 2, TRUE);
1241 case MONO_TYPE_CHAR:
1242 add_general (cinfo, ainfo, 2, FALSE);
1245 add_general (cinfo, ainfo, 4, TRUE);
1248 add_general (cinfo, ainfo, 4, FALSE);
1253 case MONO_TYPE_FNPTR:
1254 case MONO_TYPE_CLASS:
1255 case MONO_TYPE_OBJECT:
1256 case MONO_TYPE_SZARRAY:
1257 case MONO_TYPE_ARRAY:
1258 case MONO_TYPE_STRING:
1261 add_general (cinfo, ainfo, 8, FALSE);
1264 add_fp (cinfo, ainfo, FALSE);
1267 add_fp (cinfo, ainfo, TRUE);
1269 case MONO_TYPE_VALUETYPE:
1270 case MONO_TYPE_TYPEDBYREF:
1271 add_valuetype (cinfo, ainfo, ptype);
1273 case MONO_TYPE_VOID:
1274 ainfo->storage = ArgNone;
1276 case MONO_TYPE_GENERICINST:
1277 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1278 add_general (cinfo, ainfo, 8, FALSE);
1279 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1281 * Treat gsharedvt arguments as large vtypes
1283 ainfo->storage = ArgVtypeByRef;
1284 ainfo->gsharedvt = TRUE;
1286 add_valuetype (cinfo, ainfo, ptype);
1290 case MONO_TYPE_MVAR:
1291 g_assert (mini_is_gsharedvt_type (ptype));
1292 ainfo->storage = ArgVtypeByRef;
1293 ainfo->gsharedvt = TRUE;
1296 g_assert_not_reached ();
1304 * Obtain information about a call according to the calling convention.
1307 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1311 int n, pstart, pindex;
1313 n = sig->hasthis + sig->param_count;
1316 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1318 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1321 cinfo->pinvoke = sig->pinvoke;
1324 add_param (cinfo, &cinfo->ret, sig->ret);
1325 if (cinfo->ret.storage == ArgVtypeByRef)
1326 cinfo->ret.reg = ARMREG_R8;
1330 cinfo->stack_usage = 0;
1334 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1336 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1337 ainfo = cinfo->args + sig->hasthis + pindex;
1339 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1340 /* Prevent implicit arguments and sig_cookie from
1341 being passed in registers */
1342 cinfo->gr = PARAM_REGS;
1343 cinfo->fr = FP_PARAM_REGS;
1344 /* Emit the signature cookie just before the implicit arguments */
1345 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1348 add_param (cinfo, ainfo, sig->params [pindex]);
1349 if (ainfo->storage == ArgVtypeByRef) {
1350 /* Pass the argument address in the next register */
1351 if (cinfo->gr >= PARAM_REGS) {
1352 ainfo->storage = ArgVtypeByRefOnStack;
1353 ainfo->offset = cinfo->stack_usage;
1354 cinfo->stack_usage += 8;
1356 ainfo->reg = cinfo->gr;
1362 /* Handle the case where there are no implicit arguments */
1363 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1364 /* Prevent implicit arguments and sig_cookie from
1365 being passed in registers */
1366 cinfo->gr = PARAM_REGS;
1367 cinfo->fr = FP_PARAM_REGS;
1368 /* Emit the signature cookie just before the implicit arguments */
1369 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1372 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1378 MonoMethodSignature *sig;
1381 MonoType **param_types;
1382 int n_fpargs, n_fpret;
1386 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1390 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1393 // FIXME: Add more cases
1394 switch (cinfo->ret.storage) {
1401 case ArgVtypeInIRegs:
1402 if (cinfo->ret.nregs > 2)
1411 for (i = 0; i < cinfo->nargs; ++i) {
1412 ArgInfo *ainfo = &cinfo->args [i];
1414 switch (ainfo->storage) {
1416 case ArgVtypeInIRegs:
1423 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1435 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1437 ArchDynCallInfo *info;
1441 cinfo = get_call_info (NULL, sig);
1443 if (!dyn_call_supported (cinfo, sig)) {
1448 info = g_new0 (ArchDynCallInfo, 1);
1449 // FIXME: Preprocess the info to speed up start_dyn_call ()
1451 info->cinfo = cinfo;
1452 info->rtype = mini_get_underlying_type (sig->ret);
1453 info->param_types = g_new0 (MonoType*, sig->param_count);
1454 for (i = 0; i < sig->param_count; ++i)
1455 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1457 switch (cinfo->ret.storage) {
1463 info->n_fpret = cinfo->ret.nregs;
1469 return (MonoDynCallInfo*)info;
1473 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1475 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1477 g_free (ainfo->cinfo);
1478 g_free (ainfo->param_types);
1483 bitcast_r4_to_r8 (float f)
1491 bitcast_r8_to_r4 (double f)
1499 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1501 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1502 DynCallArgs *p = (DynCallArgs*)buf;
1503 int aindex, arg_index, greg, i, pindex;
1504 MonoMethodSignature *sig = dinfo->sig;
1505 CallInfo *cinfo = dinfo->cinfo;
1506 int buffer_offset = 0;
1508 g_assert (buf_len >= sizeof (DynCallArgs));
1512 p->n_fpargs = dinfo->n_fpargs;
1513 p->n_fpret = dinfo->n_fpret;
1520 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1522 if (cinfo->ret.storage == ArgVtypeByRef)
1523 p->regs [ARMREG_R8] = (mgreg_t)ret;
1525 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1526 MonoType *t = dinfo->param_types [aindex];
1527 gpointer *arg = args [arg_index ++];
1528 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1531 if (ainfo->storage == ArgOnStack) {
1532 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1538 p->regs [slot] = (mgreg_t)*arg;
1542 if (ios_abi && ainfo->storage == ArgOnStack) {
1543 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1544 gboolean handled = TRUE;
1546 /* Special case arguments smaller than 1 machine word */
1548 case MONO_TYPE_BOOLEAN:
1550 *(guint8*)stack_arg = *(guint8*)arg;
1553 *(gint8*)stack_arg = *(gint8*)arg;
1556 case MONO_TYPE_CHAR:
1557 *(guint16*)stack_arg = *(guint16*)arg;
1560 *(gint16*)stack_arg = *(gint16*)arg;
1563 *(gint32*)stack_arg = *(gint32*)arg;
1566 *(guint32*)stack_arg = *(guint32*)arg;
1577 case MONO_TYPE_STRING:
1578 case MONO_TYPE_CLASS:
1579 case MONO_TYPE_ARRAY:
1580 case MONO_TYPE_SZARRAY:
1581 case MONO_TYPE_OBJECT:
1587 p->regs [slot] = (mgreg_t)*arg;
1589 case MONO_TYPE_BOOLEAN:
1591 p->regs [slot] = *(guint8*)arg;
1594 p->regs [slot] = *(gint8*)arg;
1597 p->regs [slot] = *(gint16*)arg;
1600 case MONO_TYPE_CHAR:
1601 p->regs [slot] = *(guint16*)arg;
1604 p->regs [slot] = *(gint32*)arg;
1607 p->regs [slot] = *(guint32*)arg;
1610 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1614 p->fpregs [ainfo->reg] = *(double*)arg;
1617 case MONO_TYPE_GENERICINST:
1618 if (MONO_TYPE_IS_REFERENCE (t)) {
1619 p->regs [slot] = (mgreg_t)*arg;
1622 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1623 MonoClass *klass = mono_class_from_mono_type (t);
1624 guint8 *nullable_buf;
1628 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1629 * if the nullable param is passed by ref.
1631 size = mono_class_value_size (klass, NULL);
1632 nullable_buf = p->buffer + buffer_offset;
1633 buffer_offset += size;
1634 g_assert (buffer_offset <= 256);
1636 /* The argument pointed to by arg is either a boxed vtype or null */
1637 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1639 arg = (gpointer*)nullable_buf;
1645 case MONO_TYPE_VALUETYPE:
1646 switch (ainfo->storage) {
1647 case ArgVtypeInIRegs:
1648 for (i = 0; i < ainfo->nregs; ++i)
1649 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1652 if (ainfo->esize == 4) {
1653 for (i = 0; i < ainfo->nregs; ++i)
1654 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1656 for (i = 0; i < ainfo->nregs; ++i)
1657 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1659 p->n_fpargs += ainfo->nregs;
1662 p->regs [slot] = (mgreg_t)arg;
1665 g_assert_not_reached ();
1670 g_assert_not_reached ();
1676 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1678 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1679 CallInfo *cinfo = ainfo->cinfo;
1680 DynCallArgs *args = (DynCallArgs*)buf;
1681 MonoType *ptype = ainfo->rtype;
1682 guint8 *ret = args->ret;
1683 mgreg_t res = args->res;
1684 mgreg_t res2 = args->res2;
1687 if (cinfo->ret.storage == ArgVtypeByRef)
1690 switch (ptype->type) {
1691 case MONO_TYPE_VOID:
1692 *(gpointer*)ret = NULL;
1694 case MONO_TYPE_STRING:
1695 case MONO_TYPE_CLASS:
1696 case MONO_TYPE_ARRAY:
1697 case MONO_TYPE_SZARRAY:
1698 case MONO_TYPE_OBJECT:
1702 *(gpointer*)ret = (gpointer)res;
1708 case MONO_TYPE_BOOLEAN:
1709 *(guint8*)ret = res;
1712 *(gint16*)ret = res;
1715 case MONO_TYPE_CHAR:
1716 *(guint16*)ret = res;
1719 *(gint32*)ret = res;
1722 *(guint32*)ret = res;
1726 *(guint64*)ret = res;
1729 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1732 *(double*)ret = args->fpregs [0];
1734 case MONO_TYPE_GENERICINST:
1735 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1736 *(gpointer*)ret = (gpointer)res;
1741 case MONO_TYPE_VALUETYPE:
1742 switch (ainfo->cinfo->ret.storage) {
1743 case ArgVtypeInIRegs:
1744 *(mgreg_t*)ret = res;
1745 if (ainfo->cinfo->ret.nregs > 1)
1746 ((mgreg_t*)ret) [1] = res2;
1749 /* Use the same area for returning fp values */
1750 if (cinfo->ret.esize == 4) {
1751 for (i = 0; i < cinfo->ret.nregs; ++i)
1752 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1754 for (i = 0; i < cinfo->ret.nregs; ++i)
1755 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1759 g_assert_not_reached ();
1764 g_assert_not_reached ();
1769 void sys_icache_invalidate (void *start, size_t len);
1773 mono_arch_flush_icache (guint8 *code, gint size)
1775 #ifndef MONO_CROSS_COMPILE
1777 sys_icache_invalidate (code, size);
1779 __clear_cache (code, code + size);
1787 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1794 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1799 for (i = 0; i < cfg->num_varinfo; i++) {
1800 MonoInst *ins = cfg->varinfo [i];
1801 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1804 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1807 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1808 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1811 if (mono_is_regsize_var (ins->inst_vtype)) {
1812 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1813 g_assert (i == vmv->idx);
1814 vars = g_list_prepend (vars, vmv);
1818 vars = mono_varlist_sort (cfg, vars, 0);
1824 mono_arch_get_global_int_regs (MonoCompile *cfg)
1829 /* r28 is reserved for cfg->arch.args_reg */
1830 /* r27 is reserved for the imt argument */
1831 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1832 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1838 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1840 MonoInst *ins = cfg->varinfo [vmv->idx];
1842 if (ins->opcode == OP_ARG)
1849 mono_arch_create_vars (MonoCompile *cfg)
1851 MonoMethodSignature *sig;
1854 sig = mono_method_signature (cfg->method);
1855 if (!cfg->arch.cinfo)
1856 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1857 cinfo = cfg->arch.cinfo;
1859 if (cinfo->ret.storage == ArgVtypeByRef) {
1860 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1861 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1864 if (cfg->gen_sdb_seq_points) {
1867 if (cfg->compile_aot) {
1868 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1869 ins->flags |= MONO_INST_VOLATILE;
1870 cfg->arch.seq_point_info_var = ins;
1873 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1874 ins->flags |= MONO_INST_VOLATILE;
1875 cfg->arch.ss_tramp_var = ins;
1877 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1878 ins->flags |= MONO_INST_VOLATILE;
1879 cfg->arch.bp_tramp_var = ins;
1882 if (cfg->method->save_lmf) {
1883 cfg->create_lmf_var = TRUE;
1886 cfg->lmf_ir_mono_lmf = TRUE;
1892 mono_arch_allocate_vars (MonoCompile *cfg)
1894 MonoMethodSignature *sig;
1898 int i, offset, size, align;
1899 guint32 locals_stack_size, locals_stack_align;
1903 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1904 * Compute cfg->stack_offset and update cfg->used_int_regs.
1907 sig = mono_method_signature (cfg->method);
1909 if (!cfg->arch.cinfo)
1910 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1911 cinfo = cfg->arch.cinfo;
1914 * The ARM64 ABI always uses a frame pointer.
1915 * The instruction set prefers positive offsets, so fp points to the bottom of the
1916 * frame, and stack slots are at positive offsets.
1917 * If some arguments are received on the stack, their offsets relative to fp can
1918 * not be computed right now because the stack frame might grow due to spilling
1919 * done by the local register allocator. To solve this, we reserve a register
1920 * which points to them.
1921 * The stack frame looks like this:
1922 * args_reg -> <bottom of parent frame>
1924 * fp -> <saved fp+lr>
1925 * sp -> <localloc/params area>
1927 cfg->frame_reg = ARMREG_FP;
1928 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1934 if (cinfo->stack_usage) {
1935 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1936 cfg->arch.args_reg = ARMREG_R28;
1937 cfg->used_int_regs |= 1 << ARMREG_R28;
1940 if (cfg->method->save_lmf) {
1941 /* The LMF var is allocated normally */
1943 /* Callee saved regs */
1944 cfg->arch.saved_gregs_offset = offset;
1945 for (i = 0; i < 32; ++i)
1946 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1951 switch (cinfo->ret.storage) {
1957 cfg->ret->opcode = OP_REGVAR;
1958 cfg->ret->dreg = cinfo->ret.reg;
1960 case ArgVtypeInIRegs:
1962 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1963 cfg->ret->opcode = OP_REGOFFSET;
1964 cfg->ret->inst_basereg = cfg->frame_reg;
1965 cfg->ret->inst_offset = offset;
1966 if (cinfo->ret.storage == ArgHFA)
1973 /* This variable will be initalized in the prolog from R8 */
1974 cfg->vret_addr->opcode = OP_REGOFFSET;
1975 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1976 cfg->vret_addr->inst_offset = offset;
1978 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1979 printf ("vret_addr =");
1980 mono_print_ins (cfg->vret_addr);
1984 g_assert_not_reached ();
1989 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1990 ainfo = cinfo->args + i;
1992 ins = cfg->args [i];
1993 if (ins->opcode == OP_REGVAR)
1996 ins->opcode = OP_REGOFFSET;
1997 ins->inst_basereg = cfg->frame_reg;
1999 switch (ainfo->storage) {
2003 // FIXME: Use nregs/size
2004 /* These will be copied to the stack in the prolog */
2005 ins->inst_offset = offset;
2011 case ArgVtypeOnStack:
2012 /* These are in the parent frame */
2013 g_assert (cfg->arch.args_reg);
2014 ins->inst_basereg = cfg->arch.args_reg;
2015 ins->inst_offset = ainfo->offset;
2017 case ArgVtypeInIRegs:
2019 ins->opcode = OP_REGOFFSET;
2020 ins->inst_basereg = cfg->frame_reg;
2021 /* These arguments are saved to the stack in the prolog */
2022 ins->inst_offset = offset;
2023 if (cfg->verbose_level >= 2)
2024 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2025 if (ainfo->storage == ArgHFA)
2031 case ArgVtypeByRefOnStack: {
2034 if (ainfo->gsharedvt) {
2035 ins->opcode = OP_REGOFFSET;
2036 ins->inst_basereg = cfg->arch.args_reg;
2037 ins->inst_offset = ainfo->offset;
2041 /* The vtype address is in the parent frame */
2042 g_assert (cfg->arch.args_reg);
2043 MONO_INST_NEW (cfg, vtaddr, 0);
2044 vtaddr->opcode = OP_REGOFFSET;
2045 vtaddr->inst_basereg = cfg->arch.args_reg;
2046 vtaddr->inst_offset = ainfo->offset;
2048 /* Need an indirection */
2049 ins->opcode = OP_VTARG_ADDR;
2050 ins->inst_left = vtaddr;
2053 case ArgVtypeByRef: {
2056 if (ainfo->gsharedvt) {
2057 ins->opcode = OP_REGOFFSET;
2058 ins->inst_basereg = cfg->frame_reg;
2059 ins->inst_offset = offset;
2064 /* The vtype address is in a register, will be copied to the stack in the prolog */
2065 MONO_INST_NEW (cfg, vtaddr, 0);
2066 vtaddr->opcode = OP_REGOFFSET;
2067 vtaddr->inst_basereg = cfg->frame_reg;
2068 vtaddr->inst_offset = offset;
2071 /* Need an indirection */
2072 ins->opcode = OP_VTARG_ADDR;
2073 ins->inst_left = vtaddr;
2077 g_assert_not_reached ();
2082 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2083 // FIXME: Allocate these to registers
2084 ins = cfg->arch.seq_point_info_var;
2088 offset += align - 1;
2089 offset &= ~(align - 1);
2090 ins->opcode = OP_REGOFFSET;
2091 ins->inst_basereg = cfg->frame_reg;
2092 ins->inst_offset = offset;
2095 ins = cfg->arch.ss_tramp_var;
2099 offset += align - 1;
2100 offset &= ~(align - 1);
2101 ins->opcode = OP_REGOFFSET;
2102 ins->inst_basereg = cfg->frame_reg;
2103 ins->inst_offset = offset;
2106 ins = cfg->arch.bp_tramp_var;
2110 offset += align - 1;
2111 offset &= ~(align - 1);
2112 ins->opcode = OP_REGOFFSET;
2113 ins->inst_basereg = cfg->frame_reg;
2114 ins->inst_offset = offset;
2119 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2120 if (locals_stack_align)
2121 offset = ALIGN_TO (offset, locals_stack_align);
2123 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2124 if (offsets [i] != -1) {
2125 ins = cfg->varinfo [i];
2126 ins->opcode = OP_REGOFFSET;
2127 ins->inst_basereg = cfg->frame_reg;
2128 ins->inst_offset = offset + offsets [i];
2129 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2132 offset += locals_stack_size;
2134 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2136 cfg->stack_offset = offset;
2141 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2146 LLVMCallInfo *linfo;
2148 n = sig->param_count + sig->hasthis;
2150 cinfo = get_call_info (cfg->mempool, sig);
2152 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2154 switch (cinfo->ret.storage) {
2161 linfo->ret.storage = LLVMArgVtypeByRef;
2164 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2165 // array which is returned in int regs
2168 linfo->ret.storage = LLVMArgFpStruct;
2169 linfo->ret.nslots = cinfo->ret.nregs;
2170 linfo->ret.esize = cinfo->ret.esize;
2172 case ArgVtypeInIRegs:
2173 /* LLVM models this by returning an int */
2174 linfo->ret.storage = LLVMArgVtypeAsScalar;
2175 linfo->ret.nslots = cinfo->ret.nregs;
2176 linfo->ret.esize = cinfo->ret.esize;
2179 g_assert_not_reached ();
2183 for (i = 0; i < n; ++i) {
2184 LLVMArgInfo *lainfo = &linfo->args [i];
2186 ainfo = cinfo->args + i;
2188 lainfo->storage = LLVMArgNone;
2190 switch (ainfo->storage) {
2197 lainfo->storage = LLVMArgNormal;
2200 case ArgVtypeByRefOnStack:
2201 lainfo->storage = LLVMArgVtypeByRef;
2206 lainfo->storage = LLVMArgAsFpArgs;
2207 lainfo->nslots = ainfo->nregs;
2208 lainfo->esize = ainfo->esize;
2209 for (j = 0; j < ainfo->nregs; ++j)
2210 lainfo->pair_storage [j] = LLVMArgInFPReg;
2213 case ArgVtypeInIRegs:
2214 lainfo->storage = LLVMArgAsIArgs;
2215 lainfo->nslots = ainfo->nregs;
2217 case ArgVtypeOnStack:
2221 lainfo->storage = LLVMArgAsFpArgs;
2222 lainfo->nslots = ainfo->nregs;
2223 lainfo->esize = ainfo->esize;
2224 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2225 for (j = 0; j < ainfo->nregs; ++j)
2226 lainfo->pair_storage [j] = LLVMArgInFPReg;
2228 lainfo->storage = LLVMArgAsIArgs;
2229 lainfo->nslots = ainfo->size / 8;
2233 g_assert_not_reached ();
2243 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2249 MONO_INST_NEW (cfg, ins, OP_MOVE);
2250 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2251 ins->sreg1 = arg->dreg;
2252 MONO_ADD_INS (cfg->cbb, ins);
2253 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2256 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2257 ins->dreg = mono_alloc_freg (cfg);
2258 ins->sreg1 = arg->dreg;
2259 MONO_ADD_INS (cfg->cbb, ins);
2260 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2263 if (COMPILE_LLVM (cfg))
2264 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2266 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2268 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2269 ins->dreg = mono_alloc_freg (cfg);
2270 ins->sreg1 = arg->dreg;
2271 MONO_ADD_INS (cfg->cbb, ins);
2272 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2275 g_assert_not_reached ();
2281 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2283 MonoMethodSignature *tmp_sig;
2286 if (call->tail_call)
2289 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2292 * mono_ArgIterator_Setup assumes the signature cookie is
2293 * passed first and all the arguments which were before it are
2294 * passed on the stack after the signature. So compensate by
2295 * passing a different signature.
2297 tmp_sig = mono_metadata_signature_dup (call->signature);
2298 tmp_sig->param_count -= call->signature->sentinelpos;
2299 tmp_sig->sentinelpos = 0;
2300 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2302 sig_reg = mono_alloc_ireg (cfg);
2303 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2305 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2309 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2311 MonoMethodSignature *sig;
2312 MonoInst *arg, *vtarg;
2317 sig = call->signature;
2319 cinfo = get_call_info (cfg->mempool, sig);
2321 switch (cinfo->ret.storage) {
2322 case ArgVtypeInIRegs:
2325 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2326 * the location pointed to by it after call in emit_move_return_value ().
2328 if (!cfg->arch.vret_addr_loc) {
2329 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2330 /* Prevent it from being register allocated or optimized away */
2331 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2334 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2337 /* Pass the vtype return address in R8 */
2338 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2339 vtarg->sreg1 = call->vret_var->dreg;
2340 vtarg->dreg = mono_alloc_preg (cfg);
2341 MONO_ADD_INS (cfg->cbb, vtarg);
2343 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2349 for (i = 0; i < cinfo->nargs; ++i) {
2350 ainfo = cinfo->args + i;
2351 arg = call->args [i];
2353 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2354 /* Emit the signature cookie just before the implicit arguments */
2355 emit_sig_cookie (cfg, call, cinfo);
2358 switch (ainfo->storage) {
2362 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2365 switch (ainfo->slot_size) {
2367 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2370 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2373 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2376 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2379 g_assert_not_reached ();
2384 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2387 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2389 case ArgVtypeInIRegs:
2391 case ArgVtypeByRefOnStack:
2392 case ArgVtypeOnStack:
2398 size = mono_class_value_size (arg->klass, &align);
2400 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2401 ins->sreg1 = arg->dreg;
2402 ins->klass = arg->klass;
2403 ins->backend.size = size;
2404 ins->inst_p0 = call;
2405 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2406 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2407 MONO_ADD_INS (cfg->cbb, ins);
2411 g_assert_not_reached ();
2416 /* Handle the case where there are no implicit arguments */
2417 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2418 emit_sig_cookie (cfg, call, cinfo);
2420 call->call_info = cinfo;
2421 call->stack_usage = cinfo->stack_usage;
2425 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2427 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2428 ArgInfo *ainfo = ins->inst_p1;
2432 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2435 switch (ainfo->storage) {
2436 case ArgVtypeInIRegs:
2437 for (i = 0; i < ainfo->nregs; ++i) {
2438 // FIXME: Smaller sizes
2439 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2440 load->dreg = mono_alloc_ireg (cfg);
2441 load->inst_basereg = src->dreg;
2442 load->inst_offset = i * sizeof(mgreg_t);
2443 MONO_ADD_INS (cfg->cbb, load);
2444 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2448 for (i = 0; i < ainfo->nregs; ++i) {
2449 if (ainfo->esize == 4)
2450 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2452 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2453 load->dreg = mono_alloc_freg (cfg);
2454 load->inst_basereg = src->dreg;
2455 load->inst_offset = ainfo->foffsets [i];
2456 MONO_ADD_INS (cfg->cbb, load);
2457 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2461 case ArgVtypeByRefOnStack: {
2462 MonoInst *vtaddr, *load, *arg;
2464 /* Pass the vtype address in a reg/on the stack */
2465 if (ainfo->gsharedvt) {
2468 /* Make a copy of the argument */
2469 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2471 MONO_INST_NEW (cfg, load, OP_LDADDR);
2472 load->inst_p0 = vtaddr;
2473 vtaddr->flags |= MONO_INST_INDIRECT;
2474 load->type = STACK_MP;
2475 load->klass = vtaddr->klass;
2476 load->dreg = mono_alloc_ireg (cfg);
2477 MONO_ADD_INS (cfg->cbb, load);
2478 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2481 if (ainfo->storage == ArgVtypeByRef) {
2482 MONO_INST_NEW (cfg, arg, OP_MOVE);
2483 arg->dreg = mono_alloc_preg (cfg);
2484 arg->sreg1 = load->dreg;
2485 MONO_ADD_INS (cfg->cbb, arg);
2486 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2488 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2492 case ArgVtypeOnStack:
2493 for (i = 0; i < ainfo->size / 8; ++i) {
2494 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2495 load->dreg = mono_alloc_ireg (cfg);
2496 load->inst_basereg = src->dreg;
2497 load->inst_offset = i * 8;
2498 MONO_ADD_INS (cfg->cbb, load);
2499 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2503 g_assert_not_reached ();
2509 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2511 MonoMethodSignature *sig;
2514 sig = mono_method_signature (cfg->method);
2515 if (!cfg->arch.cinfo)
2516 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2517 cinfo = cfg->arch.cinfo;
2519 switch (cinfo->ret.storage) {
2523 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2526 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2529 if (COMPILE_LLVM (cfg))
2530 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2532 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2534 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2537 g_assert_not_reached ();
2543 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2548 if (cfg->compile_aot && !cfg->full_aot)
2549 /* OP_TAILCALL doesn't work with AOT */
2552 c1 = get_call_info (NULL, caller_sig);
2553 c2 = get_call_info (NULL, callee_sig);
2555 // FIXME: Relax these restrictions
2556 if (c1->stack_usage != 0)
2558 if (c1->stack_usage != c2->stack_usage)
2560 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2570 mono_arch_is_inst_imm (gint64 imm)
2572 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2576 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2583 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2590 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2596 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2601 #define ADD_NEW_INS(cfg,dest,op) do { \
2602 MONO_INST_NEW ((cfg), (dest), (op)); \
2603 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2607 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2609 MonoInst *ins, *temp, *last_ins = NULL;
2611 MONO_BB_FOR_EACH_INS (bb, ins) {
2612 switch (ins->opcode) {
2617 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2618 /* ARM sets the C flag to 1 if there was _no_ overflow */
2619 ins->next->opcode = OP_COND_EXC_NC;
2623 case OP_IDIV_UN_IMM:
2624 case OP_IREM_UN_IMM:
2626 mono_decompose_op_imm (cfg, bb, ins);
2628 case OP_LOCALLOC_IMM:
2629 if (ins->inst_imm > 32) {
2630 ADD_NEW_INS (cfg, temp, OP_ICONST);
2631 temp->inst_c0 = ins->inst_imm;
2632 temp->dreg = mono_alloc_ireg (cfg);
2633 ins->sreg1 = temp->dreg;
2634 ins->opcode = mono_op_imm_to_op (ins->opcode);
2637 case OP_ICOMPARE_IMM:
2638 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2639 ins->next->opcode = OP_ARM64_CBZW;
2640 ins->next->sreg1 = ins->sreg1;
2642 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2643 ins->next->opcode = OP_ARM64_CBNZW;
2644 ins->next->sreg1 = ins->sreg1;
2648 case OP_LCOMPARE_IMM:
2649 case OP_COMPARE_IMM:
2650 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2651 ins->next->opcode = OP_ARM64_CBZX;
2652 ins->next->sreg1 = ins->sreg1;
2654 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2655 ins->next->opcode = OP_ARM64_CBNZX;
2656 ins->next->sreg1 = ins->sreg1;
2661 gboolean swap = FALSE;
2665 /* Optimized away */
2671 * FP compares with unordered operands set the flags
2672 * to NZCV=0011, which matches some non-unordered compares
2673 * as well, like LE, so have to swap the operands.
2675 switch (ins->next->opcode) {
2677 ins->next->opcode = OP_FBGT;
2681 ins->next->opcode = OP_FBGE;
2689 ins->sreg1 = ins->sreg2;
2700 bb->last_ins = last_ins;
2701 bb->max_vreg = cfg->next_vreg;
2705 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2710 opcode_to_armcond (int opcode)
2721 case OP_COND_EXC_IEQ:
2722 case OP_COND_EXC_EQ:
2739 case OP_COND_EXC_IGT:
2740 case OP_COND_EXC_GT:
2755 case OP_COND_EXC_ILT:
2756 case OP_COND_EXC_LT:
2764 case OP_COND_EXC_INE_UN:
2765 case OP_COND_EXC_NE_UN:
2771 case OP_COND_EXC_IGE_UN:
2772 case OP_COND_EXC_GE_UN:
2782 case OP_COND_EXC_IGT_UN:
2783 case OP_COND_EXC_GT_UN:
2789 case OP_COND_EXC_ILE_UN:
2790 case OP_COND_EXC_LE_UN:
2798 case OP_COND_EXC_ILT_UN:
2799 case OP_COND_EXC_LT_UN:
2802 * FCMP sets the NZCV condition bits as follows:
2807 * ARMCOND_LT is N!=V, so it matches unordered too, so
2808 * fclt and fclt_un need to be special cased.
2818 case OP_COND_EXC_IC:
2820 case OP_COND_EXC_OV:
2821 case OP_COND_EXC_IOV:
2823 case OP_COND_EXC_NC:
2824 case OP_COND_EXC_INC:
2826 case OP_COND_EXC_NO:
2827 case OP_COND_EXC_INO:
2830 printf ("%s\n", mono_inst_name (opcode));
2831 g_assert_not_reached ();
2836 /* This clobbers LR */
2837 static inline __attribute__((warn_unused_result)) guint8*
2838 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2842 cond = opcode_to_armcond (opcode);
2844 arm_adrx (code, ARMREG_IP1, code);
2845 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2846 arm_bcc (code, cond, 0);
2851 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2856 call = (MonoCallInst*)ins;
2857 cinfo = call->call_info;
2859 switch (cinfo->ret.storage) {
2863 /* LLVM compiled code might only set the bottom bits */
2864 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2865 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2866 else if (call->inst.dreg != cinfo->ret.reg)
2867 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2870 if (call->inst.dreg != cinfo->ret.reg)
2871 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2875 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2877 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2879 case ArgVtypeInIRegs: {
2880 MonoInst *loc = cfg->arch.vret_addr_loc;
2883 /* Load the destination address */
2884 g_assert (loc && loc->opcode == OP_REGOFFSET);
2885 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2886 for (i = 0; i < cinfo->ret.nregs; ++i)
2887 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2891 MonoInst *loc = cfg->arch.vret_addr_loc;
2894 /* Load the destination address */
2895 g_assert (loc && loc->opcode == OP_REGOFFSET);
2896 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2897 for (i = 0; i < cinfo->ret.nregs; ++i) {
2898 if (cinfo->ret.esize == 4)
2899 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2901 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2908 g_assert_not_reached ();
2915 * emit_branch_island:
2917 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2920 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2923 int offset, island_size;
2925 /* Iterate over the patch infos added so far by this bb */
2927 for (ji = cfg->patch_info; ji; ji = ji->next) {
2928 if (ji->ip.i < start_offset)
2929 /* The patch infos are in reverse order, so this means the end */
2931 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2936 offset = code - cfg->native_code;
2937 if (offset > (cfg->code_size - island_size - 16)) {
2938 cfg->code_size *= 2;
2939 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2940 code = cfg->native_code + offset;
2943 /* Branch over the island */
2944 arm_b (code, code + 4 + island_size);
2946 for (ji = cfg->patch_info; ji; ji = ji->next) {
2947 if (ji->ip.i < start_offset)
2949 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2950 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2951 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2952 /* Rewrite the patch so it points to the unconditional branch */
2953 ji->ip.i = code - cfg->native_code;
2954 ji->relocation = MONO_R_ARM64_B;
2963 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2968 guint8 *code = cfg->native_code + cfg->code_len;
2969 int start_offset, max_len, dreg, sreg1, sreg2;
2972 if (cfg->verbose_level > 2)
2973 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2975 start_offset = code - cfg->native_code;
2977 MONO_BB_FOR_EACH_INS (bb, ins) {
2978 offset = code - cfg->native_code;
2980 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2982 if (offset > (cfg->code_size - max_len - 16)) {
2983 cfg->code_size *= 2;
2984 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2985 code = cfg->native_code + offset;
2988 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
2989 /* Emit a branch island for large basic blocks */
2990 code = emit_branch_island (cfg, code, start_offset);
2991 offset = code - cfg->native_code;
2992 start_offset = offset;
2995 mono_debug_record_line_number (cfg, ins, offset);
3000 imm = ins->inst_imm;
3002 switch (ins->opcode) {
3004 code = emit_imm (code, dreg, ins->inst_c0);
3007 code = emit_imm64 (code, dreg, ins->inst_c0);
3011 arm_movx (code, dreg, sreg1);
3014 case OP_RELAXED_NOP:
3017 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3018 code = emit_imm64_template (code, dreg);
3022 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3023 * So instead of emitting a trap, we emit a call a C function and place a
3026 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3031 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3032 // FIXME: andx_imm doesn't work yet
3033 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3034 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3035 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3036 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3037 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3038 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3041 /* ip1 = pointer, ip0 = end */
3042 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3044 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3046 arm_bcc (code, ARMCOND_EQ, 0);
3047 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3048 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3049 arm_b (code, buf [0]);
3050 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3052 arm_movspx (code, dreg, ARMREG_SP);
3053 if (cfg->param_area)
3054 code = emit_subx_sp_imm (code, cfg->param_area);
3057 case OP_LOCALLOC_IMM: {
3060 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3061 g_assert (arm_is_arith_imm (imm));
3062 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3065 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3067 while (offset < imm) {
3068 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3071 arm_movspx (code, dreg, ARMREG_SP);
3072 if (cfg->param_area)
3073 code = emit_subx_sp_imm (code, cfg->param_area);
3077 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3079 case OP_OBJC_GET_SELECTOR:
3080 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3081 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3082 arm_ldrx_lit (code, ins->dreg, 0);
3086 case OP_SEQ_POINT: {
3087 MonoInst *info_var = cfg->arch.seq_point_info_var;
3090 * For AOT, we use one got slot per method, which will point to a
3091 * SeqPointInfo structure, containing all the information required
3092 * by the code below.
3094 if (cfg->compile_aot) {
3095 g_assert (info_var);
3096 g_assert (info_var->opcode == OP_REGOFFSET);
3099 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3100 MonoInst *var = cfg->arch.ss_tramp_var;
3103 g_assert (var->opcode == OP_REGOFFSET);
3104 /* Load ss_tramp_var */
3105 /* This is equal to &ss_trampoline */
3106 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3107 /* Load the trampoline address */
3108 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3109 /* Call it if it is non-null */
3110 arm_cbzx (code, ARMREG_IP1, code + 8);
3111 arm_blrx (code, ARMREG_IP1);
3114 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3116 if (cfg->compile_aot) {
3117 guint32 offset = code - cfg->native_code;
3120 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3121 /* Add the offset */
3122 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3123 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3124 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3125 /* Skip the load if its 0 */
3126 arm_cbzx (code, ARMREG_IP1, code + 8);
3127 /* Call the breakpoint trampoline */
3128 arm_blrx (code, ARMREG_IP1);
3130 MonoInst *var = cfg->arch.bp_tramp_var;
3133 g_assert (var->opcode == OP_REGOFFSET);
3134 /* Load the address of the bp trampoline into IP0 */
3135 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3137 * A placeholder for a possible breakpoint inserted by
3138 * mono_arch_set_breakpoint ().
3147 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3151 arm_brx (code, sreg1);
3183 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3184 cond = opcode_to_armcond (ins->opcode);
3185 arm_bcc (code, cond, 0);
3189 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3190 /* For fp compares, ARMCOND_LT is lt or unordered */
3191 arm_bcc (code, ARMCOND_LT, 0);
3194 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3195 arm_bcc (code, ARMCOND_EQ, 0);
3196 offset = code - cfg->native_code;
3197 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3198 /* For fp compares, ARMCOND_LT is lt or unordered */
3199 arm_bcc (code, ARMCOND_LT, 0);
3202 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3203 arm_cbzw (code, sreg1, 0);
3206 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3207 arm_cbzx (code, sreg1, 0);
3209 case OP_ARM64_CBNZW:
3210 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3211 arm_cbnzw (code, sreg1, 0);
3213 case OP_ARM64_CBNZX:
3214 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3215 arm_cbnzx (code, sreg1, 0);
3219 arm_addw (code, dreg, sreg1, sreg2);
3222 arm_addx (code, dreg, sreg1, sreg2);
3225 arm_subw (code, dreg, sreg1, sreg2);
3228 arm_subx (code, dreg, sreg1, sreg2);
3231 arm_andw (code, dreg, sreg1, sreg2);
3234 arm_andx (code, dreg, sreg1, sreg2);
3237 arm_orrw (code, dreg, sreg1, sreg2);
3240 arm_orrx (code, dreg, sreg1, sreg2);
3243 arm_eorw (code, dreg, sreg1, sreg2);
3246 arm_eorx (code, dreg, sreg1, sreg2);
3249 arm_negw (code, dreg, sreg1);
3252 arm_negx (code, dreg, sreg1);
3255 arm_mvnw (code, dreg, sreg1);
3258 arm_mvnx (code, dreg, sreg1);
3261 arm_addsw (code, dreg, sreg1, sreg2);
3265 arm_addsx (code, dreg, sreg1, sreg2);
3268 arm_subsw (code, dreg, sreg1, sreg2);
3272 arm_subsx (code, dreg, sreg1, sreg2);
3275 arm_cmpw (code, sreg1, sreg2);
3279 arm_cmpx (code, sreg1, sreg2);
3282 code = emit_addw_imm (code, dreg, sreg1, imm);
3286 code = emit_addx_imm (code, dreg, sreg1, imm);
3289 code = emit_subw_imm (code, dreg, sreg1, imm);
3292 code = emit_subx_imm (code, dreg, sreg1, imm);
3295 code = emit_andw_imm (code, dreg, sreg1, imm);
3299 code = emit_andx_imm (code, dreg, sreg1, imm);
3302 code = emit_orrw_imm (code, dreg, sreg1, imm);
3305 code = emit_orrx_imm (code, dreg, sreg1, imm);
3308 code = emit_eorw_imm (code, dreg, sreg1, imm);
3311 code = emit_eorx_imm (code, dreg, sreg1, imm);
3313 case OP_ICOMPARE_IMM:
3314 code = emit_cmpw_imm (code, sreg1, imm);
3316 case OP_LCOMPARE_IMM:
3317 case OP_COMPARE_IMM:
3319 arm_cmpx (code, sreg1, ARMREG_RZR);
3321 // FIXME: 32 vs 64 bit issues for 0xffffffff
3322 code = emit_imm64 (code, ARMREG_LR, imm);
3323 arm_cmpx (code, sreg1, ARMREG_LR);
3327 arm_lslvw (code, dreg, sreg1, sreg2);
3330 arm_lslvx (code, dreg, sreg1, sreg2);
3333 arm_asrvw (code, dreg, sreg1, sreg2);
3336 arm_asrvx (code, dreg, sreg1, sreg2);
3339 arm_lsrvw (code, dreg, sreg1, sreg2);
3342 arm_lsrvx (code, dreg, sreg1, sreg2);
3346 arm_movx (code, dreg, sreg1);
3348 arm_lslw (code, dreg, sreg1, imm);
3352 arm_movx (code, dreg, sreg1);
3354 arm_lslx (code, dreg, sreg1, imm);
3358 arm_movx (code, dreg, sreg1);
3360 arm_asrw (code, dreg, sreg1, imm);
3365 arm_movx (code, dreg, sreg1);
3367 arm_asrx (code, dreg, sreg1, imm);
3369 case OP_ISHR_UN_IMM:
3371 arm_movx (code, dreg, sreg1);
3373 arm_lsrw (code, dreg, sreg1, imm);
3376 case OP_LSHR_UN_IMM:
3378 arm_movx (code, dreg, sreg1);
3380 arm_lsrx (code, dreg, sreg1, imm);
3385 arm_sxtwx (code, dreg, sreg1);
3388 /* Clean out the upper word */
3389 arm_movw (code, dreg, sreg1);
3392 arm_lslx (code, dreg, sreg1, imm);
3395 /* MULTIPLY/DIVISION */
3398 // FIXME: Optimize this
3399 /* Check for zero */
3400 arm_cmpx_imm (code, sreg2, 0);
3401 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3402 /* Check for INT_MIN/-1 */
3403 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3404 arm_cmpx (code, sreg1, ARMREG_IP0);
3405 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3406 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3407 arm_cmpx (code, sreg2, ARMREG_IP0);
3408 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3409 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3410 arm_cmpx_imm (code, ARMREG_IP0, 1);
3411 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3412 if (ins->opcode == OP_IREM) {
3413 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3414 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3416 arm_sdivw (code, dreg, sreg1, sreg2);
3420 arm_cmpx_imm (code, sreg2, 0);
3421 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3422 arm_udivw (code, dreg, sreg1, sreg2);
3425 arm_cmpx_imm (code, sreg2, 0);
3426 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3427 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3428 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3432 // FIXME: Optimize this
3433 /* Check for zero */
3434 arm_cmpx_imm (code, sreg2, 0);
3435 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3436 /* Check for INT64_MIN/-1 */
3437 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3438 arm_cmpx (code, sreg1, ARMREG_IP0);
3439 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3440 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3441 arm_cmpx (code, sreg2, ARMREG_IP0);
3442 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3443 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3444 arm_cmpx_imm (code, ARMREG_IP0, 1);
3445 /* 64 bit uses ArithmeticException */
3446 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3447 if (ins->opcode == OP_LREM) {
3448 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3449 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3451 arm_sdivx (code, dreg, sreg1, sreg2);
3455 arm_cmpx_imm (code, sreg2, 0);
3456 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3457 arm_udivx (code, dreg, sreg1, sreg2);
3460 arm_cmpx_imm (code, sreg2, 0);
3461 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3462 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3463 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3466 arm_mulw (code, dreg, sreg1, sreg2);
3469 arm_mulx (code, dreg, sreg1, sreg2);
3472 code = emit_imm (code, ARMREG_LR, imm);
3473 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3477 code = emit_imm (code, ARMREG_LR, imm);
3478 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3482 case OP_ICONV_TO_I1:
3483 case OP_LCONV_TO_I1:
3484 arm_sxtbx (code, dreg, sreg1);
3486 case OP_ICONV_TO_I2:
3487 case OP_LCONV_TO_I2:
3488 arm_sxthx (code, dreg, sreg1);
3490 case OP_ICONV_TO_U1:
3491 case OP_LCONV_TO_U1:
3492 arm_uxtbw (code, dreg, sreg1);
3494 case OP_ICONV_TO_U2:
3495 case OP_LCONV_TO_U2:
3496 arm_uxthw (code, dreg, sreg1);
3522 cond = opcode_to_armcond (ins->opcode);
3523 arm_cset (code, cond, dreg);
3536 cond = opcode_to_armcond (ins->opcode);
3537 arm_fcmpd (code, sreg1, sreg2);
3538 arm_cset (code, cond, dreg);
3543 case OP_LOADI1_MEMBASE:
3544 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3546 case OP_LOADU1_MEMBASE:
3547 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3549 case OP_LOADI2_MEMBASE:
3550 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3552 case OP_LOADU2_MEMBASE:
3553 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3555 case OP_LOADI4_MEMBASE:
3556 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3558 case OP_LOADU4_MEMBASE:
3559 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3561 case OP_LOAD_MEMBASE:
3562 case OP_LOADI8_MEMBASE:
3563 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3565 case OP_STOREI1_MEMBASE_IMM:
3566 case OP_STOREI2_MEMBASE_IMM:
3567 case OP_STOREI4_MEMBASE_IMM:
3568 case OP_STORE_MEMBASE_IMM:
3569 case OP_STOREI8_MEMBASE_IMM: {
3573 code = emit_imm (code, ARMREG_LR, imm);
3576 immreg = ARMREG_RZR;
3579 switch (ins->opcode) {
3580 case OP_STOREI1_MEMBASE_IMM:
3581 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3583 case OP_STOREI2_MEMBASE_IMM:
3584 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3586 case OP_STOREI4_MEMBASE_IMM:
3587 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3589 case OP_STORE_MEMBASE_IMM:
3590 case OP_STOREI8_MEMBASE_IMM:
3591 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3594 g_assert_not_reached ();
3599 case OP_STOREI1_MEMBASE_REG:
3600 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3602 case OP_STOREI2_MEMBASE_REG:
3603 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3605 case OP_STOREI4_MEMBASE_REG:
3606 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3608 case OP_STORE_MEMBASE_REG:
3609 case OP_STOREI8_MEMBASE_REG:
3610 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3614 code = emit_tls_get (code, dreg, ins->inst_offset);
3616 case OP_TLS_GET_REG:
3617 code = emit_tls_get_reg (code, dreg, sreg1);
3620 code = emit_tls_set (code, sreg1, ins->inst_offset);
3622 case OP_TLS_SET_REG:
3623 code = emit_tls_set_reg (code, sreg1, sreg2);
3627 case OP_MEMORY_BARRIER:
3630 case OP_ATOMIC_ADD_I4: {
3634 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3635 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3636 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3637 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3639 arm_movx (code, dreg, ARMREG_IP0);
3642 case OP_ATOMIC_ADD_I8: {
3646 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3647 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3648 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3649 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3651 arm_movx (code, dreg, ARMREG_IP0);
3654 case OP_ATOMIC_EXCHANGE_I4: {
3658 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3659 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3660 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3662 arm_movx (code, dreg, ARMREG_IP0);
3665 case OP_ATOMIC_EXCHANGE_I8: {
3669 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3670 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3671 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3673 arm_movx (code, dreg, ARMREG_IP0);
3676 case OP_ATOMIC_CAS_I4: {
3679 /* sreg2 is the value, sreg3 is the comparand */
3681 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3682 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3684 arm_bcc (code, ARMCOND_NE, 0);
3685 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3686 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3687 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3689 arm_movx (code, dreg, ARMREG_IP0);
3692 case OP_ATOMIC_CAS_I8: {
3696 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3697 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3699 arm_bcc (code, ARMCOND_NE, 0);
3700 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3701 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3702 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3704 arm_movx (code, dreg, ARMREG_IP0);
3707 case OP_ATOMIC_LOAD_I1: {
3708 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3709 arm_ldarb (code, ins->dreg, ARMREG_LR);
3710 arm_sxtbx (code, ins->dreg, ins->dreg);
3713 case OP_ATOMIC_LOAD_U1: {
3714 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3715 arm_ldarb (code, ins->dreg, ARMREG_LR);
3716 arm_uxtbx (code, ins->dreg, ins->dreg);
3719 case OP_ATOMIC_LOAD_I2: {
3720 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3721 arm_ldarh (code, ins->dreg, ARMREG_LR);
3722 arm_sxthx (code, ins->dreg, ins->dreg);
3725 case OP_ATOMIC_LOAD_U2: {
3726 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3727 arm_ldarh (code, ins->dreg, ARMREG_LR);
3728 arm_uxthx (code, ins->dreg, ins->dreg);
3731 case OP_ATOMIC_LOAD_I4: {
3732 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3733 arm_ldarw (code, ins->dreg, ARMREG_LR);
3734 arm_sxtwx (code, ins->dreg, ins->dreg);
3737 case OP_ATOMIC_LOAD_U4: {
3738 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3739 arm_ldarw (code, ins->dreg, ARMREG_LR);
3740 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3743 case OP_ATOMIC_LOAD_I8:
3744 case OP_ATOMIC_LOAD_U8: {
3745 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3746 arm_ldarx (code, ins->dreg, ARMREG_LR);
3749 case OP_ATOMIC_LOAD_R4: {
3750 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3752 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3753 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3755 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3756 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3757 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3761 case OP_ATOMIC_LOAD_R8: {
3762 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3763 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3764 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3767 case OP_ATOMIC_STORE_I1:
3768 case OP_ATOMIC_STORE_U1: {
3769 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3770 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3773 case OP_ATOMIC_STORE_I2:
3774 case OP_ATOMIC_STORE_U2: {
3775 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3776 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3779 case OP_ATOMIC_STORE_I4:
3780 case OP_ATOMIC_STORE_U4: {
3781 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3782 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3785 case OP_ATOMIC_STORE_I8:
3786 case OP_ATOMIC_STORE_U8: {
3787 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3788 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3791 case OP_ATOMIC_STORE_R4: {
3792 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3794 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3795 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3797 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3798 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3799 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3803 case OP_ATOMIC_STORE_R8: {
3804 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3805 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3806 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3812 guint64 imm = *(guint64*)ins->inst_p0;
3815 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3817 code = emit_imm64 (code, ARMREG_LR, imm);
3818 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3823 guint64 imm = *(guint32*)ins->inst_p0;
3825 code = emit_imm64 (code, ARMREG_LR, imm);
3827 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3829 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3830 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3834 case OP_LOADR8_MEMBASE:
3835 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3837 case OP_LOADR4_MEMBASE:
3839 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3841 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3842 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3845 case OP_STORER8_MEMBASE_REG:
3846 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3848 case OP_STORER4_MEMBASE_REG:
3850 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3852 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3853 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3858 arm_fmovd (code, dreg, sreg1);
3862 arm_fmovs (code, dreg, sreg1);
3864 case OP_MOVE_F_TO_I4:
3866 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3868 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3869 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3872 case OP_MOVE_I4_TO_F:
3874 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3876 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3877 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3880 case OP_MOVE_F_TO_I8:
3881 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3883 case OP_MOVE_I8_TO_F:
3884 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3887 arm_fcmpd (code, sreg1, sreg2);
3890 arm_fcmps (code, sreg1, sreg2);
3892 case OP_FCONV_TO_I1:
3893 arm_fcvtzs_dx (code, dreg, sreg1);
3894 arm_sxtbx (code, dreg, dreg);
3896 case OP_FCONV_TO_U1:
3897 arm_fcvtzu_dx (code, dreg, sreg1);
3898 arm_uxtbw (code, dreg, dreg);
3900 case OP_FCONV_TO_I2:
3901 arm_fcvtzs_dx (code, dreg, sreg1);
3902 arm_sxthx (code, dreg, dreg);
3904 case OP_FCONV_TO_U2:
3905 arm_fcvtzu_dx (code, dreg, sreg1);
3906 arm_uxthw (code, dreg, dreg);
3908 case OP_FCONV_TO_I4:
3909 arm_fcvtzs_dx (code, dreg, sreg1);
3910 arm_sxtwx (code, dreg, dreg);
3912 case OP_FCONV_TO_U4:
3913 arm_fcvtzu_dx (code, dreg, sreg1);
3915 case OP_FCONV_TO_I8:
3916 arm_fcvtzs_dx (code, dreg, sreg1);
3918 case OP_FCONV_TO_U8:
3919 arm_fcvtzu_dx (code, dreg, sreg1);
3921 case OP_FCONV_TO_R4:
3923 arm_fcvt_ds (code, dreg, sreg1);
3925 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3926 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3929 case OP_ICONV_TO_R4:
3931 arm_scvtf_rw_to_s (code, dreg, sreg1);
3933 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
3934 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3937 case OP_LCONV_TO_R4:
3939 arm_scvtf_rx_to_s (code, dreg, sreg1);
3941 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
3942 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3945 case OP_ICONV_TO_R8:
3946 arm_scvtf_rw_to_d (code, dreg, sreg1);
3948 case OP_LCONV_TO_R8:
3949 arm_scvtf_rx_to_d (code, dreg, sreg1);
3951 case OP_ICONV_TO_R_UN:
3952 arm_ucvtf_rw_to_d (code, dreg, sreg1);
3954 case OP_LCONV_TO_R_UN:
3955 arm_ucvtf_rx_to_d (code, dreg, sreg1);
3958 arm_fadd_d (code, dreg, sreg1, sreg2);
3961 arm_fsub_d (code, dreg, sreg1, sreg2);
3964 arm_fmul_d (code, dreg, sreg1, sreg2);
3967 arm_fdiv_d (code, dreg, sreg1, sreg2);
3971 g_assert_not_reached ();
3974 arm_fneg_d (code, dreg, sreg1);
3976 case OP_ARM_SETFREG_R4:
3977 arm_fcvt_ds (code, dreg, sreg1);
3980 /* Check for infinity */
3981 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
3982 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3983 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
3984 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
3985 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
3986 /* Check for nans */
3987 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
3988 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
3989 arm_fmovd (code, dreg, sreg1);
3994 arm_fadd_s (code, dreg, sreg1, sreg2);
3997 arm_fsub_s (code, dreg, sreg1, sreg2);
4000 arm_fmul_s (code, dreg, sreg1, sreg2);
4003 arm_fdiv_s (code, dreg, sreg1, sreg2);
4006 arm_fneg_s (code, dreg, sreg1);
4008 case OP_RCONV_TO_I1:
4009 arm_fcvtzs_sx (code, dreg, sreg1);
4010 arm_sxtbx (code, dreg, dreg);
4012 case OP_RCONV_TO_U1:
4013 arm_fcvtzu_sx (code, dreg, sreg1);
4014 arm_uxtbw (code, dreg, dreg);
4016 case OP_RCONV_TO_I2:
4017 arm_fcvtzs_sx (code, dreg, sreg1);
4018 arm_sxthx (code, dreg, dreg);
4020 case OP_RCONV_TO_U2:
4021 arm_fcvtzu_sx (code, dreg, sreg1);
4022 arm_uxthw (code, dreg, dreg);
4024 case OP_RCONV_TO_I4:
4025 arm_fcvtzs_sx (code, dreg, sreg1);
4026 arm_sxtwx (code, dreg, dreg);
4028 case OP_RCONV_TO_U4:
4029 arm_fcvtzu_sx (code, dreg, sreg1);
4031 case OP_RCONV_TO_I8:
4032 arm_fcvtzs_sx (code, dreg, sreg1);
4034 case OP_RCONV_TO_U8:
4035 arm_fcvtzu_sx (code, dreg, sreg1);
4037 case OP_RCONV_TO_R8:
4038 arm_fcvt_sd (code, dreg, sreg1);
4040 case OP_RCONV_TO_R4:
4042 arm_fmovs (code, dreg, sreg1);
4054 cond = opcode_to_armcond (ins->opcode);
4055 arm_fcmps (code, sreg1, sreg2);
4056 arm_cset (code, cond, dreg);
4067 call = (MonoCallInst*)ins;
4068 if (ins->flags & MONO_INST_HAS_METHOD)
4069 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4071 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4072 code = emit_move_return_value (cfg, code, ins);
4074 case OP_VOIDCALL_REG:
4080 arm_blrx (code, sreg1);
4081 code = emit_move_return_value (cfg, code, ins);
4083 case OP_VOIDCALL_MEMBASE:
4084 case OP_CALL_MEMBASE:
4085 case OP_LCALL_MEMBASE:
4086 case OP_FCALL_MEMBASE:
4087 case OP_RCALL_MEMBASE:
4088 case OP_VCALL2_MEMBASE:
4089 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4090 arm_blrx (code, ARMREG_IP0);
4091 code = emit_move_return_value (cfg, code, ins);
4094 MonoCallInst *call = (MonoCallInst*)ins;
4096 g_assert (!cfg->method->save_lmf);
4098 // FIXME: Copy stack arguments
4100 /* Restore registers */
4101 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4104 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4106 if (cfg->compile_aot) {
4107 /* This is not a PLT patch */
4108 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4109 arm_brx (code, ARMREG_IP0);
4111 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4114 ins->flags |= MONO_INST_GC_CALLSITE;
4115 ins->backend.pc_offset = code - cfg->native_code;
4119 g_assert (cfg->arch.cinfo);
4120 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4121 arm_strx (code, ARMREG_IP0, sreg1, 0);
4124 MonoInst *var = cfg->dyn_call_var;
4125 guint8 *labels [16];
4129 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4130 * sreg2 is the function to call.
4133 g_assert (var->opcode == OP_REGOFFSET);
4135 arm_movx (code, ARMREG_LR, sreg1);
4136 arm_movx (code, ARMREG_IP1, sreg2);
4138 /* Save args buffer */
4139 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4141 /* Set fp argument regs */
4142 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4143 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4145 arm_bcc (code, ARMCOND_EQ, 0);
4146 for (i = 0; i < 8; ++i)
4147 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4148 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4150 /* Set stack args */
4151 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4152 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4153 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4156 /* Set argument registers + r8 */
4157 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4160 arm_blrx (code, ARMREG_IP1);
4163 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4164 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4165 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4166 /* Save fp result */
4167 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4168 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4170 arm_bcc (code, ARMCOND_EQ, 0);
4171 for (i = 0; i < 8; ++i)
4172 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4173 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4177 case OP_GENERIC_CLASS_INIT: {
4178 static int byte_offset = -1;
4179 static guint8 bitmask;
4182 if (byte_offset < 0)
4183 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4185 /* Load vtable->initialized */
4186 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4187 // FIXME: No andx_imm yet */
4188 code = mono_arm_emit_imm64 (code, ARMREG_IP1, bitmask);
4189 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
4191 arm_cbnzx (code, ARMREG_IP0, 0);
4194 g_assert (sreg1 == ARMREG_R0);
4195 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4196 (gpointer)"mono_generic_class_init");
4198 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4203 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4206 case OP_NOT_REACHED:
4209 case OP_IL_SEQ_POINT:
4210 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4215 case OP_COND_EXC_IC:
4216 case OP_COND_EXC_OV:
4217 case OP_COND_EXC_IOV:
4218 case OP_COND_EXC_NC:
4219 case OP_COND_EXC_INC:
4220 case OP_COND_EXC_NO:
4221 case OP_COND_EXC_INO:
4222 case OP_COND_EXC_EQ:
4223 case OP_COND_EXC_IEQ:
4224 case OP_COND_EXC_NE_UN:
4225 case OP_COND_EXC_INE_UN:
4226 case OP_COND_EXC_ILT:
4227 case OP_COND_EXC_LT:
4228 case OP_COND_EXC_ILT_UN:
4229 case OP_COND_EXC_LT_UN:
4230 case OP_COND_EXC_IGT:
4231 case OP_COND_EXC_GT:
4232 case OP_COND_EXC_IGT_UN:
4233 case OP_COND_EXC_GT_UN:
4234 case OP_COND_EXC_IGE:
4235 case OP_COND_EXC_GE:
4236 case OP_COND_EXC_IGE_UN:
4237 case OP_COND_EXC_GE_UN:
4238 case OP_COND_EXC_ILE:
4239 case OP_COND_EXC_LE:
4240 case OP_COND_EXC_ILE_UN:
4241 case OP_COND_EXC_LE_UN:
4242 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4245 if (sreg1 != ARMREG_R0)
4246 arm_movx (code, ARMREG_R0, sreg1);
4247 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4248 (gpointer)"mono_arch_throw_exception");
4251 if (sreg1 != ARMREG_R0)
4252 arm_movx (code, ARMREG_R0, sreg1);
4253 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4254 (gpointer)"mono_arch_rethrow_exception");
4256 case OP_CALL_HANDLER:
4257 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4259 cfg->thunk_area += THUNK_SIZE;
4261 case OP_START_HANDLER: {
4262 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4264 /* Save caller address */
4265 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4268 * Reserve a param area, see test_0_finally_param_area ().
4269 * This is needed because the param area is not set up when
4270 * we are called from EH code.
4272 if (cfg->param_area)
4273 code = emit_subx_sp_imm (code, cfg->param_area);
4277 case OP_ENDFILTER: {
4278 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4280 if (cfg->param_area)
4281 code = emit_addx_sp_imm (code, cfg->param_area);
4283 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4284 arm_movx (code, ARMREG_R0, sreg1);
4286 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4287 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4288 arm_brx (code, ARMREG_LR);
4292 if (ins->dreg != ARMREG_R0)
4293 arm_movx (code, ins->dreg, ARMREG_R0);
4295 case OP_GC_SAFE_POINT: {
4296 #if defined (USE_COOP_GC)
4299 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4300 /* Call it if it is non-null */
4302 arm_cbzx (code, ARMREG_IP1, 0);
4303 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4304 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4310 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4311 g_assert_not_reached ();
4314 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4315 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4316 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4317 g_assert_not_reached ();
4322 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4323 * insert branch islands between/inside basic blocks.
4325 if (cfg->arch.cond_branch_islands)
4326 code = emit_branch_island (cfg, code, start_offset);
4328 cfg->code_len = code - cfg->native_code;
4332 emit_move_args (MonoCompile *cfg, guint8 *code)
4339 cinfo = cfg->arch.cinfo;
4341 for (i = 0; i < cinfo->nargs; ++i) {
4342 ainfo = cinfo->args + i;
4343 ins = cfg->args [i];
4345 if (ins->opcode == OP_REGVAR) {
4346 switch (ainfo->storage) {
4348 arm_movx (code, ins->dreg, ainfo->reg);
4351 switch (ainfo->slot_size) {
4354 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4356 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4360 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4362 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4366 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4368 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4371 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4376 g_assert_not_reached ();
4380 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4381 g_assert (ins->opcode == OP_REGOFFSET);
4383 switch (ainfo->storage) {
4385 /* Stack slots for arguments have size 8 */
4386 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4389 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4392 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4397 case ArgVtypeByRefOnStack:
4398 case ArgVtypeOnStack:
4400 case ArgVtypeByRef: {
4401 MonoInst *addr_arg = ins->inst_left;
4403 if (ainfo->gsharedvt) {
4404 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4405 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4407 g_assert (ins->opcode == OP_VTARG_ADDR);
4408 g_assert (addr_arg->opcode == OP_REGOFFSET);
4409 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4413 case ArgVtypeInIRegs:
4414 for (part = 0; part < ainfo->nregs; part ++) {
4415 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4419 for (part = 0; part < ainfo->nregs; part ++) {
4420 if (ainfo->esize == 4)
4421 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4423 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4427 g_assert_not_reached ();
4437 * emit_store_regarray:
4439 * Emit code to store the registers in REGS into the appropriate elements of
4440 * the register array at BASEREG+OFFSET.
4442 static __attribute__((warn_unused_result)) guint8*
4443 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4447 for (i = 0; i < 32; ++i) {
4448 if (regs & (1 << i)) {
4449 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4450 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4452 } else if (i == ARMREG_SP) {
4453 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4454 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4456 arm_strx (code, i, basereg, offset + (i * 8));
4464 * emit_load_regarray:
4466 * Emit code to load the registers in REGS from the appropriate elements of
4467 * the register array at BASEREG+OFFSET.
4469 static __attribute__((warn_unused_result)) guint8*
4470 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4474 for (i = 0; i < 32; ++i) {
4475 if (regs & (1 << i)) {
4476 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4477 if (offset + (i * 8) < 500)
4478 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4480 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4481 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4484 } else if (i == ARMREG_SP) {
4485 g_assert_not_reached ();
4487 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4495 * emit_store_regset:
4497 * Emit code to store the registers in REGS into consecutive memory locations starting
4498 * at BASEREG+OFFSET.
4500 static __attribute__((warn_unused_result)) guint8*
4501 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4506 for (i = 0; i < 32; ++i) {
4507 if (regs & (1 << i)) {
4508 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4509 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4512 } else if (i == ARMREG_SP) {
4513 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4514 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4516 arm_strx (code, i, basereg, offset + (pos * 8));
4527 * Emit code to load the registers in REGS from consecutive memory locations starting
4528 * at BASEREG+OFFSET.
4530 static __attribute__((warn_unused_result)) guint8*
4531 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4536 for (i = 0; i < 32; ++i) {
4537 if (regs & (1 << i)) {
4538 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4539 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4542 } else if (i == ARMREG_SP) {
4543 g_assert_not_reached ();
4545 arm_ldrx (code, i, basereg, offset + (pos * 8));
4553 __attribute__((warn_unused_result)) guint8*
4554 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4556 return emit_load_regarray (code, regs, basereg, offset);
4559 __attribute__((warn_unused_result)) guint8*
4560 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4562 return emit_store_regarray (code, regs, basereg, offset);
4565 __attribute__((warn_unused_result)) guint8*
4566 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4568 return emit_store_regset (code, regs, basereg, offset);
4571 /* Same as emit_store_regset, but emit unwind info too */
4572 /* CFA_OFFSET is the offset between the CFA and basereg */
4573 static __attribute__((warn_unused_result)) guint8*
4574 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4576 int i, j, pos, nregs;
4577 guint32 cfa_regset = regs & ~no_cfa_regset;
4580 for (i = 0; i < 32; ++i) {
4582 if (regs & (1 << i)) {
4583 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4585 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4587 code = emit_strx (code, i, basereg, offset + (pos * 8));
4588 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4591 } else if (i == ARMREG_SP) {
4592 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4593 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4595 code = emit_strx (code, i, basereg, offset + (pos * 8));
4598 for (j = 0; j < nregs; ++j) {
4599 if (cfa_regset & (1 << (i + j)))
4600 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4613 * Emit code to initialize an LMF structure at LMF_OFFSET.
4617 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4620 * The LMF should contain all the state required to be able to reconstruct the machine state
4621 * at the current point of execution. Since the LMF is only read during EH, only callee
4622 * saved etc. registers need to be saved.
4623 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4624 * need to be restored during EH.
4628 arm_adrx (code, ARMREG_LR, code);
4629 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4630 /* gregs + fp + sp */
4631 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4632 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4638 mono_arch_emit_prolog (MonoCompile *cfg)
4640 MonoMethod *method = cfg->method;
4641 MonoMethodSignature *sig;
4644 int cfa_offset, max_offset;
4646 sig = mono_method_signature (method);
4647 cfg->code_size = 256 + sig->param_count * 64;
4648 code = cfg->native_code = g_malloc (cfg->code_size);
4650 /* This can be unaligned */
4651 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4657 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4660 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4661 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4663 /* sp -= cfg->stack_offset */
4664 /* This clobbers ip0/ip1 */
4665 code = emit_subx_sp_imm (code, cfg->stack_offset);
4666 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4668 cfa_offset += cfg->stack_offset;
4669 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4670 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4671 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4672 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4673 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4674 if (cfg->param_area) {
4675 /* The param area is below the frame pointer */
4676 code = emit_subx_sp_imm (code, cfg->param_area);
4679 if (cfg->method->save_lmf) {
4680 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4683 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4686 /* Setup args reg */
4687 if (cfg->arch.args_reg) {
4688 /* The register was already saved above */
4689 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4692 /* Save return area addr received in R8 */
4693 if (cfg->vret_addr) {
4694 MonoInst *ins = cfg->vret_addr;
4696 g_assert (ins->opcode == OP_REGOFFSET);
4697 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4700 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4701 if (cfg->rgctx_var) {
4702 MonoInst *ins = cfg->rgctx_var;
4704 g_assert (ins->opcode == OP_REGOFFSET);
4706 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4710 * Move arguments to their registers/stack locations.
4712 code = emit_move_args (cfg, code);
4714 /* Initialize seq_point_info_var */
4715 if (cfg->arch.seq_point_info_var) {
4716 MonoInst *ins = cfg->arch.seq_point_info_var;
4718 /* Initialize the variable from a GOT slot */
4719 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4720 g_assert (ins->opcode == OP_REGOFFSET);
4721 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4723 /* Initialize ss_tramp_var */
4724 ins = cfg->arch.ss_tramp_var;
4725 g_assert (ins->opcode == OP_REGOFFSET);
4727 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4728 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4732 if (cfg->arch.ss_tramp_var) {
4733 /* Initialize ss_tramp_var */
4734 ins = cfg->arch.ss_tramp_var;
4735 g_assert (ins->opcode == OP_REGOFFSET);
4737 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4738 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4741 if (cfg->arch.bp_tramp_var) {
4742 /* Initialize bp_tramp_var */
4743 ins = cfg->arch.bp_tramp_var;
4744 g_assert (ins->opcode == OP_REGOFFSET);
4746 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4747 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4752 if (cfg->opt & MONO_OPT_BRANCH) {
4753 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4755 bb->max_offset = max_offset;
4757 MONO_BB_FOR_EACH_INS (bb, ins) {
4758 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4762 if (max_offset > 0x3ffff * 4)
4763 cfg->arch.cond_branch_islands = TRUE;
4769 realloc_code (MonoCompile *cfg, int size)
4771 while (cfg->code_len + size > (cfg->code_size - 16)) {
4772 cfg->code_size *= 2;
4773 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4774 cfg->stat_code_reallocs++;
4776 return cfg->native_code + cfg->code_len;
4780 mono_arch_emit_epilog (MonoCompile *cfg)
4783 int max_epilog_size;
4787 max_epilog_size = 16 + 20*4;
4788 code = realloc_code (cfg, max_epilog_size);
4790 if (cfg->method->save_lmf) {
4791 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4794 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4797 /* Load returned vtypes into registers if needed */
4798 cinfo = cfg->arch.cinfo;
4799 switch (cinfo->ret.storage) {
4800 case ArgVtypeInIRegs: {
4801 MonoInst *ins = cfg->ret;
4803 for (i = 0; i < cinfo->ret.nregs; ++i)
4804 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4808 MonoInst *ins = cfg->ret;
4810 for (i = 0; i < cinfo->ret.nregs; ++i) {
4811 if (cinfo->ret.esize == 4)
4812 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4814 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4823 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4825 arm_retx (code, ARMREG_LR);
4827 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4829 cfg->code_len = code - cfg->native_code;
4833 mono_arch_emit_exceptions (MonoCompile *cfg)
4836 MonoClass *exc_class;
4838 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4839 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4840 int i, id, size = 0;
4842 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4843 exc_throw_pos [i] = NULL;
4844 exc_throw_found [i] = 0;
4847 for (ji = cfg->patch_info; ji; ji = ji->next) {
4848 if (ji->type == MONO_PATCH_INFO_EXC) {
4849 i = mini_exception_id_by_name (ji->data.target);
4850 if (!exc_throw_found [i]) {
4852 exc_throw_found [i] = TRUE;
4857 code = realloc_code (cfg, size);
4859 /* Emit code to raise corlib exceptions */
4860 for (ji = cfg->patch_info; ji; ji = ji->next) {
4861 if (ji->type != MONO_PATCH_INFO_EXC)
4864 ip = cfg->native_code + ji->ip.i;
4866 id = mini_exception_id_by_name (ji->data.target);
4868 if (exc_throw_pos [id]) {
4869 /* ip points to the bcc () in OP_COND_EXC_... */
4870 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4871 ji->type = MONO_PATCH_INFO_NONE;
4875 exc_throw_pos [id] = code;
4876 arm_patch_rel (ip, code, ji->relocation);
4878 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4880 /* r0 = type token */
4881 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4882 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4884 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4885 /* Branch to the corlib exception throwing trampoline */
4886 ji->ip.i = code - cfg->native_code;
4887 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4888 ji->data.name = "mono_arch_throw_corlib_exception";
4889 ji->relocation = MONO_R_ARM64_BL;
4891 cfg->thunk_area += THUNK_SIZE;
4894 cfg->code_len = code - cfg->native_code;
4896 g_assert (cfg->code_len < cfg->code_size);
4900 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4906 mono_arch_print_tree (MonoInst *tree, int arity)
4912 mono_arch_get_patch_offset (guint8 *code)
4918 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4919 gpointer fail_tramp)
4921 int i, buf_len, imt_reg;
4925 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4926 for (i = 0; i < count; ++i) {
4927 MonoIMTCheckItem *item = imt_entries [i];
4928 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
4933 for (i = 0; i < count; ++i) {
4934 MonoIMTCheckItem *item = imt_entries [i];
4935 if (item->is_equals) {
4936 gboolean fail_case = !item->check_target_idx && fail_tramp;
4938 if (item->check_target_idx || fail_case) {
4939 if (!item->compare_done || fail_case) {
4940 buf_len += 4 * 4 + 4;
4943 if (item->has_target_code) {
4960 buf = mono_method_alloc_generic_virtual_thunk (domain, buf_len);
4962 buf = mono_domain_code_reserve (domain, buf_len);
4966 * We are called by JITted code, which passes in the IMT argument in
4967 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
4970 imt_reg = MONO_ARCH_RGCTX_REG;
4971 for (i = 0; i < count; ++i) {
4972 MonoIMTCheckItem *item = imt_entries [i];
4974 item->code_target = code;
4976 if (item->is_equals) {
4978 * Check the imt argument against item->key, if equals, jump to either
4979 * item->value.target_code or to vtable [item->value.vtable_slot].
4980 * If fail_tramp is set, jump to it if not-equals.
4982 gboolean fail_case = !item->check_target_idx && fail_tramp;
4984 if (item->check_target_idx || fail_case) {
4985 /* Compare imt_reg with item->key */
4986 if (!item->compare_done || fail_case) {
4987 // FIXME: Optimize this
4988 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
4989 arm_cmpx (code, imt_reg, ARMREG_IP0);
4991 item->jmp_code = code;
4992 arm_bcc (code, ARMCOND_NE, 0);
4993 /* Jump to target if equals */
4994 if (item->has_target_code) {
4995 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
4996 arm_brx (code, ARMREG_IP0);
4998 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5000 code = emit_imm64 (code, ARMREG_IP0, imm);
5001 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5002 arm_brx (code, ARMREG_IP0);
5006 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5007 item->jmp_code = NULL;
5008 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5009 arm_brx (code, ARMREG_IP0);
5012 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5014 code = emit_imm64 (code, ARMREG_IP0, imm);
5015 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5016 arm_brx (code, ARMREG_IP0);
5019 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5020 arm_cmpx (code, imt_reg, ARMREG_IP0);
5021 item->jmp_code = code;
5022 arm_bcc (code, ARMCOND_HS, 0);
5025 /* Patch the branches */
5026 for (i = 0; i < count; ++i) {
5027 MonoIMTCheckItem *item = imt_entries [i];
5028 if (item->jmp_code && item->check_target_idx)
5029 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5032 g_assert ((code - buf) < buf_len);
5034 mono_arch_flush_icache (buf, code - buf);
5040 mono_arch_get_trampolines (gboolean aot)
5042 return mono_arm_get_exception_trampolines (aot);
5045 #else /* DISABLE_JIT */
5048 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5049 gpointer fail_tramp)
5051 g_assert_not_reached ();
5055 #endif /* !DISABLE_JIT */
5057 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5060 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5063 guint32 native_offset = ip - (guint8*)ji->code_start;
5066 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5068 g_assert (native_offset % 4 == 0);
5069 g_assert (info->bp_addrs [native_offset / 4] == 0);
5070 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5072 /* ip points to an ldrx */
5074 arm_blrx (code, ARMREG_IP0);
5075 mono_arch_flush_icache (ip, code - ip);
5080 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5085 guint32 native_offset = ip - (guint8*)ji->code_start;
5086 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5088 g_assert (native_offset % 4 == 0);
5089 info->bp_addrs [native_offset / 4] = NULL;
5091 /* ip points to an ldrx */
5094 mono_arch_flush_icache (ip, code - ip);
5099 mono_arch_start_single_stepping (void)
5101 ss_trampoline = mini_get_single_step_trampoline ();
5105 mono_arch_stop_single_stepping (void)
5107 ss_trampoline = NULL;
5111 mono_arch_is_single_step_event (void *info, void *sigctx)
5113 /* We use soft breakpoints on arm64 */
5118 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5120 /* We use soft breakpoints on arm64 */
5125 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5127 g_assert_not_reached ();
5131 mono_arch_skip_single_step (MonoContext *ctx)
5133 g_assert_not_reached ();
5137 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5142 // FIXME: Add a free function
5144 mono_domain_lock (domain);
5145 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5147 mono_domain_unlock (domain);
5150 ji = mono_jit_info_table_find (domain, (char*)code);
5153 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5155 info->ss_tramp_addr = &ss_trampoline;
5157 mono_domain_lock (domain);
5158 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5160 mono_domain_unlock (domain);
5167 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5169 ext->lmf.previous_lmf = prev_lmf;
5170 /* Mark that this is a MonoLMFExt */
5171 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5172 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5175 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5178 mono_arch_opcode_supported (int opcode)
5181 case OP_ATOMIC_ADD_I4:
5182 case OP_ATOMIC_ADD_I8:
5183 case OP_ATOMIC_EXCHANGE_I4:
5184 case OP_ATOMIC_EXCHANGE_I8:
5185 case OP_ATOMIC_CAS_I4:
5186 case OP_ATOMIC_CAS_I8:
5187 case OP_ATOMIC_LOAD_I1:
5188 case OP_ATOMIC_LOAD_I2:
5189 case OP_ATOMIC_LOAD_I4:
5190 case OP_ATOMIC_LOAD_I8:
5191 case OP_ATOMIC_LOAD_U1:
5192 case OP_ATOMIC_LOAD_U2:
5193 case OP_ATOMIC_LOAD_U4:
5194 case OP_ATOMIC_LOAD_U8:
5195 case OP_ATOMIC_LOAD_R4:
5196 case OP_ATOMIC_LOAD_R8:
5197 case OP_ATOMIC_STORE_I1:
5198 case OP_ATOMIC_STORE_I2:
5199 case OP_ATOMIC_STORE_I4:
5200 case OP_ATOMIC_STORE_I8:
5201 case OP_ATOMIC_STORE_U1:
5202 case OP_ATOMIC_STORE_U2:
5203 case OP_ATOMIC_STORE_U4:
5204 case OP_ATOMIC_STORE_U8:
5205 case OP_ATOMIC_STORE_R4:
5206 case OP_ATOMIC_STORE_R8:
5214 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5216 return get_call_info (mp, sig);
5220 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
5227 bp = MONO_CONTEXT_GET_BP (ctx);
5228 lr_loc = (gpointer*)(bp + clause->exvar_offset);
5230 old_value = *lr_loc;
5231 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
5234 *lr_loc = new_value;