2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 /* Sanity check: This makes no sense */
34 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
35 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
39 * IS_SOFT_FLOAT: Is full software floating point used?
40 * IS_HARD_FLOAT: Is full hardware floating point used?
41 * IS_VFP: Is hardware floating point with software ABI used?
43 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
44 * IS_VFP may delegate to mono_arch_is_soft_float ().
47 #if defined(ARM_FPU_VFP_HARD)
48 #define IS_SOFT_FLOAT (FALSE)
49 #define IS_HARD_FLOAT (TRUE)
51 #elif defined(ARM_FPU_NONE)
52 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
53 #define IS_HARD_FLOAT (FALSE)
54 #define IS_VFP (!mono_arch_is_soft_float ())
56 #define IS_SOFT_FLOAT (FALSE)
57 #define IS_HARD_FLOAT (FALSE)
61 #define THUNK_SIZE (3 * 4)
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
66 void sys_icache_invalidate (void *start, size_t len);
69 /* This mutex protects architecture specific caches */
70 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
71 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
72 static mono_mutex_t mini_arch_mutex;
74 static gboolean v5_supported = FALSE;
75 static gboolean v6_supported = FALSE;
76 static gboolean v7_supported = FALSE;
77 static gboolean v7s_supported = FALSE;
78 static gboolean v7k_supported = FALSE;
79 static gboolean thumb_supported = FALSE;
80 static gboolean thumb2_supported = FALSE;
82 * Whenever to use the ARM EABI
84 static gboolean eabi_supported = FALSE;
87 * Whenever to use the iphone ABI extensions:
88 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
89 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
90 * This is required for debugging/profiling tools to work, but it has some overhead so it should
91 * only be turned on in debug builds.
93 static gboolean iphone_abi = FALSE;
96 * The FPU we are generating code for. This is NOT runtime configurable right now,
97 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
99 static MonoArmFPU arm_fpu;
101 #if defined(ARM_FPU_VFP_HARD)
103 * On armhf, d0-d7 are used for argument passing and d8-d15
104 * must be preserved across calls, which leaves us no room
105 * for scratch registers. So we use d14-d15 but back up their
106 * previous contents to a stack slot before using them - see
107 * mono_arm_emit_vfp_scratch_save/_restore ().
109 static int vfp_scratch1 = ARM_VFP_D14;
110 static int vfp_scratch2 = ARM_VFP_D15;
113 * On armel, d0-d7 do not need to be preserved, so we can
114 * freely make use of them as scratch registers.
116 static int vfp_scratch1 = ARM_VFP_D0;
117 static int vfp_scratch2 = ARM_VFP_D1;
122 static gpointer single_step_tramp, breakpoint_tramp;
123 static gpointer get_tls_tramp;
126 * The code generated for sequence points reads from this location, which is
127 * made read-only when single stepping is enabled.
129 static gpointer ss_trigger_page;
131 /* Enabled breakpoints read from this trigger page */
132 static gpointer bp_trigger_page;
136 * floating point support: on ARM it is a mess, there are at least 3
137 * different setups, each of which binary incompat with the other.
138 * 1) FPA: old and ugly, but unfortunately what current distros use
139 * the double binary format has the two words swapped. 8 double registers.
140 * Implemented usually by kernel emulation.
141 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
142 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
143 * 3) VFP: the new and actually sensible and useful FP support. Implemented
144 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
146 * We do not care about FPA. We will support soft float and VFP.
148 int mono_exc_esp_offset = 0;
150 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
151 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
152 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
154 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
155 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
156 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
158 //#define DEBUG_IMT 0
161 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
168 mono_arch_regname (int reg)
170 static const char * rnames[] = {
171 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
172 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
173 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
176 if (reg >= 0 && reg < 16)
182 mono_arch_fregname (int reg)
184 static const char * rnames[] = {
185 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
186 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
187 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
188 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
189 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
190 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
193 if (reg >= 0 && reg < 32)
201 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
203 int imm8, rot_amount;
204 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
205 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
209 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
210 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
218 /* If dreg == sreg, this clobbers IP */
220 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
222 int imm8, rot_amount;
223 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
224 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
228 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
229 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
231 code = mono_arm_emit_load_imm (code, dreg, imm);
232 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
238 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
240 /* we can use r0-r3, since this is called only for incoming args on the stack */
241 if (size > sizeof (gpointer) * 4) {
243 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
244 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
245 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
246 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
247 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
248 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
250 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
251 ARM_B_COND (code, ARMCOND_NE, 0);
252 arm_patch (code - 4, start_loop);
255 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
256 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
258 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
259 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 doffset = soffset = 0;
269 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
270 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
276 g_assert (size == 0);
281 emit_call_reg (guint8 *code, int reg)
284 ARM_BLX_REG (code, reg);
286 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
290 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
296 emit_call_seq (MonoCompile *cfg, guint8 *code)
298 if (cfg->method->dynamic) {
299 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
301 *(gpointer*)code = NULL;
303 code = emit_call_reg (code, ARMREG_IP);
307 cfg->thunk_area += THUNK_SIZE;
312 mono_arm_patchable_b (guint8 *code, int cond)
314 ARM_B_COND (code, cond, 0);
319 mono_arm_patchable_bl (guint8 *code, int cond)
321 ARM_BL_COND (code, cond, 0);
326 mono_arch_have_fast_tls (void)
334 * Emit code to push an LMF structure on the LMF stack.
335 * On arm, this is intermixed with the initialization of other fields of the structure.
338 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
342 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
343 (gpointer)"mono_get_lmf_addr");
344 code = emit_call_seq (cfg, code);
345 /* we build the MonoLMF structure on the stack - see mini-arm.h */
346 /* lmf_offset is the offset from the previous stack pointer,
347 * alloc_size is the total stack space allocated, so the offset
348 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
349 * The pointer to the struct is put in r1 (new_lmf).
350 * ip is used as scratch
351 * The callee-saved registers are already in the MonoLMF structure
353 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
354 /* r0 is the result from mono_get_lmf_addr () */
355 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
356 /* new_lmf->previous_lmf = *lmf_addr */
357 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
358 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
359 /* *(lmf_addr) = r1 */
360 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
361 /* Skip method (only needed for trampoline LMF frames) */
362 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
363 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
364 /* save the current IP */
365 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
366 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
368 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
369 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
380 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
384 for (list = inst->float_args; list; list = list->next) {
385 FloatArgData *fad = list->data;
386 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
387 gboolean imm = arm_is_fpimm8 (var->inst_offset);
389 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
395 if (*offset + *max_len > cfg->code_size) {
396 cfg->code_size += *max_len;
397 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
399 code = cfg->native_code + *offset;
403 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
404 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
406 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
408 *offset = code - cfg->native_code;
415 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
419 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
421 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
424 if (!arm_is_fpimm8 (inst->inst_offset)) {
425 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
426 ARM_FSTD (code, reg, ARMREG_LR, 0);
428 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
435 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
439 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
441 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
444 if (!arm_is_fpimm8 (inst->inst_offset)) {
445 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
446 ARM_FLDD (code, reg, ARMREG_LR, 0);
448 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
457 * Emit code to pop an LMF structure from the LMF stack.
460 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
464 if (lmf_offset < 32) {
465 basereg = cfg->frame_reg;
470 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
473 /* ip = previous_lmf */
474 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
476 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
477 /* *(lmf_addr) = previous_lmf */
478 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
483 #endif /* #ifndef DISABLE_JIT */
486 * mono_arch_get_argument_info:
487 * @csig: a method signature
488 * @param_count: the number of parameters to consider
489 * @arg_info: an array to store the result infos
491 * Gathers information on parameters such as size, alignment and
492 * padding. arg_info should be large enought to hold param_count + 1 entries.
494 * Returns the size of the activation frame.
497 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
499 int k, frame_size = 0;
500 guint32 size, align, pad;
504 t = mini_get_underlying_type (csig->ret);
505 if (MONO_TYPE_ISSTRUCT (t)) {
506 frame_size += sizeof (gpointer);
510 arg_info [0].offset = offset;
513 frame_size += sizeof (gpointer);
517 arg_info [0].size = frame_size;
519 for (k = 0; k < param_count; k++) {
520 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
522 /* ignore alignment for now */
525 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
526 arg_info [k].pad = pad;
528 arg_info [k + 1].pad = 0;
529 arg_info [k + 1].size = size;
531 arg_info [k + 1].offset = offset;
535 align = MONO_ARCH_FRAME_ALIGNMENT;
536 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
537 arg_info [k].pad = pad;
542 #define MAX_ARCH_DELEGATE_PARAMS 3
545 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
547 guint8 *code, *start;
548 GSList *unwind_ops = mono_arch_get_cie_program ();
551 start = code = mono_global_codeman_reserve (12);
553 /* Replace the this argument with the target */
554 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
555 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
556 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
558 g_assert ((code - start) <= 12);
560 mono_arch_flush_icache (start, 12);
564 size = 8 + param_count * 4;
565 start = code = mono_global_codeman_reserve (size);
567 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
568 /* slide down the arguments */
569 for (i = 0; i < param_count; ++i) {
570 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
572 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
574 g_assert ((code - start) <= size);
576 mono_arch_flush_icache (start, size);
580 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
582 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
583 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
587 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
593 * mono_arch_get_delegate_invoke_impls:
595 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
599 mono_arch_get_delegate_invoke_impls (void)
605 get_delegate_invoke_impl (&info, TRUE, 0);
606 res = g_slist_prepend (res, info);
608 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
609 get_delegate_invoke_impl (&info, FALSE, i);
610 res = g_slist_prepend (res, info);
617 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
619 guint8 *code, *start;
622 /* FIXME: Support more cases */
623 sig_ret = mini_get_underlying_type (sig->ret);
624 if (MONO_TYPE_ISSTRUCT (sig_ret))
628 static guint8* cached = NULL;
629 mono_mini_arch_lock ();
631 mono_mini_arch_unlock ();
636 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
639 start = get_delegate_invoke_impl (&info, TRUE, 0);
640 mono_tramp_info_register (info, NULL);
643 mono_mini_arch_unlock ();
646 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
649 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
651 for (i = 0; i < sig->param_count; ++i)
652 if (!mono_is_regsize_var (sig->params [i]))
655 mono_mini_arch_lock ();
656 code = cache [sig->param_count];
658 mono_mini_arch_unlock ();
663 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
664 start = mono_aot_get_trampoline (name);
668 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
669 mono_tramp_info_register (info, NULL);
671 cache [sig->param_count] = start;
672 mono_mini_arch_unlock ();
680 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
686 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
688 return (gpointer)regs [ARMREG_R0];
692 * Initialize the cpu to execute managed code.
695 mono_arch_cpu_init (void)
697 i8_align = MONO_ABI_ALIGNOF (gint64);
698 #ifdef MONO_CROSS_COMPILE
699 /* Need to set the alignment of i8 since it can different on the target */
700 #ifdef TARGET_ANDROID
702 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
708 * Initialize architecture specific code.
711 mono_arch_init (void)
713 const char *cpu_arch;
715 #ifdef TARGET_WATCHOS
716 mini_get_debug_options ()->soft_breakpoints = TRUE;
719 mono_os_mutex_init_recursive (&mini_arch_mutex);
720 if (mini_get_debug_options ()->soft_breakpoints) {
722 breakpoint_tramp = mini_get_breakpoint_trampoline ();
724 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
725 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
726 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
729 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
730 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
731 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
732 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
733 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
735 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
737 #if defined(__ARM_EABI__)
738 eabi_supported = TRUE;
741 #if defined(ARM_FPU_VFP_HARD)
742 arm_fpu = MONO_ARM_FPU_VFP_HARD;
744 arm_fpu = MONO_ARM_FPU_VFP;
746 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
748 * If we're compiling with a soft float fallback and it
749 * turns out that no VFP unit is available, we need to
750 * switch to soft float. We don't do this for iOS, since
751 * iOS devices always have a VFP unit.
753 if (!mono_hwcap_arm_has_vfp)
754 arm_fpu = MONO_ARM_FPU_NONE;
757 * This environment variable can be useful in testing
758 * environments to make sure the soft float fallback
759 * works. Most ARM devices have VFP units these days, so
760 * normally soft float code would not be exercised much.
762 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
764 if (soft && !strncmp (soft, "1", 1))
765 arm_fpu = MONO_ARM_FPU_NONE;
769 v5_supported = mono_hwcap_arm_is_v5;
770 v6_supported = mono_hwcap_arm_is_v6;
771 v7_supported = mono_hwcap_arm_is_v7;
774 * On weird devices, the hwcap code may fail to detect
775 * the ARM version. In that case, we can at least safely
776 * assume the version the runtime was compiled for.
788 #if defined(__APPLE__)
789 /* iOS is special-cased here because we don't yet
790 have a way to properly detect CPU features on it. */
791 thumb_supported = TRUE;
794 thumb_supported = mono_hwcap_arm_has_thumb;
795 thumb2_supported = mono_hwcap_arm_has_thumb2;
798 /* Format: armv(5|6|7[s])[-thumb[2]] */
799 cpu_arch = g_getenv ("MONO_CPU_ARCH");
801 /* Do this here so it overrides any detection. */
803 if (strncmp (cpu_arch, "armv", 4) == 0) {
804 v5_supported = cpu_arch [4] >= '5';
805 v6_supported = cpu_arch [4] >= '6';
806 v7_supported = cpu_arch [4] >= '7';
807 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
808 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
811 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
812 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
817 * Cleanup architecture specific code.
820 mono_arch_cleanup (void)
825 * This function returns the optimizations supported on this cpu.
828 mono_arch_cpu_optimizations (guint32 *exclude_mask)
830 /* no arm-specific optimizations yet */
836 * This function test for all SIMD functions supported.
838 * Returns a bitmask corresponding to all supported versions.
842 mono_arch_cpu_enumerate_simd_versions (void)
844 /* SIMD is currently unimplemented */
849 mono_arm_is_hard_float (void)
851 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
857 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
859 if (v7s_supported || v7k_supported) {
873 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
875 mono_arch_is_soft_float (void)
877 return arm_fpu == MONO_ARM_FPU_NONE;
882 is_regsize_var (MonoType *t)
886 t = mini_get_underlying_type (t);
893 case MONO_TYPE_FNPTR:
895 case MONO_TYPE_OBJECT:
896 case MONO_TYPE_STRING:
897 case MONO_TYPE_CLASS:
898 case MONO_TYPE_SZARRAY:
899 case MONO_TYPE_ARRAY:
901 case MONO_TYPE_GENERICINST:
902 if (!mono_type_generic_inst_is_valuetype (t))
905 case MONO_TYPE_VALUETYPE:
912 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
917 for (i = 0; i < cfg->num_varinfo; i++) {
918 MonoInst *ins = cfg->varinfo [i];
919 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
922 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
925 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 /* we can only allocate 32 bit values */
929 if (is_regsize_var (ins->inst_vtype)) {
930 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
931 g_assert (i == vmv->idx);
932 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
940 mono_arch_get_global_int_regs (MonoCompile *cfg)
944 mono_arch_compute_omit_fp (cfg);
947 * FIXME: Interface calls might go through a static rgctx trampoline which
948 * sets V5, but it doesn't save it, so we need to save it ourselves, and
951 if (cfg->flags & MONO_CFG_HAS_CALLS)
952 cfg->uses_rgctx_reg = TRUE;
954 if (cfg->arch.omit_fp)
955 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
956 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
957 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
958 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
960 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
961 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
963 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
964 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
965 /* V5 is reserved for passing the vtable/rgctx/IMT method */
966 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
967 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
968 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
974 * mono_arch_regalloc_cost:
976 * Return the cost, in number of memory references, of the action of
977 * allocating the variable VMV into a register during global register
981 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
987 #endif /* #ifndef DISABLE_JIT */
990 mono_arch_flush_icache (guint8 *code, gint size)
992 #if defined(MONO_CROSS_COMPILE)
994 sys_icache_invalidate (code, size);
996 __builtin___clear_cache (code, code + size);
1003 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1006 if (*gr > ARMREG_R3) {
1008 ainfo->offset = *stack_size;
1009 ainfo->reg = ARMREG_SP; /* in the caller */
1010 ainfo->storage = RegTypeBase;
1013 ainfo->storage = RegTypeGeneral;
1020 split = i8_align == 4;
1025 if (*gr == ARMREG_R3 && split) {
1026 /* first word in r3 and the second on the stack */
1027 ainfo->offset = *stack_size;
1028 ainfo->reg = ARMREG_SP; /* in the caller */
1029 ainfo->storage = RegTypeBaseGen;
1031 } else if (*gr >= ARMREG_R3) {
1032 if (eabi_supported) {
1033 /* darwin aligns longs to 4 byte only */
1034 if (i8_align == 8) {
1039 ainfo->offset = *stack_size;
1040 ainfo->reg = ARMREG_SP; /* in the caller */
1041 ainfo->storage = RegTypeBase;
1044 if (eabi_supported) {
1045 if (i8_align == 8 && ((*gr) & 1))
1048 ainfo->storage = RegTypeIRegPair;
1057 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1060 * If we're calling a function like this:
1062 * void foo(float a, double b, float c)
1064 * We pass a in s0 and b in d1. That leaves us
1065 * with s1 being unused. The armhf ABI recognizes
1066 * this and requires register assignment to then
1067 * use that for the next single-precision arg,
1068 * i.e. c in this example. So float_spare either
1069 * tells us which reg to use for the next single-
1070 * precision arg, or it's -1, meaning use *fpr.
1072 * Note that even though most of the JIT speaks
1073 * double-precision, fpr represents single-
1074 * precision registers.
1076 * See parts 5.5 and 6.1.2 of the AAPCS for how
1080 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1081 ainfo->storage = RegTypeFP;
1085 * If we're passing a double-precision value
1086 * and *fpr is odd (e.g. it's s1, s3, ...)
1087 * we need to use the next even register. So
1088 * we mark the current *fpr as a spare that
1089 * can be used for the next single-precision
1093 *float_spare = *fpr;
1098 * At this point, we have an even register
1099 * so we assign that and move along.
1103 } else if (*float_spare >= 0) {
1105 * We're passing a single-precision value
1106 * and it looks like a spare single-
1107 * precision register is available. Let's
1111 ainfo->reg = *float_spare;
1115 * If we hit this branch, we're passing a
1116 * single-precision value and we can simply
1117 * use the next available register.
1125 * We've exhausted available floating point
1126 * regs, so pass the rest on the stack.
1134 ainfo->offset = *stack_size;
1135 ainfo->reg = ARMREG_SP;
1136 ainfo->storage = RegTypeBase;
1143 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1147 MonoClassField *field;
1148 MonoType *ftype, *prev_ftype = NULL;
1151 klass = mono_class_from_mono_type (t);
1153 while ((field = mono_class_get_fields (klass, &iter))) {
1154 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1156 ftype = mono_field_get_type (field);
1157 ftype = mini_get_underlying_type (ftype);
1159 if (MONO_TYPE_ISSTRUCT (ftype)) {
1160 int nested_nfields, nested_esize;
1162 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1164 if (nested_esize == 4)
1165 ftype = &mono_defaults.single_class->byval_arg;
1167 ftype = &mono_defaults.double_class->byval_arg;
1168 if (prev_ftype && prev_ftype->type != ftype->type)
1171 nfields += nested_nfields;
1173 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1175 if (prev_ftype && prev_ftype->type != ftype->type)
1181 if (nfields == 0 || nfields > 4)
1183 *out_nfields = nfields;
1184 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1189 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1191 guint i, gr, fpr, pstart;
1193 int n = sig->hasthis + sig->param_count;
1197 guint32 stack_size = 0;
1199 gboolean is_pinvoke = sig->pinvoke;
1200 gboolean vtype_retaddr = FALSE;
1203 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1205 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1212 t = mini_get_underlying_type (sig->ret);
1223 case MONO_TYPE_FNPTR:
1224 case MONO_TYPE_CLASS:
1225 case MONO_TYPE_OBJECT:
1226 case MONO_TYPE_SZARRAY:
1227 case MONO_TYPE_ARRAY:
1228 case MONO_TYPE_STRING:
1229 cinfo->ret.storage = RegTypeGeneral;
1230 cinfo->ret.reg = ARMREG_R0;
1234 cinfo->ret.storage = RegTypeIRegPair;
1235 cinfo->ret.reg = ARMREG_R0;
1239 cinfo->ret.storage = RegTypeFP;
1241 if (t->type == MONO_TYPE_R4)
1242 cinfo->ret.size = 4;
1244 cinfo->ret.size = 8;
1246 if (IS_HARD_FLOAT) {
1247 cinfo->ret.reg = ARM_VFP_F0;
1249 cinfo->ret.reg = ARMREG_R0;
1252 case MONO_TYPE_GENERICINST:
1253 if (!mono_type_generic_inst_is_valuetype (t)) {
1254 cinfo->ret.storage = RegTypeGeneral;
1255 cinfo->ret.reg = ARMREG_R0;
1258 if (mini_is_gsharedvt_variable_type (t)) {
1259 cinfo->ret.storage = RegTypeStructByAddr;
1263 case MONO_TYPE_VALUETYPE:
1264 case MONO_TYPE_TYPEDBYREF:
1265 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1266 cinfo->ret.storage = RegTypeHFA;
1268 cinfo->ret.nregs = nfields;
1269 cinfo->ret.esize = esize;
1272 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1275 #ifdef TARGET_WATCHOS
1280 if (native_size <= max_size) {
1281 cinfo->ret.storage = RegTypeStructByVal;
1282 cinfo->ret.struct_size = native_size;
1283 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1285 cinfo->ret.storage = RegTypeStructByAddr;
1288 cinfo->ret.storage = RegTypeStructByAddr;
1293 case MONO_TYPE_MVAR:
1294 g_assert (mini_is_gsharedvt_type (t));
1295 cinfo->ret.storage = RegTypeStructByAddr;
1297 case MONO_TYPE_VOID:
1300 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1303 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1308 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1309 * the first argument, allowing 'this' to be always passed in the first arg reg.
1310 * Also do this if the first argument is a reference type, since virtual calls
1311 * are sometimes made using calli without sig->hasthis set, like in the delegate
1314 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1316 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1318 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1322 cinfo->ret.reg = gr;
1324 cinfo->vret_arg_index = 1;
1328 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1331 if (vtype_retaddr) {
1332 cinfo->ret.reg = gr;
1337 DEBUG(g_print("params: %d\n", sig->param_count));
1338 for (i = pstart; i < sig->param_count; ++i) {
1339 ArgInfo *ainfo = &cinfo->args [n];
1341 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1342 /* Prevent implicit arguments and sig_cookie from
1343 being passed in registers */
1346 /* Emit the signature cookie just before the implicit arguments */
1347 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1349 DEBUG(g_print("param %d: ", i));
1350 if (sig->params [i]->byref) {
1351 DEBUG(g_print("byref\n"));
1352 add_general (&gr, &stack_size, ainfo, TRUE);
1356 t = mini_get_underlying_type (sig->params [i]);
1360 cinfo->args [n].size = 1;
1361 add_general (&gr, &stack_size, ainfo, TRUE);
1365 cinfo->args [n].size = 2;
1366 add_general (&gr, &stack_size, ainfo, TRUE);
1370 cinfo->args [n].size = 4;
1371 add_general (&gr, &stack_size, ainfo, TRUE);
1376 case MONO_TYPE_FNPTR:
1377 case MONO_TYPE_CLASS:
1378 case MONO_TYPE_OBJECT:
1379 case MONO_TYPE_STRING:
1380 case MONO_TYPE_SZARRAY:
1381 case MONO_TYPE_ARRAY:
1382 cinfo->args [n].size = sizeof (gpointer);
1383 add_general (&gr, &stack_size, ainfo, TRUE);
1385 case MONO_TYPE_GENERICINST:
1386 if (!mono_type_generic_inst_is_valuetype (t)) {
1387 cinfo->args [n].size = sizeof (gpointer);
1388 add_general (&gr, &stack_size, ainfo, TRUE);
1391 if (mini_is_gsharedvt_variable_type (t)) {
1392 /* gsharedvt arguments are passed by ref */
1393 g_assert (mini_is_gsharedvt_type (t));
1394 add_general (&gr, &stack_size, ainfo, TRUE);
1395 switch (ainfo->storage) {
1396 case RegTypeGeneral:
1397 ainfo->storage = RegTypeGSharedVtInReg;
1400 ainfo->storage = RegTypeGSharedVtOnStack;
1403 g_assert_not_reached ();
1408 case MONO_TYPE_TYPEDBYREF:
1409 case MONO_TYPE_VALUETYPE: {
1412 int nwords, nfields, esize;
1415 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1416 if (fpr + nfields < ARM_VFP_F16) {
1417 ainfo->storage = RegTypeHFA;
1419 ainfo->nregs = nfields;
1420 ainfo->esize = esize;
1431 if (t->type == MONO_TYPE_TYPEDBYREF) {
1432 size = sizeof (MonoTypedRef);
1433 align = sizeof (gpointer);
1435 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1437 size = mono_class_native_size (klass, &align);
1439 size = mini_type_stack_size_full (t, &align, FALSE);
1441 DEBUG(g_print ("load %d bytes struct\n", size));
1443 #ifdef TARGET_WATCHOS
1444 /* Watchos pass large structures by ref */
1445 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1446 if (sig->pinvoke && size > 16) {
1447 add_general (&gr, &stack_size, ainfo, TRUE);
1448 switch (ainfo->storage) {
1449 case RegTypeGeneral:
1450 ainfo->storage = RegTypeStructByAddr;
1453 ainfo->storage = RegTypeStructByAddrOnStack;
1456 g_assert_not_reached ();
1465 align_size += (sizeof (gpointer) - 1);
1466 align_size &= ~(sizeof (gpointer) - 1);
1467 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1468 ainfo->storage = RegTypeStructByVal;
1469 ainfo->struct_size = size;
1470 /* FIXME: align stack_size if needed */
1471 if (eabi_supported) {
1472 if (align >= 8 && (gr & 1))
1475 if (gr > ARMREG_R3) {
1477 ainfo->vtsize = nwords;
1479 int rest = ARMREG_R3 - gr + 1;
1480 int n_in_regs = rest >= nwords? nwords: rest;
1482 ainfo->size = n_in_regs;
1483 ainfo->vtsize = nwords - n_in_regs;
1486 nwords -= n_in_regs;
1488 if (sig->call_convention == MONO_CALL_VARARG)
1489 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1490 stack_size = ALIGN_TO (stack_size, align);
1491 ainfo->offset = stack_size;
1492 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1493 stack_size += nwords * sizeof (gpointer);
1499 add_general (&gr, &stack_size, ainfo, FALSE);
1505 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1507 add_general (&gr, &stack_size, ainfo, TRUE);
1513 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1515 add_general (&gr, &stack_size, ainfo, FALSE);
1518 case MONO_TYPE_MVAR:
1519 /* gsharedvt arguments are passed by ref */
1520 g_assert (mini_is_gsharedvt_type (t));
1521 add_general (&gr, &stack_size, ainfo, TRUE);
1522 switch (ainfo->storage) {
1523 case RegTypeGeneral:
1524 ainfo->storage = RegTypeGSharedVtInReg;
1527 ainfo->storage = RegTypeGSharedVtOnStack;
1530 g_assert_not_reached ();
1534 g_error ("Can't handle 0x%x", sig->params [i]->type);
1539 /* Handle the case where there are no implicit arguments */
1540 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1541 /* Prevent implicit arguments and sig_cookie from
1542 being passed in registers */
1545 /* Emit the signature cookie just before the implicit arguments */
1546 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1549 /* align stack size to 8 */
1550 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1551 stack_size = (stack_size + 7) & ~7;
1553 cinfo->stack_usage = stack_size;
1559 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1561 MonoType *callee_ret;
1565 c1 = get_call_info (NULL, caller_sig);
1566 c2 = get_call_info (NULL, callee_sig);
1569 * Tail calls with more callee stack usage than the caller cannot be supported, since
1570 * the extra stack space would be left on the stack after the tail call.
1572 res = c1->stack_usage >= c2->stack_usage;
1573 callee_ret = mini_get_underlying_type (callee_sig->ret);
1574 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1575 /* An address on the callee's stack is passed as the first argument */
1578 if (c2->stack_usage > 16 * 4)
1590 debug_omit_fp (void)
1593 return mono_debug_count ();
1600 * mono_arch_compute_omit_fp:
1602 * Determine whenever the frame pointer can be eliminated.
1605 mono_arch_compute_omit_fp (MonoCompile *cfg)
1607 MonoMethodSignature *sig;
1608 MonoMethodHeader *header;
1612 if (cfg->arch.omit_fp_computed)
1615 header = cfg->header;
1617 sig = mono_method_signature (cfg->method);
1619 if (!cfg->arch.cinfo)
1620 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1621 cinfo = cfg->arch.cinfo;
1624 * FIXME: Remove some of the restrictions.
1626 cfg->arch.omit_fp = TRUE;
1627 cfg->arch.omit_fp_computed = TRUE;
1629 if (cfg->disable_omit_fp)
1630 cfg->arch.omit_fp = FALSE;
1631 if (!debug_omit_fp ())
1632 cfg->arch.omit_fp = FALSE;
1634 if (cfg->method->save_lmf)
1635 cfg->arch.omit_fp = FALSE;
1637 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1638 cfg->arch.omit_fp = FALSE;
1639 if (header->num_clauses)
1640 cfg->arch.omit_fp = FALSE;
1641 if (cfg->param_area)
1642 cfg->arch.omit_fp = FALSE;
1643 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1644 cfg->arch.omit_fp = FALSE;
1645 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1646 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1647 cfg->arch.omit_fp = FALSE;
1648 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1649 ArgInfo *ainfo = &cinfo->args [i];
1651 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1653 * The stack offset can only be determined when the frame
1656 cfg->arch.omit_fp = FALSE;
1661 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1662 MonoInst *ins = cfg->varinfo [i];
1665 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1670 * Set var information according to the calling convention. arm version.
1671 * The locals var stuff should most likely be split in another method.
1674 mono_arch_allocate_vars (MonoCompile *cfg)
1676 MonoMethodSignature *sig;
1677 MonoMethodHeader *header;
1680 int i, offset, size, align, curinst;
1685 sig = mono_method_signature (cfg->method);
1687 if (!cfg->arch.cinfo)
1688 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1689 cinfo = cfg->arch.cinfo;
1690 sig_ret = mini_get_underlying_type (sig->ret);
1692 mono_arch_compute_omit_fp (cfg);
1694 if (cfg->arch.omit_fp)
1695 cfg->frame_reg = ARMREG_SP;
1697 cfg->frame_reg = ARMREG_FP;
1699 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1701 /* allow room for the vararg method args: void* and long/double */
1702 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1703 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1705 header = cfg->header;
1707 /* See mono_arch_get_global_int_regs () */
1708 if (cfg->flags & MONO_CFG_HAS_CALLS)
1709 cfg->uses_rgctx_reg = TRUE;
1711 if (cfg->frame_reg != ARMREG_SP)
1712 cfg->used_int_regs |= 1 << cfg->frame_reg;
1714 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1715 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1716 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1720 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1721 if (sig_ret->type != MONO_TYPE_VOID) {
1722 cfg->ret->opcode = OP_REGVAR;
1723 cfg->ret->inst_c0 = ARMREG_R0;
1726 /* local vars are at a positive offset from the stack pointer */
1728 * also note that if the function uses alloca, we use FP
1729 * to point at the local variables.
1731 offset = 0; /* linkage area */
1732 /* align the offset to 16 bytes: not sure this is needed here */
1734 //offset &= ~(8 - 1);
1736 /* add parameter area size for called functions */
1737 offset += cfg->param_area;
1740 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1743 /* allow room to save the return value */
1744 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1747 switch (cinfo->ret.storage) {
1748 case RegTypeStructByVal:
1750 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1751 offset = ALIGN_TO (offset, 8);
1752 cfg->ret->opcode = OP_REGOFFSET;
1753 cfg->ret->inst_basereg = cfg->frame_reg;
1754 cfg->ret->inst_offset = offset;
1755 if (cinfo->ret.storage == RegTypeStructByVal)
1756 offset += cinfo->ret.nregs * sizeof (gpointer);
1760 case RegTypeStructByAddr:
1761 ins = cfg->vret_addr;
1762 offset += sizeof(gpointer) - 1;
1763 offset &= ~(sizeof(gpointer) - 1);
1764 ins->inst_offset = offset;
1765 ins->opcode = OP_REGOFFSET;
1766 ins->inst_basereg = cfg->frame_reg;
1767 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1768 g_print ("vret_addr =");
1769 mono_print_ins (cfg->vret_addr);
1771 offset += sizeof(gpointer);
1777 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1778 if (cfg->arch.seq_point_info_var) {
1781 ins = cfg->arch.seq_point_info_var;
1785 offset += align - 1;
1786 offset &= ~(align - 1);
1787 ins->opcode = OP_REGOFFSET;
1788 ins->inst_basereg = cfg->frame_reg;
1789 ins->inst_offset = offset;
1792 if (cfg->arch.ss_trigger_page_var) {
1795 ins = cfg->arch.ss_trigger_page_var;
1798 offset += align - 1;
1799 offset &= ~(align - 1);
1800 ins->opcode = OP_REGOFFSET;
1801 ins->inst_basereg = cfg->frame_reg;
1802 ins->inst_offset = offset;
1806 if (cfg->arch.seq_point_ss_method_var) {
1809 ins = cfg->arch.seq_point_ss_method_var;
1812 offset += align - 1;
1813 offset &= ~(align - 1);
1814 ins->opcode = OP_REGOFFSET;
1815 ins->inst_basereg = cfg->frame_reg;
1816 ins->inst_offset = offset;
1819 if (cfg->arch.seq_point_bp_method_var) {
1822 ins = cfg->arch.seq_point_bp_method_var;
1825 offset += align - 1;
1826 offset &= ~(align - 1);
1827 ins->opcode = OP_REGOFFSET;
1828 ins->inst_basereg = cfg->frame_reg;
1829 ins->inst_offset = offset;
1833 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1834 /* Allocate a temporary used by the atomic ops */
1838 /* Allocate a local slot to hold the sig cookie address */
1839 offset += align - 1;
1840 offset &= ~(align - 1);
1841 cfg->arch.atomic_tmp_offset = offset;
1844 cfg->arch.atomic_tmp_offset = -1;
1847 cfg->locals_min_stack_offset = offset;
1849 curinst = cfg->locals_start;
1850 for (i = curinst; i < cfg->num_varinfo; ++i) {
1853 ins = cfg->varinfo [i];
1854 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1857 t = ins->inst_vtype;
1858 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1861 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1862 * pinvoke wrappers when they call functions returning structure */
1863 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1864 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1868 size = mono_type_size (t, &align);
1870 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1871 * since it loads/stores misaligned words, which don't do the right thing.
1873 if (align < 4 && size >= 4)
1875 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1876 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1877 offset += align - 1;
1878 offset &= ~(align - 1);
1879 ins->opcode = OP_REGOFFSET;
1880 ins->inst_offset = offset;
1881 ins->inst_basereg = cfg->frame_reg;
1883 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1886 cfg->locals_max_stack_offset = offset;
1890 ins = cfg->args [curinst];
1891 if (ins->opcode != OP_REGVAR) {
1892 ins->opcode = OP_REGOFFSET;
1893 ins->inst_basereg = cfg->frame_reg;
1894 offset += sizeof (gpointer) - 1;
1895 offset &= ~(sizeof (gpointer) - 1);
1896 ins->inst_offset = offset;
1897 offset += sizeof (gpointer);
1902 if (sig->call_convention == MONO_CALL_VARARG) {
1906 /* Allocate a local slot to hold the sig cookie address */
1907 offset += align - 1;
1908 offset &= ~(align - 1);
1909 cfg->sig_cookie = offset;
1913 for (i = 0; i < sig->param_count; ++i) {
1914 ainfo = cinfo->args + i;
1916 ins = cfg->args [curinst];
1918 switch (ainfo->storage) {
1920 offset = ALIGN_TO (offset, 8);
1921 ins->opcode = OP_REGOFFSET;
1922 ins->inst_basereg = cfg->frame_reg;
1923 /* These arguments are saved to the stack in the prolog */
1924 ins->inst_offset = offset;
1925 if (cfg->verbose_level >= 2)
1926 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1934 if (ins->opcode != OP_REGVAR) {
1935 ins->opcode = OP_REGOFFSET;
1936 ins->inst_basereg = cfg->frame_reg;
1937 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1939 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1940 * since it loads/stores misaligned words, which don't do the right thing.
1942 if (align < 4 && size >= 4)
1944 /* The code in the prolog () stores words when storing vtypes received in a register */
1945 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1947 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1948 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1949 offset += align - 1;
1950 offset &= ~(align - 1);
1951 ins->inst_offset = offset;
1957 /* align the offset to 8 bytes */
1958 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1959 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1964 cfg->stack_offset = offset;
1968 mono_arch_create_vars (MonoCompile *cfg)
1970 MonoMethodSignature *sig;
1974 sig = mono_method_signature (cfg->method);
1976 if (!cfg->arch.cinfo)
1977 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1978 cinfo = cfg->arch.cinfo;
1980 if (IS_HARD_FLOAT) {
1981 for (i = 0; i < 2; i++) {
1982 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
1983 inst->flags |= MONO_INST_VOLATILE;
1985 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
1989 if (cinfo->ret.storage == RegTypeStructByVal)
1990 cfg->ret_var_is_local = TRUE;
1992 if (cinfo->ret.storage == RegTypeStructByAddr) {
1993 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1994 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1995 g_print ("vret_addr = ");
1996 mono_print_ins (cfg->vret_addr);
2000 if (cfg->gen_sdb_seq_points) {
2001 if (cfg->compile_aot) {
2002 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2003 ins->flags |= MONO_INST_VOLATILE;
2004 cfg->arch.seq_point_info_var = ins;
2006 if (!cfg->soft_breakpoints) {
2007 /* Allocate a separate variable for this to save 1 load per seq point */
2008 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2009 ins->flags |= MONO_INST_VOLATILE;
2010 cfg->arch.ss_trigger_page_var = ins;
2013 if (cfg->soft_breakpoints) {
2016 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2017 ins->flags |= MONO_INST_VOLATILE;
2018 cfg->arch.seq_point_ss_method_var = ins;
2020 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2021 ins->flags |= MONO_INST_VOLATILE;
2022 cfg->arch.seq_point_bp_method_var = ins;
2028 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2030 MonoMethodSignature *tmp_sig;
2033 if (call->tail_call)
2036 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2039 * mono_ArgIterator_Setup assumes the signature cookie is
2040 * passed first and all the arguments which were before it are
2041 * passed on the stack after the signature. So compensate by
2042 * passing a different signature.
2044 tmp_sig = mono_metadata_signature_dup (call->signature);
2045 tmp_sig->param_count -= call->signature->sentinelpos;
2046 tmp_sig->sentinelpos = 0;
2047 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2049 sig_reg = mono_alloc_ireg (cfg);
2050 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2052 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2057 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2062 LLVMCallInfo *linfo;
2064 n = sig->param_count + sig->hasthis;
2066 cinfo = get_call_info (cfg->mempool, sig);
2068 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2071 * LLVM always uses the native ABI while we use our own ABI, the
2072 * only difference is the handling of vtypes:
2073 * - we only pass/receive them in registers in some cases, and only
2074 * in 1 or 2 integer registers.
2076 switch (cinfo->ret.storage) {
2077 case RegTypeGeneral:
2080 case RegTypeIRegPair:
2082 case RegTypeStructByAddr:
2083 /* Vtype returned using a hidden argument */
2084 linfo->ret.storage = LLVMArgVtypeRetAddr;
2085 linfo->vret_arg_index = cinfo->vret_arg_index;
2088 case RegTypeStructByVal:
2089 /* LLVM models this by returning an int array */
2090 linfo->ret.storage = LLVMArgAsIArgs;
2091 linfo->ret.nslots = cinfo->ret.nregs;
2095 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2096 cfg->disable_llvm = TRUE;
2100 for (i = 0; i < n; ++i) {
2101 LLVMArgInfo *lainfo = &linfo->args [i];
2102 ainfo = cinfo->args + i;
2104 lainfo->storage = LLVMArgNone;
2106 switch (ainfo->storage) {
2107 case RegTypeGeneral:
2108 case RegTypeIRegPair:
2110 case RegTypeBaseGen:
2112 lainfo->storage = LLVMArgNormal;
2114 case RegTypeStructByVal:
2115 lainfo->storage = LLVMArgAsIArgs;
2116 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2118 case RegTypeStructByAddr:
2119 case RegTypeStructByAddrOnStack:
2120 lainfo->storage = LLVMArgVtypeByRef;
2123 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2124 cfg->disable_llvm = TRUE;
2134 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2137 MonoMethodSignature *sig;
2141 sig = call->signature;
2142 n = sig->param_count + sig->hasthis;
2144 cinfo = get_call_info (cfg->mempool, sig);
2146 switch (cinfo->ret.storage) {
2147 case RegTypeStructByVal:
2149 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2150 /* The JIT will transform this into a normal call */
2151 call->vret_in_reg = TRUE;
2154 if (call->inst.opcode == OP_TAILCALL)
2157 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2158 * the location pointed to by it after call in emit_move_return_value ().
2160 if (!cfg->arch.vret_addr_loc) {
2161 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2162 /* Prevent it from being register allocated or optimized away */
2163 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2166 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2168 case RegTypeStructByAddr: {
2170 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2171 vtarg->sreg1 = call->vret_var->dreg;
2172 vtarg->dreg = mono_alloc_preg (cfg);
2173 MONO_ADD_INS (cfg->cbb, vtarg);
2175 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2182 for (i = 0; i < n; ++i) {
2183 ArgInfo *ainfo = cinfo->args + i;
2186 if (i >= sig->hasthis)
2187 t = sig->params [i - sig->hasthis];
2189 t = &mono_defaults.int_class->byval_arg;
2190 t = mini_get_underlying_type (t);
2192 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2193 /* Emit the signature cookie just before the implicit arguments */
2194 emit_sig_cookie (cfg, call, cinfo);
2197 in = call->args [i];
2199 switch (ainfo->storage) {
2200 case RegTypeGeneral:
2201 case RegTypeIRegPair:
2202 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2203 MONO_INST_NEW (cfg, ins, OP_MOVE);
2204 ins->dreg = mono_alloc_ireg (cfg);
2205 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2206 MONO_ADD_INS (cfg->cbb, ins);
2207 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2209 MONO_INST_NEW (cfg, ins, OP_MOVE);
2210 ins->dreg = mono_alloc_ireg (cfg);
2211 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2212 MONO_ADD_INS (cfg->cbb, ins);
2213 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2214 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2215 if (ainfo->size == 4) {
2216 if (IS_SOFT_FLOAT) {
2217 /* mono_emit_call_args () have already done the r8->r4 conversion */
2218 /* The converted value is in an int vreg */
2219 MONO_INST_NEW (cfg, ins, OP_MOVE);
2220 ins->dreg = mono_alloc_ireg (cfg);
2221 ins->sreg1 = in->dreg;
2222 MONO_ADD_INS (cfg->cbb, ins);
2223 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2227 cfg->param_area = MAX (cfg->param_area, 8);
2228 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2229 creg = mono_alloc_ireg (cfg);
2230 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2231 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2234 if (IS_SOFT_FLOAT) {
2235 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2236 ins->dreg = mono_alloc_ireg (cfg);
2237 ins->sreg1 = in->dreg;
2238 MONO_ADD_INS (cfg->cbb, ins);
2239 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2241 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2242 ins->dreg = mono_alloc_ireg (cfg);
2243 ins->sreg1 = in->dreg;
2244 MONO_ADD_INS (cfg->cbb, ins);
2245 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2249 cfg->param_area = MAX (cfg->param_area, 8);
2250 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2251 creg = mono_alloc_ireg (cfg);
2252 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2253 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2254 creg = mono_alloc_ireg (cfg);
2255 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2256 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2259 cfg->flags |= MONO_CFG_HAS_FPOUT;
2261 MONO_INST_NEW (cfg, ins, OP_MOVE);
2262 ins->dreg = mono_alloc_ireg (cfg);
2263 ins->sreg1 = in->dreg;
2264 MONO_ADD_INS (cfg->cbb, ins);
2266 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2269 case RegTypeStructByVal:
2270 case RegTypeGSharedVtInReg:
2271 case RegTypeGSharedVtOnStack:
2273 case RegTypeStructByAddr:
2274 case RegTypeStructByAddrOnStack:
2275 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2276 ins->opcode = OP_OUTARG_VT;
2277 ins->sreg1 = in->dreg;
2278 ins->klass = in->klass;
2279 ins->inst_p0 = call;
2280 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2281 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2282 mono_call_inst_add_outarg_vt (cfg, call, ins);
2283 MONO_ADD_INS (cfg->cbb, ins);
2286 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2287 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2288 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2289 if (t->type == MONO_TYPE_R8) {
2290 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2293 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2295 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2298 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2301 case RegTypeBaseGen:
2302 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2303 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2304 MONO_INST_NEW (cfg, ins, OP_MOVE);
2305 ins->dreg = mono_alloc_ireg (cfg);
2306 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2307 MONO_ADD_INS (cfg->cbb, ins);
2308 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2309 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2312 /* This should work for soft-float as well */
2314 cfg->param_area = MAX (cfg->param_area, 8);
2315 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2316 creg = mono_alloc_ireg (cfg);
2317 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2318 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2319 creg = mono_alloc_ireg (cfg);
2320 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2321 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2322 cfg->flags |= MONO_CFG_HAS_FPOUT;
2324 g_assert_not_reached ();
2328 int fdreg = mono_alloc_freg (cfg);
2330 if (ainfo->size == 8) {
2331 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2332 ins->sreg1 = in->dreg;
2334 MONO_ADD_INS (cfg->cbb, ins);
2336 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2341 * Mono's register allocator doesn't speak single-precision registers that
2342 * overlap double-precision registers (i.e. armhf). So we have to work around
2343 * the register allocator and load the value from memory manually.
2345 * So we create a variable for the float argument and an instruction to store
2346 * the argument into the variable. We then store the list of these arguments
2347 * in call->float_args. This list is then used by emit_float_args later to
2348 * pass the arguments in the various call opcodes.
2350 * This is not very nice, and we should really try to fix the allocator.
2353 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2355 /* Make sure the instruction isn't seen as pointless and removed.
2357 float_arg->flags |= MONO_INST_VOLATILE;
2359 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2361 /* We use the dreg to look up the instruction later. The hreg is used to
2362 * emit the instruction that loads the value into the FP reg.
2364 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2365 fad->vreg = float_arg->dreg;
2366 fad->hreg = ainfo->reg;
2368 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2371 call->used_iregs |= 1 << ainfo->reg;
2372 cfg->flags |= MONO_CFG_HAS_FPOUT;
2376 g_assert_not_reached ();
2380 /* Handle the case where there are no implicit arguments */
2381 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2382 emit_sig_cookie (cfg, call, cinfo);
2384 call->call_info = cinfo;
2385 call->stack_usage = cinfo->stack_usage;
2389 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2395 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2396 ins->dreg = mono_alloc_freg (cfg);
2397 ins->sreg1 = arg->dreg;
2398 MONO_ADD_INS (cfg->cbb, ins);
2399 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2402 g_assert_not_reached ();
2408 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2410 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2412 ArgInfo *ainfo = ins->inst_p1;
2413 int ovf_size = ainfo->vtsize;
2414 int doffset = ainfo->offset;
2415 int struct_size = ainfo->struct_size;
2416 int i, soffset, dreg, tmpreg;
2418 switch (ainfo->storage) {
2419 case RegTypeGSharedVtInReg:
2420 case RegTypeStructByAddr:
2422 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2424 case RegTypeGSharedVtOnStack:
2425 case RegTypeStructByAddrOnStack:
2426 /* Pass by addr on stack */
2427 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2430 for (i = 0; i < ainfo->nregs; ++i) {
2431 if (ainfo->esize == 4)
2432 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2434 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2435 load->dreg = mono_alloc_freg (cfg);
2436 load->inst_basereg = src->dreg;
2437 load->inst_offset = i * ainfo->esize;
2438 MONO_ADD_INS (cfg->cbb, load);
2440 if (ainfo->esize == 4) {
2443 /* See RegTypeFP in mono_arch_emit_call () */
2444 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2445 float_arg->flags |= MONO_INST_VOLATILE;
2446 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2448 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2449 fad->vreg = float_arg->dreg;
2450 fad->hreg = ainfo->reg + i;
2452 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2454 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2460 for (i = 0; i < ainfo->size; ++i) {
2461 dreg = mono_alloc_ireg (cfg);
2462 switch (struct_size) {
2464 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2467 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2470 tmpreg = mono_alloc_ireg (cfg);
2471 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2472 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2473 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2474 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2475 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2476 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2477 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2480 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2483 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2484 soffset += sizeof (gpointer);
2485 struct_size -= sizeof (gpointer);
2487 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2489 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2495 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2497 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2500 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2503 if (COMPILE_LLVM (cfg)) {
2504 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2506 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2507 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2508 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2509 MONO_ADD_INS (cfg->cbb, ins);
2514 case MONO_ARM_FPU_NONE:
2515 if (ret->type == MONO_TYPE_R8) {
2518 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2519 ins->dreg = cfg->ret->dreg;
2520 ins->sreg1 = val->dreg;
2521 MONO_ADD_INS (cfg->cbb, ins);
2524 if (ret->type == MONO_TYPE_R4) {
2525 /* Already converted to an int in method_to_ir () */
2526 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2530 case MONO_ARM_FPU_VFP:
2531 case MONO_ARM_FPU_VFP_HARD:
2532 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2535 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2536 ins->dreg = cfg->ret->dreg;
2537 ins->sreg1 = val->dreg;
2538 MONO_ADD_INS (cfg->cbb, ins);
2543 g_assert_not_reached ();
2547 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2550 #endif /* #ifndef DISABLE_JIT */
2553 mono_arch_is_inst_imm (gint64 imm)
2559 MonoMethodSignature *sig;
2562 MonoType **param_types;
2566 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2570 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2573 switch (cinfo->ret.storage) {
2575 case RegTypeGeneral:
2576 case RegTypeIRegPair:
2577 case RegTypeStructByAddr:
2588 for (i = 0; i < cinfo->nargs; ++i) {
2589 ArgInfo *ainfo = &cinfo->args [i];
2592 switch (ainfo->storage) {
2593 case RegTypeGeneral:
2594 case RegTypeIRegPair:
2595 case RegTypeBaseGen:
2599 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2602 case RegTypeStructByVal:
2603 if (ainfo->size == 0)
2604 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2606 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2607 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2615 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2616 for (i = 0; i < sig->param_count; ++i) {
2617 MonoType *t = sig->params [i];
2622 t = mini_get_underlying_type (t);
2645 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2647 ArchDynCallInfo *info;
2651 cinfo = get_call_info (NULL, sig);
2653 if (!dyn_call_supported (cinfo, sig)) {
2658 info = g_new0 (ArchDynCallInfo, 1);
2659 // FIXME: Preprocess the info to speed up start_dyn_call ()
2661 info->cinfo = cinfo;
2662 info->rtype = mini_get_underlying_type (sig->ret);
2663 info->param_types = g_new0 (MonoType*, sig->param_count);
2664 for (i = 0; i < sig->param_count; ++i)
2665 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2667 return (MonoDynCallInfo*)info;
2671 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2673 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2675 g_free (ainfo->cinfo);
2680 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2682 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2683 DynCallArgs *p = (DynCallArgs*)buf;
2684 int arg_index, greg, i, j, pindex;
2685 MonoMethodSignature *sig = dinfo->sig;
2687 g_assert (buf_len >= sizeof (DynCallArgs));
2697 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2698 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2703 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2704 p->regs [greg ++] = (mgreg_t)ret;
2706 for (i = pindex; i < sig->param_count; i++) {
2707 MonoType *t = dinfo->param_types [i];
2708 gpointer *arg = args [arg_index ++];
2709 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2712 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2714 } else if (ainfo->storage == RegTypeFP) {
2715 } else if (ainfo->storage == RegTypeBase) {
2716 slot = PARAM_REGS + (ainfo->offset / 4);
2717 } else if (ainfo->storage == RegTypeBaseGen) {
2718 /* slot + 1 is the first stack slot, so the code below will work */
2721 g_assert_not_reached ();
2725 p->regs [slot] = (mgreg_t)*arg;
2730 case MONO_TYPE_STRING:
2731 case MONO_TYPE_CLASS:
2732 case MONO_TYPE_ARRAY:
2733 case MONO_TYPE_SZARRAY:
2734 case MONO_TYPE_OBJECT:
2738 p->regs [slot] = (mgreg_t)*arg;
2741 p->regs [slot] = *(guint8*)arg;
2744 p->regs [slot] = *(gint8*)arg;
2747 p->regs [slot] = *(gint16*)arg;
2750 p->regs [slot] = *(guint16*)arg;
2753 p->regs [slot] = *(gint32*)arg;
2756 p->regs [slot] = *(guint32*)arg;
2760 p->regs [slot ++] = (mgreg_t)arg [0];
2761 p->regs [slot] = (mgreg_t)arg [1];
2764 if (ainfo->storage == RegTypeFP) {
2765 float f = *(float*)arg;
2766 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2769 p->regs [slot] = *(mgreg_t*)arg;
2773 if (ainfo->storage == RegTypeFP) {
2774 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2777 p->regs [slot ++] = (mgreg_t)arg [0];
2778 p->regs [slot] = (mgreg_t)arg [1];
2781 case MONO_TYPE_GENERICINST:
2782 if (MONO_TYPE_IS_REFERENCE (t)) {
2783 p->regs [slot] = (mgreg_t)*arg;
2786 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2787 MonoClass *klass = mono_class_from_mono_type (t);
2788 guint8 *nullable_buf;
2791 size = mono_class_value_size (klass, NULL);
2792 nullable_buf = g_alloca (size);
2793 g_assert (nullable_buf);
2795 /* The argument pointed to by arg is either a boxed vtype or null */
2796 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2798 arg = (gpointer*)nullable_buf;
2804 case MONO_TYPE_VALUETYPE:
2805 g_assert (ainfo->storage == RegTypeStructByVal);
2807 if (ainfo->size == 0)
2808 slot = PARAM_REGS + (ainfo->offset / 4);
2812 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2813 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2816 g_assert_not_reached ();
2822 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2824 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2825 DynCallArgs *p = (DynCallArgs*)buf;
2826 MonoType *ptype = ainfo->rtype;
2827 guint8 *ret = p->ret;
2828 mgreg_t res = p->res;
2829 mgreg_t res2 = p->res2;
2831 switch (ptype->type) {
2832 case MONO_TYPE_VOID:
2833 *(gpointer*)ret = NULL;
2835 case MONO_TYPE_STRING:
2836 case MONO_TYPE_CLASS:
2837 case MONO_TYPE_ARRAY:
2838 case MONO_TYPE_SZARRAY:
2839 case MONO_TYPE_OBJECT:
2843 *(gpointer*)ret = (gpointer)res;
2849 *(guint8*)ret = res;
2852 *(gint16*)ret = res;
2855 *(guint16*)ret = res;
2858 *(gint32*)ret = res;
2861 *(guint32*)ret = res;
2865 /* This handles endianness as well */
2866 ((gint32*)ret) [0] = res;
2867 ((gint32*)ret) [1] = res2;
2869 case MONO_TYPE_GENERICINST:
2870 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2871 *(gpointer*)ret = (gpointer)res;
2876 case MONO_TYPE_VALUETYPE:
2877 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2883 *(float*)ret = *(float*)&p->fpregs [0];
2885 *(float*)ret = *(float*)&res;
2887 case MONO_TYPE_R8: {
2891 if (IS_HARD_FLOAT) {
2892 *(double*)ret = p->fpregs [0];
2897 *(double*)ret = *(double*)®s;
2902 g_assert_not_reached ();
2909 * Allow tracing to work with this interface (with an optional argument)
2913 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2917 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2918 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2919 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2920 code = emit_call_reg (code, ARMREG_R2);
2934 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2937 int save_mode = SAVE_NONE;
2939 MonoMethod *method = cfg->method;
2940 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
2941 int rtype = ret_type->type;
2942 int save_offset = cfg->param_area;
2946 offset = code - cfg->native_code;
2947 /* we need about 16 instructions */
2948 if (offset > (cfg->code_size - 16 * 4)) {
2949 cfg->code_size *= 2;
2950 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2951 code = cfg->native_code + offset;
2954 case MONO_TYPE_VOID:
2955 /* special case string .ctor icall */
2956 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2957 save_mode = SAVE_ONE;
2959 save_mode = SAVE_NONE;
2963 save_mode = SAVE_TWO;
2967 save_mode = SAVE_ONE_FP;
2969 save_mode = SAVE_ONE;
2973 save_mode = SAVE_TWO_FP;
2975 save_mode = SAVE_TWO;
2977 case MONO_TYPE_GENERICINST:
2978 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
2979 save_mode = SAVE_ONE;
2983 case MONO_TYPE_VALUETYPE:
2984 save_mode = SAVE_STRUCT;
2987 save_mode = SAVE_ONE;
2991 switch (save_mode) {
2993 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2994 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2995 if (enable_arguments) {
2996 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2997 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3001 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3002 if (enable_arguments) {
3003 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3007 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3008 if (enable_arguments) {
3009 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3013 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3014 if (enable_arguments) {
3015 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3019 if (enable_arguments) {
3020 /* FIXME: get the actual address */
3021 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3029 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3030 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3031 code = emit_call_reg (code, ARMREG_IP);
3033 switch (save_mode) {
3035 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3036 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3039 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3042 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3045 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3056 * The immediate field for cond branches is big enough for all reasonable methods
3058 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3059 if (0 && ins->inst_true_bb->native_offset) { \
3060 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3062 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3063 ARM_B_COND (code, (condcode), 0); \
3066 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3068 /* emit an exception if condition is fail
3070 * We assign the extra code used to throw the implicit exceptions
3071 * to cfg->bb_exit as far as the big branch handling is concerned
3073 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3075 mono_add_patch_info (cfg, code - cfg->native_code, \
3076 MONO_PATCH_INFO_EXC, exc_name); \
3077 ARM_BL_COND (code, (condcode), 0); \
3080 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3083 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3088 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3092 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3093 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3095 switch (ins->opcode) {
3098 /* Already done by an arch-independent pass */
3100 case OP_LOAD_MEMBASE:
3101 case OP_LOADI4_MEMBASE:
3103 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3104 * OP_LOAD_MEMBASE offset(basereg), reg
3106 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3107 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3108 ins->inst_basereg == last_ins->inst_destbasereg &&
3109 ins->inst_offset == last_ins->inst_offset) {
3110 if (ins->dreg == last_ins->sreg1) {
3111 MONO_DELETE_INS (bb, ins);
3114 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3115 ins->opcode = OP_MOVE;
3116 ins->sreg1 = last_ins->sreg1;
3120 * Note: reg1 must be different from the basereg in the second load
3121 * OP_LOAD_MEMBASE offset(basereg), reg1
3122 * OP_LOAD_MEMBASE offset(basereg), reg2
3124 * OP_LOAD_MEMBASE offset(basereg), reg1
3125 * OP_MOVE reg1, reg2
3127 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3128 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3129 ins->inst_basereg != last_ins->dreg &&
3130 ins->inst_basereg == last_ins->inst_basereg &&
3131 ins->inst_offset == last_ins->inst_offset) {
3133 if (ins->dreg == last_ins->dreg) {
3134 MONO_DELETE_INS (bb, ins);
3137 ins->opcode = OP_MOVE;
3138 ins->sreg1 = last_ins->dreg;
3141 //g_assert_not_reached ();
3145 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3146 * OP_LOAD_MEMBASE offset(basereg), reg
3148 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3149 * OP_ICONST reg, imm
3151 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3152 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3153 ins->inst_basereg == last_ins->inst_destbasereg &&
3154 ins->inst_offset == last_ins->inst_offset) {
3155 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3156 ins->opcode = OP_ICONST;
3157 ins->inst_c0 = last_ins->inst_imm;
3158 g_assert_not_reached (); // check this rule
3162 case OP_LOADU1_MEMBASE:
3163 case OP_LOADI1_MEMBASE:
3164 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3165 ins->inst_basereg == last_ins->inst_destbasereg &&
3166 ins->inst_offset == last_ins->inst_offset) {
3167 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3168 ins->sreg1 = last_ins->sreg1;
3171 case OP_LOADU2_MEMBASE:
3172 case OP_LOADI2_MEMBASE:
3173 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3174 ins->inst_basereg == last_ins->inst_destbasereg &&
3175 ins->inst_offset == last_ins->inst_offset) {
3176 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3177 ins->sreg1 = last_ins->sreg1;
3181 ins->opcode = OP_MOVE;
3185 if (ins->dreg == ins->sreg1) {
3186 MONO_DELETE_INS (bb, ins);
3190 * OP_MOVE sreg, dreg
3191 * OP_MOVE dreg, sreg
3193 if (last_ins && last_ins->opcode == OP_MOVE &&
3194 ins->sreg1 == last_ins->dreg &&
3195 ins->dreg == last_ins->sreg1) {
3196 MONO_DELETE_INS (bb, ins);
3205 * the branch_cc_table should maintain the order of these
3219 branch_cc_table [] = {
3233 #define ADD_NEW_INS(cfg,dest,op) do { \
3234 MONO_INST_NEW ((cfg), (dest), (op)); \
3235 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3239 map_to_reg_reg_op (int op)
3248 case OP_COMPARE_IMM:
3250 case OP_ICOMPARE_IMM:
3264 case OP_LOAD_MEMBASE:
3265 return OP_LOAD_MEMINDEX;
3266 case OP_LOADI4_MEMBASE:
3267 return OP_LOADI4_MEMINDEX;
3268 case OP_LOADU4_MEMBASE:
3269 return OP_LOADU4_MEMINDEX;
3270 case OP_LOADU1_MEMBASE:
3271 return OP_LOADU1_MEMINDEX;
3272 case OP_LOADI2_MEMBASE:
3273 return OP_LOADI2_MEMINDEX;
3274 case OP_LOADU2_MEMBASE:
3275 return OP_LOADU2_MEMINDEX;
3276 case OP_LOADI1_MEMBASE:
3277 return OP_LOADI1_MEMINDEX;
3278 case OP_STOREI1_MEMBASE_REG:
3279 return OP_STOREI1_MEMINDEX;
3280 case OP_STOREI2_MEMBASE_REG:
3281 return OP_STOREI2_MEMINDEX;
3282 case OP_STOREI4_MEMBASE_REG:
3283 return OP_STOREI4_MEMINDEX;
3284 case OP_STORE_MEMBASE_REG:
3285 return OP_STORE_MEMINDEX;
3286 case OP_STORER4_MEMBASE_REG:
3287 return OP_STORER4_MEMINDEX;
3288 case OP_STORER8_MEMBASE_REG:
3289 return OP_STORER8_MEMINDEX;
3290 case OP_STORE_MEMBASE_IMM:
3291 return OP_STORE_MEMBASE_REG;
3292 case OP_STOREI1_MEMBASE_IMM:
3293 return OP_STOREI1_MEMBASE_REG;
3294 case OP_STOREI2_MEMBASE_IMM:
3295 return OP_STOREI2_MEMBASE_REG;
3296 case OP_STOREI4_MEMBASE_IMM:
3297 return OP_STOREI4_MEMBASE_REG;
3299 g_assert_not_reached ();
3303 * Remove from the instruction list the instructions that can't be
3304 * represented with very simple instructions with no register
3308 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3310 MonoInst *ins, *temp, *last_ins = NULL;
3311 int rot_amount, imm8, low_imm;
3313 MONO_BB_FOR_EACH_INS (bb, ins) {
3315 switch (ins->opcode) {
3319 case OP_COMPARE_IMM:
3320 case OP_ICOMPARE_IMM:
3334 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3335 int opcode2 = mono_op_imm_to_op (ins->opcode);
3336 ADD_NEW_INS (cfg, temp, OP_ICONST);
3337 temp->inst_c0 = ins->inst_imm;
3338 temp->dreg = mono_alloc_ireg (cfg);
3339 ins->sreg2 = temp->dreg;
3341 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3342 ins->opcode = opcode2;
3344 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3350 if (ins->inst_imm == 1) {
3351 ins->opcode = OP_MOVE;
3354 if (ins->inst_imm == 0) {
3355 ins->opcode = OP_ICONST;
3359 imm8 = mono_is_power_of_two (ins->inst_imm);
3361 ins->opcode = OP_SHL_IMM;
3362 ins->inst_imm = imm8;
3365 ADD_NEW_INS (cfg, temp, OP_ICONST);
3366 temp->inst_c0 = ins->inst_imm;
3367 temp->dreg = mono_alloc_ireg (cfg);
3368 ins->sreg2 = temp->dreg;
3369 ins->opcode = OP_IMUL;
3375 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3376 /* ARM sets the C flag to 1 if there was _no_ overflow */
3377 ins->next->opcode = OP_COND_EXC_NC;
3380 case OP_IDIV_UN_IMM:
3382 case OP_IREM_UN_IMM: {
3383 int opcode2 = mono_op_imm_to_op (ins->opcode);
3384 ADD_NEW_INS (cfg, temp, OP_ICONST);
3385 temp->inst_c0 = ins->inst_imm;
3386 temp->dreg = mono_alloc_ireg (cfg);
3387 ins->sreg2 = temp->dreg;
3389 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3390 ins->opcode = opcode2;
3393 case OP_LOCALLOC_IMM:
3394 ADD_NEW_INS (cfg, temp, OP_ICONST);
3395 temp->inst_c0 = ins->inst_imm;
3396 temp->dreg = mono_alloc_ireg (cfg);
3397 ins->sreg1 = temp->dreg;
3398 ins->opcode = OP_LOCALLOC;
3400 case OP_LOAD_MEMBASE:
3401 case OP_LOADI4_MEMBASE:
3402 case OP_LOADU4_MEMBASE:
3403 case OP_LOADU1_MEMBASE:
3404 /* we can do two things: load the immed in a register
3405 * and use an indexed load, or see if the immed can be
3406 * represented as an ad_imm + a load with a smaller offset
3407 * that fits. We just do the first for now, optimize later.
3409 if (arm_is_imm12 (ins->inst_offset))
3411 ADD_NEW_INS (cfg, temp, OP_ICONST);
3412 temp->inst_c0 = ins->inst_offset;
3413 temp->dreg = mono_alloc_ireg (cfg);
3414 ins->sreg2 = temp->dreg;
3415 ins->opcode = map_to_reg_reg_op (ins->opcode);
3417 case OP_LOADI2_MEMBASE:
3418 case OP_LOADU2_MEMBASE:
3419 case OP_LOADI1_MEMBASE:
3420 if (arm_is_imm8 (ins->inst_offset))
3422 ADD_NEW_INS (cfg, temp, OP_ICONST);
3423 temp->inst_c0 = ins->inst_offset;
3424 temp->dreg = mono_alloc_ireg (cfg);
3425 ins->sreg2 = temp->dreg;
3426 ins->opcode = map_to_reg_reg_op (ins->opcode);
3428 case OP_LOADR4_MEMBASE:
3429 case OP_LOADR8_MEMBASE:
3430 if (arm_is_fpimm8 (ins->inst_offset))
3432 low_imm = ins->inst_offset & 0x1ff;
3433 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3434 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3435 temp->inst_imm = ins->inst_offset & ~0x1ff;
3436 temp->sreg1 = ins->inst_basereg;
3437 temp->dreg = mono_alloc_ireg (cfg);
3438 ins->inst_basereg = temp->dreg;
3439 ins->inst_offset = low_imm;
3443 ADD_NEW_INS (cfg, temp, OP_ICONST);
3444 temp->inst_c0 = ins->inst_offset;
3445 temp->dreg = mono_alloc_ireg (cfg);
3447 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3448 add_ins->sreg1 = ins->inst_basereg;
3449 add_ins->sreg2 = temp->dreg;
3450 add_ins->dreg = mono_alloc_ireg (cfg);
3452 ins->inst_basereg = add_ins->dreg;
3453 ins->inst_offset = 0;
3456 case OP_STORE_MEMBASE_REG:
3457 case OP_STOREI4_MEMBASE_REG:
3458 case OP_STOREI1_MEMBASE_REG:
3459 if (arm_is_imm12 (ins->inst_offset))
3461 ADD_NEW_INS (cfg, temp, OP_ICONST);
3462 temp->inst_c0 = ins->inst_offset;
3463 temp->dreg = mono_alloc_ireg (cfg);
3464 ins->sreg2 = temp->dreg;
3465 ins->opcode = map_to_reg_reg_op (ins->opcode);
3467 case OP_STOREI2_MEMBASE_REG:
3468 if (arm_is_imm8 (ins->inst_offset))
3470 ADD_NEW_INS (cfg, temp, OP_ICONST);
3471 temp->inst_c0 = ins->inst_offset;
3472 temp->dreg = mono_alloc_ireg (cfg);
3473 ins->sreg2 = temp->dreg;
3474 ins->opcode = map_to_reg_reg_op (ins->opcode);
3476 case OP_STORER4_MEMBASE_REG:
3477 case OP_STORER8_MEMBASE_REG:
3478 if (arm_is_fpimm8 (ins->inst_offset))
3480 low_imm = ins->inst_offset & 0x1ff;
3481 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3482 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3483 temp->inst_imm = ins->inst_offset & ~0x1ff;
3484 temp->sreg1 = ins->inst_destbasereg;
3485 temp->dreg = mono_alloc_ireg (cfg);
3486 ins->inst_destbasereg = temp->dreg;
3487 ins->inst_offset = low_imm;
3491 ADD_NEW_INS (cfg, temp, OP_ICONST);
3492 temp->inst_c0 = ins->inst_offset;
3493 temp->dreg = mono_alloc_ireg (cfg);
3495 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3496 add_ins->sreg1 = ins->inst_destbasereg;
3497 add_ins->sreg2 = temp->dreg;
3498 add_ins->dreg = mono_alloc_ireg (cfg);
3500 ins->inst_destbasereg = add_ins->dreg;
3501 ins->inst_offset = 0;
3504 case OP_STORE_MEMBASE_IMM:
3505 case OP_STOREI1_MEMBASE_IMM:
3506 case OP_STOREI2_MEMBASE_IMM:
3507 case OP_STOREI4_MEMBASE_IMM:
3508 ADD_NEW_INS (cfg, temp, OP_ICONST);
3509 temp->inst_c0 = ins->inst_imm;
3510 temp->dreg = mono_alloc_ireg (cfg);
3511 ins->sreg1 = temp->dreg;
3512 ins->opcode = map_to_reg_reg_op (ins->opcode);
3514 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3517 gboolean swap = FALSE;
3521 /* Optimized away */
3526 /* Some fp compares require swapped operands */
3527 switch (ins->next->opcode) {
3529 ins->next->opcode = OP_FBLT;
3533 ins->next->opcode = OP_FBLT_UN;
3537 ins->next->opcode = OP_FBGE;
3541 ins->next->opcode = OP_FBGE_UN;
3549 ins->sreg1 = ins->sreg2;
3558 bb->last_ins = last_ins;
3559 bb->max_vreg = cfg->next_vreg;
3563 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3567 if (long_ins->opcode == OP_LNEG) {
3569 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3570 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3576 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3578 /* sreg is a float, dreg is an integer reg */
3580 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3582 ARM_TOSIZD (code, vfp_scratch1, sreg);
3584 ARM_TOUIZD (code, vfp_scratch1, sreg);
3585 ARM_FMRS (code, dreg, vfp_scratch1);
3586 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3590 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3591 else if (size == 2) {
3592 ARM_SHL_IMM (code, dreg, dreg, 16);
3593 ARM_SHR_IMM (code, dreg, dreg, 16);
3597 ARM_SHL_IMM (code, dreg, dreg, 24);
3598 ARM_SAR_IMM (code, dreg, dreg, 24);
3599 } else if (size == 2) {
3600 ARM_SHL_IMM (code, dreg, dreg, 16);
3601 ARM_SAR_IMM (code, dreg, dreg, 16);
3608 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3610 /* sreg is a float, dreg is an integer reg */
3612 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3614 ARM_TOSIZS (code, vfp_scratch1, sreg);
3616 ARM_TOUIZS (code, vfp_scratch1, sreg);
3617 ARM_FMRS (code, dreg, vfp_scratch1);
3618 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3622 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3623 else if (size == 2) {
3624 ARM_SHL_IMM (code, dreg, dreg, 16);
3625 ARM_SHR_IMM (code, dreg, dreg, 16);
3629 ARM_SHL_IMM (code, dreg, dreg, 24);
3630 ARM_SAR_IMM (code, dreg, dreg, 24);
3631 } else if (size == 2) {
3632 ARM_SHL_IMM (code, dreg, dreg, 16);
3633 ARM_SAR_IMM (code, dreg, dreg, 16);
3639 #endif /* #ifndef DISABLE_JIT */
3641 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3644 emit_thunk (guint8 *code, gconstpointer target)
3648 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3649 if (thumb_supported)
3650 ARM_BX (code, ARMREG_IP);
3652 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3653 *(guint32*)code = (guint32)target;
3655 mono_arch_flush_icache (p, code - p);
3659 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3661 MonoJitInfo *ji = NULL;
3662 MonoThunkJitInfo *info;
3665 guint8 *orig_target;
3666 guint8 *target_thunk;
3669 domain = mono_domain_get ();
3673 * This can be called multiple times during JITting,
3674 * save the current position in cfg->arch to avoid
3675 * doing a O(n^2) search.
3677 if (!cfg->arch.thunks) {
3678 cfg->arch.thunks = cfg->thunks;
3679 cfg->arch.thunks_size = cfg->thunk_area;
3681 thunks = cfg->arch.thunks;
3682 thunks_size = cfg->arch.thunks_size;
3684 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3685 g_assert_not_reached ();
3688 g_assert (*(guint32*)thunks == 0);
3689 emit_thunk (thunks, target);
3690 arm_patch (code, thunks);
3692 cfg->arch.thunks += THUNK_SIZE;
3693 cfg->arch.thunks_size -= THUNK_SIZE;
3695 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3697 info = mono_jit_info_get_thunk_info (ji);
3700 thunks = (guint8*)ji->code_start + info->thunks_offset;
3701 thunks_size = info->thunks_size;
3703 orig_target = mono_arch_get_call_target (code + 4);
3705 mono_mini_arch_lock ();
3707 target_thunk = NULL;
3708 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3709 /* The call already points to a thunk, because of trampolines etc. */
3710 target_thunk = orig_target;
3712 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3713 if (((guint32*)p) [0] == 0) {
3717 } else if (((guint32*)p) [2] == (guint32)target) {
3718 /* Thunk already points to target */
3725 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3727 if (!target_thunk) {
3728 mono_mini_arch_unlock ();
3729 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3730 g_assert_not_reached ();
3733 emit_thunk (target_thunk, target);
3734 arm_patch (code, target_thunk);
3735 mono_arch_flush_icache (code, 4);
3737 mono_mini_arch_unlock ();
3742 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3744 guint32 *code32 = (void*)code;
3745 guint32 ins = *code32;
3746 guint32 prim = (ins >> 25) & 7;
3747 guint32 tval = GPOINTER_TO_UINT (target);
3749 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3750 if (prim == 5) { /* 101b */
3751 /* the diff starts 8 bytes from the branch opcode */
3752 gint diff = target - code - 8;
3754 gint tmask = 0xffffffff;
3755 if (tval & 1) { /* entering thumb mode */
3756 diff = target - 1 - code - 8;
3757 g_assert (thumb_supported);
3758 tbits = 0xf << 28; /* bl->blx bit pattern */
3759 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3760 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3764 tmask = ~(1 << 24); /* clear the link bit */
3765 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3770 if (diff <= 33554431) {
3772 ins = (ins & 0xff000000) | diff;
3774 *code32 = ins | tbits;
3778 /* diff between 0 and -33554432 */
3779 if (diff >= -33554432) {
3781 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3783 *code32 = ins | tbits;
3788 handle_thunk (cfg, domain, code, target);
3793 * The alternative call sequences looks like this:
3795 * ldr ip, [pc] // loads the address constant
3796 * b 1f // jumps around the constant
3797 * address constant embedded in the code
3802 * There are two cases for patching:
3803 * a) at the end of method emission: in this case code points to the start
3804 * of the call sequence
3805 * b) during runtime patching of the call site: in this case code points
3806 * to the mov pc, ip instruction
3808 * We have to handle also the thunk jump code sequence:
3812 * address constant // execution never reaches here
3814 if ((ins & 0x0ffffff0) == 0x12fff10) {
3815 /* Branch and exchange: the address is constructed in a reg
3816 * We can patch BX when the code sequence is the following:
3817 * ldr ip, [pc, #0] ; 0x8
3824 guint8 *emit = (guint8*)ccode;
3825 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3827 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3828 ARM_BX (emit, ARMREG_IP);
3830 /*patching from magic trampoline*/
3831 if (ins == ccode [3]) {
3832 g_assert (code32 [-4] == ccode [0]);
3833 g_assert (code32 [-3] == ccode [1]);
3834 g_assert (code32 [-1] == ccode [2]);
3835 code32 [-2] = (guint32)target;
3838 /*patching from JIT*/
3839 if (ins == ccode [0]) {
3840 g_assert (code32 [1] == ccode [1]);
3841 g_assert (code32 [3] == ccode [2]);
3842 g_assert (code32 [4] == ccode [3]);
3843 code32 [2] = (guint32)target;
3846 g_assert_not_reached ();
3847 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3855 guint8 *emit = (guint8*)ccode;
3856 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3858 ARM_BLX_REG (emit, ARMREG_IP);
3860 g_assert (code32 [-3] == ccode [0]);
3861 g_assert (code32 [-2] == ccode [1]);
3862 g_assert (code32 [0] == ccode [2]);
3864 code32 [-1] = (guint32)target;
3867 guint32 *tmp = ccode;
3868 guint8 *emit = (guint8*)tmp;
3869 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3870 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3871 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3872 ARM_BX (emit, ARMREG_IP);
3873 if (ins == ccode [2]) {
3874 g_assert_not_reached (); // should be -2 ...
3875 code32 [-1] = (guint32)target;
3878 if (ins == ccode [0]) {
3879 /* handles both thunk jump code and the far call sequence */
3880 code32 [2] = (guint32)target;
3883 g_assert_not_reached ();
3885 // g_print ("patched with 0x%08x\n", ins);
3889 arm_patch (guchar *code, const guchar *target)
3891 arm_patch_general (NULL, NULL, code, target);
3895 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3896 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3897 * to be used with the emit macros.
3898 * Return -1 otherwise.
3901 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3904 for (i = 0; i < 31; i+= 2) {
3905 res = (val << (32 - i)) | (val >> i);
3908 *rot_amount = i? 32 - i: 0;
3915 * Emits in code a sequence of instructions that load the value 'val'
3916 * into the dreg register. Uses at most 4 instructions.
3919 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3921 int imm8, rot_amount;
3923 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3924 /* skip the constant pool */
3930 if (mini_get_debug_options()->single_imm_size && v7_supported) {
3931 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3932 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3936 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3937 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3938 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3939 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3942 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3944 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3948 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3950 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3952 if (val & 0xFF0000) {
3953 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3955 if (val & 0xFF000000) {
3956 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3958 } else if (val & 0xFF00) {
3959 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3960 if (val & 0xFF0000) {
3961 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3963 if (val & 0xFF000000) {
3964 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3966 } else if (val & 0xFF0000) {
3967 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3968 if (val & 0xFF000000) {
3969 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3972 //g_assert_not_reached ();
3978 mono_arm_thumb_supported (void)
3980 return thumb_supported;
3986 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3991 call = (MonoCallInst*)ins;
3992 cinfo = call->call_info;
3994 switch (cinfo->ret.storage) {
3995 case RegTypeStructByVal:
3997 MonoInst *loc = cfg->arch.vret_addr_loc;
4000 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4001 /* The JIT treats this as a normal call */
4005 /* Load the destination address */
4006 g_assert (loc && loc->opcode == OP_REGOFFSET);
4008 if (arm_is_imm12 (loc->inst_offset)) {
4009 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4011 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4012 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4015 if (cinfo->ret.storage == RegTypeStructByVal) {
4016 int rsize = cinfo->ret.struct_size;
4018 for (i = 0; i < cinfo->ret.nregs; ++i) {
4019 g_assert (rsize >= 0);
4024 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4027 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4030 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4036 for (i = 0; i < cinfo->ret.nregs; ++i) {
4037 if (cinfo->ret.esize == 4)
4038 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4040 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4049 switch (ins->opcode) {
4052 case OP_FCALL_MEMBASE:
4054 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4055 if (sig_ret->type == MONO_TYPE_R4) {
4056 if (IS_HARD_FLOAT) {
4057 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4059 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4060 ARM_CVTS (code, ins->dreg, ins->dreg);
4063 if (IS_HARD_FLOAT) {
4064 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4066 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4073 case OP_RCALL_MEMBASE: {
4078 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4079 g_assert (sig_ret->type == MONO_TYPE_R4);
4080 if (IS_HARD_FLOAT) {
4081 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4083 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4084 ARM_CPYS (code, ins->dreg, ins->dreg);
4096 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4101 guint8 *code = cfg->native_code + cfg->code_len;
4102 MonoInst *last_ins = NULL;
4103 guint last_offset = 0;
4105 int imm8, rot_amount;
4107 /* we don't align basic blocks of loops on arm */
4109 if (cfg->verbose_level > 2)
4110 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4112 cpos = bb->max_offset;
4114 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4115 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4116 //g_assert (!mono_compile_aot);
4119 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4120 /* this is not thread save, but good enough */
4121 /* fixme: howto handle overflows? */
4122 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4125 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4126 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4127 (gpointer)"mono_break");
4128 code = emit_call_seq (cfg, code);
4131 MONO_BB_FOR_EACH_INS (bb, ins) {
4132 offset = code - cfg->native_code;
4134 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4136 if (offset > (cfg->code_size - max_len - 16)) {
4137 cfg->code_size *= 2;
4138 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4139 code = cfg->native_code + offset;
4141 // if (ins->cil_code)
4142 // g_print ("cil code\n");
4143 mono_debug_record_line_number (cfg, ins, offset);
4145 switch (ins->opcode) {
4146 case OP_MEMORY_BARRIER:
4148 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4149 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4152 case OP_ATOMIC_EXCHANGE_I4:
4153 case OP_ATOMIC_CAS_I4:
4154 case OP_ATOMIC_ADD_I4: {
4158 g_assert (v7_supported);
4161 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4163 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4165 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4169 g_assert (cfg->arch.atomic_tmp_offset != -1);
4170 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4172 switch (ins->opcode) {
4173 case OP_ATOMIC_EXCHANGE_I4:
4175 ARM_DMB (code, ARM_DMB_SY);
4176 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4177 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4178 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4180 ARM_B_COND (code, ARMCOND_NE, 0);
4181 arm_patch (buf [1], buf [0]);
4183 case OP_ATOMIC_CAS_I4:
4184 ARM_DMB (code, ARM_DMB_SY);
4186 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4187 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4189 ARM_B_COND (code, ARMCOND_NE, 0);
4190 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4191 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4193 ARM_B_COND (code, ARMCOND_NE, 0);
4194 arm_patch (buf [2], buf [0]);
4195 arm_patch (buf [1], code);
4197 case OP_ATOMIC_ADD_I4:
4199 ARM_DMB (code, ARM_DMB_SY);
4200 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4201 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4202 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4203 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4205 ARM_B_COND (code, ARMCOND_NE, 0);
4206 arm_patch (buf [1], buf [0]);
4209 g_assert_not_reached ();
4212 ARM_DMB (code, ARM_DMB_SY);
4213 if (tmpreg != ins->dreg)
4214 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4215 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4218 case OP_ATOMIC_LOAD_I1:
4219 case OP_ATOMIC_LOAD_U1:
4220 case OP_ATOMIC_LOAD_I2:
4221 case OP_ATOMIC_LOAD_U2:
4222 case OP_ATOMIC_LOAD_I4:
4223 case OP_ATOMIC_LOAD_U4:
4224 case OP_ATOMIC_LOAD_R4:
4225 case OP_ATOMIC_LOAD_R8: {
4226 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4227 ARM_DMB (code, ARM_DMB_SY);
4229 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4231 switch (ins->opcode) {
4232 case OP_ATOMIC_LOAD_I1:
4233 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4235 case OP_ATOMIC_LOAD_U1:
4236 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4238 case OP_ATOMIC_LOAD_I2:
4239 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4241 case OP_ATOMIC_LOAD_U2:
4242 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4244 case OP_ATOMIC_LOAD_I4:
4245 case OP_ATOMIC_LOAD_U4:
4246 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4248 case OP_ATOMIC_LOAD_R4:
4250 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4251 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4253 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4254 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4255 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4256 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4257 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4260 case OP_ATOMIC_LOAD_R8:
4261 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4262 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4266 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4267 ARM_DMB (code, ARM_DMB_SY);
4270 case OP_ATOMIC_STORE_I1:
4271 case OP_ATOMIC_STORE_U1:
4272 case OP_ATOMIC_STORE_I2:
4273 case OP_ATOMIC_STORE_U2:
4274 case OP_ATOMIC_STORE_I4:
4275 case OP_ATOMIC_STORE_U4:
4276 case OP_ATOMIC_STORE_R4:
4277 case OP_ATOMIC_STORE_R8: {
4278 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4279 ARM_DMB (code, ARM_DMB_SY);
4281 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4283 switch (ins->opcode) {
4284 case OP_ATOMIC_STORE_I1:
4285 case OP_ATOMIC_STORE_U1:
4286 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4288 case OP_ATOMIC_STORE_I2:
4289 case OP_ATOMIC_STORE_U2:
4290 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4292 case OP_ATOMIC_STORE_I4:
4293 case OP_ATOMIC_STORE_U4:
4294 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4296 case OP_ATOMIC_STORE_R4:
4298 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4299 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4301 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4302 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4303 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4304 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4305 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4308 case OP_ATOMIC_STORE_R8:
4309 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4310 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4314 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4315 ARM_DMB (code, ARM_DMB_SY);
4319 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4322 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4324 case OP_STOREI1_MEMBASE_IMM:
4325 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4326 g_assert (arm_is_imm12 (ins->inst_offset));
4327 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4329 case OP_STOREI2_MEMBASE_IMM:
4330 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4331 g_assert (arm_is_imm8 (ins->inst_offset));
4332 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4334 case OP_STORE_MEMBASE_IMM:
4335 case OP_STOREI4_MEMBASE_IMM:
4336 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4337 g_assert (arm_is_imm12 (ins->inst_offset));
4338 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4340 case OP_STOREI1_MEMBASE_REG:
4341 g_assert (arm_is_imm12 (ins->inst_offset));
4342 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4344 case OP_STOREI2_MEMBASE_REG:
4345 g_assert (arm_is_imm8 (ins->inst_offset));
4346 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4348 case OP_STORE_MEMBASE_REG:
4349 case OP_STOREI4_MEMBASE_REG:
4350 /* this case is special, since it happens for spill code after lowering has been called */
4351 if (arm_is_imm12 (ins->inst_offset)) {
4352 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4354 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4355 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4358 case OP_STOREI1_MEMINDEX:
4359 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4361 case OP_STOREI2_MEMINDEX:
4362 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4364 case OP_STORE_MEMINDEX:
4365 case OP_STOREI4_MEMINDEX:
4366 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4369 g_assert_not_reached ();
4371 case OP_LOAD_MEMINDEX:
4372 case OP_LOADI4_MEMINDEX:
4373 case OP_LOADU4_MEMINDEX:
4374 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4376 case OP_LOADI1_MEMINDEX:
4377 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4379 case OP_LOADU1_MEMINDEX:
4380 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4382 case OP_LOADI2_MEMINDEX:
4383 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4385 case OP_LOADU2_MEMINDEX:
4386 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4388 case OP_LOAD_MEMBASE:
4389 case OP_LOADI4_MEMBASE:
4390 case OP_LOADU4_MEMBASE:
4391 /* this case is special, since it happens for spill code after lowering has been called */
4392 if (arm_is_imm12 (ins->inst_offset)) {
4393 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4395 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4396 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4399 case OP_LOADI1_MEMBASE:
4400 g_assert (arm_is_imm8 (ins->inst_offset));
4401 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4403 case OP_LOADU1_MEMBASE:
4404 g_assert (arm_is_imm12 (ins->inst_offset));
4405 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4407 case OP_LOADU2_MEMBASE:
4408 g_assert (arm_is_imm8 (ins->inst_offset));
4409 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4411 case OP_LOADI2_MEMBASE:
4412 g_assert (arm_is_imm8 (ins->inst_offset));
4413 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4415 case OP_ICONV_TO_I1:
4416 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4417 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4419 case OP_ICONV_TO_I2:
4420 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4421 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4423 case OP_ICONV_TO_U1:
4424 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4426 case OP_ICONV_TO_U2:
4427 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4428 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4432 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4434 case OP_COMPARE_IMM:
4435 case OP_ICOMPARE_IMM:
4436 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4437 g_assert (imm8 >= 0);
4438 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4442 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4443 * So instead of emitting a trap, we emit a call a C function and place a
4446 //*(int*)code = 0xef9f0001;
4449 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4450 (gpointer)"mono_break");
4451 code = emit_call_seq (cfg, code);
4453 case OP_RELAXED_NOP:
4458 case OP_DUMMY_STORE:
4459 case OP_DUMMY_ICONST:
4460 case OP_DUMMY_R8CONST:
4461 case OP_NOT_REACHED:
4464 case OP_IL_SEQ_POINT:
4465 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4467 case OP_SEQ_POINT: {
4469 MonoInst *info_var = cfg->arch.seq_point_info_var;
4470 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4471 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4472 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4474 int dreg = ARMREG_LR;
4477 if (cfg->soft_breakpoints) {
4478 g_assert (!cfg->compile_aot);
4483 * For AOT, we use one got slot per method, which will point to a
4484 * SeqPointInfo structure, containing all the information required
4485 * by the code below.
4487 if (cfg->compile_aot) {
4488 g_assert (info_var);
4489 g_assert (info_var->opcode == OP_REGOFFSET);
4490 g_assert (arm_is_imm12 (info_var->inst_offset));
4493 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4495 * Read from the single stepping trigger page. This will cause a
4496 * SIGSEGV when single stepping is enabled.
4497 * We do this _before_ the breakpoint, so single stepping after
4498 * a breakpoint is hit will step to the next IL offset.
4500 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4503 /* Single step check */
4504 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4505 if (cfg->soft_breakpoints) {
4506 /* Load the address of the sequence point method variable. */
4507 var = ss_method_var;
4509 g_assert (var->opcode == OP_REGOFFSET);
4510 g_assert (arm_is_imm12 (var->inst_offset));
4511 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4513 /* Read the value and check whether it is non-zero. */
4514 ARM_LDR_IMM (code, dreg, dreg, 0);
4515 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4516 /* Call it conditionally. */
4517 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4519 if (cfg->compile_aot) {
4520 /* Load the trigger page addr from the variable initialized in the prolog */
4521 var = ss_trigger_page_var;
4523 g_assert (var->opcode == OP_REGOFFSET);
4524 g_assert (arm_is_imm12 (var->inst_offset));
4525 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4527 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4529 *(int*)code = (int)ss_trigger_page;
4532 ARM_LDR_IMM (code, dreg, dreg, 0);
4536 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4538 /* Breakpoint check */
4539 if (cfg->compile_aot) {
4540 guint32 offset = code - cfg->native_code;
4543 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4544 /* Add the offset */
4545 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4546 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4547 if (arm_is_imm12 ((int)val)) {
4548 ARM_LDR_IMM (code, dreg, dreg, val);
4550 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4552 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4554 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4555 g_assert (!(val & 0xFF000000));
4557 ARM_LDR_IMM (code, dreg, dreg, 0);
4559 /* What is faster, a branch or a load ? */
4560 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4561 /* The breakpoint instruction */
4562 if (cfg->soft_breakpoints)
4563 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4565 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4566 } else if (cfg->soft_breakpoints) {
4567 /* Load the address of the breakpoint method into ip. */
4568 var = bp_method_var;
4570 g_assert (var->opcode == OP_REGOFFSET);
4571 g_assert (arm_is_imm12 (var->inst_offset));
4572 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4575 * A placeholder for a possible breakpoint inserted by
4576 * mono_arch_set_breakpoint ().
4581 * A placeholder for a possible breakpoint inserted by
4582 * mono_arch_set_breakpoint ().
4584 for (i = 0; i < 4; ++i)
4589 * Add an additional nop so skipping the bp doesn't cause the ip to point
4590 * to another IL offset.
4598 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4601 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4605 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4608 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4609 g_assert (imm8 >= 0);
4610 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4614 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4615 g_assert (imm8 >= 0);
4616 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4620 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4621 g_assert (imm8 >= 0);
4622 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4625 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4626 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4628 case OP_IADD_OVF_UN:
4629 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4630 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4633 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4634 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4636 case OP_ISUB_OVF_UN:
4637 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4638 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4640 case OP_ADD_OVF_CARRY:
4641 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4642 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4644 case OP_ADD_OVF_UN_CARRY:
4645 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4646 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4648 case OP_SUB_OVF_CARRY:
4649 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4650 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4652 case OP_SUB_OVF_UN_CARRY:
4653 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4654 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4658 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4661 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4662 g_assert (imm8 >= 0);
4663 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4666 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4670 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4674 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4675 g_assert (imm8 >= 0);
4676 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4680 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4681 g_assert (imm8 >= 0);
4682 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4684 case OP_ARM_RSBS_IMM:
4685 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4686 g_assert (imm8 >= 0);
4687 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4689 case OP_ARM_RSC_IMM:
4690 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4691 g_assert (imm8 >= 0);
4692 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4695 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4699 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4700 g_assert (imm8 >= 0);
4701 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4704 g_assert (v7s_supported || v7k_supported);
4705 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4708 g_assert (v7s_supported || v7k_supported);
4709 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4712 g_assert (v7s_supported || v7k_supported);
4713 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4714 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4717 g_assert (v7s_supported || v7k_supported);
4718 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4719 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4723 g_assert_not_reached ();
4725 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4730 g_assert (imm8 >= 0);
4731 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4734 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4738 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4739 g_assert (imm8 >= 0);
4740 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4743 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4748 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4749 else if (ins->dreg != ins->sreg1)
4750 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4753 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4758 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4759 else if (ins->dreg != ins->sreg1)
4760 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4763 case OP_ISHR_UN_IMM:
4765 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4766 else if (ins->dreg != ins->sreg1)
4767 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4770 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4773 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4776 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4779 if (ins->dreg == ins->sreg2)
4780 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4782 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4785 g_assert_not_reached ();
4788 /* FIXME: handle ovf/ sreg2 != dreg */
4789 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4790 /* FIXME: MUL doesn't set the C/O flags on ARM */
4792 case OP_IMUL_OVF_UN:
4793 /* FIXME: handle ovf/ sreg2 != dreg */
4794 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4795 /* FIXME: MUL doesn't set the C/O flags on ARM */
4798 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4801 /* Load the GOT offset */
4802 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4803 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4805 *(gpointer*)code = NULL;
4807 /* Load the value from the GOT */
4808 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4810 case OP_OBJC_GET_SELECTOR:
4811 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4812 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4814 *(gpointer*)code = NULL;
4816 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4818 case OP_ICONV_TO_I4:
4819 case OP_ICONV_TO_U4:
4821 if (ins->dreg != ins->sreg1)
4822 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4825 int saved = ins->sreg2;
4826 if (ins->sreg2 == ARM_LSW_REG) {
4827 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4830 if (ins->sreg1 != ARM_LSW_REG)
4831 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4832 if (saved != ARM_MSW_REG)
4833 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4837 if (IS_VFP && ins->dreg != ins->sreg1)
4838 ARM_CPYD (code, ins->dreg, ins->sreg1);
4841 if (IS_VFP && ins->dreg != ins->sreg1)
4842 ARM_CPYS (code, ins->dreg, ins->sreg1);
4844 case OP_MOVE_F_TO_I4:
4846 ARM_FMRS (code, ins->dreg, ins->sreg1);
4848 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4849 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4850 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4851 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4854 case OP_MOVE_I4_TO_F:
4856 ARM_FMSR (code, ins->dreg, ins->sreg1);
4858 ARM_FMSR (code, ins->dreg, ins->sreg1);
4859 ARM_CVTS (code, ins->dreg, ins->dreg);
4862 case OP_FCONV_TO_R4:
4865 ARM_CVTD (code, ins->dreg, ins->sreg1);
4867 ARM_CVTD (code, ins->dreg, ins->sreg1);
4868 ARM_CVTS (code, ins->dreg, ins->dreg);
4873 MonoCallInst *call = (MonoCallInst*)ins;
4876 * The stack looks like the following:
4877 * <caller argument area>
4880 * <callee argument area>
4881 * Need to copy the arguments from the callee argument area to
4882 * the caller argument area, and pop the frame.
4884 if (call->stack_usage) {
4885 int i, prev_sp_offset = 0;
4887 /* Compute size of saved registers restored below */
4889 prev_sp_offset = 2 * 4;
4891 prev_sp_offset = 1 * 4;
4892 for (i = 0; i < 16; ++i) {
4893 if (cfg->used_int_regs & (1 << i))
4894 prev_sp_offset += 4;
4897 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4899 /* Copy arguments on the stack to our argument area */
4900 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4901 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4902 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4907 * Keep in sync with mono_arch_emit_epilog
4909 g_assert (!cfg->method->save_lmf);
4911 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4913 if (cfg->used_int_regs)
4914 ARM_POP (code, cfg->used_int_regs);
4915 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4917 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4920 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4921 if (cfg->compile_aot) {
4922 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4924 *(gpointer*)code = NULL;
4926 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4928 code = mono_arm_patchable_b (code, ARMCOND_AL);
4929 cfg->thunk_area += THUNK_SIZE;
4934 /* ensure ins->sreg1 is not NULL */
4935 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4938 g_assert (cfg->sig_cookie < 128);
4939 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4940 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4950 call = (MonoCallInst*)ins;
4953 code = emit_float_args (cfg, call, code, &max_len, &offset);
4955 if (ins->flags & MONO_INST_HAS_METHOD)
4956 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4958 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4959 code = emit_call_seq (cfg, code);
4960 ins->flags |= MONO_INST_GC_CALLSITE;
4961 ins->backend.pc_offset = code - cfg->native_code;
4962 code = emit_move_return_value (cfg, ins, code);
4969 case OP_VOIDCALL_REG:
4972 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
4974 code = emit_call_reg (code, ins->sreg1);
4975 ins->flags |= MONO_INST_GC_CALLSITE;
4976 ins->backend.pc_offset = code - cfg->native_code;
4977 code = emit_move_return_value (cfg, ins, code);
4979 case OP_FCALL_MEMBASE:
4980 case OP_RCALL_MEMBASE:
4981 case OP_LCALL_MEMBASE:
4982 case OP_VCALL_MEMBASE:
4983 case OP_VCALL2_MEMBASE:
4984 case OP_VOIDCALL_MEMBASE:
4985 case OP_CALL_MEMBASE: {
4986 g_assert (ins->sreg1 != ARMREG_LR);
4987 call = (MonoCallInst*)ins;
4990 code = emit_float_args (cfg, call, code, &max_len, &offset);
4991 if (!arm_is_imm12 (ins->inst_offset)) {
4992 /* sreg1 might be IP */
4993 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
4994 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
4995 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
4996 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4997 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
4999 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5000 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5002 ins->flags |= MONO_INST_GC_CALLSITE;
5003 ins->backend.pc_offset = code - cfg->native_code;
5004 code = emit_move_return_value (cfg, ins, code);
5007 case OP_GENERIC_CLASS_INIT: {
5011 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5013 g_assert (arm_is_imm8 (byte_offset));
5014 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5015 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5017 ARM_B_COND (code, ARMCOND_NE, 0);
5019 /* Uninitialized case */
5020 g_assert (ins->sreg1 == ARMREG_R0);
5022 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5023 (gpointer)"mono_generic_class_init");
5024 code = emit_call_seq (cfg, code);
5026 /* Initialized case */
5027 arm_patch (jump, code);
5031 /* round the size to 8 bytes */
5032 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5033 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5034 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5035 /* memzero the area: dreg holds the size, sp is the pointer */
5036 if (ins->flags & MONO_INST_INIT) {
5037 guint8 *start_loop, *branch_to_cond;
5038 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5039 branch_to_cond = code;
5042 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5043 arm_patch (branch_to_cond, code);
5044 /* decrement by 4 and set flags */
5045 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5046 ARM_B_COND (code, ARMCOND_GE, 0);
5047 arm_patch (code - 4, start_loop);
5049 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5050 if (cfg->param_area)
5051 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5056 MonoInst *var = cfg->dyn_call_var;
5059 g_assert (var->opcode == OP_REGOFFSET);
5060 g_assert (arm_is_imm12 (var->inst_offset));
5062 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5063 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5065 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5067 /* Save args buffer */
5068 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5070 /* Set stack slots using R0 as scratch reg */
5071 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5072 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5073 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5074 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5077 /* Set fp argument registers */
5078 if (IS_HARD_FLOAT) {
5079 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5080 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5082 ARM_B_COND (code, ARMCOND_EQ, 0);
5083 for (i = 0; i < FP_PARAM_REGS; ++i) {
5084 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5085 g_assert (arm_is_fpimm8 (offset));
5086 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5088 arm_patch (buf [0], code);
5091 /* Set argument registers */
5092 for (i = 0; i < PARAM_REGS; ++i)
5093 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5096 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5097 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5100 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5101 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5102 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5104 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5108 if (ins->sreg1 != ARMREG_R0)
5109 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5110 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5111 (gpointer)"mono_arch_throw_exception");
5112 code = emit_call_seq (cfg, code);
5116 if (ins->sreg1 != ARMREG_R0)
5117 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5118 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5119 (gpointer)"mono_arch_rethrow_exception");
5120 code = emit_call_seq (cfg, code);
5123 case OP_START_HANDLER: {
5124 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5125 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5128 /* Reserve a param area, see filter-stack.exe */
5130 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5131 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5133 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5134 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5138 if (arm_is_imm12 (spvar->inst_offset)) {
5139 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5141 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5142 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5146 case OP_ENDFILTER: {
5147 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5148 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5151 /* Free the param area */
5153 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5154 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5156 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5157 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5161 if (ins->sreg1 != ARMREG_R0)
5162 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5163 if (arm_is_imm12 (spvar->inst_offset)) {
5164 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5166 g_assert (ARMREG_IP != spvar->inst_basereg);
5167 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5168 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5170 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5173 case OP_ENDFINALLY: {
5174 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5175 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5178 /* Free the param area */
5180 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5181 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5183 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5184 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5188 if (arm_is_imm12 (spvar->inst_offset)) {
5189 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5191 g_assert (ARMREG_IP != spvar->inst_basereg);
5192 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5193 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5195 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5198 case OP_CALL_HANDLER:
5199 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5200 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5201 cfg->thunk_area += THUNK_SIZE;
5202 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5205 if (ins->dreg != ARMREG_R0)
5206 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5210 ins->inst_c0 = code - cfg->native_code;
5213 /*if (ins->inst_target_bb->native_offset) {
5215 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5217 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5218 code = mono_arm_patchable_b (code, ARMCOND_AL);
5222 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5226 * In the normal case we have:
5227 * ldr pc, [pc, ins->sreg1 << 2]
5230 * ldr lr, [pc, ins->sreg1 << 2]
5232 * After follows the data.
5233 * FIXME: add aot support.
5235 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5236 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5237 if (offset + max_len > (cfg->code_size - 16)) {
5238 cfg->code_size += max_len;
5239 cfg->code_size *= 2;
5240 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5241 code = cfg->native_code + offset;
5243 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5245 code += 4 * GPOINTER_TO_INT (ins->klass);
5249 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5250 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5254 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5255 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5259 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5260 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5264 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5265 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5269 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5270 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5273 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5274 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5277 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5278 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5281 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5282 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5285 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5286 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5289 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5290 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5292 case OP_COND_EXC_EQ:
5293 case OP_COND_EXC_NE_UN:
5294 case OP_COND_EXC_LT:
5295 case OP_COND_EXC_LT_UN:
5296 case OP_COND_EXC_GT:
5297 case OP_COND_EXC_GT_UN:
5298 case OP_COND_EXC_GE:
5299 case OP_COND_EXC_GE_UN:
5300 case OP_COND_EXC_LE:
5301 case OP_COND_EXC_LE_UN:
5302 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5304 case OP_COND_EXC_IEQ:
5305 case OP_COND_EXC_INE_UN:
5306 case OP_COND_EXC_ILT:
5307 case OP_COND_EXC_ILT_UN:
5308 case OP_COND_EXC_IGT:
5309 case OP_COND_EXC_IGT_UN:
5310 case OP_COND_EXC_IGE:
5311 case OP_COND_EXC_IGE_UN:
5312 case OP_COND_EXC_ILE:
5313 case OP_COND_EXC_ILE_UN:
5314 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5317 case OP_COND_EXC_IC:
5318 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5320 case OP_COND_EXC_OV:
5321 case OP_COND_EXC_IOV:
5322 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5324 case OP_COND_EXC_NC:
5325 case OP_COND_EXC_INC:
5326 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5328 case OP_COND_EXC_NO:
5329 case OP_COND_EXC_INO:
5330 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5342 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5345 /* floating point opcodes */
5347 if (cfg->compile_aot) {
5348 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5350 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5352 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5355 /* FIXME: we can optimize the imm load by dealing with part of
5356 * the displacement in LDFD (aligning to 512).
5358 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5359 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5363 if (cfg->compile_aot) {
5364 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5366 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5369 ARM_CVTS (code, ins->dreg, ins->dreg);
5371 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5372 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5374 ARM_CVTS (code, ins->dreg, ins->dreg);
5377 case OP_STORER8_MEMBASE_REG:
5378 /* This is generated by the local regalloc pass which runs after the lowering pass */
5379 if (!arm_is_fpimm8 (ins->inst_offset)) {
5380 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5381 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5382 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5384 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5387 case OP_LOADR8_MEMBASE:
5388 /* This is generated by the local regalloc pass which runs after the lowering pass */
5389 if (!arm_is_fpimm8 (ins->inst_offset)) {
5390 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5391 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5392 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5394 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5397 case OP_STORER4_MEMBASE_REG:
5398 g_assert (arm_is_fpimm8 (ins->inst_offset));
5400 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5402 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5403 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5404 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5405 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5408 case OP_LOADR4_MEMBASE:
5410 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5412 g_assert (arm_is_fpimm8 (ins->inst_offset));
5413 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5414 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5415 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5416 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5419 case OP_ICONV_TO_R_UN: {
5420 g_assert_not_reached ();
5423 case OP_ICONV_TO_R4:
5425 ARM_FMSR (code, ins->dreg, ins->sreg1);
5426 ARM_FSITOS (code, ins->dreg, ins->dreg);
5428 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5429 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5430 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5431 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5432 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5435 case OP_ICONV_TO_R8:
5436 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5437 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5438 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5439 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5443 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5444 if (sig_ret->type == MONO_TYPE_R4) {
5446 if (IS_HARD_FLOAT) {
5447 if (ins->sreg1 != ARM_VFP_D0)
5448 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5450 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5453 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5456 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5460 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5462 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5466 case OP_FCONV_TO_I1:
5467 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5469 case OP_FCONV_TO_U1:
5470 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5472 case OP_FCONV_TO_I2:
5473 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5475 case OP_FCONV_TO_U2:
5476 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5478 case OP_FCONV_TO_I4:
5480 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5482 case OP_FCONV_TO_U4:
5484 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5486 case OP_FCONV_TO_I8:
5487 case OP_FCONV_TO_U8:
5488 g_assert_not_reached ();
5489 /* Implemented as helper calls */
5491 case OP_LCONV_TO_R_UN:
5492 g_assert_not_reached ();
5493 /* Implemented as helper calls */
5495 case OP_LCONV_TO_OVF_I4_2: {
5496 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5498 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5501 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5502 high_bit_not_set = code;
5503 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5505 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5506 valid_negative = code;
5507 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5508 invalid_negative = code;
5509 ARM_B_COND (code, ARMCOND_AL, 0);
5511 arm_patch (high_bit_not_set, code);
5513 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5514 valid_positive = code;
5515 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5517 arm_patch (invalid_negative, code);
5518 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5520 arm_patch (valid_negative, code);
5521 arm_patch (valid_positive, code);
5523 if (ins->dreg != ins->sreg1)
5524 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5528 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5531 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5534 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5537 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5540 ARM_NEGD (code, ins->dreg, ins->sreg1);
5544 g_assert_not_reached ();
5548 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5554 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5559 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5562 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5563 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5567 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5570 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5571 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5575 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5578 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5579 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5580 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5584 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5587 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5588 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5592 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5595 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5596 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5597 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5601 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5604 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5605 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5609 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5612 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5613 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5617 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5620 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5621 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5624 /* ARM FPA flags table:
5625 * N Less than ARMCOND_MI
5626 * Z Equal ARMCOND_EQ
5627 * C Greater Than or Equal ARMCOND_CS
5628 * V Unordered ARMCOND_VS
5631 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5634 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5637 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5640 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5641 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5647 g_assert_not_reached ();
5651 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5653 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5654 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5655 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5659 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5660 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5665 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5666 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5668 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5669 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5671 *(guint32*)code = 0xffffffff;
5673 *(guint32*)code = 0x7fefffff;
5675 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5677 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5678 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5680 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5681 ARM_CPYD (code, ins->dreg, ins->sreg1);
5683 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5684 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5689 case OP_RCONV_TO_I1:
5690 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5692 case OP_RCONV_TO_U1:
5693 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5695 case OP_RCONV_TO_I2:
5696 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5698 case OP_RCONV_TO_U2:
5699 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5701 case OP_RCONV_TO_I4:
5702 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5704 case OP_RCONV_TO_U4:
5705 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5707 case OP_RCONV_TO_R4:
5709 if (ins->dreg != ins->sreg1)
5710 ARM_CPYS (code, ins->dreg, ins->sreg1);
5712 case OP_RCONV_TO_R8:
5714 ARM_CVTS (code, ins->dreg, ins->sreg1);
5717 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5720 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5723 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5726 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5729 ARM_NEGS (code, ins->dreg, ins->sreg1);
5733 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5736 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5737 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5741 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5744 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5745 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5749 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5752 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5753 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5754 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5758 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5761 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5762 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5766 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5769 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5770 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5771 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5775 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5778 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5779 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5783 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5786 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5787 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5791 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5794 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5795 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5798 case OP_GC_LIVENESS_DEF:
5799 case OP_GC_LIVENESS_USE:
5800 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5801 ins->backend.pc_offset = code - cfg->native_code;
5803 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5804 ins->backend.pc_offset = code - cfg->native_code;
5805 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5807 case OP_GC_SAFE_POINT: {
5810 g_assert (mono_threads_is_coop_enabled ());
5812 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5813 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5815 ARM_B_COND (code, ARMCOND_EQ, 0);
5816 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5817 code = emit_call_seq (cfg, code);
5818 arm_patch (buf [0], code);
5823 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5824 g_assert_not_reached ();
5827 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5828 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5829 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5830 g_assert_not_reached ();
5836 last_offset = offset;
5839 cfg->code_len = code - cfg->native_code;
5842 #endif /* DISABLE_JIT */
5845 mono_arch_register_lowlevel_calls (void)
5847 /* The signature doesn't matter */
5848 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5849 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5850 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5853 #define patch_lis_ori(ip,val) do {\
5854 guint16 *__lis_ori = (guint16*)(ip); \
5855 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5856 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5860 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5862 unsigned char *ip = ji->ip.i + code;
5864 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5868 case MONO_PATCH_INFO_SWITCH: {
5869 gpointer *jt = (gpointer*)(ip + 8);
5871 /* jt is the inlined jump table, 2 instructions after ip
5872 * In the normal case we store the absolute addresses,
5873 * otherwise the displacements.
5875 for (i = 0; i < ji->data.table->table_size; i++)
5876 jt [i] = code + (int)ji->data.table->table [i];
5879 case MONO_PATCH_INFO_IP:
5880 g_assert_not_reached ();
5881 patch_lis_ori (ip, ip);
5883 case MONO_PATCH_INFO_METHOD_REL:
5884 g_assert_not_reached ();
5885 *((gpointer *)(ip)) = target;
5887 case MONO_PATCH_INFO_METHODCONST:
5888 case MONO_PATCH_INFO_CLASS:
5889 case MONO_PATCH_INFO_IMAGE:
5890 case MONO_PATCH_INFO_FIELD:
5891 case MONO_PATCH_INFO_VTABLE:
5892 case MONO_PATCH_INFO_IID:
5893 case MONO_PATCH_INFO_SFLDA:
5894 case MONO_PATCH_INFO_LDSTR:
5895 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5896 case MONO_PATCH_INFO_LDTOKEN:
5897 g_assert_not_reached ();
5898 /* from OP_AOTCONST : lis + ori */
5899 patch_lis_ori (ip, target);
5901 case MONO_PATCH_INFO_R4:
5902 case MONO_PATCH_INFO_R8:
5903 g_assert_not_reached ();
5904 *((gconstpointer *)(ip + 2)) = target;
5906 case MONO_PATCH_INFO_EXC_NAME:
5907 g_assert_not_reached ();
5908 *((gconstpointer *)(ip + 1)) = target;
5910 case MONO_PATCH_INFO_NONE:
5911 case MONO_PATCH_INFO_BB_OVF:
5912 case MONO_PATCH_INFO_EXC_OVF:
5913 /* everything is dealt with at epilog output time */
5916 arm_patch_general (cfg, domain, ip, target);
5922 mono_arm_unaligned_stack (MonoMethod *method)
5924 g_assert_not_reached ();
5930 * Stack frame layout:
5932 * ------------------- fp
5933 * MonoLMF structure or saved registers
5934 * -------------------
5936 * -------------------
5938 * -------------------
5939 * optional 8 bytes for tracing
5940 * -------------------
5941 * param area size is cfg->param_area
5942 * ------------------- sp
5945 mono_arch_emit_prolog (MonoCompile *cfg)
5947 MonoMethod *method = cfg->method;
5949 MonoMethodSignature *sig;
5951 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
5956 int prev_sp_offset, reg_offset;
5958 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5961 sig = mono_method_signature (method);
5962 cfg->code_size = 256 + sig->param_count * 64;
5963 code = cfg->native_code = g_malloc (cfg->code_size);
5965 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5967 alloc_size = cfg->stack_offset;
5973 * The iphone uses R7 as the frame pointer, and it points at the saved
5978 * We can't use r7 as a frame pointer since it points into the middle of
5979 * the frame, so we keep using our own frame pointer.
5980 * FIXME: Optimize this.
5982 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5983 prev_sp_offset += 8; /* r7 and lr */
5984 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5985 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5986 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5989 if (!method->save_lmf) {
5991 /* No need to push LR again */
5992 if (cfg->used_int_regs)
5993 ARM_PUSH (code, cfg->used_int_regs);
5995 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5996 prev_sp_offset += 4;
5998 for (i = 0; i < 16; ++i) {
5999 if (cfg->used_int_regs & (1 << i))
6000 prev_sp_offset += 4;
6002 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6004 for (i = 0; i < 16; ++i) {
6005 if ((cfg->used_int_regs & (1 << i))) {
6006 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6007 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6011 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6012 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6014 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6015 ARM_PUSH (code, 0x5ff0);
6016 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6017 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6019 for (i = 0; i < 16; ++i) {
6020 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6021 /* The original r7 is saved at the start */
6022 if (!(iphone_abi && i == ARMREG_R7))
6023 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6027 g_assert (reg_offset == 4 * 10);
6028 pos += sizeof (MonoLMF) - (4 * 10);
6032 orig_alloc_size = alloc_size;
6033 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6034 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6035 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6036 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6039 /* the stack used in the pushed regs */
6040 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6041 cfg->stack_usage = alloc_size;
6043 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6044 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6046 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6047 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6049 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6051 if (cfg->frame_reg != ARMREG_SP) {
6052 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6053 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6055 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6056 prev_sp_offset += alloc_size;
6058 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6059 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6061 /* compute max_offset in order to use short forward jumps
6062 * we could skip do it on arm because the immediate displacement
6063 * for jumps is large enough, it may be useful later for constant pools
6066 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6067 MonoInst *ins = bb->code;
6068 bb->max_offset = max_offset;
6070 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6073 MONO_BB_FOR_EACH_INS (bb, ins)
6074 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6077 /* stack alignment check */
6081 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6082 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6083 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6084 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6086 ARM_B_COND (code, ARMCOND_EQ, 0);
6087 if (cfg->compile_aot)
6088 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6090 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6091 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6092 code = emit_call_seq (cfg, code);
6093 arm_patch (buf [0], code);
6097 /* store runtime generic context */
6098 if (cfg->rgctx_var) {
6099 MonoInst *ins = cfg->rgctx_var;
6101 g_assert (ins->opcode == OP_REGOFFSET);
6103 if (arm_is_imm12 (ins->inst_offset)) {
6104 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6106 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6107 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6111 /* load arguments allocated to register from the stack */
6114 cinfo = get_call_info (NULL, sig);
6116 if (cinfo->ret.storage == RegTypeStructByAddr) {
6117 ArgInfo *ainfo = &cinfo->ret;
6118 inst = cfg->vret_addr;
6119 g_assert (arm_is_imm12 (inst->inst_offset));
6120 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6123 if (sig->call_convention == MONO_CALL_VARARG) {
6124 ArgInfo *cookie = &cinfo->sig_cookie;
6126 /* Save the sig cookie address */
6127 g_assert (cookie->storage == RegTypeBase);
6129 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6130 g_assert (arm_is_imm12 (cfg->sig_cookie));
6131 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6132 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6135 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6136 ArgInfo *ainfo = cinfo->args + i;
6137 inst = cfg->args [pos];
6139 if (cfg->verbose_level > 2)
6140 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6142 if (inst->opcode == OP_REGVAR) {
6143 if (ainfo->storage == RegTypeGeneral)
6144 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6145 else if (ainfo->storage == RegTypeFP) {
6146 g_assert_not_reached ();
6147 } else if (ainfo->storage == RegTypeBase) {
6148 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6149 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6151 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6152 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6155 g_assert_not_reached ();
6157 if (cfg->verbose_level > 2)
6158 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6160 switch (ainfo->storage) {
6162 for (part = 0; part < ainfo->nregs; part ++) {
6163 if (ainfo->esize == 4)
6164 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6166 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6169 case RegTypeGeneral:
6170 case RegTypeIRegPair:
6171 case RegTypeGSharedVtInReg:
6172 case RegTypeStructByAddr:
6173 switch (ainfo->size) {
6175 if (arm_is_imm12 (inst->inst_offset))
6176 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6178 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6179 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6183 if (arm_is_imm8 (inst->inst_offset)) {
6184 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6186 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6187 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6191 if (arm_is_imm12 (inst->inst_offset)) {
6192 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6194 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6195 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6197 if (arm_is_imm12 (inst->inst_offset + 4)) {
6198 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6200 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6201 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6205 if (arm_is_imm12 (inst->inst_offset)) {
6206 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6208 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6209 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6214 case RegTypeBaseGen:
6215 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6216 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6218 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6219 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6221 if (arm_is_imm12 (inst->inst_offset + 4)) {
6222 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6223 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6225 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6226 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6227 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6228 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6232 case RegTypeGSharedVtOnStack:
6233 case RegTypeStructByAddrOnStack:
6234 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6235 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6237 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6238 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6241 switch (ainfo->size) {
6243 if (arm_is_imm8 (inst->inst_offset)) {
6244 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6246 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6247 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6251 if (arm_is_imm8 (inst->inst_offset)) {
6252 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6254 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6255 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6259 if (arm_is_imm12 (inst->inst_offset)) {
6260 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6262 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6263 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6265 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6266 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6268 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6269 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6271 if (arm_is_imm12 (inst->inst_offset + 4)) {
6272 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6274 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6275 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6279 if (arm_is_imm12 (inst->inst_offset)) {
6280 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6282 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6283 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6289 int imm8, rot_amount;
6291 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6292 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6293 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6295 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6297 if (ainfo->size == 8)
6298 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6300 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6303 case RegTypeStructByVal: {
6304 int doffset = inst->inst_offset;
6308 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6309 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6310 if (arm_is_imm12 (doffset)) {
6311 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6313 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6314 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6316 soffset += sizeof (gpointer);
6317 doffset += sizeof (gpointer);
6319 if (ainfo->vtsize) {
6320 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6321 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6322 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6327 g_assert_not_reached ();
6334 if (method->save_lmf)
6335 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6338 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6340 if (cfg->arch.seq_point_info_var) {
6341 MonoInst *ins = cfg->arch.seq_point_info_var;
6343 /* Initialize the variable from a GOT slot */
6344 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6345 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6347 *(gpointer*)code = NULL;
6349 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6351 g_assert (ins->opcode == OP_REGOFFSET);
6353 if (arm_is_imm12 (ins->inst_offset)) {
6354 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6356 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6357 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6361 /* Initialize ss_trigger_page_var */
6362 if (!cfg->soft_breakpoints) {
6363 MonoInst *info_var = cfg->arch.seq_point_info_var;
6364 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6365 int dreg = ARMREG_LR;
6368 g_assert (info_var->opcode == OP_REGOFFSET);
6369 g_assert (arm_is_imm12 (info_var->inst_offset));
6371 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6372 /* Load the trigger page addr */
6373 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6374 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6378 if (cfg->arch.seq_point_ss_method_var) {
6379 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6380 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6382 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6383 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6385 if (cfg->compile_aot) {
6386 MonoInst *info_var = cfg->arch.seq_point_info_var;
6387 int dreg = ARMREG_LR;
6389 g_assert (info_var->opcode == OP_REGOFFSET);
6390 g_assert (arm_is_imm12 (info_var->inst_offset));
6392 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6393 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6394 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6396 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6397 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6399 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6401 *(gpointer*)code = &single_step_tramp;
6403 *(gpointer*)code = breakpoint_tramp;
6406 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6407 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6408 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6409 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6413 cfg->code_len = code - cfg->native_code;
6414 g_assert (cfg->code_len < cfg->code_size);
6421 mono_arch_emit_epilog (MonoCompile *cfg)
6423 MonoMethod *method = cfg->method;
6424 int pos, i, rot_amount;
6425 int max_epilog_size = 16 + 20*4;
6429 if (cfg->method->save_lmf)
6430 max_epilog_size += 128;
6432 if (mono_jit_trace_calls != NULL)
6433 max_epilog_size += 50;
6435 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6436 max_epilog_size += 50;
6438 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6439 cfg->code_size *= 2;
6440 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6441 cfg->stat_code_reallocs++;
6445 * Keep in sync with OP_JMP
6447 code = cfg->native_code + cfg->code_len;
6449 /* Save the uwind state which is needed by the out-of-line code */
6450 mono_emit_unwind_op_remember_state (cfg, code);
6452 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6453 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6457 /* Load returned vtypes into registers if needed */
6458 cinfo = cfg->arch.cinfo;
6459 switch (cinfo->ret.storage) {
6460 case RegTypeStructByVal: {
6461 MonoInst *ins = cfg->ret;
6463 if (cinfo->ret.nregs == 1) {
6464 if (arm_is_imm12 (ins->inst_offset)) {
6465 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6467 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6468 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6471 for (i = 0; i < cinfo->ret.nregs; ++i) {
6472 int offset = ins->inst_offset + (i * 4);
6473 if (arm_is_imm12 (offset)) {
6474 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6476 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6477 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6484 MonoInst *ins = cfg->ret;
6486 for (i = 0; i < cinfo->ret.nregs; ++i) {
6487 if (cinfo->ret.esize == 4)
6488 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6490 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6498 if (method->save_lmf) {
6499 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6500 /* all but r0-r3, sp and pc */
6501 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6504 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6506 /* This points to r4 inside MonoLMF->iregs */
6507 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6509 regmask = 0x9ff0; /* restore lr to pc */
6510 /* Skip caller saved registers not used by the method */
6511 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6512 regmask &= ~(1 << reg);
6517 /* Restored later */
6518 regmask &= ~(1 << ARMREG_PC);
6519 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6520 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6521 for (i = 0; i < 16; i++) {
6522 if (regmask & (1 << i))
6525 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6527 ARM_POP (code, regmask);
6529 for (i = 0; i < 16; i++) {
6530 if (regmask & (1 << i))
6531 mono_emit_unwind_op_same_value (cfg, code, i);
6533 /* Restore saved r7, restore LR to PC */
6534 /* Skip lr from the lmf */
6535 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6536 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6537 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6538 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6541 int i, nused_int_regs = 0;
6543 for (i = 0; i < 16; i++) {
6544 if (cfg->used_int_regs & (1 << i))
6548 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6549 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6551 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6552 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6555 if (cfg->frame_reg != ARMREG_SP) {
6556 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6560 /* Restore saved gregs */
6561 if (cfg->used_int_regs) {
6562 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6563 ARM_POP (code, cfg->used_int_regs);
6564 for (i = 0; i < 16; i++) {
6565 if (cfg->used_int_regs & (1 << i))
6566 mono_emit_unwind_op_same_value (cfg, code, i);
6569 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6570 /* Restore saved r7, restore LR to PC */
6571 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6573 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6574 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6578 /* Restore the unwind state to be the same as before the epilog */
6579 mono_emit_unwind_op_restore_state (cfg, code);
6581 cfg->code_len = code - cfg->native_code;
6583 g_assert (cfg->code_len < cfg->code_size);
6588 mono_arch_emit_exceptions (MonoCompile *cfg)
6590 MonoJumpInfo *patch_info;
6593 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6594 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6595 int max_epilog_size = 50;
6597 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6598 exc_throw_pos [i] = NULL;
6599 exc_throw_found [i] = 0;
6602 /* count the number of exception infos */
6605 * make sure we have enough space for exceptions
6607 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6608 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6609 i = mini_exception_id_by_name (patch_info->data.target);
6610 if (!exc_throw_found [i]) {
6611 max_epilog_size += 32;
6612 exc_throw_found [i] = TRUE;
6617 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6618 cfg->code_size *= 2;
6619 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6620 cfg->stat_code_reallocs++;
6623 code = cfg->native_code + cfg->code_len;
6625 /* add code to raise exceptions */
6626 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6627 switch (patch_info->type) {
6628 case MONO_PATCH_INFO_EXC: {
6629 MonoClass *exc_class;
6630 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6632 i = mini_exception_id_by_name (patch_info->data.target);
6633 if (exc_throw_pos [i]) {
6634 arm_patch (ip, exc_throw_pos [i]);
6635 patch_info->type = MONO_PATCH_INFO_NONE;
6638 exc_throw_pos [i] = code;
6640 arm_patch (ip, code);
6642 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6644 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6645 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6646 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6647 patch_info->data.name = "mono_arch_throw_corlib_exception";
6648 patch_info->ip.i = code - cfg->native_code;
6650 cfg->thunk_area += THUNK_SIZE;
6651 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6661 cfg->code_len = code - cfg->native_code;
6663 g_assert (cfg->code_len < cfg->code_size);
6667 #endif /* #ifndef DISABLE_JIT */
6670 mono_arch_finish_init (void)
6675 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6680 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6687 mono_arch_print_tree (MonoInst *tree, int arity)
6697 mono_arch_get_patch_offset (guint8 *code)
6704 mono_arch_flush_register_windows (void)
6709 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6711 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6715 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6717 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6721 mono_arch_get_cie_program (void)
6725 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6730 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6731 #define BASE_SIZE (6 * 4)
6732 #define BSEARCH_ENTRY_SIZE (4 * 4)
6733 #define CMP_SIZE (3 * 4)
6734 #define BRANCH_SIZE (1 * 4)
6735 #define CALL_SIZE (2 * 4)
6736 #define WMC_SIZE (8 * 4)
6737 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6740 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6742 guint32 delta = DISTANCE (target, code);
6744 g_assert (delta >= 0 && delta <= 0xFFF);
6745 *target = *target | delta;
6750 #ifdef ENABLE_WRONG_METHOD_CHECK
6752 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6754 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6760 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6761 gpointer fail_tramp)
6764 arminstr_t *code, *start;
6765 gboolean large_offsets = FALSE;
6766 guint32 **constant_pool_starts;
6767 arminstr_t *vtable_target = NULL;
6768 int extra_space = 0;
6769 #ifdef ENABLE_WRONG_METHOD_CHECK
6775 constant_pool_starts = g_new0 (guint32*, count);
6777 for (i = 0; i < count; ++i) {
6778 MonoIMTCheckItem *item = imt_entries [i];
6779 if (item->is_equals) {
6780 gboolean fail_case = !item->check_target_idx && fail_tramp;
6782 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6783 item->chunk_size += 32;
6784 large_offsets = TRUE;
6787 if (item->check_target_idx || fail_case) {
6788 if (!item->compare_done || fail_case)
6789 item->chunk_size += CMP_SIZE;
6790 item->chunk_size += BRANCH_SIZE;
6792 #ifdef ENABLE_WRONG_METHOD_CHECK
6793 item->chunk_size += WMC_SIZE;
6797 item->chunk_size += 16;
6798 large_offsets = TRUE;
6800 item->chunk_size += CALL_SIZE;
6802 item->chunk_size += BSEARCH_ENTRY_SIZE;
6803 imt_entries [item->check_target_idx]->compare_done = TRUE;
6805 size += item->chunk_size;
6809 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6812 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6814 code = mono_domain_code_reserve (domain, size);
6817 unwind_ops = mono_arch_get_cie_program ();
6820 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6821 for (i = 0; i < count; ++i) {
6822 MonoIMTCheckItem *item = imt_entries [i];
6823 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6827 if (large_offsets) {
6828 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6829 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6831 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6832 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6834 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6835 vtable_target = code;
6836 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6837 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6839 for (i = 0; i < count; ++i) {
6840 MonoIMTCheckItem *item = imt_entries [i];
6841 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6842 gint32 vtable_offset;
6844 item->code_target = (guint8*)code;
6846 if (item->is_equals) {
6847 gboolean fail_case = !item->check_target_idx && fail_tramp;
6849 if (item->check_target_idx || fail_case) {
6850 if (!item->compare_done || fail_case) {
6852 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6853 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6855 item->jmp_code = (guint8*)code;
6856 ARM_B_COND (code, ARMCOND_NE, 0);
6858 /*Enable the commented code to assert on wrong method*/
6859 #ifdef ENABLE_WRONG_METHOD_CHECK
6861 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6862 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6864 ARM_B_COND (code, ARMCOND_EQ, 0);
6866 /* Define this if your system is so bad that gdb is failing. */
6867 #ifdef BROKEN_DEV_ENV
6868 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6870 arm_patch (code - 1, mini_dump_bad_imt);
6874 arm_patch (cond, code);
6878 if (item->has_target_code) {
6879 /* Load target address */
6880 target_code_ins = code;
6881 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6882 /* Save it to the fourth slot */
6883 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6884 /* Restore registers and branch */
6885 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6887 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6889 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6890 if (!arm_is_imm12 (vtable_offset)) {
6892 * We need to branch to a computed address but we don't have
6893 * a free register to store it, since IP must contain the
6894 * vtable address. So we push the two values to the stack, and
6895 * load them both using LDM.
6897 /* Compute target address */
6898 vtable_offset_ins = code;
6899 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6900 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6901 /* Save it to the fourth slot */
6902 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6903 /* Restore registers and branch */
6904 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6906 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6908 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6909 if (large_offsets) {
6910 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6911 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6913 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6914 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6919 arm_patch (item->jmp_code, (guchar*)code);
6921 target_code_ins = code;
6922 /* Load target address */
6923 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6924 /* Save it to the fourth slot */
6925 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6926 /* Restore registers and branch */
6927 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6929 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
6930 item->jmp_code = NULL;
6934 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
6936 /*must emit after unconditional branch*/
6937 if (vtable_target) {
6938 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
6939 item->chunk_size += 4;
6940 vtable_target = NULL;
6943 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
6944 constant_pool_starts [i] = code;
6946 code += extra_space;
6950 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6951 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6953 item->jmp_code = (guint8*)code;
6954 ARM_B_COND (code, ARMCOND_HS, 0);
6959 for (i = 0; i < count; ++i) {
6960 MonoIMTCheckItem *item = imt_entries [i];
6961 if (item->jmp_code) {
6962 if (item->check_target_idx)
6963 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6965 if (i > 0 && item->is_equals) {
6967 arminstr_t *space_start = constant_pool_starts [i];
6968 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
6969 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
6976 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
6977 mono_disassemble_code (NULL, (guint8*)start, size, buff);
6982 g_free (constant_pool_starts);
6984 mono_arch_flush_icache ((guint8*)start, size);
6985 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
6986 mono_stats.imt_trampolines_size += code - start;
6988 g_assert (DISTANCE (start, code) <= size);
6990 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
6996 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6998 return ctx->regs [reg];
7002 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7004 ctx->regs [reg] = val;
7008 * mono_arch_get_trampolines:
7010 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7014 mono_arch_get_trampolines (gboolean aot)
7016 return mono_arm_get_exception_trampolines (aot);
7020 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7027 bp = MONO_CONTEXT_GET_BP (ctx);
7028 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7030 old_value = *lr_loc;
7031 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7034 *lr_loc = new_value;
7039 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7041 * mono_arch_set_breakpoint:
7043 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7044 * The location should contain code emitted by OP_SEQ_POINT.
7047 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7050 guint32 native_offset = ip - (guint8*)ji->code_start;
7051 MonoDebugOptions *opt = mini_get_debug_options ();
7054 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7056 if (!breakpoint_tramp)
7057 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7059 g_assert (native_offset % 4 == 0);
7060 g_assert (info->bp_addrs [native_offset / 4] == 0);
7061 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7062 } else if (opt->soft_breakpoints) {
7064 ARM_BLX_REG (code, ARMREG_LR);
7065 mono_arch_flush_icache (code - 4, 4);
7067 int dreg = ARMREG_LR;
7069 /* Read from another trigger page */
7070 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7072 *(int*)code = (int)bp_trigger_page;
7074 ARM_LDR_IMM (code, dreg, dreg, 0);
7076 mono_arch_flush_icache (code - 16, 16);
7079 /* This is currently implemented by emitting an SWI instruction, which
7080 * qemu/linux seems to convert to a SIGILL.
7082 *(int*)code = (0xef << 24) | 8;
7084 mono_arch_flush_icache (code - 4, 4);
7090 * mono_arch_clear_breakpoint:
7092 * Clear the breakpoint at IP.
7095 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7097 MonoDebugOptions *opt = mini_get_debug_options ();
7102 guint32 native_offset = ip - (guint8*)ji->code_start;
7103 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7105 if (!breakpoint_tramp)
7106 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7108 g_assert (native_offset % 4 == 0);
7109 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7110 info->bp_addrs [native_offset / 4] = 0;
7111 } else if (opt->soft_breakpoints) {
7114 mono_arch_flush_icache (code - 4, 4);
7116 for (i = 0; i < 4; ++i)
7119 mono_arch_flush_icache (ip, code - ip);
7124 * mono_arch_start_single_stepping:
7126 * Start single stepping.
7129 mono_arch_start_single_stepping (void)
7131 if (ss_trigger_page)
7132 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7134 single_step_tramp = mini_get_single_step_trampoline ();
7138 * mono_arch_stop_single_stepping:
7140 * Stop single stepping.
7143 mono_arch_stop_single_stepping (void)
7145 if (ss_trigger_page)
7146 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7148 single_step_tramp = NULL;
7152 #define DBG_SIGNAL SIGBUS
7154 #define DBG_SIGNAL SIGSEGV
7158 * mono_arch_is_single_step_event:
7160 * Return whenever the machine state in SIGCTX corresponds to a single
7164 mono_arch_is_single_step_event (void *info, void *sigctx)
7166 siginfo_t *sinfo = info;
7168 if (!ss_trigger_page)
7171 /* Sometimes the address is off by 4 */
7172 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7179 * mono_arch_is_breakpoint_event:
7181 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7184 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7186 siginfo_t *sinfo = info;
7188 if (!ss_trigger_page)
7191 if (sinfo->si_signo == DBG_SIGNAL) {
7192 /* Sometimes the address is off by 4 */
7193 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7203 * mono_arch_skip_breakpoint:
7205 * See mini-amd64.c for docs.
7208 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7210 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7214 * mono_arch_skip_single_step:
7216 * See mini-amd64.c for docs.
7219 mono_arch_skip_single_step (MonoContext *ctx)
7221 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7224 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7227 * mono_arch_get_seq_point_info:
7229 * See mini-amd64.c for docs.
7232 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7237 // FIXME: Add a free function
7239 mono_domain_lock (domain);
7240 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7242 mono_domain_unlock (domain);
7245 ji = mono_jit_info_table_find (domain, (char*)code);
7248 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7250 info->ss_trigger_page = ss_trigger_page;
7251 info->bp_trigger_page = bp_trigger_page;
7252 info->ss_tramp_addr = &single_step_tramp;
7254 mono_domain_lock (domain);
7255 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7257 mono_domain_unlock (domain);
7264 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7266 ext->lmf.previous_lmf = prev_lmf;
7267 /* Mark that this is a MonoLMFExt */
7268 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7269 ext->lmf.sp = (gssize)ext;
7273 * mono_arch_set_target:
7275 * Set the target architecture the JIT backend should generate code for, in the form
7276 * of a GNU target triplet. Only used in AOT mode.
7279 mono_arch_set_target (char *mtriple)
7281 /* The GNU target triple format is not very well documented */
7282 if (strstr (mtriple, "armv7")) {
7283 v5_supported = TRUE;
7284 v6_supported = TRUE;
7285 v7_supported = TRUE;
7287 if (strstr (mtriple, "armv6")) {
7288 v5_supported = TRUE;
7289 v6_supported = TRUE;
7291 if (strstr (mtriple, "armv7s")) {
7292 v7s_supported = TRUE;
7294 if (strstr (mtriple, "armv7k")) {
7295 v7k_supported = TRUE;
7297 if (strstr (mtriple, "thumbv7s")) {
7298 v5_supported = TRUE;
7299 v6_supported = TRUE;
7300 v7_supported = TRUE;
7301 v7s_supported = TRUE;
7302 thumb_supported = TRUE;
7303 thumb2_supported = TRUE;
7305 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7306 v5_supported = TRUE;
7307 v6_supported = TRUE;
7308 thumb_supported = TRUE;
7311 if (strstr (mtriple, "gnueabi"))
7312 eabi_supported = TRUE;
7316 mono_arch_opcode_supported (int opcode)
7319 case OP_ATOMIC_ADD_I4:
7320 case OP_ATOMIC_EXCHANGE_I4:
7321 case OP_ATOMIC_CAS_I4:
7322 case OP_ATOMIC_LOAD_I1:
7323 case OP_ATOMIC_LOAD_I2:
7324 case OP_ATOMIC_LOAD_I4:
7325 case OP_ATOMIC_LOAD_U1:
7326 case OP_ATOMIC_LOAD_U2:
7327 case OP_ATOMIC_LOAD_U4:
7328 case OP_ATOMIC_STORE_I1:
7329 case OP_ATOMIC_STORE_I2:
7330 case OP_ATOMIC_STORE_I4:
7331 case OP_ATOMIC_STORE_U1:
7332 case OP_ATOMIC_STORE_U2:
7333 case OP_ATOMIC_STORE_U4:
7334 return v7_supported;
7335 case OP_ATOMIC_LOAD_R4:
7336 case OP_ATOMIC_LOAD_R8:
7337 case OP_ATOMIC_STORE_R4:
7338 case OP_ATOMIC_STORE_R8:
7339 return v7_supported && IS_VFP;
7346 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7348 return get_call_info (mp, sig);
7352 mono_arch_get_get_tls_tramp (void)
7358 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7361 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7362 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7364 *(gpointer*)code = NULL;
7366 /* Load the value from the GOT */
7367 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);