2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 #include <mono/metadata/abi-details.h>
16 #include <mono/metadata/appdomain.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/metadata/debug-helpers.h>
19 #include <mono/utils/mono-mmap.h>
20 #include <mono/utils/mono-hwcap-arm.h>
21 #include <mono/utils/mono-memory-model.h>
24 #include "mini-arm-tls.h"
28 #include "debugger-agent.h"
30 #include "mono/arch/arm/arm-vfp-codegen.h"
32 #if defined(HAVE_KW_THREAD) && defined(__linux__) \
33 || defined(TARGET_ANDROID) \
34 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
38 /* Sanity check: This makes no sense */
39 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
40 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
44 * IS_SOFT_FLOAT: Is full software floating point used?
45 * IS_HARD_FLOAT: Is full hardware floating point used?
46 * IS_VFP: Is hardware floating point with software ABI used?
48 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
49 * IS_VFP may delegate to mono_arch_is_soft_float ().
52 #if defined(ARM_FPU_VFP_HARD)
53 #define IS_SOFT_FLOAT (FALSE)
54 #define IS_HARD_FLOAT (TRUE)
56 #elif defined(ARM_FPU_NONE)
57 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
58 #define IS_HARD_FLOAT (FALSE)
59 #define IS_VFP (!mono_arch_is_soft_float ())
61 #define IS_SOFT_FLOAT (FALSE)
62 #define IS_HARD_FLOAT (FALSE)
66 #define THUNK_SIZE (3 * 4)
68 #ifdef __native_client_codegen__
69 const guint kNaClAlignment = kNaClAlignmentARM;
70 const guint kNaClAlignmentMask = kNaClAlignmentMaskARM;
71 gint8 nacl_align_byte = -1; /* 0xff */
74 mono_arch_nacl_pad (guint8 *code, int pad)
76 /* Not yet properly implemented. */
77 g_assert_not_reached ();
82 mono_arch_nacl_skip_nops (guint8 *code)
84 /* Not yet properly implemented. */
85 g_assert_not_reached ();
89 #endif /* __native_client_codegen__ */
91 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
94 void sys_icache_invalidate (void *start, size_t len);
97 /* This mutex protects architecture specific caches */
98 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
99 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
100 static mono_mutex_t mini_arch_mutex;
102 static gboolean v5_supported = FALSE;
103 static gboolean v6_supported = FALSE;
104 static gboolean v7_supported = FALSE;
105 static gboolean v7s_supported = FALSE;
106 static gboolean v7k_supported = FALSE;
107 static gboolean thumb_supported = FALSE;
108 static gboolean thumb2_supported = FALSE;
110 * Whenever to use the ARM EABI
112 static gboolean eabi_supported = FALSE;
115 * Whenever to use the iphone ABI extensions:
116 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
117 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
118 * This is required for debugging/profiling tools to work, but it has some overhead so it should
119 * only be turned on in debug builds.
121 static gboolean iphone_abi = FALSE;
124 * The FPU we are generating code for. This is NOT runtime configurable right now,
125 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
127 static MonoArmFPU arm_fpu;
129 #if defined(ARM_FPU_VFP_HARD)
131 * On armhf, d0-d7 are used for argument passing and d8-d15
132 * must be preserved across calls, which leaves us no room
133 * for scratch registers. So we use d14-d15 but back up their
134 * previous contents to a stack slot before using them - see
135 * mono_arm_emit_vfp_scratch_save/_restore ().
137 static int vfp_scratch1 = ARM_VFP_D14;
138 static int vfp_scratch2 = ARM_VFP_D15;
141 * On armel, d0-d7 do not need to be preserved, so we can
142 * freely make use of them as scratch registers.
144 static int vfp_scratch1 = ARM_VFP_D0;
145 static int vfp_scratch2 = ARM_VFP_D1;
150 static gpointer single_step_tramp, breakpoint_tramp;
153 * The code generated for sequence points reads from this location, which is
154 * made read-only when single stepping is enabled.
156 static gpointer ss_trigger_page;
158 /* Enabled breakpoints read from this trigger page */
159 static gpointer bp_trigger_page;
163 * floating point support: on ARM it is a mess, there are at least 3
164 * different setups, each of which binary incompat with the other.
165 * 1) FPA: old and ugly, but unfortunately what current distros use
166 * the double binary format has the two words swapped. 8 double registers.
167 * Implemented usually by kernel emulation.
168 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
169 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
170 * 3) VFP: the new and actually sensible and useful FP support. Implemented
171 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
173 * We do not care about FPA. We will support soft float and VFP.
175 int mono_exc_esp_offset = 0;
177 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
178 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
179 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
181 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
182 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
183 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
185 //#define DEBUG_IMT 0
188 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
192 mono_arch_regname (int reg)
194 static const char * rnames[] = {
195 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
196 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
197 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
200 if (reg >= 0 && reg < 16)
206 mono_arch_fregname (int reg)
208 static const char * rnames[] = {
209 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
210 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
211 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
212 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
213 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
214 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
217 if (reg >= 0 && reg < 32)
225 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
227 int imm8, rot_amount;
228 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
229 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
233 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
234 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
236 code = mono_arm_emit_load_imm (code, dreg, imm);
237 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
242 /* If dreg == sreg, this clobbers IP */
244 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
246 int imm8, rot_amount;
247 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
248 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
252 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
253 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
255 code = mono_arm_emit_load_imm (code, dreg, imm);
256 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
262 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
264 /* we can use r0-r3, since this is called only for incoming args on the stack */
265 if (size > sizeof (gpointer) * 4) {
267 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
268 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
269 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
270 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
271 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
272 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
273 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
274 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
275 ARM_B_COND (code, ARMCOND_NE, 0);
276 arm_patch (code - 4, start_loop);
279 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
280 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
282 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
283 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
289 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
290 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
291 doffset = soffset = 0;
293 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
294 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
300 g_assert (size == 0);
305 emit_call_reg (guint8 *code, int reg)
308 ARM_BLX_REG (code, reg);
310 #ifdef USE_JUMP_TABLES
311 g_assert_not_reached ();
313 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
317 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
323 emit_call_seq (MonoCompile *cfg, guint8 *code)
325 #ifdef USE_JUMP_TABLES
326 code = mono_arm_patchable_bl (code, ARMCOND_AL);
328 if (cfg->method->dynamic) {
329 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
331 *(gpointer*)code = NULL;
333 code = emit_call_reg (code, ARMREG_IP);
337 cfg->thunk_area += THUNK_SIZE;
343 mono_arm_patchable_b (guint8 *code, int cond)
345 #ifdef USE_JUMP_TABLES
348 jte = mono_jumptable_add_entry ();
349 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
350 ARM_BX_COND (code, cond, ARMREG_IP);
352 ARM_B_COND (code, cond, 0);
358 mono_arm_patchable_bl (guint8 *code, int cond)
360 #ifdef USE_JUMP_TABLES
363 jte = mono_jumptable_add_entry ();
364 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
365 ARM_BLX_REG_COND (code, cond, ARMREG_IP);
367 ARM_BL_COND (code, cond, 0);
372 #ifdef USE_JUMP_TABLES
374 mono_arm_load_jumptable_entry_addr (guint8 *code, gpointer *jte, ARMReg reg)
376 ARM_MOVW_REG_IMM (code, reg, GPOINTER_TO_UINT(jte) & 0xffff);
377 ARM_MOVT_REG_IMM (code, reg, (GPOINTER_TO_UINT(jte) >> 16) & 0xffff);
382 mono_arm_load_jumptable_entry (guint8 *code, gpointer* jte, ARMReg reg)
384 code = mono_arm_load_jumptable_entry_addr (code, jte, reg);
385 ARM_LDR_IMM (code, reg, reg, 0);
391 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
394 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
395 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
397 code = emit_call_seq (cfg, code);
398 if (dreg != ARMREG_R0)
399 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
401 g_assert_not_reached ();
407 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
410 if (tls_offset_reg != ARMREG_R0)
411 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
412 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
414 code = emit_call_seq (cfg, code);
415 if (dreg != ARMREG_R0)
416 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
418 g_assert_not_reached ();
424 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
427 if (sreg != ARMREG_R1)
428 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
429 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
430 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
432 code = emit_call_seq (cfg, code);
434 g_assert_not_reached ();
440 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
443 /* Get sreg in R1 and tls_offset_reg in R0 */
444 if (tls_offset_reg == ARMREG_R1) {
445 if (sreg == ARMREG_R0) {
446 /* swap sreg and tls_offset_reg */
447 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
448 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
449 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
451 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
452 if (sreg != ARMREG_R1)
453 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
456 if (sreg != ARMREG_R1)
457 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
458 if (tls_offset_reg != ARMREG_R0)
459 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
461 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
463 code = emit_call_seq (cfg, code);
465 g_assert_not_reached ();
473 * Emit code to push an LMF structure on the LMF stack.
474 * On arm, this is intermixed with the initialization of other fields of the structure.
477 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
479 gboolean get_lmf_fast = FALSE;
482 if (mono_arm_have_tls_get ()) {
484 if (cfg->compile_aot) {
486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
487 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
489 *(gpointer*)code = NULL;
491 /* Load the value from the GOT */
492 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
493 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
495 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
496 g_assert (lmf_addr_tls_offset != -1);
497 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
503 (gpointer)"mono_get_lmf_addr");
504 code = emit_call_seq (cfg, code);
506 /* we build the MonoLMF structure on the stack - see mini-arm.h */
507 /* lmf_offset is the offset from the previous stack pointer,
508 * alloc_size is the total stack space allocated, so the offset
509 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
510 * The pointer to the struct is put in r1 (new_lmf).
511 * ip is used as scratch
512 * The callee-saved registers are already in the MonoLMF structure
514 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
515 /* r0 is the result from mono_get_lmf_addr () */
516 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
517 /* new_lmf->previous_lmf = *lmf_addr */
518 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
519 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
520 /* *(lmf_addr) = r1 */
521 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
522 /* Skip method (only needed for trampoline LMF frames) */
523 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
524 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
525 /* save the current IP */
526 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
527 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
529 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
530 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
541 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
545 g_assert (!cfg->r4fp);
547 for (list = inst->float_args; list; list = list->next) {
548 FloatArgData *fad = list->data;
549 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
550 gboolean imm = arm_is_fpimm8 (var->inst_offset);
552 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
558 if (*offset + *max_len > cfg->code_size) {
559 cfg->code_size += *max_len;
560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
562 code = cfg->native_code + *offset;
566 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
567 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
569 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
571 *offset = code - cfg->native_code;
578 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
582 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
584 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
587 if (!arm_is_fpimm8 (inst->inst_offset)) {
588 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
589 ARM_FSTD (code, reg, ARMREG_LR, 0);
591 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
598 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
602 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
604 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
607 if (!arm_is_fpimm8 (inst->inst_offset)) {
608 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
609 ARM_FLDD (code, reg, ARMREG_LR, 0);
611 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
620 * Emit code to pop an LMF structure from the LMF stack.
623 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
627 if (lmf_offset < 32) {
628 basereg = cfg->frame_reg;
633 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
636 /* ip = previous_lmf */
637 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
639 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
640 /* *(lmf_addr) = previous_lmf */
641 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
646 #endif /* #ifndef DISABLE_JIT */
648 #ifndef MONO_CROSS_COMPILE
650 mono_arm_have_fast_tls (void)
652 if (mini_get_debug_options ()->arm_use_fallback_tls)
654 #if (defined(HAVE_KW_THREAD) && defined(__linux__)) \
655 || defined(TARGET_ANDROID)
656 guint32* kuser_get_tls = (void*)0xffff0fe0;
657 guint32 expected [] = {0xee1d0f70, 0xe12fff1e};
659 /* Expecting mrc + bx lr in the kuser_get_tls kernel helper */
660 return memcmp (kuser_get_tls, expected, 8) == 0;
661 #elif defined(TARGET_IOS)
662 guint32 expected [] = {0x1f70ee1d, 0x0103f021, 0x0020f851, 0xbf004770};
663 /* Discard thumb bit */
664 guint32* pthread_getspecific_addr = (guint32*) ((guint32)pthread_getspecific & 0xfffffffe);
665 return memcmp ((void*)pthread_getspecific_addr, expected, 16) == 0;
673 * mono_arm_have_tls_get:
675 * Returns whether we have tls access implemented on the current
679 mono_arm_have_tls_get (void)
690 * mono_arch_get_argument_info:
691 * @csig: a method signature
692 * @param_count: the number of parameters to consider
693 * @arg_info: an array to store the result infos
695 * Gathers information on parameters such as size, alignment and
696 * padding. arg_info should be large enought to hold param_count + 1 entries.
698 * Returns the size of the activation frame.
701 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
703 int k, frame_size = 0;
704 guint32 size, align, pad;
708 t = mini_get_underlying_type (csig->ret);
709 if (MONO_TYPE_ISSTRUCT (t)) {
710 frame_size += sizeof (gpointer);
714 arg_info [0].offset = offset;
717 frame_size += sizeof (gpointer);
721 arg_info [0].size = frame_size;
723 for (k = 0; k < param_count; k++) {
724 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
726 /* ignore alignment for now */
729 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
730 arg_info [k].pad = pad;
732 arg_info [k + 1].pad = 0;
733 arg_info [k + 1].size = size;
735 arg_info [k + 1].offset = offset;
739 align = MONO_ARCH_FRAME_ALIGNMENT;
740 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
741 arg_info [k].pad = pad;
746 #define MAX_ARCH_DELEGATE_PARAMS 3
749 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
751 guint8 *code, *start;
752 GSList *unwind_ops = mono_arch_get_cie_program ();
755 start = code = mono_global_codeman_reserve (12);
757 /* Replace the this argument with the target */
758 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
759 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
760 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
762 g_assert ((code - start) <= 12);
764 mono_arch_flush_icache (start, 12);
768 size = 8 + param_count * 4;
769 start = code = mono_global_codeman_reserve (size);
771 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
772 /* slide down the arguments */
773 for (i = 0; i < param_count; ++i) {
774 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
776 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
778 g_assert ((code - start) <= size);
780 mono_arch_flush_icache (start, size);
784 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
786 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
787 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
791 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
797 * mono_arch_get_delegate_invoke_impls:
799 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
803 mono_arch_get_delegate_invoke_impls (void)
809 get_delegate_invoke_impl (&info, TRUE, 0);
810 res = g_slist_prepend (res, info);
812 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
813 get_delegate_invoke_impl (&info, FALSE, i);
814 res = g_slist_prepend (res, info);
821 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
823 guint8 *code, *start;
826 /* FIXME: Support more cases */
827 sig_ret = mini_get_underlying_type (sig->ret);
828 if (MONO_TYPE_ISSTRUCT (sig_ret))
832 static guint8* cached = NULL;
833 mono_mini_arch_lock ();
835 mono_mini_arch_unlock ();
840 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
843 start = get_delegate_invoke_impl (&info, TRUE, 0);
844 mono_tramp_info_register (info, NULL);
847 mono_mini_arch_unlock ();
850 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
853 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
855 for (i = 0; i < sig->param_count; ++i)
856 if (!mono_is_regsize_var (sig->params [i]))
859 mono_mini_arch_lock ();
860 code = cache [sig->param_count];
862 mono_mini_arch_unlock ();
867 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
868 start = mono_aot_get_trampoline (name);
872 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
873 mono_tramp_info_register (info, NULL);
875 cache [sig->param_count] = start;
876 mono_mini_arch_unlock ();
884 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
890 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
892 return (gpointer)regs [ARMREG_R0];
896 * Initialize the cpu to execute managed code.
899 mono_arch_cpu_init (void)
901 i8_align = MONO_ABI_ALIGNOF (gint64);
902 #ifdef MONO_CROSS_COMPILE
903 /* Need to set the alignment of i8 since it can different on the target */
904 #ifdef TARGET_ANDROID
906 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
912 * Initialize architecture specific code.
915 mono_arch_init (void)
917 const char *cpu_arch;
919 mono_os_mutex_init_recursive (&mini_arch_mutex);
920 if (mini_get_debug_options ()->soft_breakpoints) {
921 breakpoint_tramp = mini_get_breakpoint_trampoline ();
923 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
924 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
925 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
928 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
929 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
930 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
931 #if defined(ENABLE_GSHAREDVT)
932 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
934 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
936 #if defined(__ARM_EABI__)
937 eabi_supported = TRUE;
940 #if defined(ARM_FPU_VFP_HARD)
941 arm_fpu = MONO_ARM_FPU_VFP_HARD;
943 arm_fpu = MONO_ARM_FPU_VFP;
945 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
947 * If we're compiling with a soft float fallback and it
948 * turns out that no VFP unit is available, we need to
949 * switch to soft float. We don't do this for iOS, since
950 * iOS devices always have a VFP unit.
952 if (!mono_hwcap_arm_has_vfp)
953 arm_fpu = MONO_ARM_FPU_NONE;
956 * This environment variable can be useful in testing
957 * environments to make sure the soft float fallback
958 * works. Most ARM devices have VFP units these days, so
959 * normally soft float code would not be exercised much.
961 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
963 if (soft && !strncmp (soft, "1", 1))
964 arm_fpu = MONO_ARM_FPU_NONE;
968 v5_supported = mono_hwcap_arm_is_v5;
969 v6_supported = mono_hwcap_arm_is_v6;
970 v7_supported = mono_hwcap_arm_is_v7;
972 #if defined(__APPLE__)
973 /* iOS is special-cased here because we don't yet
974 have a way to properly detect CPU features on it. */
975 thumb_supported = TRUE;
978 thumb_supported = mono_hwcap_arm_has_thumb;
979 thumb2_supported = mono_hwcap_arm_has_thumb2;
982 /* Format: armv(5|6|7[s])[-thumb[2]] */
983 cpu_arch = g_getenv ("MONO_CPU_ARCH");
985 /* Do this here so it overrides any detection. */
987 if (strncmp (cpu_arch, "armv", 4) == 0) {
988 v5_supported = cpu_arch [4] >= '5';
989 v6_supported = cpu_arch [4] >= '6';
990 v7_supported = cpu_arch [4] >= '7';
991 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
992 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
995 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
996 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
1001 * Cleanup architecture specific code.
1004 mono_arch_cleanup (void)
1009 * This function returns the optimizations supported on this cpu.
1012 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1014 /* no arm-specific optimizations yet */
1020 * This function test for all SIMD functions supported.
1022 * Returns a bitmask corresponding to all supported versions.
1026 mono_arch_cpu_enumerate_simd_versions (void)
1028 /* SIMD is currently unimplemented */
1036 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1038 if (v7s_supported || v7k_supported) {
1052 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
1054 mono_arch_is_soft_float (void)
1056 return arm_fpu == MONO_ARM_FPU_NONE;
1061 mono_arm_is_hard_float (void)
1063 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
1067 is_regsize_var (MonoType *t)
1071 t = mini_get_underlying_type (t);
1078 case MONO_TYPE_FNPTR:
1080 case MONO_TYPE_OBJECT:
1081 case MONO_TYPE_STRING:
1082 case MONO_TYPE_CLASS:
1083 case MONO_TYPE_SZARRAY:
1084 case MONO_TYPE_ARRAY:
1086 case MONO_TYPE_GENERICINST:
1087 if (!mono_type_generic_inst_is_valuetype (t))
1090 case MONO_TYPE_VALUETYPE:
1097 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1102 for (i = 0; i < cfg->num_varinfo; i++) {
1103 MonoInst *ins = cfg->varinfo [i];
1104 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1107 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1110 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1113 /* we can only allocate 32 bit values */
1114 if (is_regsize_var (ins->inst_vtype)) {
1115 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1116 g_assert (i == vmv->idx);
1117 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1125 mono_arch_get_global_int_regs (MonoCompile *cfg)
1129 mono_arch_compute_omit_fp (cfg);
1132 * FIXME: Interface calls might go through a static rgctx trampoline which
1133 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1136 if (cfg->flags & MONO_CFG_HAS_CALLS)
1137 cfg->uses_rgctx_reg = TRUE;
1139 if (cfg->arch.omit_fp)
1140 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1141 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1142 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1143 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1145 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1146 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1148 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1149 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1150 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1151 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1152 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1153 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1159 * mono_arch_regalloc_cost:
1161 * Return the cost, in number of memory references, of the action of
1162 * allocating the variable VMV into a register during global register
1166 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1172 #endif /* #ifndef DISABLE_JIT */
1175 mono_arch_flush_icache (guint8 *code, gint size)
1177 #if defined(MONO_CROSS_COMPILE) || defined(__native_client__)
1178 // For Native Client we don't have to flush i-cache here,
1179 // as it's being done by dyncode interface.
1181 sys_icache_invalidate (code, size);
1183 __builtin___clear_cache (code, code + size);
1189 /* Passed/returned in an ireg */
1191 /* Passed/returned in a pair of iregs */
1193 /* Passed on the stack */
1195 /* First word in r3, second word on the stack */
1197 /* FP value passed in either an ireg or a vfp reg */
1200 RegTypeStructByAddr,
1201 /* gsharedvt argument passed by addr in greg */
1202 RegTypeGSharedVtInReg,
1203 /* gsharedvt argument passed by addr on stack */
1204 RegTypeGSharedVtOnStack,
1210 guint16 vtsize; /* in param area */
1218 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
1223 guint32 stack_usage;
1224 /* The index of the vret arg in the argument list for RegTypeStructByAddr */
1234 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1237 if (*gr > ARMREG_R3) {
1239 ainfo->offset = *stack_size;
1240 ainfo->reg = ARMREG_SP; /* in the caller */
1241 ainfo->storage = RegTypeBase;
1244 ainfo->storage = RegTypeGeneral;
1251 split = i8_align == 4;
1256 if (*gr == ARMREG_R3 && split) {
1257 /* first word in r3 and the second on the stack */
1258 ainfo->offset = *stack_size;
1259 ainfo->reg = ARMREG_SP; /* in the caller */
1260 ainfo->storage = RegTypeBaseGen;
1262 } else if (*gr >= ARMREG_R3) {
1263 if (eabi_supported) {
1264 /* darwin aligns longs to 4 byte only */
1265 if (i8_align == 8) {
1270 ainfo->offset = *stack_size;
1271 ainfo->reg = ARMREG_SP; /* in the caller */
1272 ainfo->storage = RegTypeBase;
1275 if (eabi_supported) {
1276 if (i8_align == 8 && ((*gr) & 1))
1279 ainfo->storage = RegTypeIRegPair;
1288 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1291 * If we're calling a function like this:
1293 * void foo(float a, double b, float c)
1295 * We pass a in s0 and b in d1. That leaves us
1296 * with s1 being unused. The armhf ABI recognizes
1297 * this and requires register assignment to then
1298 * use that for the next single-precision arg,
1299 * i.e. c in this example. So float_spare either
1300 * tells us which reg to use for the next single-
1301 * precision arg, or it's -1, meaning use *fpr.
1303 * Note that even though most of the JIT speaks
1304 * double-precision, fpr represents single-
1305 * precision registers.
1307 * See parts 5.5 and 6.1.2 of the AAPCS for how
1311 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1312 ainfo->storage = RegTypeFP;
1316 * If we're passing a double-precision value
1317 * and *fpr is odd (e.g. it's s1, s3, ...)
1318 * we need to use the next even register. So
1319 * we mark the current *fpr as a spare that
1320 * can be used for the next single-precision
1324 *float_spare = *fpr;
1329 * At this point, we have an even register
1330 * so we assign that and move along.
1334 } else if (*float_spare >= 0) {
1336 * We're passing a single-precision value
1337 * and it looks like a spare single-
1338 * precision register is available. Let's
1342 ainfo->reg = *float_spare;
1346 * If we hit this branch, we're passing a
1347 * single-precision value and we can simply
1348 * use the next available register.
1356 * We've exhausted available floating point
1357 * regs, so pass the rest on the stack.
1365 ainfo->offset = *stack_size;
1366 ainfo->reg = ARMREG_SP;
1367 ainfo->storage = RegTypeBase;
1374 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1378 MonoClassField *field;
1379 MonoType *ftype, *prev_ftype = NULL;
1382 klass = mono_class_from_mono_type (t);
1384 while ((field = mono_class_get_fields (klass, &iter))) {
1385 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1387 ftype = mono_field_get_type (field);
1388 ftype = mini_get_underlying_type (ftype);
1390 if (MONO_TYPE_ISSTRUCT (ftype)) {
1391 int nested_nfields, nested_esize;
1393 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1395 if (nested_esize == 4)
1396 ftype = &mono_defaults.single_class->byval_arg;
1398 ftype = &mono_defaults.double_class->byval_arg;
1399 if (prev_ftype && prev_ftype->type != ftype->type)
1402 nfields += nested_nfields;
1404 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1406 if (prev_ftype && prev_ftype->type != ftype->type)
1412 if (nfields == 0 || nfields > 4)
1414 *out_nfields = nfields;
1415 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1420 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1422 guint i, gr, fpr, pstart;
1424 int n = sig->hasthis + sig->param_count;
1428 guint32 stack_size = 0;
1430 gboolean is_pinvoke = sig->pinvoke;
1431 gboolean vtype_retaddr = FALSE;
1434 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1436 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1443 t = mini_get_underlying_type (sig->ret);
1454 case MONO_TYPE_FNPTR:
1455 case MONO_TYPE_CLASS:
1456 case MONO_TYPE_OBJECT:
1457 case MONO_TYPE_SZARRAY:
1458 case MONO_TYPE_ARRAY:
1459 case MONO_TYPE_STRING:
1460 cinfo->ret.storage = RegTypeGeneral;
1461 cinfo->ret.reg = ARMREG_R0;
1465 cinfo->ret.storage = RegTypeIRegPair;
1466 cinfo->ret.reg = ARMREG_R0;
1470 cinfo->ret.storage = RegTypeFP;
1472 if (t->type == MONO_TYPE_R4)
1473 cinfo->ret.size = 4;
1475 cinfo->ret.size = 8;
1477 if (IS_HARD_FLOAT) {
1478 cinfo->ret.reg = ARM_VFP_F0;
1480 cinfo->ret.reg = ARMREG_R0;
1483 case MONO_TYPE_GENERICINST:
1484 if (!mono_type_generic_inst_is_valuetype (t)) {
1485 cinfo->ret.storage = RegTypeGeneral;
1486 cinfo->ret.reg = ARMREG_R0;
1489 if (mini_is_gsharedvt_variable_type (t)) {
1490 cinfo->ret.storage = RegTypeStructByAddr;
1494 case MONO_TYPE_VALUETYPE:
1495 case MONO_TYPE_TYPEDBYREF:
1496 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1497 cinfo->ret.storage = RegTypeHFA;
1499 cinfo->ret.nregs = nfields;
1500 cinfo->ret.esize = esize;
1502 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (t), &align) <= sizeof (gpointer))
1503 cinfo->ret.storage = RegTypeStructByVal;
1505 cinfo->ret.storage = RegTypeStructByAddr;
1509 case MONO_TYPE_MVAR:
1510 g_assert (mini_is_gsharedvt_type (t));
1511 cinfo->ret.storage = RegTypeStructByAddr;
1513 case MONO_TYPE_VOID:
1516 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1519 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1524 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1525 * the first argument, allowing 'this' to be always passed in the first arg reg.
1526 * Also do this if the first argument is a reference type, since virtual calls
1527 * are sometimes made using calli without sig->hasthis set, like in the delegate
1530 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1532 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1534 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1538 cinfo->ret.reg = gr;
1540 cinfo->vret_arg_index = 1;
1544 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1547 if (vtype_retaddr) {
1548 cinfo->ret.reg = gr;
1553 DEBUG(g_print("params: %d\n", sig->param_count));
1554 for (i = pstart; i < sig->param_count; ++i) {
1555 ArgInfo *ainfo = &cinfo->args [n];
1557 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1558 /* Prevent implicit arguments and sig_cookie from
1559 being passed in registers */
1562 /* Emit the signature cookie just before the implicit arguments */
1563 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1565 DEBUG(g_print("param %d: ", i));
1566 if (sig->params [i]->byref) {
1567 DEBUG(g_print("byref\n"));
1568 add_general (&gr, &stack_size, ainfo, TRUE);
1572 t = mini_get_underlying_type (sig->params [i]);
1576 cinfo->args [n].size = 1;
1577 add_general (&gr, &stack_size, ainfo, TRUE);
1581 cinfo->args [n].size = 2;
1582 add_general (&gr, &stack_size, ainfo, TRUE);
1586 cinfo->args [n].size = 4;
1587 add_general (&gr, &stack_size, ainfo, TRUE);
1592 case MONO_TYPE_FNPTR:
1593 case MONO_TYPE_CLASS:
1594 case MONO_TYPE_OBJECT:
1595 case MONO_TYPE_STRING:
1596 case MONO_TYPE_SZARRAY:
1597 case MONO_TYPE_ARRAY:
1598 cinfo->args [n].size = sizeof (gpointer);
1599 add_general (&gr, &stack_size, ainfo, TRUE);
1601 case MONO_TYPE_GENERICINST:
1602 if (!mono_type_generic_inst_is_valuetype (t)) {
1603 cinfo->args [n].size = sizeof (gpointer);
1604 add_general (&gr, &stack_size, ainfo, TRUE);
1607 if (mini_is_gsharedvt_variable_type (t)) {
1608 /* gsharedvt arguments are passed by ref */
1609 g_assert (mini_is_gsharedvt_type (t));
1610 add_general (&gr, &stack_size, ainfo, TRUE);
1611 switch (ainfo->storage) {
1612 case RegTypeGeneral:
1613 ainfo->storage = RegTypeGSharedVtInReg;
1616 ainfo->storage = RegTypeGSharedVtOnStack;
1619 g_assert_not_reached ();
1624 case MONO_TYPE_TYPEDBYREF:
1625 case MONO_TYPE_VALUETYPE: {
1628 int nwords, nfields, esize;
1631 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1632 if (fpr + nfields < ARM_VFP_F16) {
1633 ainfo->storage = RegTypeHFA;
1635 ainfo->nregs = nfields;
1636 ainfo->esize = esize;
1647 if (t->type == MONO_TYPE_TYPEDBYREF) {
1648 size = sizeof (MonoTypedRef);
1649 align = sizeof (gpointer);
1651 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1653 size = mono_class_native_size (klass, &align);
1655 size = mini_type_stack_size_full (t, &align, FALSE);
1657 DEBUG(g_print ("load %d bytes struct\n", size));
1660 align_size += (sizeof (gpointer) - 1);
1661 align_size &= ~(sizeof (gpointer) - 1);
1662 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1663 ainfo->storage = RegTypeStructByVal;
1664 ainfo->struct_size = size;
1665 /* FIXME: align stack_size if needed */
1666 if (eabi_supported) {
1667 if (align >= 8 && (gr & 1))
1670 if (gr > ARMREG_R3) {
1672 ainfo->vtsize = nwords;
1674 int rest = ARMREG_R3 - gr + 1;
1675 int n_in_regs = rest >= nwords? nwords: rest;
1677 ainfo->size = n_in_regs;
1678 ainfo->vtsize = nwords - n_in_regs;
1681 nwords -= n_in_regs;
1683 if (sig->call_convention == MONO_CALL_VARARG)
1684 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1685 stack_size = ALIGN_TO (stack_size, align);
1686 ainfo->offset = stack_size;
1687 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1688 stack_size += nwords * sizeof (gpointer);
1694 add_general (&gr, &stack_size, ainfo, FALSE);
1700 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1702 add_general (&gr, &stack_size, ainfo, TRUE);
1708 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1710 add_general (&gr, &stack_size, ainfo, FALSE);
1713 case MONO_TYPE_MVAR:
1714 /* gsharedvt arguments are passed by ref */
1715 g_assert (mini_is_gsharedvt_type (t));
1716 add_general (&gr, &stack_size, ainfo, TRUE);
1717 switch (ainfo->storage) {
1718 case RegTypeGeneral:
1719 ainfo->storage = RegTypeGSharedVtInReg;
1722 ainfo->storage = RegTypeGSharedVtOnStack;
1725 g_assert_not_reached ();
1729 g_error ("Can't handle 0x%x", sig->params [i]->type);
1734 /* Handle the case where there are no implicit arguments */
1735 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1736 /* Prevent implicit arguments and sig_cookie from
1737 being passed in registers */
1740 /* Emit the signature cookie just before the implicit arguments */
1741 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1744 /* align stack size to 8 */
1745 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1746 stack_size = (stack_size + 7) & ~7;
1748 cinfo->stack_usage = stack_size;
1754 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1756 MonoType *callee_ret;
1760 c1 = get_call_info (NULL, caller_sig);
1761 c2 = get_call_info (NULL, callee_sig);
1764 * Tail calls with more callee stack usage than the caller cannot be supported, since
1765 * the extra stack space would be left on the stack after the tail call.
1767 res = c1->stack_usage >= c2->stack_usage;
1768 callee_ret = mini_get_underlying_type (callee_sig->ret);
1769 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1770 /* An address on the callee's stack is passed as the first argument */
1773 if (c2->stack_usage > 16 * 4)
1785 debug_omit_fp (void)
1788 return mono_debug_count ();
1795 * mono_arch_compute_omit_fp:
1797 * Determine whenever the frame pointer can be eliminated.
1800 mono_arch_compute_omit_fp (MonoCompile *cfg)
1802 MonoMethodSignature *sig;
1803 MonoMethodHeader *header;
1807 if (cfg->arch.omit_fp_computed)
1810 header = cfg->header;
1812 sig = mono_method_signature (cfg->method);
1814 if (!cfg->arch.cinfo)
1815 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1816 cinfo = cfg->arch.cinfo;
1819 * FIXME: Remove some of the restrictions.
1821 cfg->arch.omit_fp = TRUE;
1822 cfg->arch.omit_fp_computed = TRUE;
1824 if (cfg->disable_omit_fp)
1825 cfg->arch.omit_fp = FALSE;
1826 if (!debug_omit_fp ())
1827 cfg->arch.omit_fp = FALSE;
1829 if (cfg->method->save_lmf)
1830 cfg->arch.omit_fp = FALSE;
1832 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1833 cfg->arch.omit_fp = FALSE;
1834 if (header->num_clauses)
1835 cfg->arch.omit_fp = FALSE;
1836 if (cfg->param_area)
1837 cfg->arch.omit_fp = FALSE;
1838 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1839 cfg->arch.omit_fp = FALSE;
1840 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1841 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1842 cfg->arch.omit_fp = FALSE;
1843 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1844 ArgInfo *ainfo = &cinfo->args [i];
1846 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1848 * The stack offset can only be determined when the frame
1851 cfg->arch.omit_fp = FALSE;
1856 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1857 MonoInst *ins = cfg->varinfo [i];
1860 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1865 * Set var information according to the calling convention. arm version.
1866 * The locals var stuff should most likely be split in another method.
1869 mono_arch_allocate_vars (MonoCompile *cfg)
1871 MonoMethodSignature *sig;
1872 MonoMethodHeader *header;
1875 int i, offset, size, align, curinst;
1880 sig = mono_method_signature (cfg->method);
1882 if (!cfg->arch.cinfo)
1883 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1884 cinfo = cfg->arch.cinfo;
1885 sig_ret = mini_get_underlying_type (sig->ret);
1887 mono_arch_compute_omit_fp (cfg);
1889 if (cfg->arch.omit_fp)
1890 cfg->frame_reg = ARMREG_SP;
1892 cfg->frame_reg = ARMREG_FP;
1894 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1896 /* allow room for the vararg method args: void* and long/double */
1897 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1898 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1900 header = cfg->header;
1902 /* See mono_arch_get_global_int_regs () */
1903 if (cfg->flags & MONO_CFG_HAS_CALLS)
1904 cfg->uses_rgctx_reg = TRUE;
1906 if (cfg->frame_reg != ARMREG_SP)
1907 cfg->used_int_regs |= 1 << cfg->frame_reg;
1909 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1910 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1911 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1915 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1916 if (sig_ret->type != MONO_TYPE_VOID) {
1917 cfg->ret->opcode = OP_REGVAR;
1918 cfg->ret->inst_c0 = ARMREG_R0;
1921 /* local vars are at a positive offset from the stack pointer */
1923 * also note that if the function uses alloca, we use FP
1924 * to point at the local variables.
1926 offset = 0; /* linkage area */
1927 /* align the offset to 16 bytes: not sure this is needed here */
1929 //offset &= ~(8 - 1);
1931 /* add parameter area size for called functions */
1932 offset += cfg->param_area;
1935 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1938 /* allow room to save the return value */
1939 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1942 switch (cinfo->ret.storage) {
1943 case RegTypeStructByVal:
1944 cfg->ret->opcode = OP_REGOFFSET;
1945 cfg->ret->inst_basereg = cfg->frame_reg;
1946 offset += sizeof (gpointer) - 1;
1947 offset &= ~(sizeof (gpointer) - 1);
1948 cfg->ret->inst_offset = - offset;
1949 offset += sizeof(gpointer);
1952 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1953 offset = ALIGN_TO (offset, 8);
1954 cfg->ret->opcode = OP_REGOFFSET;
1955 cfg->ret->inst_basereg = cfg->frame_reg;
1956 cfg->ret->inst_offset = offset;
1960 case RegTypeStructByAddr:
1961 ins = cfg->vret_addr;
1962 offset += sizeof(gpointer) - 1;
1963 offset &= ~(sizeof(gpointer) - 1);
1964 ins->inst_offset = offset;
1965 ins->opcode = OP_REGOFFSET;
1966 ins->inst_basereg = cfg->frame_reg;
1967 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1968 g_print ("vret_addr =");
1969 mono_print_ins (cfg->vret_addr);
1971 offset += sizeof(gpointer);
1977 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1978 if (cfg->arch.seq_point_info_var) {
1981 ins = cfg->arch.seq_point_info_var;
1985 offset += align - 1;
1986 offset &= ~(align - 1);
1987 ins->opcode = OP_REGOFFSET;
1988 ins->inst_basereg = cfg->frame_reg;
1989 ins->inst_offset = offset;
1992 ins = cfg->arch.ss_trigger_page_var;
1995 offset += align - 1;
1996 offset &= ~(align - 1);
1997 ins->opcode = OP_REGOFFSET;
1998 ins->inst_basereg = cfg->frame_reg;
1999 ins->inst_offset = offset;
2003 if (cfg->arch.seq_point_ss_method_var) {
2006 ins = cfg->arch.seq_point_ss_method_var;
2009 offset += align - 1;
2010 offset &= ~(align - 1);
2011 ins->opcode = OP_REGOFFSET;
2012 ins->inst_basereg = cfg->frame_reg;
2013 ins->inst_offset = offset;
2016 ins = cfg->arch.seq_point_bp_method_var;
2019 offset += align - 1;
2020 offset &= ~(align - 1);
2021 ins->opcode = OP_REGOFFSET;
2022 ins->inst_basereg = cfg->frame_reg;
2023 ins->inst_offset = offset;
2027 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
2028 /* Allocate a temporary used by the atomic ops */
2032 /* Allocate a local slot to hold the sig cookie address */
2033 offset += align - 1;
2034 offset &= ~(align - 1);
2035 cfg->arch.atomic_tmp_offset = offset;
2038 cfg->arch.atomic_tmp_offset = -1;
2041 cfg->locals_min_stack_offset = offset;
2043 curinst = cfg->locals_start;
2044 for (i = curinst; i < cfg->num_varinfo; ++i) {
2047 ins = cfg->varinfo [i];
2048 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
2051 t = ins->inst_vtype;
2052 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
2055 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
2056 * pinvoke wrappers when they call functions returning structure */
2057 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
2058 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
2062 size = mono_type_size (t, &align);
2064 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2065 * since it loads/stores misaligned words, which don't do the right thing.
2067 if (align < 4 && size >= 4)
2069 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2070 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2071 offset += align - 1;
2072 offset &= ~(align - 1);
2073 ins->opcode = OP_REGOFFSET;
2074 ins->inst_offset = offset;
2075 ins->inst_basereg = cfg->frame_reg;
2077 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
2080 cfg->locals_max_stack_offset = offset;
2084 ins = cfg->args [curinst];
2085 if (ins->opcode != OP_REGVAR) {
2086 ins->opcode = OP_REGOFFSET;
2087 ins->inst_basereg = cfg->frame_reg;
2088 offset += sizeof (gpointer) - 1;
2089 offset &= ~(sizeof (gpointer) - 1);
2090 ins->inst_offset = offset;
2091 offset += sizeof (gpointer);
2096 if (sig->call_convention == MONO_CALL_VARARG) {
2100 /* Allocate a local slot to hold the sig cookie address */
2101 offset += align - 1;
2102 offset &= ~(align - 1);
2103 cfg->sig_cookie = offset;
2107 for (i = 0; i < sig->param_count; ++i) {
2108 ainfo = cinfo->args + i;
2110 ins = cfg->args [curinst];
2112 switch (ainfo->storage) {
2114 offset = ALIGN_TO (offset, 8);
2115 ins->opcode = OP_REGOFFSET;
2116 ins->inst_basereg = cfg->frame_reg;
2117 /* These arguments are saved to the stack in the prolog */
2118 ins->inst_offset = offset;
2119 if (cfg->verbose_level >= 2)
2120 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2128 if (ins->opcode != OP_REGVAR) {
2129 ins->opcode = OP_REGOFFSET;
2130 ins->inst_basereg = cfg->frame_reg;
2131 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2133 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2134 * since it loads/stores misaligned words, which don't do the right thing.
2136 if (align < 4 && size >= 4)
2138 /* The code in the prolog () stores words when storing vtypes received in a register */
2139 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2141 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2142 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2143 offset += align - 1;
2144 offset &= ~(align - 1);
2145 ins->inst_offset = offset;
2151 /* align the offset to 8 bytes */
2152 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2153 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2158 cfg->stack_offset = offset;
2162 mono_arch_create_vars (MonoCompile *cfg)
2164 MonoMethodSignature *sig;
2168 sig = mono_method_signature (cfg->method);
2170 if (!cfg->arch.cinfo)
2171 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2172 cinfo = cfg->arch.cinfo;
2174 if (IS_HARD_FLOAT) {
2175 for (i = 0; i < 2; i++) {
2176 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2177 inst->flags |= MONO_INST_VOLATILE;
2179 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2183 if (cinfo->ret.storage == RegTypeStructByVal)
2184 cfg->ret_var_is_local = TRUE;
2186 if (cinfo->ret.storage == RegTypeStructByAddr) {
2187 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2188 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2189 g_print ("vret_addr = ");
2190 mono_print_ins (cfg->vret_addr);
2194 if (cfg->gen_sdb_seq_points) {
2195 if (cfg->soft_breakpoints) {
2198 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2199 ins->flags |= MONO_INST_VOLATILE;
2200 cfg->arch.seq_point_ss_method_var = ins;
2202 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2203 ins->flags |= MONO_INST_VOLATILE;
2204 cfg->arch.seq_point_bp_method_var = ins;
2206 g_assert (!cfg->compile_aot);
2207 } else if (cfg->compile_aot) {
2208 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2209 ins->flags |= MONO_INST_VOLATILE;
2210 cfg->arch.seq_point_info_var = ins;
2212 /* Allocate a separate variable for this to save 1 load per seq point */
2213 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2214 ins->flags |= MONO_INST_VOLATILE;
2215 cfg->arch.ss_trigger_page_var = ins;
2221 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2223 MonoMethodSignature *tmp_sig;
2226 if (call->tail_call)
2229 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2232 * mono_ArgIterator_Setup assumes the signature cookie is
2233 * passed first and all the arguments which were before it are
2234 * passed on the stack after the signature. So compensate by
2235 * passing a different signature.
2237 tmp_sig = mono_metadata_signature_dup (call->signature);
2238 tmp_sig->param_count -= call->signature->sentinelpos;
2239 tmp_sig->sentinelpos = 0;
2240 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2242 sig_reg = mono_alloc_ireg (cfg);
2243 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2245 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2250 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2255 LLVMCallInfo *linfo;
2257 n = sig->param_count + sig->hasthis;
2259 cinfo = get_call_info (cfg->mempool, sig);
2261 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2264 * LLVM always uses the native ABI while we use our own ABI, the
2265 * only difference is the handling of vtypes:
2266 * - we only pass/receive them in registers in some cases, and only
2267 * in 1 or 2 integer registers.
2269 switch (cinfo->ret.storage) {
2270 case RegTypeGeneral:
2273 case RegTypeIRegPair:
2275 case RegTypeStructByAddr:
2276 /* Vtype returned using a hidden argument */
2277 linfo->ret.storage = LLVMArgVtypeRetAddr;
2278 linfo->vret_arg_index = cinfo->vret_arg_index;
2281 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2282 cfg->disable_llvm = TRUE;
2286 for (i = 0; i < n; ++i) {
2287 ainfo = cinfo->args + i;
2289 linfo->args [i].storage = LLVMArgNone;
2291 switch (ainfo->storage) {
2292 case RegTypeGeneral:
2293 case RegTypeIRegPair:
2295 case RegTypeBaseGen:
2296 linfo->args [i].storage = LLVMArgNormal;
2298 case RegTypeStructByVal:
2299 linfo->args [i].storage = LLVMArgAsIArgs;
2300 linfo->args [i].nslots = ainfo->struct_size / sizeof (gpointer);
2303 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2304 cfg->disable_llvm = TRUE;
2314 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2317 MonoMethodSignature *sig;
2321 sig = call->signature;
2322 n = sig->param_count + sig->hasthis;
2324 cinfo = get_call_info (cfg->mempool, sig);
2326 switch (cinfo->ret.storage) {
2327 case RegTypeStructByVal:
2328 /* The JIT will transform this into a normal call */
2329 call->vret_in_reg = TRUE;
2333 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2334 * the location pointed to by it after call in emit_move_return_value ().
2336 if (!cfg->arch.vret_addr_loc) {
2337 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2338 /* Prevent it from being register allocated or optimized away */
2339 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2342 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2344 case RegTypeStructByAddr: {
2346 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2347 vtarg->sreg1 = call->vret_var->dreg;
2348 vtarg->dreg = mono_alloc_preg (cfg);
2349 MONO_ADD_INS (cfg->cbb, vtarg);
2351 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2358 for (i = 0; i < n; ++i) {
2359 ArgInfo *ainfo = cinfo->args + i;
2362 if (i >= sig->hasthis)
2363 t = sig->params [i - sig->hasthis];
2365 t = &mono_defaults.int_class->byval_arg;
2366 t = mini_get_underlying_type (t);
2368 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2369 /* Emit the signature cookie just before the implicit arguments */
2370 emit_sig_cookie (cfg, call, cinfo);
2373 in = call->args [i];
2375 switch (ainfo->storage) {
2376 case RegTypeGeneral:
2377 case RegTypeIRegPair:
2378 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2379 MONO_INST_NEW (cfg, ins, OP_MOVE);
2380 ins->dreg = mono_alloc_ireg (cfg);
2381 ins->sreg1 = in->dreg + 1;
2382 MONO_ADD_INS (cfg->cbb, ins);
2383 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2385 MONO_INST_NEW (cfg, ins, OP_MOVE);
2386 ins->dreg = mono_alloc_ireg (cfg);
2387 ins->sreg1 = in->dreg + 2;
2388 MONO_ADD_INS (cfg->cbb, ins);
2389 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2390 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2391 if (ainfo->size == 4) {
2392 if (IS_SOFT_FLOAT) {
2393 /* mono_emit_call_args () have already done the r8->r4 conversion */
2394 /* The converted value is in an int vreg */
2395 MONO_INST_NEW (cfg, ins, OP_MOVE);
2396 ins->dreg = mono_alloc_ireg (cfg);
2397 ins->sreg1 = in->dreg;
2398 MONO_ADD_INS (cfg->cbb, ins);
2399 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2404 creg = mono_alloc_ireg (cfg);
2405 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2406 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2409 if (IS_SOFT_FLOAT) {
2410 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2411 ins->dreg = mono_alloc_ireg (cfg);
2412 ins->sreg1 = in->dreg;
2413 MONO_ADD_INS (cfg->cbb, ins);
2414 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2416 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2417 ins->dreg = mono_alloc_ireg (cfg);
2418 ins->sreg1 = in->dreg;
2419 MONO_ADD_INS (cfg->cbb, ins);
2420 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2424 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2425 creg = mono_alloc_ireg (cfg);
2426 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2427 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2428 creg = mono_alloc_ireg (cfg);
2429 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2430 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2433 cfg->flags |= MONO_CFG_HAS_FPOUT;
2435 MONO_INST_NEW (cfg, ins, OP_MOVE);
2436 ins->dreg = mono_alloc_ireg (cfg);
2437 ins->sreg1 = in->dreg;
2438 MONO_ADD_INS (cfg->cbb, ins);
2440 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2443 case RegTypeStructByAddr:
2446 /* FIXME: where si the data allocated? */
2447 arg->backend.reg3 = ainfo->reg;
2448 call->used_iregs |= 1 << ainfo->reg;
2449 g_assert_not_reached ();
2452 case RegTypeStructByVal:
2453 case RegTypeGSharedVtInReg:
2454 case RegTypeGSharedVtOnStack:
2456 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2457 ins->opcode = OP_OUTARG_VT;
2458 ins->sreg1 = in->dreg;
2459 ins->klass = in->klass;
2460 ins->inst_p0 = call;
2461 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2462 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2463 mono_call_inst_add_outarg_vt (cfg, call, ins);
2464 MONO_ADD_INS (cfg->cbb, ins);
2467 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2468 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2469 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2470 if (t->type == MONO_TYPE_R8) {
2471 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2474 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2476 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2479 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2482 case RegTypeBaseGen:
2483 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2484 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
2485 MONO_INST_NEW (cfg, ins, OP_MOVE);
2486 ins->dreg = mono_alloc_ireg (cfg);
2487 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
2488 MONO_ADD_INS (cfg->cbb, ins);
2489 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2490 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2493 /* This should work for soft-float as well */
2495 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2496 creg = mono_alloc_ireg (cfg);
2497 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2498 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2499 creg = mono_alloc_ireg (cfg);
2500 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2501 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2502 cfg->flags |= MONO_CFG_HAS_FPOUT;
2504 g_assert_not_reached ();
2508 int fdreg = mono_alloc_freg (cfg);
2510 if (ainfo->size == 8) {
2511 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2512 ins->sreg1 = in->dreg;
2514 MONO_ADD_INS (cfg->cbb, ins);
2516 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2521 * Mono's register allocator doesn't speak single-precision registers that
2522 * overlap double-precision registers (i.e. armhf). So we have to work around
2523 * the register allocator and load the value from memory manually.
2525 * So we create a variable for the float argument and an instruction to store
2526 * the argument into the variable. We then store the list of these arguments
2527 * in cfg->float_args. This list is then used by emit_float_args later to
2528 * pass the arguments in the various call opcodes.
2530 * This is not very nice, and we should really try to fix the allocator.
2533 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2535 /* Make sure the instruction isn't seen as pointless and removed.
2537 float_arg->flags |= MONO_INST_VOLATILE;
2539 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2541 /* We use the dreg to look up the instruction later. The hreg is used to
2542 * emit the instruction that loads the value into the FP reg.
2544 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2545 fad->vreg = float_arg->dreg;
2546 fad->hreg = ainfo->reg;
2548 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2551 call->used_iregs |= 1 << ainfo->reg;
2552 cfg->flags |= MONO_CFG_HAS_FPOUT;
2556 g_assert_not_reached ();
2560 /* Handle the case where there are no implicit arguments */
2561 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2562 emit_sig_cookie (cfg, call, cinfo);
2564 call->call_info = cinfo;
2565 call->stack_usage = cinfo->stack_usage;
2569 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2575 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2576 ins->dreg = mono_alloc_freg (cfg);
2577 ins->sreg1 = arg->dreg;
2578 MONO_ADD_INS (cfg->cbb, ins);
2579 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2582 g_assert_not_reached ();
2588 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2590 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2592 ArgInfo *ainfo = ins->inst_p1;
2593 int ovf_size = ainfo->vtsize;
2594 int doffset = ainfo->offset;
2595 int struct_size = ainfo->struct_size;
2596 int i, soffset, dreg, tmpreg;
2598 switch (ainfo->storage) {
2599 case RegTypeGSharedVtInReg:
2601 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2603 case RegTypeGSharedVtOnStack:
2604 /* Pass by addr on stack */
2605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2608 for (i = 0; i < ainfo->nregs; ++i) {
2609 if (ainfo->esize == 4)
2610 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2612 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2613 load->dreg = mono_alloc_freg (cfg);
2614 load->inst_basereg = src->dreg;
2615 load->inst_offset = i * ainfo->esize;
2616 MONO_ADD_INS (cfg->cbb, load);
2618 if (ainfo->esize == 4) {
2621 /* See RegTypeFP in mono_arch_emit_call () */
2622 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2623 float_arg->flags |= MONO_INST_VOLATILE;
2624 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2626 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2627 fad->vreg = float_arg->dreg;
2628 fad->hreg = ainfo->reg + i;
2630 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2632 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2638 for (i = 0; i < ainfo->size; ++i) {
2639 dreg = mono_alloc_ireg (cfg);
2640 switch (struct_size) {
2642 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2645 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2648 tmpreg = mono_alloc_ireg (cfg);
2649 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2650 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2651 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2652 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2653 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2654 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2655 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2658 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2661 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2662 soffset += sizeof (gpointer);
2663 struct_size -= sizeof (gpointer);
2665 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2667 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2673 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2675 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2678 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2681 if (COMPILE_LLVM (cfg)) {
2682 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2684 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2685 ins->sreg1 = val->dreg + 1;
2686 ins->sreg2 = val->dreg + 2;
2687 MONO_ADD_INS (cfg->cbb, ins);
2692 case MONO_ARM_FPU_NONE:
2693 if (ret->type == MONO_TYPE_R8) {
2696 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2697 ins->dreg = cfg->ret->dreg;
2698 ins->sreg1 = val->dreg;
2699 MONO_ADD_INS (cfg->cbb, ins);
2702 if (ret->type == MONO_TYPE_R4) {
2703 /* Already converted to an int in method_to_ir () */
2704 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2708 case MONO_ARM_FPU_VFP:
2709 case MONO_ARM_FPU_VFP_HARD:
2710 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2713 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2714 ins->dreg = cfg->ret->dreg;
2715 ins->sreg1 = val->dreg;
2716 MONO_ADD_INS (cfg->cbb, ins);
2721 g_assert_not_reached ();
2725 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2728 #endif /* #ifndef DISABLE_JIT */
2731 mono_arch_is_inst_imm (gint64 imm)
2737 MonoMethodSignature *sig;
2740 MonoType **param_types;
2744 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2748 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2751 switch (cinfo->ret.storage) {
2753 case RegTypeGeneral:
2754 case RegTypeIRegPair:
2755 case RegTypeStructByAddr:
2766 for (i = 0; i < cinfo->nargs; ++i) {
2767 ArgInfo *ainfo = &cinfo->args [i];
2770 switch (ainfo->storage) {
2771 case RegTypeGeneral:
2772 case RegTypeIRegPair:
2773 case RegTypeBaseGen:
2776 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2779 case RegTypeStructByVal:
2780 if (ainfo->size == 0)
2781 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2783 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2784 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2792 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2793 for (i = 0; i < sig->param_count; ++i) {
2794 MonoType *t = sig->params [i];
2799 t = mini_get_underlying_type (t);
2822 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2824 ArchDynCallInfo *info;
2828 cinfo = get_call_info (NULL, sig);
2830 if (!dyn_call_supported (cinfo, sig)) {
2835 info = g_new0 (ArchDynCallInfo, 1);
2836 // FIXME: Preprocess the info to speed up start_dyn_call ()
2838 info->cinfo = cinfo;
2839 info->rtype = mini_get_underlying_type (sig->ret);
2840 info->param_types = g_new0 (MonoType*, sig->param_count);
2841 for (i = 0; i < sig->param_count; ++i)
2842 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2844 return (MonoDynCallInfo*)info;
2848 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2850 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2852 g_free (ainfo->cinfo);
2857 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2859 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2860 DynCallArgs *p = (DynCallArgs*)buf;
2861 int arg_index, greg, i, j, pindex;
2862 MonoMethodSignature *sig = dinfo->sig;
2864 g_assert (buf_len >= sizeof (DynCallArgs));
2873 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2874 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2879 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2880 p->regs [greg ++] = (mgreg_t)ret;
2882 for (i = pindex; i < sig->param_count; i++) {
2883 MonoType *t = dinfo->param_types [i];
2884 gpointer *arg = args [arg_index ++];
2885 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2888 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2890 } else if (ainfo->storage == RegTypeBase) {
2891 slot = PARAM_REGS + (ainfo->offset / 4);
2892 } else if (ainfo->storage == RegTypeBaseGen) {
2893 /* slot + 1 is the first stack slot, so the code below will work */
2896 g_assert_not_reached ();
2900 p->regs [slot] = (mgreg_t)*arg;
2905 case MONO_TYPE_STRING:
2906 case MONO_TYPE_CLASS:
2907 case MONO_TYPE_ARRAY:
2908 case MONO_TYPE_SZARRAY:
2909 case MONO_TYPE_OBJECT:
2913 p->regs [slot] = (mgreg_t)*arg;
2916 p->regs [slot] = *(guint8*)arg;
2919 p->regs [slot] = *(gint8*)arg;
2922 p->regs [slot] = *(gint16*)arg;
2925 p->regs [slot] = *(guint16*)arg;
2928 p->regs [slot] = *(gint32*)arg;
2931 p->regs [slot] = *(guint32*)arg;
2935 p->regs [slot ++] = (mgreg_t)arg [0];
2936 p->regs [slot] = (mgreg_t)arg [1];
2939 p->regs [slot] = *(mgreg_t*)arg;
2942 p->regs [slot ++] = (mgreg_t)arg [0];
2943 p->regs [slot] = (mgreg_t)arg [1];
2945 case MONO_TYPE_GENERICINST:
2946 if (MONO_TYPE_IS_REFERENCE (t)) {
2947 p->regs [slot] = (mgreg_t)*arg;
2950 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2951 MonoClass *klass = mono_class_from_mono_type (t);
2952 guint8 *nullable_buf;
2955 size = mono_class_value_size (klass, NULL);
2956 nullable_buf = g_alloca (size);
2957 g_assert (nullable_buf);
2959 /* The argument pointed to by arg is either a boxed vtype or null */
2960 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2962 arg = (gpointer*)nullable_buf;
2968 case MONO_TYPE_VALUETYPE:
2969 g_assert (ainfo->storage == RegTypeStructByVal);
2971 if (ainfo->size == 0)
2972 slot = PARAM_REGS + (ainfo->offset / 4);
2976 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2977 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2980 g_assert_not_reached ();
2986 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2988 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2989 MonoType *ptype = ainfo->rtype;
2990 guint8 *ret = ((DynCallArgs*)buf)->ret;
2991 mgreg_t res = ((DynCallArgs*)buf)->res;
2992 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2994 switch (ptype->type) {
2995 case MONO_TYPE_VOID:
2996 *(gpointer*)ret = NULL;
2998 case MONO_TYPE_STRING:
2999 case MONO_TYPE_CLASS:
3000 case MONO_TYPE_ARRAY:
3001 case MONO_TYPE_SZARRAY:
3002 case MONO_TYPE_OBJECT:
3006 *(gpointer*)ret = (gpointer)res;
3012 *(guint8*)ret = res;
3015 *(gint16*)ret = res;
3018 *(guint16*)ret = res;
3021 *(gint32*)ret = res;
3024 *(guint32*)ret = res;
3028 /* This handles endianness as well */
3029 ((gint32*)ret) [0] = res;
3030 ((gint32*)ret) [1] = res2;
3032 case MONO_TYPE_GENERICINST:
3033 if (MONO_TYPE_IS_REFERENCE (ptype)) {
3034 *(gpointer*)ret = (gpointer)res;
3039 case MONO_TYPE_VALUETYPE:
3040 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
3045 *(float*)ret = *(float*)&res;
3047 case MONO_TYPE_R8: {
3054 *(double*)ret = *(double*)®s;
3058 g_assert_not_reached ();
3065 * Allow tracing to work with this interface (with an optional argument)
3069 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3073 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3074 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3075 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3076 code = emit_call_reg (code, ARMREG_R2);
3090 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3093 int save_mode = SAVE_NONE;
3095 MonoMethod *method = cfg->method;
3096 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3097 int rtype = ret_type->type;
3098 int save_offset = cfg->param_area;
3102 offset = code - cfg->native_code;
3103 /* we need about 16 instructions */
3104 if (offset > (cfg->code_size - 16 * 4)) {
3105 cfg->code_size *= 2;
3106 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3107 code = cfg->native_code + offset;
3110 case MONO_TYPE_VOID:
3111 /* special case string .ctor icall */
3112 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3113 save_mode = SAVE_ONE;
3115 save_mode = SAVE_NONE;
3119 save_mode = SAVE_TWO;
3123 save_mode = SAVE_ONE_FP;
3125 save_mode = SAVE_ONE;
3129 save_mode = SAVE_TWO_FP;
3131 save_mode = SAVE_TWO;
3133 case MONO_TYPE_GENERICINST:
3134 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3135 save_mode = SAVE_ONE;
3139 case MONO_TYPE_VALUETYPE:
3140 save_mode = SAVE_STRUCT;
3143 save_mode = SAVE_ONE;
3147 switch (save_mode) {
3149 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3150 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3151 if (enable_arguments) {
3152 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3153 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3157 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3158 if (enable_arguments) {
3159 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3163 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3164 if (enable_arguments) {
3165 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3169 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3170 if (enable_arguments) {
3171 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3175 if (enable_arguments) {
3176 /* FIXME: get the actual address */
3177 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3185 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3186 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3187 code = emit_call_reg (code, ARMREG_IP);
3189 switch (save_mode) {
3191 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3192 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3195 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3198 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3201 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3212 * The immediate field for cond branches is big enough for all reasonable methods
3214 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3215 if (0 && ins->inst_true_bb->native_offset) { \
3216 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3218 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3219 ARM_B_COND (code, (condcode), 0); \
3222 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3224 /* emit an exception if condition is fail
3226 * We assign the extra code used to throw the implicit exceptions
3227 * to cfg->bb_exit as far as the big branch handling is concerned
3229 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3231 mono_add_patch_info (cfg, code - cfg->native_code, \
3232 MONO_PATCH_INFO_EXC, exc_name); \
3233 ARM_BL_COND (code, (condcode), 0); \
3236 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3239 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3244 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3248 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3249 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3251 switch (ins->opcode) {
3254 /* Already done by an arch-independent pass */
3256 case OP_LOAD_MEMBASE:
3257 case OP_LOADI4_MEMBASE:
3259 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3260 * OP_LOAD_MEMBASE offset(basereg), reg
3262 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3263 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3264 ins->inst_basereg == last_ins->inst_destbasereg &&
3265 ins->inst_offset == last_ins->inst_offset) {
3266 if (ins->dreg == last_ins->sreg1) {
3267 MONO_DELETE_INS (bb, ins);
3270 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3271 ins->opcode = OP_MOVE;
3272 ins->sreg1 = last_ins->sreg1;
3276 * Note: reg1 must be different from the basereg in the second load
3277 * OP_LOAD_MEMBASE offset(basereg), reg1
3278 * OP_LOAD_MEMBASE offset(basereg), reg2
3280 * OP_LOAD_MEMBASE offset(basereg), reg1
3281 * OP_MOVE reg1, reg2
3283 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3284 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3285 ins->inst_basereg != last_ins->dreg &&
3286 ins->inst_basereg == last_ins->inst_basereg &&
3287 ins->inst_offset == last_ins->inst_offset) {
3289 if (ins->dreg == last_ins->dreg) {
3290 MONO_DELETE_INS (bb, ins);
3293 ins->opcode = OP_MOVE;
3294 ins->sreg1 = last_ins->dreg;
3297 //g_assert_not_reached ();
3301 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3302 * OP_LOAD_MEMBASE offset(basereg), reg
3304 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3305 * OP_ICONST reg, imm
3307 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3308 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3309 ins->inst_basereg == last_ins->inst_destbasereg &&
3310 ins->inst_offset == last_ins->inst_offset) {
3311 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3312 ins->opcode = OP_ICONST;
3313 ins->inst_c0 = last_ins->inst_imm;
3314 g_assert_not_reached (); // check this rule
3318 case OP_LOADU1_MEMBASE:
3319 case OP_LOADI1_MEMBASE:
3320 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3321 ins->inst_basereg == last_ins->inst_destbasereg &&
3322 ins->inst_offset == last_ins->inst_offset) {
3323 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3324 ins->sreg1 = last_ins->sreg1;
3327 case OP_LOADU2_MEMBASE:
3328 case OP_LOADI2_MEMBASE:
3329 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3330 ins->inst_basereg == last_ins->inst_destbasereg &&
3331 ins->inst_offset == last_ins->inst_offset) {
3332 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3333 ins->sreg1 = last_ins->sreg1;
3337 ins->opcode = OP_MOVE;
3341 if (ins->dreg == ins->sreg1) {
3342 MONO_DELETE_INS (bb, ins);
3346 * OP_MOVE sreg, dreg
3347 * OP_MOVE dreg, sreg
3349 if (last_ins && last_ins->opcode == OP_MOVE &&
3350 ins->sreg1 == last_ins->dreg &&
3351 ins->dreg == last_ins->sreg1) {
3352 MONO_DELETE_INS (bb, ins);
3361 * the branch_cc_table should maintain the order of these
3375 branch_cc_table [] = {
3389 #define ADD_NEW_INS(cfg,dest,op) do { \
3390 MONO_INST_NEW ((cfg), (dest), (op)); \
3391 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3395 map_to_reg_reg_op (int op)
3404 case OP_COMPARE_IMM:
3406 case OP_ICOMPARE_IMM:
3420 case OP_LOAD_MEMBASE:
3421 return OP_LOAD_MEMINDEX;
3422 case OP_LOADI4_MEMBASE:
3423 return OP_LOADI4_MEMINDEX;
3424 case OP_LOADU4_MEMBASE:
3425 return OP_LOADU4_MEMINDEX;
3426 case OP_LOADU1_MEMBASE:
3427 return OP_LOADU1_MEMINDEX;
3428 case OP_LOADI2_MEMBASE:
3429 return OP_LOADI2_MEMINDEX;
3430 case OP_LOADU2_MEMBASE:
3431 return OP_LOADU2_MEMINDEX;
3432 case OP_LOADI1_MEMBASE:
3433 return OP_LOADI1_MEMINDEX;
3434 case OP_STOREI1_MEMBASE_REG:
3435 return OP_STOREI1_MEMINDEX;
3436 case OP_STOREI2_MEMBASE_REG:
3437 return OP_STOREI2_MEMINDEX;
3438 case OP_STOREI4_MEMBASE_REG:
3439 return OP_STOREI4_MEMINDEX;
3440 case OP_STORE_MEMBASE_REG:
3441 return OP_STORE_MEMINDEX;
3442 case OP_STORER4_MEMBASE_REG:
3443 return OP_STORER4_MEMINDEX;
3444 case OP_STORER8_MEMBASE_REG:
3445 return OP_STORER8_MEMINDEX;
3446 case OP_STORE_MEMBASE_IMM:
3447 return OP_STORE_MEMBASE_REG;
3448 case OP_STOREI1_MEMBASE_IMM:
3449 return OP_STOREI1_MEMBASE_REG;
3450 case OP_STOREI2_MEMBASE_IMM:
3451 return OP_STOREI2_MEMBASE_REG;
3452 case OP_STOREI4_MEMBASE_IMM:
3453 return OP_STOREI4_MEMBASE_REG;
3455 g_assert_not_reached ();
3459 * Remove from the instruction list the instructions that can't be
3460 * represented with very simple instructions with no register
3464 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3466 MonoInst *ins, *temp, *last_ins = NULL;
3467 int rot_amount, imm8, low_imm;
3469 MONO_BB_FOR_EACH_INS (bb, ins) {
3471 switch (ins->opcode) {
3475 case OP_COMPARE_IMM:
3476 case OP_ICOMPARE_IMM:
3490 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3491 ADD_NEW_INS (cfg, temp, OP_ICONST);
3492 temp->inst_c0 = ins->inst_imm;
3493 temp->dreg = mono_alloc_ireg (cfg);
3494 ins->sreg2 = temp->dreg;
3495 ins->opcode = mono_op_imm_to_op (ins->opcode);
3497 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3503 if (ins->inst_imm == 1) {
3504 ins->opcode = OP_MOVE;
3507 if (ins->inst_imm == 0) {
3508 ins->opcode = OP_ICONST;
3512 imm8 = mono_is_power_of_two (ins->inst_imm);
3514 ins->opcode = OP_SHL_IMM;
3515 ins->inst_imm = imm8;
3518 ADD_NEW_INS (cfg, temp, OP_ICONST);
3519 temp->inst_c0 = ins->inst_imm;
3520 temp->dreg = mono_alloc_ireg (cfg);
3521 ins->sreg2 = temp->dreg;
3522 ins->opcode = OP_IMUL;
3528 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3529 /* ARM sets the C flag to 1 if there was _no_ overflow */
3530 ins->next->opcode = OP_COND_EXC_NC;
3533 case OP_IDIV_UN_IMM:
3535 case OP_IREM_UN_IMM:
3536 ADD_NEW_INS (cfg, temp, OP_ICONST);
3537 temp->inst_c0 = ins->inst_imm;
3538 temp->dreg = mono_alloc_ireg (cfg);
3539 ins->sreg2 = temp->dreg;
3540 ins->opcode = mono_op_imm_to_op (ins->opcode);
3542 case OP_LOCALLOC_IMM:
3543 ADD_NEW_INS (cfg, temp, OP_ICONST);
3544 temp->inst_c0 = ins->inst_imm;
3545 temp->dreg = mono_alloc_ireg (cfg);
3546 ins->sreg1 = temp->dreg;
3547 ins->opcode = OP_LOCALLOC;
3549 case OP_LOAD_MEMBASE:
3550 case OP_LOADI4_MEMBASE:
3551 case OP_LOADU4_MEMBASE:
3552 case OP_LOADU1_MEMBASE:
3553 /* we can do two things: load the immed in a register
3554 * and use an indexed load, or see if the immed can be
3555 * represented as an ad_imm + a load with a smaller offset
3556 * that fits. We just do the first for now, optimize later.
3558 if (arm_is_imm12 (ins->inst_offset))
3560 ADD_NEW_INS (cfg, temp, OP_ICONST);
3561 temp->inst_c0 = ins->inst_offset;
3562 temp->dreg = mono_alloc_ireg (cfg);
3563 ins->sreg2 = temp->dreg;
3564 ins->opcode = map_to_reg_reg_op (ins->opcode);
3566 case OP_LOADI2_MEMBASE:
3567 case OP_LOADU2_MEMBASE:
3568 case OP_LOADI1_MEMBASE:
3569 if (arm_is_imm8 (ins->inst_offset))
3571 ADD_NEW_INS (cfg, temp, OP_ICONST);
3572 temp->inst_c0 = ins->inst_offset;
3573 temp->dreg = mono_alloc_ireg (cfg);
3574 ins->sreg2 = temp->dreg;
3575 ins->opcode = map_to_reg_reg_op (ins->opcode);
3577 case OP_LOADR4_MEMBASE:
3578 case OP_LOADR8_MEMBASE:
3579 if (arm_is_fpimm8 (ins->inst_offset))
3581 low_imm = ins->inst_offset & 0x1ff;
3582 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3583 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3584 temp->inst_imm = ins->inst_offset & ~0x1ff;
3585 temp->sreg1 = ins->inst_basereg;
3586 temp->dreg = mono_alloc_ireg (cfg);
3587 ins->inst_basereg = temp->dreg;
3588 ins->inst_offset = low_imm;
3592 ADD_NEW_INS (cfg, temp, OP_ICONST);
3593 temp->inst_c0 = ins->inst_offset;
3594 temp->dreg = mono_alloc_ireg (cfg);
3596 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3597 add_ins->sreg1 = ins->inst_basereg;
3598 add_ins->sreg2 = temp->dreg;
3599 add_ins->dreg = mono_alloc_ireg (cfg);
3601 ins->inst_basereg = add_ins->dreg;
3602 ins->inst_offset = 0;
3605 case OP_STORE_MEMBASE_REG:
3606 case OP_STOREI4_MEMBASE_REG:
3607 case OP_STOREI1_MEMBASE_REG:
3608 if (arm_is_imm12 (ins->inst_offset))
3610 ADD_NEW_INS (cfg, temp, OP_ICONST);
3611 temp->inst_c0 = ins->inst_offset;
3612 temp->dreg = mono_alloc_ireg (cfg);
3613 ins->sreg2 = temp->dreg;
3614 ins->opcode = map_to_reg_reg_op (ins->opcode);
3616 case OP_STOREI2_MEMBASE_REG:
3617 if (arm_is_imm8 (ins->inst_offset))
3619 ADD_NEW_INS (cfg, temp, OP_ICONST);
3620 temp->inst_c0 = ins->inst_offset;
3621 temp->dreg = mono_alloc_ireg (cfg);
3622 ins->sreg2 = temp->dreg;
3623 ins->opcode = map_to_reg_reg_op (ins->opcode);
3625 case OP_STORER4_MEMBASE_REG:
3626 case OP_STORER8_MEMBASE_REG:
3627 if (arm_is_fpimm8 (ins->inst_offset))
3629 low_imm = ins->inst_offset & 0x1ff;
3630 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3631 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3632 temp->inst_imm = ins->inst_offset & ~0x1ff;
3633 temp->sreg1 = ins->inst_destbasereg;
3634 temp->dreg = mono_alloc_ireg (cfg);
3635 ins->inst_destbasereg = temp->dreg;
3636 ins->inst_offset = low_imm;
3640 ADD_NEW_INS (cfg, temp, OP_ICONST);
3641 temp->inst_c0 = ins->inst_offset;
3642 temp->dreg = mono_alloc_ireg (cfg);
3644 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3645 add_ins->sreg1 = ins->inst_destbasereg;
3646 add_ins->sreg2 = temp->dreg;
3647 add_ins->dreg = mono_alloc_ireg (cfg);
3649 ins->inst_destbasereg = add_ins->dreg;
3650 ins->inst_offset = 0;
3653 case OP_STORE_MEMBASE_IMM:
3654 case OP_STOREI1_MEMBASE_IMM:
3655 case OP_STOREI2_MEMBASE_IMM:
3656 case OP_STOREI4_MEMBASE_IMM:
3657 ADD_NEW_INS (cfg, temp, OP_ICONST);
3658 temp->inst_c0 = ins->inst_imm;
3659 temp->dreg = mono_alloc_ireg (cfg);
3660 ins->sreg1 = temp->dreg;
3661 ins->opcode = map_to_reg_reg_op (ins->opcode);
3663 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3666 gboolean swap = FALSE;
3670 /* Optimized away */
3675 /* Some fp compares require swapped operands */
3676 switch (ins->next->opcode) {
3678 ins->next->opcode = OP_FBLT;
3682 ins->next->opcode = OP_FBLT_UN;
3686 ins->next->opcode = OP_FBGE;
3690 ins->next->opcode = OP_FBGE_UN;
3698 ins->sreg1 = ins->sreg2;
3707 bb->last_ins = last_ins;
3708 bb->max_vreg = cfg->next_vreg;
3712 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3716 if (long_ins->opcode == OP_LNEG) {
3718 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
3719 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
3725 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3727 /* sreg is a float, dreg is an integer reg */
3729 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3731 ARM_TOSIZD (code, vfp_scratch1, sreg);
3733 ARM_TOUIZD (code, vfp_scratch1, sreg);
3734 ARM_FMRS (code, dreg, vfp_scratch1);
3735 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3739 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3740 else if (size == 2) {
3741 ARM_SHL_IMM (code, dreg, dreg, 16);
3742 ARM_SHR_IMM (code, dreg, dreg, 16);
3746 ARM_SHL_IMM (code, dreg, dreg, 24);
3747 ARM_SAR_IMM (code, dreg, dreg, 24);
3748 } else if (size == 2) {
3749 ARM_SHL_IMM (code, dreg, dreg, 16);
3750 ARM_SAR_IMM (code, dreg, dreg, 16);
3757 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3759 /* sreg is a float, dreg is an integer reg */
3761 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3763 ARM_TOSIZS (code, vfp_scratch1, sreg);
3765 ARM_TOUIZS (code, vfp_scratch1, sreg);
3766 ARM_FMRS (code, dreg, vfp_scratch1);
3767 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3771 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3772 else if (size == 2) {
3773 ARM_SHL_IMM (code, dreg, dreg, 16);
3774 ARM_SHR_IMM (code, dreg, dreg, 16);
3778 ARM_SHL_IMM (code, dreg, dreg, 24);
3779 ARM_SAR_IMM (code, dreg, dreg, 24);
3780 } else if (size == 2) {
3781 ARM_SHL_IMM (code, dreg, dreg, 16);
3782 ARM_SAR_IMM (code, dreg, dreg, 16);
3788 #endif /* #ifndef DISABLE_JIT */
3790 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3793 emit_thunk (guint8 *code, gconstpointer target)
3797 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3798 if (thumb_supported)
3799 ARM_BX (code, ARMREG_IP);
3801 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3802 *(guint32*)code = (guint32)target;
3804 mono_arch_flush_icache (p, code - p);
3808 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3810 MonoJitInfo *ji = NULL;
3811 MonoThunkJitInfo *info;
3814 guint8 *orig_target;
3815 guint8 *target_thunk;
3818 domain = mono_domain_get ();
3822 * This can be called multiple times during JITting,
3823 * save the current position in cfg->arch to avoid
3824 * doing a O(n^2) search.
3826 if (!cfg->arch.thunks) {
3827 cfg->arch.thunks = cfg->thunks;
3828 cfg->arch.thunks_size = cfg->thunk_area;
3830 thunks = cfg->arch.thunks;
3831 thunks_size = cfg->arch.thunks_size;
3833 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3834 g_assert_not_reached ();
3837 g_assert (*(guint32*)thunks == 0);
3838 emit_thunk (thunks, target);
3839 arm_patch (code, thunks);
3841 cfg->arch.thunks += THUNK_SIZE;
3842 cfg->arch.thunks_size -= THUNK_SIZE;
3844 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3846 info = mono_jit_info_get_thunk_info (ji);
3849 thunks = (guint8*)ji->code_start + info->thunks_offset;
3850 thunks_size = info->thunks_size;
3852 orig_target = mono_arch_get_call_target (code + 4);
3854 mono_mini_arch_lock ();
3856 target_thunk = NULL;
3857 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3858 /* The call already points to a thunk, because of trampolines etc. */
3859 target_thunk = orig_target;
3861 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3862 if (((guint32*)p) [0] == 0) {
3866 } else if (((guint32*)p) [2] == (guint32)target) {
3867 /* Thunk already points to target */
3874 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3876 if (!target_thunk) {
3877 mono_mini_arch_unlock ();
3878 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3879 g_assert_not_reached ();
3882 emit_thunk (target_thunk, target);
3883 arm_patch (code, target_thunk);
3884 mono_arch_flush_icache (code, 4);
3886 mono_mini_arch_unlock ();
3891 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3893 guint32 *code32 = (void*)code;
3894 guint32 ins = *code32;
3895 guint32 prim = (ins >> 25) & 7;
3896 guint32 tval = GPOINTER_TO_UINT (target);
3898 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3899 if (prim == 5) { /* 101b */
3900 /* the diff starts 8 bytes from the branch opcode */
3901 gint diff = target - code - 8;
3903 gint tmask = 0xffffffff;
3904 if (tval & 1) { /* entering thumb mode */
3905 diff = target - 1 - code - 8;
3906 g_assert (thumb_supported);
3907 tbits = 0xf << 28; /* bl->blx bit pattern */
3908 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3909 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3913 tmask = ~(1 << 24); /* clear the link bit */
3914 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3919 if (diff <= 33554431) {
3921 ins = (ins & 0xff000000) | diff;
3923 *code32 = ins | tbits;
3927 /* diff between 0 and -33554432 */
3928 if (diff >= -33554432) {
3930 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3932 *code32 = ins | tbits;
3937 handle_thunk (cfg, domain, code, target);
3941 #ifdef USE_JUMP_TABLES
3943 gpointer *jte = mono_jumptable_get_entry (code);
3945 jte [0] = (gpointer) target;
3949 * The alternative call sequences looks like this:
3951 * ldr ip, [pc] // loads the address constant
3952 * b 1f // jumps around the constant
3953 * address constant embedded in the code
3958 * There are two cases for patching:
3959 * a) at the end of method emission: in this case code points to the start
3960 * of the call sequence
3961 * b) during runtime patching of the call site: in this case code points
3962 * to the mov pc, ip instruction
3964 * We have to handle also the thunk jump code sequence:
3968 * address constant // execution never reaches here
3970 if ((ins & 0x0ffffff0) == 0x12fff10) {
3971 /* Branch and exchange: the address is constructed in a reg
3972 * We can patch BX when the code sequence is the following:
3973 * ldr ip, [pc, #0] ; 0x8
3980 guint8 *emit = (guint8*)ccode;
3981 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3983 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3984 ARM_BX (emit, ARMREG_IP);
3986 /*patching from magic trampoline*/
3987 if (ins == ccode [3]) {
3988 g_assert (code32 [-4] == ccode [0]);
3989 g_assert (code32 [-3] == ccode [1]);
3990 g_assert (code32 [-1] == ccode [2]);
3991 code32 [-2] = (guint32)target;
3994 /*patching from JIT*/
3995 if (ins == ccode [0]) {
3996 g_assert (code32 [1] == ccode [1]);
3997 g_assert (code32 [3] == ccode [2]);
3998 g_assert (code32 [4] == ccode [3]);
3999 code32 [2] = (guint32)target;
4002 g_assert_not_reached ();
4003 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
4011 guint8 *emit = (guint8*)ccode;
4012 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4014 ARM_BLX_REG (emit, ARMREG_IP);
4016 g_assert (code32 [-3] == ccode [0]);
4017 g_assert (code32 [-2] == ccode [1]);
4018 g_assert (code32 [0] == ccode [2]);
4020 code32 [-1] = (guint32)target;
4023 guint32 *tmp = ccode;
4024 guint8 *emit = (guint8*)tmp;
4025 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
4026 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
4027 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
4028 ARM_BX (emit, ARMREG_IP);
4029 if (ins == ccode [2]) {
4030 g_assert_not_reached (); // should be -2 ...
4031 code32 [-1] = (guint32)target;
4034 if (ins == ccode [0]) {
4035 /* handles both thunk jump code and the far call sequence */
4036 code32 [2] = (guint32)target;
4039 g_assert_not_reached ();
4041 // g_print ("patched with 0x%08x\n", ins);
4046 arm_patch (guchar *code, const guchar *target)
4048 arm_patch_general (NULL, NULL, code, target);
4052 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
4053 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
4054 * to be used with the emit macros.
4055 * Return -1 otherwise.
4058 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
4061 for (i = 0; i < 31; i+= 2) {
4062 res = (val << (32 - i)) | (val >> i);
4065 *rot_amount = i? 32 - i: 0;
4072 * Emits in code a sequence of instructions that load the value 'val'
4073 * into the dreg register. Uses at most 4 instructions.
4076 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4078 int imm8, rot_amount;
4080 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4081 /* skip the constant pool */
4087 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4088 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4089 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4093 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4094 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4095 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4096 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4099 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4101 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4105 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4107 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4109 if (val & 0xFF0000) {
4110 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4112 if (val & 0xFF000000) {
4113 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4115 } else if (val & 0xFF00) {
4116 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4117 if (val & 0xFF0000) {
4118 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4120 if (val & 0xFF000000) {
4121 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4123 } else if (val & 0xFF0000) {
4124 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4125 if (val & 0xFF000000) {
4126 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4129 //g_assert_not_reached ();
4135 mono_arm_thumb_supported (void)
4137 return thumb_supported;
4143 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4148 call = (MonoCallInst*)ins;
4149 cinfo = call->call_info;
4151 switch (cinfo->ret.storage) {
4153 MonoInst *loc = cfg->arch.vret_addr_loc;
4156 /* Load the destination address */
4157 g_assert (loc && loc->opcode == OP_REGOFFSET);
4159 if (arm_is_imm12 (loc->inst_offset)) {
4160 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4162 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4163 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4165 for (i = 0; i < cinfo->ret.nregs; ++i) {
4166 if (cinfo->ret.esize == 4)
4167 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4169 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4177 switch (ins->opcode) {
4180 case OP_FCALL_MEMBASE:
4182 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4183 if (sig_ret->type == MONO_TYPE_R4) {
4184 if (IS_HARD_FLOAT) {
4185 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4187 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4188 ARM_CVTS (code, ins->dreg, ins->dreg);
4191 if (IS_HARD_FLOAT) {
4192 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4194 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4201 case OP_RCALL_MEMBASE: {
4206 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4207 g_assert (sig_ret->type == MONO_TYPE_R4);
4208 if (IS_HARD_FLOAT) {
4209 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4211 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4212 ARM_CPYS (code, ins->dreg, ins->dreg);
4224 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4229 guint8 *code = cfg->native_code + cfg->code_len;
4230 MonoInst *last_ins = NULL;
4231 guint last_offset = 0;
4233 int imm8, rot_amount;
4235 /* we don't align basic blocks of loops on arm */
4237 if (cfg->verbose_level > 2)
4238 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4240 cpos = bb->max_offset;
4242 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4243 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4244 //g_assert (!mono_compile_aot);
4247 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4248 /* this is not thread save, but good enough */
4249 /* fixme: howto handle overflows? */
4250 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4253 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4254 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4255 (gpointer)"mono_break");
4256 code = emit_call_seq (cfg, code);
4259 MONO_BB_FOR_EACH_INS (bb, ins) {
4260 offset = code - cfg->native_code;
4262 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4264 if (offset > (cfg->code_size - max_len - 16)) {
4265 cfg->code_size *= 2;
4266 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4267 code = cfg->native_code + offset;
4269 // if (ins->cil_code)
4270 // g_print ("cil code\n");
4271 mono_debug_record_line_number (cfg, ins, offset);
4273 switch (ins->opcode) {
4274 case OP_MEMORY_BARRIER:
4276 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4277 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4281 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4283 case OP_TLS_GET_REG:
4284 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4287 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4289 case OP_TLS_SET_REG:
4290 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4292 case OP_ATOMIC_EXCHANGE_I4:
4293 case OP_ATOMIC_CAS_I4:
4294 case OP_ATOMIC_ADD_I4: {
4298 g_assert (v7_supported);
4301 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4303 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4305 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4309 g_assert (cfg->arch.atomic_tmp_offset != -1);
4310 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4312 switch (ins->opcode) {
4313 case OP_ATOMIC_EXCHANGE_I4:
4315 ARM_DMB (code, ARM_DMB_SY);
4316 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4317 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4318 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4320 ARM_B_COND (code, ARMCOND_NE, 0);
4321 arm_patch (buf [1], buf [0]);
4323 case OP_ATOMIC_CAS_I4:
4324 ARM_DMB (code, ARM_DMB_SY);
4326 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4327 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4329 ARM_B_COND (code, ARMCOND_NE, 0);
4330 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4331 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4333 ARM_B_COND (code, ARMCOND_NE, 0);
4334 arm_patch (buf [2], buf [0]);
4335 arm_patch (buf [1], code);
4337 case OP_ATOMIC_ADD_I4:
4339 ARM_DMB (code, ARM_DMB_SY);
4340 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4341 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4342 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4343 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4345 ARM_B_COND (code, ARMCOND_NE, 0);
4346 arm_patch (buf [1], buf [0]);
4349 g_assert_not_reached ();
4352 ARM_DMB (code, ARM_DMB_SY);
4353 if (tmpreg != ins->dreg)
4354 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4355 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4358 case OP_ATOMIC_LOAD_I1:
4359 case OP_ATOMIC_LOAD_U1:
4360 case OP_ATOMIC_LOAD_I2:
4361 case OP_ATOMIC_LOAD_U2:
4362 case OP_ATOMIC_LOAD_I4:
4363 case OP_ATOMIC_LOAD_U4:
4364 case OP_ATOMIC_LOAD_R4:
4365 case OP_ATOMIC_LOAD_R8: {
4366 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4367 ARM_DMB (code, ARM_DMB_SY);
4369 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4371 switch (ins->opcode) {
4372 case OP_ATOMIC_LOAD_I1:
4373 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4375 case OP_ATOMIC_LOAD_U1:
4376 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4378 case OP_ATOMIC_LOAD_I2:
4379 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4381 case OP_ATOMIC_LOAD_U2:
4382 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4384 case OP_ATOMIC_LOAD_I4:
4385 case OP_ATOMIC_LOAD_U4:
4386 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4388 case OP_ATOMIC_LOAD_R4:
4390 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4391 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4393 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4394 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4395 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4396 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4397 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4400 case OP_ATOMIC_LOAD_R8:
4401 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4402 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4406 ARM_DMB (code, ARM_DMB_SY);
4409 case OP_ATOMIC_STORE_I1:
4410 case OP_ATOMIC_STORE_U1:
4411 case OP_ATOMIC_STORE_I2:
4412 case OP_ATOMIC_STORE_U2:
4413 case OP_ATOMIC_STORE_I4:
4414 case OP_ATOMIC_STORE_U4:
4415 case OP_ATOMIC_STORE_R4:
4416 case OP_ATOMIC_STORE_R8: {
4417 ARM_DMB (code, ARM_DMB_SY);
4419 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4421 switch (ins->opcode) {
4422 case OP_ATOMIC_STORE_I1:
4423 case OP_ATOMIC_STORE_U1:
4424 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4426 case OP_ATOMIC_STORE_I2:
4427 case OP_ATOMIC_STORE_U2:
4428 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4430 case OP_ATOMIC_STORE_I4:
4431 case OP_ATOMIC_STORE_U4:
4432 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4434 case OP_ATOMIC_STORE_R4:
4436 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4437 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4439 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4440 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4441 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4442 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4443 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4446 case OP_ATOMIC_STORE_R8:
4447 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4448 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4452 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4453 ARM_DMB (code, ARM_DMB_SY);
4457 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4458 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4461 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4462 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4464 case OP_STOREI1_MEMBASE_IMM:
4465 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4466 g_assert (arm_is_imm12 (ins->inst_offset));
4467 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4469 case OP_STOREI2_MEMBASE_IMM:
4470 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4471 g_assert (arm_is_imm8 (ins->inst_offset));
4472 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4474 case OP_STORE_MEMBASE_IMM:
4475 case OP_STOREI4_MEMBASE_IMM:
4476 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4477 g_assert (arm_is_imm12 (ins->inst_offset));
4478 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4480 case OP_STOREI1_MEMBASE_REG:
4481 g_assert (arm_is_imm12 (ins->inst_offset));
4482 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4484 case OP_STOREI2_MEMBASE_REG:
4485 g_assert (arm_is_imm8 (ins->inst_offset));
4486 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4488 case OP_STORE_MEMBASE_REG:
4489 case OP_STOREI4_MEMBASE_REG:
4490 /* this case is special, since it happens for spill code after lowering has been called */
4491 if (arm_is_imm12 (ins->inst_offset)) {
4492 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4494 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4495 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4498 case OP_STOREI1_MEMINDEX:
4499 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4501 case OP_STOREI2_MEMINDEX:
4502 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4504 case OP_STORE_MEMINDEX:
4505 case OP_STOREI4_MEMINDEX:
4506 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4509 g_assert_not_reached ();
4511 case OP_LOAD_MEMINDEX:
4512 case OP_LOADI4_MEMINDEX:
4513 case OP_LOADU4_MEMINDEX:
4514 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4516 case OP_LOADI1_MEMINDEX:
4517 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4519 case OP_LOADU1_MEMINDEX:
4520 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4522 case OP_LOADI2_MEMINDEX:
4523 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4525 case OP_LOADU2_MEMINDEX:
4526 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4528 case OP_LOAD_MEMBASE:
4529 case OP_LOADI4_MEMBASE:
4530 case OP_LOADU4_MEMBASE:
4531 /* this case is special, since it happens for spill code after lowering has been called */
4532 if (arm_is_imm12 (ins->inst_offset)) {
4533 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4535 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4536 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4539 case OP_LOADI1_MEMBASE:
4540 g_assert (arm_is_imm8 (ins->inst_offset));
4541 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4543 case OP_LOADU1_MEMBASE:
4544 g_assert (arm_is_imm12 (ins->inst_offset));
4545 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4547 case OP_LOADU2_MEMBASE:
4548 g_assert (arm_is_imm8 (ins->inst_offset));
4549 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4551 case OP_LOADI2_MEMBASE:
4552 g_assert (arm_is_imm8 (ins->inst_offset));
4553 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4555 case OP_ICONV_TO_I1:
4556 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4557 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4559 case OP_ICONV_TO_I2:
4560 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4561 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4563 case OP_ICONV_TO_U1:
4564 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4566 case OP_ICONV_TO_U2:
4567 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4568 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4572 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4574 case OP_COMPARE_IMM:
4575 case OP_ICOMPARE_IMM:
4576 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4577 g_assert (imm8 >= 0);
4578 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4582 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4583 * So instead of emitting a trap, we emit a call a C function and place a
4586 //*(int*)code = 0xef9f0001;
4589 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4590 (gpointer)"mono_break");
4591 code = emit_call_seq (cfg, code);
4593 case OP_RELAXED_NOP:
4598 case OP_DUMMY_STORE:
4599 case OP_DUMMY_ICONST:
4600 case OP_DUMMY_R8CONST:
4601 case OP_NOT_REACHED:
4604 case OP_IL_SEQ_POINT:
4605 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4607 case OP_SEQ_POINT: {
4609 MonoInst *info_var = cfg->arch.seq_point_info_var;
4610 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4611 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4612 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4614 int dreg = ARMREG_LR;
4616 if (cfg->soft_breakpoints) {
4617 g_assert (!cfg->compile_aot);
4621 * For AOT, we use one got slot per method, which will point to a
4622 * SeqPointInfo structure, containing all the information required
4623 * by the code below.
4625 if (cfg->compile_aot) {
4626 g_assert (info_var);
4627 g_assert (info_var->opcode == OP_REGOFFSET);
4628 g_assert (arm_is_imm12 (info_var->inst_offset));
4631 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4633 * Read from the single stepping trigger page. This will cause a
4634 * SIGSEGV when single stepping is enabled.
4635 * We do this _before_ the breakpoint, so single stepping after
4636 * a breakpoint is hit will step to the next IL offset.
4638 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4641 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4642 if (cfg->soft_breakpoints) {
4643 /* Load the address of the sequence point method variable. */
4644 var = ss_method_var;
4646 g_assert (var->opcode == OP_REGOFFSET);
4647 g_assert (arm_is_imm12 (var->inst_offset));
4648 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4650 /* Read the value and check whether it is non-zero. */
4651 ARM_LDR_IMM (code, dreg, dreg, 0);
4652 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4653 /* Call it conditionally. */
4654 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4656 if (cfg->compile_aot) {
4657 /* Load the trigger page addr from the variable initialized in the prolog */
4658 var = ss_trigger_page_var;
4660 g_assert (var->opcode == OP_REGOFFSET);
4661 g_assert (arm_is_imm12 (var->inst_offset));
4662 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4664 #ifdef USE_JUMP_TABLES
4665 gpointer *jte = mono_jumptable_add_entry ();
4666 code = mono_arm_load_jumptable_entry (code, jte, dreg);
4667 jte [0] = ss_trigger_page;
4669 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4671 *(int*)code = (int)ss_trigger_page;
4675 ARM_LDR_IMM (code, dreg, dreg, 0);
4679 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4681 if (cfg->soft_breakpoints) {
4682 /* Load the address of the breakpoint method into ip. */
4683 var = bp_method_var;
4685 g_assert (var->opcode == OP_REGOFFSET);
4686 g_assert (arm_is_imm12 (var->inst_offset));
4687 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4690 * A placeholder for a possible breakpoint inserted by
4691 * mono_arch_set_breakpoint ().
4694 } else if (cfg->compile_aot) {
4695 guint32 offset = code - cfg->native_code;
4698 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4699 /* Add the offset */
4700 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4701 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4702 if (arm_is_imm12 ((int)val)) {
4703 ARM_LDR_IMM (code, dreg, dreg, val);
4705 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4707 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4709 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4710 g_assert (!(val & 0xFF000000));
4712 ARM_LDR_IMM (code, dreg, dreg, 0);
4714 /* What is faster, a branch or a load ? */
4715 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4716 /* The breakpoint instruction */
4717 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4720 * A placeholder for a possible breakpoint inserted by
4721 * mono_arch_set_breakpoint ().
4723 for (i = 0; i < 4; ++i)
4728 * Add an additional nop so skipping the bp doesn't cause the ip to point
4729 * to another IL offset.
4737 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4740 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4744 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4747 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4748 g_assert (imm8 >= 0);
4749 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4759 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4760 g_assert (imm8 >= 0);
4761 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4764 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4765 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4767 case OP_IADD_OVF_UN:
4768 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4769 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4772 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4773 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4775 case OP_ISUB_OVF_UN:
4776 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4777 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4779 case OP_ADD_OVF_CARRY:
4780 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4781 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4783 case OP_ADD_OVF_UN_CARRY:
4784 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4785 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4787 case OP_SUB_OVF_CARRY:
4788 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4789 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4791 case OP_SUB_OVF_UN_CARRY:
4792 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4793 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4797 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4800 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4801 g_assert (imm8 >= 0);
4802 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4805 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4809 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4813 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4814 g_assert (imm8 >= 0);
4815 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4819 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4820 g_assert (imm8 >= 0);
4821 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4823 case OP_ARM_RSBS_IMM:
4824 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4825 g_assert (imm8 >= 0);
4826 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4828 case OP_ARM_RSC_IMM:
4829 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4830 g_assert (imm8 >= 0);
4831 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4834 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4838 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4839 g_assert (imm8 >= 0);
4840 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4843 g_assert (v7s_supported || v7k_supported);
4844 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4847 g_assert (v7s_supported || v7k_supported);
4848 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4851 g_assert (v7s_supported || v7k_supported);
4852 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4853 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4856 g_assert (v7s_supported || v7k_supported);
4857 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4858 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4862 g_assert_not_reached ();
4864 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4868 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4869 g_assert (imm8 >= 0);
4870 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4873 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4877 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4878 g_assert (imm8 >= 0);
4879 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4882 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4887 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4888 else if (ins->dreg != ins->sreg1)
4889 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4892 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4897 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4898 else if (ins->dreg != ins->sreg1)
4899 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4902 case OP_ISHR_UN_IMM:
4904 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4905 else if (ins->dreg != ins->sreg1)
4906 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4909 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4912 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4915 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4918 if (ins->dreg == ins->sreg2)
4919 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4921 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4924 g_assert_not_reached ();
4927 /* FIXME: handle ovf/ sreg2 != dreg */
4928 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4929 /* FIXME: MUL doesn't set the C/O flags on ARM */
4931 case OP_IMUL_OVF_UN:
4932 /* FIXME: handle ovf/ sreg2 != dreg */
4933 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4934 /* FIXME: MUL doesn't set the C/O flags on ARM */
4937 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4940 /* Load the GOT offset */
4941 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4942 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4944 *(gpointer*)code = NULL;
4946 /* Load the value from the GOT */
4947 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4949 case OP_OBJC_GET_SELECTOR:
4950 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4951 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4953 *(gpointer*)code = NULL;
4955 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4957 case OP_ICONV_TO_I4:
4958 case OP_ICONV_TO_U4:
4960 if (ins->dreg != ins->sreg1)
4961 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4964 int saved = ins->sreg2;
4965 if (ins->sreg2 == ARM_LSW_REG) {
4966 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4969 if (ins->sreg1 != ARM_LSW_REG)
4970 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4971 if (saved != ARM_MSW_REG)
4972 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4976 if (IS_VFP && ins->dreg != ins->sreg1)
4977 ARM_CPYD (code, ins->dreg, ins->sreg1);
4980 if (IS_VFP && ins->dreg != ins->sreg1)
4981 ARM_CPYS (code, ins->dreg, ins->sreg1);
4983 case OP_MOVE_F_TO_I4:
4985 ARM_FMRS (code, ins->dreg, ins->sreg1);
4987 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4988 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4989 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4990 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4993 case OP_MOVE_I4_TO_F:
4995 ARM_FMSR (code, ins->dreg, ins->sreg1);
4997 ARM_FMSR (code, ins->dreg, ins->sreg1);
4998 ARM_CVTS (code, ins->dreg, ins->dreg);
5001 case OP_FCONV_TO_R4:
5004 ARM_CVTD (code, ins->dreg, ins->sreg1);
5006 ARM_CVTD (code, ins->dreg, ins->sreg1);
5007 ARM_CVTS (code, ins->dreg, ins->dreg);
5012 MonoCallInst *call = (MonoCallInst*)ins;
5015 * The stack looks like the following:
5016 * <caller argument area>
5019 * <callee argument area>
5020 * Need to copy the arguments from the callee argument area to
5021 * the caller argument area, and pop the frame.
5023 if (call->stack_usage) {
5024 int i, prev_sp_offset = 0;
5026 /* Compute size of saved registers restored below */
5028 prev_sp_offset = 2 * 4;
5030 prev_sp_offset = 1 * 4;
5031 for (i = 0; i < 16; ++i) {
5032 if (cfg->used_int_regs & (1 << i))
5033 prev_sp_offset += 4;
5036 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
5038 /* Copy arguments on the stack to our argument area */
5039 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
5040 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
5041 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5046 * Keep in sync with mono_arch_emit_epilog
5048 g_assert (!cfg->method->save_lmf);
5050 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5052 if (cfg->used_int_regs)
5053 ARM_POP (code, cfg->used_int_regs);
5054 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5056 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5059 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5060 if (cfg->compile_aot) {
5061 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5063 *(gpointer*)code = NULL;
5065 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5067 code = mono_arm_patchable_b (code, ARMCOND_AL);
5068 cfg->thunk_area += THUNK_SIZE;
5073 /* ensure ins->sreg1 is not NULL */
5074 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5077 g_assert (cfg->sig_cookie < 128);
5078 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5079 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5089 call = (MonoCallInst*)ins;
5092 code = emit_float_args (cfg, call, code, &max_len, &offset);
5094 if (ins->flags & MONO_INST_HAS_METHOD)
5095 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5097 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5098 code = emit_call_seq (cfg, code);
5099 ins->flags |= MONO_INST_GC_CALLSITE;
5100 ins->backend.pc_offset = code - cfg->native_code;
5101 code = emit_move_return_value (cfg, ins, code);
5108 case OP_VOIDCALL_REG:
5111 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5113 code = emit_call_reg (code, ins->sreg1);
5114 ins->flags |= MONO_INST_GC_CALLSITE;
5115 ins->backend.pc_offset = code - cfg->native_code;
5116 code = emit_move_return_value (cfg, ins, code);
5118 case OP_FCALL_MEMBASE:
5119 case OP_RCALL_MEMBASE:
5120 case OP_LCALL_MEMBASE:
5121 case OP_VCALL_MEMBASE:
5122 case OP_VCALL2_MEMBASE:
5123 case OP_VOIDCALL_MEMBASE:
5124 case OP_CALL_MEMBASE: {
5125 g_assert (ins->sreg1 != ARMREG_LR);
5126 call = (MonoCallInst*)ins;
5129 code = emit_float_args (cfg, call, code, &max_len, &offset);
5130 if (!arm_is_imm12 (ins->inst_offset))
5131 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5132 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5133 if (!arm_is_imm12 (ins->inst_offset))
5134 ARM_LDR_REG_REG (code, ARMREG_PC, ins->sreg1, ARMREG_IP);
5136 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5137 ins->flags |= MONO_INST_GC_CALLSITE;
5138 ins->backend.pc_offset = code - cfg->native_code;
5139 code = emit_move_return_value (cfg, ins, code);
5142 case OP_GENERIC_CLASS_INIT: {
5143 static int byte_offset = -1;
5144 static guint8 bitmask;
5148 if (byte_offset < 0)
5149 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5151 g_assert (arm_is_imm8 (byte_offset));
5152 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5153 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5154 g_assert (imm8 >= 0);
5155 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5156 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5158 ARM_B_COND (code, ARMCOND_NE, 0);
5160 /* Uninitialized case */
5161 g_assert (ins->sreg1 == ARMREG_R0);
5163 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5164 (gpointer)"mono_generic_class_init");
5165 code = emit_call_seq (cfg, code);
5167 /* Initialized case */
5168 arm_patch (jump, code);
5172 /* round the size to 8 bytes */
5173 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5174 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5175 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5176 /* memzero the area: dreg holds the size, sp is the pointer */
5177 if (ins->flags & MONO_INST_INIT) {
5178 guint8 *start_loop, *branch_to_cond;
5179 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5180 branch_to_cond = code;
5183 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5184 arm_patch (branch_to_cond, code);
5185 /* decrement by 4 and set flags */
5186 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5187 ARM_B_COND (code, ARMCOND_GE, 0);
5188 arm_patch (code - 4, start_loop);
5190 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5191 if (cfg->param_area)
5192 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5197 MonoInst *var = cfg->dyn_call_var;
5199 g_assert (var->opcode == OP_REGOFFSET);
5200 g_assert (arm_is_imm12 (var->inst_offset));
5202 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5203 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
5205 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
5207 /* Save args buffer */
5208 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5210 /* Set stack slots using R0 as scratch reg */
5211 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5212 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5213 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5214 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5217 /* Set argument registers */
5218 for (i = 0; i < PARAM_REGS; ++i)
5219 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5222 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5223 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5226 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5227 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5228 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5232 if (ins->sreg1 != ARMREG_R0)
5233 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5234 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5235 (gpointer)"mono_arch_throw_exception");
5236 code = emit_call_seq (cfg, code);
5240 if (ins->sreg1 != ARMREG_R0)
5241 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5242 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5243 (gpointer)"mono_arch_rethrow_exception");
5244 code = emit_call_seq (cfg, code);
5247 case OP_START_HANDLER: {
5248 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5249 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5252 /* Reserve a param area, see filter-stack.exe */
5254 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5255 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5257 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5258 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5262 if (arm_is_imm12 (spvar->inst_offset)) {
5263 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5265 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5266 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5270 case OP_ENDFILTER: {
5271 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5272 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5275 /* Free the param area */
5277 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5278 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5280 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5281 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5285 if (ins->sreg1 != ARMREG_R0)
5286 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5287 if (arm_is_imm12 (spvar->inst_offset)) {
5288 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5290 g_assert (ARMREG_IP != spvar->inst_basereg);
5291 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5292 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5294 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5297 case OP_ENDFINALLY: {
5298 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5299 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5302 /* Free the param area */
5304 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5305 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5307 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5308 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5312 if (arm_is_imm12 (spvar->inst_offset)) {
5313 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5315 g_assert (ARMREG_IP != spvar->inst_basereg);
5316 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5317 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5319 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5322 case OP_CALL_HANDLER:
5323 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5324 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5325 cfg->thunk_area += THUNK_SIZE;
5326 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5329 if (ins->dreg != ARMREG_R0)
5330 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5334 ins->inst_c0 = code - cfg->native_code;
5337 /*if (ins->inst_target_bb->native_offset) {
5339 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5341 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5342 code = mono_arm_patchable_b (code, ARMCOND_AL);
5346 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5350 * In the normal case we have:
5351 * ldr pc, [pc, ins->sreg1 << 2]
5354 * ldr lr, [pc, ins->sreg1 << 2]
5356 * After follows the data.
5357 * FIXME: add aot support.
5359 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5360 #ifdef USE_JUMP_TABLES
5362 gpointer *jte = mono_jumptable_add_entries (GPOINTER_TO_INT (ins->klass));
5363 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5364 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_IP, ins->sreg1, ARMSHIFT_LSL, 2);
5368 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5369 if (offset + max_len > (cfg->code_size - 16)) {
5370 cfg->code_size += max_len;
5371 cfg->code_size *= 2;
5372 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5373 code = cfg->native_code + offset;
5375 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5377 code += 4 * GPOINTER_TO_INT (ins->klass);
5382 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5383 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5387 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5388 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5392 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5393 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5397 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5398 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5402 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5403 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5406 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5407 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5410 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5411 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5414 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5415 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5418 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5419 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5422 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5423 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5425 case OP_COND_EXC_EQ:
5426 case OP_COND_EXC_NE_UN:
5427 case OP_COND_EXC_LT:
5428 case OP_COND_EXC_LT_UN:
5429 case OP_COND_EXC_GT:
5430 case OP_COND_EXC_GT_UN:
5431 case OP_COND_EXC_GE:
5432 case OP_COND_EXC_GE_UN:
5433 case OP_COND_EXC_LE:
5434 case OP_COND_EXC_LE_UN:
5435 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5437 case OP_COND_EXC_IEQ:
5438 case OP_COND_EXC_INE_UN:
5439 case OP_COND_EXC_ILT:
5440 case OP_COND_EXC_ILT_UN:
5441 case OP_COND_EXC_IGT:
5442 case OP_COND_EXC_IGT_UN:
5443 case OP_COND_EXC_IGE:
5444 case OP_COND_EXC_IGE_UN:
5445 case OP_COND_EXC_ILE:
5446 case OP_COND_EXC_ILE_UN:
5447 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5450 case OP_COND_EXC_IC:
5451 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5453 case OP_COND_EXC_OV:
5454 case OP_COND_EXC_IOV:
5455 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5457 case OP_COND_EXC_NC:
5458 case OP_COND_EXC_INC:
5459 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5461 case OP_COND_EXC_NO:
5462 case OP_COND_EXC_INO:
5463 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5475 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5478 /* floating point opcodes */
5480 if (cfg->compile_aot) {
5481 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5483 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5485 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5488 /* FIXME: we can optimize the imm load by dealing with part of
5489 * the displacement in LDFD (aligning to 512).
5491 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5492 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5496 if (cfg->compile_aot) {
5497 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5499 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5502 ARM_CVTS (code, ins->dreg, ins->dreg);
5504 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5505 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5507 ARM_CVTS (code, ins->dreg, ins->dreg);
5510 case OP_STORER8_MEMBASE_REG:
5511 /* This is generated by the local regalloc pass which runs after the lowering pass */
5512 if (!arm_is_fpimm8 (ins->inst_offset)) {
5513 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5514 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5515 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5517 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5520 case OP_LOADR8_MEMBASE:
5521 /* This is generated by the local regalloc pass which runs after the lowering pass */
5522 if (!arm_is_fpimm8 (ins->inst_offset)) {
5523 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5524 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5525 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5527 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5530 case OP_STORER4_MEMBASE_REG:
5531 g_assert (arm_is_fpimm8 (ins->inst_offset));
5533 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5535 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5536 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5537 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5538 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5541 case OP_LOADR4_MEMBASE:
5543 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5545 g_assert (arm_is_fpimm8 (ins->inst_offset));
5546 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5547 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5548 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5549 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5552 case OP_ICONV_TO_R_UN: {
5553 g_assert_not_reached ();
5556 case OP_ICONV_TO_R4:
5558 ARM_FMSR (code, ins->dreg, ins->sreg1);
5559 ARM_FSITOS (code, ins->dreg, ins->dreg);
5561 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5562 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5563 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5564 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5565 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5568 case OP_ICONV_TO_R8:
5569 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5570 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5571 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5572 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5576 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5577 if (sig_ret->type == MONO_TYPE_R4) {
5579 g_assert (!IS_HARD_FLOAT);
5580 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5582 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5585 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5589 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5591 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5595 case OP_FCONV_TO_I1:
5596 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5598 case OP_FCONV_TO_U1:
5599 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5601 case OP_FCONV_TO_I2:
5602 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5604 case OP_FCONV_TO_U2:
5605 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5607 case OP_FCONV_TO_I4:
5609 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5611 case OP_FCONV_TO_U4:
5613 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5615 case OP_FCONV_TO_I8:
5616 case OP_FCONV_TO_U8:
5617 g_assert_not_reached ();
5618 /* Implemented as helper calls */
5620 case OP_LCONV_TO_R_UN:
5621 g_assert_not_reached ();
5622 /* Implemented as helper calls */
5624 case OP_LCONV_TO_OVF_I4_2: {
5625 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5627 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5630 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5631 high_bit_not_set = code;
5632 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5634 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5635 valid_negative = code;
5636 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5637 invalid_negative = code;
5638 ARM_B_COND (code, ARMCOND_AL, 0);
5640 arm_patch (high_bit_not_set, code);
5642 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5643 valid_positive = code;
5644 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5646 arm_patch (invalid_negative, code);
5647 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5649 arm_patch (valid_negative, code);
5650 arm_patch (valid_positive, code);
5652 if (ins->dreg != ins->sreg1)
5653 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5657 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5660 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5663 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5666 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5669 ARM_NEGD (code, ins->dreg, ins->sreg1);
5673 g_assert_not_reached ();
5677 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5683 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5688 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5691 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5692 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5696 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5699 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5700 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5704 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5707 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5708 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5709 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5713 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5716 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5717 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5721 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5724 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5725 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5726 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5730 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5733 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5734 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5738 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5741 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5742 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5746 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5749 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5750 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5753 /* ARM FPA flags table:
5754 * N Less than ARMCOND_MI
5755 * Z Equal ARMCOND_EQ
5756 * C Greater Than or Equal ARMCOND_CS
5757 * V Unordered ARMCOND_VS
5760 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5763 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5766 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5769 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5770 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5776 g_assert_not_reached ();
5780 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5782 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5783 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5784 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5788 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5789 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5794 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5795 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5797 #ifdef USE_JUMP_TABLES
5799 gpointer *jte = mono_jumptable_add_entries (2);
5800 jte [0] = GUINT_TO_POINTER (0xffffffff);
5801 jte [1] = GUINT_TO_POINTER (0x7fefffff);
5802 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_IP);
5803 ARM_FLDD (code, vfp_scratch1, ARMREG_IP, 0);
5806 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5807 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5809 *(guint32*)code = 0xffffffff;
5811 *(guint32*)code = 0x7fefffff;
5814 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5816 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
5817 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5819 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
5820 ARM_CPYD (code, ins->dreg, ins->sreg1);
5822 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5823 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5828 case OP_RCONV_TO_I1:
5829 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5831 case OP_RCONV_TO_U1:
5832 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5834 case OP_RCONV_TO_I2:
5835 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5837 case OP_RCONV_TO_U2:
5838 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5840 case OP_RCONV_TO_I4:
5841 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5843 case OP_RCONV_TO_U4:
5844 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5846 case OP_RCONV_TO_R4:
5848 if (ins->dreg != ins->sreg1)
5849 ARM_CPYS (code, ins->dreg, ins->sreg1);
5851 case OP_RCONV_TO_R8:
5853 ARM_CVTS (code, ins->dreg, ins->sreg1);
5856 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5859 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5862 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5865 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5868 ARM_NEGS (code, ins->dreg, ins->sreg1);
5872 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5875 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5876 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5880 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5883 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5884 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5888 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5891 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5892 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5893 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5897 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5900 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5901 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5905 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5908 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5909 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5910 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5914 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5917 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5918 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5922 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5925 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5926 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5930 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5933 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5934 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5937 case OP_GC_LIVENESS_DEF:
5938 case OP_GC_LIVENESS_USE:
5939 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5940 ins->backend.pc_offset = code - cfg->native_code;
5942 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5943 ins->backend.pc_offset = code - cfg->native_code;
5944 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5946 case OP_GC_SAFE_POINT: {
5947 const char *polling_func = NULL;
5950 g_assert (mono_threads_is_coop_enabled ());
5952 polling_func = "mono_threads_state_poll";
5953 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5954 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5956 ARM_B_COND (code, ARMCOND_EQ, 0);
5957 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5958 code = emit_call_seq (cfg, code);
5959 arm_patch (buf [0], code);
5964 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5965 g_assert_not_reached ();
5968 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5969 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5970 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5971 g_assert_not_reached ();
5977 last_offset = offset;
5980 cfg->code_len = code - cfg->native_code;
5983 #endif /* DISABLE_JIT */
5986 mono_arch_register_lowlevel_calls (void)
5988 /* The signature doesn't matter */
5989 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5990 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5991 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5993 #ifndef MONO_CROSS_COMPILE
5994 if (mono_arm_have_tls_get ()) {
5995 if (mono_arm_have_fast_tls ()) {
5996 mono_register_jit_icall (mono_fast_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5997 mono_register_jit_icall (mono_fast_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5999 mono_tramp_info_register (
6000 mono_tramp_info_create (
6002 (guint8*)mono_fast_get_tls_key,
6003 (guint8*)mono_fast_get_tls_key_end - (guint8*)mono_fast_get_tls_key,
6005 mono_arch_get_cie_program ()
6009 mono_tramp_info_register (
6010 mono_tramp_info_create (
6012 (guint8*)mono_fast_set_tls_key,
6013 (guint8*)mono_fast_set_tls_key_end - (guint8*)mono_fast_set_tls_key,
6015 mono_arch_get_cie_program ()
6020 g_warning ("No fast tls on device. Using fallbacks.");
6021 mono_register_jit_icall (mono_fallback_get_tls_key, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
6022 mono_register_jit_icall (mono_fallback_set_tls_key, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
6028 #define patch_lis_ori(ip,val) do {\
6029 guint16 *__lis_ori = (guint16*)(ip); \
6030 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
6031 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
6035 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6037 unsigned char *ip = ji->ip.i + code;
6039 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6043 case MONO_PATCH_INFO_SWITCH: {
6044 #ifdef USE_JUMP_TABLES
6045 gpointer *jt = mono_jumptable_get_entry (ip);
6047 gpointer *jt = (gpointer*)(ip + 8);
6050 /* jt is the inlined jump table, 2 instructions after ip
6051 * In the normal case we store the absolute addresses,
6052 * otherwise the displacements.
6054 for (i = 0; i < ji->data.table->table_size; i++)
6055 jt [i] = code + (int)ji->data.table->table [i];
6058 case MONO_PATCH_INFO_IP:
6059 g_assert_not_reached ();
6060 patch_lis_ori (ip, ip);
6062 case MONO_PATCH_INFO_METHOD_REL:
6063 g_assert_not_reached ();
6064 *((gpointer *)(ip)) = target;
6066 case MONO_PATCH_INFO_METHODCONST:
6067 case MONO_PATCH_INFO_CLASS:
6068 case MONO_PATCH_INFO_IMAGE:
6069 case MONO_PATCH_INFO_FIELD:
6070 case MONO_PATCH_INFO_VTABLE:
6071 case MONO_PATCH_INFO_IID:
6072 case MONO_PATCH_INFO_SFLDA:
6073 case MONO_PATCH_INFO_LDSTR:
6074 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6075 case MONO_PATCH_INFO_LDTOKEN:
6076 g_assert_not_reached ();
6077 /* from OP_AOTCONST : lis + ori */
6078 patch_lis_ori (ip, target);
6080 case MONO_PATCH_INFO_R4:
6081 case MONO_PATCH_INFO_R8:
6082 g_assert_not_reached ();
6083 *((gconstpointer *)(ip + 2)) = target;
6085 case MONO_PATCH_INFO_EXC_NAME:
6086 g_assert_not_reached ();
6087 *((gconstpointer *)(ip + 1)) = target;
6089 case MONO_PATCH_INFO_NONE:
6090 case MONO_PATCH_INFO_BB_OVF:
6091 case MONO_PATCH_INFO_EXC_OVF:
6092 /* everything is dealt with at epilog output time */
6095 arm_patch_general (cfg, domain, ip, target);
6101 mono_arm_unaligned_stack (MonoMethod *method)
6103 g_assert_not_reached ();
6109 * Stack frame layout:
6111 * ------------------- fp
6112 * MonoLMF structure or saved registers
6113 * -------------------
6115 * -------------------
6117 * -------------------
6118 * optional 8 bytes for tracing
6119 * -------------------
6120 * param area size is cfg->param_area
6121 * ------------------- sp
6124 mono_arch_emit_prolog (MonoCompile *cfg)
6126 MonoMethod *method = cfg->method;
6128 MonoMethodSignature *sig;
6130 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6135 int prev_sp_offset, reg_offset;
6137 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6140 sig = mono_method_signature (method);
6141 cfg->code_size = 256 + sig->param_count * 64;
6142 code = cfg->native_code = g_malloc (cfg->code_size);
6144 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6146 alloc_size = cfg->stack_offset;
6152 * The iphone uses R7 as the frame pointer, and it points at the saved
6157 * We can't use r7 as a frame pointer since it points into the middle of
6158 * the frame, so we keep using our own frame pointer.
6159 * FIXME: Optimize this.
6161 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6162 prev_sp_offset += 8; /* r7 and lr */
6163 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6164 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6165 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6168 if (!method->save_lmf) {
6170 /* No need to push LR again */
6171 if (cfg->used_int_regs)
6172 ARM_PUSH (code, cfg->used_int_regs);
6174 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6175 prev_sp_offset += 4;
6177 for (i = 0; i < 16; ++i) {
6178 if (cfg->used_int_regs & (1 << i))
6179 prev_sp_offset += 4;
6181 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6183 for (i = 0; i < 16; ++i) {
6184 if ((cfg->used_int_regs & (1 << i))) {
6185 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6186 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6191 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6192 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6194 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6195 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6198 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6199 ARM_PUSH (code, 0x5ff0);
6200 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6201 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6203 for (i = 0; i < 16; ++i) {
6204 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6205 /* The original r7 is saved at the start */
6206 if (!(iphone_abi && i == ARMREG_R7))
6207 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6211 g_assert (reg_offset == 4 * 10);
6212 pos += sizeof (MonoLMF) - (4 * 10);
6216 orig_alloc_size = alloc_size;
6217 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6218 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6219 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6220 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6223 /* the stack used in the pushed regs */
6224 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6225 cfg->stack_usage = alloc_size;
6227 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6228 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6230 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6231 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6233 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6235 if (cfg->frame_reg != ARMREG_SP) {
6236 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6237 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6239 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6240 prev_sp_offset += alloc_size;
6242 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6243 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6245 /* compute max_offset in order to use short forward jumps
6246 * we could skip do it on arm because the immediate displacement
6247 * for jumps is large enough, it may be useful later for constant pools
6250 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6251 MonoInst *ins = bb->code;
6252 bb->max_offset = max_offset;
6254 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6257 MONO_BB_FOR_EACH_INS (bb, ins)
6258 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6261 /* stack alignment check */
6265 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6266 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6267 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6268 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6270 ARM_B_COND (code, ARMCOND_EQ, 0);
6271 if (cfg->compile_aot)
6272 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6274 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6275 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6276 code = emit_call_seq (cfg, code);
6277 arm_patch (buf [0], code);
6281 /* store runtime generic context */
6282 if (cfg->rgctx_var) {
6283 MonoInst *ins = cfg->rgctx_var;
6285 g_assert (ins->opcode == OP_REGOFFSET);
6287 if (arm_is_imm12 (ins->inst_offset)) {
6288 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6290 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6291 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6295 /* load arguments allocated to register from the stack */
6298 cinfo = get_call_info (NULL, sig);
6300 if (cinfo->ret.storage == RegTypeStructByAddr) {
6301 ArgInfo *ainfo = &cinfo->ret;
6302 inst = cfg->vret_addr;
6303 g_assert (arm_is_imm12 (inst->inst_offset));
6304 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6307 if (sig->call_convention == MONO_CALL_VARARG) {
6308 ArgInfo *cookie = &cinfo->sig_cookie;
6310 /* Save the sig cookie address */
6311 g_assert (cookie->storage == RegTypeBase);
6313 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6314 g_assert (arm_is_imm12 (cfg->sig_cookie));
6315 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6316 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6319 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6320 ArgInfo *ainfo = cinfo->args + i;
6321 inst = cfg->args [pos];
6323 if (cfg->verbose_level > 2)
6324 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6326 if (inst->opcode == OP_REGVAR) {
6327 if (ainfo->storage == RegTypeGeneral)
6328 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6329 else if (ainfo->storage == RegTypeFP) {
6330 g_assert_not_reached ();
6331 } else if (ainfo->storage == RegTypeBase) {
6332 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6333 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6335 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6336 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6339 g_assert_not_reached ();
6341 if (cfg->verbose_level > 2)
6342 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6344 switch (ainfo->storage) {
6346 for (part = 0; part < ainfo->nregs; part ++) {
6347 if (ainfo->esize == 4)
6348 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6350 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6353 case RegTypeGeneral:
6354 case RegTypeIRegPair:
6355 case RegTypeGSharedVtInReg:
6356 switch (ainfo->size) {
6358 if (arm_is_imm12 (inst->inst_offset))
6359 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6361 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6362 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6366 if (arm_is_imm8 (inst->inst_offset)) {
6367 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6369 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6370 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6374 if (arm_is_imm12 (inst->inst_offset)) {
6375 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6377 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6378 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6380 if (arm_is_imm12 (inst->inst_offset + 4)) {
6381 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6383 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6384 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6388 if (arm_is_imm12 (inst->inst_offset)) {
6389 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6391 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6392 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6397 case RegTypeBaseGen:
6398 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6399 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6401 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6402 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6404 if (arm_is_imm12 (inst->inst_offset + 4)) {
6405 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6406 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6408 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6409 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6410 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6411 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6415 case RegTypeGSharedVtOnStack:
6416 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6417 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6419 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6420 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6423 switch (ainfo->size) {
6425 if (arm_is_imm8 (inst->inst_offset)) {
6426 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6428 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6429 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6433 if (arm_is_imm8 (inst->inst_offset)) {
6434 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6436 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6437 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6441 if (arm_is_imm12 (inst->inst_offset)) {
6442 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6444 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6445 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6447 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6448 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6450 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6451 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6453 if (arm_is_imm12 (inst->inst_offset + 4)) {
6454 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6456 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6457 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6461 if (arm_is_imm12 (inst->inst_offset)) {
6462 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6464 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6465 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6471 int imm8, rot_amount;
6473 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6474 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6475 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6477 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6479 if (ainfo->size == 8)
6480 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6482 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6485 case RegTypeStructByVal: {
6486 int doffset = inst->inst_offset;
6490 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6491 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6492 if (arm_is_imm12 (doffset)) {
6493 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6495 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6496 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6498 soffset += sizeof (gpointer);
6499 doffset += sizeof (gpointer);
6501 if (ainfo->vtsize) {
6502 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6503 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6504 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6508 case RegTypeStructByAddr:
6509 g_assert_not_reached ();
6510 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6511 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
6513 g_assert_not_reached ();
6520 if (method->save_lmf)
6521 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6524 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6526 if (cfg->arch.seq_point_info_var) {
6527 MonoInst *ins = cfg->arch.seq_point_info_var;
6529 /* Initialize the variable from a GOT slot */
6530 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6531 #ifdef USE_JUMP_TABLES
6533 gpointer *jte = mono_jumptable_add_entry ();
6534 code = mono_arm_load_jumptable_entry (code, jte, ARMREG_IP);
6535 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_IP, 0);
6537 /** XXX: is it correct? */
6539 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6541 *(gpointer*)code = NULL;
6544 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6546 g_assert (ins->opcode == OP_REGOFFSET);
6548 if (arm_is_imm12 (ins->inst_offset)) {
6549 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6551 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6552 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6556 /* Initialize ss_trigger_page_var */
6557 if (!cfg->soft_breakpoints) {
6558 MonoInst *info_var = cfg->arch.seq_point_info_var;
6559 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6560 int dreg = ARMREG_LR;
6563 g_assert (info_var->opcode == OP_REGOFFSET);
6564 g_assert (arm_is_imm12 (info_var->inst_offset));
6566 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6567 /* Load the trigger page addr */
6568 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6569 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6573 if (cfg->arch.seq_point_ss_method_var) {
6574 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6575 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6576 #ifdef USE_JUMP_TABLES
6579 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6580 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6581 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6582 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6584 #ifdef USE_JUMP_TABLES
6585 jte = mono_jumptable_add_entries (3);
6586 jte [0] = &single_step_tramp;
6587 jte [1] = breakpoint_tramp;
6588 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_LR);
6590 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6592 *(gpointer*)code = &single_step_tramp;
6594 *(gpointer*)code = breakpoint_tramp;
6598 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6599 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6600 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6601 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6604 cfg->code_len = code - cfg->native_code;
6605 g_assert (cfg->code_len < cfg->code_size);
6612 mono_arch_emit_epilog (MonoCompile *cfg)
6614 MonoMethod *method = cfg->method;
6615 int pos, i, rot_amount;
6616 int max_epilog_size = 16 + 20*4;
6620 if (cfg->method->save_lmf)
6621 max_epilog_size += 128;
6623 if (mono_jit_trace_calls != NULL)
6624 max_epilog_size += 50;
6626 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6627 max_epilog_size += 50;
6629 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6630 cfg->code_size *= 2;
6631 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6632 cfg->stat_code_reallocs++;
6636 * Keep in sync with OP_JMP
6638 code = cfg->native_code + cfg->code_len;
6640 /* Save the uwind state which is needed by the out-of-line code */
6641 mono_emit_unwind_op_remember_state (cfg, code);
6643 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6644 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6648 /* Load returned vtypes into registers if needed */
6649 cinfo = cfg->arch.cinfo;
6650 switch (cinfo->ret.storage) {
6651 case RegTypeStructByVal: {
6652 MonoInst *ins = cfg->ret;
6654 if (arm_is_imm12 (ins->inst_offset)) {
6655 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6657 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6658 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6663 MonoInst *ins = cfg->ret;
6665 for (i = 0; i < cinfo->ret.nregs; ++i) {
6666 if (cinfo->ret.esize == 4)
6667 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6669 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6677 if (method->save_lmf) {
6678 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6679 /* all but r0-r3, sp and pc */
6680 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6683 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6685 /* This points to r4 inside MonoLMF->iregs */
6686 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6688 regmask = 0x9ff0; /* restore lr to pc */
6689 /* Skip caller saved registers not used by the method */
6690 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6691 regmask &= ~(1 << reg);
6696 /* Restored later */
6697 regmask &= ~(1 << ARMREG_PC);
6698 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6699 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6700 for (i = 0; i < 16; i++) {
6701 if (regmask & (1 << i))
6704 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6706 ARM_POP (code, regmask);
6708 for (i = 0; i < 16; i++) {
6709 if (regmask & (1 << i))
6710 mono_emit_unwind_op_same_value (cfg, code, i);
6712 /* Restore saved r7, restore LR to PC */
6713 /* Skip lr from the lmf */
6714 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6715 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6716 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6717 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6720 int i, nused_int_regs = 0;
6722 for (i = 0; i < 16; i++) {
6723 if (cfg->used_int_regs & (1 << i))
6727 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6728 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6730 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6731 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6734 if (cfg->frame_reg != ARMREG_SP) {
6735 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6739 /* Restore saved gregs */
6740 if (cfg->used_int_regs) {
6741 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6742 ARM_POP (code, cfg->used_int_regs);
6743 for (i = 0; i < 16; i++) {
6744 if (cfg->used_int_regs & (1 << i))
6745 mono_emit_unwind_op_same_value (cfg, code, i);
6748 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6749 /* Restore saved r7, restore LR to PC */
6750 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6752 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6753 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6757 /* Restore the unwind state to be the same as before the epilog */
6758 mono_emit_unwind_op_restore_state (cfg, code);
6760 cfg->code_len = code - cfg->native_code;
6762 g_assert (cfg->code_len < cfg->code_size);
6767 mono_arch_emit_exceptions (MonoCompile *cfg)
6769 MonoJumpInfo *patch_info;
6772 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6773 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6774 int max_epilog_size = 50;
6776 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6777 exc_throw_pos [i] = NULL;
6778 exc_throw_found [i] = 0;
6781 /* count the number of exception infos */
6784 * make sure we have enough space for exceptions
6786 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6787 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6788 i = mini_exception_id_by_name (patch_info->data.target);
6789 if (!exc_throw_found [i]) {
6790 max_epilog_size += 32;
6791 exc_throw_found [i] = TRUE;
6796 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6797 cfg->code_size *= 2;
6798 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6799 cfg->stat_code_reallocs++;
6802 code = cfg->native_code + cfg->code_len;
6804 /* add code to raise exceptions */
6805 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6806 switch (patch_info->type) {
6807 case MONO_PATCH_INFO_EXC: {
6808 MonoClass *exc_class;
6809 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6811 i = mini_exception_id_by_name (patch_info->data.target);
6812 if (exc_throw_pos [i]) {
6813 arm_patch (ip, exc_throw_pos [i]);
6814 patch_info->type = MONO_PATCH_INFO_NONE;
6817 exc_throw_pos [i] = code;
6819 arm_patch (ip, code);
6821 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6822 g_assert (exc_class);
6824 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6825 #ifdef USE_JUMP_TABLES
6827 gpointer *jte = mono_jumptable_add_entries (2);
6828 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6829 patch_info->data.name = "mono_arch_throw_corlib_exception";
6830 patch_info->ip.i = code - cfg->native_code;
6831 code = mono_arm_load_jumptable_entry_addr (code, jte, ARMREG_R0);
6832 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, 0);
6833 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, 4);
6834 ARM_BLX_REG (code, ARMREG_IP);
6835 jte [1] = GUINT_TO_POINTER (exc_class->type_token);
6838 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6839 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6840 patch_info->data.name = "mono_arch_throw_corlib_exception";
6841 patch_info->ip.i = code - cfg->native_code;
6843 cfg->thunk_area += THUNK_SIZE;
6844 *(guint32*)(gpointer)code = exc_class->type_token;
6855 cfg->code_len = code - cfg->native_code;
6857 g_assert (cfg->code_len < cfg->code_size);
6861 #endif /* #ifndef DISABLE_JIT */
6864 mono_arch_finish_init (void)
6869 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6874 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6881 mono_arch_print_tree (MonoInst *tree, int arity)
6891 mono_arch_get_patch_offset (guint8 *code)
6898 mono_arch_flush_register_windows (void)
6903 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6905 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6909 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6911 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6915 mono_arch_get_cie_program (void)
6919 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6924 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6925 #define BASE_SIZE (6 * 4)
6926 #define BSEARCH_ENTRY_SIZE (4 * 4)
6927 #define CMP_SIZE (3 * 4)
6928 #define BRANCH_SIZE (1 * 4)
6929 #define CALL_SIZE (2 * 4)
6930 #define WMC_SIZE (8 * 4)
6931 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6933 #ifdef USE_JUMP_TABLES
6935 set_jumptable_element (gpointer *base, guint32 index, gpointer value)
6937 g_assert (base [index] == NULL);
6938 base [index] = value;
6941 load_element_with_regbase_cond (arminstr_t *code, ARMReg dreg, ARMReg base, guint32 jti, int cond)
6943 if (arm_is_imm12 (jti * 4)) {
6944 ARM_LDR_IMM_COND (code, dreg, base, jti * 4, cond);
6946 ARM_MOVW_REG_IMM_COND (code, dreg, (jti * 4) & 0xffff, cond);
6947 if ((jti * 4) >> 16)
6948 ARM_MOVT_REG_IMM_COND (code, dreg, ((jti * 4) >> 16) & 0xffff, cond);
6949 ARM_LDR_REG_REG_SHIFT_COND (code, dreg, base, dreg, ARMSHIFT_LSL, 0, cond);
6955 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6957 guint32 delta = DISTANCE (target, code);
6959 g_assert (delta >= 0 && delta <= 0xFFF);
6960 *target = *target | delta;
6966 #ifdef ENABLE_WRONG_METHOD_CHECK
6968 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6970 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6976 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6977 gpointer fail_tramp)
6980 arminstr_t *code, *start;
6981 #ifdef USE_JUMP_TABLES
6984 gboolean large_offsets = FALSE;
6985 guint32 **constant_pool_starts;
6986 arminstr_t *vtable_target = NULL;
6987 int extra_space = 0;
6989 #ifdef ENABLE_WRONG_METHOD_CHECK
6995 #ifdef USE_JUMP_TABLES
6996 for (i = 0; i < count; ++i) {
6997 MonoIMTCheckItem *item = imt_entries [i];
6998 item->chunk_size += 4 * 16;
6999 if (!item->is_equals)
7000 imt_entries [item->check_target_idx]->compare_done = TRUE;
7001 size += item->chunk_size;
7004 constant_pool_starts = g_new0 (guint32*, count);
7006 for (i = 0; i < count; ++i) {
7007 MonoIMTCheckItem *item = imt_entries [i];
7008 if (item->is_equals) {
7009 gboolean fail_case = !item->check_target_idx && fail_tramp;
7011 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
7012 item->chunk_size += 32;
7013 large_offsets = TRUE;
7016 if (item->check_target_idx || fail_case) {
7017 if (!item->compare_done || fail_case)
7018 item->chunk_size += CMP_SIZE;
7019 item->chunk_size += BRANCH_SIZE;
7021 #ifdef ENABLE_WRONG_METHOD_CHECK
7022 item->chunk_size += WMC_SIZE;
7026 item->chunk_size += 16;
7027 large_offsets = TRUE;
7029 item->chunk_size += CALL_SIZE;
7031 item->chunk_size += BSEARCH_ENTRY_SIZE;
7032 imt_entries [item->check_target_idx]->compare_done = TRUE;
7034 size += item->chunk_size;
7038 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
7042 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7044 code = mono_domain_code_reserve (domain, size);
7047 unwind_ops = mono_arch_get_cie_program ();
7050 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
7051 for (i = 0; i < count; ++i) {
7052 MonoIMTCheckItem *item = imt_entries [i];
7053 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
7057 #ifdef USE_JUMP_TABLES
7058 ARM_PUSH3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7059 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 3 * sizeof (mgreg_t));
7060 #define VTABLE_JTI 0
7061 #define IMT_METHOD_OFFSET 0
7062 #define TARGET_CODE_OFFSET 1
7063 #define JUMP_CODE_OFFSET 2
7064 #define RECORDS_PER_ENTRY 3
7065 #define IMT_METHOD_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + IMT_METHOD_OFFSET)
7066 #define TARGET_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + TARGET_CODE_OFFSET)
7067 #define JUMP_CODE_JTI(idx) (1 + idx * RECORDS_PER_ENTRY + JUMP_CODE_OFFSET)
7069 jte = mono_jumptable_add_entries (RECORDS_PER_ENTRY * count + 1 /* vtable */);
7070 code = (arminstr_t *) mono_arm_load_jumptable_entry_addr ((guint8 *) code, jte, ARMREG_R2);
7071 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R2, VTABLE_JTI);
7072 set_jumptable_element (jte, VTABLE_JTI, vtable);
7074 if (large_offsets) {
7075 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7076 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
7078 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
7079 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7081 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
7082 vtable_target = code;
7083 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
7085 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
7087 for (i = 0; i < count; ++i) {
7088 MonoIMTCheckItem *item = imt_entries [i];
7089 #ifdef USE_JUMP_TABLES
7090 guint32 imt_method_jti = 0, target_code_jti = 0;
7092 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
7094 gint32 vtable_offset;
7096 item->code_target = (guint8*)code;
7098 if (item->is_equals) {
7099 gboolean fail_case = !item->check_target_idx && fail_tramp;
7101 if (item->check_target_idx || fail_case) {
7102 if (!item->compare_done || fail_case) {
7103 #ifdef USE_JUMP_TABLES
7104 imt_method_jti = IMT_METHOD_JTI (i);
7105 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7108 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7110 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7112 #ifdef USE_JUMP_TABLES
7113 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_NE);
7114 ARM_BX_COND (code, ARMCOND_NE, ARMREG_R1);
7115 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7117 item->jmp_code = (guint8*)code;
7118 ARM_B_COND (code, ARMCOND_NE, 0);
7121 /*Enable the commented code to assert on wrong method*/
7122 #ifdef ENABLE_WRONG_METHOD_CHECK
7123 #ifdef USE_JUMP_TABLES
7124 imt_method_jti = IMT_METHOD_JTI (i);
7125 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, imt_method_jti, ARMCOND_AL);
7128 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7130 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7132 ARM_B_COND (code, ARMCOND_EQ, 0);
7134 /* Define this if your system is so bad that gdb is failing. */
7135 #ifdef BROKEN_DEV_ENV
7136 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
7138 arm_patch (code - 1, mini_dump_bad_imt);
7142 arm_patch (cond, code);
7146 if (item->has_target_code) {
7147 /* Load target address */
7148 #ifdef USE_JUMP_TABLES
7149 target_code_jti = TARGET_CODE_JTI (i);
7150 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7151 /* Restore registers */
7152 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7153 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7155 ARM_BX (code, ARMREG_R1);
7156 set_jumptable_element (jte, target_code_jti, item->value.target_code);
7158 target_code_ins = code;
7159 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7160 /* Save it to the fourth slot */
7161 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7162 /* Restore registers and branch */
7163 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7165 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7168 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7169 if (!arm_is_imm12 (vtable_offset)) {
7171 * We need to branch to a computed address but we don't have
7172 * a free register to store it, since IP must contain the
7173 * vtable address. So we push the two values to the stack, and
7174 * load them both using LDM.
7176 /* Compute target address */
7177 #ifdef USE_JUMP_TABLES
7178 ARM_MOVW_REG_IMM (code, ARMREG_R1, vtable_offset & 0xffff);
7179 if (vtable_offset >> 16)
7180 ARM_MOVT_REG_IMM (code, ARMREG_R1, (vtable_offset >> 16) & 0xffff);
7181 /* IP had vtable base. */
7182 ARM_LDR_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_R1);
7183 /* Restore registers and branch */
7184 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7185 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7186 ARM_BX (code, ARMREG_IP);
7188 vtable_offset_ins = code;
7189 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7190 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7191 /* Save it to the fourth slot */
7192 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7193 /* Restore registers and branch */
7194 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7196 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7199 #ifdef USE_JUMP_TABLES
7200 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_IP, vtable_offset);
7201 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7202 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7203 ARM_BX (code, ARMREG_IP);
7205 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7206 if (large_offsets) {
7207 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7208 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7210 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7211 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7217 #ifdef USE_JUMP_TABLES
7218 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), code);
7219 target_code_jti = TARGET_CODE_JTI (i);
7220 /* Load target address */
7221 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, target_code_jti, ARMCOND_AL);
7222 /* Restore registers */
7223 ARM_POP3 (code, ARMREG_R0, ARMREG_R1, ARMREG_R2);
7224 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7226 ARM_BX (code, ARMREG_R1);
7227 set_jumptable_element (jte, target_code_jti, fail_tramp);
7229 arm_patch (item->jmp_code, (guchar*)code);
7231 target_code_ins = code;
7232 /* Load target address */
7233 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7234 /* Save it to the fourth slot */
7235 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7236 /* Restore registers and branch */
7237 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7239 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7241 item->jmp_code = NULL;
7244 #ifdef USE_JUMP_TABLES
7246 set_jumptable_element (jte, imt_method_jti, item->key);
7249 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7251 /*must emit after unconditional branch*/
7252 if (vtable_target) {
7253 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7254 item->chunk_size += 4;
7255 vtable_target = NULL;
7258 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7259 constant_pool_starts [i] = code;
7261 code += extra_space;
7266 #ifdef USE_JUMP_TABLES
7267 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, IMT_METHOD_JTI (i), ARMCOND_AL);
7268 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7269 code = load_element_with_regbase_cond (code, ARMREG_R1, ARMREG_R2, JUMP_CODE_JTI (i), ARMCOND_HS);
7270 ARM_BX_COND (code, ARMCOND_HS, ARMREG_R1);
7271 item->jmp_code = GUINT_TO_POINTER (JUMP_CODE_JTI (i));
7273 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7274 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7276 item->jmp_code = (guint8*)code;
7277 ARM_B_COND (code, ARMCOND_HS, 0);
7283 for (i = 0; i < count; ++i) {
7284 MonoIMTCheckItem *item = imt_entries [i];
7285 if (item->jmp_code) {
7286 if (item->check_target_idx)
7287 #ifdef USE_JUMP_TABLES
7288 set_jumptable_element (jte, GPOINTER_TO_UINT (item->jmp_code), imt_entries [item->check_target_idx]->code_target);
7290 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7293 if (i > 0 && item->is_equals) {
7295 #ifdef USE_JUMP_TABLES
7296 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j)
7297 set_jumptable_element (jte, IMT_METHOD_JTI (j), imt_entries [j]->key);
7299 arminstr_t *space_start = constant_pool_starts [i];
7300 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7301 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7309 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7310 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7315 #ifndef USE_JUMP_TABLES
7316 g_free (constant_pool_starts);
7319 mono_arch_flush_icache ((guint8*)start, size);
7320 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7321 mono_stats.imt_thunks_size += code - start;
7323 g_assert (DISTANCE (start, code) <= size);
7325 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7331 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7333 return ctx->regs [reg];
7337 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7339 ctx->regs [reg] = val;
7343 * mono_arch_get_trampolines:
7345 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7349 mono_arch_get_trampolines (gboolean aot)
7351 return mono_arm_get_exception_trampolines (aot);
7355 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7362 bp = MONO_CONTEXT_GET_BP (ctx);
7363 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7365 old_value = *lr_loc;
7366 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7369 *lr_loc = new_value;
7374 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7376 * mono_arch_set_breakpoint:
7378 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7379 * The location should contain code emitted by OP_SEQ_POINT.
7382 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7385 guint32 native_offset = ip - (guint8*)ji->code_start;
7386 MonoDebugOptions *opt = mini_get_debug_options ();
7388 if (opt->soft_breakpoints) {
7389 g_assert (!ji->from_aot);
7391 ARM_BLX_REG (code, ARMREG_LR);
7392 mono_arch_flush_icache (code - 4, 4);
7393 } else if (ji->from_aot) {
7394 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7396 g_assert (native_offset % 4 == 0);
7397 g_assert (info->bp_addrs [native_offset / 4] == 0);
7398 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7400 int dreg = ARMREG_LR;
7402 /* Read from another trigger page */
7403 #ifdef USE_JUMP_TABLES
7404 gpointer *jte = mono_jumptable_add_entry ();
7405 code = mono_arm_load_jumptable_entry (code, jte, dreg);
7406 jte [0] = bp_trigger_page;
7408 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7410 *(int*)code = (int)bp_trigger_page;
7413 ARM_LDR_IMM (code, dreg, dreg, 0);
7415 mono_arch_flush_icache (code - 16, 16);
7418 /* This is currently implemented by emitting an SWI instruction, which
7419 * qemu/linux seems to convert to a SIGILL.
7421 *(int*)code = (0xef << 24) | 8;
7423 mono_arch_flush_icache (code - 4, 4);
7429 * mono_arch_clear_breakpoint:
7431 * Clear the breakpoint at IP.
7434 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7436 MonoDebugOptions *opt = mini_get_debug_options ();
7440 if (opt->soft_breakpoints) {
7441 g_assert (!ji->from_aot);
7444 mono_arch_flush_icache (code - 4, 4);
7445 } else if (ji->from_aot) {
7446 guint32 native_offset = ip - (guint8*)ji->code_start;
7447 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7449 g_assert (native_offset % 4 == 0);
7450 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7451 info->bp_addrs [native_offset / 4] = 0;
7453 for (i = 0; i < 4; ++i)
7456 mono_arch_flush_icache (ip, code - ip);
7461 * mono_arch_start_single_stepping:
7463 * Start single stepping.
7466 mono_arch_start_single_stepping (void)
7468 if (ss_trigger_page)
7469 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7471 single_step_tramp = mini_get_single_step_trampoline ();
7475 * mono_arch_stop_single_stepping:
7477 * Stop single stepping.
7480 mono_arch_stop_single_stepping (void)
7482 if (ss_trigger_page)
7483 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7485 single_step_tramp = NULL;
7489 #define DBG_SIGNAL SIGBUS
7491 #define DBG_SIGNAL SIGSEGV
7495 * mono_arch_is_single_step_event:
7497 * Return whenever the machine state in SIGCTX corresponds to a single
7501 mono_arch_is_single_step_event (void *info, void *sigctx)
7503 siginfo_t *sinfo = info;
7505 if (!ss_trigger_page)
7508 /* Sometimes the address is off by 4 */
7509 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7516 * mono_arch_is_breakpoint_event:
7518 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7521 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7523 siginfo_t *sinfo = info;
7525 if (!ss_trigger_page)
7528 if (sinfo->si_signo == DBG_SIGNAL) {
7529 /* Sometimes the address is off by 4 */
7530 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7540 * mono_arch_skip_breakpoint:
7542 * See mini-amd64.c for docs.
7545 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7547 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7551 * mono_arch_skip_single_step:
7553 * See mini-amd64.c for docs.
7556 mono_arch_skip_single_step (MonoContext *ctx)
7558 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7561 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7564 * mono_arch_get_seq_point_info:
7566 * See mini-amd64.c for docs.
7569 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7574 // FIXME: Add a free function
7576 mono_domain_lock (domain);
7577 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7579 mono_domain_unlock (domain);
7582 ji = mono_jit_info_table_find (domain, (char*)code);
7585 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7587 info->ss_trigger_page = ss_trigger_page;
7588 info->bp_trigger_page = bp_trigger_page;
7590 mono_domain_lock (domain);
7591 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7593 mono_domain_unlock (domain);
7600 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7602 ext->lmf.previous_lmf = prev_lmf;
7603 /* Mark that this is a MonoLMFExt */
7604 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7605 ext->lmf.sp = (gssize)ext;
7609 * mono_arch_set_target:
7611 * Set the target architecture the JIT backend should generate code for, in the form
7612 * of a GNU target triplet. Only used in AOT mode.
7615 mono_arch_set_target (char *mtriple)
7617 /* The GNU target triple format is not very well documented */
7618 if (strstr (mtriple, "armv7")) {
7619 v5_supported = TRUE;
7620 v6_supported = TRUE;
7621 v7_supported = TRUE;
7623 if (strstr (mtriple, "armv6")) {
7624 v5_supported = TRUE;
7625 v6_supported = TRUE;
7627 if (strstr (mtriple, "armv7s")) {
7628 v7s_supported = TRUE;
7630 if (strstr (mtriple, "armv7k")) {
7631 v7k_supported = TRUE;
7633 if (strstr (mtriple, "thumbv7s")) {
7634 v5_supported = TRUE;
7635 v6_supported = TRUE;
7636 v7_supported = TRUE;
7637 v7s_supported = TRUE;
7638 thumb_supported = TRUE;
7639 thumb2_supported = TRUE;
7641 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7642 v5_supported = TRUE;
7643 v6_supported = TRUE;
7644 thumb_supported = TRUE;
7647 if (strstr (mtriple, "gnueabi"))
7648 eabi_supported = TRUE;
7652 mono_arch_opcode_supported (int opcode)
7655 case OP_ATOMIC_ADD_I4:
7656 case OP_ATOMIC_EXCHANGE_I4:
7657 case OP_ATOMIC_CAS_I4:
7658 case OP_ATOMIC_LOAD_I1:
7659 case OP_ATOMIC_LOAD_I2:
7660 case OP_ATOMIC_LOAD_I4:
7661 case OP_ATOMIC_LOAD_U1:
7662 case OP_ATOMIC_LOAD_U2:
7663 case OP_ATOMIC_LOAD_U4:
7664 case OP_ATOMIC_STORE_I1:
7665 case OP_ATOMIC_STORE_I2:
7666 case OP_ATOMIC_STORE_I4:
7667 case OP_ATOMIC_STORE_U1:
7668 case OP_ATOMIC_STORE_U2:
7669 case OP_ATOMIC_STORE_U4:
7670 return v7_supported;
7671 case OP_ATOMIC_LOAD_R4:
7672 case OP_ATOMIC_LOAD_R8:
7673 case OP_ATOMIC_STORE_R4:
7674 case OP_ATOMIC_STORE_R8:
7675 return v7_supported && IS_VFP;
7681 #if defined(ENABLE_GSHAREDVT)
7683 #include "../../../mono-extensions/mono/mini/mini-arm-gsharedvt.c"
7685 #endif /* !MONOTOUCH */