2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
29 #include "debugger-agent.h"
31 #include "mono/arch/arm/arm-vfp-codegen.h"
33 /* Sanity check: This makes no sense */
34 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
35 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
39 * IS_SOFT_FLOAT: Is full software floating point used?
40 * IS_HARD_FLOAT: Is full hardware floating point used?
41 * IS_VFP: Is hardware floating point with software ABI used?
43 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
44 * IS_VFP may delegate to mono_arch_is_soft_float ().
47 #if defined(ARM_FPU_VFP_HARD)
48 #define IS_SOFT_FLOAT (FALSE)
49 #define IS_HARD_FLOAT (TRUE)
51 #elif defined(ARM_FPU_NONE)
52 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
53 #define IS_HARD_FLOAT (FALSE)
54 #define IS_VFP (!mono_arch_is_soft_float ())
56 #define IS_SOFT_FLOAT (FALSE)
57 #define IS_HARD_FLOAT (FALSE)
61 #define THUNK_SIZE (3 * 4)
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
66 void sys_icache_invalidate (void *start, size_t len);
69 /* This mutex protects architecture specific caches */
70 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
71 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
72 static mono_mutex_t mini_arch_mutex;
74 static gboolean v5_supported = FALSE;
75 static gboolean v6_supported = FALSE;
76 static gboolean v7_supported = FALSE;
77 static gboolean v7s_supported = FALSE;
78 static gboolean v7k_supported = FALSE;
79 static gboolean thumb_supported = FALSE;
80 static gboolean thumb2_supported = FALSE;
82 * Whenever to use the ARM EABI
84 static gboolean eabi_supported = FALSE;
87 * Whenever to use the iphone ABI extensions:
88 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
89 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
90 * This is required for debugging/profiling tools to work, but it has some overhead so it should
91 * only be turned on in debug builds.
93 static gboolean iphone_abi = FALSE;
96 * The FPU we are generating code for. This is NOT runtime configurable right now,
97 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
99 static MonoArmFPU arm_fpu;
101 #if defined(ARM_FPU_VFP_HARD)
103 * On armhf, d0-d7 are used for argument passing and d8-d15
104 * must be preserved across calls, which leaves us no room
105 * for scratch registers. So we use d14-d15 but back up their
106 * previous contents to a stack slot before using them - see
107 * mono_arm_emit_vfp_scratch_save/_restore ().
109 static int vfp_scratch1 = ARM_VFP_D14;
110 static int vfp_scratch2 = ARM_VFP_D15;
113 * On armel, d0-d7 do not need to be preserved, so we can
114 * freely make use of them as scratch registers.
116 static int vfp_scratch1 = ARM_VFP_D0;
117 static int vfp_scratch2 = ARM_VFP_D1;
122 static gpointer single_step_tramp, breakpoint_tramp;
123 static gpointer get_tls_tramp;
126 * The code generated for sequence points reads from this location, which is
127 * made read-only when single stepping is enabled.
129 static gpointer ss_trigger_page;
131 /* Enabled breakpoints read from this trigger page */
132 static gpointer bp_trigger_page;
136 * floating point support: on ARM it is a mess, there are at least 3
137 * different setups, each of which binary incompat with the other.
138 * 1) FPA: old and ugly, but unfortunately what current distros use
139 * the double binary format has the two words swapped. 8 double registers.
140 * Implemented usually by kernel emulation.
141 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
142 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
143 * 3) VFP: the new and actually sensible and useful FP support. Implemented
144 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
146 * We do not care about FPA. We will support soft float and VFP.
148 int mono_exc_esp_offset = 0;
150 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
151 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
152 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
154 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
155 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
156 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
158 //#define DEBUG_IMT 0
161 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data);
168 mono_arch_regname (int reg)
170 static const char * rnames[] = {
171 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
172 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
173 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
176 if (reg >= 0 && reg < 16)
182 mono_arch_fregname (int reg)
184 static const char * rnames[] = {
185 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
186 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
187 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
188 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
189 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
190 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
193 if (reg >= 0 && reg < 32)
201 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
203 int imm8, rot_amount;
204 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
205 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
209 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
210 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
212 code = mono_arm_emit_load_imm (code, dreg, imm);
213 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
218 /* If dreg == sreg, this clobbers IP */
220 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
222 int imm8, rot_amount;
223 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
224 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
228 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
229 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
231 code = mono_arm_emit_load_imm (code, dreg, imm);
232 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
238 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
240 /* we can use r0-r3, since this is called only for incoming args on the stack */
241 if (size > sizeof (gpointer) * 4) {
243 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
244 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
245 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
246 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
247 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
248 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
249 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
250 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
251 ARM_B_COND (code, ARMCOND_NE, 0);
252 arm_patch (code - 4, start_loop);
255 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
256 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
258 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
259 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
265 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
266 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
267 doffset = soffset = 0;
269 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
270 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
276 g_assert (size == 0);
281 emit_call_reg (guint8 *code, int reg)
284 ARM_BLX_REG (code, reg);
286 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
290 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
296 emit_call_seq (MonoCompile *cfg, guint8 *code)
298 if (cfg->method->dynamic) {
299 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
301 *(gpointer*)code = NULL;
303 code = emit_call_reg (code, ARMREG_IP);
307 cfg->thunk_area += THUNK_SIZE;
312 mono_arm_patchable_b (guint8 *code, int cond)
314 ARM_B_COND (code, cond, 0);
319 mono_arm_patchable_bl (guint8 *code, int cond)
321 ARM_BL_COND (code, cond, 0);
325 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID) && !defined(__native_client__)
326 #define HAVE_AEABI_READ_TP 1
329 #ifdef HAVE_AEABI_READ_TP
330 gpointer __aeabi_read_tp (void);
334 mono_arch_have_fast_tls (void)
336 #ifdef HAVE_AEABI_READ_TP
337 static gboolean have_fast_tls = FALSE;
338 static gboolean inited = FALSE;
341 if (mini_get_debug_options ()->use_fallback_tls)
345 return have_fast_tls;
347 tp1 = __aeabi_read_tp ();
348 asm volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tp2));
350 have_fast_tls = tp1 && tp1 == tp2;
352 return have_fast_tls;
359 emit_tls_get (guint8 *code, int dreg, int tls_offset)
361 ARM_MRC (code, 15, 0, dreg, 13, 0, 3);
362 ARM_LDR_IMM (code, dreg, dreg, tls_offset);
367 emit_tls_set (guint8 *code, int sreg, int tls_offset)
369 int tp_reg = (sreg != ARMREG_R0) ? ARMREG_R0 : ARMREG_R1;
370 ARM_MRC (code, 15, 0, tp_reg, 13, 0, 3);
371 ARM_STR_IMM (code, sreg, tp_reg, tls_offset);
378 * Emit code to push an LMF structure on the LMF stack.
379 * On arm, this is intermixed with the initialization of other fields of the structure.
382 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
386 if (mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR) != -1) {
387 code = emit_tls_get (code, ARMREG_R0, mono_tls_get_tls_offset (TLS_KEY_LMF_ADDR));
389 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
390 (gpointer)"mono_tls_get_lmf_addr");
391 code = emit_call_seq (cfg, code);
393 /* we build the MonoLMF structure on the stack - see mini-arm.h */
394 /* lmf_offset is the offset from the previous stack pointer,
395 * alloc_size is the total stack space allocated, so the offset
396 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
397 * The pointer to the struct is put in r1 (new_lmf).
398 * ip is used as scratch
399 * The callee-saved registers are already in the MonoLMF structure
401 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
402 /* r0 is the result from mono_get_lmf_addr () */
403 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
404 /* new_lmf->previous_lmf = *lmf_addr */
405 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
406 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
407 /* *(lmf_addr) = r1 */
408 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
409 /* Skip method (only needed for trampoline LMF frames) */
410 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
411 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
412 /* save the current IP */
413 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
414 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
416 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
417 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
428 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
432 for (list = inst->float_args; list; list = list->next) {
433 FloatArgData *fad = list->data;
434 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
435 gboolean imm = arm_is_fpimm8 (var->inst_offset);
437 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
443 if (*offset + *max_len > cfg->code_size) {
444 cfg->code_size += *max_len;
445 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
447 code = cfg->native_code + *offset;
451 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
452 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
454 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
456 *offset = code - cfg->native_code;
463 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
467 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
469 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
472 if (!arm_is_fpimm8 (inst->inst_offset)) {
473 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
474 ARM_FSTD (code, reg, ARMREG_LR, 0);
476 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
483 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
487 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
489 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
492 if (!arm_is_fpimm8 (inst->inst_offset)) {
493 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
494 ARM_FLDD (code, reg, ARMREG_LR, 0);
496 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
505 * Emit code to pop an LMF structure from the LMF stack.
508 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
512 if (lmf_offset < 32) {
513 basereg = cfg->frame_reg;
518 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
521 /* ip = previous_lmf */
522 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
524 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
525 /* *(lmf_addr) = previous_lmf */
526 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
531 #endif /* #ifndef DISABLE_JIT */
534 * mono_arch_get_argument_info:
535 * @csig: a method signature
536 * @param_count: the number of parameters to consider
537 * @arg_info: an array to store the result infos
539 * Gathers information on parameters such as size, alignment and
540 * padding. arg_info should be large enought to hold param_count + 1 entries.
542 * Returns the size of the activation frame.
545 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
547 int k, frame_size = 0;
548 guint32 size, align, pad;
552 t = mini_get_underlying_type (csig->ret);
553 if (MONO_TYPE_ISSTRUCT (t)) {
554 frame_size += sizeof (gpointer);
558 arg_info [0].offset = offset;
561 frame_size += sizeof (gpointer);
565 arg_info [0].size = frame_size;
567 for (k = 0; k < param_count; k++) {
568 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
570 /* ignore alignment for now */
573 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
574 arg_info [k].pad = pad;
576 arg_info [k + 1].pad = 0;
577 arg_info [k + 1].size = size;
579 arg_info [k + 1].offset = offset;
583 align = MONO_ARCH_FRAME_ALIGNMENT;
584 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
585 arg_info [k].pad = pad;
590 #define MAX_ARCH_DELEGATE_PARAMS 3
593 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
595 guint8 *code, *start;
596 GSList *unwind_ops = mono_arch_get_cie_program ();
599 start = code = mono_global_codeman_reserve (12);
601 /* Replace the this argument with the target */
602 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
603 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
604 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
606 g_assert ((code - start) <= 12);
608 mono_arch_flush_icache (start, 12);
612 size = 8 + param_count * 4;
613 start = code = mono_global_codeman_reserve (size);
615 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
616 /* slide down the arguments */
617 for (i = 0; i < param_count; ++i) {
618 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
620 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
622 g_assert ((code - start) <= size);
624 mono_arch_flush_icache (start, size);
628 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
630 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
631 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
635 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
641 * mono_arch_get_delegate_invoke_impls:
643 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
647 mono_arch_get_delegate_invoke_impls (void)
653 get_delegate_invoke_impl (&info, TRUE, 0);
654 res = g_slist_prepend (res, info);
656 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
657 get_delegate_invoke_impl (&info, FALSE, i);
658 res = g_slist_prepend (res, info);
665 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
667 guint8 *code, *start;
670 /* FIXME: Support more cases */
671 sig_ret = mini_get_underlying_type (sig->ret);
672 if (MONO_TYPE_ISSTRUCT (sig_ret))
676 static guint8* cached = NULL;
677 mono_mini_arch_lock ();
679 mono_mini_arch_unlock ();
684 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
687 start = get_delegate_invoke_impl (&info, TRUE, 0);
688 mono_tramp_info_register (info, NULL);
691 mono_mini_arch_unlock ();
694 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
697 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
699 for (i = 0; i < sig->param_count; ++i)
700 if (!mono_is_regsize_var (sig->params [i]))
703 mono_mini_arch_lock ();
704 code = cache [sig->param_count];
706 mono_mini_arch_unlock ();
711 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
712 start = mono_aot_get_trampoline (name);
716 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
717 mono_tramp_info_register (info, NULL);
719 cache [sig->param_count] = start;
720 mono_mini_arch_unlock ();
728 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
734 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
736 return (gpointer)regs [ARMREG_R0];
740 * Initialize the cpu to execute managed code.
743 mono_arch_cpu_init (void)
745 i8_align = MONO_ABI_ALIGNOF (gint64);
746 #ifdef MONO_CROSS_COMPILE
747 /* Need to set the alignment of i8 since it can different on the target */
748 #ifdef TARGET_ANDROID
750 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 const char *cpu_arch;
763 #ifdef TARGET_WATCHOS
764 mini_get_debug_options ()->soft_breakpoints = TRUE;
767 mono_os_mutex_init_recursive (&mini_arch_mutex);
768 if (mini_get_debug_options ()->soft_breakpoints) {
770 breakpoint_tramp = mini_get_breakpoint_trampoline ();
772 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
773 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT, MONO_MEM_ACCOUNT_OTHER);
774 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
777 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
778 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
779 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
780 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
781 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
783 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
785 #if defined(__ARM_EABI__)
786 eabi_supported = TRUE;
789 #if defined(ARM_FPU_VFP_HARD)
790 arm_fpu = MONO_ARM_FPU_VFP_HARD;
792 arm_fpu = MONO_ARM_FPU_VFP;
794 #if defined(ARM_FPU_NONE) && !defined(TARGET_IOS)
796 * If we're compiling with a soft float fallback and it
797 * turns out that no VFP unit is available, we need to
798 * switch to soft float. We don't do this for iOS, since
799 * iOS devices always have a VFP unit.
801 if (!mono_hwcap_arm_has_vfp)
802 arm_fpu = MONO_ARM_FPU_NONE;
805 * This environment variable can be useful in testing
806 * environments to make sure the soft float fallback
807 * works. Most ARM devices have VFP units these days, so
808 * normally soft float code would not be exercised much.
810 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
812 if (soft && !strncmp (soft, "1", 1))
813 arm_fpu = MONO_ARM_FPU_NONE;
817 v5_supported = mono_hwcap_arm_is_v5;
818 v6_supported = mono_hwcap_arm_is_v6;
819 v7_supported = mono_hwcap_arm_is_v7;
822 * On weird devices, the hwcap code may fail to detect
823 * the ARM version. In that case, we can at least safely
824 * assume the version the runtime was compiled for.
836 #if defined(TARGET_IOS)
837 /* iOS is special-cased here because we don't yet
838 have a way to properly detect CPU features on it. */
839 thumb_supported = TRUE;
842 thumb_supported = mono_hwcap_arm_has_thumb;
843 thumb2_supported = mono_hwcap_arm_has_thumb2;
846 /* Format: armv(5|6|7[s])[-thumb[2]] */
847 cpu_arch = g_getenv ("MONO_CPU_ARCH");
849 /* Do this here so it overrides any detection. */
851 if (strncmp (cpu_arch, "armv", 4) == 0) {
852 v5_supported = cpu_arch [4] >= '5';
853 v6_supported = cpu_arch [4] >= '6';
854 v7_supported = cpu_arch [4] >= '7';
855 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
856 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
859 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
860 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
865 * Cleanup architecture specific code.
868 mono_arch_cleanup (void)
873 * This function returns the optimizations supported on this cpu.
876 mono_arch_cpu_optimizations (guint32 *exclude_mask)
878 /* no arm-specific optimizations yet */
884 * This function test for all SIMD functions supported.
886 * Returns a bitmask corresponding to all supported versions.
890 mono_arch_cpu_enumerate_simd_versions (void)
892 /* SIMD is currently unimplemented */
897 mono_arm_is_hard_float (void)
899 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
905 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
907 if (v7s_supported || v7k_supported) {
921 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
923 mono_arch_is_soft_float (void)
925 return arm_fpu == MONO_ARM_FPU_NONE;
930 is_regsize_var (MonoType *t)
934 t = mini_get_underlying_type (t);
941 case MONO_TYPE_FNPTR:
943 case MONO_TYPE_OBJECT:
944 case MONO_TYPE_STRING:
945 case MONO_TYPE_CLASS:
946 case MONO_TYPE_SZARRAY:
947 case MONO_TYPE_ARRAY:
949 case MONO_TYPE_GENERICINST:
950 if (!mono_type_generic_inst_is_valuetype (t))
953 case MONO_TYPE_VALUETYPE:
960 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
965 for (i = 0; i < cfg->num_varinfo; i++) {
966 MonoInst *ins = cfg->varinfo [i];
967 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
970 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
973 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
976 /* we can only allocate 32 bit values */
977 if (is_regsize_var (ins->inst_vtype)) {
978 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
979 g_assert (i == vmv->idx);
980 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
988 mono_arch_get_global_int_regs (MonoCompile *cfg)
992 mono_arch_compute_omit_fp (cfg);
995 * FIXME: Interface calls might go through a static rgctx trampoline which
996 * sets V5, but it doesn't save it, so we need to save it ourselves, and
999 if (cfg->flags & MONO_CFG_HAS_CALLS)
1000 cfg->uses_rgctx_reg = TRUE;
1002 if (cfg->arch.omit_fp)
1003 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1004 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1005 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1006 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1008 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1009 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1011 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1012 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1013 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1014 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1015 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1016 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1022 * mono_arch_regalloc_cost:
1024 * Return the cost, in number of memory references, of the action of
1025 * allocating the variable VMV into a register during global register
1029 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1035 #endif /* #ifndef DISABLE_JIT */
1038 mono_arch_flush_icache (guint8 *code, gint size)
1040 #if defined(MONO_CROSS_COMPILE)
1042 sys_icache_invalidate (code, size);
1044 __builtin___clear_cache (code, code + size);
1051 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1054 if (*gr > ARMREG_R3) {
1056 ainfo->offset = *stack_size;
1057 ainfo->reg = ARMREG_SP; /* in the caller */
1058 ainfo->storage = RegTypeBase;
1061 ainfo->storage = RegTypeGeneral;
1068 split = i8_align == 4;
1073 if (*gr == ARMREG_R3 && split) {
1074 /* first word in r3 and the second on the stack */
1075 ainfo->offset = *stack_size;
1076 ainfo->reg = ARMREG_SP; /* in the caller */
1077 ainfo->storage = RegTypeBaseGen;
1079 } else if (*gr >= ARMREG_R3) {
1080 if (eabi_supported) {
1081 /* darwin aligns longs to 4 byte only */
1082 if (i8_align == 8) {
1087 ainfo->offset = *stack_size;
1088 ainfo->reg = ARMREG_SP; /* in the caller */
1089 ainfo->storage = RegTypeBase;
1092 if (eabi_supported) {
1093 if (i8_align == 8 && ((*gr) & 1))
1096 ainfo->storage = RegTypeIRegPair;
1105 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1108 * If we're calling a function like this:
1110 * void foo(float a, double b, float c)
1112 * We pass a in s0 and b in d1. That leaves us
1113 * with s1 being unused. The armhf ABI recognizes
1114 * this and requires register assignment to then
1115 * use that for the next single-precision arg,
1116 * i.e. c in this example. So float_spare either
1117 * tells us which reg to use for the next single-
1118 * precision arg, or it's -1, meaning use *fpr.
1120 * Note that even though most of the JIT speaks
1121 * double-precision, fpr represents single-
1122 * precision registers.
1124 * See parts 5.5 and 6.1.2 of the AAPCS for how
1128 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1129 ainfo->storage = RegTypeFP;
1133 * If we're passing a double-precision value
1134 * and *fpr is odd (e.g. it's s1, s3, ...)
1135 * we need to use the next even register. So
1136 * we mark the current *fpr as a spare that
1137 * can be used for the next single-precision
1141 *float_spare = *fpr;
1146 * At this point, we have an even register
1147 * so we assign that and move along.
1151 } else if (*float_spare >= 0) {
1153 * We're passing a single-precision value
1154 * and it looks like a spare single-
1155 * precision register is available. Let's
1159 ainfo->reg = *float_spare;
1163 * If we hit this branch, we're passing a
1164 * single-precision value and we can simply
1165 * use the next available register.
1173 * We've exhausted available floating point
1174 * regs, so pass the rest on the stack.
1182 ainfo->offset = *stack_size;
1183 ainfo->reg = ARMREG_SP;
1184 ainfo->storage = RegTypeBase;
1191 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1195 MonoClassField *field;
1196 MonoType *ftype, *prev_ftype = NULL;
1199 klass = mono_class_from_mono_type (t);
1201 while ((field = mono_class_get_fields (klass, &iter))) {
1202 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1204 ftype = mono_field_get_type (field);
1205 ftype = mini_get_underlying_type (ftype);
1207 if (MONO_TYPE_ISSTRUCT (ftype)) {
1208 int nested_nfields, nested_esize;
1210 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1212 if (nested_esize == 4)
1213 ftype = &mono_defaults.single_class->byval_arg;
1215 ftype = &mono_defaults.double_class->byval_arg;
1216 if (prev_ftype && prev_ftype->type != ftype->type)
1219 nfields += nested_nfields;
1221 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1223 if (prev_ftype && prev_ftype->type != ftype->type)
1229 if (nfields == 0 || nfields > 4)
1231 *out_nfields = nfields;
1232 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1237 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1239 guint i, gr, fpr, pstart;
1241 int n = sig->hasthis + sig->param_count;
1245 guint32 stack_size = 0;
1247 gboolean is_pinvoke = sig->pinvoke;
1248 gboolean vtype_retaddr = FALSE;
1251 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1253 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1260 t = mini_get_underlying_type (sig->ret);
1271 case MONO_TYPE_FNPTR:
1272 case MONO_TYPE_CLASS:
1273 case MONO_TYPE_OBJECT:
1274 case MONO_TYPE_SZARRAY:
1275 case MONO_TYPE_ARRAY:
1276 case MONO_TYPE_STRING:
1277 cinfo->ret.storage = RegTypeGeneral;
1278 cinfo->ret.reg = ARMREG_R0;
1282 cinfo->ret.storage = RegTypeIRegPair;
1283 cinfo->ret.reg = ARMREG_R0;
1287 cinfo->ret.storage = RegTypeFP;
1289 if (t->type == MONO_TYPE_R4)
1290 cinfo->ret.size = 4;
1292 cinfo->ret.size = 8;
1294 if (IS_HARD_FLOAT) {
1295 cinfo->ret.reg = ARM_VFP_F0;
1297 cinfo->ret.reg = ARMREG_R0;
1300 case MONO_TYPE_GENERICINST:
1301 if (!mono_type_generic_inst_is_valuetype (t)) {
1302 cinfo->ret.storage = RegTypeGeneral;
1303 cinfo->ret.reg = ARMREG_R0;
1306 if (mini_is_gsharedvt_variable_type (t)) {
1307 cinfo->ret.storage = RegTypeStructByAddr;
1311 case MONO_TYPE_VALUETYPE:
1312 case MONO_TYPE_TYPEDBYREF:
1313 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1314 cinfo->ret.storage = RegTypeHFA;
1316 cinfo->ret.nregs = nfields;
1317 cinfo->ret.esize = esize;
1320 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1323 #ifdef TARGET_WATCHOS
1328 if (native_size <= max_size) {
1329 cinfo->ret.storage = RegTypeStructByVal;
1330 cinfo->ret.struct_size = native_size;
1331 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1333 cinfo->ret.storage = RegTypeStructByAddr;
1336 cinfo->ret.storage = RegTypeStructByAddr;
1341 case MONO_TYPE_MVAR:
1342 g_assert (mini_is_gsharedvt_type (t));
1343 cinfo->ret.storage = RegTypeStructByAddr;
1345 case MONO_TYPE_VOID:
1348 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1351 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1356 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1357 * the first argument, allowing 'this' to be always passed in the first arg reg.
1358 * Also do this if the first argument is a reference type, since virtual calls
1359 * are sometimes made using calli without sig->hasthis set, like in the delegate
1362 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1364 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1366 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1370 cinfo->ret.reg = gr;
1372 cinfo->vret_arg_index = 1;
1376 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1379 if (vtype_retaddr) {
1380 cinfo->ret.reg = gr;
1385 DEBUG(g_print("params: %d\n", sig->param_count));
1386 for (i = pstart; i < sig->param_count; ++i) {
1387 ArgInfo *ainfo = &cinfo->args [n];
1389 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1390 /* Prevent implicit arguments and sig_cookie from
1391 being passed in registers */
1394 /* Emit the signature cookie just before the implicit arguments */
1395 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1397 DEBUG(g_print("param %d: ", i));
1398 if (sig->params [i]->byref) {
1399 DEBUG(g_print("byref\n"));
1400 add_general (&gr, &stack_size, ainfo, TRUE);
1404 t = mini_get_underlying_type (sig->params [i]);
1408 cinfo->args [n].size = 1;
1409 add_general (&gr, &stack_size, ainfo, TRUE);
1413 cinfo->args [n].size = 2;
1414 add_general (&gr, &stack_size, ainfo, TRUE);
1418 cinfo->args [n].size = 4;
1419 add_general (&gr, &stack_size, ainfo, TRUE);
1424 case MONO_TYPE_FNPTR:
1425 case MONO_TYPE_CLASS:
1426 case MONO_TYPE_OBJECT:
1427 case MONO_TYPE_STRING:
1428 case MONO_TYPE_SZARRAY:
1429 case MONO_TYPE_ARRAY:
1430 cinfo->args [n].size = sizeof (gpointer);
1431 add_general (&gr, &stack_size, ainfo, TRUE);
1433 case MONO_TYPE_GENERICINST:
1434 if (!mono_type_generic_inst_is_valuetype (t)) {
1435 cinfo->args [n].size = sizeof (gpointer);
1436 add_general (&gr, &stack_size, ainfo, TRUE);
1439 if (mini_is_gsharedvt_variable_type (t)) {
1440 /* gsharedvt arguments are passed by ref */
1441 g_assert (mini_is_gsharedvt_type (t));
1442 add_general (&gr, &stack_size, ainfo, TRUE);
1443 switch (ainfo->storage) {
1444 case RegTypeGeneral:
1445 ainfo->storage = RegTypeGSharedVtInReg;
1448 ainfo->storage = RegTypeGSharedVtOnStack;
1451 g_assert_not_reached ();
1456 case MONO_TYPE_TYPEDBYREF:
1457 case MONO_TYPE_VALUETYPE: {
1460 int nwords, nfields, esize;
1463 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1464 if (fpr + nfields < ARM_VFP_F16) {
1465 ainfo->storage = RegTypeHFA;
1467 ainfo->nregs = nfields;
1468 ainfo->esize = esize;
1479 if (t->type == MONO_TYPE_TYPEDBYREF) {
1480 size = sizeof (MonoTypedRef);
1481 align = sizeof (gpointer);
1483 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1485 size = mono_class_native_size (klass, &align);
1487 size = mini_type_stack_size_full (t, &align, FALSE);
1489 DEBUG(g_print ("load %d bytes struct\n", size));
1491 #ifdef TARGET_WATCHOS
1492 /* Watchos pass large structures by ref */
1493 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1494 if (sig->pinvoke && size > 16) {
1495 add_general (&gr, &stack_size, ainfo, TRUE);
1496 switch (ainfo->storage) {
1497 case RegTypeGeneral:
1498 ainfo->storage = RegTypeStructByAddr;
1501 ainfo->storage = RegTypeStructByAddrOnStack;
1504 g_assert_not_reached ();
1513 align_size += (sizeof (gpointer) - 1);
1514 align_size &= ~(sizeof (gpointer) - 1);
1515 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1516 ainfo->storage = RegTypeStructByVal;
1517 ainfo->struct_size = size;
1518 ainfo->align = align;
1519 /* FIXME: align stack_size if needed */
1520 if (eabi_supported) {
1521 if (align >= 8 && (gr & 1))
1524 if (gr > ARMREG_R3) {
1526 ainfo->vtsize = nwords;
1528 int rest = ARMREG_R3 - gr + 1;
1529 int n_in_regs = rest >= nwords? nwords: rest;
1531 ainfo->size = n_in_regs;
1532 ainfo->vtsize = nwords - n_in_regs;
1535 nwords -= n_in_regs;
1537 if (sig->call_convention == MONO_CALL_VARARG)
1538 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1539 stack_size = ALIGN_TO (stack_size, align);
1540 ainfo->offset = stack_size;
1541 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1542 stack_size += nwords * sizeof (gpointer);
1548 add_general (&gr, &stack_size, ainfo, FALSE);
1554 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1556 add_general (&gr, &stack_size, ainfo, TRUE);
1562 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1564 add_general (&gr, &stack_size, ainfo, FALSE);
1567 case MONO_TYPE_MVAR:
1568 /* gsharedvt arguments are passed by ref */
1569 g_assert (mini_is_gsharedvt_type (t));
1570 add_general (&gr, &stack_size, ainfo, TRUE);
1571 switch (ainfo->storage) {
1572 case RegTypeGeneral:
1573 ainfo->storage = RegTypeGSharedVtInReg;
1576 ainfo->storage = RegTypeGSharedVtOnStack;
1579 g_assert_not_reached ();
1583 g_error ("Can't handle 0x%x", sig->params [i]->type);
1588 /* Handle the case where there are no implicit arguments */
1589 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1590 /* Prevent implicit arguments and sig_cookie from
1591 being passed in registers */
1594 /* Emit the signature cookie just before the implicit arguments */
1595 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1598 /* align stack size to 8 */
1599 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1600 stack_size = (stack_size + 7) & ~7;
1602 cinfo->stack_usage = stack_size;
1608 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1610 MonoType *callee_ret;
1614 c1 = get_call_info (NULL, caller_sig);
1615 c2 = get_call_info (NULL, callee_sig);
1618 * Tail calls with more callee stack usage than the caller cannot be supported, since
1619 * the extra stack space would be left on the stack after the tail call.
1621 res = c1->stack_usage >= c2->stack_usage;
1622 callee_ret = mini_get_underlying_type (callee_sig->ret);
1623 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1624 /* An address on the callee's stack is passed as the first argument */
1627 if (c2->stack_usage > 16 * 4)
1639 debug_omit_fp (void)
1642 return mono_debug_count ();
1649 * mono_arch_compute_omit_fp:
1651 * Determine whenever the frame pointer can be eliminated.
1654 mono_arch_compute_omit_fp (MonoCompile *cfg)
1656 MonoMethodSignature *sig;
1657 MonoMethodHeader *header;
1661 if (cfg->arch.omit_fp_computed)
1664 header = cfg->header;
1666 sig = mono_method_signature (cfg->method);
1668 if (!cfg->arch.cinfo)
1669 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1670 cinfo = cfg->arch.cinfo;
1673 * FIXME: Remove some of the restrictions.
1675 cfg->arch.omit_fp = TRUE;
1676 cfg->arch.omit_fp_computed = TRUE;
1678 if (cfg->disable_omit_fp)
1679 cfg->arch.omit_fp = FALSE;
1680 if (!debug_omit_fp ())
1681 cfg->arch.omit_fp = FALSE;
1683 if (cfg->method->save_lmf)
1684 cfg->arch.omit_fp = FALSE;
1686 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1687 cfg->arch.omit_fp = FALSE;
1688 if (header->num_clauses)
1689 cfg->arch.omit_fp = FALSE;
1690 if (cfg->param_area)
1691 cfg->arch.omit_fp = FALSE;
1692 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1693 cfg->arch.omit_fp = FALSE;
1694 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1695 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1696 cfg->arch.omit_fp = FALSE;
1697 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1698 ArgInfo *ainfo = &cinfo->args [i];
1700 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1702 * The stack offset can only be determined when the frame
1705 cfg->arch.omit_fp = FALSE;
1710 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1711 MonoInst *ins = cfg->varinfo [i];
1714 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1719 * Set var information according to the calling convention. arm version.
1720 * The locals var stuff should most likely be split in another method.
1723 mono_arch_allocate_vars (MonoCompile *cfg)
1725 MonoMethodSignature *sig;
1726 MonoMethodHeader *header;
1729 int i, offset, size, align, curinst;
1734 sig = mono_method_signature (cfg->method);
1736 if (!cfg->arch.cinfo)
1737 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1738 cinfo = cfg->arch.cinfo;
1739 sig_ret = mini_get_underlying_type (sig->ret);
1741 mono_arch_compute_omit_fp (cfg);
1743 if (cfg->arch.omit_fp)
1744 cfg->frame_reg = ARMREG_SP;
1746 cfg->frame_reg = ARMREG_FP;
1748 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1750 /* allow room for the vararg method args: void* and long/double */
1751 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1752 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1754 header = cfg->header;
1756 /* See mono_arch_get_global_int_regs () */
1757 if (cfg->flags & MONO_CFG_HAS_CALLS)
1758 cfg->uses_rgctx_reg = TRUE;
1760 if (cfg->frame_reg != ARMREG_SP)
1761 cfg->used_int_regs |= 1 << cfg->frame_reg;
1763 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1764 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1765 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1769 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1770 if (sig_ret->type != MONO_TYPE_VOID) {
1771 cfg->ret->opcode = OP_REGVAR;
1772 cfg->ret->inst_c0 = ARMREG_R0;
1775 /* local vars are at a positive offset from the stack pointer */
1777 * also note that if the function uses alloca, we use FP
1778 * to point at the local variables.
1780 offset = 0; /* linkage area */
1781 /* align the offset to 16 bytes: not sure this is needed here */
1783 //offset &= ~(8 - 1);
1785 /* add parameter area size for called functions */
1786 offset += cfg->param_area;
1789 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1792 /* allow room to save the return value */
1793 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1796 switch (cinfo->ret.storage) {
1797 case RegTypeStructByVal:
1799 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1800 offset = ALIGN_TO (offset, 8);
1801 cfg->ret->opcode = OP_REGOFFSET;
1802 cfg->ret->inst_basereg = cfg->frame_reg;
1803 cfg->ret->inst_offset = offset;
1804 if (cinfo->ret.storage == RegTypeStructByVal)
1805 offset += cinfo->ret.nregs * sizeof (gpointer);
1809 case RegTypeStructByAddr:
1810 ins = cfg->vret_addr;
1811 offset += sizeof(gpointer) - 1;
1812 offset &= ~(sizeof(gpointer) - 1);
1813 ins->inst_offset = offset;
1814 ins->opcode = OP_REGOFFSET;
1815 ins->inst_basereg = cfg->frame_reg;
1816 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1817 g_print ("vret_addr =");
1818 mono_print_ins (cfg->vret_addr);
1820 offset += sizeof(gpointer);
1826 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1827 if (cfg->arch.seq_point_info_var) {
1830 ins = cfg->arch.seq_point_info_var;
1834 offset += align - 1;
1835 offset &= ~(align - 1);
1836 ins->opcode = OP_REGOFFSET;
1837 ins->inst_basereg = cfg->frame_reg;
1838 ins->inst_offset = offset;
1841 if (cfg->arch.ss_trigger_page_var) {
1844 ins = cfg->arch.ss_trigger_page_var;
1847 offset += align - 1;
1848 offset &= ~(align - 1);
1849 ins->opcode = OP_REGOFFSET;
1850 ins->inst_basereg = cfg->frame_reg;
1851 ins->inst_offset = offset;
1855 if (cfg->arch.seq_point_ss_method_var) {
1858 ins = cfg->arch.seq_point_ss_method_var;
1861 offset += align - 1;
1862 offset &= ~(align - 1);
1863 ins->opcode = OP_REGOFFSET;
1864 ins->inst_basereg = cfg->frame_reg;
1865 ins->inst_offset = offset;
1868 if (cfg->arch.seq_point_bp_method_var) {
1871 ins = cfg->arch.seq_point_bp_method_var;
1874 offset += align - 1;
1875 offset &= ~(align - 1);
1876 ins->opcode = OP_REGOFFSET;
1877 ins->inst_basereg = cfg->frame_reg;
1878 ins->inst_offset = offset;
1882 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1883 /* Allocate a temporary used by the atomic ops */
1887 /* Allocate a local slot to hold the sig cookie address */
1888 offset += align - 1;
1889 offset &= ~(align - 1);
1890 cfg->arch.atomic_tmp_offset = offset;
1893 cfg->arch.atomic_tmp_offset = -1;
1896 cfg->locals_min_stack_offset = offset;
1898 curinst = cfg->locals_start;
1899 for (i = curinst; i < cfg->num_varinfo; ++i) {
1902 ins = cfg->varinfo [i];
1903 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1906 t = ins->inst_vtype;
1907 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1910 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1911 * pinvoke wrappers when they call functions returning structure */
1912 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1913 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1917 size = mono_type_size (t, &align);
1919 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1920 * since it loads/stores misaligned words, which don't do the right thing.
1922 if (align < 4 && size >= 4)
1924 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1925 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1926 offset += align - 1;
1927 offset &= ~(align - 1);
1928 ins->opcode = OP_REGOFFSET;
1929 ins->inst_offset = offset;
1930 ins->inst_basereg = cfg->frame_reg;
1932 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1935 cfg->locals_max_stack_offset = offset;
1939 ins = cfg->args [curinst];
1940 if (ins->opcode != OP_REGVAR) {
1941 ins->opcode = OP_REGOFFSET;
1942 ins->inst_basereg = cfg->frame_reg;
1943 offset += sizeof (gpointer) - 1;
1944 offset &= ~(sizeof (gpointer) - 1);
1945 ins->inst_offset = offset;
1946 offset += sizeof (gpointer);
1951 if (sig->call_convention == MONO_CALL_VARARG) {
1955 /* Allocate a local slot to hold the sig cookie address */
1956 offset += align - 1;
1957 offset &= ~(align - 1);
1958 cfg->sig_cookie = offset;
1962 for (i = 0; i < sig->param_count; ++i) {
1963 ainfo = cinfo->args + i;
1965 ins = cfg->args [curinst];
1967 switch (ainfo->storage) {
1969 offset = ALIGN_TO (offset, 8);
1970 ins->opcode = OP_REGOFFSET;
1971 ins->inst_basereg = cfg->frame_reg;
1972 /* These arguments are saved to the stack in the prolog */
1973 ins->inst_offset = offset;
1974 if (cfg->verbose_level >= 2)
1975 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
1983 if (ins->opcode != OP_REGVAR) {
1984 ins->opcode = OP_REGOFFSET;
1985 ins->inst_basereg = cfg->frame_reg;
1986 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
1988 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1989 * since it loads/stores misaligned words, which don't do the right thing.
1991 if (align < 4 && size >= 4)
1993 /* The code in the prolog () stores words when storing vtypes received in a register */
1994 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1996 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1997 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1998 offset += align - 1;
1999 offset &= ~(align - 1);
2000 ins->inst_offset = offset;
2006 /* align the offset to 8 bytes */
2007 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2008 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2013 cfg->stack_offset = offset;
2017 mono_arch_create_vars (MonoCompile *cfg)
2019 MonoMethodSignature *sig;
2023 sig = mono_method_signature (cfg->method);
2025 if (!cfg->arch.cinfo)
2026 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2027 cinfo = cfg->arch.cinfo;
2029 if (IS_HARD_FLOAT) {
2030 for (i = 0; i < 2; i++) {
2031 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2032 inst->flags |= MONO_INST_VOLATILE;
2034 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2038 if (cinfo->ret.storage == RegTypeStructByVal)
2039 cfg->ret_var_is_local = TRUE;
2041 if (cinfo->ret.storage == RegTypeStructByAddr) {
2042 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2043 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2044 g_print ("vret_addr = ");
2045 mono_print_ins (cfg->vret_addr);
2049 if (cfg->gen_sdb_seq_points) {
2050 if (cfg->compile_aot) {
2051 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2052 ins->flags |= MONO_INST_VOLATILE;
2053 cfg->arch.seq_point_info_var = ins;
2055 if (!cfg->soft_breakpoints) {
2056 /* Allocate a separate variable for this to save 1 load per seq point */
2057 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2058 ins->flags |= MONO_INST_VOLATILE;
2059 cfg->arch.ss_trigger_page_var = ins;
2062 if (cfg->soft_breakpoints) {
2065 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2066 ins->flags |= MONO_INST_VOLATILE;
2067 cfg->arch.seq_point_ss_method_var = ins;
2069 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2070 ins->flags |= MONO_INST_VOLATILE;
2071 cfg->arch.seq_point_bp_method_var = ins;
2077 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2079 MonoMethodSignature *tmp_sig;
2082 if (call->tail_call)
2085 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2088 * mono_ArgIterator_Setup assumes the signature cookie is
2089 * passed first and all the arguments which were before it are
2090 * passed on the stack after the signature. So compensate by
2091 * passing a different signature.
2093 tmp_sig = mono_metadata_signature_dup (call->signature);
2094 tmp_sig->param_count -= call->signature->sentinelpos;
2095 tmp_sig->sentinelpos = 0;
2096 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2098 sig_reg = mono_alloc_ireg (cfg);
2099 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2101 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2106 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2111 LLVMCallInfo *linfo;
2113 n = sig->param_count + sig->hasthis;
2115 cinfo = get_call_info (cfg->mempool, sig);
2117 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2120 * LLVM always uses the native ABI while we use our own ABI, the
2121 * only difference is the handling of vtypes:
2122 * - we only pass/receive them in registers in some cases, and only
2123 * in 1 or 2 integer registers.
2125 switch (cinfo->ret.storage) {
2126 case RegTypeGeneral:
2129 case RegTypeIRegPair:
2131 case RegTypeStructByAddr:
2132 /* Vtype returned using a hidden argument */
2133 linfo->ret.storage = LLVMArgVtypeRetAddr;
2134 linfo->vret_arg_index = cinfo->vret_arg_index;
2137 case RegTypeStructByVal:
2138 /* LLVM models this by returning an int array */
2139 linfo->ret.storage = LLVMArgAsIArgs;
2140 linfo->ret.nslots = cinfo->ret.nregs;
2144 linfo->ret.storage = LLVMArgFpStruct;
2145 linfo->ret.nslots = cinfo->ret.nregs;
2146 linfo->ret.esize = cinfo->ret.esize;
2149 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2150 cfg->disable_llvm = TRUE;
2154 for (i = 0; i < n; ++i) {
2155 LLVMArgInfo *lainfo = &linfo->args [i];
2156 ainfo = cinfo->args + i;
2158 lainfo->storage = LLVMArgNone;
2160 switch (ainfo->storage) {
2161 case RegTypeGeneral:
2162 case RegTypeIRegPair:
2164 case RegTypeBaseGen:
2166 lainfo->storage = LLVMArgNormal;
2168 case RegTypeStructByVal:
2169 lainfo->storage = LLVMArgAsIArgs;
2170 if (eabi_supported && ainfo->align == 8) {
2171 /* LLVM models this by passing an int64 array */
2172 lainfo->nslots = ALIGN_TO (ainfo->struct_size, 8) / 8;
2175 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2179 printf ("D: %d\n", ainfo->align);
2181 case RegTypeStructByAddr:
2182 case RegTypeStructByAddrOnStack:
2183 lainfo->storage = LLVMArgVtypeByRef;
2188 lainfo->storage = LLVMArgAsFpArgs;
2189 lainfo->nslots = ainfo->nregs;
2190 lainfo->esize = ainfo->esize;
2191 for (j = 0; j < ainfo->nregs; ++j)
2192 lainfo->pair_storage [j] = LLVMArgInFPReg;
2196 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2197 cfg->disable_llvm = TRUE;
2207 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2210 MonoMethodSignature *sig;
2214 sig = call->signature;
2215 n = sig->param_count + sig->hasthis;
2217 cinfo = get_call_info (cfg->mempool, sig);
2219 switch (cinfo->ret.storage) {
2220 case RegTypeStructByVal:
2222 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2223 /* The JIT will transform this into a normal call */
2224 call->vret_in_reg = TRUE;
2227 if (call->inst.opcode == OP_TAILCALL)
2230 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2231 * the location pointed to by it after call in emit_move_return_value ().
2233 if (!cfg->arch.vret_addr_loc) {
2234 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2235 /* Prevent it from being register allocated or optimized away */
2236 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2239 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2241 case RegTypeStructByAddr: {
2243 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2244 vtarg->sreg1 = call->vret_var->dreg;
2245 vtarg->dreg = mono_alloc_preg (cfg);
2246 MONO_ADD_INS (cfg->cbb, vtarg);
2248 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2255 for (i = 0; i < n; ++i) {
2256 ArgInfo *ainfo = cinfo->args + i;
2259 if (i >= sig->hasthis)
2260 t = sig->params [i - sig->hasthis];
2262 t = &mono_defaults.int_class->byval_arg;
2263 t = mini_get_underlying_type (t);
2265 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2266 /* Emit the signature cookie just before the implicit arguments */
2267 emit_sig_cookie (cfg, call, cinfo);
2270 in = call->args [i];
2272 switch (ainfo->storage) {
2273 case RegTypeGeneral:
2274 case RegTypeIRegPair:
2275 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2276 MONO_INST_NEW (cfg, ins, OP_MOVE);
2277 ins->dreg = mono_alloc_ireg (cfg);
2278 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2279 MONO_ADD_INS (cfg->cbb, ins);
2280 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2282 MONO_INST_NEW (cfg, ins, OP_MOVE);
2283 ins->dreg = mono_alloc_ireg (cfg);
2284 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2285 MONO_ADD_INS (cfg->cbb, ins);
2286 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2287 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2288 if (ainfo->size == 4) {
2289 if (IS_SOFT_FLOAT) {
2290 /* mono_emit_call_args () have already done the r8->r4 conversion */
2291 /* The converted value is in an int vreg */
2292 MONO_INST_NEW (cfg, ins, OP_MOVE);
2293 ins->dreg = mono_alloc_ireg (cfg);
2294 ins->sreg1 = in->dreg;
2295 MONO_ADD_INS (cfg->cbb, ins);
2296 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2300 cfg->param_area = MAX (cfg->param_area, 8);
2301 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2302 creg = mono_alloc_ireg (cfg);
2303 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2304 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2307 if (IS_SOFT_FLOAT) {
2308 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2309 ins->dreg = mono_alloc_ireg (cfg);
2310 ins->sreg1 = in->dreg;
2311 MONO_ADD_INS (cfg->cbb, ins);
2312 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2314 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2315 ins->dreg = mono_alloc_ireg (cfg);
2316 ins->sreg1 = in->dreg;
2317 MONO_ADD_INS (cfg->cbb, ins);
2318 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2322 cfg->param_area = MAX (cfg->param_area, 8);
2323 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2324 creg = mono_alloc_ireg (cfg);
2325 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2326 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2327 creg = mono_alloc_ireg (cfg);
2328 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2329 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2332 cfg->flags |= MONO_CFG_HAS_FPOUT;
2334 MONO_INST_NEW (cfg, ins, OP_MOVE);
2335 ins->dreg = mono_alloc_ireg (cfg);
2336 ins->sreg1 = in->dreg;
2337 MONO_ADD_INS (cfg->cbb, ins);
2339 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2342 case RegTypeStructByVal:
2343 case RegTypeGSharedVtInReg:
2344 case RegTypeGSharedVtOnStack:
2346 case RegTypeStructByAddr:
2347 case RegTypeStructByAddrOnStack:
2348 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2349 ins->opcode = OP_OUTARG_VT;
2350 ins->sreg1 = in->dreg;
2351 ins->klass = in->klass;
2352 ins->inst_p0 = call;
2353 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2354 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2355 mono_call_inst_add_outarg_vt (cfg, call, ins);
2356 MONO_ADD_INS (cfg->cbb, ins);
2359 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2360 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2361 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2362 if (t->type == MONO_TYPE_R8) {
2363 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2366 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2368 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2371 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2374 case RegTypeBaseGen:
2375 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2376 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2377 MONO_INST_NEW (cfg, ins, OP_MOVE);
2378 ins->dreg = mono_alloc_ireg (cfg);
2379 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2380 MONO_ADD_INS (cfg->cbb, ins);
2381 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2382 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2385 /* This should work for soft-float as well */
2387 cfg->param_area = MAX (cfg->param_area, 8);
2388 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2389 creg = mono_alloc_ireg (cfg);
2390 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2391 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2392 creg = mono_alloc_ireg (cfg);
2393 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2394 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2395 cfg->flags |= MONO_CFG_HAS_FPOUT;
2397 g_assert_not_reached ();
2401 int fdreg = mono_alloc_freg (cfg);
2403 if (ainfo->size == 8) {
2404 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2405 ins->sreg1 = in->dreg;
2407 MONO_ADD_INS (cfg->cbb, ins);
2409 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2414 * Mono's register allocator doesn't speak single-precision registers that
2415 * overlap double-precision registers (i.e. armhf). So we have to work around
2416 * the register allocator and load the value from memory manually.
2418 * So we create a variable for the float argument and an instruction to store
2419 * the argument into the variable. We then store the list of these arguments
2420 * in call->float_args. This list is then used by emit_float_args later to
2421 * pass the arguments in the various call opcodes.
2423 * This is not very nice, and we should really try to fix the allocator.
2426 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2428 /* Make sure the instruction isn't seen as pointless and removed.
2430 float_arg->flags |= MONO_INST_VOLATILE;
2432 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2434 /* We use the dreg to look up the instruction later. The hreg is used to
2435 * emit the instruction that loads the value into the FP reg.
2437 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2438 fad->vreg = float_arg->dreg;
2439 fad->hreg = ainfo->reg;
2441 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2444 call->used_iregs |= 1 << ainfo->reg;
2445 cfg->flags |= MONO_CFG_HAS_FPOUT;
2449 g_assert_not_reached ();
2453 /* Handle the case where there are no implicit arguments */
2454 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2455 emit_sig_cookie (cfg, call, cinfo);
2457 call->call_info = cinfo;
2458 call->stack_usage = cinfo->stack_usage;
2462 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2468 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2469 ins->dreg = mono_alloc_freg (cfg);
2470 ins->sreg1 = arg->dreg;
2471 MONO_ADD_INS (cfg->cbb, ins);
2472 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2475 g_assert_not_reached ();
2481 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2483 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2485 ArgInfo *ainfo = ins->inst_p1;
2486 int ovf_size = ainfo->vtsize;
2487 int doffset = ainfo->offset;
2488 int struct_size = ainfo->struct_size;
2489 int i, soffset, dreg, tmpreg;
2491 switch (ainfo->storage) {
2492 case RegTypeGSharedVtInReg:
2493 case RegTypeStructByAddr:
2495 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2497 case RegTypeGSharedVtOnStack:
2498 case RegTypeStructByAddrOnStack:
2499 /* Pass by addr on stack */
2500 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2503 for (i = 0; i < ainfo->nregs; ++i) {
2504 if (ainfo->esize == 4)
2505 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2507 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2508 load->dreg = mono_alloc_freg (cfg);
2509 load->inst_basereg = src->dreg;
2510 load->inst_offset = i * ainfo->esize;
2511 MONO_ADD_INS (cfg->cbb, load);
2513 if (ainfo->esize == 4) {
2516 /* See RegTypeFP in mono_arch_emit_call () */
2517 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2518 float_arg->flags |= MONO_INST_VOLATILE;
2519 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2521 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2522 fad->vreg = float_arg->dreg;
2523 fad->hreg = ainfo->reg + i;
2525 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2527 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2533 for (i = 0; i < ainfo->size; ++i) {
2534 dreg = mono_alloc_ireg (cfg);
2535 switch (struct_size) {
2537 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2540 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2543 tmpreg = mono_alloc_ireg (cfg);
2544 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2545 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2546 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2547 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2548 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2549 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2550 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2553 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2556 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2557 soffset += sizeof (gpointer);
2558 struct_size -= sizeof (gpointer);
2560 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2562 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2568 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2570 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2573 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2576 if (COMPILE_LLVM (cfg)) {
2577 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2579 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2580 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2581 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2582 MONO_ADD_INS (cfg->cbb, ins);
2587 case MONO_ARM_FPU_NONE:
2588 if (ret->type == MONO_TYPE_R8) {
2591 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2592 ins->dreg = cfg->ret->dreg;
2593 ins->sreg1 = val->dreg;
2594 MONO_ADD_INS (cfg->cbb, ins);
2597 if (ret->type == MONO_TYPE_R4) {
2598 /* Already converted to an int in method_to_ir () */
2599 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2603 case MONO_ARM_FPU_VFP:
2604 case MONO_ARM_FPU_VFP_HARD:
2605 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2608 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2609 ins->dreg = cfg->ret->dreg;
2610 ins->sreg1 = val->dreg;
2611 MONO_ADD_INS (cfg->cbb, ins);
2616 g_assert_not_reached ();
2620 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2623 #endif /* #ifndef DISABLE_JIT */
2626 mono_arch_is_inst_imm (gint64 imm)
2632 MonoMethodSignature *sig;
2635 MonoType **param_types;
2639 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2643 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2646 switch (cinfo->ret.storage) {
2648 case RegTypeGeneral:
2649 case RegTypeIRegPair:
2650 case RegTypeStructByAddr:
2661 for (i = 0; i < cinfo->nargs; ++i) {
2662 ArgInfo *ainfo = &cinfo->args [i];
2665 switch (ainfo->storage) {
2666 case RegTypeGeneral:
2667 case RegTypeIRegPair:
2668 case RegTypeBaseGen:
2672 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2675 case RegTypeStructByVal:
2676 if (ainfo->size == 0)
2677 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2679 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2680 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2688 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2689 for (i = 0; i < sig->param_count; ++i) {
2690 MonoType *t = sig->params [i];
2695 t = mini_get_underlying_type (t);
2718 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2720 ArchDynCallInfo *info;
2724 cinfo = get_call_info (NULL, sig);
2726 if (!dyn_call_supported (cinfo, sig)) {
2731 info = g_new0 (ArchDynCallInfo, 1);
2732 // FIXME: Preprocess the info to speed up start_dyn_call ()
2734 info->cinfo = cinfo;
2735 info->rtype = mini_get_underlying_type (sig->ret);
2736 info->param_types = g_new0 (MonoType*, sig->param_count);
2737 for (i = 0; i < sig->param_count; ++i)
2738 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2740 return (MonoDynCallInfo*)info;
2744 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2746 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2748 g_free (ainfo->cinfo);
2753 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2755 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2756 DynCallArgs *p = (DynCallArgs*)buf;
2757 int arg_index, greg, i, j, pindex;
2758 MonoMethodSignature *sig = dinfo->sig;
2760 g_assert (buf_len >= sizeof (DynCallArgs));
2770 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2771 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2776 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2777 p->regs [greg ++] = (mgreg_t)ret;
2779 for (i = pindex; i < sig->param_count; i++) {
2780 MonoType *t = dinfo->param_types [i];
2781 gpointer *arg = args [arg_index ++];
2782 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2785 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2787 } else if (ainfo->storage == RegTypeFP) {
2788 } else if (ainfo->storage == RegTypeBase) {
2789 slot = PARAM_REGS + (ainfo->offset / 4);
2790 } else if (ainfo->storage == RegTypeBaseGen) {
2791 /* slot + 1 is the first stack slot, so the code below will work */
2794 g_assert_not_reached ();
2798 p->regs [slot] = (mgreg_t)*arg;
2803 case MONO_TYPE_STRING:
2804 case MONO_TYPE_CLASS:
2805 case MONO_TYPE_ARRAY:
2806 case MONO_TYPE_SZARRAY:
2807 case MONO_TYPE_OBJECT:
2811 p->regs [slot] = (mgreg_t)*arg;
2814 p->regs [slot] = *(guint8*)arg;
2817 p->regs [slot] = *(gint8*)arg;
2820 p->regs [slot] = *(gint16*)arg;
2823 p->regs [slot] = *(guint16*)arg;
2826 p->regs [slot] = *(gint32*)arg;
2829 p->regs [slot] = *(guint32*)arg;
2833 p->regs [slot ++] = (mgreg_t)arg [0];
2834 p->regs [slot] = (mgreg_t)arg [1];
2837 if (ainfo->storage == RegTypeFP) {
2838 float f = *(float*)arg;
2839 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2842 p->regs [slot] = *(mgreg_t*)arg;
2846 if (ainfo->storage == RegTypeFP) {
2847 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2850 p->regs [slot ++] = (mgreg_t)arg [0];
2851 p->regs [slot] = (mgreg_t)arg [1];
2854 case MONO_TYPE_GENERICINST:
2855 if (MONO_TYPE_IS_REFERENCE (t)) {
2856 p->regs [slot] = (mgreg_t)*arg;
2859 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2860 MonoClass *klass = mono_class_from_mono_type (t);
2861 guint8 *nullable_buf;
2864 size = mono_class_value_size (klass, NULL);
2865 nullable_buf = g_alloca (size);
2866 g_assert (nullable_buf);
2868 /* The argument pointed to by arg is either a boxed vtype or null */
2869 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2871 arg = (gpointer*)nullable_buf;
2877 case MONO_TYPE_VALUETYPE:
2878 g_assert (ainfo->storage == RegTypeStructByVal);
2880 if (ainfo->size == 0)
2881 slot = PARAM_REGS + (ainfo->offset / 4);
2885 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2886 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2889 g_assert_not_reached ();
2895 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2897 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2898 DynCallArgs *p = (DynCallArgs*)buf;
2899 MonoType *ptype = ainfo->rtype;
2900 guint8 *ret = p->ret;
2901 mgreg_t res = p->res;
2902 mgreg_t res2 = p->res2;
2904 switch (ptype->type) {
2905 case MONO_TYPE_VOID:
2906 *(gpointer*)ret = NULL;
2908 case MONO_TYPE_STRING:
2909 case MONO_TYPE_CLASS:
2910 case MONO_TYPE_ARRAY:
2911 case MONO_TYPE_SZARRAY:
2912 case MONO_TYPE_OBJECT:
2916 *(gpointer*)ret = (gpointer)res;
2922 *(guint8*)ret = res;
2925 *(gint16*)ret = res;
2928 *(guint16*)ret = res;
2931 *(gint32*)ret = res;
2934 *(guint32*)ret = res;
2938 /* This handles endianness as well */
2939 ((gint32*)ret) [0] = res;
2940 ((gint32*)ret) [1] = res2;
2942 case MONO_TYPE_GENERICINST:
2943 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2944 *(gpointer*)ret = (gpointer)res;
2949 case MONO_TYPE_VALUETYPE:
2950 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2956 *(float*)ret = *(float*)&p->fpregs [0];
2958 *(float*)ret = *(float*)&res;
2960 case MONO_TYPE_R8: {
2964 if (IS_HARD_FLOAT) {
2965 *(double*)ret = p->fpregs [0];
2970 *(double*)ret = *(double*)®s;
2975 g_assert_not_reached ();
2982 * Allow tracing to work with this interface (with an optional argument)
2986 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2990 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2991 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2992 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2993 code = emit_call_reg (code, ARMREG_R2);
3007 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3010 int save_mode = SAVE_NONE;
3012 MonoMethod *method = cfg->method;
3013 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3014 int rtype = ret_type->type;
3015 int save_offset = cfg->param_area;
3019 offset = code - cfg->native_code;
3020 /* we need about 16 instructions */
3021 if (offset > (cfg->code_size - 16 * 4)) {
3022 cfg->code_size *= 2;
3023 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3024 code = cfg->native_code + offset;
3027 case MONO_TYPE_VOID:
3028 /* special case string .ctor icall */
3029 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3030 save_mode = SAVE_ONE;
3032 save_mode = SAVE_NONE;
3036 save_mode = SAVE_TWO;
3040 save_mode = SAVE_ONE_FP;
3042 save_mode = SAVE_ONE;
3046 save_mode = SAVE_TWO_FP;
3048 save_mode = SAVE_TWO;
3050 case MONO_TYPE_GENERICINST:
3051 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3052 save_mode = SAVE_ONE;
3056 case MONO_TYPE_VALUETYPE:
3057 save_mode = SAVE_STRUCT;
3060 save_mode = SAVE_ONE;
3064 switch (save_mode) {
3066 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3067 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3068 if (enable_arguments) {
3069 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3070 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3074 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3075 if (enable_arguments) {
3076 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3080 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3081 if (enable_arguments) {
3082 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3086 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3087 if (enable_arguments) {
3088 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3092 if (enable_arguments) {
3093 /* FIXME: get the actual address */
3094 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3102 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3103 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3104 code = emit_call_reg (code, ARMREG_IP);
3106 switch (save_mode) {
3108 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3109 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3112 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3115 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3118 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3129 * The immediate field for cond branches is big enough for all reasonable methods
3131 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3132 if (0 && ins->inst_true_bb->native_offset) { \
3133 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3135 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3136 ARM_B_COND (code, (condcode), 0); \
3139 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3141 /* emit an exception if condition is fail
3143 * We assign the extra code used to throw the implicit exceptions
3144 * to cfg->bb_exit as far as the big branch handling is concerned
3146 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3148 mono_add_patch_info (cfg, code - cfg->native_code, \
3149 MONO_PATCH_INFO_EXC, exc_name); \
3150 ARM_BL_COND (code, (condcode), 0); \
3153 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3156 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3161 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3165 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3166 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3168 switch (ins->opcode) {
3171 /* Already done by an arch-independent pass */
3173 case OP_LOAD_MEMBASE:
3174 case OP_LOADI4_MEMBASE:
3176 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3177 * OP_LOAD_MEMBASE offset(basereg), reg
3179 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3180 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3181 ins->inst_basereg == last_ins->inst_destbasereg &&
3182 ins->inst_offset == last_ins->inst_offset) {
3183 if (ins->dreg == last_ins->sreg1) {
3184 MONO_DELETE_INS (bb, ins);
3187 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3188 ins->opcode = OP_MOVE;
3189 ins->sreg1 = last_ins->sreg1;
3193 * Note: reg1 must be different from the basereg in the second load
3194 * OP_LOAD_MEMBASE offset(basereg), reg1
3195 * OP_LOAD_MEMBASE offset(basereg), reg2
3197 * OP_LOAD_MEMBASE offset(basereg), reg1
3198 * OP_MOVE reg1, reg2
3200 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3201 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3202 ins->inst_basereg != last_ins->dreg &&
3203 ins->inst_basereg == last_ins->inst_basereg &&
3204 ins->inst_offset == last_ins->inst_offset) {
3206 if (ins->dreg == last_ins->dreg) {
3207 MONO_DELETE_INS (bb, ins);
3210 ins->opcode = OP_MOVE;
3211 ins->sreg1 = last_ins->dreg;
3214 //g_assert_not_reached ();
3218 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3219 * OP_LOAD_MEMBASE offset(basereg), reg
3221 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3222 * OP_ICONST reg, imm
3224 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3225 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3226 ins->inst_basereg == last_ins->inst_destbasereg &&
3227 ins->inst_offset == last_ins->inst_offset) {
3228 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3229 ins->opcode = OP_ICONST;
3230 ins->inst_c0 = last_ins->inst_imm;
3231 g_assert_not_reached (); // check this rule
3235 case OP_LOADU1_MEMBASE:
3236 case OP_LOADI1_MEMBASE:
3237 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3238 ins->inst_basereg == last_ins->inst_destbasereg &&
3239 ins->inst_offset == last_ins->inst_offset) {
3240 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3241 ins->sreg1 = last_ins->sreg1;
3244 case OP_LOADU2_MEMBASE:
3245 case OP_LOADI2_MEMBASE:
3246 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3247 ins->inst_basereg == last_ins->inst_destbasereg &&
3248 ins->inst_offset == last_ins->inst_offset) {
3249 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3250 ins->sreg1 = last_ins->sreg1;
3254 ins->opcode = OP_MOVE;
3258 if (ins->dreg == ins->sreg1) {
3259 MONO_DELETE_INS (bb, ins);
3263 * OP_MOVE sreg, dreg
3264 * OP_MOVE dreg, sreg
3266 if (last_ins && last_ins->opcode == OP_MOVE &&
3267 ins->sreg1 == last_ins->dreg &&
3268 ins->dreg == last_ins->sreg1) {
3269 MONO_DELETE_INS (bb, ins);
3278 * the branch_cc_table should maintain the order of these
3292 branch_cc_table [] = {
3306 #define ADD_NEW_INS(cfg,dest,op) do { \
3307 MONO_INST_NEW ((cfg), (dest), (op)); \
3308 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3312 map_to_reg_reg_op (int op)
3321 case OP_COMPARE_IMM:
3323 case OP_ICOMPARE_IMM:
3337 case OP_LOAD_MEMBASE:
3338 return OP_LOAD_MEMINDEX;
3339 case OP_LOADI4_MEMBASE:
3340 return OP_LOADI4_MEMINDEX;
3341 case OP_LOADU4_MEMBASE:
3342 return OP_LOADU4_MEMINDEX;
3343 case OP_LOADU1_MEMBASE:
3344 return OP_LOADU1_MEMINDEX;
3345 case OP_LOADI2_MEMBASE:
3346 return OP_LOADI2_MEMINDEX;
3347 case OP_LOADU2_MEMBASE:
3348 return OP_LOADU2_MEMINDEX;
3349 case OP_LOADI1_MEMBASE:
3350 return OP_LOADI1_MEMINDEX;
3351 case OP_STOREI1_MEMBASE_REG:
3352 return OP_STOREI1_MEMINDEX;
3353 case OP_STOREI2_MEMBASE_REG:
3354 return OP_STOREI2_MEMINDEX;
3355 case OP_STOREI4_MEMBASE_REG:
3356 return OP_STOREI4_MEMINDEX;
3357 case OP_STORE_MEMBASE_REG:
3358 return OP_STORE_MEMINDEX;
3359 case OP_STORER4_MEMBASE_REG:
3360 return OP_STORER4_MEMINDEX;
3361 case OP_STORER8_MEMBASE_REG:
3362 return OP_STORER8_MEMINDEX;
3363 case OP_STORE_MEMBASE_IMM:
3364 return OP_STORE_MEMBASE_REG;
3365 case OP_STOREI1_MEMBASE_IMM:
3366 return OP_STOREI1_MEMBASE_REG;
3367 case OP_STOREI2_MEMBASE_IMM:
3368 return OP_STOREI2_MEMBASE_REG;
3369 case OP_STOREI4_MEMBASE_IMM:
3370 return OP_STOREI4_MEMBASE_REG;
3372 g_assert_not_reached ();
3376 * Remove from the instruction list the instructions that can't be
3377 * represented with very simple instructions with no register
3381 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3383 MonoInst *ins, *temp, *last_ins = NULL;
3384 int rot_amount, imm8, low_imm;
3386 MONO_BB_FOR_EACH_INS (bb, ins) {
3388 switch (ins->opcode) {
3392 case OP_COMPARE_IMM:
3393 case OP_ICOMPARE_IMM:
3407 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3408 int opcode2 = mono_op_imm_to_op (ins->opcode);
3409 ADD_NEW_INS (cfg, temp, OP_ICONST);
3410 temp->inst_c0 = ins->inst_imm;
3411 temp->dreg = mono_alloc_ireg (cfg);
3412 ins->sreg2 = temp->dreg;
3414 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3415 ins->opcode = opcode2;
3417 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3423 if (ins->inst_imm == 1) {
3424 ins->opcode = OP_MOVE;
3427 if (ins->inst_imm == 0) {
3428 ins->opcode = OP_ICONST;
3432 imm8 = mono_is_power_of_two (ins->inst_imm);
3434 ins->opcode = OP_SHL_IMM;
3435 ins->inst_imm = imm8;
3438 ADD_NEW_INS (cfg, temp, OP_ICONST);
3439 temp->inst_c0 = ins->inst_imm;
3440 temp->dreg = mono_alloc_ireg (cfg);
3441 ins->sreg2 = temp->dreg;
3442 ins->opcode = OP_IMUL;
3448 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3449 /* ARM sets the C flag to 1 if there was _no_ overflow */
3450 ins->next->opcode = OP_COND_EXC_NC;
3453 case OP_IDIV_UN_IMM:
3455 case OP_IREM_UN_IMM: {
3456 int opcode2 = mono_op_imm_to_op (ins->opcode);
3457 ADD_NEW_INS (cfg, temp, OP_ICONST);
3458 temp->inst_c0 = ins->inst_imm;
3459 temp->dreg = mono_alloc_ireg (cfg);
3460 ins->sreg2 = temp->dreg;
3462 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3463 ins->opcode = opcode2;
3466 case OP_LOCALLOC_IMM:
3467 ADD_NEW_INS (cfg, temp, OP_ICONST);
3468 temp->inst_c0 = ins->inst_imm;
3469 temp->dreg = mono_alloc_ireg (cfg);
3470 ins->sreg1 = temp->dreg;
3471 ins->opcode = OP_LOCALLOC;
3473 case OP_LOAD_MEMBASE:
3474 case OP_LOADI4_MEMBASE:
3475 case OP_LOADU4_MEMBASE:
3476 case OP_LOADU1_MEMBASE:
3477 /* we can do two things: load the immed in a register
3478 * and use an indexed load, or see if the immed can be
3479 * represented as an ad_imm + a load with a smaller offset
3480 * that fits. We just do the first for now, optimize later.
3482 if (arm_is_imm12 (ins->inst_offset))
3484 ADD_NEW_INS (cfg, temp, OP_ICONST);
3485 temp->inst_c0 = ins->inst_offset;
3486 temp->dreg = mono_alloc_ireg (cfg);
3487 ins->sreg2 = temp->dreg;
3488 ins->opcode = map_to_reg_reg_op (ins->opcode);
3490 case OP_LOADI2_MEMBASE:
3491 case OP_LOADU2_MEMBASE:
3492 case OP_LOADI1_MEMBASE:
3493 if (arm_is_imm8 (ins->inst_offset))
3495 ADD_NEW_INS (cfg, temp, OP_ICONST);
3496 temp->inst_c0 = ins->inst_offset;
3497 temp->dreg = mono_alloc_ireg (cfg);
3498 ins->sreg2 = temp->dreg;
3499 ins->opcode = map_to_reg_reg_op (ins->opcode);
3501 case OP_LOADR4_MEMBASE:
3502 case OP_LOADR8_MEMBASE:
3503 if (arm_is_fpimm8 (ins->inst_offset))
3505 low_imm = ins->inst_offset & 0x1ff;
3506 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3507 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3508 temp->inst_imm = ins->inst_offset & ~0x1ff;
3509 temp->sreg1 = ins->inst_basereg;
3510 temp->dreg = mono_alloc_ireg (cfg);
3511 ins->inst_basereg = temp->dreg;
3512 ins->inst_offset = low_imm;
3516 ADD_NEW_INS (cfg, temp, OP_ICONST);
3517 temp->inst_c0 = ins->inst_offset;
3518 temp->dreg = mono_alloc_ireg (cfg);
3520 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3521 add_ins->sreg1 = ins->inst_basereg;
3522 add_ins->sreg2 = temp->dreg;
3523 add_ins->dreg = mono_alloc_ireg (cfg);
3525 ins->inst_basereg = add_ins->dreg;
3526 ins->inst_offset = 0;
3529 case OP_STORE_MEMBASE_REG:
3530 case OP_STOREI4_MEMBASE_REG:
3531 case OP_STOREI1_MEMBASE_REG:
3532 if (arm_is_imm12 (ins->inst_offset))
3534 ADD_NEW_INS (cfg, temp, OP_ICONST);
3535 temp->inst_c0 = ins->inst_offset;
3536 temp->dreg = mono_alloc_ireg (cfg);
3537 ins->sreg2 = temp->dreg;
3538 ins->opcode = map_to_reg_reg_op (ins->opcode);
3540 case OP_STOREI2_MEMBASE_REG:
3541 if (arm_is_imm8 (ins->inst_offset))
3543 ADD_NEW_INS (cfg, temp, OP_ICONST);
3544 temp->inst_c0 = ins->inst_offset;
3545 temp->dreg = mono_alloc_ireg (cfg);
3546 ins->sreg2 = temp->dreg;
3547 ins->opcode = map_to_reg_reg_op (ins->opcode);
3549 case OP_STORER4_MEMBASE_REG:
3550 case OP_STORER8_MEMBASE_REG:
3551 if (arm_is_fpimm8 (ins->inst_offset))
3553 low_imm = ins->inst_offset & 0x1ff;
3554 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3555 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3556 temp->inst_imm = ins->inst_offset & ~0x1ff;
3557 temp->sreg1 = ins->inst_destbasereg;
3558 temp->dreg = mono_alloc_ireg (cfg);
3559 ins->inst_destbasereg = temp->dreg;
3560 ins->inst_offset = low_imm;
3564 ADD_NEW_INS (cfg, temp, OP_ICONST);
3565 temp->inst_c0 = ins->inst_offset;
3566 temp->dreg = mono_alloc_ireg (cfg);
3568 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3569 add_ins->sreg1 = ins->inst_destbasereg;
3570 add_ins->sreg2 = temp->dreg;
3571 add_ins->dreg = mono_alloc_ireg (cfg);
3573 ins->inst_destbasereg = add_ins->dreg;
3574 ins->inst_offset = 0;
3577 case OP_STORE_MEMBASE_IMM:
3578 case OP_STOREI1_MEMBASE_IMM:
3579 case OP_STOREI2_MEMBASE_IMM:
3580 case OP_STOREI4_MEMBASE_IMM:
3581 ADD_NEW_INS (cfg, temp, OP_ICONST);
3582 temp->inst_c0 = ins->inst_imm;
3583 temp->dreg = mono_alloc_ireg (cfg);
3584 ins->sreg1 = temp->dreg;
3585 ins->opcode = map_to_reg_reg_op (ins->opcode);
3587 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3590 gboolean swap = FALSE;
3594 /* Optimized away */
3599 /* Some fp compares require swapped operands */
3600 switch (ins->next->opcode) {
3602 ins->next->opcode = OP_FBLT;
3606 ins->next->opcode = OP_FBLT_UN;
3610 ins->next->opcode = OP_FBGE;
3614 ins->next->opcode = OP_FBGE_UN;
3622 ins->sreg1 = ins->sreg2;
3631 bb->last_ins = last_ins;
3632 bb->max_vreg = cfg->next_vreg;
3636 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3640 if (long_ins->opcode == OP_LNEG) {
3642 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3643 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3649 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3651 /* sreg is a float, dreg is an integer reg */
3653 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3655 ARM_TOSIZD (code, vfp_scratch1, sreg);
3657 ARM_TOUIZD (code, vfp_scratch1, sreg);
3658 ARM_FMRS (code, dreg, vfp_scratch1);
3659 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3663 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3664 else if (size == 2) {
3665 ARM_SHL_IMM (code, dreg, dreg, 16);
3666 ARM_SHR_IMM (code, dreg, dreg, 16);
3670 ARM_SHL_IMM (code, dreg, dreg, 24);
3671 ARM_SAR_IMM (code, dreg, dreg, 24);
3672 } else if (size == 2) {
3673 ARM_SHL_IMM (code, dreg, dreg, 16);
3674 ARM_SAR_IMM (code, dreg, dreg, 16);
3681 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3683 /* sreg is a float, dreg is an integer reg */
3685 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3687 ARM_TOSIZS (code, vfp_scratch1, sreg);
3689 ARM_TOUIZS (code, vfp_scratch1, sreg);
3690 ARM_FMRS (code, dreg, vfp_scratch1);
3691 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3695 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3696 else if (size == 2) {
3697 ARM_SHL_IMM (code, dreg, dreg, 16);
3698 ARM_SHR_IMM (code, dreg, dreg, 16);
3702 ARM_SHL_IMM (code, dreg, dreg, 24);
3703 ARM_SAR_IMM (code, dreg, dreg, 24);
3704 } else if (size == 2) {
3705 ARM_SHL_IMM (code, dreg, dreg, 16);
3706 ARM_SAR_IMM (code, dreg, dreg, 16);
3712 #endif /* #ifndef DISABLE_JIT */
3714 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3717 emit_thunk (guint8 *code, gconstpointer target)
3721 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3722 if (thumb_supported)
3723 ARM_BX (code, ARMREG_IP);
3725 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3726 *(guint32*)code = (guint32)target;
3728 mono_arch_flush_icache (p, code - p);
3732 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3734 MonoJitInfo *ji = NULL;
3735 MonoThunkJitInfo *info;
3738 guint8 *orig_target;
3739 guint8 *target_thunk;
3742 domain = mono_domain_get ();
3746 * This can be called multiple times during JITting,
3747 * save the current position in cfg->arch to avoid
3748 * doing a O(n^2) search.
3750 if (!cfg->arch.thunks) {
3751 cfg->arch.thunks = cfg->thunks;
3752 cfg->arch.thunks_size = cfg->thunk_area;
3754 thunks = cfg->arch.thunks;
3755 thunks_size = cfg->arch.thunks_size;
3757 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3758 g_assert_not_reached ();
3761 g_assert (*(guint32*)thunks == 0);
3762 emit_thunk (thunks, target);
3763 arm_patch (code, thunks);
3765 cfg->arch.thunks += THUNK_SIZE;
3766 cfg->arch.thunks_size -= THUNK_SIZE;
3768 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3770 info = mono_jit_info_get_thunk_info (ji);
3773 thunks = (guint8*)ji->code_start + info->thunks_offset;
3774 thunks_size = info->thunks_size;
3776 orig_target = mono_arch_get_call_target (code + 4);
3778 mono_mini_arch_lock ();
3780 target_thunk = NULL;
3781 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3782 /* The call already points to a thunk, because of trampolines etc. */
3783 target_thunk = orig_target;
3785 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3786 if (((guint32*)p) [0] == 0) {
3790 } else if (((guint32*)p) [2] == (guint32)target) {
3791 /* Thunk already points to target */
3798 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3800 if (!target_thunk) {
3801 mono_mini_arch_unlock ();
3802 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3803 g_assert_not_reached ();
3806 emit_thunk (target_thunk, target);
3807 arm_patch (code, target_thunk);
3808 mono_arch_flush_icache (code, 4);
3810 mono_mini_arch_unlock ();
3815 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3817 guint32 *code32 = (void*)code;
3818 guint32 ins = *code32;
3819 guint32 prim = (ins >> 25) & 7;
3820 guint32 tval = GPOINTER_TO_UINT (target);
3822 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3823 if (prim == 5) { /* 101b */
3824 /* the diff starts 8 bytes from the branch opcode */
3825 gint diff = target - code - 8;
3827 gint tmask = 0xffffffff;
3828 if (tval & 1) { /* entering thumb mode */
3829 diff = target - 1 - code - 8;
3830 g_assert (thumb_supported);
3831 tbits = 0xf << 28; /* bl->blx bit pattern */
3832 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3833 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3837 tmask = ~(1 << 24); /* clear the link bit */
3838 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3843 if (diff <= 33554431) {
3845 ins = (ins & 0xff000000) | diff;
3847 *code32 = ins | tbits;
3851 /* diff between 0 and -33554432 */
3852 if (diff >= -33554432) {
3854 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3856 *code32 = ins | tbits;
3861 handle_thunk (cfg, domain, code, target);
3866 * The alternative call sequences looks like this:
3868 * ldr ip, [pc] // loads the address constant
3869 * b 1f // jumps around the constant
3870 * address constant embedded in the code
3875 * There are two cases for patching:
3876 * a) at the end of method emission: in this case code points to the start
3877 * of the call sequence
3878 * b) during runtime patching of the call site: in this case code points
3879 * to the mov pc, ip instruction
3881 * We have to handle also the thunk jump code sequence:
3885 * address constant // execution never reaches here
3887 if ((ins & 0x0ffffff0) == 0x12fff10) {
3888 /* Branch and exchange: the address is constructed in a reg
3889 * We can patch BX when the code sequence is the following:
3890 * ldr ip, [pc, #0] ; 0x8
3897 guint8 *emit = (guint8*)ccode;
3898 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3900 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3901 ARM_BX (emit, ARMREG_IP);
3903 /*patching from magic trampoline*/
3904 if (ins == ccode [3]) {
3905 g_assert (code32 [-4] == ccode [0]);
3906 g_assert (code32 [-3] == ccode [1]);
3907 g_assert (code32 [-1] == ccode [2]);
3908 code32 [-2] = (guint32)target;
3911 /*patching from JIT*/
3912 if (ins == ccode [0]) {
3913 g_assert (code32 [1] == ccode [1]);
3914 g_assert (code32 [3] == ccode [2]);
3915 g_assert (code32 [4] == ccode [3]);
3916 code32 [2] = (guint32)target;
3919 g_assert_not_reached ();
3920 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3928 guint8 *emit = (guint8*)ccode;
3929 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3931 ARM_BLX_REG (emit, ARMREG_IP);
3933 g_assert (code32 [-3] == ccode [0]);
3934 g_assert (code32 [-2] == ccode [1]);
3935 g_assert (code32 [0] == ccode [2]);
3937 code32 [-1] = (guint32)target;
3940 guint32 *tmp = ccode;
3941 guint8 *emit = (guint8*)tmp;
3942 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3943 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3944 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3945 ARM_BX (emit, ARMREG_IP);
3946 if (ins == ccode [2]) {
3947 g_assert_not_reached (); // should be -2 ...
3948 code32 [-1] = (guint32)target;
3951 if (ins == ccode [0]) {
3952 /* handles both thunk jump code and the far call sequence */
3953 code32 [2] = (guint32)target;
3956 g_assert_not_reached ();
3958 // g_print ("patched with 0x%08x\n", ins);
3962 arm_patch (guchar *code, const guchar *target)
3964 arm_patch_general (NULL, NULL, code, target);
3968 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3969 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3970 * to be used with the emit macros.
3971 * Return -1 otherwise.
3974 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3977 for (i = 0; i < 31; i+= 2) {
3978 res = (val << (32 - i)) | (val >> i);
3981 *rot_amount = i? 32 - i: 0;
3988 * Emits in code a sequence of instructions that load the value 'val'
3989 * into the dreg register. Uses at most 4 instructions.
3992 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3994 int imm8, rot_amount;
3996 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3997 /* skip the constant pool */
4003 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4004 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4005 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4009 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4010 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4011 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4012 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4015 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4017 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4021 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4023 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4025 if (val & 0xFF0000) {
4026 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4028 if (val & 0xFF000000) {
4029 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4031 } else if (val & 0xFF00) {
4032 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4033 if (val & 0xFF0000) {
4034 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4036 if (val & 0xFF000000) {
4037 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4039 } else if (val & 0xFF0000) {
4040 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4041 if (val & 0xFF000000) {
4042 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4045 //g_assert_not_reached ();
4051 mono_arm_thumb_supported (void)
4053 return thumb_supported;
4059 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4064 call = (MonoCallInst*)ins;
4065 cinfo = call->call_info;
4067 switch (cinfo->ret.storage) {
4068 case RegTypeStructByVal:
4070 MonoInst *loc = cfg->arch.vret_addr_loc;
4073 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4074 /* The JIT treats this as a normal call */
4078 /* Load the destination address */
4079 g_assert (loc && loc->opcode == OP_REGOFFSET);
4081 if (arm_is_imm12 (loc->inst_offset)) {
4082 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4084 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4085 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4088 if (cinfo->ret.storage == RegTypeStructByVal) {
4089 int rsize = cinfo->ret.struct_size;
4091 for (i = 0; i < cinfo->ret.nregs; ++i) {
4092 g_assert (rsize >= 0);
4097 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4100 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4103 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4109 for (i = 0; i < cinfo->ret.nregs; ++i) {
4110 if (cinfo->ret.esize == 4)
4111 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4113 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4122 switch (ins->opcode) {
4125 case OP_FCALL_MEMBASE:
4127 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4128 if (sig_ret->type == MONO_TYPE_R4) {
4129 if (IS_HARD_FLOAT) {
4130 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4132 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4133 ARM_CVTS (code, ins->dreg, ins->dreg);
4136 if (IS_HARD_FLOAT) {
4137 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4139 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4146 case OP_RCALL_MEMBASE: {
4151 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4152 g_assert (sig_ret->type == MONO_TYPE_R4);
4153 if (IS_HARD_FLOAT) {
4154 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4156 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4157 ARM_CPYS (code, ins->dreg, ins->dreg);
4169 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4174 guint8 *code = cfg->native_code + cfg->code_len;
4175 MonoInst *last_ins = NULL;
4176 guint last_offset = 0;
4178 int imm8, rot_amount;
4180 /* we don't align basic blocks of loops on arm */
4182 if (cfg->verbose_level > 2)
4183 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4185 cpos = bb->max_offset;
4187 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4188 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4189 //g_assert (!mono_compile_aot);
4192 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4193 /* this is not thread save, but good enough */
4194 /* fixme: howto handle overflows? */
4195 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4198 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4199 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4200 (gpointer)"mono_break");
4201 code = emit_call_seq (cfg, code);
4204 MONO_BB_FOR_EACH_INS (bb, ins) {
4205 offset = code - cfg->native_code;
4207 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4209 if (offset > (cfg->code_size - max_len - 16)) {
4210 cfg->code_size *= 2;
4211 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4212 code = cfg->native_code + offset;
4214 // if (ins->cil_code)
4215 // g_print ("cil code\n");
4216 mono_debug_record_line_number (cfg, ins, offset);
4218 switch (ins->opcode) {
4219 case OP_MEMORY_BARRIER:
4221 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4222 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4226 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4229 code = emit_tls_set (code, ins->sreg1, ins->inst_offset);
4231 case OP_ATOMIC_EXCHANGE_I4:
4232 case OP_ATOMIC_CAS_I4:
4233 case OP_ATOMIC_ADD_I4: {
4237 g_assert (v7_supported);
4240 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4242 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4244 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4248 g_assert (cfg->arch.atomic_tmp_offset != -1);
4249 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4251 switch (ins->opcode) {
4252 case OP_ATOMIC_EXCHANGE_I4:
4254 ARM_DMB (code, ARM_DMB_SY);
4255 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4256 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4257 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4259 ARM_B_COND (code, ARMCOND_NE, 0);
4260 arm_patch (buf [1], buf [0]);
4262 case OP_ATOMIC_CAS_I4:
4263 ARM_DMB (code, ARM_DMB_SY);
4265 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4266 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4268 ARM_B_COND (code, ARMCOND_NE, 0);
4269 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4270 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4272 ARM_B_COND (code, ARMCOND_NE, 0);
4273 arm_patch (buf [2], buf [0]);
4274 arm_patch (buf [1], code);
4276 case OP_ATOMIC_ADD_I4:
4278 ARM_DMB (code, ARM_DMB_SY);
4279 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4280 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4281 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4282 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4284 ARM_B_COND (code, ARMCOND_NE, 0);
4285 arm_patch (buf [1], buf [0]);
4288 g_assert_not_reached ();
4291 ARM_DMB (code, ARM_DMB_SY);
4292 if (tmpreg != ins->dreg)
4293 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4294 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4297 case OP_ATOMIC_LOAD_I1:
4298 case OP_ATOMIC_LOAD_U1:
4299 case OP_ATOMIC_LOAD_I2:
4300 case OP_ATOMIC_LOAD_U2:
4301 case OP_ATOMIC_LOAD_I4:
4302 case OP_ATOMIC_LOAD_U4:
4303 case OP_ATOMIC_LOAD_R4:
4304 case OP_ATOMIC_LOAD_R8: {
4305 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4306 ARM_DMB (code, ARM_DMB_SY);
4308 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4310 switch (ins->opcode) {
4311 case OP_ATOMIC_LOAD_I1:
4312 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4314 case OP_ATOMIC_LOAD_U1:
4315 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4317 case OP_ATOMIC_LOAD_I2:
4318 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4320 case OP_ATOMIC_LOAD_U2:
4321 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4323 case OP_ATOMIC_LOAD_I4:
4324 case OP_ATOMIC_LOAD_U4:
4325 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4327 case OP_ATOMIC_LOAD_R4:
4329 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4330 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4332 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4333 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4334 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4335 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4336 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4339 case OP_ATOMIC_LOAD_R8:
4340 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4341 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4345 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4346 ARM_DMB (code, ARM_DMB_SY);
4349 case OP_ATOMIC_STORE_I1:
4350 case OP_ATOMIC_STORE_U1:
4351 case OP_ATOMIC_STORE_I2:
4352 case OP_ATOMIC_STORE_U2:
4353 case OP_ATOMIC_STORE_I4:
4354 case OP_ATOMIC_STORE_U4:
4355 case OP_ATOMIC_STORE_R4:
4356 case OP_ATOMIC_STORE_R8: {
4357 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4358 ARM_DMB (code, ARM_DMB_SY);
4360 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4362 switch (ins->opcode) {
4363 case OP_ATOMIC_STORE_I1:
4364 case OP_ATOMIC_STORE_U1:
4365 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4367 case OP_ATOMIC_STORE_I2:
4368 case OP_ATOMIC_STORE_U2:
4369 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4371 case OP_ATOMIC_STORE_I4:
4372 case OP_ATOMIC_STORE_U4:
4373 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4375 case OP_ATOMIC_STORE_R4:
4377 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4378 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4380 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4381 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4382 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4383 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4384 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4387 case OP_ATOMIC_STORE_R8:
4388 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4389 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4393 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4394 ARM_DMB (code, ARM_DMB_SY);
4398 ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4401 ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
4403 case OP_STOREI1_MEMBASE_IMM:
4404 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4405 g_assert (arm_is_imm12 (ins->inst_offset));
4406 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4408 case OP_STOREI2_MEMBASE_IMM:
4409 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4410 g_assert (arm_is_imm8 (ins->inst_offset));
4411 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4413 case OP_STORE_MEMBASE_IMM:
4414 case OP_STOREI4_MEMBASE_IMM:
4415 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4416 g_assert (arm_is_imm12 (ins->inst_offset));
4417 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4419 case OP_STOREI1_MEMBASE_REG:
4420 g_assert (arm_is_imm12 (ins->inst_offset));
4421 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4423 case OP_STOREI2_MEMBASE_REG:
4424 g_assert (arm_is_imm8 (ins->inst_offset));
4425 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4427 case OP_STORE_MEMBASE_REG:
4428 case OP_STOREI4_MEMBASE_REG:
4429 /* this case is special, since it happens for spill code after lowering has been called */
4430 if (arm_is_imm12 (ins->inst_offset)) {
4431 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4433 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4434 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4437 case OP_STOREI1_MEMINDEX:
4438 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4440 case OP_STOREI2_MEMINDEX:
4441 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4443 case OP_STORE_MEMINDEX:
4444 case OP_STOREI4_MEMINDEX:
4445 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4448 g_assert_not_reached ();
4450 case OP_LOAD_MEMINDEX:
4451 case OP_LOADI4_MEMINDEX:
4452 case OP_LOADU4_MEMINDEX:
4453 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4455 case OP_LOADI1_MEMINDEX:
4456 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4458 case OP_LOADU1_MEMINDEX:
4459 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4461 case OP_LOADI2_MEMINDEX:
4462 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4464 case OP_LOADU2_MEMINDEX:
4465 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4467 case OP_LOAD_MEMBASE:
4468 case OP_LOADI4_MEMBASE:
4469 case OP_LOADU4_MEMBASE:
4470 /* this case is special, since it happens for spill code after lowering has been called */
4471 if (arm_is_imm12 (ins->inst_offset)) {
4472 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4474 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4475 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4478 case OP_LOADI1_MEMBASE:
4479 g_assert (arm_is_imm8 (ins->inst_offset));
4480 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4482 case OP_LOADU1_MEMBASE:
4483 g_assert (arm_is_imm12 (ins->inst_offset));
4484 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4486 case OP_LOADU2_MEMBASE:
4487 g_assert (arm_is_imm8 (ins->inst_offset));
4488 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4490 case OP_LOADI2_MEMBASE:
4491 g_assert (arm_is_imm8 (ins->inst_offset));
4492 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4494 case OP_ICONV_TO_I1:
4495 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4496 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4498 case OP_ICONV_TO_I2:
4499 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4500 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4502 case OP_ICONV_TO_U1:
4503 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4505 case OP_ICONV_TO_U2:
4506 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4507 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4511 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4513 case OP_COMPARE_IMM:
4514 case OP_ICOMPARE_IMM:
4515 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4516 g_assert (imm8 >= 0);
4517 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4521 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4522 * So instead of emitting a trap, we emit a call a C function and place a
4525 //*(int*)code = 0xef9f0001;
4528 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4529 (gpointer)"mono_break");
4530 code = emit_call_seq (cfg, code);
4532 case OP_RELAXED_NOP:
4537 case OP_DUMMY_STORE:
4538 case OP_DUMMY_ICONST:
4539 case OP_DUMMY_R8CONST:
4540 case OP_NOT_REACHED:
4543 case OP_IL_SEQ_POINT:
4544 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4546 case OP_SEQ_POINT: {
4548 MonoInst *info_var = cfg->arch.seq_point_info_var;
4549 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4550 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4551 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4553 int dreg = ARMREG_LR;
4556 if (cfg->soft_breakpoints) {
4557 g_assert (!cfg->compile_aot);
4562 * For AOT, we use one got slot per method, which will point to a
4563 * SeqPointInfo structure, containing all the information required
4564 * by the code below.
4566 if (cfg->compile_aot) {
4567 g_assert (info_var);
4568 g_assert (info_var->opcode == OP_REGOFFSET);
4569 g_assert (arm_is_imm12 (info_var->inst_offset));
4572 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4574 * Read from the single stepping trigger page. This will cause a
4575 * SIGSEGV when single stepping is enabled.
4576 * We do this _before_ the breakpoint, so single stepping after
4577 * a breakpoint is hit will step to the next IL offset.
4579 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4582 /* Single step check */
4583 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4584 if (cfg->soft_breakpoints) {
4585 /* Load the address of the sequence point method variable. */
4586 var = ss_method_var;
4588 g_assert (var->opcode == OP_REGOFFSET);
4589 g_assert (arm_is_imm12 (var->inst_offset));
4590 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4592 /* Read the value and check whether it is non-zero. */
4593 ARM_LDR_IMM (code, dreg, dreg, 0);
4594 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4595 /* Call it conditionally. */
4596 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4598 if (cfg->compile_aot) {
4599 /* Load the trigger page addr from the variable initialized in the prolog */
4600 var = ss_trigger_page_var;
4602 g_assert (var->opcode == OP_REGOFFSET);
4603 g_assert (arm_is_imm12 (var->inst_offset));
4604 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4606 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4608 *(int*)code = (int)ss_trigger_page;
4611 ARM_LDR_IMM (code, dreg, dreg, 0);
4615 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4617 /* Breakpoint check */
4618 if (cfg->compile_aot) {
4619 guint32 offset = code - cfg->native_code;
4622 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4623 /* Add the offset */
4624 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4625 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4626 if (arm_is_imm12 ((int)val)) {
4627 ARM_LDR_IMM (code, dreg, dreg, val);
4629 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4631 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4633 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4634 g_assert (!(val & 0xFF000000));
4636 ARM_LDR_IMM (code, dreg, dreg, 0);
4638 /* What is faster, a branch or a load ? */
4639 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4640 /* The breakpoint instruction */
4641 if (cfg->soft_breakpoints)
4642 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4644 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4645 } else if (cfg->soft_breakpoints) {
4646 /* Load the address of the breakpoint method into ip. */
4647 var = bp_method_var;
4649 g_assert (var->opcode == OP_REGOFFSET);
4650 g_assert (arm_is_imm12 (var->inst_offset));
4651 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4654 * A placeholder for a possible breakpoint inserted by
4655 * mono_arch_set_breakpoint ().
4660 * A placeholder for a possible breakpoint inserted by
4661 * mono_arch_set_breakpoint ().
4663 for (i = 0; i < 4; ++i)
4668 * Add an additional nop so skipping the bp doesn't cause the ip to point
4669 * to another IL offset.
4677 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4680 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4684 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4687 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4688 g_assert (imm8 >= 0);
4689 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4693 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4694 g_assert (imm8 >= 0);
4695 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4699 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4700 g_assert (imm8 >= 0);
4701 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4704 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4705 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4707 case OP_IADD_OVF_UN:
4708 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4709 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4712 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4713 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4715 case OP_ISUB_OVF_UN:
4716 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4717 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4719 case OP_ADD_OVF_CARRY:
4720 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4721 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4723 case OP_ADD_OVF_UN_CARRY:
4724 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4725 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4727 case OP_SUB_OVF_CARRY:
4728 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4731 case OP_SUB_OVF_UN_CARRY:
4732 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4733 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4737 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4740 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4741 g_assert (imm8 >= 0);
4742 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4745 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4749 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4753 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4754 g_assert (imm8 >= 0);
4755 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4759 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4760 g_assert (imm8 >= 0);
4761 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4763 case OP_ARM_RSBS_IMM:
4764 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4765 g_assert (imm8 >= 0);
4766 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4768 case OP_ARM_RSC_IMM:
4769 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4770 g_assert (imm8 >= 0);
4771 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4774 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4778 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4779 g_assert (imm8 >= 0);
4780 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4783 g_assert (v7s_supported || v7k_supported);
4784 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4787 g_assert (v7s_supported || v7k_supported);
4788 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4791 g_assert (v7s_supported || v7k_supported);
4792 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4793 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4796 g_assert (v7s_supported || v7k_supported);
4797 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4798 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4802 g_assert_not_reached ();
4804 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4808 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4809 g_assert (imm8 >= 0);
4810 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4813 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4817 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4818 g_assert (imm8 >= 0);
4819 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4822 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4827 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4828 else if (ins->dreg != ins->sreg1)
4829 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4832 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4837 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4838 else if (ins->dreg != ins->sreg1)
4839 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4842 case OP_ISHR_UN_IMM:
4844 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4845 else if (ins->dreg != ins->sreg1)
4846 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4849 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4852 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4855 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4858 if (ins->dreg == ins->sreg2)
4859 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4861 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4864 g_assert_not_reached ();
4867 /* FIXME: handle ovf/ sreg2 != dreg */
4868 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4869 /* FIXME: MUL doesn't set the C/O flags on ARM */
4871 case OP_IMUL_OVF_UN:
4872 /* FIXME: handle ovf/ sreg2 != dreg */
4873 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4874 /* FIXME: MUL doesn't set the C/O flags on ARM */
4877 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4880 /* Load the GOT offset */
4881 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4882 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4884 *(gpointer*)code = NULL;
4886 /* Load the value from the GOT */
4887 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4889 case OP_OBJC_GET_SELECTOR:
4890 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4891 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4893 *(gpointer*)code = NULL;
4895 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4897 case OP_ICONV_TO_I4:
4898 case OP_ICONV_TO_U4:
4900 if (ins->dreg != ins->sreg1)
4901 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4904 int saved = ins->sreg2;
4905 if (ins->sreg2 == ARM_LSW_REG) {
4906 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4909 if (ins->sreg1 != ARM_LSW_REG)
4910 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4911 if (saved != ARM_MSW_REG)
4912 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4916 if (IS_VFP && ins->dreg != ins->sreg1)
4917 ARM_CPYD (code, ins->dreg, ins->sreg1);
4920 if (IS_VFP && ins->dreg != ins->sreg1)
4921 ARM_CPYS (code, ins->dreg, ins->sreg1);
4923 case OP_MOVE_F_TO_I4:
4925 ARM_FMRS (code, ins->dreg, ins->sreg1);
4927 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4928 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4929 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4930 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4933 case OP_MOVE_I4_TO_F:
4935 ARM_FMSR (code, ins->dreg, ins->sreg1);
4937 ARM_FMSR (code, ins->dreg, ins->sreg1);
4938 ARM_CVTS (code, ins->dreg, ins->dreg);
4941 case OP_FCONV_TO_R4:
4944 ARM_CVTD (code, ins->dreg, ins->sreg1);
4946 ARM_CVTD (code, ins->dreg, ins->sreg1);
4947 ARM_CVTS (code, ins->dreg, ins->dreg);
4952 MonoCallInst *call = (MonoCallInst*)ins;
4955 * The stack looks like the following:
4956 * <caller argument area>
4959 * <callee argument area>
4960 * Need to copy the arguments from the callee argument area to
4961 * the caller argument area, and pop the frame.
4963 if (call->stack_usage) {
4964 int i, prev_sp_offset = 0;
4966 /* Compute size of saved registers restored below */
4968 prev_sp_offset = 2 * 4;
4970 prev_sp_offset = 1 * 4;
4971 for (i = 0; i < 16; ++i) {
4972 if (cfg->used_int_regs & (1 << i))
4973 prev_sp_offset += 4;
4976 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4978 /* Copy arguments on the stack to our argument area */
4979 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4980 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4981 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
4986 * Keep in sync with mono_arch_emit_epilog
4988 g_assert (!cfg->method->save_lmf);
4990 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4992 if (cfg->used_int_regs)
4993 ARM_POP (code, cfg->used_int_regs);
4994 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4996 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4999 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5000 if (cfg->compile_aot) {
5001 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5003 *(gpointer*)code = NULL;
5005 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5007 code = mono_arm_patchable_b (code, ARMCOND_AL);
5008 cfg->thunk_area += THUNK_SIZE;
5013 /* ensure ins->sreg1 is not NULL */
5014 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5017 g_assert (cfg->sig_cookie < 128);
5018 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5019 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5029 call = (MonoCallInst*)ins;
5032 code = emit_float_args (cfg, call, code, &max_len, &offset);
5034 if (ins->flags & MONO_INST_HAS_METHOD)
5035 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5037 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5038 code = emit_call_seq (cfg, code);
5039 ins->flags |= MONO_INST_GC_CALLSITE;
5040 ins->backend.pc_offset = code - cfg->native_code;
5041 code = emit_move_return_value (cfg, ins, code);
5048 case OP_VOIDCALL_REG:
5051 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5053 code = emit_call_reg (code, ins->sreg1);
5054 ins->flags |= MONO_INST_GC_CALLSITE;
5055 ins->backend.pc_offset = code - cfg->native_code;
5056 code = emit_move_return_value (cfg, ins, code);
5058 case OP_FCALL_MEMBASE:
5059 case OP_RCALL_MEMBASE:
5060 case OP_LCALL_MEMBASE:
5061 case OP_VCALL_MEMBASE:
5062 case OP_VCALL2_MEMBASE:
5063 case OP_VOIDCALL_MEMBASE:
5064 case OP_CALL_MEMBASE: {
5065 g_assert (ins->sreg1 != ARMREG_LR);
5066 call = (MonoCallInst*)ins;
5069 code = emit_float_args (cfg, call, code, &max_len, &offset);
5070 if (!arm_is_imm12 (ins->inst_offset)) {
5071 /* sreg1 might be IP */
5072 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5073 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5074 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5075 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5076 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5078 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5079 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5081 ins->flags |= MONO_INST_GC_CALLSITE;
5082 ins->backend.pc_offset = code - cfg->native_code;
5083 code = emit_move_return_value (cfg, ins, code);
5086 case OP_GENERIC_CLASS_INIT: {
5090 byte_offset = MONO_STRUCT_OFFSET (MonoVTable, initialized);
5092 g_assert (arm_is_imm8 (byte_offset));
5093 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5094 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5096 ARM_B_COND (code, ARMCOND_NE, 0);
5098 /* Uninitialized case */
5099 g_assert (ins->sreg1 == ARMREG_R0);
5101 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5102 (gpointer)"mono_generic_class_init");
5103 code = emit_call_seq (cfg, code);
5105 /* Initialized case */
5106 arm_patch (jump, code);
5110 /* round the size to 8 bytes */
5111 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5112 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5113 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5114 /* memzero the area: dreg holds the size, sp is the pointer */
5115 if (ins->flags & MONO_INST_INIT) {
5116 guint8 *start_loop, *branch_to_cond;
5117 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5118 branch_to_cond = code;
5121 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5122 arm_patch (branch_to_cond, code);
5123 /* decrement by 4 and set flags */
5124 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5125 ARM_B_COND (code, ARMCOND_GE, 0);
5126 arm_patch (code - 4, start_loop);
5128 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5129 if (cfg->param_area)
5130 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5135 MonoInst *var = cfg->dyn_call_var;
5138 g_assert (var->opcode == OP_REGOFFSET);
5139 g_assert (arm_is_imm12 (var->inst_offset));
5141 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5142 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5144 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5146 /* Save args buffer */
5147 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5149 /* Set stack slots using R0 as scratch reg */
5150 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5151 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5152 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5153 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5156 /* Set fp argument registers */
5157 if (IS_HARD_FLOAT) {
5158 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5159 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5161 ARM_B_COND (code, ARMCOND_EQ, 0);
5162 for (i = 0; i < FP_PARAM_REGS; ++i) {
5163 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5164 g_assert (arm_is_fpimm8 (offset));
5165 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5167 arm_patch (buf [0], code);
5170 /* Set argument registers */
5171 for (i = 0; i < PARAM_REGS; ++i)
5172 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5175 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5176 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5179 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5180 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5181 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5183 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5187 if (ins->sreg1 != ARMREG_R0)
5188 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5189 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5190 (gpointer)"mono_arch_throw_exception");
5191 code = emit_call_seq (cfg, code);
5195 if (ins->sreg1 != ARMREG_R0)
5196 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5197 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5198 (gpointer)"mono_arch_rethrow_exception");
5199 code = emit_call_seq (cfg, code);
5202 case OP_START_HANDLER: {
5203 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5204 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5207 /* Reserve a param area, see filter-stack.exe */
5209 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5210 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5212 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5213 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5217 if (arm_is_imm12 (spvar->inst_offset)) {
5218 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5220 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5221 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5225 case OP_ENDFILTER: {
5226 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5227 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5230 /* Free the param area */
5232 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5233 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5235 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5236 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5240 if (ins->sreg1 != ARMREG_R0)
5241 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5242 if (arm_is_imm12 (spvar->inst_offset)) {
5243 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5245 g_assert (ARMREG_IP != spvar->inst_basereg);
5246 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5247 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5249 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5252 case OP_ENDFINALLY: {
5253 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5254 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5257 /* Free the param area */
5259 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5260 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5262 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5263 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5267 if (arm_is_imm12 (spvar->inst_offset)) {
5268 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5270 g_assert (ARMREG_IP != spvar->inst_basereg);
5271 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5272 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5274 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5277 case OP_CALL_HANDLER:
5278 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5279 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5280 cfg->thunk_area += THUNK_SIZE;
5281 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5284 if (ins->dreg != ARMREG_R0)
5285 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5289 ins->inst_c0 = code - cfg->native_code;
5292 /*if (ins->inst_target_bb->native_offset) {
5294 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5296 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5297 code = mono_arm_patchable_b (code, ARMCOND_AL);
5301 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5305 * In the normal case we have:
5306 * ldr pc, [pc, ins->sreg1 << 2]
5309 * ldr lr, [pc, ins->sreg1 << 2]
5311 * After follows the data.
5312 * FIXME: add aot support.
5314 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5315 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5316 if (offset + max_len > (cfg->code_size - 16)) {
5317 cfg->code_size += max_len;
5318 cfg->code_size *= 2;
5319 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5320 code = cfg->native_code + offset;
5322 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5324 code += 4 * GPOINTER_TO_INT (ins->klass);
5328 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5329 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5333 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5334 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5338 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5339 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5343 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5344 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5348 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5349 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5352 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5353 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5356 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5357 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5360 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5361 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5364 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5365 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5368 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5369 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5371 case OP_COND_EXC_EQ:
5372 case OP_COND_EXC_NE_UN:
5373 case OP_COND_EXC_LT:
5374 case OP_COND_EXC_LT_UN:
5375 case OP_COND_EXC_GT:
5376 case OP_COND_EXC_GT_UN:
5377 case OP_COND_EXC_GE:
5378 case OP_COND_EXC_GE_UN:
5379 case OP_COND_EXC_LE:
5380 case OP_COND_EXC_LE_UN:
5381 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5383 case OP_COND_EXC_IEQ:
5384 case OP_COND_EXC_INE_UN:
5385 case OP_COND_EXC_ILT:
5386 case OP_COND_EXC_ILT_UN:
5387 case OP_COND_EXC_IGT:
5388 case OP_COND_EXC_IGT_UN:
5389 case OP_COND_EXC_IGE:
5390 case OP_COND_EXC_IGE_UN:
5391 case OP_COND_EXC_ILE:
5392 case OP_COND_EXC_ILE_UN:
5393 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5396 case OP_COND_EXC_IC:
5397 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5399 case OP_COND_EXC_OV:
5400 case OP_COND_EXC_IOV:
5401 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5403 case OP_COND_EXC_NC:
5404 case OP_COND_EXC_INC:
5405 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5407 case OP_COND_EXC_NO:
5408 case OP_COND_EXC_INO:
5409 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5421 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5424 /* floating point opcodes */
5426 if (cfg->compile_aot) {
5427 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5429 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5431 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5434 /* FIXME: we can optimize the imm load by dealing with part of
5435 * the displacement in LDFD (aligning to 512).
5437 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5438 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5442 if (cfg->compile_aot) {
5443 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5445 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5448 ARM_CVTS (code, ins->dreg, ins->dreg);
5450 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5451 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5453 ARM_CVTS (code, ins->dreg, ins->dreg);
5456 case OP_STORER8_MEMBASE_REG:
5457 /* This is generated by the local regalloc pass which runs after the lowering pass */
5458 if (!arm_is_fpimm8 (ins->inst_offset)) {
5459 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5460 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5461 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5463 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5466 case OP_LOADR8_MEMBASE:
5467 /* This is generated by the local regalloc pass which runs after the lowering pass */
5468 if (!arm_is_fpimm8 (ins->inst_offset)) {
5469 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5470 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5471 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5473 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5476 case OP_STORER4_MEMBASE_REG:
5477 g_assert (arm_is_fpimm8 (ins->inst_offset));
5479 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5481 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5482 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5483 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5484 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5487 case OP_LOADR4_MEMBASE:
5489 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5491 g_assert (arm_is_fpimm8 (ins->inst_offset));
5492 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5493 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5494 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5495 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5498 case OP_ICONV_TO_R_UN: {
5499 g_assert_not_reached ();
5502 case OP_ICONV_TO_R4:
5504 ARM_FMSR (code, ins->dreg, ins->sreg1);
5505 ARM_FSITOS (code, ins->dreg, ins->dreg);
5507 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5508 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5509 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5510 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5511 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5514 case OP_ICONV_TO_R8:
5515 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5516 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5517 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5518 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5522 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5523 if (sig_ret->type == MONO_TYPE_R4) {
5525 if (IS_HARD_FLOAT) {
5526 if (ins->sreg1 != ARM_VFP_D0)
5527 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5529 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5532 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5535 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5539 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5541 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5545 case OP_FCONV_TO_I1:
5546 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5548 case OP_FCONV_TO_U1:
5549 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5551 case OP_FCONV_TO_I2:
5552 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5554 case OP_FCONV_TO_U2:
5555 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5557 case OP_FCONV_TO_I4:
5559 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5561 case OP_FCONV_TO_U4:
5563 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5565 case OP_FCONV_TO_I8:
5566 case OP_FCONV_TO_U8:
5567 g_assert_not_reached ();
5568 /* Implemented as helper calls */
5570 case OP_LCONV_TO_R_UN:
5571 g_assert_not_reached ();
5572 /* Implemented as helper calls */
5574 case OP_LCONV_TO_OVF_I4_2: {
5575 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5577 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5580 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5581 high_bit_not_set = code;
5582 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5584 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5585 valid_negative = code;
5586 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5587 invalid_negative = code;
5588 ARM_B_COND (code, ARMCOND_AL, 0);
5590 arm_patch (high_bit_not_set, code);
5592 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5593 valid_positive = code;
5594 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5596 arm_patch (invalid_negative, code);
5597 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5599 arm_patch (valid_negative, code);
5600 arm_patch (valid_positive, code);
5602 if (ins->dreg != ins->sreg1)
5603 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5607 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5610 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5613 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5616 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5619 ARM_NEGD (code, ins->dreg, ins->sreg1);
5623 g_assert_not_reached ();
5627 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5633 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5638 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5641 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5642 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5646 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5649 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5650 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5654 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5657 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5658 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5659 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5663 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5666 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5667 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5671 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5674 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5675 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5676 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5680 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5683 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5684 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5688 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5691 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5692 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5696 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5699 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5700 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5703 /* ARM FPA flags table:
5704 * N Less than ARMCOND_MI
5705 * Z Equal ARMCOND_EQ
5706 * C Greater Than or Equal ARMCOND_CS
5707 * V Unordered ARMCOND_VS
5710 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5713 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5716 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5719 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5720 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5726 g_assert_not_reached ();
5730 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5732 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5733 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5734 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5738 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5739 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5744 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5745 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5747 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5748 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5750 *(guint32*)code = 0xffffffff;
5752 *(guint32*)code = 0x7fefffff;
5754 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5756 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5757 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5759 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5760 ARM_CPYD (code, ins->dreg, ins->sreg1);
5762 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5763 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5768 case OP_RCONV_TO_I1:
5769 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5771 case OP_RCONV_TO_U1:
5772 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5774 case OP_RCONV_TO_I2:
5775 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5777 case OP_RCONV_TO_U2:
5778 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5780 case OP_RCONV_TO_I4:
5781 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5783 case OP_RCONV_TO_U4:
5784 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5786 case OP_RCONV_TO_R4:
5788 if (ins->dreg != ins->sreg1)
5789 ARM_CPYS (code, ins->dreg, ins->sreg1);
5791 case OP_RCONV_TO_R8:
5793 ARM_CVTS (code, ins->dreg, ins->sreg1);
5796 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5799 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5802 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5805 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5808 ARM_NEGS (code, ins->dreg, ins->sreg1);
5812 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5815 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5816 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5820 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5823 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5824 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5828 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5831 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5832 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5833 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5837 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5840 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5841 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5845 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5848 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5849 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5850 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5854 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5857 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5858 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5862 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5865 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5866 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5870 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5873 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5874 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5877 case OP_GC_LIVENESS_DEF:
5878 case OP_GC_LIVENESS_USE:
5879 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5880 ins->backend.pc_offset = code - cfg->native_code;
5882 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5883 ins->backend.pc_offset = code - cfg->native_code;
5884 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5886 case OP_GC_SAFE_POINT: {
5889 g_assert (mono_threads_is_coop_enabled ());
5891 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5892 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5894 ARM_B_COND (code, ARMCOND_EQ, 0);
5895 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5896 code = emit_call_seq (cfg, code);
5897 arm_patch (buf [0], code);
5902 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5903 g_assert_not_reached ();
5906 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5907 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5908 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5909 g_assert_not_reached ();
5915 last_offset = offset;
5918 cfg->code_len = code - cfg->native_code;
5921 #endif /* DISABLE_JIT */
5924 mono_arch_register_lowlevel_calls (void)
5926 /* The signature doesn't matter */
5927 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5928 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5929 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5932 #define patch_lis_ori(ip,val) do {\
5933 guint16 *__lis_ori = (guint16*)(ip); \
5934 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5935 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5939 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5941 unsigned char *ip = ji->ip.i + code;
5943 if (ji->type == MONO_PATCH_INFO_SWITCH) {
5947 case MONO_PATCH_INFO_SWITCH: {
5948 gpointer *jt = (gpointer*)(ip + 8);
5950 /* jt is the inlined jump table, 2 instructions after ip
5951 * In the normal case we store the absolute addresses,
5952 * otherwise the displacements.
5954 for (i = 0; i < ji->data.table->table_size; i++)
5955 jt [i] = code + (int)ji->data.table->table [i];
5958 case MONO_PATCH_INFO_IP:
5959 g_assert_not_reached ();
5960 patch_lis_ori (ip, ip);
5962 case MONO_PATCH_INFO_METHOD_REL:
5963 g_assert_not_reached ();
5964 *((gpointer *)(ip)) = target;
5966 case MONO_PATCH_INFO_METHODCONST:
5967 case MONO_PATCH_INFO_CLASS:
5968 case MONO_PATCH_INFO_IMAGE:
5969 case MONO_PATCH_INFO_FIELD:
5970 case MONO_PATCH_INFO_VTABLE:
5971 case MONO_PATCH_INFO_IID:
5972 case MONO_PATCH_INFO_SFLDA:
5973 case MONO_PATCH_INFO_LDSTR:
5974 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
5975 case MONO_PATCH_INFO_LDTOKEN:
5976 g_assert_not_reached ();
5977 /* from OP_AOTCONST : lis + ori */
5978 patch_lis_ori (ip, target);
5980 case MONO_PATCH_INFO_R4:
5981 case MONO_PATCH_INFO_R8:
5982 g_assert_not_reached ();
5983 *((gconstpointer *)(ip + 2)) = target;
5985 case MONO_PATCH_INFO_EXC_NAME:
5986 g_assert_not_reached ();
5987 *((gconstpointer *)(ip + 1)) = target;
5989 case MONO_PATCH_INFO_NONE:
5990 case MONO_PATCH_INFO_BB_OVF:
5991 case MONO_PATCH_INFO_EXC_OVF:
5992 /* everything is dealt with at epilog output time */
5995 arm_patch_general (cfg, domain, ip, target);
6001 mono_arm_unaligned_stack (MonoMethod *method)
6003 g_assert_not_reached ();
6009 * Stack frame layout:
6011 * ------------------- fp
6012 * MonoLMF structure or saved registers
6013 * -------------------
6015 * -------------------
6017 * -------------------
6018 * optional 8 bytes for tracing
6019 * -------------------
6020 * param area size is cfg->param_area
6021 * ------------------- sp
6024 mono_arch_emit_prolog (MonoCompile *cfg)
6026 MonoMethod *method = cfg->method;
6028 MonoMethodSignature *sig;
6030 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6035 int prev_sp_offset, reg_offset;
6037 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6040 sig = mono_method_signature (method);
6041 cfg->code_size = 256 + sig->param_count * 64;
6042 code = cfg->native_code = g_malloc (cfg->code_size);
6044 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6046 alloc_size = cfg->stack_offset;
6052 * The iphone uses R7 as the frame pointer, and it points at the saved
6057 * We can't use r7 as a frame pointer since it points into the middle of
6058 * the frame, so we keep using our own frame pointer.
6059 * FIXME: Optimize this.
6061 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6062 prev_sp_offset += 8; /* r7 and lr */
6063 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6064 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6065 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6068 if (!method->save_lmf) {
6070 /* No need to push LR again */
6071 if (cfg->used_int_regs)
6072 ARM_PUSH (code, cfg->used_int_regs);
6074 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6075 prev_sp_offset += 4;
6077 for (i = 0; i < 16; ++i) {
6078 if (cfg->used_int_regs & (1 << i))
6079 prev_sp_offset += 4;
6081 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6083 for (i = 0; i < 16; ++i) {
6084 if ((cfg->used_int_regs & (1 << i))) {
6085 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6086 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6090 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6091 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6093 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6094 ARM_PUSH (code, 0x5ff0);
6095 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6096 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6098 for (i = 0; i < 16; ++i) {
6099 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6100 /* The original r7 is saved at the start */
6101 if (!(iphone_abi && i == ARMREG_R7))
6102 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6106 g_assert (reg_offset == 4 * 10);
6107 pos += sizeof (MonoLMF) - (4 * 10);
6111 orig_alloc_size = alloc_size;
6112 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6113 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6114 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6115 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6118 /* the stack used in the pushed regs */
6119 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6120 cfg->stack_usage = alloc_size;
6122 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6123 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6125 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6126 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6128 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6130 if (cfg->frame_reg != ARMREG_SP) {
6131 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6132 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6134 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6135 prev_sp_offset += alloc_size;
6137 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6138 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6140 /* compute max_offset in order to use short forward jumps
6141 * we could skip do it on arm because the immediate displacement
6142 * for jumps is large enough, it may be useful later for constant pools
6145 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6146 MonoInst *ins = bb->code;
6147 bb->max_offset = max_offset;
6149 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6152 MONO_BB_FOR_EACH_INS (bb, ins)
6153 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6156 /* stack alignment check */
6160 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6161 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6162 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6163 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6165 ARM_B_COND (code, ARMCOND_EQ, 0);
6166 if (cfg->compile_aot)
6167 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6169 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6170 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6171 code = emit_call_seq (cfg, code);
6172 arm_patch (buf [0], code);
6176 /* store runtime generic context */
6177 if (cfg->rgctx_var) {
6178 MonoInst *ins = cfg->rgctx_var;
6180 g_assert (ins->opcode == OP_REGOFFSET);
6182 if (arm_is_imm12 (ins->inst_offset)) {
6183 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6185 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6186 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6190 /* load arguments allocated to register from the stack */
6193 cinfo = get_call_info (NULL, sig);
6195 if (cinfo->ret.storage == RegTypeStructByAddr) {
6196 ArgInfo *ainfo = &cinfo->ret;
6197 inst = cfg->vret_addr;
6198 g_assert (arm_is_imm12 (inst->inst_offset));
6199 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6202 if (sig->call_convention == MONO_CALL_VARARG) {
6203 ArgInfo *cookie = &cinfo->sig_cookie;
6205 /* Save the sig cookie address */
6206 g_assert (cookie->storage == RegTypeBase);
6208 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6209 g_assert (arm_is_imm12 (cfg->sig_cookie));
6210 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6211 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6214 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6215 ArgInfo *ainfo = cinfo->args + i;
6216 inst = cfg->args [pos];
6218 if (cfg->verbose_level > 2)
6219 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6221 if (inst->opcode == OP_REGVAR) {
6222 if (ainfo->storage == RegTypeGeneral)
6223 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6224 else if (ainfo->storage == RegTypeFP) {
6225 g_assert_not_reached ();
6226 } else if (ainfo->storage == RegTypeBase) {
6227 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6228 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6230 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6231 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6234 g_assert_not_reached ();
6236 if (cfg->verbose_level > 2)
6237 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6239 switch (ainfo->storage) {
6241 for (part = 0; part < ainfo->nregs; part ++) {
6242 if (ainfo->esize == 4)
6243 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6245 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6248 case RegTypeGeneral:
6249 case RegTypeIRegPair:
6250 case RegTypeGSharedVtInReg:
6251 case RegTypeStructByAddr:
6252 switch (ainfo->size) {
6254 if (arm_is_imm12 (inst->inst_offset))
6255 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6257 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6258 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6262 if (arm_is_imm8 (inst->inst_offset)) {
6263 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6265 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6266 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6270 if (arm_is_imm12 (inst->inst_offset)) {
6271 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6273 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6274 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6276 if (arm_is_imm12 (inst->inst_offset + 4)) {
6277 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6279 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6280 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6284 if (arm_is_imm12 (inst->inst_offset)) {
6285 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6287 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6288 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6293 case RegTypeBaseGen:
6294 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6295 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6297 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6298 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6300 if (arm_is_imm12 (inst->inst_offset + 4)) {
6301 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6302 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6304 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6305 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6306 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6307 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6311 case RegTypeGSharedVtOnStack:
6312 case RegTypeStructByAddrOnStack:
6313 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6314 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6316 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6317 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6320 switch (ainfo->size) {
6322 if (arm_is_imm8 (inst->inst_offset)) {
6323 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6325 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6326 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6330 if (arm_is_imm8 (inst->inst_offset)) {
6331 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6333 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6334 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6338 if (arm_is_imm12 (inst->inst_offset)) {
6339 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6344 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6345 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6347 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6348 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6350 if (arm_is_imm12 (inst->inst_offset + 4)) {
6351 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6353 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6354 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6358 if (arm_is_imm12 (inst->inst_offset)) {
6359 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6361 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6362 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6368 int imm8, rot_amount;
6370 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6371 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6372 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6374 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6376 if (ainfo->size == 8)
6377 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6379 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6382 case RegTypeStructByVal: {
6383 int doffset = inst->inst_offset;
6387 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6388 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6389 if (arm_is_imm12 (doffset)) {
6390 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6392 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6393 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6395 soffset += sizeof (gpointer);
6396 doffset += sizeof (gpointer);
6398 if (ainfo->vtsize) {
6399 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6400 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6401 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6406 g_assert_not_reached ();
6413 if (method->save_lmf)
6414 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6417 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6419 if (cfg->arch.seq_point_info_var) {
6420 MonoInst *ins = cfg->arch.seq_point_info_var;
6422 /* Initialize the variable from a GOT slot */
6423 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6424 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6426 *(gpointer*)code = NULL;
6428 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6430 g_assert (ins->opcode == OP_REGOFFSET);
6432 if (arm_is_imm12 (ins->inst_offset)) {
6433 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6435 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6436 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6440 /* Initialize ss_trigger_page_var */
6441 if (!cfg->soft_breakpoints) {
6442 MonoInst *info_var = cfg->arch.seq_point_info_var;
6443 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6444 int dreg = ARMREG_LR;
6447 g_assert (info_var->opcode == OP_REGOFFSET);
6448 g_assert (arm_is_imm12 (info_var->inst_offset));
6450 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6451 /* Load the trigger page addr */
6452 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6453 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6457 if (cfg->arch.seq_point_ss_method_var) {
6458 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6459 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6461 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6462 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6464 if (cfg->compile_aot) {
6465 MonoInst *info_var = cfg->arch.seq_point_info_var;
6466 int dreg = ARMREG_LR;
6468 g_assert (info_var->opcode == OP_REGOFFSET);
6469 g_assert (arm_is_imm12 (info_var->inst_offset));
6471 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6472 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
6473 ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6475 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6476 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6478 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6480 *(gpointer*)code = &single_step_tramp;
6482 *(gpointer*)code = breakpoint_tramp;
6485 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6486 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6487 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6488 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6492 cfg->code_len = code - cfg->native_code;
6493 g_assert (cfg->code_len < cfg->code_size);
6500 mono_arch_emit_epilog (MonoCompile *cfg)
6502 MonoMethod *method = cfg->method;
6503 int pos, i, rot_amount;
6504 int max_epilog_size = 16 + 20*4;
6508 if (cfg->method->save_lmf)
6509 max_epilog_size += 128;
6511 if (mono_jit_trace_calls != NULL)
6512 max_epilog_size += 50;
6514 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6515 max_epilog_size += 50;
6517 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6518 cfg->code_size *= 2;
6519 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6520 cfg->stat_code_reallocs++;
6524 * Keep in sync with OP_JMP
6526 code = cfg->native_code + cfg->code_len;
6528 /* Save the uwind state which is needed by the out-of-line code */
6529 mono_emit_unwind_op_remember_state (cfg, code);
6531 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6532 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6536 /* Load returned vtypes into registers if needed */
6537 cinfo = cfg->arch.cinfo;
6538 switch (cinfo->ret.storage) {
6539 case RegTypeStructByVal: {
6540 MonoInst *ins = cfg->ret;
6542 if (cinfo->ret.nregs == 1) {
6543 if (arm_is_imm12 (ins->inst_offset)) {
6544 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6546 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6547 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6550 for (i = 0; i < cinfo->ret.nregs; ++i) {
6551 int offset = ins->inst_offset + (i * 4);
6552 if (arm_is_imm12 (offset)) {
6553 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6555 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6556 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6563 MonoInst *ins = cfg->ret;
6565 for (i = 0; i < cinfo->ret.nregs; ++i) {
6566 if (cinfo->ret.esize == 4)
6567 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6569 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6577 if (method->save_lmf) {
6578 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6579 /* all but r0-r3, sp and pc */
6580 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6583 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6585 /* This points to r4 inside MonoLMF->iregs */
6586 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6588 regmask = 0x9ff0; /* restore lr to pc */
6589 /* Skip caller saved registers not used by the method */
6590 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6591 regmask &= ~(1 << reg);
6596 /* Restored later */
6597 regmask &= ~(1 << ARMREG_PC);
6598 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6599 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6600 for (i = 0; i < 16; i++) {
6601 if (regmask & (1 << i))
6604 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6606 ARM_POP (code, regmask);
6608 for (i = 0; i < 16; i++) {
6609 if (regmask & (1 << i))
6610 mono_emit_unwind_op_same_value (cfg, code, i);
6612 /* Restore saved r7, restore LR to PC */
6613 /* Skip lr from the lmf */
6614 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6615 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6616 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6617 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6620 int i, nused_int_regs = 0;
6622 for (i = 0; i < 16; i++) {
6623 if (cfg->used_int_regs & (1 << i))
6627 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6628 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6630 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6631 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6634 if (cfg->frame_reg != ARMREG_SP) {
6635 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6639 /* Restore saved gregs */
6640 if (cfg->used_int_regs) {
6641 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6642 ARM_POP (code, cfg->used_int_regs);
6643 for (i = 0; i < 16; i++) {
6644 if (cfg->used_int_regs & (1 << i))
6645 mono_emit_unwind_op_same_value (cfg, code, i);
6648 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6649 /* Restore saved r7, restore LR to PC */
6650 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6652 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6653 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6657 /* Restore the unwind state to be the same as before the epilog */
6658 mono_emit_unwind_op_restore_state (cfg, code);
6660 cfg->code_len = code - cfg->native_code;
6662 g_assert (cfg->code_len < cfg->code_size);
6667 mono_arch_emit_exceptions (MonoCompile *cfg)
6669 MonoJumpInfo *patch_info;
6672 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6673 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6674 int max_epilog_size = 50;
6676 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6677 exc_throw_pos [i] = NULL;
6678 exc_throw_found [i] = 0;
6681 /* count the number of exception infos */
6684 * make sure we have enough space for exceptions
6686 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6687 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6688 i = mini_exception_id_by_name (patch_info->data.target);
6689 if (!exc_throw_found [i]) {
6690 max_epilog_size += 32;
6691 exc_throw_found [i] = TRUE;
6696 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6697 cfg->code_size *= 2;
6698 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6699 cfg->stat_code_reallocs++;
6702 code = cfg->native_code + cfg->code_len;
6704 /* add code to raise exceptions */
6705 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6706 switch (patch_info->type) {
6707 case MONO_PATCH_INFO_EXC: {
6708 MonoClass *exc_class;
6709 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6711 i = mini_exception_id_by_name (patch_info->data.target);
6712 if (exc_throw_pos [i]) {
6713 arm_patch (ip, exc_throw_pos [i]);
6714 patch_info->type = MONO_PATCH_INFO_NONE;
6717 exc_throw_pos [i] = code;
6719 arm_patch (ip, code);
6721 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6723 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6724 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6725 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6726 patch_info->data.name = "mono_arch_throw_corlib_exception";
6727 patch_info->ip.i = code - cfg->native_code;
6729 cfg->thunk_area += THUNK_SIZE;
6730 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6740 cfg->code_len = code - cfg->native_code;
6742 g_assert (cfg->code_len < cfg->code_size);
6746 #endif /* #ifndef DISABLE_JIT */
6749 mono_arch_finish_init (void)
6754 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6759 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6766 mono_arch_print_tree (MonoInst *tree, int arity)
6776 mono_arch_get_patch_offset (guint8 *code)
6783 mono_arch_flush_register_windows (void)
6788 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6790 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6794 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6796 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6800 mono_arch_get_cie_program (void)
6804 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6809 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6810 #define BASE_SIZE (6 * 4)
6811 #define BSEARCH_ENTRY_SIZE (4 * 4)
6812 #define CMP_SIZE (3 * 4)
6813 #define BRANCH_SIZE (1 * 4)
6814 #define CALL_SIZE (2 * 4)
6815 #define WMC_SIZE (8 * 4)
6816 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6819 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6821 guint32 delta = DISTANCE (target, code);
6823 g_assert (delta >= 0 && delta <= 0xFFF);
6824 *target = *target | delta;
6829 #ifdef ENABLE_WRONG_METHOD_CHECK
6831 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6833 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6839 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6840 gpointer fail_tramp)
6843 arminstr_t *code, *start;
6844 gboolean large_offsets = FALSE;
6845 guint32 **constant_pool_starts;
6846 arminstr_t *vtable_target = NULL;
6847 int extra_space = 0;
6848 #ifdef ENABLE_WRONG_METHOD_CHECK
6854 constant_pool_starts = g_new0 (guint32*, count);
6856 for (i = 0; i < count; ++i) {
6857 MonoIMTCheckItem *item = imt_entries [i];
6858 if (item->is_equals) {
6859 gboolean fail_case = !item->check_target_idx && fail_tramp;
6861 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6862 item->chunk_size += 32;
6863 large_offsets = TRUE;
6866 if (item->check_target_idx || fail_case) {
6867 if (!item->compare_done || fail_case)
6868 item->chunk_size += CMP_SIZE;
6869 item->chunk_size += BRANCH_SIZE;
6871 #ifdef ENABLE_WRONG_METHOD_CHECK
6872 item->chunk_size += WMC_SIZE;
6876 item->chunk_size += 16;
6877 large_offsets = TRUE;
6879 item->chunk_size += CALL_SIZE;
6881 item->chunk_size += BSEARCH_ENTRY_SIZE;
6882 imt_entries [item->check_target_idx]->compare_done = TRUE;
6884 size += item->chunk_size;
6888 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6891 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
6893 code = mono_domain_code_reserve (domain, size);
6896 unwind_ops = mono_arch_get_cie_program ();
6899 g_print ("Building IMT trampoline for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6900 for (i = 0; i < count; ++i) {
6901 MonoIMTCheckItem *item = imt_entries [i];
6902 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6906 if (large_offsets) {
6907 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6908 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6910 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6911 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6913 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6914 vtable_target = code;
6915 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6916 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6918 for (i = 0; i < count; ++i) {
6919 MonoIMTCheckItem *item = imt_entries [i];
6920 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6921 gint32 vtable_offset;
6923 item->code_target = (guint8*)code;
6925 if (item->is_equals) {
6926 gboolean fail_case = !item->check_target_idx && fail_tramp;
6928 if (item->check_target_idx || fail_case) {
6929 if (!item->compare_done || fail_case) {
6931 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6932 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6934 item->jmp_code = (guint8*)code;
6935 ARM_B_COND (code, ARMCOND_NE, 0);
6937 /*Enable the commented code to assert on wrong method*/
6938 #ifdef ENABLE_WRONG_METHOD_CHECK
6940 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6941 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6943 ARM_B_COND (code, ARMCOND_EQ, 0);
6945 /* Define this if your system is so bad that gdb is failing. */
6946 #ifdef BROKEN_DEV_ENV
6947 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6949 arm_patch (code - 1, mini_dump_bad_imt);
6953 arm_patch (cond, code);
6957 if (item->has_target_code) {
6958 /* Load target address */
6959 target_code_ins = code;
6960 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6961 /* Save it to the fourth slot */
6962 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6963 /* Restore registers and branch */
6964 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6966 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
6968 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
6969 if (!arm_is_imm12 (vtable_offset)) {
6971 * We need to branch to a computed address but we don't have
6972 * a free register to store it, since IP must contain the
6973 * vtable address. So we push the two values to the stack, and
6974 * load them both using LDM.
6976 /* Compute target address */
6977 vtable_offset_ins = code;
6978 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6979 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
6980 /* Save it to the fourth slot */
6981 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
6982 /* Restore registers and branch */
6983 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6985 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
6987 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
6988 if (large_offsets) {
6989 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6990 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
6992 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
6993 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
6998 arm_patch (item->jmp_code, (guchar*)code);
7000 target_code_ins = code;
7001 /* Load target address */
7002 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7003 /* Save it to the fourth slot */
7004 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7005 /* Restore registers and branch */
7006 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7008 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7009 item->jmp_code = NULL;
7013 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7015 /*must emit after unconditional branch*/
7016 if (vtable_target) {
7017 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7018 item->chunk_size += 4;
7019 vtable_target = NULL;
7022 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7023 constant_pool_starts [i] = code;
7025 code += extra_space;
7029 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7030 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7032 item->jmp_code = (guint8*)code;
7033 ARM_B_COND (code, ARMCOND_HS, 0);
7038 for (i = 0; i < count; ++i) {
7039 MonoIMTCheckItem *item = imt_entries [i];
7040 if (item->jmp_code) {
7041 if (item->check_target_idx)
7042 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7044 if (i > 0 && item->is_equals) {
7046 arminstr_t *space_start = constant_pool_starts [i];
7047 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7048 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7055 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7056 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7061 g_free (constant_pool_starts);
7063 mono_arch_flush_icache ((guint8*)start, size);
7064 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7065 mono_stats.imt_trampolines_size += code - start;
7067 g_assert (DISTANCE (start, code) <= size);
7069 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7075 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7077 return ctx->regs [reg];
7081 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7083 ctx->regs [reg] = val;
7087 * mono_arch_get_trampolines:
7089 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7093 mono_arch_get_trampolines (gboolean aot)
7095 return mono_arm_get_exception_trampolines (aot);
7099 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7106 bp = MONO_CONTEXT_GET_BP (ctx);
7107 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7109 old_value = *lr_loc;
7110 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7113 *lr_loc = new_value;
7118 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7120 * mono_arch_set_breakpoint:
7122 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7123 * The location should contain code emitted by OP_SEQ_POINT.
7126 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7129 guint32 native_offset = ip - (guint8*)ji->code_start;
7130 MonoDebugOptions *opt = mini_get_debug_options ();
7133 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7135 if (!breakpoint_tramp)
7136 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7138 g_assert (native_offset % 4 == 0);
7139 g_assert (info->bp_addrs [native_offset / 4] == 0);
7140 info->bp_addrs [native_offset / 4] = opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page;
7141 } else if (opt->soft_breakpoints) {
7143 ARM_BLX_REG (code, ARMREG_LR);
7144 mono_arch_flush_icache (code - 4, 4);
7146 int dreg = ARMREG_LR;
7148 /* Read from another trigger page */
7149 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7151 *(int*)code = (int)bp_trigger_page;
7153 ARM_LDR_IMM (code, dreg, dreg, 0);
7155 mono_arch_flush_icache (code - 16, 16);
7158 /* This is currently implemented by emitting an SWI instruction, which
7159 * qemu/linux seems to convert to a SIGILL.
7161 *(int*)code = (0xef << 24) | 8;
7163 mono_arch_flush_icache (code - 4, 4);
7169 * mono_arch_clear_breakpoint:
7171 * Clear the breakpoint at IP.
7174 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7176 MonoDebugOptions *opt = mini_get_debug_options ();
7181 guint32 native_offset = ip - (guint8*)ji->code_start;
7182 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7184 if (!breakpoint_tramp)
7185 breakpoint_tramp = mini_get_breakpoint_trampoline ();
7187 g_assert (native_offset % 4 == 0);
7188 g_assert (info->bp_addrs [native_offset / 4] == (opt->soft_breakpoints ? breakpoint_tramp : bp_trigger_page));
7189 info->bp_addrs [native_offset / 4] = 0;
7190 } else if (opt->soft_breakpoints) {
7193 mono_arch_flush_icache (code - 4, 4);
7195 for (i = 0; i < 4; ++i)
7198 mono_arch_flush_icache (ip, code - ip);
7203 * mono_arch_start_single_stepping:
7205 * Start single stepping.
7208 mono_arch_start_single_stepping (void)
7210 if (ss_trigger_page)
7211 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7213 single_step_tramp = mini_get_single_step_trampoline ();
7217 * mono_arch_stop_single_stepping:
7219 * Stop single stepping.
7222 mono_arch_stop_single_stepping (void)
7224 if (ss_trigger_page)
7225 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7227 single_step_tramp = NULL;
7231 #define DBG_SIGNAL SIGBUS
7233 #define DBG_SIGNAL SIGSEGV
7237 * mono_arch_is_single_step_event:
7239 * Return whenever the machine state in SIGCTX corresponds to a single
7243 mono_arch_is_single_step_event (void *info, void *sigctx)
7245 siginfo_t *sinfo = info;
7247 if (!ss_trigger_page)
7250 /* Sometimes the address is off by 4 */
7251 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7258 * mono_arch_is_breakpoint_event:
7260 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7263 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7265 siginfo_t *sinfo = info;
7267 if (!ss_trigger_page)
7270 if (sinfo->si_signo == DBG_SIGNAL) {
7271 /* Sometimes the address is off by 4 */
7272 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7282 * mono_arch_skip_breakpoint:
7284 * See mini-amd64.c for docs.
7287 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7289 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7293 * mono_arch_skip_single_step:
7295 * See mini-amd64.c for docs.
7298 mono_arch_skip_single_step (MonoContext *ctx)
7300 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7303 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7306 * mono_arch_get_seq_point_info:
7308 * See mini-amd64.c for docs.
7311 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7316 // FIXME: Add a free function
7318 mono_domain_lock (domain);
7319 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7321 mono_domain_unlock (domain);
7324 ji = mono_jit_info_table_find (domain, (char*)code);
7327 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7329 info->ss_trigger_page = ss_trigger_page;
7330 info->bp_trigger_page = bp_trigger_page;
7331 info->ss_tramp_addr = &single_step_tramp;
7333 mono_domain_lock (domain);
7334 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7336 mono_domain_unlock (domain);
7343 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7345 ext->lmf.previous_lmf = prev_lmf;
7346 /* Mark that this is a MonoLMFExt */
7347 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7348 ext->lmf.sp = (gssize)ext;
7352 * mono_arch_set_target:
7354 * Set the target architecture the JIT backend should generate code for, in the form
7355 * of a GNU target triplet. Only used in AOT mode.
7358 mono_arch_set_target (char *mtriple)
7360 /* The GNU target triple format is not very well documented */
7361 if (strstr (mtriple, "armv7")) {
7362 v5_supported = TRUE;
7363 v6_supported = TRUE;
7364 v7_supported = TRUE;
7366 if (strstr (mtriple, "armv6")) {
7367 v5_supported = TRUE;
7368 v6_supported = TRUE;
7370 if (strstr (mtriple, "armv7s")) {
7371 v7s_supported = TRUE;
7373 if (strstr (mtriple, "armv7k")) {
7374 v7k_supported = TRUE;
7376 if (strstr (mtriple, "thumbv7s")) {
7377 v5_supported = TRUE;
7378 v6_supported = TRUE;
7379 v7_supported = TRUE;
7380 v7s_supported = TRUE;
7381 thumb_supported = TRUE;
7382 thumb2_supported = TRUE;
7384 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7385 v5_supported = TRUE;
7386 v6_supported = TRUE;
7387 thumb_supported = TRUE;
7390 if (strstr (mtriple, "gnueabi"))
7391 eabi_supported = TRUE;
7395 mono_arch_opcode_supported (int opcode)
7398 case OP_ATOMIC_ADD_I4:
7399 case OP_ATOMIC_EXCHANGE_I4:
7400 case OP_ATOMIC_CAS_I4:
7401 case OP_ATOMIC_LOAD_I1:
7402 case OP_ATOMIC_LOAD_I2:
7403 case OP_ATOMIC_LOAD_I4:
7404 case OP_ATOMIC_LOAD_U1:
7405 case OP_ATOMIC_LOAD_U2:
7406 case OP_ATOMIC_LOAD_U4:
7407 case OP_ATOMIC_STORE_I1:
7408 case OP_ATOMIC_STORE_I2:
7409 case OP_ATOMIC_STORE_I4:
7410 case OP_ATOMIC_STORE_U1:
7411 case OP_ATOMIC_STORE_U2:
7412 case OP_ATOMIC_STORE_U4:
7413 return v7_supported;
7414 case OP_ATOMIC_LOAD_R4:
7415 case OP_ATOMIC_LOAD_R8:
7416 case OP_ATOMIC_STORE_R4:
7417 case OP_ATOMIC_STORE_R8:
7418 return v7_supported && IS_VFP;
7425 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7427 return get_call_info (mp, sig);
7431 mono_arch_get_get_tls_tramp (void)
7437 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, int patch_type, gpointer data)
7440 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
7441 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7443 *(gpointer*)code = NULL;
7445 /* Load the value from the GOT */
7446 ARM_LDR_REG_REG (code, dreg, ARMREG_PC, dreg);