mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  */
  10 #include "mini.h"
  11 #include <string.h>
  12
  13 #include <mono/metadata/appdomain.h>
  14 #include <mono/metadata/debug-helpers.h>
  15 #include <mono/utils/mono-mmap.h>
  16
  17 #include "mini-arm.h"
  18 #include "cpu-arm.h"
  19 #include "trace.h"
  20 #include "ir-emit.h"
  21 #ifdef ARM_FPU_FPA
  22 #include "mono/arch/arm/arm-fpa-codegen.h"
  23 #elif defined(ARM_FPU_VFP)
  24 #include "mono/arch/arm/arm-vfp-codegen.h"
  25 #endif
  26
  27 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
  28 #define HAVE_AEABI_READ_TP 1
  29 #endif
  30
  31 static gint lmf_tls_offset = -1;
  32 static gint lmf_addr_tls_offset = -1;
  33
  34 /* This mutex protects architecture specific caches */
  35 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  36 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  37 static CRITICAL_SECTION mini_arch_mutex;
  38
  39 static int v5_supported = 0;
  40 static int v6_supported = 0;
  41 static int v7_supported = 0;
  42 static int thumb_supported = 0;
  43 /*
  44  * Whenever to use the ARM EABI
  45  */
  46 static int eabi_supported = 0;
  47
  48 /*
  49  * Whenever we are on arm/darwin aka the iphone.
  50  */
  51 static int darwin = 0;
  52 /*
  53  * Whenever to use the iphone ABI extensions:
  54  * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
  55  * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
  56  * This is required for debugging/profiling tools to work, but it has some overhead so it should
  57  * only be turned on in debug builds.
  58  */
  59 static int iphone_abi = 0;
  60 static int i8_align;
  61
  62 /*
  63  * The code generated for sequence points reads from this location, which is
  64  * made read-only when single stepping is enabled.
  65  */
  66 static gpointer ss_trigger_page;
  67
  68 /* Enabled breakpoints read from this trigger page */
  69 static gpointer bp_trigger_page;
  70
  71 /* Structure used by the sequence points in AOTed code */
  72 typedef struct {
  73         gpointer ss_trigger_page;
  74         gpointer bp_trigger_page;
  75         guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
  76 } SeqPointInfo;
  77
  78 /*
  79  * TODO:
  80  * floating point support: on ARM it is a mess, there are at least 3
  81  * different setups, each of which binary incompat with the other.
  82  * 1) FPA: old and ugly, but unfortunately what current distros use
  83  *    the double binary format has the two words swapped. 8 double registers.
  84  *    Implemented usually by kernel emulation.
  85  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
  86  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
  87  * 3) VFP: the new and actually sensible and useful FP support. Implemented
  88  *    in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
  89  *
  90  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
  91  */
  92 int mono_exc_esp_offset = 0;
  93
  94 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
  95 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
  96 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
  97
  98 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
  99 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
 100 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
 101
 102 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
 103 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) |  (ARMREG_LR << 12) | ARMREG_PC)
 104 #define DEBUG_IMT 0
 105
 106 /* A variant of ARM_LDR_IMM which can handle large offsets */
 107 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
 108         if (arm_is_imm12 ((offset))) { \
 109                 ARM_LDR_IMM (code, (dreg), (basereg), (offset));        \
 110         } else {                                                                                                \
 111                 g_assert ((scratch_reg) != (basereg));                                     \
 112                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 113                 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 114         }                                                                                                                                       \
 115         } while (0)
 116
 117 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do {      \
 118         if (arm_is_imm12 ((offset))) { \
 119                 ARM_STR_IMM (code, (dreg), (basereg), (offset));        \
 120         } else {                                                                                                \
 121                 g_assert ((scratch_reg) != (basereg));                                     \
 122                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 123                 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 124         }                                                                                                                                       \
 125         } while (0)
 126
 127 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
 128
 129 const char*
 130 mono_arch_regname (int reg)
 131 {
 132         static const char * rnames[] = {
 133                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
 134                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
 135                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
 136                 "arm_pc"
 137         };
 138         if (reg >= 0 && reg < 16)
 139                 return rnames [reg];
 140         return "unknown";
 141 }
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         static const char * rnames[] = {
 147                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
 148                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
 149                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
 150                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
 151                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
 152                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
 153                 "arm_f30", "arm_f31"
 154         };
 155         if (reg >= 0 && reg < 32)
 156                 return rnames [reg];
 157         return "unknown";
 158 }
 159
 160 #ifndef DISABLE_JIT
 161
 162 static guint8*
 163 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
 164 {
 165         int imm8, rot_amount;
 166         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
 167                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
 168                 return code;
 169         }
 170         g_assert (dreg != sreg);
 171         code = mono_arm_emit_load_imm (code, dreg, imm);
 172         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
 173         return code;
 174 }
 175
 176 static guint8*
 177 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
 178 {
 179         /* we can use r0-r3, since this is called only for incoming args on the stack */
 180         if (size > sizeof (gpointer) * 4) {
 181                 guint8 *start_loop;
 182                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 183                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 184                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
 185                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
 186                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
 187                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
 188                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
 189                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
 190                 ARM_B_COND (code, ARMCOND_NE, 0);
 191                 arm_patch (code - 4, start_loop);
 192                 return code;
 193         }
 194         if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
 195                         arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
 196                 while (size >= 4) {
 197                         ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 198                         ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 199                         doffset += 4;
 200                         soffset += 4;
 201                         size -= 4;
 202                 }
 203         } else if (size) {
 204                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 205                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 206                 doffset = soffset = 0;
 207                 while (size >= 4) {
 208                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
 209                         ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
 210                         doffset += 4;
 211                         soffset += 4;
 212                         size -= 4;
 213                 }
 214         }
 215         g_assert (size == 0);
 216         return code;
 217 }
 218
 219 static guint8*
 220 emit_call_reg (guint8 *code, int reg)
 221 {
 222         if (v5_supported) {
 223                 ARM_BLX_REG (code, reg);
 224         } else {
 225                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 226                 if (thumb_supported)
 227                         ARM_BX (code, reg);
 228                 else
 229                         ARM_MOV_REG_REG (code, ARMREG_PC, reg);
 230         }
 231         return code;
 232 }
 233
 234 static guint8*
 235 emit_call_seq (MonoCompile *cfg, guint8 *code)
 236 {
 237         if (cfg->method->dynamic) {
 238                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 239                 ARM_B (code, 0);
 240                 *(gpointer*)code = NULL;
 241                 code += 4;
 242                 code = emit_call_reg (code, ARMREG_IP);
 243         } else {
 244                 ARM_BL (code, 0);
 245         }
 246         return code;
 247 }
 248
 249 static guint8*
 250 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
 251 {
 252         switch (ins->opcode) {
 253         case OP_FCALL:
 254         case OP_FCALL_REG:
 255         case OP_FCALL_MEMBASE:
 256 #ifdef ARM_FPU_FPA
 257                 if (ins->dreg != ARM_FPA_F0)
 258                         ARM_MVFD (code, ins->dreg, ARM_FPA_F0);
 259 #elif defined(ARM_FPU_VFP)
 260                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
 261                         ARM_FMSR (code, ins->dreg, ARMREG_R0);
 262                         ARM_CVTS (code, ins->dreg, ins->dreg);
 263                 } else {
 264                         ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
 265                 }
 266 #endif
 267                 break;
 268         }
 269
 270         return code;
 271 }
 272
 273 /*
 274  * emit_save_lmf:
 275  *
 276  *   Emit code to push an LMF structure on the LMF stack.
 277  * On arm, this is intermixed with the initialization of other fields of the structure.
 278  */
 279 static guint8*
 280 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
 281 {
 282         gboolean get_lmf_fast = FALSE;
 283
 284 #ifdef HAVE_AEABI_READ_TP
 285         gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
 286
 287         if (lmf_addr_tls_offset != -1) {
 288                 get_lmf_fast = TRUE;
 289
 290                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
 291                                                          (gpointer)"__aeabi_read_tp");
 292                 code = emit_call_seq (cfg, code);
 293
 294                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
 295                 get_lmf_fast = TRUE;
 296         }
 297 #endif
 298         if (!get_lmf_fast) {
 299                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
 300                                                                  (gpointer)"mono_get_lmf_addr");
 301                 code = emit_call_seq (cfg, code);
 302         }
 303         /* we build the MonoLMF structure on the stack - see mini-arm.h */
 304         /* lmf_offset is the offset from the previous stack pointer,
 305          * alloc_size is the total stack space allocated, so the offset
 306          * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
 307          * The pointer to the struct is put in r1 (new_lmf).
 308          * ip is used as scratch
 309          * The callee-saved registers are already in the MonoLMF structure
 310          */
 311         code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
 312         /* r0 is the result from mono_get_lmf_addr () */
 313         ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
 314         /* new_lmf->previous_lmf = *lmf_addr */
 315         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 316         ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 317         /* *(lmf_addr) = r1 */
 318         ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 319         /* Skip method (only needed for trampoline LMF frames) */
 320         ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, esp));
 321         /* save the current IP */
 322         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
 323         ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, eip));
 324
 325         return code;
 326 }
 327
 328 /*
 329  * emit_save_lmf:
 330  *
 331  *   Emit code to pop an LMF structure from the LMF stack.
 332  */
 333 static guint8*
 334 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
 335 {
 336         int basereg, offset;
 337
 338         if (lmf_offset < 32) {
 339                 basereg = cfg->frame_reg;
 340                 offset = lmf_offset;
 341         } else {
 342                 basereg = ARMREG_R2;
 343                 offset = 0;
 344                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
 345         }
 346
 347         /* ip = previous_lmf */
 348         ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 349         /* lr = lmf_addr */
 350         ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
 351         /* *(lmf_addr) = previous_lmf */
 352         ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 353
 354         return code;
 355 }
 356
 357 #endif /* #ifndef DISABLE_JIT */
 358
 359 /*
 360  * mono_arch_get_argument_info:
 361  * @csig:  a method signature
 362  * @param_count: the number of parameters to consider
 363  * @arg_info: an array to store the result infos
 364  *
 365  * Gathers information on parameters such as size, alignment and
 366  * padding. arg_info should be large enought to hold param_count + 1 entries.
 367  *
 368  * Returns the size of the activation frame.
 369  */
 370 int
 371 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 372 {
 373         int k, frame_size = 0;
 374         guint32 size, align, pad;
 375         int offset = 8;
 376
 377         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 378                 frame_size += sizeof (gpointer);
 379                 offset += 4;
 380         }
 381
 382         arg_info [0].offset = offset;
 383
 384         if (csig->hasthis) {
 385                 frame_size += sizeof (gpointer);
 386                 offset += 4;
 387         }
 388
 389         arg_info [0].size = frame_size;
 390
 391         for (k = 0; k < param_count; k++) {
 392                 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
 393
 394                 /* ignore alignment for now */
 395                 align = 1;
 396
 397                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 398                 arg_info [k].pad = pad;
 399                 frame_size += size;
 400                 arg_info [k + 1].pad = 0;
 401                 arg_info [k + 1].size = size;
 402                 offset += pad;
 403                 arg_info [k + 1].offset = offset;
 404                 offset += size;
 405         }
 406
 407         align = MONO_ARCH_FRAME_ALIGNMENT;
 408         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 409         arg_info [k].pad = pad;
 410
 411         return frame_size;
 412 }
 413
 414 #define MAX_ARCH_DELEGATE_PARAMS 3
 415
 416 static gpointer
 417 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
 418 {
 419         guint8 *code, *start;
 420
 421         if (has_target) {
 422                 start = code = mono_global_codeman_reserve (12);
 423
 424                 /* Replace the this argument with the target */
 425                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 426                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
 427                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 428
 429                 g_assert ((code - start) <= 12);
 430
 431                 mono_arch_flush_icache (start, 12);
 432         } else {
 433                 int size, i;
 434
 435                 size = 8 + param_count * 4;
 436                 start = code = mono_global_codeman_reserve (size);
 437
 438                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 439                 /* slide down the arguments */
 440                 for (i = 0; i < param_count; ++i) {
 441                         ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
 442                 }
 443                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 444
 445                 g_assert ((code - start) <= size);
 446
 447                 mono_arch_flush_icache (start, size);
 448         }
 449
 450         if (code_size)
 451                 *code_size = code - start;
 452
 453         return start;
 454 }
 455
 456 /*
 457  * mono_arch_get_delegate_invoke_impls:
 458  *
 459  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
 460  * trampolines.
 461  */
 462 GSList*
 463 mono_arch_get_delegate_invoke_impls (void)
 464 {
 465         GSList *res = NULL;
 466         guint8 *code;
 467         guint32 code_len;
 468         int i;
 469
 470         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
 471         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
 472
 473         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
 474                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
 475                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
 476         }
 477
 478         return res;
 479 }
 480
 481 gpointer
 482 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
 483 {
 484         guint8 *code, *start;
 485
 486         /* FIXME: Support more cases */
 487         if (MONO_TYPE_ISSTRUCT (sig->ret))
 488                 return NULL;
 489
 490         if (has_target) {
 491                 static guint8* cached = NULL;
 492                 mono_mini_arch_lock ();
 493                 if (cached) {
 494                         mono_mini_arch_unlock ();
 495                         return cached;
 496                 }
 497
 498                 if (mono_aot_only)
 499                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
 500                 else
 501                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
 502                 cached = start;
 503                 mono_mini_arch_unlock ();
 504                 return cached;
 505         } else {
 506                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
 507                 int i;
 508
 509                 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
 510                         return NULL;
 511                 for (i = 0; i < sig->param_count; ++i)
 512                         if (!mono_is_regsize_var (sig->params [i]))
 513                                 return NULL;
 514
 515                 mono_mini_arch_lock ();
 516                 code = cache [sig->param_count];
 517                 if (code) {
 518                         mono_mini_arch_unlock ();
 519                         return code;
 520                 }
 521
 522                 if (mono_aot_only) {
 523                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
 524                         start = mono_aot_get_trampoline (name);
 525                         g_free (name);
 526                 } else {
 527                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
 528                 }
 529                 cache [sig->param_count] = start;
 530                 mono_mini_arch_unlock ();
 531                 return start;
 532         }
 533
 534         return NULL;
 535 }
 536
 537 gpointer
 538 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
 539 {
 540         return (gpointer)regs [ARMREG_R0];
 541 }
 542
 543 /*
 544  * Initialize the cpu to execute managed code.
 545  */
 546 void
 547 mono_arch_cpu_init (void)
 548 {
 549 #if defined(__ARM_EABI__)
 550         eabi_supported = TRUE;
 551 #endif
 552 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
 553                 i8_align = 4;
 554 #else
 555                 i8_align = __alignof__ (gint64);
 556 #endif
 557 }
 558
 559 /*
 560  * Initialize architecture specific code.
 561  */
 562 void
 563 mono_arch_init (void)
 564 {
 565         InitializeCriticalSection (&mini_arch_mutex);
 566
 567         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 568         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 569         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 570
 571         mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
 572         mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
 573         mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
 574 }
 575
 576 /*
 577  * Cleanup architecture specific code.
 578  */
 579 void
 580 mono_arch_cleanup (void)
 581 {
 582 }
 583
 584 /*
 585  * This function returns the optimizations supported on this cpu.
 586  */
 587 guint32
 588 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 589 {
 590         guint32 opts = 0;
 591         const char *cpu_arch = getenv ("MONO_CPU_ARCH");
 592         if (cpu_arch != NULL) {
 593                 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
 594                 if (strncmp (cpu_arch, "armv", 4) == 0) {
 595                         v5_supported = cpu_arch [4] >= '5';
 596                         v6_supported = cpu_arch [4] >= '6';
 597                         v7_supported = cpu_arch [4] >= '7';
 598                 }
 599         } else {
 600 #if __APPLE__
 601         thumb_supported = TRUE;
 602         v5_supported = TRUE;
 603         darwin = TRUE;
 604         iphone_abi = TRUE;
 605 #else
 606         char buf [512];
 607         char *line;
 608         FILE *file = fopen ("/proc/cpuinfo", "r");
 609         if (file) {
 610                 while ((line = fgets (buf, 512, file))) {
 611                         if (strncmp (line, "Processor", 9) == 0) {
 612                                 char *ver = strstr (line, "(v");
 613                                 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
 614                                         v5_supported = TRUE;
 615                                 if (ver && (ver [2] == '6' || ver [2] == '7'))
 616                                         v6_supported = TRUE;
 617                                 if (ver && (ver [2] == '7'))
 618                                         v7_supported = TRUE;
 619                                 continue;
 620                         }
 621                         if (strncmp (line, "Features", 8) == 0) {
 622                                 char *th = strstr (line, "thumb");
 623                                 if (th) {
 624                                         thumb_supported = TRUE;
 625                                         if (v5_supported)
 626                                                 break;
 627                                 }
 628                                 continue;
 629                         }
 630                 }
 631                 fclose (file);
 632                 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
 633         }
 634 #endif
 635         }
 636
 637         /* no arm-specific optimizations yet */
 638         *exclude_mask = 0;
 639         return opts;
 640 }
 641
 642 #ifndef DISABLE_JIT
 643
 644 static gboolean
 645 is_regsize_var (MonoType *t) {
 646         if (t->byref)
 647                 return TRUE;
 648         t = mini_type_get_underlying_type (NULL, t);
 649         switch (t->type) {
 650         case MONO_TYPE_I4:
 651         case MONO_TYPE_U4:
 652         case MONO_TYPE_I:
 653         case MONO_TYPE_U:
 654         case MONO_TYPE_PTR:
 655         case MONO_TYPE_FNPTR:
 656                 return TRUE;
 657         case MONO_TYPE_OBJECT:
 658         case MONO_TYPE_STRING:
 659         case MONO_TYPE_CLASS:
 660         case MONO_TYPE_SZARRAY:
 661         case MONO_TYPE_ARRAY:
 662                 return TRUE;
 663         case MONO_TYPE_GENERICINST:
 664                 if (!mono_type_generic_inst_is_valuetype (t))
 665                         return TRUE;
 666                 return FALSE;
 667         case MONO_TYPE_VALUETYPE:
 668                 return FALSE;
 669         }
 670         return FALSE;
 671 }
 672
 673 GList *
 674 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 675 {
 676         GList *vars = NULL;
 677         int i;
 678
 679         for (i = 0; i < cfg->num_varinfo; i++) {
 680                 MonoInst *ins = cfg->varinfo [i];
 681                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 682
 683                 /* unused vars */
 684                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 685                         continue;
 686
 687                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 688                         continue;
 689
 690                 /* we can only allocate 32 bit values */
 691                 if (is_regsize_var (ins->inst_vtype)) {
 692                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 693                         g_assert (i == vmv->idx);
 694                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 695                 }
 696         }
 697
 698         return vars;
 699 }
 700
 701 #define USE_EXTRA_TEMPS 0
 702
 703 GList *
 704 mono_arch_get_global_int_regs (MonoCompile *cfg)
 705 {
 706         GList *regs = NULL;
 707
 708         mono_arch_compute_omit_fp (cfg);
 709
 710         /*
 711          * FIXME: Interface calls might go through a static rgctx trampoline which
 712          * sets V5, but it doesn't save it, so we need to save it ourselves, and
 713          * avoid using it.
 714          */
 715         if (cfg->flags & MONO_CFG_HAS_CALLS)
 716                 cfg->uses_rgctx_reg = TRUE;
 717
 718         if (cfg->arch.omit_fp)
 719                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
 720         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 721         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 722         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 723         if (darwin)
 724                 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
 725                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
 726         else
 727                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 728         if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
 729                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
 730                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 731         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 732         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 733
 734         return regs;
 735 }
 736
 737 /*
 738  * mono_arch_regalloc_cost:
 739  *
 740  *  Return the cost, in number of memory references, of the action of
 741  * allocating the variable VMV into a register during global register
 742  * allocation.
 743  */
 744 guint32
 745 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 746 {
 747         /* FIXME: */
 748         return 2;
 749 }
 750
 751 #endif /* #ifndef DISABLE_JIT */
 752
 753 #ifndef __GNUC_PREREQ
 754 #define __GNUC_PREREQ(maj, min) (0)
 755 #endif
 756
 757 void
 758 mono_arch_flush_icache (guint8 *code, gint size)
 759 {
 760 #if __APPLE__
 761         sys_icache_invalidate (code, size);
 762 #elif __GNUC_PREREQ(4, 1)
 763         __clear_cache (code, code + size);
 764 #elif defined(PLATFORM_ANDROID)
 765         const int syscall = 0xf0002;
 766         __asm __volatile (
 767                 "mov     r0, %0\n"
 768                 "mov     r1, %1\n"
 769                 "mov     r7, %2\n"
 770                 "mov     r2, #0x0\n"
 771                 "svc     0x00000000\n"
 772                 :
 773                 :       "r" (code), "r" (code + size), "r" (syscall)
 774                 :       "r0", "r1", "r7", "r2"
 775                 );
 776 #else
 777         __asm __volatile ("mov r0, %0\n"
 778                         "mov r1, %1\n"
 779                         "mov r2, %2\n"
 780                         "swi 0x9f0002       @ sys_cacheflush"
 781                         : /* no outputs */
 782                         : "r" (code), "r" (code + size), "r" (0)
 783                         : "r0", "r1", "r3" );
 784 #endif
 785 }
 786
 787 typedef enum {
 788         RegTypeNone,
 789         RegTypeGeneral,
 790         RegTypeIRegPair,
 791         RegTypeBase,
 792         RegTypeBaseGen,
 793         RegTypeFP,
 794         RegTypeStructByVal,
 795         RegTypeStructByAddr
 796 } ArgStorage;
 797
 798 typedef struct {
 799         gint32  offset;
 800         guint16 vtsize; /* in param area */
 801         guint8  reg;
 802         ArgStorage  storage;
 803         gint32  struct_size;
 804         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 805 } ArgInfo;
 806
 807 typedef struct {
 808         int nargs;
 809         guint32 stack_usage;
 810         gboolean vtype_retaddr;
 811         /* The index of the vret arg in the argument list */
 812         int vret_arg_index;
 813         ArgInfo ret;
 814         ArgInfo sig_cookie;
 815         ArgInfo args [1];
 816 } CallInfo;
 817
 818 #define DEBUG(a)
 819
 820 #ifndef __GNUC__
 821 /*#define __alignof__(a) sizeof(a)*/
 822 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
 823 #endif
 824
 825 #define PARAM_REGS 4
 826
 827 static void inline
 828 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 829 {
 830         if (simple) {
 831                 if (*gr > ARMREG_R3) {
 832                         ainfo->offset = *stack_size;
 833                         ainfo->reg = ARMREG_SP; /* in the caller */
 834                         ainfo->storage = RegTypeBase;
 835                         *stack_size += 4;
 836                 } else {
 837                         ainfo->storage = RegTypeGeneral;
 838                         ainfo->reg = *gr;
 839                 }
 840         } else {
 841                 gboolean split;
 842
 843                 if (eabi_supported)
 844                         split = i8_align == 4;
 845                 else
 846                         split = TRUE;
 847
 848                 if (*gr == ARMREG_R3 && split) {
 849                         /* first word in r3 and the second on the stack */
 850                         ainfo->offset = *stack_size;
 851                         ainfo->reg = ARMREG_SP; /* in the caller */
 852                         ainfo->storage = RegTypeBaseGen;
 853                         *stack_size += 4;
 854                 } else if (*gr >= ARMREG_R3) {
 855                         if (eabi_supported) {
 856                                 /* darwin aligns longs to 4 byte only */
 857                                 if (i8_align == 8) {
 858                                         *stack_size += 7;
 859                                         *stack_size &= ~7;
 860                                 }
 861                         }
 862                         ainfo->offset = *stack_size;
 863                         ainfo->reg = ARMREG_SP; /* in the caller */
 864                         ainfo->storage = RegTypeBase;
 865                         *stack_size += 8;
 866                 } else {
 867                         if (eabi_supported) {
 868                                 if (i8_align == 8 && ((*gr) & 1))
 869                                         (*gr) ++;
 870                         }
 871                         ainfo->storage = RegTypeIRegPair;
 872                         ainfo->reg = *gr;
 873                 }
 874                 (*gr) ++;
 875         }
 876         (*gr) ++;
 877 }
 878
 879 static CallInfo*
 880 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 881 {
 882         guint i, gr, pstart;
 883         int n = sig->hasthis + sig->param_count;
 884         MonoType *simpletype;
 885         guint32 stack_size = 0;
 886         CallInfo *cinfo;
 887         gboolean is_pinvoke = sig->pinvoke;
 888
 889         if (mp)
 890                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 891         else
 892                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 893
 894         cinfo->nargs = n;
 895         gr = ARMREG_R0;
 896
 897         /* FIXME: handle returning a struct */
 898         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 899                 guint32 align;
 900
 901                 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
 902                         cinfo->ret.storage = RegTypeStructByVal;
 903                 } else {
 904                         cinfo->vtype_retaddr = TRUE;
 905                 }
 906         }
 907
 908         pstart = 0;
 909         n = 0;
 910         /*
 911          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 912          * the first argument, allowing 'this' to be always passed in the first arg reg.
 913          * Also do this if the first argument is a reference type, since virtual calls
 914          * are sometimes made using calli without sig->hasthis set, like in the delegate
 915          * invoke wrappers.
 916          */
 917         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 918                 if (sig->hasthis) {
 919                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 920                 } else {
 921                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
 922                         pstart = 1;
 923                 }
 924                 n ++;
 925                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 926                 cinfo->vret_arg_index = 1;
 927         } else {
 928                 /* this */
 929                 if (sig->hasthis) {
 930                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
 931                         n ++;
 932                 }
 933
 934                 if (cinfo->vtype_retaddr)
 935                         add_general (&gr, &stack_size, &cinfo->ret, TRUE);
 936         }
 937
 938         DEBUG(printf("params: %d\n", sig->param_count));
 939         for (i = pstart; i < sig->param_count; ++i) {
 940                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 941                         /* Prevent implicit arguments and sig_cookie from
 942                            being passed in registers */
 943                         gr = ARMREG_R3 + 1;
 944                         /* Emit the signature cookie just before the implicit arguments */
 945                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
 946                 }
 947                 DEBUG(printf("param %d: ", i));
 948                 if (sig->params [i]->byref) {
 949                         DEBUG(printf("byref\n"));
 950                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 951                         n++;
 952                         continue;
 953                 }
 954                 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
 955                 switch (simpletype->type) {
 956                 case MONO_TYPE_BOOLEAN:
 957                 case MONO_TYPE_I1:
 958                 case MONO_TYPE_U1:
 959                         cinfo->args [n].size = 1;
 960                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 961                         n++;
 962                         break;
 963                 case MONO_TYPE_CHAR:
 964                 case MONO_TYPE_I2:
 965                 case MONO_TYPE_U2:
 966                         cinfo->args [n].size = 2;
 967                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 968                         n++;
 969                         break;
 970                 case MONO_TYPE_I4:
 971                 case MONO_TYPE_U4:
 972                         cinfo->args [n].size = 4;
 973                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 974                         n++;
 975                         break;
 976                 case MONO_TYPE_I:
 977                 case MONO_TYPE_U:
 978                 case MONO_TYPE_PTR:
 979                 case MONO_TYPE_FNPTR:
 980                 case MONO_TYPE_CLASS:
 981                 case MONO_TYPE_OBJECT:
 982                 case MONO_TYPE_STRING:
 983                 case MONO_TYPE_SZARRAY:
 984                 case MONO_TYPE_ARRAY:
 985                 case MONO_TYPE_R4:
 986                         cinfo->args [n].size = sizeof (gpointer);
 987                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 988                         n++;
 989                         break;
 990                 case MONO_TYPE_GENERICINST:
 991                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
 992                                 cinfo->args [n].size = sizeof (gpointer);
 993                                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
 994                                 n++;
 995                                 break;
 996                         }
 997                         /* Fall through */
 998                 case MONO_TYPE_TYPEDBYREF:
 999                 case MONO_TYPE_VALUETYPE: {
1000                         gint size;
1001                         int align_size;
1002                         int nwords;
1003                         guint32 align;
1004
1005                         if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1006                                 size = sizeof (MonoTypedRef);
1007                                 align = sizeof (gpointer);
1008                         } else {
1009                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1010                                 if (is_pinvoke)
1011                                         size = mono_class_native_size (klass, &align);
1012                                 else
1013                                         size = mono_class_value_size (klass, &align);
1014                         }
1015                         DEBUG(printf ("load %d bytes struct\n",
1016                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
1017                         align_size = size;
1018                         nwords = 0;
1019                         align_size += (sizeof (gpointer) - 1);
1020                         align_size &= ~(sizeof (gpointer) - 1);
1021                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1022                         cinfo->args [n].storage = RegTypeStructByVal;
1023                         cinfo->args [n].struct_size = size;
1024                         /* FIXME: align stack_size if needed */
1025                         if (eabi_supported) {
1026                                 if (align >= 8 && (gr & 1))
1027                                         gr ++;
1028                         }
1029                         if (gr > ARMREG_R3) {
1030                                 cinfo->args [n].size = 0;
1031                                 cinfo->args [n].vtsize = nwords;
1032                         } else {
1033                                 int rest = ARMREG_R3 - gr + 1;
1034                                 int n_in_regs = rest >= nwords? nwords: rest;
1035
1036                                 cinfo->args [n].size = n_in_regs;
1037                                 cinfo->args [n].vtsize = nwords - n_in_regs;
1038                                 cinfo->args [n].reg = gr;
1039                                 gr += n_in_regs;
1040                                 nwords -= n_in_regs;
1041                         }
1042                         cinfo->args [n].offset = stack_size;
1043                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1044                         stack_size += nwords * sizeof (gpointer);
1045                         n++;
1046                         break;
1047                 }
1048                 case MONO_TYPE_U8:
1049                 case MONO_TYPE_I8:
1050                 case MONO_TYPE_R8:
1051                         cinfo->args [n].size = 8;
1052                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1053                         n++;
1054                         break;
1055                 default:
1056                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1057                 }
1058         }
1059
1060         /* Handle the case where there are no implicit arguments */
1061         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1062                 /* Prevent implicit arguments and sig_cookie from
1063                    being passed in registers */
1064                 gr = ARMREG_R3 + 1;
1065                 /* Emit the signature cookie just before the implicit arguments */
1066                 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1067         }
1068
1069         {
1070                 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1071                 switch (simpletype->type) {
1072                 case MONO_TYPE_BOOLEAN:
1073                 case MONO_TYPE_I1:
1074                 case MONO_TYPE_U1:
1075                 case MONO_TYPE_I2:
1076                 case MONO_TYPE_U2:
1077                 case MONO_TYPE_CHAR:
1078                 case MONO_TYPE_I4:
1079                 case MONO_TYPE_U4:
1080                 case MONO_TYPE_I:
1081                 case MONO_TYPE_U:
1082                 case MONO_TYPE_PTR:
1083                 case MONO_TYPE_FNPTR:
1084                 case MONO_TYPE_CLASS:
1085                 case MONO_TYPE_OBJECT:
1086                 case MONO_TYPE_SZARRAY:
1087                 case MONO_TYPE_ARRAY:
1088                 case MONO_TYPE_STRING:
1089                         cinfo->ret.storage = RegTypeGeneral;
1090                         cinfo->ret.reg = ARMREG_R0;
1091                         break;
1092                 case MONO_TYPE_U8:
1093                 case MONO_TYPE_I8:
1094                         cinfo->ret.storage = RegTypeIRegPair;
1095                         cinfo->ret.reg = ARMREG_R0;
1096                         break;
1097                 case MONO_TYPE_R4:
1098                 case MONO_TYPE_R8:
1099                         cinfo->ret.storage = RegTypeFP;
1100                         cinfo->ret.reg = ARMREG_R0;
1101                         /* FIXME: cinfo->ret.reg = ???;
1102                         cinfo->ret.storage = RegTypeFP;*/
1103                         break;
1104                 case MONO_TYPE_GENERICINST:
1105                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1106                                 cinfo->ret.storage = RegTypeGeneral;
1107                                 cinfo->ret.reg = ARMREG_R0;
1108                                 break;
1109                         }
1110                         /* Fall through */
1111                 case MONO_TYPE_VALUETYPE:
1112                 case MONO_TYPE_TYPEDBYREF:
1113                         if (cinfo->ret.storage != RegTypeStructByVal)
1114                                 cinfo->ret.storage = RegTypeStructByAddr;
1115                         break;
1116                 case MONO_TYPE_VOID:
1117                         break;
1118                 default:
1119                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1120                 }
1121         }
1122
1123         /* align stack size to 8 */
1124         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1125         stack_size = (stack_size + 7) & ~7;
1126
1127         cinfo->stack_usage = stack_size;
1128         return cinfo;
1129 }
1130
1131 #ifndef DISABLE_JIT
1132
1133 G_GNUC_UNUSED static void
1134 break_count (void)
1135 {
1136 }
1137
1138 G_GNUC_UNUSED static gboolean
1139 debug_count (void)
1140 {
1141         static int count = 0;
1142         count ++;
1143
1144         if (!getenv ("COUNT"))
1145                 return TRUE;
1146
1147         if (count == atoi (getenv ("COUNT"))) {
1148                 break_count ();
1149         }
1150
1151         if (count > atoi (getenv ("COUNT"))) {
1152                 return FALSE;
1153         }
1154
1155         return TRUE;
1156 }
1157
1158 static gboolean
1159 debug_omit_fp (void)
1160 {
1161 #if 0
1162         return debug_count ();
1163 #else
1164         return TRUE;
1165 #endif
1166 }
1167
1168 /**
1169  * mono_arch_compute_omit_fp:
1170  *
1171  *   Determine whenever the frame pointer can be eliminated.
1172  */
1173 static void
1174 mono_arch_compute_omit_fp (MonoCompile *cfg)
1175 {
1176         MonoMethodSignature *sig;
1177         MonoMethodHeader *header;
1178         int i, locals_size;
1179         CallInfo *cinfo;
1180
1181         if (cfg->arch.omit_fp_computed)
1182                 return;
1183
1184         header = cfg->header;
1185
1186         sig = mono_method_signature (cfg->method);
1187
1188         if (!cfg->arch.cinfo)
1189                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1190         cinfo = cfg->arch.cinfo;
1191
1192         /*
1193          * FIXME: Remove some of the restrictions.
1194          */
1195         cfg->arch.omit_fp = TRUE;
1196         cfg->arch.omit_fp_computed = TRUE;
1197
1198         if (cfg->disable_omit_fp)
1199                 cfg->arch.omit_fp = FALSE;
1200         if (!debug_omit_fp ())
1201                 cfg->arch.omit_fp = FALSE;
1202         /*
1203         if (cfg->method->save_lmf)
1204                 cfg->arch.omit_fp = FALSE;
1205         */
1206         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1207                 cfg->arch.omit_fp = FALSE;
1208         if (header->num_clauses)
1209                 cfg->arch.omit_fp = FALSE;
1210         if (cfg->param_area)
1211                 cfg->arch.omit_fp = FALSE;
1212         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1213                 cfg->arch.omit_fp = FALSE;
1214         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1215                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1216                 cfg->arch.omit_fp = FALSE;
1217         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1218                 ArgInfo *ainfo = &cinfo->args [i];
1219
1220                 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1221                         /*
1222                          * The stack offset can only be determined when the frame
1223                          * size is known.
1224                          */
1225                         cfg->arch.omit_fp = FALSE;
1226                 }
1227         }
1228
1229         locals_size = 0;
1230         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1231                 MonoInst *ins = cfg->varinfo [i];
1232                 int ialign;
1233
1234                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1235         }
1236 }
1237
1238 /*
1239  * Set var information according to the calling convention. arm version.
1240  * The locals var stuff should most likely be split in another method.
1241  */
1242 void
1243 mono_arch_allocate_vars (MonoCompile *cfg)
1244 {
1245         MonoMethodSignature *sig;
1246         MonoMethodHeader *header;
1247         MonoInst *ins;
1248         int i, offset, size, align, curinst;
1249         CallInfo *cinfo;
1250         guint32 ualign;
1251
1252         sig = mono_method_signature (cfg->method);
1253
1254         if (!cfg->arch.cinfo)
1255                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1256         cinfo = cfg->arch.cinfo;
1257
1258         mono_arch_compute_omit_fp (cfg);
1259
1260         if (cfg->arch.omit_fp)
1261                 cfg->frame_reg = ARMREG_SP;
1262         else
1263                 cfg->frame_reg = ARMREG_FP;
1264
1265         cfg->flags |= MONO_CFG_HAS_SPILLUP;
1266
1267         /* allow room for the vararg method args: void* and long/double */
1268         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1269                 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1270
1271         header = cfg->header;
1272
1273         /* See mono_arch_get_global_int_regs () */
1274         if (cfg->flags & MONO_CFG_HAS_CALLS)
1275                 cfg->uses_rgctx_reg = TRUE;
1276
1277         if (cfg->frame_reg != ARMREG_SP)
1278                 cfg->used_int_regs |= 1 << cfg->frame_reg;
1279
1280         if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1281                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1282                 cfg->used_int_regs |= (1 << ARMREG_V5);
1283
1284         offset = 0;
1285         curinst = 0;
1286         if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1287                 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1288                 case MONO_TYPE_VOID:
1289                         break;
1290                 default:
1291                         cfg->ret->opcode = OP_REGVAR;
1292                         cfg->ret->inst_c0 = ARMREG_R0;
1293                         break;
1294                 }
1295         }
1296         /* local vars are at a positive offset from the stack pointer */
1297         /*
1298          * also note that if the function uses alloca, we use FP
1299          * to point at the local variables.
1300          */
1301         offset = 0; /* linkage area */
1302         /* align the offset to 16 bytes: not sure this is needed here  */
1303         //offset += 8 - 1;
1304         //offset &= ~(8 - 1);
1305
1306         /* add parameter area size for called functions */
1307         offset += cfg->param_area;
1308         offset += 8 - 1;
1309         offset &= ~(8 - 1);
1310         if (cfg->flags & MONO_CFG_HAS_FPOUT)
1311                 offset += 8;
1312
1313         /* allow room to save the return value */
1314         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1315                 offset += 8;
1316
1317         /* the MonoLMF structure is stored just below the stack pointer */
1318         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1319                 if (cinfo->ret.storage == RegTypeStructByVal) {
1320                         cfg->ret->opcode = OP_REGOFFSET;
1321                         cfg->ret->inst_basereg = cfg->frame_reg;
1322                         offset += sizeof (gpointer) - 1;
1323                         offset &= ~(sizeof (gpointer) - 1);
1324                         cfg->ret->inst_offset = - offset;
1325                 } else {
1326                         ins = cfg->vret_addr;
1327                         offset += sizeof(gpointer) - 1;
1328                         offset &= ~(sizeof(gpointer) - 1);
1329                         ins->inst_offset = offset;
1330                         ins->opcode = OP_REGOFFSET;
1331                         ins->inst_basereg = cfg->frame_reg;
1332                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1333                                 printf ("vret_addr =");
1334                                 mono_print_ins (cfg->vret_addr);
1335                         }
1336                 }
1337                 offset += sizeof(gpointer);
1338         }
1339
1340         /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1341         if (cfg->arch.seq_point_info_var) {
1342                 MonoInst *ins;
1343
1344                 ins = cfg->arch.seq_point_info_var;
1345
1346                 size = 4;
1347                 align = 4;
1348                 offset += align - 1;
1349                 offset &= ~(align - 1);
1350                 ins->opcode = OP_REGOFFSET;
1351                 ins->inst_basereg = cfg->frame_reg;
1352                 ins->inst_offset = offset;
1353                 offset += size;
1354
1355                 ins = cfg->arch.ss_trigger_page_var;
1356                 size = 4;
1357                 align = 4;
1358                 offset += align - 1;
1359                 offset &= ~(align - 1);
1360                 ins->opcode = OP_REGOFFSET;
1361                 ins->inst_basereg = cfg->frame_reg;
1362                 ins->inst_offset = offset;
1363                 offset += size;
1364         }
1365
1366         curinst = cfg->locals_start;
1367         for (i = curinst; i < cfg->num_varinfo; ++i) {
1368                 ins = cfg->varinfo [i];
1369                 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1370                         continue;
1371
1372                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1373                 * pinvoke wrappers when they call functions returning structure */
1374                 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1375                         size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1376                         align = ualign;
1377                 }
1378                 else
1379                         size = mono_type_size (ins->inst_vtype, &align);
1380
1381                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1382                  * since it loads/stores misaligned words, which don't do the right thing.
1383                  */
1384                 if (align < 4 && size >= 4)
1385                         align = 4;
1386                 offset += align - 1;
1387                 offset &= ~(align - 1);
1388                 ins->opcode = OP_REGOFFSET;
1389                 ins->inst_offset = offset;
1390                 ins->inst_basereg = cfg->frame_reg;
1391                 offset += size;
1392                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1393         }
1394
1395         curinst = 0;
1396         if (sig->hasthis) {
1397                 ins = cfg->args [curinst];
1398                 if (ins->opcode != OP_REGVAR) {
1399                         ins->opcode = OP_REGOFFSET;
1400                         ins->inst_basereg = cfg->frame_reg;
1401                         offset += sizeof (gpointer) - 1;
1402                         offset &= ~(sizeof (gpointer) - 1);
1403                         ins->inst_offset = offset;
1404                         offset += sizeof (gpointer);
1405                 }
1406                 curinst++;
1407         }
1408
1409         if (sig->call_convention == MONO_CALL_VARARG) {
1410                 size = 4;
1411                 align = 4;
1412
1413                 /* Allocate a local slot to hold the sig cookie address */
1414                 offset += align - 1;
1415                 offset &= ~(align - 1);
1416                 cfg->sig_cookie = offset;
1417                 offset += size;
1418         }
1419
1420         for (i = 0; i < sig->param_count; ++i) {
1421                 ins = cfg->args [curinst];
1422
1423                 if (ins->opcode != OP_REGVAR) {
1424                         ins->opcode = OP_REGOFFSET;
1425                         ins->inst_basereg = cfg->frame_reg;
1426                         size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1427                         align = ualign;
1428                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1429                          * since it loads/stores misaligned words, which don't do the right thing.
1430                          */
1431                         if (align < 4 && size >= 4)
1432                                 align = 4;
1433                         /* The code in the prolog () stores words when storing vtypes received in a register */
1434                         if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1435                                 align = 4;
1436                         offset += align - 1;
1437                         offset &= ~(align - 1);
1438                         ins->inst_offset = offset;
1439                         offset += size;
1440                 }
1441                 curinst++;
1442         }
1443
1444         /* align the offset to 8 bytes */
1445         offset += 8 - 1;
1446         offset &= ~(8 - 1);
1447
1448         /* change sign? */
1449         cfg->stack_offset = offset;
1450 }
1451
1452 void
1453 mono_arch_create_vars (MonoCompile *cfg)
1454 {
1455         MonoMethodSignature *sig;
1456         CallInfo *cinfo;
1457
1458         sig = mono_method_signature (cfg->method);
1459
1460         if (!cfg->arch.cinfo)
1461                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1462         cinfo = cfg->arch.cinfo;
1463
1464         if (cinfo->ret.storage == RegTypeStructByVal)
1465                 cfg->ret_var_is_local = TRUE;
1466
1467         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1468                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1469                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1470                         printf ("vret_addr = ");
1471                         mono_print_ins (cfg->vret_addr);
1472                 }
1473         }
1474
1475         if (cfg->gen_seq_points && cfg->compile_aot) {
1476             MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1477                 ins->flags |= MONO_INST_VOLATILE;
1478                 cfg->arch.seq_point_info_var = ins;
1479
1480                 /* Allocate a separate variable for this to save 1 load per seq point */
1481             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1482                 ins->flags |= MONO_INST_VOLATILE;
1483                 cfg->arch.ss_trigger_page_var = ins;
1484         }
1485 }
1486
1487 static void
1488 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1489 {
1490         MonoMethodSignature *tmp_sig;
1491         MonoInst *sig_arg;
1492
1493         if (call->tail_call)
1494                 NOT_IMPLEMENTED;
1495
1496         /* FIXME: Add support for signature tokens to AOT */
1497         cfg->disable_aot = TRUE;
1498
1499         g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1500
1501         /*
1502          * mono_ArgIterator_Setup assumes the signature cookie is
1503          * passed first and all the arguments which were before it are
1504          * passed on the stack after the signature. So compensate by
1505          * passing a different signature.
1506          */
1507         tmp_sig = mono_metadata_signature_dup (call->signature);
1508         tmp_sig->param_count -= call->signature->sentinelpos;
1509         tmp_sig->sentinelpos = 0;
1510         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1511
1512         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1513         sig_arg->dreg = mono_alloc_ireg (cfg);
1514         sig_arg->inst_p0 = tmp_sig;
1515         MONO_ADD_INS (cfg->cbb, sig_arg);
1516
1517         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_arg->dreg);
1518 }
1519
1520 #ifdef ENABLE_LLVM
1521 LLVMCallInfo*
1522 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1523 {
1524         int i, n;
1525         CallInfo *cinfo;
1526         ArgInfo *ainfo;
1527         LLVMCallInfo *linfo;
1528
1529         n = sig->param_count + sig->hasthis;
1530
1531         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1532
1533         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1534
1535         /*
1536          * LLVM always uses the native ABI while we use our own ABI, the
1537          * only difference is the handling of vtypes:
1538          * - we only pass/receive them in registers in some cases, and only
1539          *   in 1 or 2 integer registers.
1540          */
1541         if (cinfo->vtype_retaddr) {
1542                 /* Vtype returned using a hidden argument */
1543                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1544                 linfo->vret_arg_index = cinfo->vret_arg_index;
1545         } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1546                 cfg->exception_message = g_strdup ("unknown ret conv");
1547                 cfg->disable_llvm = TRUE;
1548                 return linfo;
1549         }
1550
1551         for (i = 0; i < n; ++i) {
1552                 ainfo = cinfo->args + i;
1553
1554                 linfo->args [i].storage = LLVMArgNone;
1555
1556                 switch (ainfo->storage) {
1557                 case RegTypeGeneral:
1558                 case RegTypeIRegPair:
1559                 case RegTypeBase:
1560                         linfo->args [i].storage = LLVMArgInIReg;
1561                         break;
1562                 case RegTypeStructByVal:
1563                         // FIXME: Passing entirely on the stack or split reg/stack
1564                         if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1565                                 linfo->args [i].storage = LLVMArgVtypeInReg;
1566                                 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1567                                 if (ainfo->size == 2)
1568                                         linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1569                                 else
1570                                         linfo->args [i].pair_storage [1] = LLVMArgNone;
1571                         } else {
1572                                 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1573                                 cfg->disable_llvm = TRUE;
1574                         }
1575                         break;
1576                 default:
1577                         cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1578                         cfg->disable_llvm = TRUE;
1579                         break;
1580                 }
1581         }
1582
1583         return linfo;
1584 }
1585 #endif
1586
1587 void
1588 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1589 {
1590         MonoInst *in, *ins;
1591         MonoMethodSignature *sig;
1592         int i, n;
1593         CallInfo *cinfo;
1594
1595         sig = call->signature;
1596         n = sig->param_count + sig->hasthis;
1597
1598         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1599
1600         for (i = 0; i < n; ++i) {
1601                 ArgInfo *ainfo = cinfo->args + i;
1602                 MonoType *t;
1603
1604                 if (i >= sig->hasthis)
1605                         t = sig->params [i - sig->hasthis];
1606                 else
1607                         t = &mono_defaults.int_class->byval_arg;
1608                 t = mini_type_get_underlying_type (NULL, t);
1609
1610                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1611                         /* Emit the signature cookie just before the implicit arguments */
1612                         emit_sig_cookie (cfg, call, cinfo);
1613                 }
1614
1615                 in = call->args [i];
1616
1617                 switch (ainfo->storage) {
1618                 case RegTypeGeneral:
1619                 case RegTypeIRegPair:
1620                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1621                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1622                                 ins->dreg = mono_alloc_ireg (cfg);
1623                                 ins->sreg1 = in->dreg + 1;
1624                                 MONO_ADD_INS (cfg->cbb, ins);
1625                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1626
1627                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1628                                 ins->dreg = mono_alloc_ireg (cfg);
1629                                 ins->sreg1 = in->dreg + 2;
1630                                 MONO_ADD_INS (cfg->cbb, ins);
1631                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1632                         } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1633 #ifndef MONO_ARCH_SOFT_FLOAT
1634                                 int creg;
1635 #endif
1636
1637                                 if (ainfo->size == 4) {
1638 #ifdef MONO_ARCH_SOFT_FLOAT
1639                                         /* mono_emit_call_args () have already done the r8->r4 conversion */
1640                                         /* The converted value is in an int vreg */
1641                                         MONO_INST_NEW (cfg, ins, OP_MOVE);
1642                                         ins->dreg = mono_alloc_ireg (cfg);
1643                                         ins->sreg1 = in->dreg;
1644                                         MONO_ADD_INS (cfg->cbb, ins);
1645                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1646 #else
1647                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1648                                         creg = mono_alloc_ireg (cfg);
1649                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1650                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1651 #endif
1652                                 } else {
1653 #ifdef MONO_ARCH_SOFT_FLOAT
1654                                         MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1655                                         ins->dreg = mono_alloc_ireg (cfg);
1656                                         ins->sreg1 = in->dreg;
1657                                         MONO_ADD_INS (cfg->cbb, ins);
1658                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1659
1660                                         MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1661                                         ins->dreg = mono_alloc_ireg (cfg);
1662                                         ins->sreg1 = in->dreg;
1663                                         MONO_ADD_INS (cfg->cbb, ins);
1664                                         mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1665 #else
1666                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1667                                         creg = mono_alloc_ireg (cfg);
1668                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1669                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1670                                         creg = mono_alloc_ireg (cfg);
1671                                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1672                                         mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1673 #endif
1674                                 }
1675                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1676                         } else {
1677                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1678                                 ins->dreg = mono_alloc_ireg (cfg);
1679                                 ins->sreg1 = in->dreg;
1680                                 MONO_ADD_INS (cfg->cbb, ins);
1681
1682                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1683                         }
1684                         break;
1685                 case RegTypeStructByAddr:
1686                         NOT_IMPLEMENTED;
1687 #if 0
1688                         /* FIXME: where si the data allocated? */
1689                         arg->backend.reg3 = ainfo->reg;
1690                         call->used_iregs |= 1 << ainfo->reg;
1691                         g_assert_not_reached ();
1692 #endif
1693                         break;
1694                 case RegTypeStructByVal:
1695                         MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1696                         ins->opcode = OP_OUTARG_VT;
1697                         ins->sreg1 = in->dreg;
1698                         ins->klass = in->klass;
1699                         ins->inst_p0 = call;
1700                         ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1701                         memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1702                         mono_call_inst_add_outarg_vt (cfg, call, ins);
1703                         MONO_ADD_INS (cfg->cbb, ins);
1704                         break;
1705                 case RegTypeBase:
1706                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1707                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1708                         } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1709                                 if (t->type == MONO_TYPE_R8) {
1710                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1711                                 } else {
1712 #ifdef MONO_ARCH_SOFT_FLOAT
1713                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1714 #else
1715                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1716 #endif
1717                                 }
1718                         } else {
1719                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1720                         }
1721                         break;
1722                 case RegTypeBaseGen:
1723                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1724                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1725                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1726                                 ins->dreg = mono_alloc_ireg (cfg);
1727                                 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1728                                 MONO_ADD_INS (cfg->cbb, ins);
1729                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1730                         } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1731                                 int creg;
1732
1733                                 /* This should work for soft-float as well */
1734
1735                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1736                                 creg = mono_alloc_ireg (cfg);
1737                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1738                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1739                                 creg = mono_alloc_ireg (cfg);
1740                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1741                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1742                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1743                         } else {
1744                                 g_assert_not_reached ();
1745                         }
1746                         break;
1747                 case RegTypeFP: {
1748                         /* FIXME: */
1749                         NOT_IMPLEMENTED;
1750 #if 0
1751                         arg->backend.reg3 = ainfo->reg;
1752                         /* FP args are passed in int regs */
1753                         call->used_iregs |= 1 << ainfo->reg;
1754                         if (ainfo->size == 8) {
1755                                 arg->opcode = OP_OUTARG_R8;
1756                                 call->used_iregs |= 1 << (ainfo->reg + 1);
1757                         } else {
1758                                 arg->opcode = OP_OUTARG_R4;
1759                         }
1760 #endif
1761                         cfg->flags |= MONO_CFG_HAS_FPOUT;
1762                         break;
1763                 }
1764                 default:
1765                         g_assert_not_reached ();
1766                 }
1767         }
1768
1769         /* Handle the case where there are no implicit arguments */
1770         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1771                 emit_sig_cookie (cfg, call, cinfo);
1772
1773         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1774                 MonoInst *vtarg;
1775
1776                 if (cinfo->ret.storage == RegTypeStructByVal) {
1777                         /* The JIT will transform this into a normal call */
1778                         call->vret_in_reg = TRUE;
1779                 } else {
1780                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1781                         vtarg->sreg1 = call->vret_var->dreg;
1782                         vtarg->dreg = mono_alloc_preg (cfg);
1783                         MONO_ADD_INS (cfg->cbb, vtarg);
1784
1785                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1786                 }
1787         }
1788
1789         call->stack_usage = cinfo->stack_usage;
1790
1791         g_free (cinfo);
1792 }
1793
1794 void
1795 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1796 {
1797         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1798         ArgInfo *ainfo = ins->inst_p1;
1799         int ovf_size = ainfo->vtsize;
1800         int doffset = ainfo->offset;
1801         int struct_size = ainfo->struct_size;
1802         int i, soffset, dreg, tmpreg;
1803
1804         soffset = 0;
1805         for (i = 0; i < ainfo->size; ++i) {
1806                 dreg = mono_alloc_ireg (cfg);
1807                 switch (struct_size) {
1808                 case 1:
1809                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1810                         break;
1811                 case 2:
1812                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1813                         break;
1814                 case 3:
1815                         tmpreg = mono_alloc_ireg (cfg);
1816                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1817                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1818                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1819                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1820                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1821                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1822                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1823                         break;
1824                 default:
1825                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1826                         break;
1827                 }
1828                 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1829                 soffset += sizeof (gpointer);
1830                 struct_size -= sizeof (gpointer);
1831         }
1832         //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1833         if (ovf_size != 0)
1834                 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1835 }
1836
1837 void
1838 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1839 {
1840         MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1841
1842         if (!ret->byref) {
1843                 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1844                         MonoInst *ins;
1845
1846                         if (COMPILE_LLVM (cfg)) {
1847                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1848                         } else {
1849                                 MONO_INST_NEW (cfg, ins, OP_SETLRET);
1850                                 ins->sreg1 = val->dreg + 1;
1851                                 ins->sreg2 = val->dreg + 2;
1852                                 MONO_ADD_INS (cfg->cbb, ins);
1853                         }
1854                         return;
1855                 }
1856 #ifdef MONO_ARCH_SOFT_FLOAT
1857                 if (ret->type == MONO_TYPE_R8) {
1858                         MonoInst *ins;
1859
1860                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1861                         ins->dreg = cfg->ret->dreg;
1862                         ins->sreg1 = val->dreg;
1863                         MONO_ADD_INS (cfg->cbb, ins);
1864                         return;
1865                 }
1866                 if (ret->type == MONO_TYPE_R4) {
1867                         /* Already converted to an int in method_to_ir () */
1868                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1869                         return;
1870                 }
1871 #elif defined(ARM_FPU_VFP)
1872                 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
1873                         MonoInst *ins;
1874
1875                         MONO_INST_NEW (cfg, ins, OP_SETFRET);
1876                         ins->dreg = cfg->ret->dreg;
1877                         ins->sreg1 = val->dreg;
1878                         MONO_ADD_INS (cfg->cbb, ins);
1879                         return;
1880                 }
1881 #else
1882                 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
1883                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1884                         return;
1885                 }
1886 #endif
1887         }
1888
1889         /* FIXME: */
1890         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1891 }
1892
1893 #endif /* #ifndef DISABLE_JIT */
1894
1895 gboolean
1896 mono_arch_is_inst_imm (gint64 imm)
1897 {
1898         return TRUE;
1899 }
1900
1901 #define DYN_CALL_STACK_ARGS 6
1902
1903 typedef struct {
1904         MonoMethodSignature *sig;
1905         CallInfo *cinfo;
1906 } ArchDynCallInfo;
1907
1908 typedef struct {
1909         mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
1910         mgreg_t res, res2;
1911         guint8 *ret;
1912 } DynCallArgs;
1913
1914 static gboolean
1915 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1916 {
1917         int i;
1918
1919         if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1920                 return FALSE;
1921
1922         switch (cinfo->ret.storage) {
1923         case RegTypeNone:
1924         case RegTypeGeneral:
1925         case RegTypeIRegPair:
1926         case RegTypeStructByAddr:
1927                 break;
1928         case RegTypeFP:
1929 #ifdef ARM_FPU_FPA
1930                 return FALSE;
1931 #elif defined(ARM_FPU_VFP)
1932                 break;
1933 #else
1934                 return FALSE;
1935 #endif
1936         default:
1937                 return FALSE;
1938         }
1939
1940         for (i = 0; i < cinfo->nargs; ++i) {
1941                 switch (cinfo->args [i].storage) {
1942                 case RegTypeGeneral:
1943                         break;
1944                 case RegTypeIRegPair:
1945                         break;
1946                 case RegTypeBase:
1947                         if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
1948                                 return FALSE;
1949                         break;
1950                 case RegTypeStructByVal:
1951                         if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
1952                                 return FALSE;
1953                         break;
1954                 default:
1955                         return FALSE;
1956                 }
1957         }
1958
1959         // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
1960         for (i = 0; i < sig->param_count; ++i) {
1961                 MonoType *t = sig->params [i];
1962
1963                 if (t->byref)
1964                         continue;
1965
1966                 switch (t->type) {
1967                 case MONO_TYPE_R4:
1968                 case MONO_TYPE_R8:
1969 #ifdef MONO_ARCH_SOFT_FLOAT
1970                         return FALSE;
1971 #else
1972                         break;
1973 #endif
1974                         /*
1975                 case MONO_TYPE_I8:
1976                 case MONO_TYPE_U8:
1977                         return FALSE;
1978                         */
1979                 default:
1980                         break;
1981                 }
1982         }
1983
1984         return TRUE;
1985 }
1986
1987 MonoDynCallInfo*
1988 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1989 {
1990         ArchDynCallInfo *info;
1991         CallInfo *cinfo;
1992
1993         cinfo = get_call_info (NULL, NULL, sig);
1994
1995         if (!dyn_call_supported (cinfo, sig)) {
1996                 g_free (cinfo);
1997                 return NULL;
1998         }
1999
2000         info = g_new0 (ArchDynCallInfo, 1);
2001         // FIXME: Preprocess the info to speed up start_dyn_call ()
2002         info->sig = sig;
2003         info->cinfo = cinfo;
2004
2005         return (MonoDynCallInfo*)info;
2006 }
2007
2008 void
2009 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2010 {
2011         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2012
2013         g_free (ainfo->cinfo);
2014         g_free (ainfo);
2015 }
2016
2017 void
2018 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2019 {
2020         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2021         DynCallArgs *p = (DynCallArgs*)buf;
2022         int arg_index, greg, i, j, pindex;
2023         MonoMethodSignature *sig = dinfo->sig;
2024
2025         g_assert (buf_len >= sizeof (DynCallArgs));
2026
2027         p->res = 0;
2028         p->ret = ret;
2029
2030         arg_index = 0;
2031         greg = 0;
2032         pindex = 0;
2033
2034         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2035                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2036                 if (!sig->hasthis)
2037                         pindex = 1;
2038         }
2039
2040         if (dinfo->cinfo->vtype_retaddr)
2041                 p->regs [greg ++] = (mgreg_t)ret;
2042
2043         for (i = pindex; i < sig->param_count; i++) {
2044                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2045                 gpointer *arg = args [arg_index ++];
2046                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2047                 int slot = -1;
2048
2049                 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2050                         slot = ainfo->reg;
2051                 else if (ainfo->storage == RegTypeBase)
2052                         slot = PARAM_REGS + (ainfo->offset / 4);
2053                 else
2054                         g_assert_not_reached ();
2055
2056                 if (t->byref) {
2057                         p->regs [slot] = (mgreg_t)*arg;
2058                         continue;
2059                 }
2060
2061                 switch (t->type) {
2062                 case MONO_TYPE_STRING:
2063                 case MONO_TYPE_CLASS:
2064                 case MONO_TYPE_ARRAY:
2065                 case MONO_TYPE_SZARRAY:
2066                 case MONO_TYPE_OBJECT:
2067                 case MONO_TYPE_PTR:
2068                 case MONO_TYPE_I:
2069                 case MONO_TYPE_U:
2070                         p->regs [slot] = (mgreg_t)*arg;
2071                         break;
2072                 case MONO_TYPE_BOOLEAN:
2073                 case MONO_TYPE_U1:
2074                         p->regs [slot] = *(guint8*)arg;
2075                         break;
2076                 case MONO_TYPE_I1:
2077                         p->regs [slot] = *(gint8*)arg;
2078                         break;
2079                 case MONO_TYPE_I2:
2080                         p->regs [slot] = *(gint16*)arg;
2081                         break;
2082                 case MONO_TYPE_U2:
2083                 case MONO_TYPE_CHAR:
2084                         p->regs [slot] = *(guint16*)arg;
2085                         break;
2086                 case MONO_TYPE_I4:
2087                         p->regs [slot] = *(gint32*)arg;
2088                         break;
2089                 case MONO_TYPE_U4:
2090                         p->regs [slot] = *(guint32*)arg;
2091                         break;
2092                 case MONO_TYPE_I8:
2093                 case MONO_TYPE_U8:
2094                         p->regs [slot ++] = (mgreg_t)arg [0];
2095                         p->regs [slot] = (mgreg_t)arg [1];
2096                         break;
2097                 case MONO_TYPE_R4:
2098                         p->regs [slot] = *(mgreg_t*)arg;
2099                         break;
2100                 case MONO_TYPE_R8:
2101                         p->regs [slot ++] = (mgreg_t)arg [0];
2102                         p->regs [slot] = (mgreg_t)arg [1];
2103                         break;
2104                 case MONO_TYPE_GENERICINST:
2105                         if (MONO_TYPE_IS_REFERENCE (t)) {
2106                                 p->regs [slot] = (mgreg_t)*arg;
2107                                 break;
2108                         } else {
2109                                 /* Fall though */
2110                         }
2111                 case MONO_TYPE_VALUETYPE:
2112                         g_assert (ainfo->storage == RegTypeStructByVal);
2113
2114                         if (ainfo->size == 0)
2115                                 slot = PARAM_REGS + (ainfo->offset / 4);
2116                         else
2117                                 slot = ainfo->reg;
2118
2119                         for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2120                                 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2121                         break;
2122                 default:
2123                         g_assert_not_reached ();
2124                 }
2125         }
2126 }
2127
2128 void
2129 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2130 {
2131         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2132         MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2133         guint8 *ret = ((DynCallArgs*)buf)->ret;
2134         mgreg_t res = ((DynCallArgs*)buf)->res;
2135         mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2136
2137         switch (mono_type_get_underlying_type (sig->ret)->type) {
2138         case MONO_TYPE_VOID:
2139                 *(gpointer*)ret = NULL;
2140                 break;
2141         case MONO_TYPE_STRING:
2142         case MONO_TYPE_CLASS:
2143         case MONO_TYPE_ARRAY:
2144         case MONO_TYPE_SZARRAY:
2145         case MONO_TYPE_OBJECT:
2146         case MONO_TYPE_I:
2147         case MONO_TYPE_U:
2148         case MONO_TYPE_PTR:
2149                 *(gpointer*)ret = (gpointer)res;
2150                 break;
2151         case MONO_TYPE_I1:
2152                 *(gint8*)ret = res;
2153                 break;
2154         case MONO_TYPE_U1:
2155         case MONO_TYPE_BOOLEAN:
2156                 *(guint8*)ret = res;
2157                 break;
2158         case MONO_TYPE_I2:
2159                 *(gint16*)ret = res;
2160                 break;
2161         case MONO_TYPE_U2:
2162         case MONO_TYPE_CHAR:
2163                 *(guint16*)ret = res;
2164                 break;
2165         case MONO_TYPE_I4:
2166                 *(gint32*)ret = res;
2167                 break;
2168         case MONO_TYPE_U4:
2169                 *(guint32*)ret = res;
2170                 break;
2171         case MONO_TYPE_I8:
2172         case MONO_TYPE_U8:
2173                 /* This handles endianness as well */
2174                 ((gint32*)ret) [0] = res;
2175                 ((gint32*)ret) [1] = res2;
2176                 break;
2177         case MONO_TYPE_GENERICINST:
2178                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2179                         *(gpointer*)ret = (gpointer)res;
2180                         break;
2181                 } else {
2182                         /* Fall though */
2183                 }
2184         case MONO_TYPE_VALUETYPE:
2185                 g_assert (ainfo->cinfo->vtype_retaddr);
2186                 /* Nothing to do */
2187                 break;
2188 #if defined(ARM_FPU_VFP)
2189         case MONO_TYPE_R4:
2190                 *(float*)ret = *(float*)&res;
2191                 break;
2192         case MONO_TYPE_R8: {
2193                 mgreg_t regs [2];
2194
2195                 regs [0] = res;
2196                 regs [1] = res2;
2197
2198                 *(double*)ret = *(double*)&regs;
2199                 break;
2200         }
2201 #endif
2202         default:
2203                 g_assert_not_reached ();
2204         }
2205 }
2206
2207 #ifndef DISABLE_JIT
2208
2209 /*
2210  * Allow tracing to work with this interface (with an optional argument)
2211  */
2212
2213 void*
2214 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2215 {
2216         guchar *code = p;
2217
2218         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2219         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2220         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2221         code = emit_call_reg (code, ARMREG_R2);
2222         return code;
2223 }
2224
2225 enum {
2226         SAVE_NONE,
2227         SAVE_STRUCT,
2228         SAVE_ONE,
2229         SAVE_TWO,
2230         SAVE_FP
2231 };
2232
2233 void*
2234 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2235 {
2236         guchar *code = p;
2237         int save_mode = SAVE_NONE;
2238         int offset;
2239         MonoMethod *method = cfg->method;
2240         int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2241         int save_offset = cfg->param_area;
2242         save_offset += 7;
2243         save_offset &= ~7;
2244
2245         offset = code - cfg->native_code;
2246         /* we need about 16 instructions */
2247         if (offset > (cfg->code_size - 16 * 4)) {
2248                 cfg->code_size *= 2;
2249                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2250                 code = cfg->native_code + offset;
2251         }
2252         switch (rtype) {
2253         case MONO_TYPE_VOID:
2254                 /* special case string .ctor icall */
2255                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2256                         save_mode = SAVE_ONE;
2257                 else
2258                         save_mode = SAVE_NONE;
2259                 break;
2260         case MONO_TYPE_I8:
2261         case MONO_TYPE_U8:
2262                 save_mode = SAVE_TWO;
2263                 break;
2264         case MONO_TYPE_R4:
2265         case MONO_TYPE_R8:
2266                 save_mode = SAVE_FP;
2267                 break;
2268         case MONO_TYPE_VALUETYPE:
2269                 save_mode = SAVE_STRUCT;
2270                 break;
2271         default:
2272                 save_mode = SAVE_ONE;
2273                 break;
2274         }
2275
2276         switch (save_mode) {
2277         case SAVE_TWO:
2278                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2279                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2280                 if (enable_arguments) {
2281                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2282                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2283                 }
2284                 break;
2285         case SAVE_ONE:
2286                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2287                 if (enable_arguments) {
2288                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2289                 }
2290                 break;
2291         case SAVE_FP:
2292                 /* FIXME: what reg?  */
2293                 if (enable_arguments) {
2294                         /* FIXME: what reg?  */
2295                 }
2296                 break;
2297         case SAVE_STRUCT:
2298                 if (enable_arguments) {
2299                         /* FIXME: get the actual address  */
2300                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2301                 }
2302                 break;
2303         case SAVE_NONE:
2304         default:
2305                 break;
2306         }
2307
2308         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2309         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2310         code = emit_call_reg (code, ARMREG_IP);
2311
2312         switch (save_mode) {
2313         case SAVE_TWO:
2314                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2315                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2316                 break;
2317         case SAVE_ONE:
2318                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2319                 break;
2320         case SAVE_FP:
2321                 /* FIXME */
2322                 break;
2323         case SAVE_NONE:
2324         default:
2325                 break;
2326         }
2327
2328         return code;
2329 }
2330
2331 /*
2332  * The immediate field for cond branches is big enough for all reasonable methods
2333  */
2334 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2335 if (0 && ins->inst_true_bb->native_offset) { \
2336         ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2337 } else { \
2338         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2339         ARM_B_COND (code, (condcode), 0);       \
2340 }
2341
2342 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2343
2344 /* emit an exception if condition is fail
2345  *
2346  * We assign the extra code used to throw the implicit exceptions
2347  * to cfg->bb_exit as far as the big branch handling is concerned
2348  */
2349 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
2350         do {                                                        \
2351                 mono_add_patch_info (cfg, code - cfg->native_code,   \
2352                                     MONO_PATCH_INFO_EXC, exc_name);  \
2353                 ARM_BL_COND (code, (condcode), 0);      \
2354         } while (0);
2355
2356 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2357
2358 void
2359 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2360 {
2361 }
2362
2363 void
2364 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2365 {
2366         MonoInst *ins, *n, *last_ins = NULL;
2367
2368         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2369                 switch (ins->opcode) {
2370                 case OP_MUL_IMM:
2371                 case OP_IMUL_IMM:
2372                         /* Already done by an arch-independent pass */
2373                         break;
2374                 case OP_LOAD_MEMBASE:
2375                 case OP_LOADI4_MEMBASE:
2376                         /*
2377                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2378                          * OP_LOAD_MEMBASE offset(basereg), reg
2379                          */
2380                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2381                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2382                             ins->inst_basereg == last_ins->inst_destbasereg &&
2383                             ins->inst_offset == last_ins->inst_offset) {
2384                                 if (ins->dreg == last_ins->sreg1) {
2385                                         MONO_DELETE_INS (bb, ins);
2386                                         continue;
2387                                 } else {
2388                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2389                                         ins->opcode = OP_MOVE;
2390                                         ins->sreg1 = last_ins->sreg1;
2391                                 }
2392
2393                         /*
2394                          * Note: reg1 must be different from the basereg in the second load
2395                          * OP_LOAD_MEMBASE offset(basereg), reg1
2396                          * OP_LOAD_MEMBASE offset(basereg), reg2
2397                          * -->
2398                          * OP_LOAD_MEMBASE offset(basereg), reg1
2399                          * OP_MOVE reg1, reg2
2400                          */
2401                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2402                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2403                               ins->inst_basereg != last_ins->dreg &&
2404                               ins->inst_basereg == last_ins->inst_basereg &&
2405                               ins->inst_offset == last_ins->inst_offset) {
2406
2407                                 if (ins->dreg == last_ins->dreg) {
2408                                         MONO_DELETE_INS (bb, ins);
2409                                         continue;
2410                                 } else {
2411                                         ins->opcode = OP_MOVE;
2412                                         ins->sreg1 = last_ins->dreg;
2413                                 }
2414
2415                                 //g_assert_not_reached ();
2416
2417 #if 0
2418                         /*
2419                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2420                          * OP_LOAD_MEMBASE offset(basereg), reg
2421                          * -->
2422                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2423                          * OP_ICONST reg, imm
2424                          */
2425                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2426                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2427                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2428                                    ins->inst_offset == last_ins->inst_offset) {
2429                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2430                                 ins->opcode = OP_ICONST;
2431                                 ins->inst_c0 = last_ins->inst_imm;
2432                                 g_assert_not_reached (); // check this rule
2433 #endif
2434                         }
2435                         break;
2436                 case OP_LOADU1_MEMBASE:
2437                 case OP_LOADI1_MEMBASE:
2438                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2439                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2440                                         ins->inst_offset == last_ins->inst_offset) {
2441                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2442                                 ins->sreg1 = last_ins->sreg1;
2443                         }
2444                         break;
2445                 case OP_LOADU2_MEMBASE:
2446                 case OP_LOADI2_MEMBASE:
2447                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2448                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2449                                         ins->inst_offset == last_ins->inst_offset) {
2450                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2451                                 ins->sreg1 = last_ins->sreg1;
2452                         }
2453                         break;
2454                 case OP_MOVE:
2455                         ins->opcode = OP_MOVE;
2456                         /*
2457                          * OP_MOVE reg, reg
2458                          */
2459                         if (ins->dreg == ins->sreg1) {
2460                                 MONO_DELETE_INS (bb, ins);
2461                                 continue;
2462                         }
2463                         /*
2464                          * OP_MOVE sreg, dreg
2465                          * OP_MOVE dreg, sreg
2466                          */
2467                         if (last_ins && last_ins->opcode == OP_MOVE &&
2468                             ins->sreg1 == last_ins->dreg &&
2469                             ins->dreg == last_ins->sreg1) {
2470                                 MONO_DELETE_INS (bb, ins);
2471                                 continue;
2472                         }
2473                         break;
2474                 }
2475                 last_ins = ins;
2476                 ins = ins->next;
2477         }
2478         bb->last_ins = last_ins;
2479 }
2480
2481 /*
2482  * the branch_cc_table should maintain the order of these
2483  * opcodes.
2484 case CEE_BEQ:
2485 case CEE_BGE:
2486 case CEE_BGT:
2487 case CEE_BLE:
2488 case CEE_BLT:
2489 case CEE_BNE_UN:
2490 case CEE_BGE_UN:
2491 case CEE_BGT_UN:
2492 case CEE_BLE_UN:
2493 case CEE_BLT_UN:
2494  */
2495 static const guchar
2496 branch_cc_table [] = {
2497         ARMCOND_EQ,
2498         ARMCOND_GE,
2499         ARMCOND_GT,
2500         ARMCOND_LE,
2501         ARMCOND_LT,
2502
2503         ARMCOND_NE,
2504         ARMCOND_HS,
2505         ARMCOND_HI,
2506         ARMCOND_LS,
2507         ARMCOND_LO
2508 };
2509
2510 #define NEW_INS(cfg,dest,op) do {       \
2511                 MONO_INST_NEW ((cfg), (dest), (op)); \
2512         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2513         } while (0)
2514
2515 static int
2516 map_to_reg_reg_op (int op)
2517 {
2518         switch (op) {
2519         case OP_ADD_IMM:
2520                 return OP_IADD;
2521         case OP_SUB_IMM:
2522                 return OP_ISUB;
2523         case OP_AND_IMM:
2524                 return OP_IAND;
2525         case OP_COMPARE_IMM:
2526                 return OP_COMPARE;
2527         case OP_ICOMPARE_IMM:
2528                 return OP_ICOMPARE;
2529         case OP_ADDCC_IMM:
2530                 return OP_ADDCC;
2531         case OP_ADC_IMM:
2532                 return OP_ADC;
2533         case OP_SUBCC_IMM:
2534                 return OP_SUBCC;
2535         case OP_SBB_IMM:
2536                 return OP_SBB;
2537         case OP_OR_IMM:
2538                 return OP_IOR;
2539         case OP_XOR_IMM:
2540                 return OP_IXOR;
2541         case OP_LOAD_MEMBASE:
2542                 return OP_LOAD_MEMINDEX;
2543         case OP_LOADI4_MEMBASE:
2544                 return OP_LOADI4_MEMINDEX;
2545         case OP_LOADU4_MEMBASE:
2546                 return OP_LOADU4_MEMINDEX;
2547         case OP_LOADU1_MEMBASE:
2548                 return OP_LOADU1_MEMINDEX;
2549         case OP_LOADI2_MEMBASE:
2550                 return OP_LOADI2_MEMINDEX;
2551         case OP_LOADU2_MEMBASE:
2552                 return OP_LOADU2_MEMINDEX;
2553         case OP_LOADI1_MEMBASE:
2554                 return OP_LOADI1_MEMINDEX;
2555         case OP_STOREI1_MEMBASE_REG:
2556                 return OP_STOREI1_MEMINDEX;
2557         case OP_STOREI2_MEMBASE_REG:
2558                 return OP_STOREI2_MEMINDEX;
2559         case OP_STOREI4_MEMBASE_REG:
2560                 return OP_STOREI4_MEMINDEX;
2561         case OP_STORE_MEMBASE_REG:
2562                 return OP_STORE_MEMINDEX;
2563         case OP_STORER4_MEMBASE_REG:
2564                 return OP_STORER4_MEMINDEX;
2565         case OP_STORER8_MEMBASE_REG:
2566                 return OP_STORER8_MEMINDEX;
2567         case OP_STORE_MEMBASE_IMM:
2568                 return OP_STORE_MEMBASE_REG;
2569         case OP_STOREI1_MEMBASE_IMM:
2570                 return OP_STOREI1_MEMBASE_REG;
2571         case OP_STOREI2_MEMBASE_IMM:
2572                 return OP_STOREI2_MEMBASE_REG;
2573         case OP_STOREI4_MEMBASE_IMM:
2574                 return OP_STOREI4_MEMBASE_REG;
2575         }
2576         g_assert_not_reached ();
2577 }
2578
2579 /*
2580  * Remove from the instruction list the instructions that can't be
2581  * represented with very simple instructions with no register
2582  * requirements.
2583  */
2584 void
2585 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2586 {
2587         MonoInst *ins, *temp, *last_ins = NULL;
2588         int rot_amount, imm8, low_imm;
2589
2590         MONO_BB_FOR_EACH_INS (bb, ins) {
2591 loop_start:
2592                 switch (ins->opcode) {
2593                 case OP_ADD_IMM:
2594                 case OP_SUB_IMM:
2595                 case OP_AND_IMM:
2596                 case OP_COMPARE_IMM:
2597                 case OP_ICOMPARE_IMM:
2598                 case OP_ADDCC_IMM:
2599                 case OP_ADC_IMM:
2600                 case OP_SUBCC_IMM:
2601                 case OP_SBB_IMM:
2602                 case OP_OR_IMM:
2603                 case OP_XOR_IMM:
2604                 case OP_IADD_IMM:
2605                 case OP_ISUB_IMM:
2606                 case OP_IAND_IMM:
2607                 case OP_IADC_IMM:
2608                 case OP_ISBB_IMM:
2609                 case OP_IOR_IMM:
2610                 case OP_IXOR_IMM:
2611                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2612                                 NEW_INS (cfg, temp, OP_ICONST);
2613                                 temp->inst_c0 = ins->inst_imm;
2614                                 temp->dreg = mono_alloc_ireg (cfg);
2615                                 ins->sreg2 = temp->dreg;
2616                                 ins->opcode = mono_op_imm_to_op (ins->opcode);
2617                         }
2618                         if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2619                                 goto loop_start;
2620                         else
2621                                 break;
2622                 case OP_MUL_IMM:
2623                 case OP_IMUL_IMM:
2624                         if (ins->inst_imm == 1) {
2625                                 ins->opcode = OP_MOVE;
2626                                 break;
2627                         }
2628                         if (ins->inst_imm == 0) {
2629                                 ins->opcode = OP_ICONST;
2630                                 ins->inst_c0 = 0;
2631                                 break;
2632                         }
2633                         imm8 = mono_is_power_of_two (ins->inst_imm);
2634                         if (imm8 > 0) {
2635                                 ins->opcode = OP_SHL_IMM;
2636                                 ins->inst_imm = imm8;
2637                                 break;
2638                         }
2639                         NEW_INS (cfg, temp, OP_ICONST);
2640                         temp->inst_c0 = ins->inst_imm;
2641                         temp->dreg = mono_alloc_ireg (cfg);
2642                         ins->sreg2 = temp->dreg;
2643                         ins->opcode = OP_IMUL;
2644                         break;
2645                 case OP_SBB:
2646                 case OP_ISBB:
2647                 case OP_SUBCC:
2648                 case OP_ISUBCC:
2649                         if (ins->next  && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2650                                 /* ARM sets the C flag to 1 if there was _no_ overflow */
2651                                 ins->next->opcode = OP_COND_EXC_NC;
2652                         break;
2653                 case OP_LOCALLOC_IMM:
2654                         NEW_INS (cfg, temp, OP_ICONST);
2655                         temp->inst_c0 = ins->inst_imm;
2656                         temp->dreg = mono_alloc_ireg (cfg);
2657                         ins->sreg1 = temp->dreg;
2658                         ins->opcode = OP_LOCALLOC;
2659                         break;
2660                 case OP_LOAD_MEMBASE:
2661                 case OP_LOADI4_MEMBASE:
2662                 case OP_LOADU4_MEMBASE:
2663                 case OP_LOADU1_MEMBASE:
2664                         /* we can do two things: load the immed in a register
2665                          * and use an indexed load, or see if the immed can be
2666                          * represented as an ad_imm + a load with a smaller offset
2667                          * that fits. We just do the first for now, optimize later.
2668                          */
2669                         if (arm_is_imm12 (ins->inst_offset))
2670                                 break;
2671                         NEW_INS (cfg, temp, OP_ICONST);
2672                         temp->inst_c0 = ins->inst_offset;
2673                         temp->dreg = mono_alloc_ireg (cfg);
2674                         ins->sreg2 = temp->dreg;
2675                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2676                         break;
2677                 case OP_LOADI2_MEMBASE:
2678                 case OP_LOADU2_MEMBASE:
2679                 case OP_LOADI1_MEMBASE:
2680                         if (arm_is_imm8 (ins->inst_offset))
2681                                 break;
2682                         NEW_INS (cfg, temp, OP_ICONST);
2683                         temp->inst_c0 = ins->inst_offset;
2684                         temp->dreg = mono_alloc_ireg (cfg);
2685                         ins->sreg2 = temp->dreg;
2686                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2687                         break;
2688                 case OP_LOADR4_MEMBASE:
2689                 case OP_LOADR8_MEMBASE:
2690                         if (arm_is_fpimm8 (ins->inst_offset))
2691                                 break;
2692                         low_imm = ins->inst_offset & 0x1ff;
2693                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2694                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2695                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2696                                 temp->sreg1 = ins->inst_basereg;
2697                                 temp->dreg = mono_alloc_ireg (cfg);
2698                                 ins->inst_basereg = temp->dreg;
2699                                 ins->inst_offset = low_imm;
2700                                 break;
2701                         }
2702                         /* VFP/FPA doesn't have indexed load instructions */
2703                         g_assert_not_reached ();
2704                         break;
2705                 case OP_STORE_MEMBASE_REG:
2706                 case OP_STOREI4_MEMBASE_REG:
2707                 case OP_STOREI1_MEMBASE_REG:
2708                         if (arm_is_imm12 (ins->inst_offset))
2709                                 break;
2710                         NEW_INS (cfg, temp, OP_ICONST);
2711                         temp->inst_c0 = ins->inst_offset;
2712                         temp->dreg = mono_alloc_ireg (cfg);
2713                         ins->sreg2 = temp->dreg;
2714                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2715                         break;
2716                 case OP_STOREI2_MEMBASE_REG:
2717                         if (arm_is_imm8 (ins->inst_offset))
2718                                 break;
2719                         NEW_INS (cfg, temp, OP_ICONST);
2720                         temp->inst_c0 = ins->inst_offset;
2721                         temp->dreg = mono_alloc_ireg (cfg);
2722                         ins->sreg2 = temp->dreg;
2723                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2724                         break;
2725                 case OP_STORER4_MEMBASE_REG:
2726                 case OP_STORER8_MEMBASE_REG:
2727                         if (arm_is_fpimm8 (ins->inst_offset))
2728                                 break;
2729                         low_imm = ins->inst_offset & 0x1ff;
2730                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2731                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2732                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2733                                 temp->sreg1 = ins->inst_destbasereg;
2734                                 temp->dreg = mono_alloc_ireg (cfg);
2735                                 ins->inst_destbasereg = temp->dreg;
2736                                 ins->inst_offset = low_imm;
2737                                 break;
2738                         }
2739                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2740                         /* VFP/FPA doesn't have indexed store instructions */
2741                         g_assert_not_reached ();
2742                         break;
2743                 case OP_STORE_MEMBASE_IMM:
2744                 case OP_STOREI1_MEMBASE_IMM:
2745                 case OP_STOREI2_MEMBASE_IMM:
2746                 case OP_STOREI4_MEMBASE_IMM:
2747                         NEW_INS (cfg, temp, OP_ICONST);
2748                         temp->inst_c0 = ins->inst_imm;
2749                         temp->dreg = mono_alloc_ireg (cfg);
2750                         ins->sreg1 = temp->dreg;
2751                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2752                         last_ins = temp;
2753                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
2754                 case OP_FCOMPARE: {
2755                         gboolean swap = FALSE;
2756                         int reg;
2757
2758                         if (!ins->next) {
2759                                 /* Optimized away */
2760                                 NULLIFY_INS (ins);
2761                                 break;
2762                         }
2763
2764                         /* Some fp compares require swapped operands */
2765                         switch (ins->next->opcode) {
2766                         case OP_FBGT:
2767                                 ins->next->opcode = OP_FBLT;
2768                                 swap = TRUE;
2769                                 break;
2770                         case OP_FBGT_UN:
2771                                 ins->next->opcode = OP_FBLT_UN;
2772                                 swap = TRUE;
2773                                 break;
2774                         case OP_FBLE:
2775                                 ins->next->opcode = OP_FBGE;
2776                                 swap = TRUE;
2777                                 break;
2778                         case OP_FBLE_UN:
2779                                 ins->next->opcode = OP_FBGE_UN;
2780                                 swap = TRUE;
2781                                 break;
2782                         default:
2783                                 break;
2784                         }
2785                         if (swap) {
2786                                 reg = ins->sreg1;
2787                                 ins->sreg1 = ins->sreg2;
2788                                 ins->sreg2 = reg;
2789                         }
2790                         break;
2791                 }
2792                 }
2793
2794                 last_ins = ins;
2795         }
2796         bb->last_ins = last_ins;
2797         bb->max_vreg = cfg->next_vreg;
2798 }
2799
2800 void
2801 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2802 {
2803         MonoInst *ins;
2804
2805         if (long_ins->opcode == OP_LNEG) {
2806                 ins = long_ins;
2807                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2808                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2809                 NULLIFY_INS (ins);
2810         }
2811 }
2812
2813 static guchar*
2814 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2815 {
2816         /* sreg is a float, dreg is an integer reg  */
2817 #ifdef ARM_FPU_FPA
2818         ARM_FIXZ (code, dreg, sreg);
2819 #elif defined(ARM_FPU_VFP)
2820         if (is_signed)
2821                 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2822         else
2823                 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2824         ARM_FMRS (code, dreg, ARM_VFP_F0);
2825 #endif
2826         if (!is_signed) {
2827                 if (size == 1)
2828                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
2829                 else if (size == 2) {
2830                         ARM_SHL_IMM (code, dreg, dreg, 16);
2831                         ARM_SHR_IMM (code, dreg, dreg, 16);
2832                 }
2833         } else {
2834                 if (size == 1) {
2835                         ARM_SHL_IMM (code, dreg, dreg, 24);
2836                         ARM_SAR_IMM (code, dreg, dreg, 24);
2837                 } else if (size == 2) {
2838                         ARM_SHL_IMM (code, dreg, dreg, 16);
2839                         ARM_SAR_IMM (code, dreg, dreg, 16);
2840                 }
2841         }
2842         return code;
2843 }
2844
2845 #endif /* #ifndef DISABLE_JIT */
2846
2847 typedef struct {
2848         guchar *code;
2849         const guchar *target;
2850         int absolute;
2851         int found;
2852 } PatchData;
2853
2854 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
2855
2856 static int
2857 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
2858         PatchData *pdata = (PatchData*)user_data;
2859         guchar *code = data;
2860         guint32 *thunks = data;
2861         guint32 *endthunks = (guint32*)(code + bsize);
2862         int count = 0;
2863         int difflow, diffhigh;
2864
2865         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
2866         difflow = (char*)pdata->code - (char*)thunks;
2867         diffhigh = (char*)pdata->code - (char*)endthunks;
2868         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
2869                 return 0;
2870
2871         /*
2872          * The thunk is composed of 3 words:
2873          * load constant from thunks [2] into ARM_IP
2874          * bx to ARM_IP
2875          * address constant
2876          * Note that the LR register is already setup
2877          */
2878         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
2879         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
2880                 while (thunks < endthunks) {
2881                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
2882                         if (thunks [2] == (guint32)pdata->target) {
2883                                 arm_patch (pdata->code, (guchar*)thunks);
2884                                 mono_arch_flush_icache (pdata->code, 4);
2885                                 pdata->found = 1;
2886                                 return 1;
2887                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
2888                                 /* found a free slot instead: emit thunk */
2889                                 /* ARMREG_IP is fine to use since this can't be an IMT call
2890                                  * which is indirect
2891                                  */
2892                                 code = (guchar*)thunks;
2893                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
2894                                 if (thumb_supported)
2895                                         ARM_BX (code, ARMREG_IP);
2896                                 else
2897                                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
2898                                 thunks [2] = (guint32)pdata->target;
2899                                 mono_arch_flush_icache ((guchar*)thunks, 12);
2900
2901                                 arm_patch (pdata->code, (guchar*)thunks);
2902                                 mono_arch_flush_icache (pdata->code, 4);
2903                                 pdata->found = 1;
2904                                 return 1;
2905                         }
2906                         /* skip 12 bytes, the size of the thunk */
2907                         thunks += 3;
2908                         count++;
2909                 }
2910                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
2911         }
2912         return 0;
2913 }
2914
2915 static void
2916 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
2917 {
2918         PatchData pdata;
2919
2920         if (!domain)
2921                 domain = mono_domain_get ();
2922
2923         pdata.code = code;
2924         pdata.target = target;
2925         pdata.absolute = absolute;
2926         pdata.found = 0;
2927
2928         if (dyn_code_mp) {
2929                 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
2930         }
2931
2932         if (pdata.found != 1) {
2933                 mono_domain_lock (domain);
2934                 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2935
2936                 if (!pdata.found) {
2937                         /* this uses the first available slot */
2938                         pdata.found = 2;
2939                         mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
2940                 }
2941                 mono_domain_unlock (domain);
2942         }
2943
2944         if (pdata.found != 1) {
2945                 GHashTable *hash;
2946                 GHashTableIter iter;
2947                 MonoJitDynamicMethodInfo *ji;
2948
2949                 /*
2950                  * This might be a dynamic method, search its code manager. We can only
2951                  * use the dynamic method containing CODE, since the others might be freed later.
2952                  */
2953                 pdata.found = 0;
2954
2955                 mono_domain_lock (domain);
2956                 hash = domain_jit_info (domain)->dynamic_code_hash;
2957                 if (hash) {
2958                         /* FIXME: Speed this up */
2959                         g_hash_table_iter_init (&iter, hash);
2960                         while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
2961                                 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
2962                                 if (pdata.found == 1)
2963                                         break;
2964                         }
2965                 }
2966                 mono_domain_unlock (domain);
2967         }
2968         if (pdata.found != 1)
2969                 g_print ("thunk failed for %p from %p\n", target, code);
2970         g_assert (pdata.found == 1);
2971 }
2972
2973 static void
2974 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
2975 {
2976         guint32 *code32 = (void*)code;
2977         guint32 ins = *code32;
2978         guint32 prim = (ins >> 25) & 7;
2979         guint32 tval = GPOINTER_TO_UINT (target);
2980
2981         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
2982         if (prim == 5) { /* 101b */
2983                 /* the diff starts 8 bytes from the branch opcode */
2984                 gint diff = target - code - 8;
2985                 gint tbits;
2986                 gint tmask = 0xffffffff;
2987                 if (tval & 1) { /* entering thumb mode */
2988                         diff = target - 1 - code - 8;
2989                         g_assert (thumb_supported);
2990                         tbits = 0xf << 28; /* bl->blx bit pattern */
2991                         g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
2992                         /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
2993                         if (diff & 2) {
2994                                 tbits |= 1 << 24;
2995                         }
2996                         tmask = ~(1 << 24); /* clear the link bit */
2997                         /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
2998                 } else {
2999                         tbits = 0;
3000                 }
3001                 if (diff >= 0) {
3002                         if (diff <= 33554431) {
3003                                 diff >>= 2;
3004                                 ins = (ins & 0xff000000) | diff;
3005                                 ins &= tmask;
3006                                 *code32 = ins | tbits;
3007                                 return;
3008                         }
3009                 } else {
3010                         /* diff between 0 and -33554432 */
3011                         if (diff >= -33554432) {
3012                                 diff >>= 2;
3013                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3014                                 ins &= tmask;
3015                                 *code32 = ins | tbits;
3016                                 return;
3017                         }
3018                 }
3019
3020                 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3021                 return;
3022         }
3023
3024         /*
3025          * The alternative call sequences looks like this:
3026          *
3027          *      ldr ip, [pc] // loads the address constant
3028          *      b 1f         // jumps around the constant
3029          *      address constant embedded in the code
3030          *   1f:
3031          *      mov lr, pc
3032          *      mov pc, ip
3033          *
3034          * There are two cases for patching:
3035          * a) at the end of method emission: in this case code points to the start
3036          *    of the call sequence
3037          * b) during runtime patching of the call site: in this case code points
3038          *    to the mov pc, ip instruction
3039          *
3040          * We have to handle also the thunk jump code sequence:
3041          *
3042          *      ldr ip, [pc]
3043          *      mov pc, ip
3044          *      address constant // execution never reaches here
3045          */
3046         if ((ins & 0x0ffffff0) == 0x12fff10) {
3047                 /* Branch and exchange: the address is constructed in a reg
3048                  * We can patch BX when the code sequence is the following:
3049                  *  ldr     ip, [pc, #0]    ; 0x8
3050                  *  b       0xc
3051                  *  .word code_ptr
3052                  *  mov     lr, pc
3053                  *  bx      ips
3054                  * */
3055                 guint32 ccode [4];
3056                 guint8 *emit = (guint8*)ccode;
3057                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3058                 ARM_B (emit, 0);
3059                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3060                 ARM_BX (emit, ARMREG_IP);
3061
3062                 /*patching from magic trampoline*/
3063                 if (ins == ccode [3]) {
3064                         g_assert (code32 [-4] == ccode [0]);
3065                         g_assert (code32 [-3] == ccode [1]);
3066                         g_assert (code32 [-1] == ccode [2]);
3067                         code32 [-2] = (guint32)target;
3068                         return;
3069                 }
3070                 /*patching from JIT*/
3071                 if (ins == ccode [0]) {
3072                         g_assert (code32 [1] == ccode [1]);
3073                         g_assert (code32 [3] == ccode [2]);
3074                         g_assert (code32 [4] == ccode [3]);
3075                         code32 [2] = (guint32)target;
3076                         return;
3077                 }
3078                 g_assert_not_reached ();
3079         } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3080                 /*
3081                  * ldr ip, [pc, #0]
3082                  * b 0xc
3083                  * .word code_ptr
3084                  * blx ip
3085                  */
3086                 guint32 ccode [4];
3087                 guint8 *emit = (guint8*)ccode;
3088                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3089                 ARM_B (emit, 0);
3090                 ARM_BLX_REG (emit, ARMREG_IP);
3091
3092                 g_assert (code32 [-3] == ccode [0]);
3093                 g_assert (code32 [-2] == ccode [1]);
3094                 g_assert (code32 [0] == ccode [2]);
3095
3096                 code32 [-1] = (guint32)target;
3097         } else {
3098                 guint32 ccode [4];
3099                 guint32 *tmp = ccode;
3100                 guint8 *emit = (guint8*)tmp;
3101                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3102                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3103                 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3104                 ARM_BX (emit, ARMREG_IP);
3105                 if (ins == ccode [2]) {
3106                         g_assert_not_reached (); // should be -2 ...
3107                         code32 [-1] = (guint32)target;
3108                         return;
3109                 }
3110                 if (ins == ccode [0]) {
3111                         /* handles both thunk jump code and the far call sequence */
3112                         code32 [2] = (guint32)target;
3113                         return;
3114                 }
3115                 g_assert_not_reached ();
3116         }
3117 //      g_print ("patched with 0x%08x\n", ins);
3118 }
3119
3120 void
3121 arm_patch (guchar *code, const guchar *target)
3122 {
3123         arm_patch_general (NULL, code, target, NULL);
3124 }
3125
3126 /*
3127  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3128  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3129  * to be used with the emit macros.
3130  * Return -1 otherwise.
3131  */
3132 int
3133 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3134 {
3135         guint32 res, i;
3136         for (i = 0; i < 31; i+= 2) {
3137                 res = (val << (32 - i)) | (val >> i);
3138                 if (res & ~0xff)
3139                         continue;
3140                 *rot_amount = i? 32 - i: 0;
3141                 return res;
3142         }
3143         return -1;
3144 }
3145
3146 /*
3147  * Emits in code a sequence of instructions that load the value 'val'
3148  * into the dreg register. Uses at most 4 instructions.
3149  */
3150 guint8*
3151 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3152 {
3153         int imm8, rot_amount;
3154 #if 0
3155         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3156         /* skip the constant pool */
3157         ARM_B (code, 0);
3158         *(int*)code = val;
3159         code += 4;
3160         return code;
3161 #endif
3162         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3163                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3164         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3165                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3166         } else {
3167                 if (v7_supported) {
3168                         ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3169                         if (val >> 16)
3170                                 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3171                         return code;
3172                 }
3173                 if (val & 0xFF) {
3174                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3175                         if (val & 0xFF00) {
3176                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3177                         }
3178                         if (val & 0xFF0000) {
3179                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3180                         }
3181                         if (val & 0xFF000000) {
3182                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3183                         }
3184                 } else if (val & 0xFF00) {
3185                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3186                         if (val & 0xFF0000) {
3187                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3188                         }
3189                         if (val & 0xFF000000) {
3190                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3191                         }
3192                 } else if (val & 0xFF0000) {
3193                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3194                         if (val & 0xFF000000) {
3195                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3196                         }
3197                 }
3198                 //g_assert_not_reached ();
3199         }
3200         return code;
3201 }
3202
3203 gboolean
3204 mono_arm_thumb_supported (void)
3205 {
3206         return thumb_supported;
3207 }
3208
3209 #ifndef DISABLE_JIT
3210
3211 /*
3212  * emit_load_volatile_arguments:
3213  *
3214  *  Load volatile arguments from the stack to the original input registers.
3215  * Required before a tail call.
3216  */
3217 static guint8*
3218 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3219 {
3220         MonoMethod *method = cfg->method;
3221         MonoMethodSignature *sig;
3222         MonoInst *inst;
3223         CallInfo *cinfo;
3224         guint32 i, pos;
3225
3226         /* FIXME: Generate intermediate code instead */
3227
3228         sig = mono_method_signature (method);
3229
3230         /* This is the opposite of the code in emit_prolog */
3231
3232         pos = 0;
3233
3234         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3235
3236         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3237                 ArgInfo *ainfo = &cinfo->ret;
3238                 inst = cfg->vret_addr;
3239                 g_assert (arm_is_imm12 (inst->inst_offset));
3240                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3241         }
3242         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3243                 ArgInfo *ainfo = cinfo->args + i;
3244                 inst = cfg->args [pos];
3245
3246                 if (cfg->verbose_level > 2)
3247                         g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3248                 if (inst->opcode == OP_REGVAR) {
3249                         if (ainfo->storage == RegTypeGeneral)
3250                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3251                         else if (ainfo->storage == RegTypeFP) {
3252                                 g_assert_not_reached ();
3253                         } else if (ainfo->storage == RegTypeBase) {
3254                                 // FIXME:
3255                                 NOT_IMPLEMENTED;
3256                                 /*
3257                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3258                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3259                                 } else {
3260                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3261                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3262                                 }
3263                                 */
3264                         } else
3265                                 g_assert_not_reached ();
3266                 } else {
3267                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3268                                 switch (ainfo->size) {
3269                                 case 1:
3270                                 case 2:
3271                                         // FIXME:
3272                                         NOT_IMPLEMENTED;
3273                                         break;
3274                                 case 8:
3275                                         g_assert (arm_is_imm12 (inst->inst_offset));
3276                                         ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3277                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
3278                                         ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3279                                         break;
3280                                 default:
3281                                         if (arm_is_imm12 (inst->inst_offset)) {
3282                                                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3283                                         } else {
3284                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3285                                                 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3286                                         }
3287                                         break;
3288                                 }
3289                         } else if (ainfo->storage == RegTypeBaseGen) {
3290                                 // FIXME:
3291                                 NOT_IMPLEMENTED;
3292                         } else if (ainfo->storage == RegTypeBase) {
3293                                 /* Nothing to do */
3294                         } else if (ainfo->storage == RegTypeFP) {
3295                                 g_assert_not_reached ();
3296                         } else if (ainfo->storage == RegTypeStructByVal) {
3297                                 int doffset = inst->inst_offset;
3298                                 int soffset = 0;
3299                                 int cur_reg;
3300                                 int size = 0;
3301                                 if (mono_class_from_mono_type (inst->inst_vtype))
3302                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3303                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3304                                         if (arm_is_imm12 (doffset)) {
3305                                                 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3306                                         } else {
3307                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3308                                                 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3309                                         }
3310                                         soffset += sizeof (gpointer);
3311                                         doffset += sizeof (gpointer);
3312                                 }
3313                                 if (ainfo->vtsize)
3314                                         // FIXME:
3315                                         NOT_IMPLEMENTED;
3316                         } else if (ainfo->storage == RegTypeStructByAddr) {
3317                         } else {
3318                                 // FIXME:
3319                                 NOT_IMPLEMENTED;
3320                         }
3321                 }
3322                 pos ++;
3323         }
3324
3325         g_free (cinfo);
3326
3327         return code;
3328 }
3329
3330 void
3331 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3332 {
3333         MonoInst *ins;
3334         MonoCallInst *call;
3335         guint offset;
3336         guint8 *code = cfg->native_code + cfg->code_len;
3337         MonoInst *last_ins = NULL;
3338         guint last_offset = 0;
3339         int max_len, cpos;
3340         int imm8, rot_amount;
3341
3342         /* we don't align basic blocks of loops on arm */
3343
3344         if (cfg->verbose_level > 2)
3345                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3346
3347         cpos = bb->max_offset;
3348
3349         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3350                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3351                 //g_assert (!mono_compile_aot);
3352                 //cpos += 6;
3353                 //if (bb->cil_code)
3354                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3355                 /* this is not thread save, but good enough */
3356                 /* fixme: howto handle overflows? */
3357                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3358         }
3359
3360     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3361                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3362                                                          (gpointer)"mono_break");
3363                 code = emit_call_seq (cfg, code);
3364         }
3365
3366         MONO_BB_FOR_EACH_INS (bb, ins) {
3367                 offset = code - cfg->native_code;
3368
3369                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3370
3371                 if (offset > (cfg->code_size - max_len - 16)) {
3372                         cfg->code_size *= 2;
3373                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3374                         code = cfg->native_code + offset;
3375                 }
3376         //      if (ins->cil_code)
3377         //              g_print ("cil code\n");
3378                 mono_debug_record_line_number (cfg, ins, offset);
3379
3380                 switch (ins->opcode) {
3381                 case OP_MEMORY_BARRIER:
3382                         if (v6_supported) {
3383                                 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3384                                 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3385                         }
3386                         break;
3387                 case OP_TLS_GET:
3388 #ifdef HAVE_AEABI_READ_TP
3389                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3390                                                                  (gpointer)"__aeabi_read_tp");
3391                         code = emit_call_seq (cfg, code);
3392
3393                         ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3394 #else
3395                         g_assert_not_reached ();
3396 #endif
3397                         break;
3398                 /*case OP_BIGMUL:
3399                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3400                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3401                         break;
3402                 case OP_BIGMUL_UN:
3403                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3404                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3405                         break;*/
3406                 case OP_STOREI1_MEMBASE_IMM:
3407                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3408                         g_assert (arm_is_imm12 (ins->inst_offset));
3409                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3410                         break;
3411                 case OP_STOREI2_MEMBASE_IMM:
3412                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3413                         g_assert (arm_is_imm8 (ins->inst_offset));
3414                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3415                         break;
3416                 case OP_STORE_MEMBASE_IMM:
3417                 case OP_STOREI4_MEMBASE_IMM:
3418                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3419                         g_assert (arm_is_imm12 (ins->inst_offset));
3420                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3421                         break;
3422                 case OP_STOREI1_MEMBASE_REG:
3423                         g_assert (arm_is_imm12 (ins->inst_offset));
3424                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3425                         break;
3426                 case OP_STOREI2_MEMBASE_REG:
3427                         g_assert (arm_is_imm8 (ins->inst_offset));
3428                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3429                         break;
3430                 case OP_STORE_MEMBASE_REG:
3431                 case OP_STOREI4_MEMBASE_REG:
3432                         /* this case is special, since it happens for spill code after lowering has been called */
3433                         if (arm_is_imm12 (ins->inst_offset)) {
3434                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3435                         } else {
3436                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3437                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3438                         }
3439                         break;
3440                 case OP_STOREI1_MEMINDEX:
3441                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3442                         break;
3443                 case OP_STOREI2_MEMINDEX:
3444                         ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3445                         break;
3446                 case OP_STORE_MEMINDEX:
3447                 case OP_STOREI4_MEMINDEX:
3448                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3449                         break;
3450                 case OP_LOADU4_MEM:
3451                         g_assert_not_reached ();
3452                         break;
3453                 case OP_LOAD_MEMINDEX:
3454                 case OP_LOADI4_MEMINDEX:
3455                 case OP_LOADU4_MEMINDEX:
3456                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3457                         break;
3458                 case OP_LOADI1_MEMINDEX:
3459                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3460                         break;
3461                 case OP_LOADU1_MEMINDEX:
3462                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3463                         break;
3464                 case OP_LOADI2_MEMINDEX:
3465                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3466                         break;
3467                 case OP_LOADU2_MEMINDEX:
3468                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3469                         break;
3470                 case OP_LOAD_MEMBASE:
3471                 case OP_LOADI4_MEMBASE:
3472                 case OP_LOADU4_MEMBASE:
3473                         /* this case is special, since it happens for spill code after lowering has been called */
3474                         if (arm_is_imm12 (ins->inst_offset)) {
3475                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3476                         } else {
3477                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3478                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3479                         }
3480                         break;
3481                 case OP_LOADI1_MEMBASE:
3482                         g_assert (arm_is_imm8 (ins->inst_offset));
3483                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3484                         break;
3485                 case OP_LOADU1_MEMBASE:
3486                         g_assert (arm_is_imm12 (ins->inst_offset));
3487                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3488                         break;
3489                 case OP_LOADU2_MEMBASE:
3490                         g_assert (arm_is_imm8 (ins->inst_offset));
3491                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3492                         break;
3493                 case OP_LOADI2_MEMBASE:
3494                         g_assert (arm_is_imm8 (ins->inst_offset));
3495                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3496                         break;
3497                 case OP_ICONV_TO_I1:
3498                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3499                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3500                         break;
3501                 case OP_ICONV_TO_I2:
3502                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3503                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3504                         break;
3505                 case OP_ICONV_TO_U1:
3506                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3507                         break;
3508                 case OP_ICONV_TO_U2:
3509                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3510                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3511                         break;
3512                 case OP_COMPARE:
3513                 case OP_ICOMPARE:
3514                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3515                         break;
3516                 case OP_COMPARE_IMM:
3517                 case OP_ICOMPARE_IMM:
3518                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3519                         g_assert (imm8 >= 0);
3520                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3521                         break;
3522                 case OP_BREAK:
3523                         /*
3524                          * gdb does not like encountering the hw breakpoint ins in the debugged code.
3525                          * So instead of emitting a trap, we emit a call a C function and place a
3526                          * breakpoint there.
3527                          */
3528                         //*(int*)code = 0xef9f0001;
3529                         //code += 4;
3530                         //ARM_DBRK (code);
3531                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3532                                                                  (gpointer)"mono_break");
3533                         code = emit_call_seq (cfg, code);
3534                         break;
3535                 case OP_RELAXED_NOP:
3536                         ARM_NOP (code);
3537                         break;
3538                 case OP_NOP:
3539                 case OP_DUMMY_USE:
3540                 case OP_DUMMY_STORE:
3541                 case OP_NOT_REACHED:
3542                 case OP_NOT_NULL:
3543                         break;
3544                 case OP_SEQ_POINT: {
3545                         int i;
3546                         MonoInst *info_var = cfg->arch.seq_point_info_var;
3547                         MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3548                         MonoInst *var;
3549                         int dreg = ARMREG_LR;
3550
3551                         /*
3552                          * For AOT, we use one got slot per method, which will point to a
3553                          * SeqPointInfo structure, containing all the information required
3554                          * by the code below.
3555                          */
3556                         if (cfg->compile_aot) {
3557                                 g_assert (info_var);
3558                                 g_assert (info_var->opcode == OP_REGOFFSET);
3559                                 g_assert (arm_is_imm12 (info_var->inst_offset));
3560                         }
3561
3562                         /*
3563                          * Read from the single stepping trigger page. This will cause a
3564                          * SIGSEGV when single stepping is enabled.
3565                          * We do this _before_ the breakpoint, so single stepping after
3566                          * a breakpoint is hit will step to the next IL offset.
3567                          */
3568                         g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3569
3570                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3571                                 if (cfg->compile_aot) {
3572                                         /* Load the trigger page addr from the variable initialized in the prolog */
3573                                         var = ss_trigger_page_var;
3574                                         g_assert (var);
3575                                         g_assert (var->opcode == OP_REGOFFSET);
3576                                         g_assert (arm_is_imm12 (var->inst_offset));
3577                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3578                                 } else {
3579                                         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3580                                         ARM_B (code, 0);
3581                                         *(int*)code = (int)ss_trigger_page;
3582                                         code += 4;
3583                                 }
3584                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3585                         }
3586
3587                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3588
3589                         if (cfg->compile_aot) {
3590                                 guint32 offset = code - cfg->native_code;
3591                                 guint32 val;
3592
3593                                 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3594                                 /* Add the offset */
3595                                 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3596                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3597                                 /*
3598                                  * Have to emit nops to keep the difference between the offset
3599                                  * stored in seq_points and breakpoint instruction constant,
3600                                  * mono_arch_get_ip_for_breakpoint () depends on this.
3601                                  */
3602                                 if (val & 0xFF00)
3603                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3604                                 else
3605                                         ARM_NOP (code);
3606                                 if (val & 0xFF0000)
3607                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3608                                 else
3609                                         ARM_NOP (code);
3610                                 g_assert (!(val & 0xFF000000));
3611                                 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3612                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3613
3614                                 /* What is faster, a branch or a load ? */
3615                                 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3616                                 /* The breakpoint instruction */
3617                                 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3618                         } else {
3619                                 /*
3620                                  * A placeholder for a possible breakpoint inserted by
3621                                  * mono_arch_set_breakpoint ().
3622                                  */
3623                                 for (i = 0; i < 4; ++i)
3624                                         ARM_NOP (code);
3625                         }
3626                         break;
3627                 }
3628                 case OP_ADDCC:
3629                 case OP_IADDCC:
3630                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3631                         break;
3632                 case OP_IADD:
3633                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3634                         break;
3635                 case OP_ADC:
3636                 case OP_IADC:
3637                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3638                         break;
3639                 case OP_ADDCC_IMM:
3640                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3641                         g_assert (imm8 >= 0);
3642                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3643                         break;
3644                 case OP_ADD_IMM:
3645                 case OP_IADD_IMM:
3646                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3647                         g_assert (imm8 >= 0);
3648                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3649                         break;
3650                 case OP_ADC_IMM:
3651                 case OP_IADC_IMM:
3652                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3653                         g_assert (imm8 >= 0);
3654                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3655                         break;
3656                 case OP_IADD_OVF:
3657                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3658                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3659                         break;
3660                 case OP_IADD_OVF_UN:
3661                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3662                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3663                         break;
3664                 case OP_ISUB_OVF:
3665                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3666                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3667                         break;
3668                 case OP_ISUB_OVF_UN:
3669                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3670                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3671                         break;
3672                 case OP_ADD_OVF_CARRY:
3673                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3674                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3675                         break;
3676                 case OP_ADD_OVF_UN_CARRY:
3677                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3678                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3679                         break;
3680                 case OP_SUB_OVF_CARRY:
3681                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3682                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3683                         break;
3684                 case OP_SUB_OVF_UN_CARRY:
3685                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3686                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3687                         break;
3688                 case OP_SUBCC:
3689                 case OP_ISUBCC:
3690                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3691                         break;
3692                 case OP_SUBCC_IMM:
3693                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3694                         g_assert (imm8 >= 0);
3695                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3696                         break;
3697                 case OP_ISUB:
3698                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3699                         break;
3700                 case OP_SBB:
3701                 case OP_ISBB:
3702                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3703                         break;
3704                 case OP_SUB_IMM:
3705                 case OP_ISUB_IMM:
3706                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3707                         g_assert (imm8 >= 0);
3708                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3709                         break;
3710                 case OP_SBB_IMM:
3711                 case OP_ISBB_IMM:
3712                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3713                         g_assert (imm8 >= 0);
3714                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3715                         break;
3716                 case OP_ARM_RSBS_IMM:
3717                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3718                         g_assert (imm8 >= 0);
3719                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3720                         break;
3721                 case OP_ARM_RSC_IMM:
3722                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3723                         g_assert (imm8 >= 0);
3724                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3725                         break;
3726                 case OP_IAND:
3727                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3728                         break;
3729                 case OP_AND_IMM:
3730                 case OP_IAND_IMM:
3731                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3732                         g_assert (imm8 >= 0);
3733                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3734                         break;
3735                 case OP_IDIV:
3736                 case OP_IDIV_UN:
3737                 case OP_DIV_IMM:
3738                 case OP_IREM:
3739                 case OP_IREM_UN:
3740                 case OP_REM_IMM:
3741                         /* crappy ARM arch doesn't have a DIV instruction */
3742                         g_assert_not_reached ();
3743                 case OP_IOR:
3744                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3745                         break;
3746                 case OP_OR_IMM:
3747                 case OP_IOR_IMM:
3748                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3749                         g_assert (imm8 >= 0);
3750                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3751                         break;
3752                 case OP_IXOR:
3753                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3754                         break;
3755                 case OP_XOR_IMM:
3756                 case OP_IXOR_IMM:
3757                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3758                         g_assert (imm8 >= 0);
3759                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3760                         break;
3761                 case OP_ISHL:
3762                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3763                         break;
3764                 case OP_SHL_IMM:
3765                 case OP_ISHL_IMM:
3766                         if (ins->inst_imm)
3767                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3768                         else if (ins->dreg != ins->sreg1)
3769                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3770                         break;
3771                 case OP_ISHR:
3772                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3773                         break;
3774                 case OP_SHR_IMM:
3775                 case OP_ISHR_IMM:
3776                         if (ins->inst_imm)
3777                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3778                         else if (ins->dreg != ins->sreg1)
3779                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3780                         break;
3781                 case OP_SHR_UN_IMM:
3782                 case OP_ISHR_UN_IMM:
3783                         if (ins->inst_imm)
3784                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3785                         else if (ins->dreg != ins->sreg1)
3786                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3787                         break;
3788                 case OP_ISHR_UN:
3789                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3790                         break;
3791                 case OP_INOT:
3792                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
3793                         break;
3794                 case OP_INEG:
3795                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
3796                         break;
3797                 case OP_IMUL:
3798                         if (ins->dreg == ins->sreg2)
3799                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3800                         else
3801                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
3802                         break;
3803                 case OP_MUL_IMM:
3804                         g_assert_not_reached ();
3805                         break;
3806                 case OP_IMUL_OVF:
3807                         /* FIXME: handle ovf/ sreg2 != dreg */
3808                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3809                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3810                         break;
3811                 case OP_IMUL_OVF_UN:
3812                         /* FIXME: handle ovf/ sreg2 != dreg */
3813                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3814                         /* FIXME: MUL doesn't set the C/O flags on ARM */
3815                         break;
3816                 case OP_ICONST:
3817                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
3818                         break;
3819                 case OP_AOTCONST:
3820                         /* Load the GOT offset */
3821                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3822                         ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
3823                         ARM_B (code, 0);
3824                         *(gpointer*)code = NULL;
3825                         code += 4;
3826                         /* Load the value from the GOT */
3827                         ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
3828                         break;
3829                 case OP_ICONV_TO_I4:
3830                 case OP_ICONV_TO_U4:
3831                 case OP_MOVE:
3832                         if (ins->dreg != ins->sreg1)
3833                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3834                         break;
3835                 case OP_SETLRET: {
3836                         int saved = ins->sreg2;
3837                         if (ins->sreg2 == ARM_LSW_REG) {
3838                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
3839                                 saved = ARMREG_LR;
3840                         }
3841                         if (ins->sreg1 != ARM_LSW_REG)
3842                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
3843                         if (saved != ARM_MSW_REG)
3844                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
3845                         break;
3846                 }
3847                 case OP_FMOVE:
3848 #ifdef ARM_FPU_FPA
3849                         ARM_MVFD (code, ins->dreg, ins->sreg1);
3850 #elif defined(ARM_FPU_VFP)
3851                         ARM_CPYD (code, ins->dreg, ins->sreg1);
3852 #endif
3853                         break;
3854                 case OP_FCONV_TO_R4:
3855 #ifdef ARM_FPU_FPA
3856                         ARM_MVFS (code, ins->dreg, ins->sreg1);
3857 #elif defined(ARM_FPU_VFP)
3858                         ARM_CVTD (code, ins->dreg, ins->sreg1);
3859                         ARM_CVTS (code, ins->dreg, ins->dreg);
3860 #endif
3861                         break;
3862                 case OP_JMP:
3863                         /*
3864                          * Keep in sync with mono_arch_emit_epilog
3865                          */
3866                         g_assert (!cfg->method->save_lmf);
3867
3868                         code = emit_load_volatile_arguments (cfg, code);
3869
3870                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
3871                         if (iphone_abi) {
3872                                 if (cfg->used_int_regs)
3873                                         ARM_POP (code, cfg->used_int_regs);
3874                                 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
3875                         } else {
3876                                 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
3877                         }
3878                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3879                         if (cfg->compile_aot) {
3880                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3881                                 ARM_B (code, 0);
3882                                 *(gpointer*)code = NULL;
3883                                 code += 4;
3884                                 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
3885                         } else {
3886                                 ARM_B (code, 0);
3887                         }
3888                         break;
3889                 case OP_CHECK_THIS:
3890                         /* ensure ins->sreg1 is not NULL */
3891                         ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
3892                         break;
3893                 case OP_ARGLIST: {
3894                         g_assert (cfg->sig_cookie < 128);
3895                         ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
3896                         ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
3897                         break;
3898                 }
3899                 case OP_FCALL:
3900                 case OP_LCALL:
3901                 case OP_VCALL:
3902                 case OP_VCALL2:
3903                 case OP_VOIDCALL:
3904                 case OP_CALL:
3905                         call = (MonoCallInst*)ins;
3906                         if (ins->flags & MONO_INST_HAS_METHOD)
3907                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
3908                         else
3909                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
3910                         code = emit_call_seq (cfg, code);
3911                         code = emit_move_return_value (cfg, ins, code);
3912                         break;
3913                 case OP_FCALL_REG:
3914                 case OP_LCALL_REG:
3915                 case OP_VCALL_REG:
3916                 case OP_VCALL2_REG:
3917                 case OP_VOIDCALL_REG:
3918                 case OP_CALL_REG:
3919                         code = emit_call_reg (code, ins->sreg1);
3920                         code = emit_move_return_value (cfg, ins, code);
3921                         break;
3922                 case OP_FCALL_MEMBASE:
3923                 case OP_LCALL_MEMBASE:
3924                 case OP_VCALL_MEMBASE:
3925                 case OP_VCALL2_MEMBASE:
3926                 case OP_VOIDCALL_MEMBASE:
3927                 case OP_CALL_MEMBASE:
3928                         g_assert (arm_is_imm12 (ins->inst_offset));
3929                         g_assert (ins->sreg1 != ARMREG_LR);
3930                         call = (MonoCallInst*)ins;
3931                         if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
3932                                 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
3933                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3934                                 /*
3935                                  * We can't embed the method in the code stream in PIC code, or
3936                                  * in gshared code.
3937                                  * Instead, we put it in V5 in code emitted by
3938                                  * mono_arch_emit_imt_argument (), and embed NULL here to
3939                                  * signal the IMT thunk that the value is in V5.
3940                                  */
3941                                 if (call->dynamic_imt_arg)
3942                                         *((gpointer*)code) = NULL;
3943                                 else
3944                                         *((gpointer*)code) = (gpointer)call->method;
3945                                 code += 4;
3946                         } else {
3947                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
3948                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
3949                         }
3950                         code = emit_move_return_value (cfg, ins, code);
3951                         break;
3952                 case OP_LOCALLOC: {
3953                         /* keep alignment */
3954                         int alloca_waste = cfg->param_area;
3955                         alloca_waste += 7;
3956                         alloca_waste &= ~7;
3957                         /* round the size to 8 bytes */
3958                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
3959                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
3960                         if (alloca_waste)
3961                                 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
3962                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
3963                         /* memzero the area: dreg holds the size, sp is the pointer */
3964                         if (ins->flags & MONO_INST_INIT) {
3965                                 guint8 *start_loop, *branch_to_cond;
3966                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
3967                                 branch_to_cond = code;
3968                                 ARM_B (code, 0);
3969                                 start_loop = code;
3970                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
3971                                 arm_patch (branch_to_cond, code);
3972                                 /* decrement by 4 and set flags */
3973                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
3974                                 ARM_B_COND (code, ARMCOND_GE, 0);
3975                                 arm_patch (code - 4, start_loop);
3976                         }
3977                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
3978                         break;
3979                 }
3980                 case OP_DYN_CALL: {
3981                         int i;
3982                         MonoInst *var = cfg->dyn_call_var;
3983
3984                         g_assert (var->opcode == OP_REGOFFSET);
3985                         g_assert (arm_is_imm12 (var->inst_offset));
3986
3987                         /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
3988                         ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
3989                         /* ip = ftn */
3990                         ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
3991
3992                         /* Save args buffer */
3993                         ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
3994
3995                         /* Set stack slots using R0 as scratch reg */
3996                         /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
3997                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
3998                                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
3999                                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4000                         }
4001
4002                         /* Set argument registers */
4003                         for (i = 0; i < PARAM_REGS; ++i)
4004                                 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4005
4006                         /* Make the call */
4007                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4008                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4009
4010                         /* Save result */
4011                         ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4012                         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4013                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4014                         break;
4015                 }
4016                 case OP_THROW: {
4017                         if (ins->sreg1 != ARMREG_R0)
4018                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4019                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4020                                              (gpointer)"mono_arch_throw_exception");
4021                         code = emit_call_seq (cfg, code);
4022                         break;
4023                 }
4024                 case OP_RETHROW: {
4025                         if (ins->sreg1 != ARMREG_R0)
4026                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4027                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4028                                              (gpointer)"mono_arch_rethrow_exception");
4029                         code = emit_call_seq (cfg, code);
4030                         break;
4031                 }
4032                 case OP_START_HANDLER: {
4033                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4034
4035                         if (arm_is_imm12 (spvar->inst_offset)) {
4036                                 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4037                         } else {
4038                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4039                                 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4040                         }
4041                         break;
4042                 }
4043                 case OP_ENDFILTER: {
4044                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4045
4046                         if (ins->sreg1 != ARMREG_R0)
4047                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4048                         if (arm_is_imm12 (spvar->inst_offset)) {
4049                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4050                         } else {
4051                                 g_assert (ARMREG_IP != spvar->inst_basereg);
4052                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4053                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4054                         }
4055                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4056                         break;
4057                 }
4058                 case OP_ENDFINALLY: {
4059                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4060
4061                         if (arm_is_imm12 (spvar->inst_offset)) {
4062                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4063                         } else {
4064                                 g_assert (ARMREG_IP != spvar->inst_basereg);
4065                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4066                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4067                         }
4068                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4069                         break;
4070                 }
4071                 case OP_CALL_HANDLER:
4072                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4073                         ARM_BL (code, 0);
4074                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4075                         break;
4076                 case OP_LABEL:
4077                         ins->inst_c0 = code - cfg->native_code;
4078                         break;
4079                 case OP_BR:
4080                         /*if (ins->inst_target_bb->native_offset) {
4081                                 ARM_B (code, 0);
4082                                 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4083                         } else*/ {
4084                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4085                                 ARM_B (code, 0);
4086                         }
4087                         break;
4088                 case OP_BR_REG:
4089                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4090                         break;
4091                 case OP_SWITCH:
4092                         /*
4093                          * In the normal case we have:
4094                          *      ldr pc, [pc, ins->sreg1 << 2]
4095                          *      nop
4096                          * If aot, we have:
4097                          *      ldr lr, [pc, ins->sreg1 << 2]
4098                          *      add pc, pc, lr
4099                          * After follows the data.
4100                          * FIXME: add aot support.
4101                          */
4102                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4103                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
4104                         if (offset + max_len > (cfg->code_size - 16)) {
4105                                 cfg->code_size += max_len;
4106                                 cfg->code_size *= 2;
4107                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4108                                 code = cfg->native_code + offset;
4109                         }
4110                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4111                         ARM_NOP (code);
4112                         code += 4 * GPOINTER_TO_INT (ins->klass);
4113                         break;
4114                 case OP_CEQ:
4115                 case OP_ICEQ:
4116                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4117                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4118                         break;
4119                 case OP_CLT:
4120                 case OP_ICLT:
4121                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4122                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4123                         break;
4124                 case OP_CLT_UN:
4125                 case OP_ICLT_UN:
4126                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4127                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4128                         break;
4129                 case OP_CGT:
4130                 case OP_ICGT:
4131                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4132                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4133                         break;
4134                 case OP_CGT_UN:
4135                 case OP_ICGT_UN:
4136                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4137                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4138                         break;
4139                 case OP_COND_EXC_EQ:
4140                 case OP_COND_EXC_NE_UN:
4141                 case OP_COND_EXC_LT:
4142                 case OP_COND_EXC_LT_UN:
4143                 case OP_COND_EXC_GT:
4144                 case OP_COND_EXC_GT_UN:
4145                 case OP_COND_EXC_GE:
4146                 case OP_COND_EXC_GE_UN:
4147                 case OP_COND_EXC_LE:
4148                 case OP_COND_EXC_LE_UN:
4149                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4150                         break;
4151                 case OP_COND_EXC_IEQ:
4152                 case OP_COND_EXC_INE_UN:
4153                 case OP_COND_EXC_ILT:
4154                 case OP_COND_EXC_ILT_UN:
4155                 case OP_COND_EXC_IGT:
4156                 case OP_COND_EXC_IGT_UN:
4157                 case OP_COND_EXC_IGE:
4158                 case OP_COND_EXC_IGE_UN:
4159                 case OP_COND_EXC_ILE:
4160                 case OP_COND_EXC_ILE_UN:
4161                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4162                         break;
4163                 case OP_COND_EXC_C:
4164                 case OP_COND_EXC_IC:
4165                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4166                         break;
4167                 case OP_COND_EXC_OV:
4168                 case OP_COND_EXC_IOV:
4169                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4170                         break;
4171                 case OP_COND_EXC_NC:
4172                 case OP_COND_EXC_INC:
4173                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4174                         break;
4175                 case OP_COND_EXC_NO:
4176                 case OP_COND_EXC_INO:
4177                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4178                         break;
4179                 case OP_IBEQ:
4180                 case OP_IBNE_UN:
4181                 case OP_IBLT:
4182                 case OP_IBLT_UN:
4183                 case OP_IBGT:
4184                 case OP_IBGT_UN:
4185                 case OP_IBGE:
4186                 case OP_IBGE_UN:
4187                 case OP_IBLE:
4188                 case OP_IBLE_UN:
4189                         EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4190                         break;
4191
4192                 /* floating point opcodes */
4193 #ifdef ARM_FPU_FPA
4194                 case OP_R8CONST:
4195                         if (cfg->compile_aot) {
4196                                 ARM_LDFD (code, ins->dreg, ARMREG_PC, 0);
4197                                 ARM_B (code, 1);
4198                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4199                                 code += 4;
4200                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4201                                 code += 4;
4202                         } else {
4203                                 /* FIXME: we can optimize the imm load by dealing with part of
4204                                  * the displacement in LDFD (aligning to 512).
4205                                  */
4206                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4207                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4208                         }
4209                         break;
4210                 case OP_R4CONST:
4211                         if (cfg->compile_aot) {
4212                                 ARM_LDFS (code, ins->dreg, ARMREG_PC, 0);
4213                                 ARM_B (code, 0);
4214                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4215                                 code += 4;
4216                         } else {
4217                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4218                                 ARM_LDFS (code, ins->dreg, ARMREG_LR, 0);
4219                         }
4220                         break;
4221                 case OP_STORER8_MEMBASE_REG:
4222                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4223                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4224                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4225                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4226                                 ARM_STFD (code, ins->sreg1, ARMREG_LR, 0);
4227                         } else {
4228                                 ARM_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4229                         }
4230                         break;
4231                 case OP_LOADR8_MEMBASE:
4232                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4233                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4234                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4235                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4236                                 ARM_LDFD (code, ins->dreg, ARMREG_LR, 0);
4237                         } else {
4238                                 ARM_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4239                         }
4240                         break;
4241                 case OP_STORER4_MEMBASE_REG:
4242                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4243                         ARM_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4244                         break;
4245                 case OP_LOADR4_MEMBASE:
4246                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4247                         ARM_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4248                         break;
4249                 case OP_ICONV_TO_R_UN: {
4250                         int tmpreg;
4251                         tmpreg = ins->dreg == 0? 1: 0;
4252                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4253                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4254                         ARM_B_COND (code, ARMCOND_GE, 8);
4255                         /* save the temp register */
4256                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4257                         ARM_STFD (code, tmpreg, ARMREG_SP, 0);
4258                         ARM_LDFD (code, tmpreg, ARMREG_PC, 12);
4259                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4260                         ARM_LDFD (code, tmpreg, ARMREG_SP, 0);
4261                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4262                         /* skip the constant pool */
4263                         ARM_B (code, 8);
4264                         code += 4;
4265                         *(int*)code = 0x41f00000;
4266                         code += 4;
4267                         *(int*)code = 0;
4268                         code += 4;
4269                         /* FIXME: adjust:
4270                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
4271                          * adfltd  fdest, fdest, ftemp
4272                          */
4273                         break;
4274                 }
4275                 case OP_ICONV_TO_R4:
4276                         ARM_FLTS (code, ins->dreg, ins->sreg1);
4277                         break;
4278                 case OP_ICONV_TO_R8:
4279                         ARM_FLTD (code, ins->dreg, ins->sreg1);
4280                         break;
4281
4282 #elif defined(ARM_FPU_VFP)
4283
4284                 case OP_R8CONST:
4285                         if (cfg->compile_aot) {
4286                                 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4287                                 ARM_B (code, 1);
4288                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4289                                 code += 4;
4290                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4291                                 code += 4;
4292                         } else {
4293                                 /* FIXME: we can optimize the imm load by dealing with part of
4294                                  * the displacement in LDFD (aligning to 512).
4295                                  */
4296                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4297                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4298                         }
4299                         break;
4300                 case OP_R4CONST:
4301                         if (cfg->compile_aot) {
4302                                 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4303                                 ARM_B (code, 0);
4304                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4305                                 code += 4;
4306                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4307                         } else {
4308                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4309                                 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4310                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4311                         }
4312                         break;
4313                 case OP_STORER8_MEMBASE_REG:
4314                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4315                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4316                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4317                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4318                                 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4319                         } else {
4320                                 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4321                         }
4322                         break;
4323                 case OP_LOADR8_MEMBASE:
4324                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4325                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4326                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4327                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4328                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4329                         } else {
4330                                 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4331                         }
4332                         break;
4333                 case OP_STORER4_MEMBASE_REG:
4334                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4335                         ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4336                         ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4337                         break;
4338                 case OP_LOADR4_MEMBASE:
4339                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4340                         ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4341                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4342                         break;
4343                 case OP_ICONV_TO_R_UN: {
4344                         g_assert_not_reached ();
4345                         break;
4346                 }
4347                 case OP_ICONV_TO_R4:
4348                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4349                         ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4350                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4351                         break;
4352                 case OP_ICONV_TO_R8:
4353                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4354                         ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4355                         break;
4356
4357                 case OP_SETFRET:
4358                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4359                                 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4360                                 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4361                         } else {
4362                                 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4363                         }
4364                         break;
4365
4366 #endif
4367
4368                 case OP_FCONV_TO_I1:
4369                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4370                         break;
4371                 case OP_FCONV_TO_U1:
4372                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4373                         break;
4374                 case OP_FCONV_TO_I2:
4375                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4376                         break;
4377                 case OP_FCONV_TO_U2:
4378                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4379                         break;
4380                 case OP_FCONV_TO_I4:
4381                 case OP_FCONV_TO_I:
4382                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4383                         break;
4384                 case OP_FCONV_TO_U4:
4385                 case OP_FCONV_TO_U:
4386                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4387                         break;
4388                 case OP_FCONV_TO_I8:
4389                 case OP_FCONV_TO_U8:
4390                         g_assert_not_reached ();
4391                         /* Implemented as helper calls */
4392                         break;
4393                 case OP_LCONV_TO_R_UN:
4394                         g_assert_not_reached ();
4395                         /* Implemented as helper calls */
4396                         break;
4397                 case OP_LCONV_TO_OVF_I4_2: {
4398                         guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4399                         /*
4400                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4401                          */
4402
4403                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4404                         high_bit_not_set = code;
4405                         ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4406
4407                         ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4408                         valid_negative = code;
4409                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4410                         invalid_negative = code;
4411                         ARM_B_COND (code, ARMCOND_AL, 0);
4412
4413                         arm_patch (high_bit_not_set, code);
4414
4415                         ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4416                         valid_positive = code;
4417                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4418
4419                         arm_patch (invalid_negative, code);
4420                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4421
4422                         arm_patch (valid_negative, code);
4423                         arm_patch (valid_positive, code);
4424
4425                         if (ins->dreg != ins->sreg1)
4426                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4427                         break;
4428                 }
4429 #ifdef ARM_FPU_FPA
4430                 case OP_FADD:
4431                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4432                         break;
4433                 case OP_FSUB:
4434                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4435                         break;
4436                 case OP_FMUL:
4437                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4438                         break;
4439                 case OP_FDIV:
4440                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4441                         break;
4442                 case OP_FNEG:
4443                         ARM_MNFD (code, ins->dreg, ins->sreg1);
4444                         break;
4445 #elif defined(ARM_FPU_VFP)
4446                 case OP_FADD:
4447                         ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4448                         break;
4449                 case OP_FSUB:
4450                         ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4451                         break;
4452                 case OP_FMUL:
4453                         ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4454                         break;
4455                 case OP_FDIV:
4456                         ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4457                         break;
4458                 case OP_FNEG:
4459                         ARM_NEGD (code, ins->dreg, ins->sreg1);
4460                         break;
4461 #endif
4462                 case OP_FREM:
4463                         /* emulated */
4464                         g_assert_not_reached ();
4465                         break;
4466                 case OP_FCOMPARE:
4467 #ifdef ARM_FPU_FPA
4468                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4469 #elif defined(ARM_FPU_VFP)
4470                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4471                         ARM_FMSTAT (code);
4472 #endif
4473                         break;
4474                 case OP_FCEQ:
4475 #ifdef ARM_FPU_FPA
4476                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4477 #elif defined(ARM_FPU_VFP)
4478                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4479                         ARM_FMSTAT (code);
4480 #endif
4481                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4482                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4483                         break;
4484                 case OP_FCLT:
4485 #ifdef ARM_FPU_FPA
4486                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4487 #elif defined(ARM_FPU_VFP)
4488                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4489                         ARM_FMSTAT (code);
4490 #endif
4491                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4492                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4493                         break;
4494                 case OP_FCLT_UN:
4495 #ifdef ARM_FPU_FPA
4496                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4497 #elif defined(ARM_FPU_VFP)
4498                         ARM_CMPD (code, ins->sreg1, ins->sreg2);
4499                         ARM_FMSTAT (code);
4500 #endif
4501                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4502                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4503                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4504                         break;
4505                 case OP_FCGT:
4506                         /* swapped */
4507 #ifdef ARM_FPU_FPA
4508                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4509 #elif defined(ARM_FPU_VFP)
4510                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4511                         ARM_FMSTAT (code);
4512 #endif
4513                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4514                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4515                         break;
4516                 case OP_FCGT_UN:
4517                         /* swapped */
4518 #ifdef ARM_FPU_FPA
4519                         ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4520 #elif defined(ARM_FPU_VFP)
4521                         ARM_CMPD (code, ins->sreg2, ins->sreg1);
4522                         ARM_FMSTAT (code);
4523 #endif
4524                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4525                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4526                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4527                         break;
4528                 /* ARM FPA flags table:
4529                  * N        Less than               ARMCOND_MI
4530                  * Z        Equal                   ARMCOND_EQ
4531                  * C        Greater Than or Equal   ARMCOND_CS
4532                  * V        Unordered               ARMCOND_VS
4533                  */
4534                 case OP_FBEQ:
4535                         EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4536                         break;
4537                 case OP_FBNE_UN:
4538                         EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4539                         break;
4540                 case OP_FBLT:
4541                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4542                         break;
4543                 case OP_FBLT_UN:
4544                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4545                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4546                         break;
4547                 case OP_FBGT:
4548                 case OP_FBGT_UN:
4549                 case OP_FBLE:
4550                 case OP_FBLE_UN:
4551                         g_assert_not_reached ();
4552                         break;
4553                 case OP_FBGE:
4554 #ifdef ARM_FPU_VFP
4555                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4556 #else
4557                         /* FPA requires EQ even thou the docs suggests that just CS is enough */
4558                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4559                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4560 #endif
4561                         break;
4562                 case OP_FBGE_UN:
4563                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4564                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4565                         break;
4566
4567                 case OP_CKFINITE: {
4568 #ifdef ARM_FPU_FPA
4569                         if (ins->dreg != ins->sreg1)
4570                                 ARM_MVFD (code, ins->dreg, ins->sreg1);
4571 #elif defined(ARM_FPU_VFP)
4572                         ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4573                         ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4574                         ARM_B (code, 1);
4575                         *(guint32*)code = 0xffffffff;
4576                         code += 4;
4577                         *(guint32*)code = 0x7fefffff;
4578                         code += 4;
4579                         ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4580                         ARM_FMSTAT (code);
4581                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4582                         ARM_CMPD (code, ins->sreg1, ins->sreg1);
4583                         ARM_FMSTAT (code);
4584                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4585
4586                         ARM_CPYD (code, ins->dreg, ins->sreg1);
4587 #endif
4588                         break;
4589                 }
4590                 default:
4591                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4592                         g_assert_not_reached ();
4593                 }
4594
4595                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4596                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4597                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4598                         g_assert_not_reached ();
4599                 }
4600
4601                 cpos += max_len;
4602
4603                 last_ins = ins;
4604                 last_offset = offset;
4605         }
4606
4607         cfg->code_len = code - cfg->native_code;
4608 }
4609
4610 #endif /* DISABLE_JIT */
4611
4612 #ifdef HAVE_AEABI_READ_TP
4613 void __aeabi_read_tp (void);
4614 #endif
4615
4616 void
4617 mono_arch_register_lowlevel_calls (void)
4618 {
4619         /* The signature doesn't matter */
4620         mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4621         mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4622
4623 #ifndef MONO_CROSS_COMPILE
4624 #ifdef HAVE_AEABI_READ_TP
4625         mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4626 #endif
4627 #endif
4628 }
4629
4630 #define patch_lis_ori(ip,val) do {\
4631                 guint16 *__lis_ori = (guint16*)(ip);    \
4632                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
4633                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
4634         } while (0)
4635
4636 void
4637 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4638 {
4639         MonoJumpInfo *patch_info;
4640         gboolean compile_aot = !run_cctors;
4641
4642         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4643                 unsigned char *ip = patch_info->ip.i + code;
4644                 const unsigned char *target;
4645
4646                 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4647                         gpointer *jt = (gpointer*)(ip + 8);
4648                         int i;
4649                         /* jt is the inlined jump table, 2 instructions after ip
4650                          * In the normal case we store the absolute addresses,
4651                          * otherwise the displacements.
4652                          */
4653                         for (i = 0; i < patch_info->data.table->table_size; i++)
4654                                 jt [i] = code + (int)patch_info->data.table->table [i];
4655                         continue;
4656                 }
4657                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4658
4659                 if (compile_aot) {
4660                         switch (patch_info->type) {
4661                         case MONO_PATCH_INFO_BB:
4662                         case MONO_PATCH_INFO_LABEL:
4663                                 break;
4664                         default:
4665                                 /* No need to patch these */
4666                                 continue;
4667                         }
4668                 }
4669
4670                 switch (patch_info->type) {
4671                 case MONO_PATCH_INFO_IP:
4672                         g_assert_not_reached ();
4673                         patch_lis_ori (ip, ip);
4674                         continue;
4675                 case MONO_PATCH_INFO_METHOD_REL:
4676                         g_assert_not_reached ();
4677                         *((gpointer *)(ip)) = code + patch_info->data.offset;
4678                         continue;
4679                 case MONO_PATCH_INFO_METHODCONST:
4680                 case MONO_PATCH_INFO_CLASS:
4681                 case MONO_PATCH_INFO_IMAGE:
4682                 case MONO_PATCH_INFO_FIELD:
4683                 case MONO_PATCH_INFO_VTABLE:
4684                 case MONO_PATCH_INFO_IID:
4685                 case MONO_PATCH_INFO_SFLDA:
4686                 case MONO_PATCH_INFO_LDSTR:
4687                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4688                 case MONO_PATCH_INFO_LDTOKEN:
4689                         g_assert_not_reached ();
4690                         /* from OP_AOTCONST : lis + ori */
4691                         patch_lis_ori (ip, target);
4692                         continue;
4693                 case MONO_PATCH_INFO_R4:
4694                 case MONO_PATCH_INFO_R8:
4695                         g_assert_not_reached ();
4696                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4697                         continue;
4698                 case MONO_PATCH_INFO_EXC_NAME:
4699                         g_assert_not_reached ();
4700                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4701                         continue;
4702                 case MONO_PATCH_INFO_NONE:
4703                 case MONO_PATCH_INFO_BB_OVF:
4704                 case MONO_PATCH_INFO_EXC_OVF:
4705                         /* everything is dealt with at epilog output time */
4706                         continue;
4707                 default:
4708                         break;
4709                 }
4710                 arm_patch_general (domain, ip, target, dyn_code_mp);
4711         }
4712 }
4713
4714 #ifndef DISABLE_JIT
4715
4716 /*
4717  * Stack frame layout:
4718  *
4719  *   ------------------- fp
4720  *      MonoLMF structure or saved registers
4721  *   -------------------
4722  *      locals
4723  *   -------------------
4724  *      spilled regs
4725  *   -------------------
4726  *      optional 8 bytes for tracing
4727  *   -------------------
4728  *      param area             size is cfg->param_area
4729  *   ------------------- sp
4730  */
4731 guint8 *
4732 mono_arch_emit_prolog (MonoCompile *cfg)
4733 {
4734         MonoMethod *method = cfg->method;
4735         MonoBasicBlock *bb;
4736         MonoMethodSignature *sig;
4737         MonoInst *inst;
4738         int alloc_size, pos, max_offset, i, rot_amount;
4739         guint8 *code;
4740         CallInfo *cinfo;
4741         int tracing = 0;
4742         int lmf_offset = 0;
4743         int prev_sp_offset, reg_offset;
4744
4745         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4746                 tracing = 1;
4747
4748         sig = mono_method_signature (method);
4749         cfg->code_size = 256 + sig->param_count * 64;
4750         code = cfg->native_code = g_malloc (cfg->code_size);
4751
4752         mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4753
4754         alloc_size = cfg->stack_offset;
4755         pos = 0;
4756         prev_sp_offset = 0;
4757
4758         if (!method->save_lmf) {
4759                 if (iphone_abi) {
4760                         /*
4761                          * The iphone uses R7 as the frame pointer, and it points at the saved
4762                          * r7+lr:
4763                          *         <lr>
4764                          * r7 ->   <r7>
4765                          *         <rest of frame>
4766                          * We can't use r7 as a frame pointer since it points into the middle of
4767                          * the frame, so we keep using our own frame pointer.
4768                          * FIXME: Optimize this.
4769                          */
4770                         g_assert (darwin);
4771                         ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4772                         ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
4773                         prev_sp_offset += 8; /* r7 and lr */
4774                         mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4775                         mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
4776
4777                         /* No need to push LR again */
4778                         if (cfg->used_int_regs)
4779                                 ARM_PUSH (code, cfg->used_int_regs);
4780                 } else {
4781                         ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
4782                         prev_sp_offset += 4;
4783                 }
4784                 for (i = 0; i < 16; ++i) {
4785                         if (cfg->used_int_regs & (1 << i))
4786                                 prev_sp_offset += 4;
4787                 }
4788                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4789                 reg_offset = 0;
4790                 for (i = 0; i < 16; ++i) {
4791                         if ((cfg->used_int_regs & (1 << i))) {
4792                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4793                                 reg_offset += 4;
4794                         }
4795                 }
4796                 if (iphone_abi) {
4797                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4798                 } else {
4799                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
4800                 }
4801         } else {
4802                 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
4803                 ARM_PUSH (code, 0x5ff0);
4804                 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
4805                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
4806                 reg_offset = 0;
4807                 for (i = 0; i < 16; ++i) {
4808                         if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
4809                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
4810                                 reg_offset += 4;
4811                         }
4812                 }
4813                 pos += sizeof (MonoLMF) - prev_sp_offset;
4814                 lmf_offset = pos;
4815         }
4816         alloc_size += pos;
4817         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
4818         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
4819                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
4820                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
4821         }
4822
4823         /* the stack used in the pushed regs */
4824         if (prev_sp_offset & 4)
4825                 alloc_size += 4;
4826         cfg->stack_usage = alloc_size;
4827         if (alloc_size) {
4828                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
4829                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4830                 } else {
4831                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
4832                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4833                 }
4834                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
4835         }
4836         if (cfg->frame_reg != ARMREG_SP) {
4837                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
4838                 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
4839         }
4840         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
4841         prev_sp_offset += alloc_size;
4842
4843         /* compute max_offset in order to use short forward jumps
4844          * we could skip do it on arm because the immediate displacement
4845          * for jumps is large enough, it may be useful later for constant pools
4846          */
4847         max_offset = 0;
4848         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4849                 MonoInst *ins = bb->code;
4850                 bb->max_offset = max_offset;
4851
4852                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4853                         max_offset += 6;
4854
4855                 MONO_BB_FOR_EACH_INS (bb, ins)
4856                         max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4857         }
4858
4859         /* store runtime generic context */
4860         if (cfg->rgctx_var) {
4861                 MonoInst *ins = cfg->rgctx_var;
4862
4863                 g_assert (ins->opcode == OP_REGOFFSET);
4864
4865                 if (arm_is_imm12 (ins->inst_offset)) {
4866                         ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4867                 } else {
4868                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4869                         ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
4870                 }
4871         }
4872
4873         /* load arguments allocated to register from the stack */
4874         pos = 0;
4875
4876         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
4877
4878         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
4879                 ArgInfo *ainfo = &cinfo->ret;
4880                 inst = cfg->vret_addr;
4881                 g_assert (arm_is_imm12 (inst->inst_offset));
4882                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4883         }
4884
4885         if (sig->call_convention == MONO_CALL_VARARG) {
4886                 ArgInfo *cookie = &cinfo->sig_cookie;
4887
4888                 /* Save the sig cookie address */
4889                 g_assert (cookie->storage == RegTypeBase);
4890
4891                 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
4892                 g_assert (arm_is_imm12 (cfg->sig_cookie));
4893                 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
4894                 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4895         }
4896
4897         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4898                 ArgInfo *ainfo = cinfo->args + i;
4899                 inst = cfg->args [pos];
4900
4901                 if (cfg->verbose_level > 2)
4902                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
4903                 if (inst->opcode == OP_REGVAR) {
4904                         if (ainfo->storage == RegTypeGeneral)
4905                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
4906                         else if (ainfo->storage == RegTypeFP) {
4907                                 g_assert_not_reached ();
4908                         } else if (ainfo->storage == RegTypeBase) {
4909                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4910                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4911                                 } else {
4912                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4913                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
4914                                 }
4915                         } else
4916                                 g_assert_not_reached ();
4917
4918                         if (cfg->verbose_level > 2)
4919                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4920                 } else {
4921                         /* the argument should be put on the stack: FIXME handle size != word  */
4922                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
4923                                 switch (ainfo->size) {
4924                                 case 1:
4925                                         if (arm_is_imm12 (inst->inst_offset))
4926                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4927                                         else {
4928                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4929                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4930                                         }
4931                                         break;
4932                                 case 2:
4933                                         if (arm_is_imm8 (inst->inst_offset)) {
4934                                                 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4935                                         } else {
4936                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4937                                                 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4938                                         }
4939                                         break;
4940                                 case 8:
4941                                         g_assert (arm_is_imm12 (inst->inst_offset));
4942                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4943                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
4944                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4945                                         break;
4946                                 default:
4947                                         if (arm_is_imm12 (inst->inst_offset)) {
4948                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4949                                         } else {
4950                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4951                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
4952                                         }
4953                                         break;
4954                                 }
4955                         } else if (ainfo->storage == RegTypeBaseGen) {
4956                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
4957                                 g_assert (arm_is_imm12 (inst->inst_offset));
4958                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4959                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
4960                                 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
4961                         } else if (ainfo->storage == RegTypeBase) {
4962                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
4963                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
4964                                 } else {
4965                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
4966                                         ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4967                                 }
4968
4969                                 switch (ainfo->size) {
4970                                 case 1:
4971                                         if (arm_is_imm8 (inst->inst_offset)) {
4972                                                 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4973                                         } else {
4974                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4975                                                 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4976                                         }
4977                                         break;
4978                                 case 2:
4979                                         if (arm_is_imm8 (inst->inst_offset)) {
4980                                                 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4981                                         } else {
4982                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4983                                                 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4984                                         }
4985                                         break;
4986                                 case 8:
4987                                         if (arm_is_imm12 (inst->inst_offset)) {
4988                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
4989                                         } else {
4990                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
4991                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
4992                                         }
4993                                         if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
4994                                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
4995                                         } else {
4996                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
4997                                                 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
4998                                         }
4999                                         if (arm_is_imm12 (inst->inst_offset + 4)) {
5000                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5001                                         } else {
5002                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5003                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5004                                         }
5005                                         break;
5006                                 default:
5007                                         if (arm_is_imm12 (inst->inst_offset)) {
5008                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5009                                         } else {
5010                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5011                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5012                                         }
5013                                         break;
5014                                 }
5015                         } else if (ainfo->storage == RegTypeFP) {
5016                                 g_assert_not_reached ();
5017                         } else if (ainfo->storage == RegTypeStructByVal) {
5018                                 int doffset = inst->inst_offset;
5019                                 int soffset = 0;
5020                                 int cur_reg;
5021                                 int size = 0;
5022                                 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5023                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5024                                         if (arm_is_imm12 (doffset)) {
5025                                                 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5026                                         } else {
5027                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5028                                                 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5029                                         }
5030                                         soffset += sizeof (gpointer);
5031                                         doffset += sizeof (gpointer);
5032                                 }
5033                                 if (ainfo->vtsize) {
5034                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5035                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5036                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5037                                 }
5038                         } else if (ainfo->storage == RegTypeStructByAddr) {
5039                                 g_assert_not_reached ();
5040                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5041                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5042                         } else
5043                                 g_assert_not_reached ();
5044                 }
5045                 pos++;
5046         }
5047
5048         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5049                 if (cfg->compile_aot)
5050                         /* AOT code is only used in the root domain */
5051                         code = mono_arm_emit_load_imm (code, ARMREG_R0, 0);
5052                 else
5053                         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->domain);
5054                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5055                              (gpointer)"mono_jit_thread_attach");
5056                 code = emit_call_seq (cfg, code);
5057         }
5058
5059         if (method->save_lmf)
5060                 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5061
5062         if (tracing)
5063                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5064
5065         if (cfg->arch.seq_point_info_var) {
5066                 MonoInst *ins = cfg->arch.seq_point_info_var;
5067
5068                 /* Initialize the variable from a GOT slot */
5069                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5070                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5071                 ARM_B (code, 0);
5072                 *(gpointer*)code = NULL;
5073                 code += 4;
5074                 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5075
5076                 g_assert (ins->opcode == OP_REGOFFSET);
5077
5078                 if (arm_is_imm12 (ins->inst_offset)) {
5079                         ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5080                 } else {
5081                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5082                         ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5083                 }
5084         }
5085
5086         /* Initialize ss_trigger_page_var */
5087         {
5088                 MonoInst *info_var = cfg->arch.seq_point_info_var;
5089                 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5090                 int dreg = ARMREG_LR;
5091
5092                 if (info_var) {
5093                         g_assert (info_var->opcode == OP_REGOFFSET);
5094                         g_assert (arm_is_imm12 (info_var->inst_offset));
5095
5096                         ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5097                         /* Load the trigger page addr */
5098                         ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5099                         ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5100                 }
5101         }
5102
5103         cfg->code_len = code - cfg->native_code;
5104         g_assert (cfg->code_len < cfg->code_size);
5105         g_free (cinfo);
5106
5107         return code;
5108 }
5109
5110 void
5111 mono_arch_emit_epilog (MonoCompile *cfg)
5112 {
5113         MonoMethod *method = cfg->method;
5114         int pos, i, rot_amount;
5115         int max_epilog_size = 16 + 20*4;
5116         guint8 *code;
5117         CallInfo *cinfo;
5118
5119         if (cfg->method->save_lmf)
5120                 max_epilog_size += 128;
5121
5122         if (mono_jit_trace_calls != NULL)
5123                 max_epilog_size += 50;
5124
5125         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5126                 max_epilog_size += 50;
5127
5128         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5129                 cfg->code_size *= 2;
5130                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5131                 mono_jit_stats.code_reallocs++;
5132         }
5133
5134         /*
5135          * Keep in sync with OP_JMP
5136          */
5137         code = cfg->native_code + cfg->code_len;
5138
5139         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5140                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5141         }
5142         pos = 0;
5143
5144         /* Load returned vtypes into registers if needed */
5145         cinfo = cfg->arch.cinfo;
5146         if (cinfo->ret.storage == RegTypeStructByVal) {
5147                 MonoInst *ins = cfg->ret;
5148
5149                 if (arm_is_imm12 (ins->inst_offset)) {
5150                         ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5151                 } else {
5152                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5153                         ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5154                 }
5155         }
5156
5157         if (method->save_lmf) {
5158                 int lmf_offset, reg, sp_adj, regmask;
5159                 /* all but r0-r3, sp and pc */
5160                 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5161                 lmf_offset = pos;
5162
5163                 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5164
5165                 /* This points to r4 inside MonoLMF->iregs */
5166                 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5167                 reg = ARMREG_R4;
5168                 regmask = 0x9ff0; /* restore lr to pc */
5169                 /* Skip caller saved registers not used by the method */
5170                 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5171                         regmask &= ~(1 << reg);
5172                         sp_adj += 4;
5173                         reg ++;
5174                 }
5175                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5176                 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5177                 /* restore iregs */
5178                 ARM_POP (code, regmask);
5179         } else {
5180                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5181                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5182                 } else {
5183                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5184                         ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5185                 }
5186
5187                 if (iphone_abi) {
5188                         /* Restore saved gregs */
5189                         if (cfg->used_int_regs)
5190                                 ARM_POP (code, cfg->used_int_regs);
5191                         /* Restore saved r7, restore LR to PC */
5192                         ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5193                 } else {
5194                         ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5195                 }
5196         }
5197
5198         cfg->code_len = code - cfg->native_code;
5199
5200         g_assert (cfg->code_len < cfg->code_size);
5201
5202 }
5203
5204 /* remove once throw_exception_by_name is eliminated */
5205 static int
5206 exception_id_by_name (const char *name)
5207 {
5208         if (strcmp (name, "IndexOutOfRangeException") == 0)
5209                 return MONO_EXC_INDEX_OUT_OF_RANGE;
5210         if (strcmp (name, "OverflowException") == 0)
5211                 return MONO_EXC_OVERFLOW;
5212         if (strcmp (name, "ArithmeticException") == 0)
5213                 return MONO_EXC_ARITHMETIC;
5214         if (strcmp (name, "DivideByZeroException") == 0)
5215                 return MONO_EXC_DIVIDE_BY_ZERO;
5216         if (strcmp (name, "InvalidCastException") == 0)
5217                 return MONO_EXC_INVALID_CAST;
5218         if (strcmp (name, "NullReferenceException") == 0)
5219                 return MONO_EXC_NULL_REF;
5220         if (strcmp (name, "ArrayTypeMismatchException") == 0)
5221                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5222         if (strcmp (name, "ArgumentException") == 0)
5223                 return MONO_EXC_ARGUMENT;
5224         g_error ("Unknown intrinsic exception %s\n", name);
5225         return -1;
5226 }
5227
5228 void
5229 mono_arch_emit_exceptions (MonoCompile *cfg)
5230 {
5231         MonoJumpInfo *patch_info;
5232         int i;
5233         guint8 *code;
5234         guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5235         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5236         int max_epilog_size = 50;
5237
5238         for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5239                 exc_throw_pos [i] = NULL;
5240                 exc_throw_found [i] = 0;
5241         }
5242
5243         /* count the number of exception infos */
5244
5245         /*
5246          * make sure we have enough space for exceptions
5247          */
5248         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5249                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5250                         i = exception_id_by_name (patch_info->data.target);
5251                         if (!exc_throw_found [i]) {
5252                                 max_epilog_size += 32;
5253                                 exc_throw_found [i] = TRUE;
5254                         }
5255                 }
5256         }
5257
5258         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5259                 cfg->code_size *= 2;
5260                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5261                 mono_jit_stats.code_reallocs++;
5262         }
5263
5264         code = cfg->native_code + cfg->code_len;
5265
5266         /* add code to raise exceptions */
5267         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5268                 switch (patch_info->type) {
5269                 case MONO_PATCH_INFO_EXC: {
5270                         MonoClass *exc_class;
5271                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
5272
5273                         i = exception_id_by_name (patch_info->data.target);
5274                         if (exc_throw_pos [i]) {
5275                                 arm_patch (ip, exc_throw_pos [i]);
5276                                 patch_info->type = MONO_PATCH_INFO_NONE;
5277                                 break;
5278                         } else {
5279                                 exc_throw_pos [i] = code;
5280                         }
5281                         arm_patch (ip, code);
5282
5283                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5284                         g_assert (exc_class);
5285
5286                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5287                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5288                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5289                         patch_info->data.name = "mono_arch_throw_corlib_exception";
5290                         patch_info->ip.i = code - cfg->native_code;
5291                         ARM_BL (code, 0);
5292                         *(guint32*)(gpointer)code = exc_class->type_token;
5293                         code += 4;
5294                         break;
5295                 }
5296                 default:
5297                         /* do nothing */
5298                         break;
5299                 }
5300         }
5301
5302         cfg->code_len = code - cfg->native_code;
5303
5304         g_assert (cfg->code_len < cfg->code_size);
5305
5306 }
5307
5308 #endif /* #ifndef DISABLE_JIT */
5309
5310 static gboolean tls_offset_inited = FALSE;
5311
5312 void
5313 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5314 {
5315         if (!tls_offset_inited) {
5316                 tls_offset_inited = TRUE;
5317
5318                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5319                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5320         }
5321 }
5322
5323 void
5324 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5325 {
5326 }
5327
5328 MonoInst*
5329 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5330 {
5331         /* FIXME: */
5332         return NULL;
5333 }
5334
5335 gboolean
5336 mono_arch_print_tree (MonoInst *tree, int arity)
5337 {
5338         return 0;
5339 }
5340
5341 MonoInst*
5342 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5343 {
5344         return mono_get_domain_intrinsic (cfg);
5345 }
5346
5347 guint32
5348 mono_arch_get_patch_offset (guint8 *code)
5349 {
5350         /* OP_AOTCONST */
5351         return 8;
5352 }
5353
5354 void
5355 mono_arch_flush_register_windows (void)
5356 {
5357 }
5358
5359 #ifdef MONO_ARCH_HAVE_IMT
5360
5361 #ifndef DISABLE_JIT
5362
5363 void
5364 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5365 {
5366         if (cfg->compile_aot) {
5367                 int method_reg = mono_alloc_ireg (cfg);
5368                 MonoInst *ins;
5369
5370                 call->dynamic_imt_arg = TRUE;
5371
5372                 if (imt_arg) {
5373                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5374                 } else {
5375                         MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5376                         ins->dreg = method_reg;
5377                         ins->inst_p0 = call->method;
5378                         ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5379                         MONO_ADD_INS (cfg->cbb, ins);
5380
5381                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5382                 }
5383         } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5384
5385                 /* Always pass in a register for simplicity */
5386                 call->dynamic_imt_arg = TRUE;
5387
5388                 cfg->uses_rgctx_reg = TRUE;
5389
5390                 if (imt_arg) {
5391                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5392                 } else {
5393                         MonoInst *ins;
5394                         int method_reg = mono_alloc_preg (cfg);
5395
5396                         MONO_INST_NEW (cfg, ins, OP_PCONST);
5397                         ins->inst_p0 = call->method;
5398                         ins->dreg = method_reg;
5399                         MONO_ADD_INS (cfg->cbb, ins);
5400
5401                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5402                 }
5403         }
5404 }
5405
5406 #endif /* DISABLE_JIT */
5407
5408 MonoMethod*
5409 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5410 {
5411         guint32 *code_ptr = (guint32*)code;
5412         code_ptr -= 2;
5413
5414         if (mono_use_llvm)
5415                 /* Passed in V5 */
5416                 return (MonoMethod*)regs [ARMREG_V5];
5417
5418         /* The IMT value is stored in the code stream right after the LDC instruction. */
5419         if (!IS_LDR_PC (code_ptr [0])) {
5420                 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5421                 g_assert (IS_LDR_PC (code_ptr [0]));
5422         }
5423         if (code_ptr [1] == 0)
5424                 /* This is AOTed code, the IMT method is in V5 */
5425                 return (MonoMethod*)regs [ARMREG_V5];
5426         else
5427                 return (MonoMethod*) code_ptr [1];
5428 }
5429
5430 MonoVTable*
5431 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5432 {
5433         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5434 }
5435
5436 #define ENABLE_WRONG_METHOD_CHECK 0
5437 #define BASE_SIZE (6 * 4)
5438 #define BSEARCH_ENTRY_SIZE (4 * 4)
5439 #define CMP_SIZE (3 * 4)
5440 #define BRANCH_SIZE (1 * 4)
5441 #define CALL_SIZE (2 * 4)
5442 #define WMC_SIZE (5 * 4)
5443 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5444
5445 static arminstr_t *
5446 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5447 {
5448         guint32 delta = DISTANCE (target, code);
5449         delta -= 8;
5450         g_assert (delta >= 0 && delta <= 0xFFF);
5451         *target = *target | delta;
5452         *code = value;
5453         return code + 1;
5454 }
5455
5456 gpointer
5457 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5458         gpointer fail_tramp)
5459 {
5460         int size, i, extra_space = 0;
5461         arminstr_t *code, *start, *vtable_target = NULL;
5462         gboolean large_offsets = FALSE;
5463         guint32 **constant_pool_starts;
5464
5465         size = BASE_SIZE;
5466         constant_pool_starts = g_new0 (guint32*, count);
5467
5468         for (i = 0; i < count; ++i) {
5469                 MonoIMTCheckItem *item = imt_entries [i];
5470                 if (item->is_equals) {
5471                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5472
5473                         if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5474                                 item->chunk_size += 32;
5475                                 large_offsets = TRUE;
5476                         }
5477
5478                         if (item->check_target_idx || fail_case) {
5479                                 if (!item->compare_done || fail_case)
5480                                         item->chunk_size += CMP_SIZE;
5481                                 item->chunk_size += BRANCH_SIZE;
5482                         } else {
5483 #if ENABLE_WRONG_METHOD_CHECK
5484                                 item->chunk_size += WMC_SIZE;
5485 #endif
5486                         }
5487                         if (fail_case) {
5488                                 item->chunk_size += 16;
5489                                 large_offsets = TRUE;
5490                         }
5491                         item->chunk_size += CALL_SIZE;
5492                 } else {
5493                         item->chunk_size += BSEARCH_ENTRY_SIZE;
5494                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5495                 }
5496                 size += item->chunk_size;
5497         }
5498
5499         if (large_offsets)
5500                 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5501
5502         if (fail_tramp)
5503                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5504         else
5505                 code = mono_domain_code_reserve (domain, size);
5506         start = code;
5507
5508 #if DEBUG_IMT
5509         printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5510         for (i = 0; i < count; ++i) {
5511                 MonoIMTCheckItem *item = imt_entries [i];
5512                 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5513         }
5514 #endif
5515
5516         if (large_offsets)
5517                 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5518         else
5519                 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5520         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5521         vtable_target = code;
5522         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5523
5524         if (mono_use_llvm) {
5525                 /* LLVM always passes the IMT method in R5 */
5526                 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5527         } else {
5528                 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5529                 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5530                 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5531         }
5532
5533         for (i = 0; i < count; ++i) {
5534                 MonoIMTCheckItem *item = imt_entries [i];
5535                 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5536                 gint32 vtable_offset;
5537
5538                 item->code_target = (guint8*)code;
5539
5540                 if (item->is_equals) {
5541                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5542
5543                         if (item->check_target_idx || fail_case) {
5544                                 if (!item->compare_done || fail_case) {
5545                                         imt_method = code;
5546                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5547                                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5548                                 }
5549                                 item->jmp_code = (guint8*)code;
5550                                 ARM_B_COND (code, ARMCOND_NE, 0);
5551                         } else {
5552                                 /*Enable the commented code to assert on wrong method*/
5553 #if ENABLE_WRONG_METHOD_CHECK
5554                                 imt_method = code;
5555                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5556                                 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5557                                 ARM_B_COND (code, ARMCOND_NE, 1);
5558
5559                                 ARM_DBRK (code);
5560 #endif
5561                         }
5562
5563                         if (item->has_target_code) {
5564                                 target_code_ins = code;
5565                                 /* Load target address */
5566                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5567                                 /* Save it to the fourth slot */
5568                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5569                                 /* Restore registers and branch */
5570                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5571
5572                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5573                         } else {
5574                                 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5575                                 if (!arm_is_imm12 (vtable_offset)) {
5576                                         /*
5577                                          * We need to branch to a computed address but we don't have
5578                                          * a free register to store it, since IP must contain the
5579                                          * vtable address. So we push the two values to the stack, and
5580                                          * load them both using LDM.
5581                                          */
5582                                         /* Compute target address */
5583                                         vtable_offset_ins = code;
5584                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5585                                         ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5586                                         /* Save it to the fourth slot */
5587                                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5588                                         /* Restore registers and branch */
5589                                         ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5590
5591                                         code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5592                                 } else {
5593                                         ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5594                                         if (large_offsets)
5595                                                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5596                                         ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5597                                 }
5598                         }
5599
5600                         if (fail_case) {
5601                                 arm_patch (item->jmp_code, (guchar*)code);
5602
5603                                 target_code_ins = code;
5604                                 /* Load target address */
5605                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5606                                 /* Save it to the fourth slot */
5607                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5608                                 /* Restore registers and branch */
5609                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5610
5611                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5612                                 item->jmp_code = NULL;
5613                         }
5614
5615                         if (imt_method)
5616                                 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5617
5618                         /*must emit after unconditional branch*/
5619                         if (vtable_target) {
5620                                 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5621                                 item->chunk_size += 4;
5622                                 vtable_target = NULL;
5623                         }
5624
5625                         /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5626                         constant_pool_starts [i] = code;
5627                         if (extra_space) {
5628                                 code += extra_space;
5629                                 extra_space = 0;
5630                         }
5631                 } else {
5632                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5633                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5634
5635                         item->jmp_code = (guint8*)code;
5636                         ARM_B_COND (code, ARMCOND_GE, 0);
5637                         ++extra_space;
5638                 }
5639         }
5640
5641         for (i = 0; i < count; ++i) {
5642                 MonoIMTCheckItem *item = imt_entries [i];
5643                 if (item->jmp_code) {
5644                         if (item->check_target_idx)
5645                                 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5646                 }
5647                 if (i > 0 && item->is_equals) {
5648                         int j;
5649                         arminstr_t *space_start = constant_pool_starts [i];
5650                         for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5651                                 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5652                         }
5653                 }
5654         }
5655
5656 #if DEBUG_IMT
5657         {
5658                 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5659                 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5660                 g_free (buff);
5661         }
5662 #endif
5663
5664         g_free (constant_pool_starts);
5665
5666         mono_arch_flush_icache ((guint8*)start, size);
5667         mono_stats.imt_thunks_size += code - start;
5668
5669         g_assert (DISTANCE (start, code) <= size);
5670         return start;
5671 }
5672
5673 #endif
5674
5675 gpointer
5676 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5677 {
5678         if (reg == ARMREG_SP)
5679                 return (gpointer)ctx->esp;
5680         else
5681                 return (gpointer)ctx->regs [reg];
5682 }
5683
5684 /*
5685  * mono_arch_get_trampolines:
5686  *
5687  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
5688  * for AOT.
5689  */
5690 GSList *
5691 mono_arch_get_trampolines (gboolean aot)
5692 {
5693         return mono_arm_get_exception_trampolines (aot);
5694 }
5695
5696 /*
5697  * mono_arch_set_breakpoint:
5698  *
5699  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5700  * The location should contain code emitted by OP_SEQ_POINT.
5701  */
5702 void
5703 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5704 {
5705         guint8 *code = ip;
5706         guint32 native_offset = ip - (guint8*)ji->code_start;
5707
5708         if (ji->from_aot) {
5709                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5710
5711                 g_assert (native_offset % 4 == 0);
5712                 g_assert (info->bp_addrs [native_offset / 4] == 0);
5713                 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5714         } else {
5715                 int dreg = ARMREG_LR;
5716
5717                 /* Read from another trigger page */
5718                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
5719                 ARM_B (code, 0);
5720                 *(int*)code = (int)bp_trigger_page;
5721                 code += 4;
5722                 ARM_LDR_IMM (code, dreg, dreg, 0);
5723
5724                 mono_arch_flush_icache (code - 16, 16);
5725
5726 #if 0
5727                 /* This is currently implemented by emitting an SWI instruction, which
5728                  * qemu/linux seems to convert to a SIGILL.
5729                  */
5730                 *(int*)code = (0xef << 24) | 8;
5731                 code += 4;
5732                 mono_arch_flush_icache (code - 4, 4);
5733 #endif
5734         }
5735 }
5736
5737 /*
5738  * mono_arch_clear_breakpoint:
5739  *
5740  *   Clear the breakpoint at IP.
5741  */
5742 void
5743 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5744 {
5745         guint8 *code = ip;
5746         int i;
5747
5748         if (ji->from_aot) {
5749                 guint32 native_offset = ip - (guint8*)ji->code_start;
5750                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5751
5752                 g_assert (native_offset % 4 == 0);
5753                 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
5754                 info->bp_addrs [native_offset / 4] = 0;
5755         } else {
5756                 for (i = 0; i < 4; ++i)
5757                         ARM_NOP (code);
5758
5759                 mono_arch_flush_icache (ip, code - ip);
5760         }
5761 }
5762
5763 /*
5764  * mono_arch_start_single_stepping:
5765  *
5766  *   Start single stepping.
5767  */
5768 void
5769 mono_arch_start_single_stepping (void)
5770 {
5771         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5772 }
5773
5774 /*
5775  * mono_arch_stop_single_stepping:
5776  *
5777  *   Stop single stepping.
5778  */
5779 void
5780 mono_arch_stop_single_stepping (void)
5781 {
5782         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5783 }
5784
5785 #if __APPLE__
5786 #define DBG_SIGNAL SIGBUS
5787 #else
5788 #define DBG_SIGNAL SIGSEGV
5789 #endif
5790
5791 /*
5792  * mono_arch_is_single_step_event:
5793  *
5794  *   Return whenever the machine state in SIGCTX corresponds to a single
5795  * step event.
5796  */
5797 gboolean
5798 mono_arch_is_single_step_event (void *info, void *sigctx)
5799 {
5800         siginfo_t *sinfo = info;
5801
5802         /* Sometimes the address is off by 4 */
5803         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
5804                 return TRUE;
5805         else
5806                 return FALSE;
5807 }
5808
5809 /*
5810  * mono_arch_is_breakpoint_event:
5811  *
5812  *   Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
5813  */
5814 gboolean
5815 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5816 {
5817         siginfo_t *sinfo = info;
5818
5819         if (sinfo->si_signo == DBG_SIGNAL) {
5820                 /* Sometimes the address is off by 4 */
5821                 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
5822                         return TRUE;
5823                 else
5824                         return FALSE;
5825         } else {
5826                 return FALSE;
5827         }
5828 }
5829
5830 guint8*
5831 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5832 {
5833         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5834
5835         if (ji->from_aot)
5836                 ip -= 6 * 4;
5837         else
5838                 ip -= 12;
5839
5840         return ip;
5841 }
5842
5843 guint8*
5844 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5845 {
5846         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5847
5848         ip += 4;
5849
5850         return ip;
5851 }
5852
5853 /*
5854  * mono_arch_skip_breakpoint:
5855  *
5856  *   See mini-amd64.c for docs.
5857  */
5858 void
5859 mono_arch_skip_breakpoint (MonoContext *ctx)
5860 {
5861         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5862 }
5863
5864 /*
5865  * mono_arch_skip_single_step:
5866  *
5867  *   See mini-amd64.c for docs.
5868  */
5869 void
5870 mono_arch_skip_single_step (MonoContext *ctx)
5871 {
5872         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
5873 }
5874
5875 /*
5876  * mono_arch_get_seq_point_info:
5877  *
5878  *   See mini-amd64.c for docs.
5879  */
5880 gpointer
5881 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5882 {
5883         SeqPointInfo *info;
5884         MonoJitInfo *ji;
5885
5886         // FIXME: Add a free function
5887
5888         mono_domain_lock (domain);
5889         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5890                                                                 code);
5891         mono_domain_unlock (domain);
5892
5893         if (!info) {
5894                 ji = mono_jit_info_table_find (domain, (char*)code);
5895                 g_assert (ji);
5896
5897                 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
5898
5899                 info->ss_trigger_page = ss_trigger_page;
5900                 info->bp_trigger_page = bp_trigger_page;
5901
5902                 mono_domain_lock (domain);
5903                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5904                                                          code, info);
5905                 mono_domain_unlock (domain);
5906         }
5907
5908         return info;
5909 }
5910
5911 /*
5912  * mono_arch_set_target:
5913  *
5914  *   Set the target architecture the JIT backend should generate code for, in the form
5915  * of a GNU target triplet. Only used in AOT mode.
5916  */
5917 void
5918 mono_arch_set_target (char *mtriple)
5919 {
5920         /* The GNU target triple format is not very well documented */
5921         if (strstr (mtriple, "armv7")) {
5922                 v6_supported = TRUE;
5923                 v7_supported = TRUE;
5924         }
5925         if (strstr (mtriple, "armv6")) {
5926                 v6_supported = TRUE;
5927         }
5928         if (strstr (mtriple, "darwin")) {
5929                 v5_supported = TRUE;
5930                 thumb_supported = TRUE;
5931                 darwin = TRUE;
5932                 iphone_abi = TRUE;
5933         }
5934         if (strstr (mtriple, "gnueabi"))
5935                 eabi_supported = TRUE;
5936 }
5937