mono/mini/mini-arm.c

   1 /*
   2  * mini-arm.c: ARM backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * (C) 2003 Ximian, Inc.
   9  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  10  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  11  */
  12 #include "mini.h"
  13 #include <string.h>
  14
  15 #include <mono/metadata/appdomain.h>
  16 #include <mono/metadata/debug-helpers.h>
  17 #include <mono/utils/mono-mmap.h>
  18
  19 #include "mini-arm.h"
  20 #include "cpu-arm.h"
  21 #include "trace.h"
  22 #include "ir-emit.h"
  23 #include "debugger-agent.h"
  24 #include "mini-gc.h"
  25 #include "mono/arch/arm/arm-fpa-codegen.h"
  26 #include "mono/arch/arm/arm-vfp-codegen.h"
  27
  28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
  29 #define HAVE_AEABI_READ_TP 1
  30 #endif
  31
  32 #ifdef ARM_FPU_VFP_HARD
  33 #define ARM_FPU_VFP 1
  34 #endif
  35
  36 #ifdef ARM_FPU_FPA
  37 #define IS_FPA 1
  38 #else
  39 #define IS_FPA 0
  40 #endif
  41
  42 #ifdef ARM_FPU_VFP
  43 #define IS_VFP 1
  44 #else
  45 #define IS_VFP 0
  46 #endif
  47
  48 #ifdef MONO_ARCH_SOFT_FLOAT
  49 #define IS_SOFT_FLOAT 1
  50 #else
  51 #define IS_SOFT_FLOAT 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 static gint lmf_tls_offset = -1;
  57 static gint lmf_addr_tls_offset = -1;
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 static int v5_supported = 0;
  65 static int v6_supported = 0;
  66 static int v7_supported = 0;
  67 static int thumb_supported = 0;
  68 /*
  69  * Whenever to use the ARM EABI
  70  */
  71 static int eabi_supported = 0;
  72
  73 /*
  74  * Whenever we are on arm/darwin aka the iphone.
  75  */
  76 static int darwin = 0;
  77 /*
  78  * Whenever to use the iphone ABI extensions:
  79  * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
  80  * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
  81  * This is required for debugging/profiling tools to work, but it has some overhead so it should
  82  * only be turned on in debug builds.
  83  */
  84 static int iphone_abi = 0;
  85
  86 /*
  87  * The FPU we are generating code for. This is NOT runtime configurable right now,
  88  * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
  89  */
  90 static MonoArmFPU arm_fpu;
  91
  92 static int i8_align;
  93
  94 static volatile int ss_trigger_var = 0;
  95
  96 static gpointer single_step_func_wrapper;
  97 static gpointer breakpoint_func_wrapper;
  98
  99 /*
 100  * The code generated for sequence points reads from this location, which is
 101  * made read-only when single stepping is enabled.
 102  */
 103 static gpointer ss_trigger_page;
 104
 105 /* Enabled breakpoints read from this trigger page */
 106 static gpointer bp_trigger_page;
 107
 108 /* Structure used by the sequence points in AOTed code */
 109 typedef struct {
 110         gpointer ss_trigger_page;
 111         gpointer bp_trigger_page;
 112         guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
 113 } SeqPointInfo;
 114
 115 /*
 116  * TODO:
 117  * floating point support: on ARM it is a mess, there are at least 3
 118  * different setups, each of which binary incompat with the other.
 119  * 1) FPA: old and ugly, but unfortunately what current distros use
 120  *    the double binary format has the two words swapped. 8 double registers.
 121  *    Implemented usually by kernel emulation.
 122  * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
 123  *    ugly swapped double format (I guess a softfloat-vfp exists, too, though).
 124  * 3) VFP: the new and actually sensible and useful FP support. Implemented
 125  *    in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
 126  *
 127  * The plan is to write the FPA support first. softfloat can be tested in a chroot.
 128  */
 129 int mono_exc_esp_offset = 0;
 130
 131 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
 132 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
 133 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
 134
 135 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
 136 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
 137 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
 138
 139 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
 140 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) |  (ARMREG_LR << 12) | ARMREG_PC)
 141 #define DEBUG_IMT 0
 142
 143 /* A variant of ARM_LDR_IMM which can handle large offsets */
 144 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
 145         if (arm_is_imm12 ((offset))) { \
 146                 ARM_LDR_IMM (code, (dreg), (basereg), (offset));        \
 147         } else {                                                                                                \
 148                 g_assert ((scratch_reg) != (basereg));                                     \
 149                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 150                 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 151         }                                                                                                                                       \
 152         } while (0)
 153
 154 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do {      \
 155         if (arm_is_imm12 ((offset))) { \
 156                 ARM_STR_IMM (code, (dreg), (basereg), (offset));        \
 157         } else {                                                                                                \
 158                 g_assert ((scratch_reg) != (basereg));                                     \
 159                 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset));  \
 160                 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg));               \
 161         }                                                                                                                                       \
 162         } while (0)
 163
 164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
 165
 166 const char*
 167 mono_arch_regname (int reg)
 168 {
 169         static const char * rnames[] = {
 170                 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
 171                 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
 172                 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
 173                 "arm_pc"
 174         };
 175         if (reg >= 0 && reg < 16)
 176                 return rnames [reg];
 177         return "unknown";
 178 }
 179
 180 const char*
 181 mono_arch_fregname (int reg)
 182 {
 183         static const char * rnames[] = {
 184                 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
 185                 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
 186                 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
 187                 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
 188                 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
 189                 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
 190                 "arm_f30", "arm_f31"
 191         };
 192         if (reg >= 0 && reg < 32)
 193                 return rnames [reg];
 194         return "unknown";
 195 }
 196
 197 #ifndef DISABLE_JIT
 198
 199 static guint8*
 200 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
 201 {
 202         int imm8, rot_amount;
 203         if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
 204                 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
 205                 return code;
 206         }
 207         g_assert (dreg != sreg);
 208         code = mono_arm_emit_load_imm (code, dreg, imm);
 209         ARM_ADD_REG_REG (code, dreg, dreg, sreg);
 210         return code;
 211 }
 212
 213 static guint8*
 214 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
 215 {
 216         /* we can use r0-r3, since this is called only for incoming args on the stack */
 217         if (size > sizeof (gpointer) * 4) {
 218                 guint8 *start_loop;
 219                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 220                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 221                 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
 222                 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
 223                 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
 224                 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
 225                 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
 226                 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
 227                 ARM_B_COND (code, ARMCOND_NE, 0);
 228                 arm_patch (code - 4, start_loop);
 229                 return code;
 230         }
 231         if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
 232                         arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
 233                 while (size >= 4) {
 234                         ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
 235                         ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
 236                         doffset += 4;
 237                         soffset += 4;
 238                         size -= 4;
 239                 }
 240         } else if (size) {
 241                 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
 242                 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
 243                 doffset = soffset = 0;
 244                 while (size >= 4) {
 245                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
 246                         ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
 247                         doffset += 4;
 248                         soffset += 4;
 249                         size -= 4;
 250                 }
 251         }
 252         g_assert (size == 0);
 253         return code;
 254 }
 255
 256 static guint8*
 257 emit_call_reg (guint8 *code, int reg)
 258 {
 259         if (v5_supported) {
 260                 ARM_BLX_REG (code, reg);
 261         } else {
 262                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
 263                 if (thumb_supported)
 264                         ARM_BX (code, reg);
 265                 else
 266                         ARM_MOV_REG_REG (code, ARMREG_PC, reg);
 267         }
 268         return code;
 269 }
 270
 271 static guint8*
 272 emit_call_seq (MonoCompile *cfg, guint8 *code)
 273 {
 274         if (cfg->method->dynamic) {
 275                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 276                 ARM_B (code, 0);
 277                 *(gpointer*)code = NULL;
 278                 code += 4;
 279                 code = emit_call_reg (code, ARMREG_IP);
 280         } else {
 281                 ARM_BL (code, 0);
 282         }
 283         return code;
 284 }
 285
 286 static guint8*
 287 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
 288 {
 289         switch (ins->opcode) {
 290         case OP_FCALL:
 291         case OP_FCALL_REG:
 292         case OP_FCALL_MEMBASE:
 293                 if (IS_FPA) {
 294                         if (ins->dreg != ARM_FPA_F0)
 295                                 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
 296                 } else if (IS_VFP) {
 297                         if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
 298                                 ARM_FMSR (code, ins->dreg, ARMREG_R0);
 299                                 ARM_CVTS (code, ins->dreg, ins->dreg);
 300                         } else {
 301                                 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
 302                         }
 303                 }
 304                 break;
 305         }
 306
 307         return code;
 308 }
 309
 310 /*
 311  * emit_save_lmf:
 312  *
 313  *   Emit code to push an LMF structure on the LMF stack.
 314  * On arm, this is intermixed with the initialization of other fields of the structure.
 315  */
 316 static guint8*
 317 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
 318 {
 319         gboolean get_lmf_fast = FALSE;
 320         int i;
 321
 322 #ifdef HAVE_AEABI_READ_TP
 323         gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
 324
 325         if (lmf_addr_tls_offset != -1) {
 326                 get_lmf_fast = TRUE;
 327
 328                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
 329                                                          (gpointer)"__aeabi_read_tp");
 330                 code = emit_call_seq (cfg, code);
 331
 332                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
 333                 get_lmf_fast = TRUE;
 334         }
 335 #endif
 336         if (!get_lmf_fast) {
 337                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
 338                                                                  (gpointer)"mono_get_lmf_addr");
 339                 code = emit_call_seq (cfg, code);
 340         }
 341         /* we build the MonoLMF structure on the stack - see mini-arm.h */
 342         /* lmf_offset is the offset from the previous stack pointer,
 343          * alloc_size is the total stack space allocated, so the offset
 344          * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
 345          * The pointer to the struct is put in r1 (new_lmf).
 346          * ip is used as scratch
 347          * The callee-saved registers are already in the MonoLMF structure
 348          */
 349         code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
 350         /* r0 is the result from mono_get_lmf_addr () */
 351         ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
 352         /* new_lmf->previous_lmf = *lmf_addr */
 353         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 354         ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 355         /* *(lmf_addr) = r1 */
 356         ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 357         /* Skip method (only needed for trampoline LMF frames) */
 358         ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
 359         ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
 360         /* save the current IP */
 361         ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
 362         ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
 363
 364         for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
 365                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
 366
 367         return code;
 368 }
 369
 370 /*
 371  * emit_save_lmf:
 372  *
 373  *   Emit code to pop an LMF structure from the LMF stack.
 374  */
 375 static guint8*
 376 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
 377 {
 378         int basereg, offset;
 379
 380         if (lmf_offset < 32) {
 381                 basereg = cfg->frame_reg;
 382                 offset = lmf_offset;
 383         } else {
 384                 basereg = ARMREG_R2;
 385                 offset = 0;
 386                 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
 387         }
 388
 389         /* ip = previous_lmf */
 390         ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 391         /* lr = lmf_addr */
 392         ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
 393         /* *(lmf_addr) = previous_lmf */
 394         ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
 395
 396         return code;
 397 }
 398
 399 #endif /* #ifndef DISABLE_JIT */
 400
 401 /*
 402  * mono_arch_get_argument_info:
 403  * @csig:  a method signature
 404  * @param_count: the number of parameters to consider
 405  * @arg_info: an array to store the result infos
 406  *
 407  * Gathers information on parameters such as size, alignment and
 408  * padding. arg_info should be large enought to hold param_count + 1 entries.
 409  *
 410  * Returns the size of the activation frame.
 411  */
 412 int
 413 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 414 {
 415         int k, frame_size = 0;
 416         guint32 size, align, pad;
 417         int offset = 8;
 418
 419         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
 420                 frame_size += sizeof (gpointer);
 421                 offset += 4;
 422         }
 423
 424         arg_info [0].offset = offset;
 425
 426         if (csig->hasthis) {
 427                 frame_size += sizeof (gpointer);
 428                 offset += 4;
 429         }
 430
 431         arg_info [0].size = frame_size;
 432
 433         for (k = 0; k < param_count; k++) {
 434                 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
 435
 436                 /* ignore alignment for now */
 437                 align = 1;
 438
 439                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 440                 arg_info [k].pad = pad;
 441                 frame_size += size;
 442                 arg_info [k + 1].pad = 0;
 443                 arg_info [k + 1].size = size;
 444                 offset += pad;
 445                 arg_info [k + 1].offset = offset;
 446                 offset += size;
 447         }
 448
 449         align = MONO_ARCH_FRAME_ALIGNMENT;
 450         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 451         arg_info [k].pad = pad;
 452
 453         return frame_size;
 454 }
 455
 456 #define MAX_ARCH_DELEGATE_PARAMS 3
 457
 458 static gpointer
 459 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
 460 {
 461         guint8 *code, *start;
 462
 463         if (has_target) {
 464                 start = code = mono_global_codeman_reserve (12);
 465
 466                 /* Replace the this argument with the target */
 467                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 468                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
 469                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 470
 471                 g_assert ((code - start) <= 12);
 472
 473                 mono_arch_flush_icache (start, 12);
 474         } else {
 475                 int size, i;
 476
 477                 size = 8 + param_count * 4;
 478                 start = code = mono_global_codeman_reserve (size);
 479
 480                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
 481                 /* slide down the arguments */
 482                 for (i = 0; i < param_count; ++i) {
 483                         ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
 484                 }
 485                 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
 486
 487                 g_assert ((code - start) <= size);
 488
 489                 mono_arch_flush_icache (start, size);
 490         }
 491
 492         if (code_size)
 493                 *code_size = code - start;
 494
 495         return start;
 496 }
 497
 498 /*
 499  * mono_arch_get_delegate_invoke_impls:
 500  *
 501  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
 502  * trampolines.
 503  */
 504 GSList*
 505 mono_arch_get_delegate_invoke_impls (void)
 506 {
 507         GSList *res = NULL;
 508         guint8 *code;
 509         guint32 code_len;
 510         int i;
 511
 512         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
 513         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
 514
 515         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
 516                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
 517                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
 518         }
 519
 520         return res;
 521 }
 522
 523 gpointer
 524 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
 525 {
 526         guint8 *code, *start;
 527
 528         /* FIXME: Support more cases */
 529         if (MONO_TYPE_ISSTRUCT (sig->ret))
 530                 return NULL;
 531
 532         if (has_target) {
 533                 static guint8* cached = NULL;
 534                 mono_mini_arch_lock ();
 535                 if (cached) {
 536                         mono_mini_arch_unlock ();
 537                         return cached;
 538                 }
 539
 540                 if (mono_aot_only)
 541                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
 542                 else
 543                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
 544                 cached = start;
 545                 mono_mini_arch_unlock ();
 546                 return cached;
 547         } else {
 548                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
 549                 int i;
 550
 551                 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
 552                         return NULL;
 553                 for (i = 0; i < sig->param_count; ++i)
 554                         if (!mono_is_regsize_var (sig->params [i]))
 555                                 return NULL;
 556
 557                 mono_mini_arch_lock ();
 558                 code = cache [sig->param_count];
 559                 if (code) {
 560                         mono_mini_arch_unlock ();
 561                         return code;
 562                 }
 563
 564                 if (mono_aot_only) {
 565                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
 566                         start = mono_aot_get_trampoline (name);
 567                         g_free (name);
 568                 } else {
 569                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
 570                 }
 571                 cache [sig->param_count] = start;
 572                 mono_mini_arch_unlock ();
 573                 return start;
 574         }
 575
 576         return NULL;
 577 }
 578
 579 gpointer
 580 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
 581 {
 582         return (gpointer)regs [ARMREG_R0];
 583 }
 584
 585 /*
 586  * Initialize the cpu to execute managed code.
 587  */
 588 void
 589 mono_arch_cpu_init (void)
 590 {
 591 #if defined(__ARM_EABI__)
 592         eabi_supported = TRUE;
 593 #endif
 594 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
 595                 i8_align = 4;
 596 #else
 597                 i8_align = __alignof__ (gint64);
 598 #endif
 599 }
 600
 601 static gpointer
 602 create_function_wrapper (gpointer function)
 603 {
 604         guint8 *start, *code;
 605
 606         start = code = mono_global_codeman_reserve (96);
 607
 608         /*
 609          * Construct the MonoContext structure on the stack.
 610          */
 611
 612         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
 613
 614         /* save ip, lr and pc into their correspodings ctx.regs slots. */
 615         ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
 616         ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
 617         ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
 618
 619         /* save r0..r10 and fp */
 620         ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
 621         ARM_STM (code, ARMREG_IP, 0x0fff);
 622
 623         /* now we can update fp. */
 624         ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
 625
 626         /* make ctx.esp hold the actual value of sp at the beginning of this method. */
 627         ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
 628         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
 629         ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
 630
 631         /* make ctx.eip hold the address of the call. */
 632         ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
 633         ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
 634
 635         /* r0 now points to the MonoContext */
 636         ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
 637
 638         /* call */
 639         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
 640         ARM_B (code, 0);
 641         *(gpointer*)code = function;
 642         code += 4;
 643         ARM_BLX_REG (code, ARMREG_IP);
 644
 645         /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
 646         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
 647         ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
 648         ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
 649
 650         /* make ip point to the regs array, then restore everything, including pc. */
 651         ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
 652         ARM_LDM (code, ARMREG_IP, 0xffff);
 653
 654         mono_arch_flush_icache (start, code - start);
 655
 656         return start;
 657 }
 658
 659 /*
 660  * Initialize architecture specific code.
 661  */
 662 void
 663 mono_arch_init (void)
 664 {
 665         InitializeCriticalSection (&mini_arch_mutex);
 666
 667         if (mini_get_debug_options ()->soft_breakpoints) {
 668                 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
 669                 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
 670         } else {
 671                 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 672                 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 673                 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 674         }
 675
 676         mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
 677         mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
 678         mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
 679
 680 #ifdef ARM_FPU_FPA
 681         arm_fpu = MONO_ARM_FPU_FPA;
 682 #elif defined(ARM_FPU_VFP_HARD)
 683         arm_fpu = MONO_ARM_FPU_VFP_HARD;
 684 #elif defined(ARM_FPU_VFP)
 685         arm_fpu = MONO_ARM_FPU_VFP;
 686 #else
 687         arm_fpu = MONO_ARM_FPU_NONE;
 688 #endif
 689 }
 690
 691 /*
 692  * Cleanup architecture specific code.
 693  */
 694 void
 695 mono_arch_cleanup (void)
 696 {
 697 }
 698
 699 /*
 700  * This function returns the optimizations supported on this cpu.
 701  */
 702 guint32
 703 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 704 {
 705         guint32 opts = 0;
 706         const char *cpu_arch = getenv ("MONO_CPU_ARCH");
 707         if (cpu_arch != NULL) {
 708                 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
 709                 if (strncmp (cpu_arch, "armv", 4) == 0) {
 710                         v5_supported = cpu_arch [4] >= '5';
 711                         v6_supported = cpu_arch [4] >= '6';
 712                         v7_supported = cpu_arch [4] >= '7';
 713                 }
 714         } else {
 715 #if __APPLE__
 716         thumb_supported = TRUE;
 717         v5_supported = TRUE;
 718         darwin = TRUE;
 719         iphone_abi = TRUE;
 720 #else
 721         char buf [512];
 722         char *line;
 723         FILE *file = fopen ("/proc/cpuinfo", "r");
 724         if (file) {
 725                 while ((line = fgets (buf, 512, file))) {
 726                         if (strncmp (line, "Processor", 9) == 0) {
 727                                 char *ver = strstr (line, "(v");
 728                                 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
 729                                         v5_supported = TRUE;
 730                                 if (ver && (ver [2] == '6' || ver [2] == '7'))
 731                                         v6_supported = TRUE;
 732                                 if (ver && (ver [2] == '7'))
 733                                         v7_supported = TRUE;
 734                                 continue;
 735                         }
 736                         if (strncmp (line, "Features", 8) == 0) {
 737                                 char *th = strstr (line, "thumb");
 738                                 if (th) {
 739                                         thumb_supported = TRUE;
 740                                         if (v5_supported)
 741                                                 break;
 742                                 }
 743                                 continue;
 744                         }
 745                 }
 746                 fclose (file);
 747                 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
 748         }
 749 #endif
 750         }
 751
 752         /* no arm-specific optimizations yet */
 753         *exclude_mask = 0;
 754         return opts;
 755 }
 756
 757 #ifndef DISABLE_JIT
 758
 759 static gboolean
 760 is_regsize_var (MonoType *t) {
 761         if (t->byref)
 762                 return TRUE;
 763         t = mini_type_get_underlying_type (NULL, t);
 764         switch (t->type) {
 765         case MONO_TYPE_I4:
 766         case MONO_TYPE_U4:
 767         case MONO_TYPE_I:
 768         case MONO_TYPE_U:
 769         case MONO_TYPE_PTR:
 770         case MONO_TYPE_FNPTR:
 771                 return TRUE;
 772         case MONO_TYPE_OBJECT:
 773         case MONO_TYPE_STRING:
 774         case MONO_TYPE_CLASS:
 775         case MONO_TYPE_SZARRAY:
 776         case MONO_TYPE_ARRAY:
 777                 return TRUE;
 778         case MONO_TYPE_GENERICINST:
 779                 if (!mono_type_generic_inst_is_valuetype (t))
 780                         return TRUE;
 781                 return FALSE;
 782         case MONO_TYPE_VALUETYPE:
 783                 return FALSE;
 784         }
 785         return FALSE;
 786 }
 787
 788 GList *
 789 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 790 {
 791         GList *vars = NULL;
 792         int i;
 793
 794         for (i = 0; i < cfg->num_varinfo; i++) {
 795                 MonoInst *ins = cfg->varinfo [i];
 796                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 797
 798                 /* unused vars */
 799                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 800                         continue;
 801
 802                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 803                         continue;
 804
 805                 /* we can only allocate 32 bit values */
 806                 if (is_regsize_var (ins->inst_vtype)) {
 807                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 808                         g_assert (i == vmv->idx);
 809                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 810                 }
 811         }
 812
 813         return vars;
 814 }
 815
 816 #define USE_EXTRA_TEMPS 0
 817
 818 GList *
 819 mono_arch_get_global_int_regs (MonoCompile *cfg)
 820 {
 821         GList *regs = NULL;
 822
 823         mono_arch_compute_omit_fp (cfg);
 824
 825         /*
 826          * FIXME: Interface calls might go through a static rgctx trampoline which
 827          * sets V5, but it doesn't save it, so we need to save it ourselves, and
 828          * avoid using it.
 829          */
 830         if (cfg->flags & MONO_CFG_HAS_CALLS)
 831                 cfg->uses_rgctx_reg = TRUE;
 832
 833         if (cfg->arch.omit_fp)
 834                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
 835         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
 836         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
 837         regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
 838         if (darwin)
 839                 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
 840                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
 841         else
 842                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
 843         if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
 844                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
 845                 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
 846         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
 847         /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
 848
 849         return regs;
 850 }
 851
 852 /*
 853  * mono_arch_regalloc_cost:
 854  *
 855  *  Return the cost, in number of memory references, of the action of
 856  * allocating the variable VMV into a register during global register
 857  * allocation.
 858  */
 859 guint32
 860 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 861 {
 862         /* FIXME: */
 863         return 2;
 864 }
 865
 866 #endif /* #ifndef DISABLE_JIT */
 867
 868 #ifndef __GNUC_PREREQ
 869 #define __GNUC_PREREQ(maj, min) (0)
 870 #endif
 871
 872 void
 873 mono_arch_flush_icache (guint8 *code, gint size)
 874 {
 875 #if __APPLE__
 876         sys_icache_invalidate (code, size);
 877 #elif __GNUC_PREREQ(4, 1)
 878         __clear_cache (code, code + size);
 879 #elif defined(PLATFORM_ANDROID)
 880         const int syscall = 0xf0002;
 881         __asm __volatile (
 882                 "mov     r0, %0\n"
 883                 "mov     r1, %1\n"
 884                 "mov     r7, %2\n"
 885                 "mov     r2, #0x0\n"
 886                 "svc     0x00000000\n"
 887                 :
 888                 :       "r" (code), "r" (code + size), "r" (syscall)
 889                 :       "r0", "r1", "r7", "r2"
 890                 );
 891 #else
 892         __asm __volatile ("mov r0, %0\n"
 893                         "mov r1, %1\n"
 894                         "mov r2, %2\n"
 895                         "swi 0x9f0002       @ sys_cacheflush"
 896                         : /* no outputs */
 897                         : "r" (code), "r" (code + size), "r" (0)
 898                         : "r0", "r1", "r3" );
 899 #endif
 900 }
 901
 902 typedef enum {
 903         RegTypeNone,
 904         RegTypeGeneral,
 905         RegTypeIRegPair,
 906         RegTypeBase,
 907         RegTypeBaseGen,
 908         RegTypeFP,
 909         RegTypeStructByVal,
 910         RegTypeStructByAddr
 911 } ArgStorage;
 912
 913 typedef struct {
 914         gint32  offset;
 915         guint16 vtsize; /* in param area */
 916         guint8  reg;
 917         ArgStorage  storage;
 918         gint32  struct_size;
 919         guint8  size    : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
 920 } ArgInfo;
 921
 922 typedef struct {
 923         int nargs;
 924         guint32 stack_usage;
 925         gboolean vtype_retaddr;
 926         /* The index of the vret arg in the argument list */
 927         int vret_arg_index;
 928         ArgInfo ret;
 929         ArgInfo sig_cookie;
 930         ArgInfo args [1];
 931 } CallInfo;
 932
 933 #define DEBUG(a)
 934
 935 #ifndef __GNUC__
 936 /*#define __alignof__(a) sizeof(a)*/
 937 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
 938 #endif
 939
 940 #define PARAM_REGS 4
 941
 942 static void inline
 943 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
 944 {
 945         if (simple) {
 946                 if (*gr > ARMREG_R3) {
 947                         ainfo->offset = *stack_size;
 948                         ainfo->reg = ARMREG_SP; /* in the caller */
 949                         ainfo->storage = RegTypeBase;
 950                         *stack_size += 4;
 951                 } else {
 952                         ainfo->storage = RegTypeGeneral;
 953                         ainfo->reg = *gr;
 954                 }
 955         } else {
 956                 gboolean split;
 957
 958                 if (eabi_supported)
 959                         split = i8_align == 4;
 960                 else
 961                         split = TRUE;
 962
 963                 if (*gr == ARMREG_R3 && split) {
 964                         /* first word in r3 and the second on the stack */
 965                         ainfo->offset = *stack_size;
 966                         ainfo->reg = ARMREG_SP; /* in the caller */
 967                         ainfo->storage = RegTypeBaseGen;
 968                         *stack_size += 4;
 969                 } else if (*gr >= ARMREG_R3) {
 970                         if (eabi_supported) {
 971                                 /* darwin aligns longs to 4 byte only */
 972                                 if (i8_align == 8) {
 973                                         *stack_size += 7;
 974                                         *stack_size &= ~7;
 975                                 }
 976                         }
 977                         ainfo->offset = *stack_size;
 978                         ainfo->reg = ARMREG_SP; /* in the caller */
 979                         ainfo->storage = RegTypeBase;
 980                         *stack_size += 8;
 981                 } else {
 982                         if (eabi_supported) {
 983                                 if (i8_align == 8 && ((*gr) & 1))
 984                                         (*gr) ++;
 985                         }
 986                         ainfo->storage = RegTypeIRegPair;
 987                         ainfo->reg = *gr;
 988                 }
 989                 (*gr) ++;
 990         }
 991         (*gr) ++;
 992 }
 993
 994 static CallInfo*
 995 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 996 {
 997         guint i, gr, pstart;
 998         int n = sig->hasthis + sig->param_count;
 999         MonoType *simpletype;
1000         guint32 stack_size = 0;
1001         CallInfo *cinfo;
1002         gboolean is_pinvoke = sig->pinvoke;
1003
1004         if (mp)
1005                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1006         else
1007                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1008
1009         cinfo->nargs = n;
1010         gr = ARMREG_R0;
1011
1012         /* FIXME: handle returning a struct */
1013         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1014                 guint32 align;
1015
1016                 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1017                         cinfo->ret.storage = RegTypeStructByVal;
1018                 } else {
1019                         cinfo->vtype_retaddr = TRUE;
1020                 }
1021         }
1022
1023         pstart = 0;
1024         n = 0;
1025         /*
1026          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1027          * the first argument, allowing 'this' to be always passed in the first arg reg.
1028          * Also do this if the first argument is a reference type, since virtual calls
1029          * are sometimes made using calli without sig->hasthis set, like in the delegate
1030          * invoke wrappers.
1031          */
1032         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1033                 if (sig->hasthis) {
1034                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1035                 } else {
1036                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1037                         pstart = 1;
1038                 }
1039                 n ++;
1040                 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1041                 cinfo->vret_arg_index = 1;
1042         } else {
1043                 /* this */
1044                 if (sig->hasthis) {
1045                         add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1046                         n ++;
1047                 }
1048
1049                 if (cinfo->vtype_retaddr)
1050                         add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1051         }
1052
1053         DEBUG(printf("params: %d\n", sig->param_count));
1054         for (i = pstart; i < sig->param_count; ++i) {
1055                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1056                         /* Prevent implicit arguments and sig_cookie from
1057                            being passed in registers */
1058                         gr = ARMREG_R3 + 1;
1059                         /* Emit the signature cookie just before the implicit arguments */
1060                         add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1061                 }
1062                 DEBUG(printf("param %d: ", i));
1063                 if (sig->params [i]->byref) {
1064                         DEBUG(printf("byref\n"));
1065                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1066                         n++;
1067                         continue;
1068                 }
1069                 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1070                 switch (simpletype->type) {
1071                 case MONO_TYPE_BOOLEAN:
1072                 case MONO_TYPE_I1:
1073                 case MONO_TYPE_U1:
1074                         cinfo->args [n].size = 1;
1075                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1076                         n++;
1077                         break;
1078                 case MONO_TYPE_CHAR:
1079                 case MONO_TYPE_I2:
1080                 case MONO_TYPE_U2:
1081                         cinfo->args [n].size = 2;
1082                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1083                         n++;
1084                         break;
1085                 case MONO_TYPE_I4:
1086                 case MONO_TYPE_U4:
1087                         cinfo->args [n].size = 4;
1088                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1089                         n++;
1090                         break;
1091                 case MONO_TYPE_I:
1092                 case MONO_TYPE_U:
1093                 case MONO_TYPE_PTR:
1094                 case MONO_TYPE_FNPTR:
1095                 case MONO_TYPE_CLASS:
1096                 case MONO_TYPE_OBJECT:
1097                 case MONO_TYPE_STRING:
1098                 case MONO_TYPE_SZARRAY:
1099                 case MONO_TYPE_ARRAY:
1100                 case MONO_TYPE_R4:
1101                         cinfo->args [n].size = sizeof (gpointer);
1102                         add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1103                         n++;
1104                         break;
1105                 case MONO_TYPE_GENERICINST:
1106                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1107                                 cinfo->args [n].size = sizeof (gpointer);
1108                                 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1109                                 n++;
1110                                 break;
1111                         }
1112                         /* Fall through */
1113                 case MONO_TYPE_TYPEDBYREF:
1114                 case MONO_TYPE_VALUETYPE: {
1115                         gint size;
1116                         int align_size;
1117                         int nwords;
1118                         guint32 align;
1119
1120                         if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1121                                 size = sizeof (MonoTypedRef);
1122                                 align = sizeof (gpointer);
1123                         } else {
1124                                 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1125                                 if (is_pinvoke)
1126                                         size = mono_class_native_size (klass, &align);
1127                                 else
1128                                         size = mono_class_value_size (klass, &align);
1129                         }
1130                         DEBUG(printf ("load %d bytes struct\n",
1131                                       mono_class_native_size (sig->params [i]->data.klass, NULL)));
1132                         align_size = size;
1133                         nwords = 0;
1134                         align_size += (sizeof (gpointer) - 1);
1135                         align_size &= ~(sizeof (gpointer) - 1);
1136                         nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1137                         cinfo->args [n].storage = RegTypeStructByVal;
1138                         cinfo->args [n].struct_size = size;
1139                         /* FIXME: align stack_size if needed */
1140                         if (eabi_supported) {
1141                                 if (align >= 8 && (gr & 1))
1142                                         gr ++;
1143                         }
1144                         if (gr > ARMREG_R3) {
1145                                 cinfo->args [n].size = 0;
1146                                 cinfo->args [n].vtsize = nwords;
1147                         } else {
1148                                 int rest = ARMREG_R3 - gr + 1;
1149                                 int n_in_regs = rest >= nwords? nwords: rest;
1150
1151                                 cinfo->args [n].size = n_in_regs;
1152                                 cinfo->args [n].vtsize = nwords - n_in_regs;
1153                                 cinfo->args [n].reg = gr;
1154                                 gr += n_in_regs;
1155                                 nwords -= n_in_regs;
1156                         }
1157                         cinfo->args [n].offset = stack_size;
1158                         /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1159                         stack_size += nwords * sizeof (gpointer);
1160                         n++;
1161                         break;
1162                 }
1163                 case MONO_TYPE_U8:
1164                 case MONO_TYPE_I8:
1165                 case MONO_TYPE_R8:
1166                         cinfo->args [n].size = 8;
1167                         add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1168                         n++;
1169                         break;
1170                 default:
1171                         g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1172                 }
1173         }
1174
1175         /* Handle the case where there are no implicit arguments */
1176         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1177                 /* Prevent implicit arguments and sig_cookie from
1178                    being passed in registers */
1179                 gr = ARMREG_R3 + 1;
1180                 /* Emit the signature cookie just before the implicit arguments */
1181                 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1182         }
1183
1184         {
1185                 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1186                 switch (simpletype->type) {
1187                 case MONO_TYPE_BOOLEAN:
1188                 case MONO_TYPE_I1:
1189                 case MONO_TYPE_U1:
1190                 case MONO_TYPE_I2:
1191                 case MONO_TYPE_U2:
1192                 case MONO_TYPE_CHAR:
1193                 case MONO_TYPE_I4:
1194                 case MONO_TYPE_U4:
1195                 case MONO_TYPE_I:
1196                 case MONO_TYPE_U:
1197                 case MONO_TYPE_PTR:
1198                 case MONO_TYPE_FNPTR:
1199                 case MONO_TYPE_CLASS:
1200                 case MONO_TYPE_OBJECT:
1201                 case MONO_TYPE_SZARRAY:
1202                 case MONO_TYPE_ARRAY:
1203                 case MONO_TYPE_STRING:
1204                         cinfo->ret.storage = RegTypeGeneral;
1205                         cinfo->ret.reg = ARMREG_R0;
1206                         break;
1207                 case MONO_TYPE_U8:
1208                 case MONO_TYPE_I8:
1209                         cinfo->ret.storage = RegTypeIRegPair;
1210                         cinfo->ret.reg = ARMREG_R0;
1211                         break;
1212                 case MONO_TYPE_R4:
1213                 case MONO_TYPE_R8:
1214                         cinfo->ret.storage = RegTypeFP;
1215                         cinfo->ret.reg = ARMREG_R0;
1216                         /* FIXME: cinfo->ret.reg = ???;
1217                         cinfo->ret.storage = RegTypeFP;*/
1218                         break;
1219                 case MONO_TYPE_GENERICINST:
1220                         if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1221                                 cinfo->ret.storage = RegTypeGeneral;
1222                                 cinfo->ret.reg = ARMREG_R0;
1223                                 break;
1224                         }
1225                         /* Fall through */
1226                 case MONO_TYPE_VALUETYPE:
1227                 case MONO_TYPE_TYPEDBYREF:
1228                         if (cinfo->ret.storage != RegTypeStructByVal)
1229                                 cinfo->ret.storage = RegTypeStructByAddr;
1230                         break;
1231                 case MONO_TYPE_VOID:
1232                         break;
1233                 default:
1234                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1235                 }
1236         }
1237
1238         /* align stack size to 8 */
1239         DEBUG (printf ("      stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1240         stack_size = (stack_size + 7) & ~7;
1241
1242         cinfo->stack_usage = stack_size;
1243         return cinfo;
1244 }
1245
1246 #ifndef DISABLE_JIT
1247
1248 G_GNUC_UNUSED static void
1249 break_count (void)
1250 {
1251 }
1252
1253 G_GNUC_UNUSED static gboolean
1254 debug_count (void)
1255 {
1256         static int count = 0;
1257         count ++;
1258
1259         if (!getenv ("COUNT"))
1260                 return TRUE;
1261
1262         if (count == atoi (getenv ("COUNT"))) {
1263                 break_count ();
1264         }
1265
1266         if (count > atoi (getenv ("COUNT"))) {
1267                 return FALSE;
1268         }
1269
1270         return TRUE;
1271 }
1272
1273 static gboolean
1274 debug_omit_fp (void)
1275 {
1276 #if 0
1277         return debug_count ();
1278 #else
1279         return TRUE;
1280 #endif
1281 }
1282
1283 /**
1284  * mono_arch_compute_omit_fp:
1285  *
1286  *   Determine whenever the frame pointer can be eliminated.
1287  */
1288 static void
1289 mono_arch_compute_omit_fp (MonoCompile *cfg)
1290 {
1291         MonoMethodSignature *sig;
1292         MonoMethodHeader *header;
1293         int i, locals_size;
1294         CallInfo *cinfo;
1295
1296         if (cfg->arch.omit_fp_computed)
1297                 return;
1298
1299         header = cfg->header;
1300
1301         sig = mono_method_signature (cfg->method);
1302
1303         if (!cfg->arch.cinfo)
1304                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1305         cinfo = cfg->arch.cinfo;
1306
1307         /*
1308          * FIXME: Remove some of the restrictions.
1309          */
1310         cfg->arch.omit_fp = TRUE;
1311         cfg->arch.omit_fp_computed = TRUE;
1312
1313         if (cfg->disable_omit_fp)
1314                 cfg->arch.omit_fp = FALSE;
1315         if (!debug_omit_fp ())
1316                 cfg->arch.omit_fp = FALSE;
1317         /*
1318         if (cfg->method->save_lmf)
1319                 cfg->arch.omit_fp = FALSE;
1320         */
1321         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1322                 cfg->arch.omit_fp = FALSE;
1323         if (header->num_clauses)
1324                 cfg->arch.omit_fp = FALSE;
1325         if (cfg->param_area)
1326                 cfg->arch.omit_fp = FALSE;
1327         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1328                 cfg->arch.omit_fp = FALSE;
1329         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1330                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1331                 cfg->arch.omit_fp = FALSE;
1332         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1333                 ArgInfo *ainfo = &cinfo->args [i];
1334
1335                 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1336                         /*
1337                          * The stack offset can only be determined when the frame
1338                          * size is known.
1339                          */
1340                         cfg->arch.omit_fp = FALSE;
1341                 }
1342         }
1343
1344         locals_size = 0;
1345         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1346                 MonoInst *ins = cfg->varinfo [i];
1347                 int ialign;
1348
1349                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1350         }
1351 }
1352
1353 /*
1354  * Set var information according to the calling convention. arm version.
1355  * The locals var stuff should most likely be split in another method.
1356  */
1357 void
1358 mono_arch_allocate_vars (MonoCompile *cfg)
1359 {
1360         MonoMethodSignature *sig;
1361         MonoMethodHeader *header;
1362         MonoInst *ins;
1363         int i, offset, size, align, curinst;
1364         CallInfo *cinfo;
1365         guint32 ualign;
1366
1367         sig = mono_method_signature (cfg->method);
1368
1369         if (!cfg->arch.cinfo)
1370                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1371         cinfo = cfg->arch.cinfo;
1372
1373         mono_arch_compute_omit_fp (cfg);
1374
1375         if (cfg->arch.omit_fp)
1376                 cfg->frame_reg = ARMREG_SP;
1377         else
1378                 cfg->frame_reg = ARMREG_FP;
1379
1380         cfg->flags |= MONO_CFG_HAS_SPILLUP;
1381
1382         /* allow room for the vararg method args: void* and long/double */
1383         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1384                 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1385
1386         header = cfg->header;
1387
1388         /* See mono_arch_get_global_int_regs () */
1389         if (cfg->flags & MONO_CFG_HAS_CALLS)
1390                 cfg->uses_rgctx_reg = TRUE;
1391
1392         if (cfg->frame_reg != ARMREG_SP)
1393                 cfg->used_int_regs |= 1 << cfg->frame_reg;
1394
1395         if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1396                 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1397                 cfg->used_int_regs |= (1 << ARMREG_V5);
1398
1399         offset = 0;
1400         curinst = 0;
1401         if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1402                 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1403                 case MONO_TYPE_VOID:
1404                         break;
1405                 default:
1406                         cfg->ret->opcode = OP_REGVAR;
1407                         cfg->ret->inst_c0 = ARMREG_R0;
1408                         break;
1409                 }
1410         }
1411         /* local vars are at a positive offset from the stack pointer */
1412         /*
1413          * also note that if the function uses alloca, we use FP
1414          * to point at the local variables.
1415          */
1416         offset = 0; /* linkage area */
1417         /* align the offset to 16 bytes: not sure this is needed here  */
1418         //offset += 8 - 1;
1419         //offset &= ~(8 - 1);
1420
1421         /* add parameter area size for called functions */
1422         offset += cfg->param_area;
1423         offset += 8 - 1;
1424         offset &= ~(8 - 1);
1425         if (cfg->flags & MONO_CFG_HAS_FPOUT)
1426                 offset += 8;
1427
1428         /* allow room to save the return value */
1429         if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1430                 offset += 8;
1431
1432         /* the MonoLMF structure is stored just below the stack pointer */
1433         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1434                 if (cinfo->ret.storage == RegTypeStructByVal) {
1435                         cfg->ret->opcode = OP_REGOFFSET;
1436                         cfg->ret->inst_basereg = cfg->frame_reg;
1437                         offset += sizeof (gpointer) - 1;
1438                         offset &= ~(sizeof (gpointer) - 1);
1439                         cfg->ret->inst_offset = - offset;
1440                 } else {
1441                         ins = cfg->vret_addr;
1442                         offset += sizeof(gpointer) - 1;
1443                         offset &= ~(sizeof(gpointer) - 1);
1444                         ins->inst_offset = offset;
1445                         ins->opcode = OP_REGOFFSET;
1446                         ins->inst_basereg = cfg->frame_reg;
1447                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1448                                 printf ("vret_addr =");
1449                                 mono_print_ins (cfg->vret_addr);
1450                         }
1451                 }
1452                 offset += sizeof(gpointer);
1453         }
1454
1455         /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1456         if (cfg->arch.seq_point_info_var) {
1457                 MonoInst *ins;
1458
1459                 ins = cfg->arch.seq_point_info_var;
1460
1461                 size = 4;
1462                 align = 4;
1463                 offset += align - 1;
1464                 offset &= ~(align - 1);
1465                 ins->opcode = OP_REGOFFSET;
1466                 ins->inst_basereg = cfg->frame_reg;
1467                 ins->inst_offset = offset;
1468                 offset += size;
1469
1470                 ins = cfg->arch.ss_trigger_page_var;
1471                 size = 4;
1472                 align = 4;
1473                 offset += align - 1;
1474                 offset &= ~(align - 1);
1475                 ins->opcode = OP_REGOFFSET;
1476                 ins->inst_basereg = cfg->frame_reg;
1477                 ins->inst_offset = offset;
1478                 offset += size;
1479         }
1480
1481         if (cfg->arch.seq_point_read_var) {
1482                 MonoInst *ins;
1483
1484                 ins = cfg->arch.seq_point_read_var;
1485
1486                 size = 4;
1487                 align = 4;
1488                 offset += align - 1;
1489                 offset &= ~(align - 1);
1490                 ins->opcode = OP_REGOFFSET;
1491                 ins->inst_basereg = cfg->frame_reg;
1492                 ins->inst_offset = offset;
1493                 offset += size;
1494
1495                 ins = cfg->arch.seq_point_ss_method_var;
1496                 size = 4;
1497                 align = 4;
1498                 offset += align - 1;
1499                 offset &= ~(align - 1);
1500                 ins->opcode = OP_REGOFFSET;
1501                 ins->inst_basereg = cfg->frame_reg;
1502                 ins->inst_offset = offset;
1503                 offset += size;
1504
1505                 ins = cfg->arch.seq_point_bp_method_var;
1506                 size = 4;
1507                 align = 4;
1508                 offset += align - 1;
1509                 offset &= ~(align - 1);
1510                 ins->opcode = OP_REGOFFSET;
1511                 ins->inst_basereg = cfg->frame_reg;
1512                 ins->inst_offset = offset;
1513                 offset += size;
1514         }
1515
1516         cfg->locals_min_stack_offset = offset;
1517
1518         curinst = cfg->locals_start;
1519         for (i = curinst; i < cfg->num_varinfo; ++i) {
1520                 ins = cfg->varinfo [i];
1521                 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1522                         continue;
1523
1524                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1525                 * pinvoke wrappers when they call functions returning structure */
1526                 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1527                         size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1528                         align = ualign;
1529                 }
1530                 else
1531                         size = mono_type_size (ins->inst_vtype, &align);
1532
1533                 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1534                  * since it loads/stores misaligned words, which don't do the right thing.
1535                  */
1536                 if (align < 4 && size >= 4)
1537                         align = 4;
1538                 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1539                         mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1540                 offset += align - 1;
1541                 offset &= ~(align - 1);
1542                 ins->opcode = OP_REGOFFSET;
1543                 ins->inst_offset = offset;
1544                 ins->inst_basereg = cfg->frame_reg;
1545                 offset += size;
1546                 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1547         }
1548
1549         cfg->locals_max_stack_offset = offset;
1550
1551         curinst = 0;
1552         if (sig->hasthis) {
1553                 ins = cfg->args [curinst];
1554                 if (ins->opcode != OP_REGVAR) {
1555                         ins->opcode = OP_REGOFFSET;
1556                         ins->inst_basereg = cfg->frame_reg;
1557                         offset += sizeof (gpointer) - 1;
1558                         offset &= ~(sizeof (gpointer) - 1);
1559                         ins->inst_offset = offset;
1560                         offset += sizeof (gpointer);
1561                 }
1562                 curinst++;
1563         }
1564
1565         if (sig->call_convention == MONO_CALL_VARARG) {
1566                 size = 4;
1567                 align = 4;
1568
1569                 /* Allocate a local slot to hold the sig cookie address */
1570                 offset += align - 1;
1571                 offset &= ~(align - 1);
1572                 cfg->sig_cookie = offset;
1573                 offset += size;
1574         }
1575
1576         for (i = 0; i < sig->param_count; ++i) {
1577                 ins = cfg->args [curinst];
1578
1579                 if (ins->opcode != OP_REGVAR) {
1580                         ins->opcode = OP_REGOFFSET;
1581                         ins->inst_basereg = cfg->frame_reg;
1582                         size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1583                         align = ualign;
1584                         /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1585                          * since it loads/stores misaligned words, which don't do the right thing.
1586                          */
1587                         if (align < 4 && size >= 4)
1588                                 align = 4;
1589                         /* The code in the prolog () stores words when storing vtypes received in a register */
1590                         if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1591                                 align = 4;
1592                         if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1593                                 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1594                         offset += align - 1;
1595                         offset &= ~(align - 1);
1596                         ins->inst_offset = offset;
1597                         offset += size;
1598                 }
1599                 curinst++;
1600         }
1601
1602         /* align the offset to 8 bytes */
1603         if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1604                 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1605         offset += 8 - 1;
1606         offset &= ~(8 - 1);
1607
1608         /* change sign? */
1609         cfg->stack_offset = offset;
1610 }
1611
1612 void
1613 mono_arch_create_vars (MonoCompile *cfg)
1614 {
1615         MonoMethodSignature *sig;
1616         CallInfo *cinfo;
1617
1618         sig = mono_method_signature (cfg->method);
1619
1620         if (!cfg->arch.cinfo)
1621                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1622         cinfo = cfg->arch.cinfo;
1623
1624         if (cinfo->ret.storage == RegTypeStructByVal)
1625                 cfg->ret_var_is_local = TRUE;
1626
1627         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1628                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1629                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1630                         printf ("vret_addr = ");
1631                         mono_print_ins (cfg->vret_addr);
1632                 }
1633         }
1634
1635         if (cfg->gen_seq_points) {
1636                 if (cfg->soft_breakpoints) {
1637                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1638                         ins->flags |= MONO_INST_VOLATILE;
1639                         cfg->arch.seq_point_read_var = ins;
1640
1641                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1642                         ins->flags |= MONO_INST_VOLATILE;
1643                         cfg->arch.seq_point_ss_method_var = ins;
1644
1645                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1646                         ins->flags |= MONO_INST_VOLATILE;
1647                         cfg->arch.seq_point_bp_method_var = ins;
1648
1649                         g_assert (!cfg->compile_aot);
1650                 } else if (cfg->compile_aot) {
1651                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1652                         ins->flags |= MONO_INST_VOLATILE;
1653                         cfg->arch.seq_point_info_var = ins;
1654
1655                         /* Allocate a separate variable for this to save 1 load per seq point */
1656                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1657                         ins->flags |= MONO_INST_VOLATILE;
1658                         cfg->arch.ss_trigger_page_var = ins;
1659                 }
1660         }
1661 }
1662
1663 static void
1664 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1665 {
1666         MonoMethodSignature *tmp_sig;
1667         int sig_reg;
1668
1669         if (call->tail_call)
1670                 NOT_IMPLEMENTED;
1671
1672         g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1673
1674         /*
1675          * mono_ArgIterator_Setup assumes the signature cookie is
1676          * passed first and all the arguments which were before it are
1677          * passed on the stack after the signature. So compensate by
1678          * passing a different signature.
1679          */
1680         tmp_sig = mono_metadata_signature_dup (call->signature);
1681         tmp_sig->param_count -= call->signature->sentinelpos;
1682         tmp_sig->sentinelpos = 0;
1683         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1684
1685         sig_reg = mono_alloc_ireg (cfg);
1686         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1687
1688         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1689 }
1690
1691 #ifdef ENABLE_LLVM
1692 LLVMCallInfo*
1693 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1694 {
1695         int i, n;
1696         CallInfo *cinfo;
1697         ArgInfo *ainfo;
1698         LLVMCallInfo *linfo;
1699
1700         n = sig->param_count + sig->hasthis;
1701
1702         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1703
1704         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1705
1706         /*
1707          * LLVM always uses the native ABI while we use our own ABI, the
1708          * only difference is the handling of vtypes:
1709          * - we only pass/receive them in registers in some cases, and only
1710          *   in 1 or 2 integer registers.
1711          */
1712         if (cinfo->vtype_retaddr) {
1713                 /* Vtype returned using a hidden argument */
1714                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1715                 linfo->vret_arg_index = cinfo->vret_arg_index;
1716         } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1717                 cfg->exception_message = g_strdup ("unknown ret conv");
1718                 cfg->disable_llvm = TRUE;
1719                 return linfo;
1720         }
1721
1722         for (i = 0; i < n; ++i) {
1723                 ainfo = cinfo->args + i;
1724
1725                 linfo->args [i].storage = LLVMArgNone;
1726
1727                 switch (ainfo->storage) {
1728                 case RegTypeGeneral:
1729                 case RegTypeIRegPair:
1730                 case RegTypeBase:
1731                         linfo->args [i].storage = LLVMArgInIReg;
1732                         break;
1733                 case RegTypeStructByVal:
1734                         // FIXME: Passing entirely on the stack or split reg/stack
1735                         if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1736                                 linfo->args [i].storage = LLVMArgVtypeInReg;
1737                                 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1738                                 if (ainfo->size == 2)
1739                                         linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1740                                 else
1741                                         linfo->args [i].pair_storage [1] = LLVMArgNone;
1742                         } else {
1743                                 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1744                                 cfg->disable_llvm = TRUE;
1745                         }
1746                         break;
1747                 default:
1748                         cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1749                         cfg->disable_llvm = TRUE;
1750                         break;
1751                 }
1752         }
1753
1754         return linfo;
1755 }
1756 #endif
1757
1758 void
1759 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1760 {
1761         MonoInst *in, *ins;
1762         MonoMethodSignature *sig;
1763         int i, n;
1764         CallInfo *cinfo;
1765
1766         sig = call->signature;
1767         n = sig->param_count + sig->hasthis;
1768
1769         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1770
1771         for (i = 0; i < n; ++i) {
1772                 ArgInfo *ainfo = cinfo->args + i;
1773                 MonoType *t;
1774
1775                 if (i >= sig->hasthis)
1776                         t = sig->params [i - sig->hasthis];
1777                 else
1778                         t = &mono_defaults.int_class->byval_arg;
1779                 t = mini_type_get_underlying_type (NULL, t);
1780
1781                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1782                         /* Emit the signature cookie just before the implicit arguments */
1783                         emit_sig_cookie (cfg, call, cinfo);
1784                 }
1785
1786                 in = call->args [i];
1787
1788                 switch (ainfo->storage) {
1789                 case RegTypeGeneral:
1790                 case RegTypeIRegPair:
1791                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1792                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1793                                 ins->dreg = mono_alloc_ireg (cfg);
1794                                 ins->sreg1 = in->dreg + 1;
1795                                 MONO_ADD_INS (cfg->cbb, ins);
1796                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1797
1798                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1799                                 ins->dreg = mono_alloc_ireg (cfg);
1800                                 ins->sreg1 = in->dreg + 2;
1801                                 MONO_ADD_INS (cfg->cbb, ins);
1802                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1803                         } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1804                                 if (ainfo->size == 4) {
1805                                         if (IS_SOFT_FLOAT) {
1806                                                 /* mono_emit_call_args () have already done the r8->r4 conversion */
1807                                                 /* The converted value is in an int vreg */
1808                                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1809                                                 ins->dreg = mono_alloc_ireg (cfg);
1810                                                 ins->sreg1 = in->dreg;
1811                                                 MONO_ADD_INS (cfg->cbb, ins);
1812                                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1813                                         } else {
1814                                                 int creg;
1815
1816                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1817                                                 creg = mono_alloc_ireg (cfg);
1818                                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1819                                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1820                                         }
1821                                 } else {
1822                                         if (IS_SOFT_FLOAT) {
1823                                                 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1824                                                 ins->dreg = mono_alloc_ireg (cfg);
1825                                                 ins->sreg1 = in->dreg;
1826                                                 MONO_ADD_INS (cfg->cbb, ins);
1827                                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1828
1829                                                 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1830                                                 ins->dreg = mono_alloc_ireg (cfg);
1831                                                 ins->sreg1 = in->dreg;
1832                                                 MONO_ADD_INS (cfg->cbb, ins);
1833                                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1834                                         } else {
1835                                                 int creg;
1836
1837                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1838                                                 creg = mono_alloc_ireg (cfg);
1839                                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1840                                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1841                                                 creg = mono_alloc_ireg (cfg);
1842                                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1843                                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1844                                         }
1845                                 }
1846                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1847                         } else {
1848                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1849                                 ins->dreg = mono_alloc_ireg (cfg);
1850                                 ins->sreg1 = in->dreg;
1851                                 MONO_ADD_INS (cfg->cbb, ins);
1852
1853                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1854                         }
1855                         break;
1856                 case RegTypeStructByAddr:
1857                         NOT_IMPLEMENTED;
1858 #if 0
1859                         /* FIXME: where si the data allocated? */
1860                         arg->backend.reg3 = ainfo->reg;
1861                         call->used_iregs |= 1 << ainfo->reg;
1862                         g_assert_not_reached ();
1863 #endif
1864                         break;
1865                 case RegTypeStructByVal:
1866                         MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1867                         ins->opcode = OP_OUTARG_VT;
1868                         ins->sreg1 = in->dreg;
1869                         ins->klass = in->klass;
1870                         ins->inst_p0 = call;
1871                         ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1872                         memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1873                         mono_call_inst_add_outarg_vt (cfg, call, ins);
1874                         MONO_ADD_INS (cfg->cbb, ins);
1875                         break;
1876                 case RegTypeBase:
1877                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1878                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1879                         } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1880                                 if (t->type == MONO_TYPE_R8) {
1881                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1882                                 } else {
1883                                         if (IS_SOFT_FLOAT)
1884                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1885                                         else
1886                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1887                                 }
1888                         } else {
1889                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1890                         }
1891                         break;
1892                 case RegTypeBaseGen:
1893                         if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1894                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1895                                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1896                                 ins->dreg = mono_alloc_ireg (cfg);
1897                                 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1898                                 MONO_ADD_INS (cfg->cbb, ins);
1899                                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1900                         } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1901                                 int creg;
1902
1903                                 /* This should work for soft-float as well */
1904
1905                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1906                                 creg = mono_alloc_ireg (cfg);
1907                                 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1908                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1909                                 creg = mono_alloc_ireg (cfg);
1910                                 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1911                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1912                                 cfg->flags |= MONO_CFG_HAS_FPOUT;
1913                         } else {
1914                                 g_assert_not_reached ();
1915                         }
1916                         break;
1917                 case RegTypeFP: {
1918                         /* FIXME: */
1919                         NOT_IMPLEMENTED;
1920 #if 0
1921                         arg->backend.reg3 = ainfo->reg;
1922                         /* FP args are passed in int regs */
1923                         call->used_iregs |= 1 << ainfo->reg;
1924                         if (ainfo->size == 8) {
1925                                 arg->opcode = OP_OUTARG_R8;
1926                                 call->used_iregs |= 1 << (ainfo->reg + 1);
1927                         } else {
1928                                 arg->opcode = OP_OUTARG_R4;
1929                         }
1930 #endif
1931                         cfg->flags |= MONO_CFG_HAS_FPOUT;
1932                         break;
1933                 }
1934                 default:
1935                         g_assert_not_reached ();
1936                 }
1937         }
1938
1939         /* Handle the case where there are no implicit arguments */
1940         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1941                 emit_sig_cookie (cfg, call, cinfo);
1942
1943         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1944                 MonoInst *vtarg;
1945
1946                 if (cinfo->ret.storage == RegTypeStructByVal) {
1947                         /* The JIT will transform this into a normal call */
1948                         call->vret_in_reg = TRUE;
1949                 } else {
1950                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1951                         vtarg->sreg1 = call->vret_var->dreg;
1952                         vtarg->dreg = mono_alloc_preg (cfg);
1953                         MONO_ADD_INS (cfg->cbb, vtarg);
1954
1955                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1956                 }
1957         }
1958
1959         call->stack_usage = cinfo->stack_usage;
1960
1961         g_free (cinfo);
1962 }
1963
1964 void
1965 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1966 {
1967         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1968         ArgInfo *ainfo = ins->inst_p1;
1969         int ovf_size = ainfo->vtsize;
1970         int doffset = ainfo->offset;
1971         int struct_size = ainfo->struct_size;
1972         int i, soffset, dreg, tmpreg;
1973
1974         soffset = 0;
1975         for (i = 0; i < ainfo->size; ++i) {
1976                 dreg = mono_alloc_ireg (cfg);
1977                 switch (struct_size) {
1978                 case 1:
1979                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1980                         break;
1981                 case 2:
1982                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1983                         break;
1984                 case 3:
1985                         tmpreg = mono_alloc_ireg (cfg);
1986                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1987                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1988                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1989                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1990                         MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1991                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1992                         MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1993                         break;
1994                 default:
1995                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1996                         break;
1997                 }
1998                 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1999                 soffset += sizeof (gpointer);
2000                 struct_size -= sizeof (gpointer);
2001         }
2002         //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2003         if (ovf_size != 0)
2004                 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2005 }
2006
2007 void
2008 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2009 {
2010         MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2011
2012         if (!ret->byref) {
2013                 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2014                         MonoInst *ins;
2015
2016                         if (COMPILE_LLVM (cfg)) {
2017                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2018                         } else {
2019                                 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2020                                 ins->sreg1 = val->dreg + 1;
2021                                 ins->sreg2 = val->dreg + 2;
2022                                 MONO_ADD_INS (cfg->cbb, ins);
2023                         }
2024                         return;
2025                 }
2026                 switch (arm_fpu) {
2027                 case MONO_ARM_FPU_NONE:
2028                         if (ret->type == MONO_TYPE_R8) {
2029                                 MonoInst *ins;
2030
2031                                 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2032                                 ins->dreg = cfg->ret->dreg;
2033                                 ins->sreg1 = val->dreg;
2034                                 MONO_ADD_INS (cfg->cbb, ins);
2035                                 return;
2036                         }
2037                         if (ret->type == MONO_TYPE_R4) {
2038                                 /* Already converted to an int in method_to_ir () */
2039                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2040                                 return;
2041                         }
2042                         break;
2043                 case MONO_ARM_FPU_VFP:
2044                         if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2045                                 MonoInst *ins;
2046
2047                                 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2048                                 ins->dreg = cfg->ret->dreg;
2049                                 ins->sreg1 = val->dreg;
2050                                 MONO_ADD_INS (cfg->cbb, ins);
2051                                 return;
2052                         }
2053                         break;
2054                 case MONO_ARM_FPU_FPA:
2055                         if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2056                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2057                                 return;
2058                         }
2059                         break;
2060                 default:
2061                         g_assert_not_reached ();
2062                 }
2063         }
2064
2065         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2066 }
2067
2068 #endif /* #ifndef DISABLE_JIT */
2069
2070 gboolean
2071 mono_arch_is_inst_imm (gint64 imm)
2072 {
2073         return TRUE;
2074 }
2075
2076 #define DYN_CALL_STACK_ARGS 6
2077
2078 typedef struct {
2079         MonoMethodSignature *sig;
2080         CallInfo *cinfo;
2081 } ArchDynCallInfo;
2082
2083 typedef struct {
2084         mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2085         mgreg_t res, res2;
2086         guint8 *ret;
2087 } DynCallArgs;
2088
2089 static gboolean
2090 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2091 {
2092         int i;
2093
2094         if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2095                 return FALSE;
2096
2097         switch (cinfo->ret.storage) {
2098         case RegTypeNone:
2099         case RegTypeGeneral:
2100         case RegTypeIRegPair:
2101         case RegTypeStructByAddr:
2102                 break;
2103         case RegTypeFP:
2104                 if (IS_FPA)
2105                         return FALSE;
2106                 else if (IS_VFP)
2107                         break;
2108                 else
2109                         return FALSE;
2110         default:
2111                 return FALSE;
2112         }
2113
2114         for (i = 0; i < cinfo->nargs; ++i) {
2115                 switch (cinfo->args [i].storage) {
2116                 case RegTypeGeneral:
2117                         break;
2118                 case RegTypeIRegPair:
2119                         break;
2120                 case RegTypeBase:
2121                         if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2122                                 return FALSE;
2123                         break;
2124                 case RegTypeStructByVal:
2125                         if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2126                                 return FALSE;
2127                         break;
2128                 default:
2129                         return FALSE;
2130                 }
2131         }
2132
2133         // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2134         for (i = 0; i < sig->param_count; ++i) {
2135                 MonoType *t = sig->params [i];
2136
2137                 if (t->byref)
2138                         continue;
2139
2140                 switch (t->type) {
2141                 case MONO_TYPE_R4:
2142                 case MONO_TYPE_R8:
2143                         if (IS_SOFT_FLOAT)
2144                                 return FALSE;
2145                         else
2146                                 break;
2147                         /*
2148                 case MONO_TYPE_I8:
2149                 case MONO_TYPE_U8:
2150                         return FALSE;
2151                         */
2152                 default:
2153                         break;
2154                 }
2155         }
2156
2157         return TRUE;
2158 }
2159
2160 MonoDynCallInfo*
2161 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2162 {
2163         ArchDynCallInfo *info;
2164         CallInfo *cinfo;
2165
2166         cinfo = get_call_info (NULL, NULL, sig);
2167
2168         if (!dyn_call_supported (cinfo, sig)) {
2169                 g_free (cinfo);
2170                 return NULL;
2171         }
2172
2173         info = g_new0 (ArchDynCallInfo, 1);
2174         // FIXME: Preprocess the info to speed up start_dyn_call ()
2175         info->sig = sig;
2176         info->cinfo = cinfo;
2177
2178         return (MonoDynCallInfo*)info;
2179 }
2180
2181 void
2182 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2183 {
2184         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2185
2186         g_free (ainfo->cinfo);
2187         g_free (ainfo);
2188 }
2189
2190 void
2191 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2192 {
2193         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2194         DynCallArgs *p = (DynCallArgs*)buf;
2195         int arg_index, greg, i, j, pindex;
2196         MonoMethodSignature *sig = dinfo->sig;
2197
2198         g_assert (buf_len >= sizeof (DynCallArgs));
2199
2200         p->res = 0;
2201         p->ret = ret;
2202
2203         arg_index = 0;
2204         greg = 0;
2205         pindex = 0;
2206
2207         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2208                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2209                 if (!sig->hasthis)
2210                         pindex = 1;
2211         }
2212
2213         if (dinfo->cinfo->vtype_retaddr)
2214                 p->regs [greg ++] = (mgreg_t)ret;
2215
2216         for (i = pindex; i < sig->param_count; i++) {
2217                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2218                 gpointer *arg = args [arg_index ++];
2219                 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2220                 int slot = -1;
2221
2222                 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2223                         slot = ainfo->reg;
2224                 else if (ainfo->storage == RegTypeBase)
2225                         slot = PARAM_REGS + (ainfo->offset / 4);
2226                 else
2227                         g_assert_not_reached ();
2228
2229                 if (t->byref) {
2230                         p->regs [slot] = (mgreg_t)*arg;
2231                         continue;
2232                 }
2233
2234                 switch (t->type) {
2235                 case MONO_TYPE_STRING:
2236                 case MONO_TYPE_CLASS:
2237                 case MONO_TYPE_ARRAY:
2238                 case MONO_TYPE_SZARRAY:
2239                 case MONO_TYPE_OBJECT:
2240                 case MONO_TYPE_PTR:
2241                 case MONO_TYPE_I:
2242                 case MONO_TYPE_U:
2243                         p->regs [slot] = (mgreg_t)*arg;
2244                         break;
2245                 case MONO_TYPE_BOOLEAN:
2246                 case MONO_TYPE_U1:
2247                         p->regs [slot] = *(guint8*)arg;
2248                         break;
2249                 case MONO_TYPE_I1:
2250                         p->regs [slot] = *(gint8*)arg;
2251                         break;
2252                 case MONO_TYPE_I2:
2253                         p->regs [slot] = *(gint16*)arg;
2254                         break;
2255                 case MONO_TYPE_U2:
2256                 case MONO_TYPE_CHAR:
2257                         p->regs [slot] = *(guint16*)arg;
2258                         break;
2259                 case MONO_TYPE_I4:
2260                         p->regs [slot] = *(gint32*)arg;
2261                         break;
2262                 case MONO_TYPE_U4:
2263                         p->regs [slot] = *(guint32*)arg;
2264                         break;
2265                 case MONO_TYPE_I8:
2266                 case MONO_TYPE_U8:
2267                         p->regs [slot ++] = (mgreg_t)arg [0];
2268                         p->regs [slot] = (mgreg_t)arg [1];
2269                         break;
2270                 case MONO_TYPE_R4:
2271                         p->regs [slot] = *(mgreg_t*)arg;
2272                         break;
2273                 case MONO_TYPE_R8:
2274                         p->regs [slot ++] = (mgreg_t)arg [0];
2275                         p->regs [slot] = (mgreg_t)arg [1];
2276                         break;
2277                 case MONO_TYPE_GENERICINST:
2278                         if (MONO_TYPE_IS_REFERENCE (t)) {
2279                                 p->regs [slot] = (mgreg_t)*arg;
2280                                 break;
2281                         } else {
2282                                 /* Fall though */
2283                         }
2284                 case MONO_TYPE_VALUETYPE:
2285                         g_assert (ainfo->storage == RegTypeStructByVal);
2286
2287                         if (ainfo->size == 0)
2288                                 slot = PARAM_REGS + (ainfo->offset / 4);
2289                         else
2290                                 slot = ainfo->reg;
2291
2292                         for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2293                                 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2294                         break;
2295                 default:
2296                         g_assert_not_reached ();
2297                 }
2298         }
2299 }
2300
2301 void
2302 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2303 {
2304         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2305         MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2306         guint8 *ret = ((DynCallArgs*)buf)->ret;
2307         mgreg_t res = ((DynCallArgs*)buf)->res;
2308         mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2309
2310         switch (mono_type_get_underlying_type (sig->ret)->type) {
2311         case MONO_TYPE_VOID:
2312                 *(gpointer*)ret = NULL;
2313                 break;
2314         case MONO_TYPE_STRING:
2315         case MONO_TYPE_CLASS:
2316         case MONO_TYPE_ARRAY:
2317         case MONO_TYPE_SZARRAY:
2318         case MONO_TYPE_OBJECT:
2319         case MONO_TYPE_I:
2320         case MONO_TYPE_U:
2321         case MONO_TYPE_PTR:
2322                 *(gpointer*)ret = (gpointer)res;
2323                 break;
2324         case MONO_TYPE_I1:
2325                 *(gint8*)ret = res;
2326                 break;
2327         case MONO_TYPE_U1:
2328         case MONO_TYPE_BOOLEAN:
2329                 *(guint8*)ret = res;
2330                 break;
2331         case MONO_TYPE_I2:
2332                 *(gint16*)ret = res;
2333                 break;
2334         case MONO_TYPE_U2:
2335         case MONO_TYPE_CHAR:
2336                 *(guint16*)ret = res;
2337                 break;
2338         case MONO_TYPE_I4:
2339                 *(gint32*)ret = res;
2340                 break;
2341         case MONO_TYPE_U4:
2342                 *(guint32*)ret = res;
2343                 break;
2344         case MONO_TYPE_I8:
2345         case MONO_TYPE_U8:
2346                 /* This handles endianness as well */
2347                 ((gint32*)ret) [0] = res;
2348                 ((gint32*)ret) [1] = res2;
2349                 break;
2350         case MONO_TYPE_GENERICINST:
2351                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2352                         *(gpointer*)ret = (gpointer)res;
2353                         break;
2354                 } else {
2355                         /* Fall though */
2356                 }
2357         case MONO_TYPE_VALUETYPE:
2358                 g_assert (ainfo->cinfo->vtype_retaddr);
2359                 /* Nothing to do */
2360                 break;
2361         case MONO_TYPE_R4:
2362                 g_assert (IS_VFP);
2363                 *(float*)ret = *(float*)&res;
2364                 break;
2365         case MONO_TYPE_R8: {
2366                 mgreg_t regs [2];
2367
2368                 g_assert (IS_VFP);
2369                 regs [0] = res;
2370                 regs [1] = res2;
2371
2372                 *(double*)ret = *(double*)&regs;
2373                 break;
2374         }
2375         default:
2376                 g_assert_not_reached ();
2377         }
2378 }
2379
2380 #ifndef DISABLE_JIT
2381
2382 /*
2383  * Allow tracing to work with this interface (with an optional argument)
2384  */
2385
2386 void*
2387 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2388 {
2389         guchar *code = p;
2390
2391         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2392         ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2393         code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2394         code = emit_call_reg (code, ARMREG_R2);
2395         return code;
2396 }
2397
2398 enum {
2399         SAVE_NONE,
2400         SAVE_STRUCT,
2401         SAVE_ONE,
2402         SAVE_TWO,
2403         SAVE_FP
2404 };
2405
2406 void*
2407 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2408 {
2409         guchar *code = p;
2410         int save_mode = SAVE_NONE;
2411         int offset;
2412         MonoMethod *method = cfg->method;
2413         int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2414         int save_offset = cfg->param_area;
2415         save_offset += 7;
2416         save_offset &= ~7;
2417
2418         offset = code - cfg->native_code;
2419         /* we need about 16 instructions */
2420         if (offset > (cfg->code_size - 16 * 4)) {
2421                 cfg->code_size *= 2;
2422                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2423                 code = cfg->native_code + offset;
2424         }
2425         switch (rtype) {
2426         case MONO_TYPE_VOID:
2427                 /* special case string .ctor icall */
2428                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2429                         save_mode = SAVE_ONE;
2430                 else
2431                         save_mode = SAVE_NONE;
2432                 break;
2433         case MONO_TYPE_I8:
2434         case MONO_TYPE_U8:
2435                 save_mode = SAVE_TWO;
2436                 break;
2437         case MONO_TYPE_R4:
2438         case MONO_TYPE_R8:
2439                 save_mode = SAVE_FP;
2440                 break;
2441         case MONO_TYPE_VALUETYPE:
2442                 save_mode = SAVE_STRUCT;
2443                 break;
2444         default:
2445                 save_mode = SAVE_ONE;
2446                 break;
2447         }
2448
2449         switch (save_mode) {
2450         case SAVE_TWO:
2451                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2452                 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2453                 if (enable_arguments) {
2454                         ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2455                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2456                 }
2457                 break;
2458         case SAVE_ONE:
2459                 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2460                 if (enable_arguments) {
2461                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2462                 }
2463                 break;
2464         case SAVE_FP:
2465                 /* FIXME: what reg?  */
2466                 if (enable_arguments) {
2467                         /* FIXME: what reg?  */
2468                 }
2469                 break;
2470         case SAVE_STRUCT:
2471                 if (enable_arguments) {
2472                         /* FIXME: get the actual address  */
2473                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2474                 }
2475                 break;
2476         case SAVE_NONE:
2477         default:
2478                 break;
2479         }
2480
2481         code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2482         code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2483         code = emit_call_reg (code, ARMREG_IP);
2484
2485         switch (save_mode) {
2486         case SAVE_TWO:
2487                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2488                 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2489                 break;
2490         case SAVE_ONE:
2491                 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2492                 break;
2493         case SAVE_FP:
2494                 /* FIXME */
2495                 break;
2496         case SAVE_NONE:
2497         default:
2498                 break;
2499         }
2500
2501         return code;
2502 }
2503
2504 /*
2505  * The immediate field for cond branches is big enough for all reasonable methods
2506  */
2507 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2508 if (0 && ins->inst_true_bb->native_offset) { \
2509         ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2510 } else { \
2511         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2512         ARM_B_COND (code, (condcode), 0);       \
2513 }
2514
2515 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2516
2517 /* emit an exception if condition is fail
2518  *
2519  * We assign the extra code used to throw the implicit exceptions
2520  * to cfg->bb_exit as far as the big branch handling is concerned
2521  */
2522 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name)            \
2523         do {                                                        \
2524                 mono_add_patch_info (cfg, code - cfg->native_code,   \
2525                                     MONO_PATCH_INFO_EXC, exc_name);  \
2526                 ARM_BL_COND (code, (condcode), 0);      \
2527         } while (0);
2528
2529 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2530
2531 void
2532 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2533 {
2534 }
2535
2536 void
2537 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2538 {
2539         MonoInst *ins, *n, *last_ins = NULL;
2540
2541         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2542                 switch (ins->opcode) {
2543                 case OP_MUL_IMM:
2544                 case OP_IMUL_IMM:
2545                         /* Already done by an arch-independent pass */
2546                         break;
2547                 case OP_LOAD_MEMBASE:
2548                 case OP_LOADI4_MEMBASE:
2549                         /*
2550                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2551                          * OP_LOAD_MEMBASE offset(basereg), reg
2552                          */
2553                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2554                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2555                             ins->inst_basereg == last_ins->inst_destbasereg &&
2556                             ins->inst_offset == last_ins->inst_offset) {
2557                                 if (ins->dreg == last_ins->sreg1) {
2558                                         MONO_DELETE_INS (bb, ins);
2559                                         continue;
2560                                 } else {
2561                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2562                                         ins->opcode = OP_MOVE;
2563                                         ins->sreg1 = last_ins->sreg1;
2564                                 }
2565
2566                         /*
2567                          * Note: reg1 must be different from the basereg in the second load
2568                          * OP_LOAD_MEMBASE offset(basereg), reg1
2569                          * OP_LOAD_MEMBASE offset(basereg), reg2
2570                          * -->
2571                          * OP_LOAD_MEMBASE offset(basereg), reg1
2572                          * OP_MOVE reg1, reg2
2573                          */
2574                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2575                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2576                               ins->inst_basereg != last_ins->dreg &&
2577                               ins->inst_basereg == last_ins->inst_basereg &&
2578                               ins->inst_offset == last_ins->inst_offset) {
2579
2580                                 if (ins->dreg == last_ins->dreg) {
2581                                         MONO_DELETE_INS (bb, ins);
2582                                         continue;
2583                                 } else {
2584                                         ins->opcode = OP_MOVE;
2585                                         ins->sreg1 = last_ins->dreg;
2586                                 }
2587
2588                                 //g_assert_not_reached ();
2589
2590 #if 0
2591                         /*
2592                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2593                          * OP_LOAD_MEMBASE offset(basereg), reg
2594                          * -->
2595                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2596                          * OP_ICONST reg, imm
2597                          */
2598                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2599                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2600                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2601                                    ins->inst_offset == last_ins->inst_offset) {
2602                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2603                                 ins->opcode = OP_ICONST;
2604                                 ins->inst_c0 = last_ins->inst_imm;
2605                                 g_assert_not_reached (); // check this rule
2606 #endif
2607                         }
2608                         break;
2609                 case OP_LOADU1_MEMBASE:
2610                 case OP_LOADI1_MEMBASE:
2611                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2612                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2613                                         ins->inst_offset == last_ins->inst_offset) {
2614                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2615                                 ins->sreg1 = last_ins->sreg1;
2616                         }
2617                         break;
2618                 case OP_LOADU2_MEMBASE:
2619                 case OP_LOADI2_MEMBASE:
2620                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2621                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2622                                         ins->inst_offset == last_ins->inst_offset) {
2623                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2624                                 ins->sreg1 = last_ins->sreg1;
2625                         }
2626                         break;
2627                 case OP_MOVE:
2628                         ins->opcode = OP_MOVE;
2629                         /*
2630                          * OP_MOVE reg, reg
2631                          */
2632                         if (ins->dreg == ins->sreg1) {
2633                                 MONO_DELETE_INS (bb, ins);
2634                                 continue;
2635                         }
2636                         /*
2637                          * OP_MOVE sreg, dreg
2638                          * OP_MOVE dreg, sreg
2639                          */
2640                         if (last_ins && last_ins->opcode == OP_MOVE &&
2641                             ins->sreg1 == last_ins->dreg &&
2642                             ins->dreg == last_ins->sreg1) {
2643                                 MONO_DELETE_INS (bb, ins);
2644                                 continue;
2645                         }
2646                         break;
2647                 }
2648                 last_ins = ins;
2649                 ins = ins->next;
2650         }
2651         bb->last_ins = last_ins;
2652 }
2653
2654 /*
2655  * the branch_cc_table should maintain the order of these
2656  * opcodes.
2657 case CEE_BEQ:
2658 case CEE_BGE:
2659 case CEE_BGT:
2660 case CEE_BLE:
2661 case CEE_BLT:
2662 case CEE_BNE_UN:
2663 case CEE_BGE_UN:
2664 case CEE_BGT_UN:
2665 case CEE_BLE_UN:
2666 case CEE_BLT_UN:
2667  */
2668 static const guchar
2669 branch_cc_table [] = {
2670         ARMCOND_EQ,
2671         ARMCOND_GE,
2672         ARMCOND_GT,
2673         ARMCOND_LE,
2674         ARMCOND_LT,
2675
2676         ARMCOND_NE,
2677         ARMCOND_HS,
2678         ARMCOND_HI,
2679         ARMCOND_LS,
2680         ARMCOND_LO
2681 };
2682
2683 #define NEW_INS(cfg,dest,op) do {       \
2684                 MONO_INST_NEW ((cfg), (dest), (op)); \
2685         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2686         } while (0)
2687
2688 static int
2689 map_to_reg_reg_op (int op)
2690 {
2691         switch (op) {
2692         case OP_ADD_IMM:
2693                 return OP_IADD;
2694         case OP_SUB_IMM:
2695                 return OP_ISUB;
2696         case OP_AND_IMM:
2697                 return OP_IAND;
2698         case OP_COMPARE_IMM:
2699                 return OP_COMPARE;
2700         case OP_ICOMPARE_IMM:
2701                 return OP_ICOMPARE;
2702         case OP_ADDCC_IMM:
2703                 return OP_ADDCC;
2704         case OP_ADC_IMM:
2705                 return OP_ADC;
2706         case OP_SUBCC_IMM:
2707                 return OP_SUBCC;
2708         case OP_SBB_IMM:
2709                 return OP_SBB;
2710         case OP_OR_IMM:
2711                 return OP_IOR;
2712         case OP_XOR_IMM:
2713                 return OP_IXOR;
2714         case OP_LOAD_MEMBASE:
2715                 return OP_LOAD_MEMINDEX;
2716         case OP_LOADI4_MEMBASE:
2717                 return OP_LOADI4_MEMINDEX;
2718         case OP_LOADU4_MEMBASE:
2719                 return OP_LOADU4_MEMINDEX;
2720         case OP_LOADU1_MEMBASE:
2721                 return OP_LOADU1_MEMINDEX;
2722         case OP_LOADI2_MEMBASE:
2723                 return OP_LOADI2_MEMINDEX;
2724         case OP_LOADU2_MEMBASE:
2725                 return OP_LOADU2_MEMINDEX;
2726         case OP_LOADI1_MEMBASE:
2727                 return OP_LOADI1_MEMINDEX;
2728         case OP_STOREI1_MEMBASE_REG:
2729                 return OP_STOREI1_MEMINDEX;
2730         case OP_STOREI2_MEMBASE_REG:
2731                 return OP_STOREI2_MEMINDEX;
2732         case OP_STOREI4_MEMBASE_REG:
2733                 return OP_STOREI4_MEMINDEX;
2734         case OP_STORE_MEMBASE_REG:
2735                 return OP_STORE_MEMINDEX;
2736         case OP_STORER4_MEMBASE_REG:
2737                 return OP_STORER4_MEMINDEX;
2738         case OP_STORER8_MEMBASE_REG:
2739                 return OP_STORER8_MEMINDEX;
2740         case OP_STORE_MEMBASE_IMM:
2741                 return OP_STORE_MEMBASE_REG;
2742         case OP_STOREI1_MEMBASE_IMM:
2743                 return OP_STOREI1_MEMBASE_REG;
2744         case OP_STOREI2_MEMBASE_IMM:
2745                 return OP_STOREI2_MEMBASE_REG;
2746         case OP_STOREI4_MEMBASE_IMM:
2747                 return OP_STOREI4_MEMBASE_REG;
2748         }
2749         g_assert_not_reached ();
2750 }
2751
2752 /*
2753  * Remove from the instruction list the instructions that can't be
2754  * represented with very simple instructions with no register
2755  * requirements.
2756  */
2757 void
2758 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2759 {
2760         MonoInst *ins, *temp, *last_ins = NULL;
2761         int rot_amount, imm8, low_imm;
2762
2763         MONO_BB_FOR_EACH_INS (bb, ins) {
2764 loop_start:
2765                 switch (ins->opcode) {
2766                 case OP_ADD_IMM:
2767                 case OP_SUB_IMM:
2768                 case OP_AND_IMM:
2769                 case OP_COMPARE_IMM:
2770                 case OP_ICOMPARE_IMM:
2771                 case OP_ADDCC_IMM:
2772                 case OP_ADC_IMM:
2773                 case OP_SUBCC_IMM:
2774                 case OP_SBB_IMM:
2775                 case OP_OR_IMM:
2776                 case OP_XOR_IMM:
2777                 case OP_IADD_IMM:
2778                 case OP_ISUB_IMM:
2779                 case OP_IAND_IMM:
2780                 case OP_IADC_IMM:
2781                 case OP_ISBB_IMM:
2782                 case OP_IOR_IMM:
2783                 case OP_IXOR_IMM:
2784                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2785                                 NEW_INS (cfg, temp, OP_ICONST);
2786                                 temp->inst_c0 = ins->inst_imm;
2787                                 temp->dreg = mono_alloc_ireg (cfg);
2788                                 ins->sreg2 = temp->dreg;
2789                                 ins->opcode = mono_op_imm_to_op (ins->opcode);
2790                         }
2791                         if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2792                                 goto loop_start;
2793                         else
2794                                 break;
2795                 case OP_MUL_IMM:
2796                 case OP_IMUL_IMM:
2797                         if (ins->inst_imm == 1) {
2798                                 ins->opcode = OP_MOVE;
2799                                 break;
2800                         }
2801                         if (ins->inst_imm == 0) {
2802                                 ins->opcode = OP_ICONST;
2803                                 ins->inst_c0 = 0;
2804                                 break;
2805                         }
2806                         imm8 = mono_is_power_of_two (ins->inst_imm);
2807                         if (imm8 > 0) {
2808                                 ins->opcode = OP_SHL_IMM;
2809                                 ins->inst_imm = imm8;
2810                                 break;
2811                         }
2812                         NEW_INS (cfg, temp, OP_ICONST);
2813                         temp->inst_c0 = ins->inst_imm;
2814                         temp->dreg = mono_alloc_ireg (cfg);
2815                         ins->sreg2 = temp->dreg;
2816                         ins->opcode = OP_IMUL;
2817                         break;
2818                 case OP_SBB:
2819                 case OP_ISBB:
2820                 case OP_SUBCC:
2821                 case OP_ISUBCC:
2822                         if (ins->next  && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2823                                 /* ARM sets the C flag to 1 if there was _no_ overflow */
2824                                 ins->next->opcode = OP_COND_EXC_NC;
2825                         break;
2826                 case OP_LOCALLOC_IMM:
2827                         NEW_INS (cfg, temp, OP_ICONST);
2828                         temp->inst_c0 = ins->inst_imm;
2829                         temp->dreg = mono_alloc_ireg (cfg);
2830                         ins->sreg1 = temp->dreg;
2831                         ins->opcode = OP_LOCALLOC;
2832                         break;
2833                 case OP_LOAD_MEMBASE:
2834                 case OP_LOADI4_MEMBASE:
2835                 case OP_LOADU4_MEMBASE:
2836                 case OP_LOADU1_MEMBASE:
2837                         /* we can do two things: load the immed in a register
2838                          * and use an indexed load, or see if the immed can be
2839                          * represented as an ad_imm + a load with a smaller offset
2840                          * that fits. We just do the first for now, optimize later.
2841                          */
2842                         if (arm_is_imm12 (ins->inst_offset))
2843                                 break;
2844                         NEW_INS (cfg, temp, OP_ICONST);
2845                         temp->inst_c0 = ins->inst_offset;
2846                         temp->dreg = mono_alloc_ireg (cfg);
2847                         ins->sreg2 = temp->dreg;
2848                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2849                         break;
2850                 case OP_LOADI2_MEMBASE:
2851                 case OP_LOADU2_MEMBASE:
2852                 case OP_LOADI1_MEMBASE:
2853                         if (arm_is_imm8 (ins->inst_offset))
2854                                 break;
2855                         NEW_INS (cfg, temp, OP_ICONST);
2856                         temp->inst_c0 = ins->inst_offset;
2857                         temp->dreg = mono_alloc_ireg (cfg);
2858                         ins->sreg2 = temp->dreg;
2859                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2860                         break;
2861                 case OP_LOADR4_MEMBASE:
2862                 case OP_LOADR8_MEMBASE:
2863                         if (arm_is_fpimm8 (ins->inst_offset))
2864                                 break;
2865                         low_imm = ins->inst_offset & 0x1ff;
2866                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2867                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2868                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2869                                 temp->sreg1 = ins->inst_basereg;
2870                                 temp->dreg = mono_alloc_ireg (cfg);
2871                                 ins->inst_basereg = temp->dreg;
2872                                 ins->inst_offset = low_imm;
2873                                 break;
2874                         }
2875                         /* VFP/FPA doesn't have indexed load instructions */
2876                         g_assert_not_reached ();
2877                         break;
2878                 case OP_STORE_MEMBASE_REG:
2879                 case OP_STOREI4_MEMBASE_REG:
2880                 case OP_STOREI1_MEMBASE_REG:
2881                         if (arm_is_imm12 (ins->inst_offset))
2882                                 break;
2883                         NEW_INS (cfg, temp, OP_ICONST);
2884                         temp->inst_c0 = ins->inst_offset;
2885                         temp->dreg = mono_alloc_ireg (cfg);
2886                         ins->sreg2 = temp->dreg;
2887                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2888                         break;
2889                 case OP_STOREI2_MEMBASE_REG:
2890                         if (arm_is_imm8 (ins->inst_offset))
2891                                 break;
2892                         NEW_INS (cfg, temp, OP_ICONST);
2893                         temp->inst_c0 = ins->inst_offset;
2894                         temp->dreg = mono_alloc_ireg (cfg);
2895                         ins->sreg2 = temp->dreg;
2896                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2897                         break;
2898                 case OP_STORER4_MEMBASE_REG:
2899                 case OP_STORER8_MEMBASE_REG:
2900                         if (arm_is_fpimm8 (ins->inst_offset))
2901                                 break;
2902                         low_imm = ins->inst_offset & 0x1ff;
2903                         if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2904                                 NEW_INS (cfg, temp, OP_ADD_IMM);
2905                                 temp->inst_imm = ins->inst_offset & ~0x1ff;
2906                                 temp->sreg1 = ins->inst_destbasereg;
2907                                 temp->dreg = mono_alloc_ireg (cfg);
2908                                 ins->inst_destbasereg = temp->dreg;
2909                                 ins->inst_offset = low_imm;
2910                                 break;
2911                         }
2912                         /*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
2913                         /* VFP/FPA doesn't have indexed store instructions */
2914                         g_assert_not_reached ();
2915                         break;
2916                 case OP_STORE_MEMBASE_IMM:
2917                 case OP_STOREI1_MEMBASE_IMM:
2918                 case OP_STOREI2_MEMBASE_IMM:
2919                 case OP_STOREI4_MEMBASE_IMM:
2920                         NEW_INS (cfg, temp, OP_ICONST);
2921                         temp->inst_c0 = ins->inst_imm;
2922                         temp->dreg = mono_alloc_ireg (cfg);
2923                         ins->sreg1 = temp->dreg;
2924                         ins->opcode = map_to_reg_reg_op (ins->opcode);
2925                         last_ins = temp;
2926                         goto loop_start; /* make it handle the possibly big ins->inst_offset */
2927                 case OP_FCOMPARE: {
2928                         gboolean swap = FALSE;
2929                         int reg;
2930
2931                         if (!ins->next) {
2932                                 /* Optimized away */
2933                                 NULLIFY_INS (ins);
2934                                 break;
2935                         }
2936
2937                         /* Some fp compares require swapped operands */
2938                         switch (ins->next->opcode) {
2939                         case OP_FBGT:
2940                                 ins->next->opcode = OP_FBLT;
2941                                 swap = TRUE;
2942                                 break;
2943                         case OP_FBGT_UN:
2944                                 ins->next->opcode = OP_FBLT_UN;
2945                                 swap = TRUE;
2946                                 break;
2947                         case OP_FBLE:
2948                                 ins->next->opcode = OP_FBGE;
2949                                 swap = TRUE;
2950                                 break;
2951                         case OP_FBLE_UN:
2952                                 ins->next->opcode = OP_FBGE_UN;
2953                                 swap = TRUE;
2954                                 break;
2955                         default:
2956                                 break;
2957                         }
2958                         if (swap) {
2959                                 reg = ins->sreg1;
2960                                 ins->sreg1 = ins->sreg2;
2961                                 ins->sreg2 = reg;
2962                         }
2963                         break;
2964                 }
2965                 }
2966
2967                 last_ins = ins;
2968         }
2969         bb->last_ins = last_ins;
2970         bb->max_vreg = cfg->next_vreg;
2971 }
2972
2973 void
2974 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2975 {
2976         MonoInst *ins;
2977
2978         if (long_ins->opcode == OP_LNEG) {
2979                 ins = long_ins;
2980                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2981                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2982                 NULLIFY_INS (ins);
2983         }
2984 }
2985
2986 static guchar*
2987 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2988 {
2989         /* sreg is a float, dreg is an integer reg  */
2990         if (IS_FPA)
2991                 ARM_FPA_FIXZ (code, dreg, sreg);
2992         else if (IS_VFP) {
2993                 if (is_signed)
2994                         ARM_TOSIZD (code, ARM_VFP_F0, sreg);
2995                 else
2996                         ARM_TOUIZD (code, ARM_VFP_F0, sreg);
2997                 ARM_FMRS (code, dreg, ARM_VFP_F0);
2998         }
2999         if (!is_signed) {
3000                 if (size == 1)
3001                         ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3002                 else if (size == 2) {
3003                         ARM_SHL_IMM (code, dreg, dreg, 16);
3004                         ARM_SHR_IMM (code, dreg, dreg, 16);
3005                 }
3006         } else {
3007                 if (size == 1) {
3008                         ARM_SHL_IMM (code, dreg, dreg, 24);
3009                         ARM_SAR_IMM (code, dreg, dreg, 24);
3010                 } else if (size == 2) {
3011                         ARM_SHL_IMM (code, dreg, dreg, 16);
3012                         ARM_SAR_IMM (code, dreg, dreg, 16);
3013                 }
3014         }
3015         return code;
3016 }
3017
3018 #endif /* #ifndef DISABLE_JIT */
3019
3020 typedef struct {
3021         guchar *code;
3022         const guchar *target;
3023         int absolute;
3024         int found;
3025 } PatchData;
3026
3027 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3028
3029 static int
3030 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3031         PatchData *pdata = (PatchData*)user_data;
3032         guchar *code = data;
3033         guint32 *thunks = data;
3034         guint32 *endthunks = (guint32*)(code + bsize);
3035         int count = 0;
3036         int difflow, diffhigh;
3037
3038         /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3039         difflow = (char*)pdata->code - (char*)thunks;
3040         diffhigh = (char*)pdata->code - (char*)endthunks;
3041         if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3042                 return 0;
3043
3044         /*
3045          * The thunk is composed of 3 words:
3046          * load constant from thunks [2] into ARM_IP
3047          * bx to ARM_IP
3048          * address constant
3049          * Note that the LR register is already setup
3050          */
3051         //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3052         if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3053                 while (thunks < endthunks) {
3054                         //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3055                         if (thunks [2] == (guint32)pdata->target) {
3056                                 arm_patch (pdata->code, (guchar*)thunks);
3057                                 mono_arch_flush_icache (pdata->code, 4);
3058                                 pdata->found = 1;
3059                                 return 1;
3060                         } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3061                                 /* found a free slot instead: emit thunk */
3062                                 /* ARMREG_IP is fine to use since this can't be an IMT call
3063                                  * which is indirect
3064                                  */
3065                                 code = (guchar*)thunks;
3066                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3067                                 if (thumb_supported)
3068                                         ARM_BX (code, ARMREG_IP);
3069                                 else
3070                                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3071                                 thunks [2] = (guint32)pdata->target;
3072                                 mono_arch_flush_icache ((guchar*)thunks, 12);
3073
3074                                 arm_patch (pdata->code, (guchar*)thunks);
3075                                 mono_arch_flush_icache (pdata->code, 4);
3076                                 pdata->found = 1;
3077                                 return 1;
3078                         }
3079                         /* skip 12 bytes, the size of the thunk */
3080                         thunks += 3;
3081                         count++;
3082                 }
3083                 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3084         }
3085         return 0;
3086 }
3087
3088 static void
3089 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3090 {
3091         PatchData pdata;
3092
3093         if (!domain)
3094                 domain = mono_domain_get ();
3095
3096         pdata.code = code;
3097         pdata.target = target;
3098         pdata.absolute = absolute;
3099         pdata.found = 0;
3100
3101         if (dyn_code_mp) {
3102                 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3103         }
3104
3105         if (pdata.found != 1) {
3106                 mono_domain_lock (domain);
3107                 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3108
3109                 if (!pdata.found) {
3110                         /* this uses the first available slot */
3111                         pdata.found = 2;
3112                         mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3113                 }
3114                 mono_domain_unlock (domain);
3115         }
3116
3117         if (pdata.found != 1) {
3118                 GHashTable *hash;
3119                 GHashTableIter iter;
3120                 MonoJitDynamicMethodInfo *ji;
3121
3122                 /*
3123                  * This might be a dynamic method, search its code manager. We can only
3124                  * use the dynamic method containing CODE, since the others might be freed later.
3125                  */
3126                 pdata.found = 0;
3127
3128                 mono_domain_lock (domain);
3129                 hash = domain_jit_info (domain)->dynamic_code_hash;
3130                 if (hash) {
3131                         /* FIXME: Speed this up */
3132                         g_hash_table_iter_init (&iter, hash);
3133                         while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3134                                 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3135                                 if (pdata.found == 1)
3136                                         break;
3137                         }
3138                 }
3139                 mono_domain_unlock (domain);
3140         }
3141         if (pdata.found != 1)
3142                 g_print ("thunk failed for %p from %p\n", target, code);
3143         g_assert (pdata.found == 1);
3144 }
3145
3146 static void
3147 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3148 {
3149         guint32 *code32 = (void*)code;
3150         guint32 ins = *code32;
3151         guint32 prim = (ins >> 25) & 7;
3152         guint32 tval = GPOINTER_TO_UINT (target);
3153
3154         //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3155         if (prim == 5) { /* 101b */
3156                 /* the diff starts 8 bytes from the branch opcode */
3157                 gint diff = target - code - 8;
3158                 gint tbits;
3159                 gint tmask = 0xffffffff;
3160                 if (tval & 1) { /* entering thumb mode */
3161                         diff = target - 1 - code - 8;
3162                         g_assert (thumb_supported);
3163                         tbits = 0xf << 28; /* bl->blx bit pattern */
3164                         g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3165                         /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3166                         if (diff & 2) {
3167                                 tbits |= 1 << 24;
3168                         }
3169                         tmask = ~(1 << 24); /* clear the link bit */
3170                         /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3171                 } else {
3172                         tbits = 0;
3173                 }
3174                 if (diff >= 0) {
3175                         if (diff <= 33554431) {
3176                                 diff >>= 2;
3177                                 ins = (ins & 0xff000000) | diff;
3178                                 ins &= tmask;
3179                                 *code32 = ins | tbits;
3180                                 return;
3181                         }
3182                 } else {
3183                         /* diff between 0 and -33554432 */
3184                         if (diff >= -33554432) {
3185                                 diff >>= 2;
3186                                 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3187                                 ins &= tmask;
3188                                 *code32 = ins | tbits;
3189                                 return;
3190                         }
3191                 }
3192
3193                 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3194                 return;
3195         }
3196
3197         /*
3198          * The alternative call sequences looks like this:
3199          *
3200          *      ldr ip, [pc] // loads the address constant
3201          *      b 1f         // jumps around the constant
3202          *      address constant embedded in the code
3203          *   1f:
3204          *      mov lr, pc
3205          *      mov pc, ip
3206          *
3207          * There are two cases for patching:
3208          * a) at the end of method emission: in this case code points to the start
3209          *    of the call sequence
3210          * b) during runtime patching of the call site: in this case code points
3211          *    to the mov pc, ip instruction
3212          *
3213          * We have to handle also the thunk jump code sequence:
3214          *
3215          *      ldr ip, [pc]
3216          *      mov pc, ip
3217          *      address constant // execution never reaches here
3218          */
3219         if ((ins & 0x0ffffff0) == 0x12fff10) {
3220                 /* Branch and exchange: the address is constructed in a reg
3221                  * We can patch BX when the code sequence is the following:
3222                  *  ldr     ip, [pc, #0]    ; 0x8
3223                  *  b       0xc
3224                  *  .word code_ptr
3225                  *  mov     lr, pc
3226                  *  bx      ips
3227                  * */
3228                 guint32 ccode [4];
3229                 guint8 *emit = (guint8*)ccode;
3230                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3231                 ARM_B (emit, 0);
3232                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3233                 ARM_BX (emit, ARMREG_IP);
3234
3235                 /*patching from magic trampoline*/
3236                 if (ins == ccode [3]) {
3237                         g_assert (code32 [-4] == ccode [0]);
3238                         g_assert (code32 [-3] == ccode [1]);
3239                         g_assert (code32 [-1] == ccode [2]);
3240                         code32 [-2] = (guint32)target;
3241                         return;
3242                 }
3243                 /*patching from JIT*/
3244                 if (ins == ccode [0]) {
3245                         g_assert (code32 [1] == ccode [1]);
3246                         g_assert (code32 [3] == ccode [2]);
3247                         g_assert (code32 [4] == ccode [3]);
3248                         code32 [2] = (guint32)target;
3249                         return;
3250                 }
3251                 g_assert_not_reached ();
3252         } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3253                 /*
3254                  * ldr ip, [pc, #0]
3255                  * b 0xc
3256                  * .word code_ptr
3257                  * blx ip
3258                  */
3259                 guint32 ccode [4];
3260                 guint8 *emit = (guint8*)ccode;
3261                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3262                 ARM_B (emit, 0);
3263                 ARM_BLX_REG (emit, ARMREG_IP);
3264
3265                 g_assert (code32 [-3] == ccode [0]);
3266                 g_assert (code32 [-2] == ccode [1]);
3267                 g_assert (code32 [0] == ccode [2]);
3268
3269                 code32 [-1] = (guint32)target;
3270         } else {
3271                 guint32 ccode [4];
3272                 guint32 *tmp = ccode;
3273                 guint8 *emit = (guint8*)tmp;
3274                 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3275                 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3276                 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3277                 ARM_BX (emit, ARMREG_IP);
3278                 if (ins == ccode [2]) {
3279                         g_assert_not_reached (); // should be -2 ...
3280                         code32 [-1] = (guint32)target;
3281                         return;
3282                 }
3283                 if (ins == ccode [0]) {
3284                         /* handles both thunk jump code and the far call sequence */
3285                         code32 [2] = (guint32)target;
3286                         return;
3287                 }
3288                 g_assert_not_reached ();
3289         }
3290 //      g_print ("patched with 0x%08x\n", ins);
3291 }
3292
3293 void
3294 arm_patch (guchar *code, const guchar *target)
3295 {
3296         arm_patch_general (NULL, code, target, NULL);
3297 }
3298
3299 /*
3300  * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3301  * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3302  * to be used with the emit macros.
3303  * Return -1 otherwise.
3304  */
3305 int
3306 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3307 {
3308         guint32 res, i;
3309         for (i = 0; i < 31; i+= 2) {
3310                 res = (val << (32 - i)) | (val >> i);
3311                 if (res & ~0xff)
3312                         continue;
3313                 *rot_amount = i? 32 - i: 0;
3314                 return res;
3315         }
3316         return -1;
3317 }
3318
3319 /*
3320  * Emits in code a sequence of instructions that load the value 'val'
3321  * into the dreg register. Uses at most 4 instructions.
3322  */
3323 guint8*
3324 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3325 {
3326         int imm8, rot_amount;
3327 #if 0
3328         ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3329         /* skip the constant pool */
3330         ARM_B (code, 0);
3331         *(int*)code = val;
3332         code += 4;
3333         return code;
3334 #endif
3335         if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3336                 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3337         } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3338                 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3339         } else {
3340                 if (v7_supported) {
3341                         ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3342                         if (val >> 16)
3343                                 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3344                         return code;
3345                 }
3346                 if (val & 0xFF) {
3347                         ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3348                         if (val & 0xFF00) {
3349                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3350                         }
3351                         if (val & 0xFF0000) {
3352                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3353                         }
3354                         if (val & 0xFF000000) {
3355                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3356                         }
3357                 } else if (val & 0xFF00) {
3358                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3359                         if (val & 0xFF0000) {
3360                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3361                         }
3362                         if (val & 0xFF000000) {
3363                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3364                         }
3365                 } else if (val & 0xFF0000) {
3366                         ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3367                         if (val & 0xFF000000) {
3368                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3369                         }
3370                 }
3371                 //g_assert_not_reached ();
3372         }
3373         return code;
3374 }
3375
3376 gboolean
3377 mono_arm_thumb_supported (void)
3378 {
3379         return thumb_supported;
3380 }
3381
3382 #ifndef DISABLE_JIT
3383
3384 /*
3385  * emit_load_volatile_arguments:
3386  *
3387  *  Load volatile arguments from the stack to the original input registers.
3388  * Required before a tail call.
3389  */
3390 static guint8*
3391 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3392 {
3393         MonoMethod *method = cfg->method;
3394         MonoMethodSignature *sig;
3395         MonoInst *inst;
3396         CallInfo *cinfo;
3397         guint32 i, pos;
3398
3399         /* FIXME: Generate intermediate code instead */
3400
3401         sig = mono_method_signature (method);
3402
3403         /* This is the opposite of the code in emit_prolog */
3404
3405         pos = 0;
3406
3407         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3408
3409         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3410                 ArgInfo *ainfo = &cinfo->ret;
3411                 inst = cfg->vret_addr;
3412                 g_assert (arm_is_imm12 (inst->inst_offset));
3413                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3414         }
3415         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3416                 ArgInfo *ainfo = cinfo->args + i;
3417                 inst = cfg->args [pos];
3418
3419                 if (cfg->verbose_level > 2)
3420                         g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3421                 if (inst->opcode == OP_REGVAR) {
3422                         if (ainfo->storage == RegTypeGeneral)
3423                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3424                         else if (ainfo->storage == RegTypeFP) {
3425                                 g_assert_not_reached ();
3426                         } else if (ainfo->storage == RegTypeBase) {
3427                                 // FIXME:
3428                                 NOT_IMPLEMENTED;
3429                                 /*
3430                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3431                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3432                                 } else {
3433                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3434                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3435                                 }
3436                                 */
3437                         } else
3438                                 g_assert_not_reached ();
3439                 } else {
3440                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3441                                 switch (ainfo->size) {
3442                                 case 1:
3443                                 case 2:
3444                                         // FIXME:
3445                                         NOT_IMPLEMENTED;
3446                                         break;
3447                                 case 8:
3448                                         g_assert (arm_is_imm12 (inst->inst_offset));
3449                                         ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3450                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
3451                                         ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3452                                         break;
3453                                 default:
3454                                         if (arm_is_imm12 (inst->inst_offset)) {
3455                                                 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3456                                         } else {
3457                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3458                                                 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3459                                         }
3460                                         break;
3461                                 }
3462                         } else if (ainfo->storage == RegTypeBaseGen) {
3463                                 // FIXME:
3464                                 NOT_IMPLEMENTED;
3465                         } else if (ainfo->storage == RegTypeBase) {
3466                                 /* Nothing to do */
3467                         } else if (ainfo->storage == RegTypeFP) {
3468                                 g_assert_not_reached ();
3469                         } else if (ainfo->storage == RegTypeStructByVal) {
3470                                 int doffset = inst->inst_offset;
3471                                 int soffset = 0;
3472                                 int cur_reg;
3473                                 int size = 0;
3474                                 if (mono_class_from_mono_type (inst->inst_vtype))
3475                                         size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3476                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3477                                         if (arm_is_imm12 (doffset)) {
3478                                                 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3479                                         } else {
3480                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3481                                                 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3482                                         }
3483                                         soffset += sizeof (gpointer);
3484                                         doffset += sizeof (gpointer);
3485                                 }
3486                                 if (ainfo->vtsize)
3487                                         // FIXME:
3488                                         NOT_IMPLEMENTED;
3489                         } else if (ainfo->storage == RegTypeStructByAddr) {
3490                         } else {
3491                                 // FIXME:
3492                                 NOT_IMPLEMENTED;
3493                         }
3494                 }
3495                 pos ++;
3496         }
3497
3498         g_free (cinfo);
3499
3500         return code;
3501 }
3502
3503 void
3504 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3505 {
3506         MonoInst *ins;
3507         MonoCallInst *call;
3508         guint offset;
3509         guint8 *code = cfg->native_code + cfg->code_len;
3510         MonoInst *last_ins = NULL;
3511         guint last_offset = 0;
3512         int max_len, cpos;
3513         int imm8, rot_amount;
3514
3515         /* we don't align basic blocks of loops on arm */
3516
3517         if (cfg->verbose_level > 2)
3518                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3519
3520         cpos = bb->max_offset;
3521
3522         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3523                 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3524                 //g_assert (!mono_compile_aot);
3525                 //cpos += 6;
3526                 //if (bb->cil_code)
3527                 //      cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3528                 /* this is not thread save, but good enough */
3529                 /* fixme: howto handle overflows? */
3530                 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3531         }
3532
3533     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3534                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3535                                                          (gpointer)"mono_break");
3536                 code = emit_call_seq (cfg, code);
3537         }
3538
3539         MONO_BB_FOR_EACH_INS (bb, ins) {
3540                 offset = code - cfg->native_code;
3541
3542                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3543
3544                 if (offset > (cfg->code_size - max_len - 16)) {
3545                         cfg->code_size *= 2;
3546                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3547                         code = cfg->native_code + offset;
3548                 }
3549         //      if (ins->cil_code)
3550         //              g_print ("cil code\n");
3551                 mono_debug_record_line_number (cfg, ins, offset);
3552
3553                 switch (ins->opcode) {
3554                 case OP_MEMORY_BARRIER:
3555                         if (v6_supported) {
3556                                 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3557                                 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3558                         }
3559                         break;
3560                 case OP_TLS_GET:
3561 #ifdef HAVE_AEABI_READ_TP
3562                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3563                                                                  (gpointer)"__aeabi_read_tp");
3564                         code = emit_call_seq (cfg, code);
3565
3566                         ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3567 #else
3568                         g_assert_not_reached ();
3569 #endif
3570                         break;
3571                 /*case OP_BIGMUL:
3572                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3573                         ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3574                         break;
3575                 case OP_BIGMUL_UN:
3576                         ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3577                         ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3578                         break;*/
3579                 case OP_STOREI1_MEMBASE_IMM:
3580                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3581                         g_assert (arm_is_imm12 (ins->inst_offset));
3582                         ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3583                         break;
3584                 case OP_STOREI2_MEMBASE_IMM:
3585                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3586                         g_assert (arm_is_imm8 (ins->inst_offset));
3587                         ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3588                         break;
3589                 case OP_STORE_MEMBASE_IMM:
3590                 case OP_STOREI4_MEMBASE_IMM:
3591                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3592                         g_assert (arm_is_imm12 (ins->inst_offset));
3593                         ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3594                         break;
3595                 case OP_STOREI1_MEMBASE_REG:
3596                         g_assert (arm_is_imm12 (ins->inst_offset));
3597                         ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3598                         break;
3599                 case OP_STOREI2_MEMBASE_REG:
3600                         g_assert (arm_is_imm8 (ins->inst_offset));
3601                         ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3602                         break;
3603                 case OP_STORE_MEMBASE_REG:
3604                 case OP_STOREI4_MEMBASE_REG:
3605                         /* this case is special, since it happens for spill code after lowering has been called */
3606                         if (arm_is_imm12 (ins->inst_offset)) {
3607                                 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3608                         } else {
3609                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3610                                 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3611                         }
3612                         break;
3613                 case OP_STOREI1_MEMINDEX:
3614                         ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3615                         break;
3616                 case OP_STOREI2_MEMINDEX:
3617                         ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3618                         break;
3619                 case OP_STORE_MEMINDEX:
3620                 case OP_STOREI4_MEMINDEX:
3621                         ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3622                         break;
3623                 case OP_LOADU4_MEM:
3624                         g_assert_not_reached ();
3625                         break;
3626                 case OP_LOAD_MEMINDEX:
3627                 case OP_LOADI4_MEMINDEX:
3628                 case OP_LOADU4_MEMINDEX:
3629                         ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3630                         break;
3631                 case OP_LOADI1_MEMINDEX:
3632                         ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3633                         break;
3634                 case OP_LOADU1_MEMINDEX:
3635                         ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3636                         break;
3637                 case OP_LOADI2_MEMINDEX:
3638                         ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3639                         break;
3640                 case OP_LOADU2_MEMINDEX:
3641                         ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3642                         break;
3643                 case OP_LOAD_MEMBASE:
3644                 case OP_LOADI4_MEMBASE:
3645                 case OP_LOADU4_MEMBASE:
3646                         /* this case is special, since it happens for spill code after lowering has been called */
3647                         if (arm_is_imm12 (ins->inst_offset)) {
3648                                 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3649                         } else {
3650                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3651                                 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3652                         }
3653                         break;
3654                 case OP_LOADI1_MEMBASE:
3655                         g_assert (arm_is_imm8 (ins->inst_offset));
3656                         ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3657                         break;
3658                 case OP_LOADU1_MEMBASE:
3659                         g_assert (arm_is_imm12 (ins->inst_offset));
3660                         ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3661                         break;
3662                 case OP_LOADU2_MEMBASE:
3663                         g_assert (arm_is_imm8 (ins->inst_offset));
3664                         ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3665                         break;
3666                 case OP_LOADI2_MEMBASE:
3667                         g_assert (arm_is_imm8 (ins->inst_offset));
3668                         ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3669                         break;
3670                 case OP_ICONV_TO_I1:
3671                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3672                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3673                         break;
3674                 case OP_ICONV_TO_I2:
3675                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3676                         ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3677                         break;
3678                 case OP_ICONV_TO_U1:
3679                         ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3680                         break;
3681                 case OP_ICONV_TO_U2:
3682                         ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3683                         ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3684                         break;
3685                 case OP_COMPARE:
3686                 case OP_ICOMPARE:
3687                         ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3688                         break;
3689                 case OP_COMPARE_IMM:
3690                 case OP_ICOMPARE_IMM:
3691                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3692                         g_assert (imm8 >= 0);
3693                         ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3694                         break;
3695                 case OP_BREAK:
3696                         /*
3697                          * gdb does not like encountering the hw breakpoint ins in the debugged code.
3698                          * So instead of emitting a trap, we emit a call a C function and place a
3699                          * breakpoint there.
3700                          */
3701                         //*(int*)code = 0xef9f0001;
3702                         //code += 4;
3703                         //ARM_DBRK (code);
3704                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3705                                                                  (gpointer)"mono_break");
3706                         code = emit_call_seq (cfg, code);
3707                         break;
3708                 case OP_RELAXED_NOP:
3709                         ARM_NOP (code);
3710                         break;
3711                 case OP_NOP:
3712                 case OP_DUMMY_USE:
3713                 case OP_DUMMY_STORE:
3714                 case OP_NOT_REACHED:
3715                 case OP_NOT_NULL:
3716                         break;
3717                 case OP_SEQ_POINT: {
3718                         int i;
3719                         MonoInst *info_var = cfg->arch.seq_point_info_var;
3720                         MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3721                         MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3722                         MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3723                         MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3724                         MonoInst *var;
3725                         int dreg = ARMREG_LR;
3726
3727                         if (cfg->soft_breakpoints) {
3728                                 g_assert (!cfg->compile_aot);
3729                         }
3730
3731                         /*
3732                          * For AOT, we use one got slot per method, which will point to a
3733                          * SeqPointInfo structure, containing all the information required
3734                          * by the code below.
3735                          */
3736                         if (cfg->compile_aot) {
3737                                 g_assert (info_var);
3738                                 g_assert (info_var->opcode == OP_REGOFFSET);
3739                                 g_assert (arm_is_imm12 (info_var->inst_offset));
3740                         }
3741
3742                         if (!cfg->soft_breakpoints) {
3743                                 /*
3744                                  * Read from the single stepping trigger page. This will cause a
3745                                  * SIGSEGV when single stepping is enabled.
3746                                  * We do this _before_ the breakpoint, so single stepping after
3747                                  * a breakpoint is hit will step to the next IL offset.
3748                                  */
3749                                 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3750                         }
3751
3752                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3753                                 if (cfg->soft_breakpoints) {
3754                                         /* Load the address of the sequence point trigger variable. */
3755                                         var = ss_read_var;
3756                                         g_assert (var);
3757                                         g_assert (var->opcode == OP_REGOFFSET);
3758                                         g_assert (arm_is_imm12 (var->inst_offset));
3759                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3760
3761                                         /* Read the value and check whether it is non-zero. */
3762                                         ARM_LDR_IMM (code, dreg, dreg, 0);
3763                                         ARM_CMP_REG_IMM (code, dreg, 0, 0);
3764
3765                                         /* Load the address of the sequence point method. */
3766                                         var = ss_method_var;
3767                                         g_assert (var);
3768                                         g_assert (var->opcode == OP_REGOFFSET);
3769                                         g_assert (arm_is_imm12 (var->inst_offset));
3770                                         ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3771
3772                                         /* Call it conditionally. */
3773                                         ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3774                                 } else {
3775                                         if (cfg->compile_aot) {
3776                                                 /* Load the trigger page addr from the variable initialized in the prolog */
3777                                                 var = ss_trigger_page_var;
3778                                                 g_assert (var);
3779                                                 g_assert (var->opcode == OP_REGOFFSET);
3780                                                 g_assert (arm_is_imm12 (var->inst_offset));
3781                                                 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3782                                         } else {
3783                                                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3784                                                 ARM_B (code, 0);
3785                                                 *(int*)code = (int)ss_trigger_page;
3786                                                 code += 4;
3787                                         }
3788                                         ARM_LDR_IMM (code, dreg, dreg, 0);
3789                                 }
3790                         }
3791
3792                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3793
3794                         if (cfg->soft_breakpoints) {
3795                                 /* Load the address of the breakpoint method into ip. */
3796                                 var = bp_method_var;
3797                                 g_assert (var);
3798                                 g_assert (var->opcode == OP_REGOFFSET);
3799                                 g_assert (arm_is_imm12 (var->inst_offset));
3800                                 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3801
3802                                 /*
3803                                  * A placeholder for a possible breakpoint inserted by
3804                                  * mono_arch_set_breakpoint ().
3805                                  */
3806                                 ARM_NOP (code);
3807                         } else if (cfg->compile_aot) {
3808                                 guint32 offset = code - cfg->native_code;
3809                                 guint32 val;
3810
3811                                 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3812                                 /* Add the offset */
3813                                 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3814                                 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3815                                 if (val & 0xFF00)
3816                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3817                                 if (val & 0xFF0000)
3818                                         ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3819                                 g_assert (!(val & 0xFF000000));
3820                                 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3821                                 ARM_LDR_IMM (code, dreg, dreg, 0);
3822
3823                                 /* What is faster, a branch or a load ? */
3824                                 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3825                                 /* The breakpoint instruction */
3826                                 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3827                         } else {
3828                                 /*
3829                                  * A placeholder for a possible breakpoint inserted by
3830                                  * mono_arch_set_breakpoint ().
3831                                  */
3832                                 for (i = 0; i < 4; ++i)
3833                                         ARM_NOP (code);
3834                         }
3835                         break;
3836                 }
3837                 case OP_ADDCC:
3838                 case OP_IADDCC:
3839                         ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3840                         break;
3841                 case OP_IADD:
3842                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3843                         break;
3844                 case OP_ADC:
3845                 case OP_IADC:
3846                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3847                         break;
3848                 case OP_ADDCC_IMM:
3849                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3850                         g_assert (imm8 >= 0);
3851                         ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3852                         break;
3853                 case OP_ADD_IMM:
3854                 case OP_IADD_IMM:
3855                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3856                         g_assert (imm8 >= 0);
3857                         ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3858                         break;
3859                 case OP_ADC_IMM:
3860                 case OP_IADC_IMM:
3861                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3862                         g_assert (imm8 >= 0);
3863                         ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3864                         break;
3865                 case OP_IADD_OVF:
3866                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3867                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3868                         break;
3869                 case OP_IADD_OVF_UN:
3870                         ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3871                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3872                         break;
3873                 case OP_ISUB_OVF:
3874                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3875                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3876                         break;
3877                 case OP_ISUB_OVF_UN:
3878                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3879                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3880                         break;
3881                 case OP_ADD_OVF_CARRY:
3882                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3883                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3884                         break;
3885                 case OP_ADD_OVF_UN_CARRY:
3886                         ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3887                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3888                         break;
3889                 case OP_SUB_OVF_CARRY:
3890                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3891                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3892                         break;
3893                 case OP_SUB_OVF_UN_CARRY:
3894                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3895                         //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3896                         break;
3897                 case OP_SUBCC:
3898                 case OP_ISUBCC:
3899                         ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3900                         break;
3901                 case OP_SUBCC_IMM:
3902                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3903                         g_assert (imm8 >= 0);
3904                         ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3905                         break;
3906                 case OP_ISUB:
3907                         ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3908                         break;
3909                 case OP_SBB:
3910                 case OP_ISBB:
3911                         ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3912                         break;
3913                 case OP_SUB_IMM:
3914                 case OP_ISUB_IMM:
3915                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3916                         g_assert (imm8 >= 0);
3917                         ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3918                         break;
3919                 case OP_SBB_IMM:
3920                 case OP_ISBB_IMM:
3921                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3922                         g_assert (imm8 >= 0);
3923                         ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3924                         break;
3925                 case OP_ARM_RSBS_IMM:
3926                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3927                         g_assert (imm8 >= 0);
3928                         ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3929                         break;
3930                 case OP_ARM_RSC_IMM:
3931                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3932                         g_assert (imm8 >= 0);
3933                         ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3934                         break;
3935                 case OP_IAND:
3936                         ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3937                         break;
3938                 case OP_AND_IMM:
3939                 case OP_IAND_IMM:
3940                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3941                         g_assert (imm8 >= 0);
3942                         ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3943                         break;
3944                 case OP_IDIV:
3945                 case OP_IDIV_UN:
3946                 case OP_DIV_IMM:
3947                 case OP_IREM:
3948                 case OP_IREM_UN:
3949                 case OP_REM_IMM:
3950                         /* crappy ARM arch doesn't have a DIV instruction */
3951                         g_assert_not_reached ();
3952                 case OP_IOR:
3953                         ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3954                         break;
3955                 case OP_OR_IMM:
3956                 case OP_IOR_IMM:
3957                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3958                         g_assert (imm8 >= 0);
3959                         ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3960                         break;
3961                 case OP_IXOR:
3962                         ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3963                         break;
3964                 case OP_XOR_IMM:
3965                 case OP_IXOR_IMM:
3966                         imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3967                         g_assert (imm8 >= 0);
3968                         ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3969                         break;
3970                 case OP_ISHL:
3971                         ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3972                         break;
3973                 case OP_SHL_IMM:
3974                 case OP_ISHL_IMM:
3975                         if (ins->inst_imm)
3976                                 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3977                         else if (ins->dreg != ins->sreg1)
3978                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3979                         break;
3980                 case OP_ISHR:
3981                         ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3982                         break;
3983                 case OP_SHR_IMM:
3984                 case OP_ISHR_IMM:
3985                         if (ins->inst_imm)
3986                                 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3987                         else if (ins->dreg != ins->sreg1)
3988                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3989                         break;
3990                 case OP_SHR_UN_IMM:
3991                 case OP_ISHR_UN_IMM:
3992                         if (ins->inst_imm)
3993                                 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3994                         else if (ins->dreg != ins->sreg1)
3995                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3996                         break;
3997                 case OP_ISHR_UN:
3998                         ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3999                         break;
4000                 case OP_INOT:
4001                         ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4002                         break;
4003                 case OP_INEG:
4004                         ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4005                         break;
4006                 case OP_IMUL:
4007                         if (ins->dreg == ins->sreg2)
4008                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4009                         else
4010                                 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4011                         break;
4012                 case OP_MUL_IMM:
4013                         g_assert_not_reached ();
4014                         break;
4015                 case OP_IMUL_OVF:
4016                         /* FIXME: handle ovf/ sreg2 != dreg */
4017                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4018                         /* FIXME: MUL doesn't set the C/O flags on ARM */
4019                         break;
4020                 case OP_IMUL_OVF_UN:
4021                         /* FIXME: handle ovf/ sreg2 != dreg */
4022                         ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4023                         /* FIXME: MUL doesn't set the C/O flags on ARM */
4024                         break;
4025                 case OP_ICONST:
4026                         code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4027                         break;
4028                 case OP_AOTCONST:
4029                         /* Load the GOT offset */
4030                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4031                         ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4032                         ARM_B (code, 0);
4033                         *(gpointer*)code = NULL;
4034                         code += 4;
4035                         /* Load the value from the GOT */
4036                         ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4037                         break;
4038                 case OP_ICONV_TO_I4:
4039                 case OP_ICONV_TO_U4:
4040                 case OP_MOVE:
4041                         if (ins->dreg != ins->sreg1)
4042                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4043                         break;
4044                 case OP_SETLRET: {
4045                         int saved = ins->sreg2;
4046                         if (ins->sreg2 == ARM_LSW_REG) {
4047                                 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4048                                 saved = ARMREG_LR;
4049                         }
4050                         if (ins->sreg1 != ARM_LSW_REG)
4051                                 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4052                         if (saved != ARM_MSW_REG)
4053                                 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4054                         break;
4055                 }
4056                 case OP_FMOVE:
4057                         if (IS_FPA)
4058                                 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4059                         else if (IS_VFP)
4060                                 ARM_CPYD (code, ins->dreg, ins->sreg1);
4061                         break;
4062                 case OP_FCONV_TO_R4:
4063                         if (IS_FPA)
4064                                 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4065                         else if (IS_VFP) {
4066                                 ARM_CVTD (code, ins->dreg, ins->sreg1);
4067                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4068                         }
4069                         break;
4070                 case OP_JMP:
4071                         /*
4072                          * Keep in sync with mono_arch_emit_epilog
4073                          */
4074                         g_assert (!cfg->method->save_lmf);
4075
4076                         code = emit_load_volatile_arguments (cfg, code);
4077
4078                         code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4079                         if (iphone_abi) {
4080                                 if (cfg->used_int_regs)
4081                                         ARM_POP (code, cfg->used_int_regs);
4082                                 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4083                         } else {
4084                                 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4085                         }
4086                         mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4087                         if (cfg->compile_aot) {
4088                                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4089                                 ARM_B (code, 0);
4090                                 *(gpointer*)code = NULL;
4091                                 code += 4;
4092                                 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4093                         } else {
4094                                 ARM_B (code, 0);
4095                         }
4096                         break;
4097                 case OP_CHECK_THIS:
4098                         /* ensure ins->sreg1 is not NULL */
4099                         ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4100                         break;
4101                 case OP_ARGLIST: {
4102                         g_assert (cfg->sig_cookie < 128);
4103                         ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4104                         ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4105                         break;
4106                 }
4107                 case OP_FCALL:
4108                 case OP_LCALL:
4109                 case OP_VCALL:
4110                 case OP_VCALL2:
4111                 case OP_VOIDCALL:
4112                 case OP_CALL:
4113                         call = (MonoCallInst*)ins;
4114                         if (ins->flags & MONO_INST_HAS_METHOD)
4115                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4116                         else
4117                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4118                         code = emit_call_seq (cfg, code);
4119                         ins->flags |= MONO_INST_GC_CALLSITE;
4120                         ins->backend.pc_offset = code - cfg->native_code;
4121                         code = emit_move_return_value (cfg, ins, code);
4122                         break;
4123                 case OP_FCALL_REG:
4124                 case OP_LCALL_REG:
4125                 case OP_VCALL_REG:
4126                 case OP_VCALL2_REG:
4127                 case OP_VOIDCALL_REG:
4128                 case OP_CALL_REG:
4129                         code = emit_call_reg (code, ins->sreg1);
4130                         ins->flags |= MONO_INST_GC_CALLSITE;
4131                         ins->backend.pc_offset = code - cfg->native_code;
4132                         code = emit_move_return_value (cfg, ins, code);
4133                         break;
4134                 case OP_FCALL_MEMBASE:
4135                 case OP_LCALL_MEMBASE:
4136                 case OP_VCALL_MEMBASE:
4137                 case OP_VCALL2_MEMBASE:
4138                 case OP_VOIDCALL_MEMBASE:
4139                 case OP_CALL_MEMBASE:
4140                         g_assert (arm_is_imm12 (ins->inst_offset));
4141                         g_assert (ins->sreg1 != ARMREG_LR);
4142                         call = (MonoCallInst*)ins;
4143                         if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4144                                 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4145                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4146                                 /*
4147                                  * We can't embed the method in the code stream in PIC code, or
4148                                  * in gshared code.
4149                                  * Instead, we put it in V5 in code emitted by
4150                                  * mono_arch_emit_imt_argument (), and embed NULL here to
4151                                  * signal the IMT thunk that the value is in V5.
4152                                  */
4153                                 if (call->dynamic_imt_arg)
4154                                         *((gpointer*)code) = NULL;
4155                                 else
4156                                         *((gpointer*)code) = (gpointer)call->method;
4157                                 code += 4;
4158                         } else {
4159                                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4160                                 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4161                         }
4162                         ins->flags |= MONO_INST_GC_CALLSITE;
4163                         ins->backend.pc_offset = code - cfg->native_code;
4164                         code = emit_move_return_value (cfg, ins, code);
4165                         break;
4166                 case OP_LOCALLOC: {
4167                         /* keep alignment */
4168                         int alloca_waste = cfg->param_area;
4169                         alloca_waste += 7;
4170                         alloca_waste &= ~7;
4171                         /* round the size to 8 bytes */
4172                         ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4173                         ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4174                         if (alloca_waste)
4175                                 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4176                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4177                         /* memzero the area: dreg holds the size, sp is the pointer */
4178                         if (ins->flags & MONO_INST_INIT) {
4179                                 guint8 *start_loop, *branch_to_cond;
4180                                 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4181                                 branch_to_cond = code;
4182                                 ARM_B (code, 0);
4183                                 start_loop = code;
4184                                 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4185                                 arm_patch (branch_to_cond, code);
4186                                 /* decrement by 4 and set flags */
4187                                 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4188                                 ARM_B_COND (code, ARMCOND_GE, 0);
4189                                 arm_patch (code - 4, start_loop);
4190                         }
4191                         ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4192                         break;
4193                 }
4194                 case OP_DYN_CALL: {
4195                         int i;
4196                         MonoInst *var = cfg->dyn_call_var;
4197
4198                         g_assert (var->opcode == OP_REGOFFSET);
4199                         g_assert (arm_is_imm12 (var->inst_offset));
4200
4201                         /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4202                         ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4203                         /* ip = ftn */
4204                         ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4205
4206                         /* Save args buffer */
4207                         ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4208
4209                         /* Set stack slots using R0 as scratch reg */
4210                         /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4211                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4212                                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4213                                 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4214                         }
4215
4216                         /* Set argument registers */
4217                         for (i = 0; i < PARAM_REGS; ++i)
4218                                 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4219
4220                         /* Make the call */
4221                         ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4222                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4223
4224                         /* Save result */
4225                         ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4226                         ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4227                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4228                         break;
4229                 }
4230                 case OP_THROW: {
4231                         if (ins->sreg1 != ARMREG_R0)
4232                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4233                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4234                                              (gpointer)"mono_arch_throw_exception");
4235                         code = emit_call_seq (cfg, code);
4236                         break;
4237                 }
4238                 case OP_RETHROW: {
4239                         if (ins->sreg1 != ARMREG_R0)
4240                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4241                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4242                                              (gpointer)"mono_arch_rethrow_exception");
4243                         code = emit_call_seq (cfg, code);
4244                         break;
4245                 }
4246                 case OP_START_HANDLER: {
4247                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4248                         int i, rot_amount;
4249
4250                         /* Reserve a param area, see filter-stack.exe */
4251                         if (cfg->param_area) {
4252                                 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4253                                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4254                                 } else {
4255                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4256                                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4257                                 }
4258                         }
4259
4260                         if (arm_is_imm12 (spvar->inst_offset)) {
4261                                 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4262                         } else {
4263                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4264                                 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4265                         }
4266                         break;
4267                 }
4268                 case OP_ENDFILTER: {
4269                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4270                         int i, rot_amount;
4271
4272                         /* Free the param area */
4273                         if (cfg->param_area) {
4274                                 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4275                                         ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4276                                 } else {
4277                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4278                                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4279                                 }
4280                         }
4281
4282                         if (ins->sreg1 != ARMREG_R0)
4283                                 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4284                         if (arm_is_imm12 (spvar->inst_offset)) {
4285                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4286                         } else {
4287                                 g_assert (ARMREG_IP != spvar->inst_basereg);
4288                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4289                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4290                         }
4291                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4292                         break;
4293                 }
4294                 case OP_ENDFINALLY: {
4295                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4296                         int i, rot_amount;
4297
4298                         /* Free the param area */
4299                         if (cfg->param_area) {
4300                                 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4301                                         ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4302                                 } else {
4303                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4304                                         ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4305                                 }
4306                         }
4307
4308                         if (arm_is_imm12 (spvar->inst_offset)) {
4309                                 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4310                         } else {
4311                                 g_assert (ARMREG_IP != spvar->inst_basereg);
4312                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4313                                 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4314                         }
4315                         ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4316                         break;
4317                 }
4318                 case OP_CALL_HANDLER:
4319                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4320                         ARM_BL (code, 0);
4321                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4322                         break;
4323                 case OP_LABEL:
4324                         ins->inst_c0 = code - cfg->native_code;
4325                         break;
4326                 case OP_BR:
4327                         /*if (ins->inst_target_bb->native_offset) {
4328                                 ARM_B (code, 0);
4329                                 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4330                         } else*/ {
4331                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4332                                 ARM_B (code, 0);
4333                         }
4334                         break;
4335                 case OP_BR_REG:
4336                         ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4337                         break;
4338                 case OP_SWITCH:
4339                         /*
4340                          * In the normal case we have:
4341                          *      ldr pc, [pc, ins->sreg1 << 2]
4342                          *      nop
4343                          * If aot, we have:
4344                          *      ldr lr, [pc, ins->sreg1 << 2]
4345                          *      add pc, pc, lr
4346                          * After follows the data.
4347                          * FIXME: add aot support.
4348                          */
4349                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4350                         max_len += 4 * GPOINTER_TO_INT (ins->klass);
4351                         if (offset + max_len > (cfg->code_size - 16)) {
4352                                 cfg->code_size += max_len;
4353                                 cfg->code_size *= 2;
4354                                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4355                                 code = cfg->native_code + offset;
4356                         }
4357                         ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4358                         ARM_NOP (code);
4359                         code += 4 * GPOINTER_TO_INT (ins->klass);
4360                         break;
4361                 case OP_CEQ:
4362                 case OP_ICEQ:
4363                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4364                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4365                         break;
4366                 case OP_CLT:
4367                 case OP_ICLT:
4368                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4369                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4370                         break;
4371                 case OP_CLT_UN:
4372                 case OP_ICLT_UN:
4373                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4374                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4375                         break;
4376                 case OP_CGT:
4377                 case OP_ICGT:
4378                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4379                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4380                         break;
4381                 case OP_CGT_UN:
4382                 case OP_ICGT_UN:
4383                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4384                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4385                         break;
4386                 case OP_COND_EXC_EQ:
4387                 case OP_COND_EXC_NE_UN:
4388                 case OP_COND_EXC_LT:
4389                 case OP_COND_EXC_LT_UN:
4390                 case OP_COND_EXC_GT:
4391                 case OP_COND_EXC_GT_UN:
4392                 case OP_COND_EXC_GE:
4393                 case OP_COND_EXC_GE_UN:
4394                 case OP_COND_EXC_LE:
4395                 case OP_COND_EXC_LE_UN:
4396                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4397                         break;
4398                 case OP_COND_EXC_IEQ:
4399                 case OP_COND_EXC_INE_UN:
4400                 case OP_COND_EXC_ILT:
4401                 case OP_COND_EXC_ILT_UN:
4402                 case OP_COND_EXC_IGT:
4403                 case OP_COND_EXC_IGT_UN:
4404                 case OP_COND_EXC_IGE:
4405                 case OP_COND_EXC_IGE_UN:
4406                 case OP_COND_EXC_ILE:
4407                 case OP_COND_EXC_ILE_UN:
4408                         EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4409                         break;
4410                 case OP_COND_EXC_C:
4411                 case OP_COND_EXC_IC:
4412                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4413                         break;
4414                 case OP_COND_EXC_OV:
4415                 case OP_COND_EXC_IOV:
4416                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4417                         break;
4418                 case OP_COND_EXC_NC:
4419                 case OP_COND_EXC_INC:
4420                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4421                         break;
4422                 case OP_COND_EXC_NO:
4423                 case OP_COND_EXC_INO:
4424                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4425                         break;
4426                 case OP_IBEQ:
4427                 case OP_IBNE_UN:
4428                 case OP_IBLT:
4429                 case OP_IBLT_UN:
4430                 case OP_IBGT:
4431                 case OP_IBGT_UN:
4432                 case OP_IBGE:
4433                 case OP_IBGE_UN:
4434                 case OP_IBLE:
4435                 case OP_IBLE_UN:
4436                         EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4437                         break;
4438
4439                 /* floating point opcodes */
4440 #ifdef ARM_FPU_FPA
4441                 case OP_R8CONST:
4442                         if (cfg->compile_aot) {
4443                                 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4444                                 ARM_B (code, 1);
4445                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4446                                 code += 4;
4447                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4448                                 code += 4;
4449                         } else {
4450                                 /* FIXME: we can optimize the imm load by dealing with part of
4451                                  * the displacement in LDFD (aligning to 512).
4452                                  */
4453                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4454                                 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4455                         }
4456                         break;
4457                 case OP_R4CONST:
4458                         if (cfg->compile_aot) {
4459                                 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4460                                 ARM_B (code, 0);
4461                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4462                                 code += 4;
4463                         } else {
4464                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4465                                 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4466                         }
4467                         break;
4468                 case OP_STORER8_MEMBASE_REG:
4469                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4470                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4471                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4472                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4473                                 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4474                         } else {
4475                                 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4476                         }
4477                         break;
4478                 case OP_LOADR8_MEMBASE:
4479                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4480                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4481                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4482                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4483                                 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4484                         } else {
4485                                 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4486                         }
4487                         break;
4488                 case OP_STORER4_MEMBASE_REG:
4489                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4490                         ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4491                         break;
4492                 case OP_LOADR4_MEMBASE:
4493                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4494                         ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4495                         break;
4496                 case OP_ICONV_TO_R_UN: {
4497                         int tmpreg;
4498                         tmpreg = ins->dreg == 0? 1: 0;
4499                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4500                         ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4501                         ARM_B_COND (code, ARMCOND_GE, 8);
4502                         /* save the temp register */
4503                         ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4504                         ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4505                         ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4506                         ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4507                         ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4508                         ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4509                         /* skip the constant pool */
4510                         ARM_B (code, 8);
4511                         code += 4;
4512                         *(int*)code = 0x41f00000;
4513                         code += 4;
4514                         *(int*)code = 0;
4515                         code += 4;
4516                         /* FIXME: adjust:
4517                          * ldfltd  ftemp, [pc, #8] 0x41f00000 0x00000000
4518                          * adfltd  fdest, fdest, ftemp
4519                          */
4520                         break;
4521                 }
4522                 case OP_ICONV_TO_R4:
4523                         ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4524                         break;
4525                 case OP_ICONV_TO_R8:
4526                         ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4527                         break;
4528
4529 #elif defined(ARM_FPU_VFP)
4530
4531                 case OP_R8CONST:
4532                         if (cfg->compile_aot) {
4533                                 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4534                                 ARM_B (code, 1);
4535                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4536                                 code += 4;
4537                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4538                                 code += 4;
4539                         } else {
4540                                 /* FIXME: we can optimize the imm load by dealing with part of
4541                                  * the displacement in LDFD (aligning to 512).
4542                                  */
4543                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4544                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4545                         }
4546                         break;
4547                 case OP_R4CONST:
4548                         if (cfg->compile_aot) {
4549                                 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4550                                 ARM_B (code, 0);
4551                                 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4552                                 code += 4;
4553                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4554                         } else {
4555                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4556                                 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4557                                 ARM_CVTS (code, ins->dreg, ins->dreg);
4558                         }
4559                         break;
4560                 case OP_STORER8_MEMBASE_REG:
4561                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4562                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4563                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4564                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4565                                 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4566                         } else {
4567                                 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4568                         }
4569                         break;
4570                 case OP_LOADR8_MEMBASE:
4571                         /* This is generated by the local regalloc pass which runs after the lowering pass */
4572                         if (!arm_is_fpimm8 (ins->inst_offset)) {
4573                                 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4574                                 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4575                                 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4576                         } else {
4577                                 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4578                         }
4579                         break;
4580                 case OP_STORER4_MEMBASE_REG:
4581                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4582                         ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4583                         ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4584                         break;
4585                 case OP_LOADR4_MEMBASE:
4586                         g_assert (arm_is_fpimm8 (ins->inst_offset));
4587                         ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4588                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4589                         break;
4590                 case OP_ICONV_TO_R_UN: {
4591                         g_assert_not_reached ();
4592                         break;
4593                 }
4594                 case OP_ICONV_TO_R4:
4595                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4596                         ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4597                         ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4598                         break;
4599                 case OP_ICONV_TO_R8:
4600                         ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4601                         ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4602                         break;
4603
4604                 case OP_SETFRET:
4605                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4606                                 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4607                                 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4608                         } else {
4609                                 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4610                         }
4611                         break;
4612
4613 #endif
4614
4615                 case OP_FCONV_TO_I1:
4616                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4617                         break;
4618                 case OP_FCONV_TO_U1:
4619                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4620                         break;
4621                 case OP_FCONV_TO_I2:
4622                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4623                         break;
4624                 case OP_FCONV_TO_U2:
4625                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4626                         break;
4627                 case OP_FCONV_TO_I4:
4628                 case OP_FCONV_TO_I:
4629                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4630                         break;
4631                 case OP_FCONV_TO_U4:
4632                 case OP_FCONV_TO_U:
4633                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4634                         break;
4635                 case OP_FCONV_TO_I8:
4636                 case OP_FCONV_TO_U8:
4637                         g_assert_not_reached ();
4638                         /* Implemented as helper calls */
4639                         break;
4640                 case OP_LCONV_TO_R_UN:
4641                         g_assert_not_reached ();
4642                         /* Implemented as helper calls */
4643                         break;
4644                 case OP_LCONV_TO_OVF_I4_2: {
4645                         guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4646                         /*
4647                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4648                          */
4649
4650                         ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4651                         high_bit_not_set = code;
4652                         ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4653
4654                         ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4655                         valid_negative = code;
4656                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4657                         invalid_negative = code;
4658                         ARM_B_COND (code, ARMCOND_AL, 0);
4659
4660                         arm_patch (high_bit_not_set, code);
4661
4662                         ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4663                         valid_positive = code;
4664                         ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4665
4666                         arm_patch (invalid_negative, code);
4667                         EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4668
4669                         arm_patch (valid_negative, code);
4670                         arm_patch (valid_positive, code);
4671
4672                         if (ins->dreg != ins->sreg1)
4673                                 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4674                         break;
4675                 }
4676 #ifdef ARM_FPU_FPA
4677                 case OP_FADD:
4678                         ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4679                         break;
4680                 case OP_FSUB:
4681                         ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4682                         break;
4683                 case OP_FMUL:
4684                         ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4685                         break;
4686                 case OP_FDIV:
4687                         ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4688                         break;
4689                 case OP_FNEG:
4690                         ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4691                         break;
4692 #elif defined(ARM_FPU_VFP)
4693                 case OP_FADD:
4694                         ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4695                         break;
4696                 case OP_FSUB:
4697                         ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4698                         break;
4699                 case OP_FMUL:
4700                         ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4701                         break;
4702                 case OP_FDIV:
4703                         ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4704                         break;
4705                 case OP_FNEG:
4706                         ARM_NEGD (code, ins->dreg, ins->sreg1);
4707                         break;
4708 #endif
4709                 case OP_FREM:
4710                         /* emulated */
4711                         g_assert_not_reached ();
4712                         break;
4713                 case OP_FCOMPARE:
4714                         if (IS_FPA) {
4715                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4716                         } else if (IS_VFP) {
4717                                 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4718                                 ARM_FMSTAT (code);
4719                         }
4720                         break;
4721                 case OP_FCEQ:
4722                         if (IS_FPA) {
4723                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4724                         } else if (IS_VFP) {
4725                                 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4726                                 ARM_FMSTAT (code);
4727                         }
4728                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4729                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4730                         break;
4731                 case OP_FCLT:
4732                         if (IS_FPA) {
4733                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4734                         } else {
4735                                 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4736                                 ARM_FMSTAT (code);
4737                         }
4738                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4739                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4740                         break;
4741                 case OP_FCLT_UN:
4742                         if (IS_FPA) {
4743                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4744                         } else if (IS_VFP) {
4745                                 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4746                                 ARM_FMSTAT (code);
4747                         }
4748                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4749                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4750                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4751                         break;
4752                 case OP_FCGT:
4753                         /* swapped */
4754                         if (IS_FPA) {
4755                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4756                         } else if (IS_VFP) {
4757                                 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4758                                 ARM_FMSTAT (code);
4759                         }
4760                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4761                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4762                         break;
4763                 case OP_FCGT_UN:
4764                         /* swapped */
4765                         if (IS_FPA) {
4766                                 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4767                         } else if (IS_VFP) {
4768                                 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4769                                 ARM_FMSTAT (code);
4770                         }
4771                         ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4772                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4773                         ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4774                         break;
4775                 /* ARM FPA flags table:
4776                  * N        Less than               ARMCOND_MI
4777                  * Z        Equal                   ARMCOND_EQ
4778                  * C        Greater Than or Equal   ARMCOND_CS
4779                  * V        Unordered               ARMCOND_VS
4780                  */
4781                 case OP_FBEQ:
4782                         EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4783                         break;
4784                 case OP_FBNE_UN:
4785                         EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4786                         break;
4787                 case OP_FBLT:
4788                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4789                         break;
4790                 case OP_FBLT_UN:
4791                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4792                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4793                         break;
4794                 case OP_FBGT:
4795                 case OP_FBGT_UN:
4796                 case OP_FBLE:
4797                 case OP_FBLE_UN:
4798                         g_assert_not_reached ();
4799                         break;
4800                 case OP_FBGE:
4801                         if (IS_VFP) {
4802                                 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4803                         } else {
4804                                 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4805                                 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4806                                 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4807                         }
4808                         break;
4809                 case OP_FBGE_UN:
4810                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4811                         EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4812                         break;
4813
4814                 case OP_CKFINITE: {
4815                         if (IS_FPA) {
4816                                 if (ins->dreg != ins->sreg1)
4817                                         ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4818                         } else if (IS_VFP) {
4819                                 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4820                                 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4821                                 ARM_B (code, 1);
4822                                 *(guint32*)code = 0xffffffff;
4823                                 code += 4;
4824                                 *(guint32*)code = 0x7fefffff;
4825                                 code += 4;
4826                                 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4827                                 ARM_FMSTAT (code);
4828                                 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4829                                 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4830                                 ARM_FMSTAT (code);
4831                                 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4832                                 ARM_CPYD (code, ins->dreg, ins->sreg1);
4833                         }
4834                         break;
4835                 }
4836
4837                 case OP_GC_LIVENESS_DEF:
4838                 case OP_GC_LIVENESS_USE:
4839                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4840                         ins->backend.pc_offset = code - cfg->native_code;
4841                         break;
4842                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4843                         ins->backend.pc_offset = code - cfg->native_code;
4844                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4845                         break;
4846
4847                 default:
4848                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4849                         g_assert_not_reached ();
4850                 }
4851
4852                 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4853                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4854                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4855                         g_assert_not_reached ();
4856                 }
4857
4858                 cpos += max_len;
4859
4860                 last_ins = ins;
4861                 last_offset = offset;
4862         }
4863
4864         cfg->code_len = code - cfg->native_code;
4865 }
4866
4867 #endif /* DISABLE_JIT */
4868
4869 #ifdef HAVE_AEABI_READ_TP
4870 void __aeabi_read_tp (void);
4871 #endif
4872
4873 void
4874 mono_arch_register_lowlevel_calls (void)
4875 {
4876         /* The signature doesn't matter */
4877         mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4878         mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4879
4880 #ifndef MONO_CROSS_COMPILE
4881 #ifdef HAVE_AEABI_READ_TP
4882         mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4883 #endif
4884 #endif
4885 }
4886
4887 #define patch_lis_ori(ip,val) do {\
4888                 guint16 *__lis_ori = (guint16*)(ip);    \
4889                 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff;      \
4890                 __lis_ori [3] = ((guint32)(val)) & 0xffff;      \
4891         } while (0)
4892
4893 void
4894 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4895 {
4896         MonoJumpInfo *patch_info;
4897         gboolean compile_aot = !run_cctors;
4898
4899         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4900                 unsigned char *ip = patch_info->ip.i + code;
4901                 const unsigned char *target;
4902
4903                 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4904                         gpointer *jt = (gpointer*)(ip + 8);
4905                         int i;
4906                         /* jt is the inlined jump table, 2 instructions after ip
4907                          * In the normal case we store the absolute addresses,
4908                          * otherwise the displacements.
4909                          */
4910                         for (i = 0; i < patch_info->data.table->table_size; i++)
4911                                 jt [i] = code + (int)patch_info->data.table->table [i];
4912                         continue;
4913                 }
4914                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4915
4916                 if (compile_aot) {
4917                         switch (patch_info->type) {
4918                         case MONO_PATCH_INFO_BB:
4919                         case MONO_PATCH_INFO_LABEL:
4920                                 break;
4921                         default:
4922                                 /* No need to patch these */
4923                                 continue;
4924                         }
4925                 }
4926
4927                 switch (patch_info->type) {
4928                 case MONO_PATCH_INFO_IP:
4929                         g_assert_not_reached ();
4930                         patch_lis_ori (ip, ip);
4931                         continue;
4932                 case MONO_PATCH_INFO_METHOD_REL:
4933                         g_assert_not_reached ();
4934                         *((gpointer *)(ip)) = code + patch_info->data.offset;
4935                         continue;
4936                 case MONO_PATCH_INFO_METHODCONST:
4937                 case MONO_PATCH_INFO_CLASS:
4938                 case MONO_PATCH_INFO_IMAGE:
4939                 case MONO_PATCH_INFO_FIELD:
4940                 case MONO_PATCH_INFO_VTABLE:
4941                 case MONO_PATCH_INFO_IID:
4942                 case MONO_PATCH_INFO_SFLDA:
4943                 case MONO_PATCH_INFO_LDSTR:
4944                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4945                 case MONO_PATCH_INFO_LDTOKEN:
4946                         g_assert_not_reached ();
4947                         /* from OP_AOTCONST : lis + ori */
4948                         patch_lis_ori (ip, target);
4949                         continue;
4950                 case MONO_PATCH_INFO_R4:
4951                 case MONO_PATCH_INFO_R8:
4952                         g_assert_not_reached ();
4953                         *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4954                         continue;
4955                 case MONO_PATCH_INFO_EXC_NAME:
4956                         g_assert_not_reached ();
4957                         *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4958                         continue;
4959                 case MONO_PATCH_INFO_NONE:
4960                 case MONO_PATCH_INFO_BB_OVF:
4961                 case MONO_PATCH_INFO_EXC_OVF:
4962                         /* everything is dealt with at epilog output time */
4963                         continue;
4964                 default:
4965                         break;
4966                 }
4967                 arm_patch_general (domain, ip, target, dyn_code_mp);
4968         }
4969 }
4970
4971 #ifndef DISABLE_JIT
4972
4973 /*
4974  * Stack frame layout:
4975  *
4976  *   ------------------- fp
4977  *      MonoLMF structure or saved registers
4978  *   -------------------
4979  *      locals
4980  *   -------------------
4981  *      spilled regs
4982  *   -------------------
4983  *      optional 8 bytes for tracing
4984  *   -------------------
4985  *      param area             size is cfg->param_area
4986  *   ------------------- sp
4987  */
4988 guint8 *
4989 mono_arch_emit_prolog (MonoCompile *cfg)
4990 {
4991         MonoMethod *method = cfg->method;
4992         MonoBasicBlock *bb;
4993         MonoMethodSignature *sig;
4994         MonoInst *inst;
4995         int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
4996         guint8 *code;
4997         CallInfo *cinfo;
4998         int tracing = 0;
4999         int lmf_offset = 0;
5000         int prev_sp_offset, reg_offset;
5001
5002         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5003                 tracing = 1;
5004
5005         sig = mono_method_signature (method);
5006         cfg->code_size = 256 + sig->param_count * 64;
5007         code = cfg->native_code = g_malloc (cfg->code_size);
5008
5009         mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5010
5011         alloc_size = cfg->stack_offset;
5012         pos = 0;
5013         prev_sp_offset = 0;
5014
5015         if (!method->save_lmf) {
5016                 if (iphone_abi) {
5017                         /*
5018                          * The iphone uses R7 as the frame pointer, and it points at the saved
5019                          * r7+lr:
5020                          *         <lr>
5021                          * r7 ->   <r7>
5022                          *         <rest of frame>
5023                          * We can't use r7 as a frame pointer since it points into the middle of
5024                          * the frame, so we keep using our own frame pointer.
5025                          * FIXME: Optimize this.
5026                          */
5027                         g_assert (darwin);
5028                         ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5029                         ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5030                         prev_sp_offset += 8; /* r7 and lr */
5031                         mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5032                         mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5033
5034                         /* No need to push LR again */
5035                         if (cfg->used_int_regs)
5036                                 ARM_PUSH (code, cfg->used_int_regs);
5037                 } else {
5038                         ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5039                         prev_sp_offset += 4;
5040                 }
5041                 for (i = 0; i < 16; ++i) {
5042                         if (cfg->used_int_regs & (1 << i))
5043                                 prev_sp_offset += 4;
5044                 }
5045                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5046                 reg_offset = 0;
5047                 for (i = 0; i < 16; ++i) {
5048                         if ((cfg->used_int_regs & (1 << i))) {
5049                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5050                                 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5051                                 reg_offset += 4;
5052                         }
5053                 }
5054                 if (iphone_abi) {
5055                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5056                         mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5057                 } else {
5058                         mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5059                         mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5060                 }
5061         } else {
5062                 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5063                 ARM_PUSH (code, 0x5ff0);
5064                 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5065                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5066                 reg_offset = 0;
5067                 for (i = 0; i < 16; ++i) {
5068                         if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5069                                 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5070                                 reg_offset += 4;
5071                         }
5072                 }
5073                 pos += sizeof (MonoLMF) - prev_sp_offset;
5074                 lmf_offset = pos;
5075         }
5076         alloc_size += pos;
5077         orig_alloc_size = alloc_size;
5078         // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5079         if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5080                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5081                 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5082         }
5083
5084         /* the stack used in the pushed regs */
5085         if (prev_sp_offset & 4)
5086                 alloc_size += 4;
5087         cfg->stack_usage = alloc_size;
5088         if (alloc_size) {
5089                 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5090                         ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5091                 } else {
5092                         code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5093                         ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5094                 }
5095                 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5096         }
5097         if (cfg->frame_reg != ARMREG_SP) {
5098                 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5099                 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5100         }
5101         //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5102         prev_sp_offset += alloc_size;
5103
5104         for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5105                 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5106
5107         /* compute max_offset in order to use short forward jumps
5108          * we could skip do it on arm because the immediate displacement
5109          * for jumps is large enough, it may be useful later for constant pools
5110          */
5111         max_offset = 0;
5112         for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5113                 MonoInst *ins = bb->code;
5114                 bb->max_offset = max_offset;
5115
5116                 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5117                         max_offset += 6;
5118
5119                 MONO_BB_FOR_EACH_INS (bb, ins)
5120                         max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5121         }
5122
5123         /* store runtime generic context */
5124         if (cfg->rgctx_var) {
5125                 MonoInst *ins = cfg->rgctx_var;
5126
5127                 g_assert (ins->opcode == OP_REGOFFSET);
5128
5129                 if (arm_is_imm12 (ins->inst_offset)) {
5130                         ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5131                 } else {
5132                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5133                         ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5134                 }
5135         }
5136
5137         /* load arguments allocated to register from the stack */
5138         pos = 0;
5139
5140         cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5141
5142         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5143                 ArgInfo *ainfo = &cinfo->ret;
5144                 inst = cfg->vret_addr;
5145                 g_assert (arm_is_imm12 (inst->inst_offset));
5146                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5147         }
5148
5149         if (sig->call_convention == MONO_CALL_VARARG) {
5150                 ArgInfo *cookie = &cinfo->sig_cookie;
5151
5152                 /* Save the sig cookie address */
5153                 g_assert (cookie->storage == RegTypeBase);
5154
5155                 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5156                 g_assert (arm_is_imm12 (cfg->sig_cookie));
5157                 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5158                 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5159         }
5160
5161         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5162                 ArgInfo *ainfo = cinfo->args + i;
5163                 inst = cfg->args [pos];
5164
5165                 if (cfg->verbose_level > 2)
5166                         g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5167                 if (inst->opcode == OP_REGVAR) {
5168                         if (ainfo->storage == RegTypeGeneral)
5169                                 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5170                         else if (ainfo->storage == RegTypeFP) {
5171                                 g_assert_not_reached ();
5172                         } else if (ainfo->storage == RegTypeBase) {
5173                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5174                                         ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5175                                 } else {
5176                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5177                                         ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5178                                 }
5179                         } else
5180                                 g_assert_not_reached ();
5181
5182                         if (cfg->verbose_level > 2)
5183                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5184                 } else {
5185                         /* the argument should be put on the stack: FIXME handle size != word  */
5186                         if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5187                                 switch (ainfo->size) {
5188                                 case 1:
5189                                         if (arm_is_imm12 (inst->inst_offset))
5190                                                 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5191                                         else {
5192                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5193                                                 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5194                                         }
5195                                         break;
5196                                 case 2:
5197                                         if (arm_is_imm8 (inst->inst_offset)) {
5198                                                 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5199                                         } else {
5200                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5201                                                 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5202                                         }
5203                                         break;
5204                                 case 8:
5205                                         g_assert (arm_is_imm12 (inst->inst_offset));
5206                                         ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5207                                         g_assert (arm_is_imm12 (inst->inst_offset + 4));
5208                                         ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5209                                         break;
5210                                 default:
5211                                         if (arm_is_imm12 (inst->inst_offset)) {
5212                                                 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5213                                         } else {
5214                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5215                                                 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5216                                         }
5217                                         break;
5218                                 }
5219                         } else if (ainfo->storage == RegTypeBaseGen) {
5220                                 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5221                                 g_assert (arm_is_imm12 (inst->inst_offset));
5222                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5223                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5224                                 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5225                         } else if (ainfo->storage == RegTypeBase) {
5226                                 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5227                                         ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5228                                 } else {
5229                                         code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5230                                         ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5231                                 }
5232
5233                                 switch (ainfo->size) {
5234                                 case 1:
5235                                         if (arm_is_imm8 (inst->inst_offset)) {
5236                                                 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5237                                         } else {
5238                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5239                                                 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5240                                         }
5241                                         break;
5242                                 case 2:
5243                                         if (arm_is_imm8 (inst->inst_offset)) {
5244                                                 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5245                                         } else {
5246                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5247                                                 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5248                                         }
5249                                         break;
5250                                 case 8:
5251                                         if (arm_is_imm12 (inst->inst_offset)) {
5252                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5253                                         } else {
5254                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5255                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5256                                         }
5257                                         if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5258                                                 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5259                                         } else {
5260                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5261                                                 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5262                                         }
5263                                         if (arm_is_imm12 (inst->inst_offset + 4)) {
5264                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5265                                         } else {
5266                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5267                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5268                                         }
5269                                         break;
5270                                 default:
5271                                         if (arm_is_imm12 (inst->inst_offset)) {
5272                                                 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5273                                         } else {
5274                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5275                                                 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5276                                         }
5277                                         break;
5278                                 }
5279                         } else if (ainfo->storage == RegTypeFP) {
5280                                 g_assert_not_reached ();
5281                         } else if (ainfo->storage == RegTypeStructByVal) {
5282                                 int doffset = inst->inst_offset;
5283                                 int soffset = 0;
5284                                 int cur_reg;
5285                                 int size = 0;
5286                                 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5287                                 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5288                                         if (arm_is_imm12 (doffset)) {
5289                                                 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5290                                         } else {
5291                                                 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5292                                                 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5293                                         }
5294                                         soffset += sizeof (gpointer);
5295                                         doffset += sizeof (gpointer);
5296                                 }
5297                                 if (ainfo->vtsize) {
5298                                         /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5299                                         //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5300                                         code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5301                                 }
5302                         } else if (ainfo->storage == RegTypeStructByAddr) {
5303                                 g_assert_not_reached ();
5304                                 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5305                                 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5306                         } else
5307                                 g_assert_not_reached ();
5308                 }
5309                 pos++;
5310         }
5311
5312         if (method->save_lmf)
5313                 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5314
5315         if (tracing)
5316                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5317
5318         if (cfg->arch.seq_point_info_var) {
5319                 MonoInst *ins = cfg->arch.seq_point_info_var;
5320
5321                 /* Initialize the variable from a GOT slot */
5322                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5323                 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5324                 ARM_B (code, 0);
5325                 *(gpointer*)code = NULL;
5326                 code += 4;
5327                 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5328
5329                 g_assert (ins->opcode == OP_REGOFFSET);
5330
5331                 if (arm_is_imm12 (ins->inst_offset)) {
5332                         ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5333                 } else {
5334                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5335                         ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5336                 }
5337         }
5338
5339         /* Initialize ss_trigger_page_var */
5340         if (!cfg->soft_breakpoints) {
5341                 MonoInst *info_var = cfg->arch.seq_point_info_var;
5342                 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5343                 int dreg = ARMREG_LR;
5344
5345                 if (info_var) {
5346                         g_assert (info_var->opcode == OP_REGOFFSET);
5347                         g_assert (arm_is_imm12 (info_var->inst_offset));
5348
5349                         ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5350                         /* Load the trigger page addr */
5351                         ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5352                         ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5353                 }
5354         }
5355
5356         if (cfg->arch.seq_point_read_var) {
5357                 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5358                 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5359                 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5360
5361                 g_assert (read_ins->opcode == OP_REGOFFSET);
5362                 g_assert (arm_is_imm12 (read_ins->inst_offset));
5363                 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5364                 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5365                 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5366                 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5367
5368                 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5369                 ARM_B (code, 2);
5370                 *(volatile int **)code = &ss_trigger_var;
5371                 code += 4;
5372                 *(gpointer*)code = single_step_func_wrapper;
5373                 code += 4;
5374                 *(gpointer*)code = breakpoint_func_wrapper;
5375                 code += 4;
5376
5377                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5378                 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5379                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5380                 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5381                 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5382                 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5383         }
5384
5385         cfg->code_len = code - cfg->native_code;
5386         g_assert (cfg->code_len < cfg->code_size);
5387         g_free (cinfo);
5388
5389         return code;
5390 }
5391
5392 void
5393 mono_arch_emit_epilog (MonoCompile *cfg)
5394 {
5395         MonoMethod *method = cfg->method;
5396         int pos, i, rot_amount;
5397         int max_epilog_size = 16 + 20*4;
5398         guint8 *code;
5399         CallInfo *cinfo;
5400
5401         if (cfg->method->save_lmf)
5402                 max_epilog_size += 128;
5403
5404         if (mono_jit_trace_calls != NULL)
5405                 max_epilog_size += 50;
5406
5407         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5408                 max_epilog_size += 50;
5409
5410         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5411                 cfg->code_size *= 2;
5412                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5413                 cfg->stat_code_reallocs++;
5414         }
5415
5416         /*
5417          * Keep in sync with OP_JMP
5418          */
5419         code = cfg->native_code + cfg->code_len;
5420
5421         if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5422                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5423         }
5424         pos = 0;
5425
5426         /* Load returned vtypes into registers if needed */
5427         cinfo = cfg->arch.cinfo;
5428         if (cinfo->ret.storage == RegTypeStructByVal) {
5429                 MonoInst *ins = cfg->ret;
5430
5431                 if (arm_is_imm12 (ins->inst_offset)) {
5432                         ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5433                 } else {
5434                         code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5435                         ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5436                 }
5437         }
5438
5439         if (method->save_lmf) {
5440                 int lmf_offset, reg, sp_adj, regmask;
5441                 /* all but r0-r3, sp and pc */
5442                 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5443                 lmf_offset = pos;
5444
5445                 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5446
5447                 /* This points to r4 inside MonoLMF->iregs */
5448                 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5449                 reg = ARMREG_R4;
5450                 regmask = 0x9ff0; /* restore lr to pc */
5451                 /* Skip caller saved registers not used by the method */
5452                 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5453                         regmask &= ~(1 << reg);
5454                         sp_adj += 4;
5455                         reg ++;
5456                 }
5457                 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5458                 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5459                 /* restore iregs */
5460                 ARM_POP (code, regmask);
5461         } else {
5462                 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5463                         ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5464                 } else {
5465                         code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5466                         ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5467                 }
5468
5469                 if (iphone_abi) {
5470                         /* Restore saved gregs */
5471                         if (cfg->used_int_regs)
5472                                 ARM_POP (code, cfg->used_int_regs);
5473                         /* Restore saved r7, restore LR to PC */
5474                         ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5475                 } else {
5476                         ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5477                 }
5478         }
5479
5480         cfg->code_len = code - cfg->native_code;
5481
5482         g_assert (cfg->code_len < cfg->code_size);
5483
5484 }
5485
5486 /* remove once throw_exception_by_name is eliminated */
5487 static int
5488 exception_id_by_name (const char *name)
5489 {
5490         if (strcmp (name, "IndexOutOfRangeException") == 0)
5491                 return MONO_EXC_INDEX_OUT_OF_RANGE;
5492         if (strcmp (name, "OverflowException") == 0)
5493                 return MONO_EXC_OVERFLOW;
5494         if (strcmp (name, "ArithmeticException") == 0)
5495                 return MONO_EXC_ARITHMETIC;
5496         if (strcmp (name, "DivideByZeroException") == 0)
5497                 return MONO_EXC_DIVIDE_BY_ZERO;
5498         if (strcmp (name, "InvalidCastException") == 0)
5499                 return MONO_EXC_INVALID_CAST;
5500         if (strcmp (name, "NullReferenceException") == 0)
5501                 return MONO_EXC_NULL_REF;
5502         if (strcmp (name, "ArrayTypeMismatchException") == 0)
5503                 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5504         if (strcmp (name, "ArgumentException") == 0)
5505                 return MONO_EXC_ARGUMENT;
5506         g_error ("Unknown intrinsic exception %s\n", name);
5507         return -1;
5508 }
5509
5510 void
5511 mono_arch_emit_exceptions (MonoCompile *cfg)
5512 {
5513         MonoJumpInfo *patch_info;
5514         int i;
5515         guint8 *code;
5516         guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5517         guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5518         int max_epilog_size = 50;
5519
5520         for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5521                 exc_throw_pos [i] = NULL;
5522                 exc_throw_found [i] = 0;
5523         }
5524
5525         /* count the number of exception infos */
5526
5527         /*
5528          * make sure we have enough space for exceptions
5529          */
5530         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5531                 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5532                         i = exception_id_by_name (patch_info->data.target);
5533                         if (!exc_throw_found [i]) {
5534                                 max_epilog_size += 32;
5535                                 exc_throw_found [i] = TRUE;
5536                         }
5537                 }
5538         }
5539
5540         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5541                 cfg->code_size *= 2;
5542                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5543                 cfg->stat_code_reallocs++;
5544         }
5545
5546         code = cfg->native_code + cfg->code_len;
5547
5548         /* add code to raise exceptions */
5549         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5550                 switch (patch_info->type) {
5551                 case MONO_PATCH_INFO_EXC: {
5552                         MonoClass *exc_class;
5553                         unsigned char *ip = patch_info->ip.i + cfg->native_code;
5554
5555                         i = exception_id_by_name (patch_info->data.target);
5556                         if (exc_throw_pos [i]) {
5557                                 arm_patch (ip, exc_throw_pos [i]);
5558                                 patch_info->type = MONO_PATCH_INFO_NONE;
5559                                 break;
5560                         } else {
5561                                 exc_throw_pos [i] = code;
5562                         }
5563                         arm_patch (ip, code);
5564
5565                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5566                         g_assert (exc_class);
5567
5568                         ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5569                         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5570                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5571                         patch_info->data.name = "mono_arch_throw_corlib_exception";
5572                         patch_info->ip.i = code - cfg->native_code;
5573                         ARM_BL (code, 0);
5574                         *(guint32*)(gpointer)code = exc_class->type_token;
5575                         code += 4;
5576                         break;
5577                 }
5578                 default:
5579                         /* do nothing */
5580                         break;
5581                 }
5582         }
5583
5584         cfg->code_len = code - cfg->native_code;
5585
5586         g_assert (cfg->code_len < cfg->code_size);
5587
5588 }
5589
5590 #endif /* #ifndef DISABLE_JIT */
5591
5592 void
5593 mono_arch_finish_init (void)
5594 {
5595         lmf_tls_offset = mono_get_lmf_tls_offset ();
5596         lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5597 }
5598
5599 void
5600 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5601 {
5602 }
5603
5604 MonoInst*
5605 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5606 {
5607         /* FIXME: */
5608         return NULL;
5609 }
5610
5611 gboolean
5612 mono_arch_print_tree (MonoInst *tree, int arity)
5613 {
5614         return 0;
5615 }
5616
5617 MonoInst*
5618 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5619 {
5620         return mono_get_domain_intrinsic (cfg);
5621 }
5622
5623 guint32
5624 mono_arch_get_patch_offset (guint8 *code)
5625 {
5626         /* OP_AOTCONST */
5627         return 8;
5628 }
5629
5630 void
5631 mono_arch_flush_register_windows (void)
5632 {
5633 }
5634
5635 #ifdef MONO_ARCH_HAVE_IMT
5636
5637 #ifndef DISABLE_JIT
5638
5639 void
5640 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5641 {
5642         if (cfg->compile_aot) {
5643                 int method_reg = mono_alloc_ireg (cfg);
5644                 MonoInst *ins;
5645
5646                 call->dynamic_imt_arg = TRUE;
5647
5648                 if (imt_arg) {
5649                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5650                 } else {
5651                         MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5652                         ins->dreg = method_reg;
5653                         ins->inst_p0 = call->method;
5654                         ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5655                         MONO_ADD_INS (cfg->cbb, ins);
5656
5657                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5658                 }
5659         } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5660
5661                 /* Always pass in a register for simplicity */
5662                 call->dynamic_imt_arg = TRUE;
5663
5664                 cfg->uses_rgctx_reg = TRUE;
5665
5666                 if (imt_arg) {
5667                         mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5668                 } else {
5669                         MonoInst *ins;
5670                         int method_reg = mono_alloc_preg (cfg);
5671
5672                         MONO_INST_NEW (cfg, ins, OP_PCONST);
5673                         ins->inst_p0 = call->method;
5674                         ins->dreg = method_reg;
5675                         MONO_ADD_INS (cfg->cbb, ins);
5676
5677                         mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5678                 }
5679         }
5680 }
5681
5682 #endif /* DISABLE_JIT */
5683
5684 MonoMethod*
5685 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5686 {
5687         guint32 *code_ptr = (guint32*)code;
5688         code_ptr -= 2;
5689
5690         if (mono_use_llvm)
5691                 /* Passed in V5 */
5692                 return (MonoMethod*)regs [ARMREG_V5];
5693
5694         /* The IMT value is stored in the code stream right after the LDC instruction. */
5695         if (!IS_LDR_PC (code_ptr [0])) {
5696                 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5697                 g_assert (IS_LDR_PC (code_ptr [0]));
5698         }
5699         if (code_ptr [1] == 0)
5700                 /* This is AOTed code, the IMT method is in V5 */
5701                 return (MonoMethod*)regs [ARMREG_V5];
5702         else
5703                 return (MonoMethod*) code_ptr [1];
5704 }
5705
5706 MonoVTable*
5707 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5708 {
5709         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5710 }
5711
5712 #define ENABLE_WRONG_METHOD_CHECK 0
5713 #define BASE_SIZE (6 * 4)
5714 #define BSEARCH_ENTRY_SIZE (4 * 4)
5715 #define CMP_SIZE (3 * 4)
5716 #define BRANCH_SIZE (1 * 4)
5717 #define CALL_SIZE (2 * 4)
5718 #define WMC_SIZE (5 * 4)
5719 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5720
5721 static arminstr_t *
5722 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5723 {
5724         guint32 delta = DISTANCE (target, code);
5725         delta -= 8;
5726         g_assert (delta >= 0 && delta <= 0xFFF);
5727         *target = *target | delta;
5728         *code = value;
5729         return code + 1;
5730 }
5731
5732 gpointer
5733 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5734         gpointer fail_tramp)
5735 {
5736         int size, i, extra_space = 0;
5737         arminstr_t *code, *start, *vtable_target = NULL;
5738         gboolean large_offsets = FALSE;
5739         guint32 **constant_pool_starts;
5740
5741         size = BASE_SIZE;
5742         constant_pool_starts = g_new0 (guint32*, count);
5743
5744         for (i = 0; i < count; ++i) {
5745                 MonoIMTCheckItem *item = imt_entries [i];
5746                 if (item->is_equals) {
5747                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5748
5749                         if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5750                                 item->chunk_size += 32;
5751                                 large_offsets = TRUE;
5752                         }
5753
5754                         if (item->check_target_idx || fail_case) {
5755                                 if (!item->compare_done || fail_case)
5756                                         item->chunk_size += CMP_SIZE;
5757                                 item->chunk_size += BRANCH_SIZE;
5758                         } else {
5759 #if ENABLE_WRONG_METHOD_CHECK
5760                                 item->chunk_size += WMC_SIZE;
5761 #endif
5762                         }
5763                         if (fail_case) {
5764                                 item->chunk_size += 16;
5765                                 large_offsets = TRUE;
5766                         }
5767                         item->chunk_size += CALL_SIZE;
5768                 } else {
5769                         item->chunk_size += BSEARCH_ENTRY_SIZE;
5770                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5771                 }
5772                 size += item->chunk_size;
5773         }
5774
5775         if (large_offsets)
5776                 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5777
5778         if (fail_tramp)
5779                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5780         else
5781                 code = mono_domain_code_reserve (domain, size);
5782         start = code;
5783
5784 #if DEBUG_IMT
5785         printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5786         for (i = 0; i < count; ++i) {
5787                 MonoIMTCheckItem *item = imt_entries [i];
5788                 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5789         }
5790 #endif
5791
5792         if (large_offsets)
5793                 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5794         else
5795                 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5796         ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5797         vtable_target = code;
5798         ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5799
5800         if (mono_use_llvm) {
5801                 /* LLVM always passes the IMT method in R5 */
5802                 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5803         } else {
5804                 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5805                 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5806                 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5807         }
5808
5809         for (i = 0; i < count; ++i) {
5810                 MonoIMTCheckItem *item = imt_entries [i];
5811                 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5812                 gint32 vtable_offset;
5813
5814                 item->code_target = (guint8*)code;
5815
5816                 if (item->is_equals) {
5817                         gboolean fail_case = !item->check_target_idx && fail_tramp;
5818
5819                         if (item->check_target_idx || fail_case) {
5820                                 if (!item->compare_done || fail_case) {
5821                                         imt_method = code;
5822                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5823                                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5824                                 }
5825                                 item->jmp_code = (guint8*)code;
5826                                 ARM_B_COND (code, ARMCOND_NE, 0);
5827                         } else {
5828                                 /*Enable the commented code to assert on wrong method*/
5829 #if ENABLE_WRONG_METHOD_CHECK
5830                                 imt_method = code;
5831                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5832                                 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5833                                 ARM_B_COND (code, ARMCOND_NE, 1);
5834
5835                                 ARM_DBRK (code);
5836 #endif
5837                         }
5838
5839                         if (item->has_target_code) {
5840                                 target_code_ins = code;
5841                                 /* Load target address */
5842                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5843                                 /* Save it to the fourth slot */
5844                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5845                                 /* Restore registers and branch */
5846                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5847
5848                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5849                         } else {
5850                                 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5851                                 if (!arm_is_imm12 (vtable_offset)) {
5852                                         /*
5853                                          * We need to branch to a computed address but we don't have
5854                                          * a free register to store it, since IP must contain the
5855                                          * vtable address. So we push the two values to the stack, and
5856                                          * load them both using LDM.
5857                                          */
5858                                         /* Compute target address */
5859                                         vtable_offset_ins = code;
5860                                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5861                                         ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5862                                         /* Save it to the fourth slot */
5863                                         ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5864                                         /* Restore registers and branch */
5865                                         ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5866
5867                                         code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5868                                 } else {
5869                                         ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5870                                         if (large_offsets)
5871                                                 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5872                                         ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5873                                 }
5874                         }
5875
5876                         if (fail_case) {
5877                                 arm_patch (item->jmp_code, (guchar*)code);
5878
5879                                 target_code_ins = code;
5880                                 /* Load target address */
5881                                 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5882                                 /* Save it to the fourth slot */
5883                                 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5884                                 /* Restore registers and branch */
5885                                 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5886
5887                                 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5888                                 item->jmp_code = NULL;
5889                         }
5890
5891                         if (imt_method)
5892                                 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5893
5894                         /*must emit after unconditional branch*/
5895                         if (vtable_target) {
5896                                 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5897                                 item->chunk_size += 4;
5898                                 vtable_target = NULL;
5899                         }
5900
5901                         /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5902                         constant_pool_starts [i] = code;
5903                         if (extra_space) {
5904                                 code += extra_space;
5905                                 extra_space = 0;
5906                         }
5907                 } else {
5908                         ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5909                         ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5910
5911                         item->jmp_code = (guint8*)code;
5912                         ARM_B_COND (code, ARMCOND_GE, 0);
5913                         ++extra_space;
5914                 }
5915         }
5916
5917         for (i = 0; i < count; ++i) {
5918                 MonoIMTCheckItem *item = imt_entries [i];
5919                 if (item->jmp_code) {
5920                         if (item->check_target_idx)
5921                                 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5922                 }
5923                 if (i > 0 && item->is_equals) {
5924                         int j;
5925                         arminstr_t *space_start = constant_pool_starts [i];
5926                         for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5927                                 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5928                         }
5929                 }
5930         }
5931
5932 #if DEBUG_IMT
5933         {
5934                 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5935                 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5936                 g_free (buff);
5937         }
5938 #endif
5939
5940         g_free (constant_pool_starts);
5941
5942         mono_arch_flush_icache ((guint8*)start, size);
5943         mono_stats.imt_thunks_size += code - start;
5944
5945         g_assert (DISTANCE (start, code) <= size);
5946         return start;
5947 }
5948
5949 #endif
5950
5951 mgreg_t
5952 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5953 {
5954         return ctx->regs [reg];
5955 }
5956
5957 void
5958 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5959 {
5960         ctx->regs [reg] = val;
5961 }
5962
5963 /*
5964  * mono_arch_get_trampolines:
5965  *
5966  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
5967  * for AOT.
5968  */
5969 GSList *
5970 mono_arch_get_trampolines (gboolean aot)
5971 {
5972         return mono_arm_get_exception_trampolines (aot);
5973 }
5974
5975 /*
5976  * mono_arch_set_breakpoint:
5977  *
5978  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5979  * The location should contain code emitted by OP_SEQ_POINT.
5980  */
5981 void
5982 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5983 {
5984         guint8 *code = ip;
5985         guint32 native_offset = ip - (guint8*)ji->code_start;
5986         MonoDebugOptions *opt = mini_get_debug_options ();
5987
5988         if (opt->soft_breakpoints) {
5989                 g_assert (!ji->from_aot);
5990                 code += 4;
5991                 ARM_BLX_REG (code, ARMREG_LR);
5992                 mono_arch_flush_icache (code - 4, 4);
5993         } else if (ji->from_aot) {
5994                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5995
5996                 g_assert (native_offset % 4 == 0);
5997                 g_assert (info->bp_addrs [native_offset / 4] == 0);
5998                 info->bp_addrs [native_offset / 4] = bp_trigger_page;
5999         } else {
6000                 int dreg = ARMREG_LR;
6001
6002                 /* Read from another trigger page */
6003                 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6004                 ARM_B (code, 0);
6005                 *(int*)code = (int)bp_trigger_page;
6006                 code += 4;
6007                 ARM_LDR_IMM (code, dreg, dreg, 0);
6008
6009                 mono_arch_flush_icache (code - 16, 16);
6010
6011 #if 0
6012                 /* This is currently implemented by emitting an SWI instruction, which
6013                  * qemu/linux seems to convert to a SIGILL.
6014                  */
6015                 *(int*)code = (0xef << 24) | 8;
6016                 code += 4;
6017                 mono_arch_flush_icache (code - 4, 4);
6018 #endif
6019         }
6020 }
6021
6022 /*
6023  * mono_arch_clear_breakpoint:
6024  *
6025  *   Clear the breakpoint at IP.
6026  */
6027 void
6028 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6029 {
6030         MonoDebugOptions *opt = mini_get_debug_options ();
6031         guint8 *code = ip;
6032         int i;
6033
6034         if (opt->soft_breakpoints) {
6035                 g_assert (!ji->from_aot);
6036                 code += 4;
6037                 ARM_NOP (code);
6038                 mono_arch_flush_icache (code - 4, 4);
6039         } else if (ji->from_aot) {
6040                 guint32 native_offset = ip - (guint8*)ji->code_start;
6041                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6042
6043                 g_assert (native_offset % 4 == 0);
6044                 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6045                 info->bp_addrs [native_offset / 4] = 0;
6046         } else {
6047                 for (i = 0; i < 4; ++i)
6048                         ARM_NOP (code);
6049
6050                 mono_arch_flush_icache (ip, code - ip);
6051         }
6052 }
6053
6054 /*
6055  * mono_arch_start_single_stepping:
6056  *
6057  *   Start single stepping.
6058  */
6059 void
6060 mono_arch_start_single_stepping (void)
6061 {
6062         if (ss_trigger_page)
6063                 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6064         else
6065                 ss_trigger_var = 1;
6066 }
6067
6068 /*
6069  * mono_arch_stop_single_stepping:
6070  *
6071  *   Stop single stepping.
6072  */
6073 void
6074 mono_arch_stop_single_stepping (void)
6075 {
6076         if (ss_trigger_page)
6077                 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6078         else
6079                 ss_trigger_var = 0;
6080 }
6081
6082 #if __APPLE__
6083 #define DBG_SIGNAL SIGBUS
6084 #else
6085 #define DBG_SIGNAL SIGSEGV
6086 #endif
6087
6088 /*
6089  * mono_arch_is_single_step_event:
6090  *
6091  *   Return whenever the machine state in SIGCTX corresponds to a single
6092  * step event.
6093  */
6094 gboolean
6095 mono_arch_is_single_step_event (void *info, void *sigctx)
6096 {
6097         siginfo_t *sinfo = info;
6098
6099         if (!ss_trigger_page)
6100                 return FALSE;
6101
6102         /* Sometimes the address is off by 4 */
6103         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6104                 return TRUE;
6105         else
6106                 return FALSE;
6107 }
6108
6109 /*
6110  * mono_arch_is_breakpoint_event:
6111  *
6112  *   Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6113  */
6114 gboolean
6115 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6116 {
6117         siginfo_t *sinfo = info;
6118
6119         if (!ss_trigger_page)
6120                 return FALSE;
6121
6122         if (sinfo->si_signo == DBG_SIGNAL) {
6123                 /* Sometimes the address is off by 4 */
6124                 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6125                         return TRUE;
6126                 else
6127                         return FALSE;
6128         } else {
6129                 return FALSE;
6130         }
6131 }
6132
6133 /*
6134  * mono_arch_skip_breakpoint:
6135  *
6136  *   See mini-amd64.c for docs.
6137  */
6138 void
6139 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6140 {
6141         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6142 }
6143
6144 /*
6145  * mono_arch_skip_single_step:
6146  *
6147  *   See mini-amd64.c for docs.
6148  */
6149 void
6150 mono_arch_skip_single_step (MonoContext *ctx)
6151 {
6152         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6153 }
6154
6155 /*
6156  * mono_arch_get_seq_point_info:
6157  *
6158  *   See mini-amd64.c for docs.
6159  */
6160 gpointer
6161 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6162 {
6163         SeqPointInfo *info;
6164         MonoJitInfo *ji;
6165
6166         // FIXME: Add a free function
6167
6168         mono_domain_lock (domain);
6169         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6170                                                                 code);
6171         mono_domain_unlock (domain);
6172
6173         if (!info) {
6174                 ji = mono_jit_info_table_find (domain, (char*)code);
6175                 g_assert (ji);
6176
6177                 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6178
6179                 info->ss_trigger_page = ss_trigger_page;
6180                 info->bp_trigger_page = bp_trigger_page;
6181
6182                 mono_domain_lock (domain);
6183                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6184                                                          code, info);
6185                 mono_domain_unlock (domain);
6186         }
6187
6188         return info;
6189 }
6190
6191 /*
6192  * mono_arch_set_target:
6193  *
6194  *   Set the target architecture the JIT backend should generate code for, in the form
6195  * of a GNU target triplet. Only used in AOT mode.
6196  */
6197 void
6198 mono_arch_set_target (char *mtriple)
6199 {
6200         /* The GNU target triple format is not very well documented */
6201         if (strstr (mtriple, "armv7")) {
6202                 v6_supported = TRUE;
6203                 v7_supported = TRUE;
6204         }
6205         if (strstr (mtriple, "armv6")) {
6206                 v6_supported = TRUE;
6207         }
6208         if (strstr (mtriple, "darwin")) {
6209                 v5_supported = TRUE;
6210                 thumb_supported = TRUE;
6211                 darwin = TRUE;
6212                 iphone_abi = TRUE;
6213         }
6214         if (strstr (mtriple, "gnueabi"))
6215                 eabi_supported = TRUE;
6216 }